mbed - version_2.0

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TARGET_NUCLEO_F030R8/stm32f0xx_tim.h@86:4f9a848d74c7, 2014-06-25 (annotated)

Committer:: erezi
Date:: Wed Jun 25 06:08:49 2014 +0000
Revision:: 86:4f9a848d74c7
Parent:: 81:7d30d6019079

version_2.0

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User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f0xx_tim.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
emilmont	77:869cf507173a	5	* @version V1.3.0
emilmont	77:869cf507173a	6	* @date 16-January-2014
emilmont	77:869cf507173a	7	* @brief This file contains all the functions prototypes for the TIM
emilmont	77:869cf507173a	8	* firmware library.
emilmont	77:869cf507173a	9	******************************************************************************
emilmont	77:869cf507173a	10	* @attention
emilmont	77:869cf507173a	11	*
bogdanm	81:7d30d6019079	12	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	13	*
bogdanm	81:7d30d6019079	14	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	81:7d30d6019079	15	* are permitted provided that the following conditions are met:
bogdanm	81:7d30d6019079	16	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	81:7d30d6019079	17	* this list of conditions and the following disclaimer.
bogdanm	81:7d30d6019079	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	81:7d30d6019079	19	* this list of conditions and the following disclaimer in the documentation
bogdanm	81:7d30d6019079	20	* and/or other materials provided with the distribution.
bogdanm	81:7d30d6019079	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	81:7d30d6019079	22	* may be used to endorse or promote products derived from this software
bogdanm	81:7d30d6019079	23	* without specific prior written permission.
emilmont	77:869cf507173a	24	*
bogdanm	81:7d30d6019079	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	81:7d30d6019079	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	81:7d30d6019079	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	81:7d30d6019079	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	81:7d30d6019079	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	81:7d30d6019079	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	81:7d30d6019079	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	81:7d30d6019079	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	81:7d30d6019079	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	81:7d30d6019079	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	35	*
emilmont	77:869cf507173a	36	******************************************************************************
emilmont	77:869cf507173a	37	*/
emilmont	77:869cf507173a	38
emilmont	77:869cf507173a	39	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	40	#ifndef __STM32F0XX_TIM_H
emilmont	77:869cf507173a	41	#define __STM32F0XX_TIM_H
emilmont	77:869cf507173a	42
emilmont	77:869cf507173a	43	#ifdef __cplusplus
emilmont	77:869cf507173a	44	extern "C" {
emilmont	77:869cf507173a	45	#endif
emilmont	77:869cf507173a	46
emilmont	77:869cf507173a	47	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	48	#include "stm32f0xx.h"
emilmont	77:869cf507173a	49
emilmont	77:869cf507173a	50	/** @addtogroup STM32F0xx_StdPeriph_Driver
emilmont	77:869cf507173a	51	* @{
emilmont	77:869cf507173a	52	*/
emilmont	77:869cf507173a	53
emilmont	77:869cf507173a	54	/** @addtogroup TIM
emilmont	77:869cf507173a	55	* @{
emilmont	77:869cf507173a	56	*/
emilmont	77:869cf507173a	57
emilmont	77:869cf507173a	58	/* Exported types ------------------------------------------------------------*/
emilmont	77:869cf507173a	59
emilmont	77:869cf507173a	60	/**
emilmont	77:869cf507173a	61	* @brief TIM Time Base Init structure definition
emilmont	77:869cf507173a	62	* @note This sturcture is used with all TIMx.
emilmont	77:869cf507173a	63	*/
emilmont	77:869cf507173a	64
emilmont	77:869cf507173a	65	typedef struct
emilmont	77:869cf507173a	66	{
emilmont	77:869cf507173a	67	uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
emilmont	77:869cf507173a	68	This parameter can be a number between 0x0000 and 0xFFFF */
emilmont	77:869cf507173a	69
emilmont	77:869cf507173a	70	uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
emilmont	77:869cf507173a	71	This parameter can be a value of @ref TIM_Counter_Mode */
emilmont	77:869cf507173a	72
emilmont	77:869cf507173a	73	uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
emilmont	77:869cf507173a	74	Auto-Reload Register at the next update event.
emilmont	77:869cf507173a	75	This parameter must be a number between 0x0000 and 0xFFFF. */
emilmont	77:869cf507173a	76
emilmont	77:869cf507173a	77	uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
emilmont	77:869cf507173a	78	This parameter can be a value of @ref TIM_Clock_Division_CKD */
emilmont	77:869cf507173a	79
emilmont	77:869cf507173a	80	uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
emilmont	77:869cf507173a	81	reaches zero, an update event is generated and counting restarts
emilmont	77:869cf507173a	82	from the RCR value (N).
emilmont	77:869cf507173a	83	This means in PWM mode that (N+1) corresponds to:
emilmont	77:869cf507173a	84	- the number of PWM periods in edge-aligned mode
emilmont	77:869cf507173a	85	- the number of half PWM period in center-aligned mode
emilmont	77:869cf507173a	86	This parameter must be a number between 0x00 and 0xFF.
emilmont	77:869cf507173a	87	@note This parameter is valid only for TIM1. */
emilmont	77:869cf507173a	88	} TIM_TimeBaseInitTypeDef;
emilmont	77:869cf507173a	89
emilmont	77:869cf507173a	90	/**
emilmont	77:869cf507173a	91	* @brief TIM Output Compare Init structure definition
emilmont	77:869cf507173a	92	*/
emilmont	77:869cf507173a	93
emilmont	77:869cf507173a	94	typedef struct
emilmont	77:869cf507173a	95	{
emilmont	77:869cf507173a	96	uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
emilmont	77:869cf507173a	97	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
emilmont	77:869cf507173a	98
emilmont	77:869cf507173a	99	uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
emilmont	77:869cf507173a	100	This parameter can be a value of @ref TIM_Output_Compare_state */
emilmont	77:869cf507173a	101
emilmont	77:869cf507173a	102	uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
emilmont	77:869cf507173a	103	This parameter can be a value of @ref TIM_Output_Compare_N_state
emilmont	77:869cf507173a	104	@note This parameter is valid only for TIM1. */
emilmont	77:869cf507173a	105
emilmont	77:869cf507173a	106	uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
emilmont	77:869cf507173a	107	This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF
emilmont	77:869cf507173a	108	for TIM2) */
emilmont	77:869cf507173a	109
emilmont	77:869cf507173a	110	uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
emilmont	77:869cf507173a	111	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
emilmont	77:869cf507173a	112
emilmont	77:869cf507173a	113	uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
emilmont	77:869cf507173a	114	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
emilmont	77:869cf507173a	115	@note This parameter is valid only for TIM1. */
emilmont	77:869cf507173a	116
emilmont	77:869cf507173a	117	uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
emilmont	77:869cf507173a	118	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
emilmont	77:869cf507173a	119	@note This parameter is valid only for TIM1. */
emilmont	77:869cf507173a	120
emilmont	77:869cf507173a	121	uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
emilmont	77:869cf507173a	122	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
emilmont	77:869cf507173a	123	@note This parameter is valid only for TIM1. */
emilmont	77:869cf507173a	124	} TIM_OCInitTypeDef;
emilmont	77:869cf507173a	125
emilmont	77:869cf507173a	126	/**
emilmont	77:869cf507173a	127	* @brief TIM Input Capture Init structure definition
emilmont	77:869cf507173a	128	*/
emilmont	77:869cf507173a	129
emilmont	77:869cf507173a	130	typedef struct
emilmont	77:869cf507173a	131	{
emilmont	77:869cf507173a	132
emilmont	77:869cf507173a	133	uint16_t TIM_Channel; /*!< Specifies the TIM channel.
emilmont	77:869cf507173a	134	This parameter can be a value of @ref TIM_Channel */
emilmont	77:869cf507173a	135
emilmont	77:869cf507173a	136	uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
emilmont	77:869cf507173a	137	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
emilmont	77:869cf507173a	138
emilmont	77:869cf507173a	139	uint16_t TIM_ICSelection; /*!< Specifies the input.
emilmont	77:869cf507173a	140	This parameter can be a value of @ref TIM_Input_Capture_Selection */
emilmont	77:869cf507173a	141
emilmont	77:869cf507173a	142	uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
emilmont	77:869cf507173a	143	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
emilmont	77:869cf507173a	144
emilmont	77:869cf507173a	145	uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
emilmont	77:869cf507173a	146	This parameter can be a number between 0x0 and 0xF */
emilmont	77:869cf507173a	147	} TIM_ICInitTypeDef;
emilmont	77:869cf507173a	148
emilmont	77:869cf507173a	149	/**
emilmont	77:869cf507173a	150	* @brief TIM_BDTR structure definition
emilmont	77:869cf507173a	151	* @note This sturcture is used only with TIM1.
emilmont	77:869cf507173a	152	*/
emilmont	77:869cf507173a	153
emilmont	77:869cf507173a	154	typedef struct
emilmont	77:869cf507173a	155	{
emilmont	77:869cf507173a	156
emilmont	77:869cf507173a	157	uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
emilmont	77:869cf507173a	158	This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
emilmont	77:869cf507173a	159
emilmont	77:869cf507173a	160	uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
emilmont	77:869cf507173a	161	This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
emilmont	77:869cf507173a	162
emilmont	77:869cf507173a	163	uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
emilmont	77:869cf507173a	164	This parameter can be a value of @ref TIM_Lock_level */
emilmont	77:869cf507173a	165
emilmont	77:869cf507173a	166	uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
emilmont	77:869cf507173a	167	switching-on of the outputs.
emilmont	77:869cf507173a	168	This parameter can be a number between 0x00 and 0xFF */
emilmont	77:869cf507173a	169
emilmont	77:869cf507173a	170	uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
emilmont	77:869cf507173a	171	This parameter can be a value of @ref TIM_Break_Input_enable_disable */
emilmont	77:869cf507173a	172
emilmont	77:869cf507173a	173	uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
emilmont	77:869cf507173a	174	This parameter can be a value of @ref TIM_Break_Polarity */
emilmont	77:869cf507173a	175
emilmont	77:869cf507173a	176	uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
emilmont	77:869cf507173a	177	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
emilmont	77:869cf507173a	178	} TIM_BDTRInitTypeDef;
emilmont	77:869cf507173a	179
emilmont	77:869cf507173a	180	/**
emilmont	77:869cf507173a	181	* @brief TIM Input Capture Init structure definition
emilmont	77:869cf507173a	182	*/
emilmont	77:869cf507173a	183
emilmont	77:869cf507173a	184	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	185
emilmont	77:869cf507173a	186
emilmont	77:869cf507173a	187	/** @defgroup TIM_Exported_constants
emilmont	77:869cf507173a	188	* @{
emilmont	77:869cf507173a	189	*/
emilmont	77:869cf507173a	190
emilmont	77:869cf507173a	191	#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
emilmont	77:869cf507173a	192	((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	193	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	194	((PERIPH) == TIM6) \|\| \
emilmont	77:869cf507173a	195	((PERIPH) == TIM7) \|\| \
emilmont	77:869cf507173a	196	((PERIPH) == TIM14)\|\| \
emilmont	77:869cf507173a	197	((PERIPH) == TIM15)\|\| \
emilmont	77:869cf507173a	198	((PERIPH) == TIM16)\|\| \
emilmont	77:869cf507173a	199	((PERIPH) == TIM17))
emilmont	77:869cf507173a	200
emilmont	77:869cf507173a	201	/* LIST1: TIM 1 */
emilmont	77:869cf507173a	202	#define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1)
emilmont	77:869cf507173a	203
emilmont	77:869cf507173a	204	/* LIST2: TIM 1, 15, 16 and 17 */
emilmont	77:869cf507173a	205	#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
emilmont	77:869cf507173a	206	((PERIPH) == TIM15)\|\| \
emilmont	77:869cf507173a	207	((PERIPH) == TIM16)\|\| \
emilmont	77:869cf507173a	208	((PERIPH) == TIM17))
emilmont	77:869cf507173a	209
emilmont	77:869cf507173a	210	/* LIST3: TIM 1, 2 and 3 */
emilmont	77:869cf507173a	211	#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
emilmont	77:869cf507173a	212	((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	213	((PERIPH) == TIM3))
emilmont	77:869cf507173a	214
emilmont	77:869cf507173a	215	/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */
emilmont	77:869cf507173a	216	#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
emilmont	77:869cf507173a	217	((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	218	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	219	((PERIPH) == TIM14) \|\| \
emilmont	77:869cf507173a	220	((PERIPH) == TIM15)\|\| \
emilmont	77:869cf507173a	221	((PERIPH) == TIM16)\|\| \
emilmont	77:869cf507173a	222	((PERIPH) == TIM17))
emilmont	77:869cf507173a	223
emilmont	77:869cf507173a	224	/* LIST5: TIM 1, 2, 3, 15, 16 and 17 */
emilmont	77:869cf507173a	225	#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
emilmont	77:869cf507173a	226	((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	227	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	228	((PERIPH) == TIM15)\|\| \
emilmont	77:869cf507173a	229	((PERIPH) == TIM16)\|\| \
emilmont	77:869cf507173a	230	((PERIPH) == TIM17))
emilmont	77:869cf507173a	231
emilmont	77:869cf507173a	232	/* LIST6: TIM 1, 2, 3 and 15 */
emilmont	77:869cf507173a	233	#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
emilmont	77:869cf507173a	234	((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	235	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	236	((PERIPH) == TIM15))
emilmont	77:869cf507173a	237
emilmont	77:869cf507173a	238	/* LIST7: TIM 1, 2, 3, 6, 7 and 14 */
emilmont	77:869cf507173a	239	#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
emilmont	77:869cf507173a	240	((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	241	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	242	((PERIPH) == TIM6) \|\| \
emilmont	77:869cf507173a	243	((PERIPH) == TIM7) \|\| \
emilmont	77:869cf507173a	244	((PERIPH) == TIM14))
emilmont	77:869cf507173a	245
emilmont	77:869cf507173a	246	/* LIST8: TIM 1, 2, 3 and 14 */
emilmont	77:869cf507173a	247	#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
emilmont	77:869cf507173a	248	((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	249	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	250	((PERIPH) == TIM14))
emilmont	77:869cf507173a	251
emilmont	77:869cf507173a	252	/* LIST9: TIM 1, 2, 3, 6, 7 and 15 */
emilmont	77:869cf507173a	253	#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
emilmont	77:869cf507173a	254	((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	255	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	256	((PERIPH) == TIM6) \|\| \
emilmont	77:869cf507173a	257	((PERIPH) == TIM7) \|\| \
emilmont	77:869cf507173a	258	((PERIPH) == TIM15))
emilmont	77:869cf507173a	259
emilmont	77:869cf507173a	260	/* LIST10: TIM 1, 2, 3, 6, 7, 15, 16 and 17 */
emilmont	77:869cf507173a	261	#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
emilmont	77:869cf507173a	262	((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	263	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	264	((PERIPH) == TIM6) \|\| \
emilmont	77:869cf507173a	265	((PERIPH) == TIM7) \|\| \
emilmont	77:869cf507173a	266	((PERIPH) == TIM15)\|\| \
emilmont	77:869cf507173a	267	((PERIPH) == TIM16)\|\| \
emilmont	77:869cf507173a	268	((PERIPH) == TIM17))
emilmont	77:869cf507173a	269
emilmont	77:869cf507173a	270	/* LIST1: TIM 11 */
emilmont	77:869cf507173a	271	#define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14)
emilmont	77:869cf507173a	272
emilmont	77:869cf507173a	273
emilmont	77:869cf507173a	274	/**
emilmont	77:869cf507173a	275	* @}
emilmont	77:869cf507173a	276	*/
emilmont	77:869cf507173a	277
emilmont	77:869cf507173a	278	/** @defgroup TIM_Output_Compare_and_PWM_modes
emilmont	77:869cf507173a	279	* @{
emilmont	77:869cf507173a	280	*/
emilmont	77:869cf507173a	281
emilmont	77:869cf507173a	282	#define TIM_OCMode_Timing ((uint16_t)0x0000)
emilmont	77:869cf507173a	283	#define TIM_OCMode_Active ((uint16_t)0x0010)
emilmont	77:869cf507173a	284	#define TIM_OCMode_Inactive ((uint16_t)0x0020)
emilmont	77:869cf507173a	285	#define TIM_OCMode_Toggle ((uint16_t)0x0030)
emilmont	77:869cf507173a	286	#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
emilmont	77:869cf507173a	287	#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
emilmont	77:869cf507173a	288	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) \|\| \
emilmont	77:869cf507173a	289	((MODE) == TIM_OCMode_Active) \|\| \
emilmont	77:869cf507173a	290	((MODE) == TIM_OCMode_Inactive) \|\| \
emilmont	77:869cf507173a	291	((MODE) == TIM_OCMode_Toggle)\|\| \
emilmont	77:869cf507173a	292	((MODE) == TIM_OCMode_PWM1) \|\| \
emilmont	77:869cf507173a	293	((MODE) == TIM_OCMode_PWM2))
emilmont	77:869cf507173a	294	#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) \|\| \
emilmont	77:869cf507173a	295	((MODE) == TIM_OCMode_Active) \|\| \
emilmont	77:869cf507173a	296	((MODE) == TIM_OCMode_Inactive) \|\| \
emilmont	77:869cf507173a	297	((MODE) == TIM_OCMode_Toggle)\|\| \
emilmont	77:869cf507173a	298	((MODE) == TIM_OCMode_PWM1) \|\| \
emilmont	77:869cf507173a	299	((MODE) == TIM_OCMode_PWM2) \|\| \
emilmont	77:869cf507173a	300	((MODE) == TIM_ForcedAction_Active) \|\| \
emilmont	77:869cf507173a	301	((MODE) == TIM_ForcedAction_InActive))
emilmont	77:869cf507173a	302	/**
emilmont	77:869cf507173a	303	* @}
emilmont	77:869cf507173a	304	*/
emilmont	77:869cf507173a	305
emilmont	77:869cf507173a	306	/** @defgroup TIM_One_Pulse_Mode
emilmont	77:869cf507173a	307	* @{
emilmont	77:869cf507173a	308	*/
emilmont	77:869cf507173a	309
emilmont	77:869cf507173a	310	#define TIM_OPMode_Single ((uint16_t)0x0008)
emilmont	77:869cf507173a	311	#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
emilmont	77:869cf507173a	312	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) \|\| \
emilmont	77:869cf507173a	313	((MODE) == TIM_OPMode_Repetitive))
emilmont	77:869cf507173a	314	/**
emilmont	77:869cf507173a	315	* @}
emilmont	77:869cf507173a	316	*/
emilmont	77:869cf507173a	317
emilmont	77:869cf507173a	318	/** @defgroup TIM_Channel
emilmont	77:869cf507173a	319	* @{
emilmont	77:869cf507173a	320	*/
emilmont	77:869cf507173a	321
emilmont	77:869cf507173a	322	#define TIM_Channel_1 ((uint16_t)0x0000)
emilmont	77:869cf507173a	323	#define TIM_Channel_2 ((uint16_t)0x0004)
emilmont	77:869cf507173a	324	#define TIM_Channel_3 ((uint16_t)0x0008)
emilmont	77:869cf507173a	325	#define TIM_Channel_4 ((uint16_t)0x000C)
emilmont	77:869cf507173a	326
emilmont	77:869cf507173a	327	#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
emilmont	77:869cf507173a	328	((CHANNEL) == TIM_Channel_2) \|\| \
emilmont	77:869cf507173a	329	((CHANNEL) == TIM_Channel_3) \|\| \
emilmont	77:869cf507173a	330	((CHANNEL) == TIM_Channel_4))
emilmont	77:869cf507173a	331	#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
emilmont	77:869cf507173a	332	((CHANNEL) == TIM_Channel_2) \|\| \
emilmont	77:869cf507173a	333	((CHANNEL) == TIM_Channel_3))
emilmont	77:869cf507173a	334	#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
emilmont	77:869cf507173a	335	((CHANNEL) == TIM_Channel_2))
emilmont	77:869cf507173a	336
emilmont	77:869cf507173a	337	/**
emilmont	77:869cf507173a	338	* @}
emilmont	77:869cf507173a	339	*/
emilmont	77:869cf507173a	340
emilmont	77:869cf507173a	341	/** @defgroup TIM_Clock_Division_CKD
emilmont	77:869cf507173a	342	* @{
emilmont	77:869cf507173a	343	*/
emilmont	77:869cf507173a	344
emilmont	77:869cf507173a	345	#define TIM_CKD_DIV1 ((uint16_t)0x0000)
emilmont	77:869cf507173a	346	#define TIM_CKD_DIV2 ((uint16_t)0x0100)
emilmont	77:869cf507173a	347	#define TIM_CKD_DIV4 ((uint16_t)0x0200)
emilmont	77:869cf507173a	348	#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) \|\| \
emilmont	77:869cf507173a	349	((DIV) == TIM_CKD_DIV2) \|\| \
emilmont	77:869cf507173a	350	((DIV) == TIM_CKD_DIV4))
emilmont	77:869cf507173a	351	/**
emilmont	77:869cf507173a	352	* @}
emilmont	77:869cf507173a	353	*/
emilmont	77:869cf507173a	354
emilmont	77:869cf507173a	355	/** @defgroup TIM_Counter_Mode
emilmont	77:869cf507173a	356	* @{
emilmont	77:869cf507173a	357	*/
emilmont	77:869cf507173a	358
emilmont	77:869cf507173a	359	#define TIM_CounterMode_Up ((uint16_t)0x0000)
emilmont	77:869cf507173a	360	#define TIM_CounterMode_Down ((uint16_t)0x0010)
emilmont	77:869cf507173a	361	#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
emilmont	77:869cf507173a	362	#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
emilmont	77:869cf507173a	363	#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
emilmont	77:869cf507173a	364	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) \|\| \
emilmont	77:869cf507173a	365	((MODE) == TIM_CounterMode_Down) \|\| \
emilmont	77:869cf507173a	366	((MODE) == TIM_CounterMode_CenterAligned1) \|\| \
emilmont	77:869cf507173a	367	((MODE) == TIM_CounterMode_CenterAligned2) \|\| \
emilmont	77:869cf507173a	368	((MODE) == TIM_CounterMode_CenterAligned3))
emilmont	77:869cf507173a	369	/**
emilmont	77:869cf507173a	370	* @}
emilmont	77:869cf507173a	371	*/
emilmont	77:869cf507173a	372
emilmont	77:869cf507173a	373	/** @defgroup TIM_Output_Compare_Polarity
emilmont	77:869cf507173a	374	* @{
emilmont	77:869cf507173a	375	*/
emilmont	77:869cf507173a	376
emilmont	77:869cf507173a	377	#define TIM_OCPolarity_High ((uint16_t)0x0000)
emilmont	77:869cf507173a	378	#define TIM_OCPolarity_Low ((uint16_t)0x0002)
emilmont	77:869cf507173a	379	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) \|\| \
emilmont	77:869cf507173a	380	((POLARITY) == TIM_OCPolarity_Low))
emilmont	77:869cf507173a	381	/**
emilmont	77:869cf507173a	382	* @}
emilmont	77:869cf507173a	383	*/
emilmont	77:869cf507173a	384
emilmont	77:869cf507173a	385	/** @defgroup TIM_Output_Compare_N_Polarity
emilmont	77:869cf507173a	386	* @{
emilmont	77:869cf507173a	387	*/
emilmont	77:869cf507173a	388
emilmont	77:869cf507173a	389	#define TIM_OCNPolarity_High ((uint16_t)0x0000)
emilmont	77:869cf507173a	390	#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
emilmont	77:869cf507173a	391	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) \|\| \
emilmont	77:869cf507173a	392	((POLARITY) == TIM_OCNPolarity_Low))
emilmont	77:869cf507173a	393	/**
emilmont	77:869cf507173a	394	* @}
emilmont	77:869cf507173a	395	*/
emilmont	77:869cf507173a	396
emilmont	77:869cf507173a	397	/** @defgroup TIM_Output_Compare_state
emilmont	77:869cf507173a	398	* @{
emilmont	77:869cf507173a	399	*/
emilmont	77:869cf507173a	400
emilmont	77:869cf507173a	401	#define TIM_OutputState_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	402	#define TIM_OutputState_Enable ((uint16_t)0x0001)
emilmont	77:869cf507173a	403	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) \|\| \
emilmont	77:869cf507173a	404	((STATE) == TIM_OutputState_Enable))
emilmont	77:869cf507173a	405	/**
emilmont	77:869cf507173a	406	* @}
emilmont	77:869cf507173a	407	*/
emilmont	77:869cf507173a	408
emilmont	77:869cf507173a	409	/** @defgroup TIM_Output_Compare_N_state
emilmont	77:869cf507173a	410	* @{
emilmont	77:869cf507173a	411	*/
emilmont	77:869cf507173a	412
emilmont	77:869cf507173a	413	#define TIM_OutputNState_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	414	#define TIM_OutputNState_Enable ((uint16_t)0x0004)
emilmont	77:869cf507173a	415	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) \|\| \
emilmont	77:869cf507173a	416	((STATE) == TIM_OutputNState_Enable))
emilmont	77:869cf507173a	417	/**
emilmont	77:869cf507173a	418	* @}
emilmont	77:869cf507173a	419	*/
emilmont	77:869cf507173a	420
emilmont	77:869cf507173a	421	/** @defgroup TIM_Capture_Compare_state
emilmont	77:869cf507173a	422	* @{
emilmont	77:869cf507173a	423	*/
emilmont	77:869cf507173a	424
emilmont	77:869cf507173a	425	#define TIM_CCx_Enable ((uint16_t)0x0001)
emilmont	77:869cf507173a	426	#define TIM_CCx_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	427	#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) \|\| \
emilmont	77:869cf507173a	428	((CCX) == TIM_CCx_Disable))
emilmont	77:869cf507173a	429	/**
emilmont	77:869cf507173a	430	* @}
emilmont	77:869cf507173a	431	*/
emilmont	77:869cf507173a	432
emilmont	77:869cf507173a	433	/** @defgroup TIM_Capture_Compare_N_state
emilmont	77:869cf507173a	434	* @{
emilmont	77:869cf507173a	435	*/
emilmont	77:869cf507173a	436
emilmont	77:869cf507173a	437	#define TIM_CCxN_Enable ((uint16_t)0x0004)
emilmont	77:869cf507173a	438	#define TIM_CCxN_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	439	#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) \|\| \
emilmont	77:869cf507173a	440	((CCXN) == TIM_CCxN_Disable))
emilmont	77:869cf507173a	441	/**
emilmont	77:869cf507173a	442	* @}
emilmont	77:869cf507173a	443	*/
emilmont	77:869cf507173a	444
emilmont	77:869cf507173a	445	/** @defgroup TIM_Break_Input_enable_disable
emilmont	77:869cf507173a	446	* @{
emilmont	77:869cf507173a	447	*/
emilmont	77:869cf507173a	448
emilmont	77:869cf507173a	449	#define TIM_Break_Enable ((uint16_t)0x1000)
emilmont	77:869cf507173a	450	#define TIM_Break_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	451	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) \|\| \
emilmont	77:869cf507173a	452	((STATE) == TIM_Break_Disable))
emilmont	77:869cf507173a	453	/**
emilmont	77:869cf507173a	454	* @}
emilmont	77:869cf507173a	455	*/
emilmont	77:869cf507173a	456
emilmont	77:869cf507173a	457	/** @defgroup TIM_Break_Polarity
emilmont	77:869cf507173a	458	* @{
emilmont	77:869cf507173a	459	*/
emilmont	77:869cf507173a	460
emilmont	77:869cf507173a	461	#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
emilmont	77:869cf507173a	462	#define TIM_BreakPolarity_High ((uint16_t)0x2000)
emilmont	77:869cf507173a	463	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) \|\| \
emilmont	77:869cf507173a	464	((POLARITY) == TIM_BreakPolarity_High))
emilmont	77:869cf507173a	465	/**
emilmont	77:869cf507173a	466	* @}
emilmont	77:869cf507173a	467	*/
emilmont	77:869cf507173a	468
emilmont	77:869cf507173a	469	/** @defgroup TIM_AOE_Bit_Set_Reset
emilmont	77:869cf507173a	470	* @{
emilmont	77:869cf507173a	471	*/
emilmont	77:869cf507173a	472
emilmont	77:869cf507173a	473	#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
emilmont	77:869cf507173a	474	#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	475	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) \|\| \
emilmont	77:869cf507173a	476	((STATE) == TIM_AutomaticOutput_Disable))
emilmont	77:869cf507173a	477	/**
emilmont	77:869cf507173a	478	* @}
emilmont	77:869cf507173a	479	*/
emilmont	77:869cf507173a	480
emilmont	77:869cf507173a	481	/** @defgroup TIM_Lock_level
emilmont	77:869cf507173a	482	* @{
emilmont	77:869cf507173a	483	*/
emilmont	77:869cf507173a	484
emilmont	77:869cf507173a	485	#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
emilmont	77:869cf507173a	486	#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
emilmont	77:869cf507173a	487	#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
emilmont	77:869cf507173a	488	#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
emilmont	77:869cf507173a	489	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) \|\| \
emilmont	77:869cf507173a	490	((LEVEL) == TIM_LOCKLevel_1) \|\| \
emilmont	77:869cf507173a	491	((LEVEL) == TIM_LOCKLevel_2) \|\| \
emilmont	77:869cf507173a	492	((LEVEL) == TIM_LOCKLevel_3))
emilmont	77:869cf507173a	493	/**
emilmont	77:869cf507173a	494	* @}
emilmont	77:869cf507173a	495	*/
emilmont	77:869cf507173a	496
emilmont	77:869cf507173a	497	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
emilmont	77:869cf507173a	498	* @{
emilmont	77:869cf507173a	499	*/
emilmont	77:869cf507173a	500
emilmont	77:869cf507173a	501	#define TIM_OSSIState_Enable ((uint16_t)0x0400)
emilmont	77:869cf507173a	502	#define TIM_OSSIState_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	503	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) \|\| \
emilmont	77:869cf507173a	504	((STATE) == TIM_OSSIState_Disable))
emilmont	77:869cf507173a	505	/**
emilmont	77:869cf507173a	506	* @}
emilmont	77:869cf507173a	507	*/
emilmont	77:869cf507173a	508
emilmont	77:869cf507173a	509	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
emilmont	77:869cf507173a	510	* @{
emilmont	77:869cf507173a	511	*/
emilmont	77:869cf507173a	512
emilmont	77:869cf507173a	513	#define TIM_OSSRState_Enable ((uint16_t)0x0800)
emilmont	77:869cf507173a	514	#define TIM_OSSRState_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	515	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) \|\| \
emilmont	77:869cf507173a	516	((STATE) == TIM_OSSRState_Disable))
emilmont	77:869cf507173a	517	/**
emilmont	77:869cf507173a	518	* @}
emilmont	77:869cf507173a	519	*/
emilmont	77:869cf507173a	520
emilmont	77:869cf507173a	521	/** @defgroup TIM_Output_Compare_Idle_State
emilmont	77:869cf507173a	522	* @{
emilmont	77:869cf507173a	523	*/
emilmont	77:869cf507173a	524
emilmont	77:869cf507173a	525	#define TIM_OCIdleState_Set ((uint16_t)0x0100)
emilmont	77:869cf507173a	526	#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
emilmont	77:869cf507173a	527	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) \|\| \
emilmont	77:869cf507173a	528	((STATE) == TIM_OCIdleState_Reset))
emilmont	77:869cf507173a	529	/**
emilmont	77:869cf507173a	530	* @}
emilmont	77:869cf507173a	531	*/
emilmont	77:869cf507173a	532
emilmont	77:869cf507173a	533	/** @defgroup TIM_Output_Compare_N_Idle_State
emilmont	77:869cf507173a	534	* @{
emilmont	77:869cf507173a	535	*/
emilmont	77:869cf507173a	536
emilmont	77:869cf507173a	537	#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
emilmont	77:869cf507173a	538	#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
emilmont	77:869cf507173a	539	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) \|\| \
emilmont	77:869cf507173a	540	((STATE) == TIM_OCNIdleState_Reset))
emilmont	77:869cf507173a	541	/**
emilmont	77:869cf507173a	542	* @}
emilmont	77:869cf507173a	543	*/
emilmont	77:869cf507173a	544
emilmont	77:869cf507173a	545	/** @defgroup TIM_Input_Capture_Polarity
emilmont	77:869cf507173a	546	* @{
emilmont	77:869cf507173a	547	*/
emilmont	77:869cf507173a	548
emilmont	77:869cf507173a	549	#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
emilmont	77:869cf507173a	550	#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
emilmont	77:869cf507173a	551	#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
emilmont	77:869cf507173a	552	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) \|\| \
emilmont	77:869cf507173a	553	((POLARITY) == TIM_ICPolarity_Falling)\|\| \
emilmont	77:869cf507173a	554	((POLARITY) == TIM_ICPolarity_BothEdge))
emilmont	77:869cf507173a	555	/**
emilmont	77:869cf507173a	556	* @}
emilmont	77:869cf507173a	557	*/
emilmont	77:869cf507173a	558
emilmont	77:869cf507173a	559	/** @defgroup TIM_Input_Capture_Selection
emilmont	77:869cf507173a	560	* @{
emilmont	77:869cf507173a	561	*/
emilmont	77:869cf507173a	562
emilmont	77:869cf507173a	563	#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
emilmont	77:869cf507173a	564	connected to IC1, IC2, IC3 or IC4, respectively */
emilmont	77:869cf507173a	565	#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
emilmont	77:869cf507173a	566	connected to IC2, IC1, IC4 or IC3, respectively. */
emilmont	77:869cf507173a	567	#define TIM_ICSelection_TRC ((uint16_t)0x0003) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. /
emilmont	77:869cf507173a	568	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) \|\| \
emilmont	77:869cf507173a	569	((SELECTION) == TIM_ICSelection_IndirectTI) \|\| \
emilmont	77:869cf507173a	570	((SELECTION) == TIM_ICSelection_TRC))
emilmont	77:869cf507173a	571	/**
emilmont	77:869cf507173a	572	* @}
emilmont	77:869cf507173a	573	*/
emilmont	77:869cf507173a	574
emilmont	77:869cf507173a	575	/** @defgroup TIM_Input_Capture_Prescaler
emilmont	77:869cf507173a	576	* @{
emilmont	77:869cf507173a	577	*/
emilmont	77:869cf507173a	578
emilmont	77:869cf507173a	579	#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /!< Capture performed each time an edge is detected on the capture input. /
emilmont	77:869cf507173a	580	#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /!< Capture performed once every 2 events. /
emilmont	77:869cf507173a	581	#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /!< Capture performed once every 4 events. /
emilmont	77:869cf507173a	582	#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /!< Capture performed once every 8 events. /
emilmont	77:869cf507173a	583	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
emilmont	77:869cf507173a	584	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
emilmont	77:869cf507173a	585	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
emilmont	77:869cf507173a	586	((PRESCALER) == TIM_ICPSC_DIV8))
emilmont	77:869cf507173a	587	/**
emilmont	77:869cf507173a	588	* @}
emilmont	77:869cf507173a	589	*/
emilmont	77:869cf507173a	590
emilmont	77:869cf507173a	591	/** @defgroup TIM_interrupt_sources
emilmont	77:869cf507173a	592	* @{
emilmont	77:869cf507173a	593	*/
emilmont	77:869cf507173a	594
emilmont	77:869cf507173a	595	#define TIM_IT_Update ((uint16_t)0x0001)
emilmont	77:869cf507173a	596	#define TIM_IT_CC1 ((uint16_t)0x0002)
emilmont	77:869cf507173a	597	#define TIM_IT_CC2 ((uint16_t)0x0004)
emilmont	77:869cf507173a	598	#define TIM_IT_CC3 ((uint16_t)0x0008)
emilmont	77:869cf507173a	599	#define TIM_IT_CC4 ((uint16_t)0x0010)
emilmont	77:869cf507173a	600	#define TIM_IT_COM ((uint16_t)0x0020)
emilmont	77:869cf507173a	601	#define TIM_IT_Trigger ((uint16_t)0x0040)
emilmont	77:869cf507173a	602	#define TIM_IT_Break ((uint16_t)0x0080)
emilmont	77:869cf507173a	603	#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
emilmont	77:869cf507173a	604
emilmont	77:869cf507173a	605	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) \|\| \
emilmont	77:869cf507173a	606	((IT) == TIM_IT_CC1) \|\| \
emilmont	77:869cf507173a	607	((IT) == TIM_IT_CC2) \|\| \
emilmont	77:869cf507173a	608	((IT) == TIM_IT_CC3) \|\| \
emilmont	77:869cf507173a	609	((IT) == TIM_IT_CC4) \|\| \
emilmont	77:869cf507173a	610	((IT) == TIM_IT_COM) \|\| \
emilmont	77:869cf507173a	611	((IT) == TIM_IT_Trigger) \|\| \
emilmont	77:869cf507173a	612	((IT) == TIM_IT_Break))
emilmont	77:869cf507173a	613	/**
emilmont	77:869cf507173a	614	* @}
emilmont	77:869cf507173a	615	*/
emilmont	77:869cf507173a	616
emilmont	77:869cf507173a	617	/** @defgroup TIM_DMA_Base_address
emilmont	77:869cf507173a	618	* @{
emilmont	77:869cf507173a	619	*/
emilmont	77:869cf507173a	620
emilmont	77:869cf507173a	621	#define TIM_DMABase_CR1 ((uint16_t)0x0000)
emilmont	77:869cf507173a	622	#define TIM_DMABase_CR2 ((uint16_t)0x0001)
emilmont	77:869cf507173a	623	#define TIM_DMABase_SMCR ((uint16_t)0x0002)
emilmont	77:869cf507173a	624	#define TIM_DMABase_DIER ((uint16_t)0x0003)
emilmont	77:869cf507173a	625	#define TIM_DMABase_SR ((uint16_t)0x0004)
emilmont	77:869cf507173a	626	#define TIM_DMABase_EGR ((uint16_t)0x0005)
emilmont	77:869cf507173a	627	#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
emilmont	77:869cf507173a	628	#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
emilmont	77:869cf507173a	629	#define TIM_DMABase_CCER ((uint16_t)0x0008)
emilmont	77:869cf507173a	630	#define TIM_DMABase_CNT ((uint16_t)0x0009)
emilmont	77:869cf507173a	631	#define TIM_DMABase_PSC ((uint16_t)0x000A)
emilmont	77:869cf507173a	632	#define TIM_DMABase_ARR ((uint16_t)0x000B)
emilmont	77:869cf507173a	633	#define TIM_DMABase_RCR ((uint16_t)0x000C)
emilmont	77:869cf507173a	634	#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
emilmont	77:869cf507173a	635	#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
emilmont	77:869cf507173a	636	#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
emilmont	77:869cf507173a	637	#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
emilmont	77:869cf507173a	638	#define TIM_DMABase_BDTR ((uint16_t)0x0011)
emilmont	77:869cf507173a	639	#define TIM_DMABase_DCR ((uint16_t)0x0012)
emilmont	77:869cf507173a	640	#define TIM_DMABase_OR ((uint16_t)0x0013)
emilmont	77:869cf507173a	641	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
emilmont	77:869cf507173a	642	((BASE) == TIM_DMABase_CR2) \|\| \
emilmont	77:869cf507173a	643	((BASE) == TIM_DMABase_SMCR) \|\| \
emilmont	77:869cf507173a	644	((BASE) == TIM_DMABase_DIER) \|\| \
emilmont	77:869cf507173a	645	((BASE) == TIM_DMABase_SR) \|\| \
emilmont	77:869cf507173a	646	((BASE) == TIM_DMABase_EGR) \|\| \
emilmont	77:869cf507173a	647	((BASE) == TIM_DMABase_CCMR1) \|\| \
emilmont	77:869cf507173a	648	((BASE) == TIM_DMABase_CCMR2) \|\| \
emilmont	77:869cf507173a	649	((BASE) == TIM_DMABase_CCER) \|\| \
emilmont	77:869cf507173a	650	((BASE) == TIM_DMABase_CNT) \|\| \
emilmont	77:869cf507173a	651	((BASE) == TIM_DMABase_PSC) \|\| \
emilmont	77:869cf507173a	652	((BASE) == TIM_DMABase_ARR) \|\| \
emilmont	77:869cf507173a	653	((BASE) == TIM_DMABase_RCR) \|\| \
emilmont	77:869cf507173a	654	((BASE) == TIM_DMABase_CCR1) \|\| \
emilmont	77:869cf507173a	655	((BASE) == TIM_DMABase_CCR2) \|\| \
emilmont	77:869cf507173a	656	((BASE) == TIM_DMABase_CCR3) \|\| \
emilmont	77:869cf507173a	657	((BASE) == TIM_DMABase_CCR4) \|\| \
emilmont	77:869cf507173a	658	((BASE) == TIM_DMABase_BDTR) \|\| \
emilmont	77:869cf507173a	659	((BASE) == TIM_DMABase_DCR) \|\| \
emilmont	77:869cf507173a	660	((BASE) == TIM_DMABase_OR))
emilmont	77:869cf507173a	661	/**
emilmont	77:869cf507173a	662	* @}
emilmont	77:869cf507173a	663	*/
emilmont	77:869cf507173a	664
emilmont	77:869cf507173a	665
emilmont	77:869cf507173a	666	/** @defgroup TIM_DMA_Burst_Length
emilmont	77:869cf507173a	667	* @{
emilmont	77:869cf507173a	668	*/
emilmont	77:869cf507173a	669
emilmont	77:869cf507173a	670	#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
emilmont	77:869cf507173a	671	#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
emilmont	77:869cf507173a	672	#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
emilmont	77:869cf507173a	673	#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
emilmont	77:869cf507173a	674	#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
emilmont	77:869cf507173a	675	#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
emilmont	77:869cf507173a	676	#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
emilmont	77:869cf507173a	677	#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
emilmont	77:869cf507173a	678	#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
emilmont	77:869cf507173a	679	#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
emilmont	77:869cf507173a	680	#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
emilmont	77:869cf507173a	681	#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
emilmont	77:869cf507173a	682	#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
emilmont	77:869cf507173a	683	#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
emilmont	77:869cf507173a	684	#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
emilmont	77:869cf507173a	685	#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
emilmont	77:869cf507173a	686	#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
emilmont	77:869cf507173a	687	#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
emilmont	77:869cf507173a	688	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
emilmont	77:869cf507173a	689	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
emilmont	77:869cf507173a	690	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
emilmont	77:869cf507173a	691	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
emilmont	77:869cf507173a	692	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
emilmont	77:869cf507173a	693	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
emilmont	77:869cf507173a	694	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
emilmont	77:869cf507173a	695	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
emilmont	77:869cf507173a	696	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
emilmont	77:869cf507173a	697	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
emilmont	77:869cf507173a	698	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
emilmont	77:869cf507173a	699	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
emilmont	77:869cf507173a	700	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
emilmont	77:869cf507173a	701	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
emilmont	77:869cf507173a	702	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
emilmont	77:869cf507173a	703	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
emilmont	77:869cf507173a	704	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
emilmont	77:869cf507173a	705	((LENGTH) == TIM_DMABurstLength_18Transfers))
emilmont	77:869cf507173a	706	/**
emilmont	77:869cf507173a	707	* @}
emilmont	77:869cf507173a	708	*/
emilmont	77:869cf507173a	709
emilmont	77:869cf507173a	710	/** @defgroup TIM_DMA_sources
emilmont	77:869cf507173a	711	* @{
emilmont	77:869cf507173a	712	*/
emilmont	77:869cf507173a	713
emilmont	77:869cf507173a	714	#define TIM_DMA_Update ((uint16_t)0x0100)
emilmont	77:869cf507173a	715	#define TIM_DMA_CC1 ((uint16_t)0x0200)
emilmont	77:869cf507173a	716	#define TIM_DMA_CC2 ((uint16_t)0x0400)
emilmont	77:869cf507173a	717	#define TIM_DMA_CC3 ((uint16_t)0x0800)
emilmont	77:869cf507173a	718	#define TIM_DMA_CC4 ((uint16_t)0x1000)
emilmont	77:869cf507173a	719	#define TIM_DMA_COM ((uint16_t)0x2000)
emilmont	77:869cf507173a	720	#define TIM_DMA_Trigger ((uint16_t)0x4000)
emilmont	77:869cf507173a	721	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
emilmont	77:869cf507173a	722
emilmont	77:869cf507173a	723	/**
emilmont	77:869cf507173a	724	* @}
emilmont	77:869cf507173a	725	*/
emilmont	77:869cf507173a	726
emilmont	77:869cf507173a	727	/** @defgroup TIM_External_Trigger_Prescaler
emilmont	77:869cf507173a	728	* @{
emilmont	77:869cf507173a	729	*/
emilmont	77:869cf507173a	730
emilmont	77:869cf507173a	731	#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
emilmont	77:869cf507173a	732	#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
emilmont	77:869cf507173a	733	#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
emilmont	77:869cf507173a	734	#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
emilmont	77:869cf507173a	735	#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) \|\| \
emilmont	77:869cf507173a	736	((PRESCALER) == TIM_ExtTRGPSC_DIV2) \|\| \
emilmont	77:869cf507173a	737	((PRESCALER) == TIM_ExtTRGPSC_DIV4) \|\| \
emilmont	77:869cf507173a	738	((PRESCALER) == TIM_ExtTRGPSC_DIV8))
emilmont	77:869cf507173a	739	/**
emilmont	77:869cf507173a	740	* @}
emilmont	77:869cf507173a	741	*/
emilmont	77:869cf507173a	742
emilmont	77:869cf507173a	743	/** @defgroup TIM_Internal_Trigger_Selection
emilmont	77:869cf507173a	744	* @{
emilmont	77:869cf507173a	745	*/
emilmont	77:869cf507173a	746
emilmont	77:869cf507173a	747	#define TIM_TS_ITR0 ((uint16_t)0x0000)
emilmont	77:869cf507173a	748	#define TIM_TS_ITR1 ((uint16_t)0x0010)
emilmont	77:869cf507173a	749	#define TIM_TS_ITR2 ((uint16_t)0x0020)
emilmont	77:869cf507173a	750	#define TIM_TS_ITR3 ((uint16_t)0x0030)
emilmont	77:869cf507173a	751	#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
emilmont	77:869cf507173a	752	#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
emilmont	77:869cf507173a	753	#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
emilmont	77:869cf507173a	754	#define TIM_TS_ETRF ((uint16_t)0x0070)
emilmont	77:869cf507173a	755	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
emilmont	77:869cf507173a	756	((SELECTION) == TIM_TS_ITR1) \|\| \
emilmont	77:869cf507173a	757	((SELECTION) == TIM_TS_ITR2) \|\| \
emilmont	77:869cf507173a	758	((SELECTION) == TIM_TS_ITR3) \|\| \
emilmont	77:869cf507173a	759	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
emilmont	77:869cf507173a	760	((SELECTION) == TIM_TS_TI1FP1) \|\| \
emilmont	77:869cf507173a	761	((SELECTION) == TIM_TS_TI2FP2) \|\| \
emilmont	77:869cf507173a	762	((SELECTION) == TIM_TS_ETRF))
emilmont	77:869cf507173a	763	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
emilmont	77:869cf507173a	764	((SELECTION) == TIM_TS_ITR1) \|\| \
emilmont	77:869cf507173a	765	((SELECTION) == TIM_TS_ITR2) \|\| \
emilmont	77:869cf507173a	766	((SELECTION) == TIM_TS_ITR3))
emilmont	77:869cf507173a	767	/**
emilmont	77:869cf507173a	768	* @}
emilmont	77:869cf507173a	769	*/
emilmont	77:869cf507173a	770
emilmont	77:869cf507173a	771	/** @defgroup TIM_TIx_External_Clock_Source
emilmont	77:869cf507173a	772	* @{
emilmont	77:869cf507173a	773	*/
emilmont	77:869cf507173a	774
emilmont	77:869cf507173a	775	#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
emilmont	77:869cf507173a	776	#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
emilmont	77:869cf507173a	777	#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
emilmont	77:869cf507173a	778
emilmont	77:869cf507173a	779	/**
emilmont	77:869cf507173a	780	* @}
emilmont	77:869cf507173a	781	*/
emilmont	77:869cf507173a	782
emilmont	77:869cf507173a	783	/** @defgroup TIM_External_Trigger_Polarity
emilmont	77:869cf507173a	784	* @{
emilmont	77:869cf507173a	785	*/
emilmont	77:869cf507173a	786	#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
emilmont	77:869cf507173a	787	#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
emilmont	77:869cf507173a	788	#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) \|\| \
emilmont	77:869cf507173a	789	((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
emilmont	77:869cf507173a	790	/**
emilmont	77:869cf507173a	791	* @}
emilmont	77:869cf507173a	792	*/
emilmont	77:869cf507173a	793
emilmont	77:869cf507173a	794	/** @defgroup TIM_Prescaler_Reload_Mode
emilmont	77:869cf507173a	795	* @{
emilmont	77:869cf507173a	796	*/
emilmont	77:869cf507173a	797
emilmont	77:869cf507173a	798	#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
emilmont	77:869cf507173a	799	#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
emilmont	77:869cf507173a	800	#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) \|\| \
emilmont	77:869cf507173a	801	((RELOAD) == TIM_PSCReloadMode_Immediate))
emilmont	77:869cf507173a	802	/**
emilmont	77:869cf507173a	803	* @}
emilmont	77:869cf507173a	804	*/
emilmont	77:869cf507173a	805
emilmont	77:869cf507173a	806	/** @defgroup TIM_Forced_Action
emilmont	77:869cf507173a	807	* @{
emilmont	77:869cf507173a	808	*/
emilmont	77:869cf507173a	809
emilmont	77:869cf507173a	810	#define TIM_ForcedAction_Active ((uint16_t)0x0050)
emilmont	77:869cf507173a	811	#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
emilmont	77:869cf507173a	812	#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) \|\| \
emilmont	77:869cf507173a	813	((ACTION) == TIM_ForcedAction_InActive))
emilmont	77:869cf507173a	814	/**
emilmont	77:869cf507173a	815	* @}
emilmont	77:869cf507173a	816	*/
emilmont	77:869cf507173a	817
emilmont	77:869cf507173a	818	/** @defgroup TIM_Encoder_Mode
emilmont	77:869cf507173a	819	* @{
emilmont	77:869cf507173a	820	*/
emilmont	77:869cf507173a	821
emilmont	77:869cf507173a	822	#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
emilmont	77:869cf507173a	823	#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
emilmont	77:869cf507173a	824	#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
emilmont	77:869cf507173a	825	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) \|\| \
emilmont	77:869cf507173a	826	((MODE) == TIM_EncoderMode_TI2) \|\| \
emilmont	77:869cf507173a	827	((MODE) == TIM_EncoderMode_TI12))
emilmont	77:869cf507173a	828	/**
emilmont	77:869cf507173a	829	* @}
emilmont	77:869cf507173a	830	*/
emilmont	77:869cf507173a	831
emilmont	77:869cf507173a	832
emilmont	77:869cf507173a	833	/** @defgroup TIM_Event_Source
emilmont	77:869cf507173a	834	* @{
emilmont	77:869cf507173a	835	*/
emilmont	77:869cf507173a	836
emilmont	77:869cf507173a	837	#define TIM_EventSource_Update ((uint16_t)0x0001)
emilmont	77:869cf507173a	838	#define TIM_EventSource_CC1 ((uint16_t)0x0002)
emilmont	77:869cf507173a	839	#define TIM_EventSource_CC2 ((uint16_t)0x0004)
emilmont	77:869cf507173a	840	#define TIM_EventSource_CC3 ((uint16_t)0x0008)
emilmont	77:869cf507173a	841	#define TIM_EventSource_CC4 ((uint16_t)0x0010)
emilmont	77:869cf507173a	842	#define TIM_EventSource_COM ((uint16_t)0x0020)
emilmont	77:869cf507173a	843	#define TIM_EventSource_Trigger ((uint16_t)0x0040)
emilmont	77:869cf507173a	844	#define TIM_EventSource_Break ((uint16_t)0x0080)
emilmont	77:869cf507173a	845	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
emilmont	77:869cf507173a	846
emilmont	77:869cf507173a	847	/**
emilmont	77:869cf507173a	848	* @}
emilmont	77:869cf507173a	849	*/
emilmont	77:869cf507173a	850
emilmont	77:869cf507173a	851	/** @defgroup TIM_Update_Source
emilmont	77:869cf507173a	852	* @{
emilmont	77:869cf507173a	853	*/
emilmont	77:869cf507173a	854
emilmont	77:869cf507173a	855	#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
emilmont	77:869cf507173a	856	or the setting of UG bit, or an update generation
emilmont	77:869cf507173a	857	through the slave mode controller. */
emilmont	77:869cf507173a	858	#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /!< Source of update is counter overflow/underflow. /
emilmont	77:869cf507173a	859	#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) \|\| \
emilmont	77:869cf507173a	860	((SOURCE) == TIM_UpdateSource_Regular))
emilmont	77:869cf507173a	861	/**
emilmont	77:869cf507173a	862	* @}
emilmont	77:869cf507173a	863	*/
emilmont	77:869cf507173a	864
emilmont	77:869cf507173a	865	/** @defgroup TIM_Output_Compare_Preload_State
emilmont	77:869cf507173a	866	* @{
emilmont	77:869cf507173a	867	*/
emilmont	77:869cf507173a	868
emilmont	77:869cf507173a	869	#define TIM_OCPreload_Enable ((uint16_t)0x0008)
emilmont	77:869cf507173a	870	#define TIM_OCPreload_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	871	#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) \|\| \
emilmont	77:869cf507173a	872	((STATE) == TIM_OCPreload_Disable))
emilmont	77:869cf507173a	873	/**
emilmont	77:869cf507173a	874	* @}
emilmont	77:869cf507173a	875	*/
emilmont	77:869cf507173a	876
emilmont	77:869cf507173a	877	/** @defgroup TIM_Output_Compare_Fast_State
emilmont	77:869cf507173a	878	* @{
emilmont	77:869cf507173a	879	*/
emilmont	77:869cf507173a	880
emilmont	77:869cf507173a	881	#define TIM_OCFast_Enable ((uint16_t)0x0004)
emilmont	77:869cf507173a	882	#define TIM_OCFast_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	883	#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) \|\| \
emilmont	77:869cf507173a	884	((STATE) == TIM_OCFast_Disable))
emilmont	77:869cf507173a	885
emilmont	77:869cf507173a	886	/**
emilmont	77:869cf507173a	887	* @}
emilmont	77:869cf507173a	888	*/
emilmont	77:869cf507173a	889
emilmont	77:869cf507173a	890	/** @defgroup TIM_Output_Compare_Clear_State
emilmont	77:869cf507173a	891	* @{
emilmont	77:869cf507173a	892	*/
emilmont	77:869cf507173a	893
emilmont	77:869cf507173a	894	#define TIM_OCClear_Enable ((uint16_t)0x0080)
emilmont	77:869cf507173a	895	#define TIM_OCClear_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	896	#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) \|\| \
emilmont	77:869cf507173a	897	((STATE) == TIM_OCClear_Disable))
emilmont	77:869cf507173a	898	/**
emilmont	77:869cf507173a	899	* @}
emilmont	77:869cf507173a	900	*/
emilmont	77:869cf507173a	901
emilmont	77:869cf507173a	902	/** @defgroup TIM_Trigger_Output_Source
emilmont	77:869cf507173a	903	* @{
emilmont	77:869cf507173a	904	*/
emilmont	77:869cf507173a	905
emilmont	77:869cf507173a	906	#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
emilmont	77:869cf507173a	907	#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
emilmont	77:869cf507173a	908	#define TIM_TRGOSource_Update ((uint16_t)0x0020)
emilmont	77:869cf507173a	909	#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
emilmont	77:869cf507173a	910	#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
emilmont	77:869cf507173a	911	#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
emilmont	77:869cf507173a	912	#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
emilmont	77:869cf507173a	913	#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
emilmont	77:869cf507173a	914	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) \|\| \
emilmont	77:869cf507173a	915	((SOURCE) == TIM_TRGOSource_Enable) \|\| \
emilmont	77:869cf507173a	916	((SOURCE) == TIM_TRGOSource_Update) \|\| \
emilmont	77:869cf507173a	917	((SOURCE) == TIM_TRGOSource_OC1) \|\| \
emilmont	77:869cf507173a	918	((SOURCE) == TIM_TRGOSource_OC1Ref) \|\| \
emilmont	77:869cf507173a	919	((SOURCE) == TIM_TRGOSource_OC2Ref) \|\| \
emilmont	77:869cf507173a	920	((SOURCE) == TIM_TRGOSource_OC3Ref) \|\| \
emilmont	77:869cf507173a	921	((SOURCE) == TIM_TRGOSource_OC4Ref))
emilmont	77:869cf507173a	922	/**
emilmont	77:869cf507173a	923	* @}
emilmont	77:869cf507173a	924	*/
emilmont	77:869cf507173a	925
emilmont	77:869cf507173a	926	/** @defgroup TIM_Slave_Mode
emilmont	77:869cf507173a	927	* @{
emilmont	77:869cf507173a	928	*/
emilmont	77:869cf507173a	929
emilmont	77:869cf507173a	930	#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
emilmont	77:869cf507173a	931	#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
emilmont	77:869cf507173a	932	#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
emilmont	77:869cf507173a	933	#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
emilmont	77:869cf507173a	934	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) \|\| \
emilmont	77:869cf507173a	935	((MODE) == TIM_SlaveMode_Gated) \|\| \
emilmont	77:869cf507173a	936	((MODE) == TIM_SlaveMode_Trigger) \|\| \
emilmont	77:869cf507173a	937	((MODE) == TIM_SlaveMode_External1))
emilmont	77:869cf507173a	938	/**
emilmont	77:869cf507173a	939	* @}
emilmont	77:869cf507173a	940	*/
emilmont	77:869cf507173a	941
emilmont	77:869cf507173a	942	/** @defgroup TIM_Master_Slave_Mode
emilmont	77:869cf507173a	943	* @{
emilmont	77:869cf507173a	944	*/
emilmont	77:869cf507173a	945
emilmont	77:869cf507173a	946	#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
emilmont	77:869cf507173a	947	#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	948	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) \|\| \
emilmont	77:869cf507173a	949	((STATE) == TIM_MasterSlaveMode_Disable))
emilmont	77:869cf507173a	950	/**
emilmont	77:869cf507173a	951	* @}
emilmont	77:869cf507173a	952	*/
emilmont	77:869cf507173a	953
emilmont	77:869cf507173a	954	/** @defgroup TIM_Flags
emilmont	77:869cf507173a	955	* @{
emilmont	77:869cf507173a	956	*/
emilmont	77:869cf507173a	957
emilmont	77:869cf507173a	958	#define TIM_FLAG_Update ((uint16_t)0x0001)
emilmont	77:869cf507173a	959	#define TIM_FLAG_CC1 ((uint16_t)0x0002)
emilmont	77:869cf507173a	960	#define TIM_FLAG_CC2 ((uint16_t)0x0004)
emilmont	77:869cf507173a	961	#define TIM_FLAG_CC3 ((uint16_t)0x0008)
emilmont	77:869cf507173a	962	#define TIM_FLAG_CC4 ((uint16_t)0x0010)
emilmont	77:869cf507173a	963	#define TIM_FLAG_COM ((uint16_t)0x0020)
emilmont	77:869cf507173a	964	#define TIM_FLAG_Trigger ((uint16_t)0x0040)
emilmont	77:869cf507173a	965	#define TIM_FLAG_Break ((uint16_t)0x0080)
emilmont	77:869cf507173a	966	#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
emilmont	77:869cf507173a	967	#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
emilmont	77:869cf507173a	968	#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
emilmont	77:869cf507173a	969	#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
emilmont	77:869cf507173a	970	#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) \|\| \
emilmont	77:869cf507173a	971	((FLAG) == TIM_FLAG_CC1) \|\| \
emilmont	77:869cf507173a	972	((FLAG) == TIM_FLAG_CC2) \|\| \
emilmont	77:869cf507173a	973	((FLAG) == TIM_FLAG_CC3) \|\| \
emilmont	77:869cf507173a	974	((FLAG) == TIM_FLAG_CC4) \|\| \
emilmont	77:869cf507173a	975	((FLAG) == TIM_FLAG_COM) \|\| \
emilmont	77:869cf507173a	976	((FLAG) == TIM_FLAG_Trigger) \|\| \
emilmont	77:869cf507173a	977	((FLAG) == TIM_FLAG_Break) \|\| \
emilmont	77:869cf507173a	978	((FLAG) == TIM_FLAG_CC1OF) \|\| \
emilmont	77:869cf507173a	979	((FLAG) == TIM_FLAG_CC2OF) \|\| \
emilmont	77:869cf507173a	980	((FLAG) == TIM_FLAG_CC3OF) \|\| \
emilmont	77:869cf507173a	981	((FLAG) == TIM_FLAG_CC4OF))
emilmont	77:869cf507173a	982
emilmont	77:869cf507173a	983
emilmont	77:869cf507173a	984	#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
emilmont	77:869cf507173a	985	/**
emilmont	77:869cf507173a	986	* @}
emilmont	77:869cf507173a	987	*/
emilmont	77:869cf507173a	988
emilmont	77:869cf507173a	989
emilmont	77:869cf507173a	990	/** @defgroup TIM_Input_Capture_Filer_Value
emilmont	77:869cf507173a	991	* @{
emilmont	77:869cf507173a	992	*/
emilmont	77:869cf507173a	993
emilmont	77:869cf507173a	994	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
emilmont	77:869cf507173a	995	/**
emilmont	77:869cf507173a	996	* @}
emilmont	77:869cf507173a	997	*/
emilmont	77:869cf507173a	998
emilmont	77:869cf507173a	999	/** @defgroup TIM_External_Trigger_Filter
emilmont	77:869cf507173a	1000	* @{
emilmont	77:869cf507173a	1001	*/
emilmont	77:869cf507173a	1002
emilmont	77:869cf507173a	1003	#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
emilmont	77:869cf507173a	1004	/**
emilmont	77:869cf507173a	1005	* @}
emilmont	77:869cf507173a	1006	*/
emilmont	77:869cf507173a	1007
emilmont	77:869cf507173a	1008	/** @defgroup TIM_OCReferenceClear
emilmont	77:869cf507173a	1009	* @{
emilmont	77:869cf507173a	1010	*/
emilmont	77:869cf507173a	1011	#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
emilmont	77:869cf507173a	1012	#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
emilmont	77:869cf507173a	1013	#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) \|\| \
emilmont	77:869cf507173a	1014	((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
emilmont	77:869cf507173a	1015
emilmont	77:869cf507173a	1016	/**
emilmont	77:869cf507173a	1017	* @}
emilmont	77:869cf507173a	1018	*/
emilmont	77:869cf507173a	1019	/** @defgroup TIM_Remap
emilmont	77:869cf507173a	1020	* @{
emilmont	77:869cf507173a	1021	*/
emilmont	77:869cf507173a	1022	#define TIM14_GPIO ((uint16_t)0x0000)
emilmont	77:869cf507173a	1023	#define TIM14_RTC_CLK ((uint16_t)0x0001)
emilmont	77:869cf507173a	1024	#define TIM14_HSEDiv32 ((uint16_t)0x0002)
emilmont	77:869cf507173a	1025	#define TIM14_MCO ((uint16_t)0x0003)
emilmont	77:869cf507173a	1026
emilmont	77:869cf507173a	1027	#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)\|\| \
emilmont	77:869cf507173a	1028	((TIM_REMAP) == TIM14_RTC_CLK) \|\| \
emilmont	77:869cf507173a	1029	((TIM_REMAP) == TIM14_HSEDiv32) \|\| \
emilmont	77:869cf507173a	1030	((TIM_REMAP) == TIM14_MCO))
emilmont	77:869cf507173a	1031	/**
emilmont	77:869cf507173a	1032	* @}
emilmont	77:869cf507173a	1033	*/
emilmont	77:869cf507173a	1034
emilmont	77:869cf507173a	1035	/** @defgroup TIM_Legacy
emilmont	77:869cf507173a	1036	* @{
emilmont	77:869cf507173a	1037	*/
emilmont	77:869cf507173a	1038
emilmont	77:869cf507173a	1039	#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
emilmont	77:869cf507173a	1040	#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
emilmont	77:869cf507173a	1041	#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
emilmont	77:869cf507173a	1042	#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
emilmont	77:869cf507173a	1043	#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
emilmont	77:869cf507173a	1044	#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
emilmont	77:869cf507173a	1045	#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
emilmont	77:869cf507173a	1046	#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
emilmont	77:869cf507173a	1047	#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
emilmont	77:869cf507173a	1048	#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
emilmont	77:869cf507173a	1049	#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
emilmont	77:869cf507173a	1050	#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
emilmont	77:869cf507173a	1051	#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
emilmont	77:869cf507173a	1052	#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
emilmont	77:869cf507173a	1053	#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
emilmont	77:869cf507173a	1054	#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
emilmont	77:869cf507173a	1055	#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
emilmont	77:869cf507173a	1056	#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
emilmont	77:869cf507173a	1057	/**
emilmont	77:869cf507173a	1058	* @}
emilmont	77:869cf507173a	1059	*/
emilmont	77:869cf507173a	1060
emilmont	77:869cf507173a	1061	/**
emilmont	77:869cf507173a	1062	* @}
emilmont	77:869cf507173a	1063	*/
emilmont	77:869cf507173a	1064
emilmont	77:869cf507173a	1065	/* Exported macro ------------------------------------------------------------*/
emilmont	77:869cf507173a	1066	/* Exported functions ------------------------------------------------------- */
emilmont	77:869cf507173a	1067
emilmont	77:869cf507173a	1068	/* TimeBase management ********************************************************/
emilmont	77:869cf507173a	1069	void TIM_DeInit(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	1070	void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
emilmont	77:869cf507173a	1071	void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
emilmont	77:869cf507173a	1072	void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
emilmont	77:869cf507173a	1073	void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
emilmont	77:869cf507173a	1074	void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
emilmont	77:869cf507173a	1075	void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
emilmont	77:869cf507173a	1076	uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	1077	uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	1078	void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	1079	void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
emilmont	77:869cf507173a	1080	void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	1081	void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
emilmont	77:869cf507173a	1082	void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
emilmont	77:869cf507173a	1083	void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	1084
emilmont	77:869cf507173a	1085	/* Advanced-control timers (TIM1) specific features*******************/
emilmont	77:869cf507173a	1086	void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
emilmont	77:869cf507173a	1087	void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
emilmont	77:869cf507173a	1088	void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	1089
emilmont	77:869cf507173a	1090	/* Output Compare management **************************************************/
emilmont	77:869cf507173a	1091	void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
emilmont	77:869cf507173a	1092	void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
emilmont	77:869cf507173a	1093	void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
emilmont	77:869cf507173a	1094	void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
emilmont	77:869cf507173a	1095	void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
emilmont	77:869cf507173a	1096	void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
emilmont	77:869cf507173a	1097	void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
emilmont	77:869cf507173a	1098	void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
emilmont	77:869cf507173a	1099	void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
emilmont	77:869cf507173a	1100	void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
emilmont	77:869cf507173a	1101	void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
emilmont	77:869cf507173a	1102	void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
emilmont	77:869cf507173a	1103	void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
emilmont	77:869cf507173a	1104	void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
emilmont	77:869cf507173a	1105	void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	1106	void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
emilmont	77:869cf507173a	1107	void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
emilmont	77:869cf507173a	1108	void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
emilmont	77:869cf507173a	1109	void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
emilmont	77:869cf507173a	1110	void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
emilmont	77:869cf507173a	1111	void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
emilmont	77:869cf507173a	1112	void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
emilmont	77:869cf507173a	1113	void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
emilmont	77:869cf507173a	1114	void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
emilmont	77:869cf507173a	1115	void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
emilmont	77:869cf507173a	1116	void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
emilmont	77:869cf507173a	1117	void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
emilmont	77:869cf507173a	1118	void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
emilmont	77:869cf507173a	1119	void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
emilmont	77:869cf507173a	1120	void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
emilmont	77:869cf507173a	1121	void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
emilmont	77:869cf507173a	1122	void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
emilmont	77:869cf507173a	1123	void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
emilmont	77:869cf507173a	1124	void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
emilmont	77:869cf507173a	1125	void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
emilmont	77:869cf507173a	1126	void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
emilmont	77:869cf507173a	1127	void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
emilmont	77:869cf507173a	1128	void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	1129
emilmont	77:869cf507173a	1130	/* Input Capture management ***************************************************/
emilmont	77:869cf507173a	1131	void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
emilmont	77:869cf507173a	1132	void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
emilmont	77:869cf507173a	1133	void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
emilmont	77:869cf507173a	1134	uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	1135	uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	1136	uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	1137	uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	1138	void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
emilmont	77:869cf507173a	1139	void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
emilmont	77:869cf507173a	1140	void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
emilmont	77:869cf507173a	1141	void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
emilmont	77:869cf507173a	1142
emilmont	77:869cf507173a	1143	/* Interrupts, DMA and flags management ***************************************/
emilmont	77:869cf507173a	1144	void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
emilmont	77:869cf507173a	1145	void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
emilmont	77:869cf507173a	1146	FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
emilmont	77:869cf507173a	1147	void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
emilmont	77:869cf507173a	1148	ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
emilmont	77:869cf507173a	1149	void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
emilmont	77:869cf507173a	1150	void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
emilmont	77:869cf507173a	1151	void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
emilmont	77:869cf507173a	1152	void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	1153
emilmont	77:869cf507173a	1154	/* Clocks management **********************************************************/
emilmont	77:869cf507173a	1155	void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	1156	void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
emilmont	77:869cf507173a	1157	void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
emilmont	77:869cf507173a	1158	uint16_t TIM_ICPolarity, uint16_t ICFilter);
emilmont	77:869cf507173a	1159	void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
emilmont	77:869cf507173a	1160	uint16_t ExtTRGFilter);
emilmont	77:869cf507173a	1161	void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
emilmont	77:869cf507173a	1162	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
emilmont	77:869cf507173a	1163
emilmont	77:869cf507173a	1164
emilmont	77:869cf507173a	1165	/* Synchronization management *************************************************/
emilmont	77:869cf507173a	1166	void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
emilmont	77:869cf507173a	1167	void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
emilmont	77:869cf507173a	1168	void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
emilmont	77:869cf507173a	1169	void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
emilmont	77:869cf507173a	1170	void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
emilmont	77:869cf507173a	1171	uint16_t ExtTRGFilter);
emilmont	77:869cf507173a	1172
emilmont	77:869cf507173a	1173	/* Specific interface management **********************************************/
emilmont	77:869cf507173a	1174	void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
emilmont	77:869cf507173a	1175	uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
emilmont	77:869cf507173a	1176	void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	1177
emilmont	77:869cf507173a	1178	/* Specific remapping management **********************************************/
emilmont	77:869cf507173a	1179	void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
emilmont	77:869cf507173a	1180
emilmont	77:869cf507173a	1181
emilmont	77:869cf507173a	1182	#ifdef __cplusplus
emilmont	77:869cf507173a	1183	}
emilmont	77:869cf507173a	1184	#endif
emilmont	77:869cf507173a	1185
emilmont	77:869cf507173a	1186	#endif /__STM32F0XX_TIM_H /
emilmont	77:869cf507173a	1187
emilmont	77:869cf507173a	1188	/**
emilmont	77:869cf507173a	1189	* @}
emilmont	77:869cf507173a	1190	*/
emilmont	77:869cf507173a	1191
emilmont	77:869cf507173a	1192	/**
emilmont	77:869cf507173a	1193	* @}
emilmont	77:869cf507173a	1194	*/
emilmont	77:869cf507173a	1195
emilmont	77:869cf507173a	1196	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	25 Jun 2014
Imports:	10
Forks:	0
Commits:	87
Dependents:	1
Dependencies:	0
Followers:	2

TARGET_NUCLEO_F030R8/stm32f0xx_tim.h@86:4f9a848d74c7, 2014-06-25 (annotated)

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