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TARGET_NUCLEO_F030R8/stm32f0xx_dma.h@86:4f9a848d74c7, 2014-06-25 (annotated)
- Committer:
- erezi
- Date:
- Wed Jun 25 06:08:49 2014 +0000
- Revision:
- 86:4f9a848d74c7
- Parent:
- 81:7d30d6019079
version_2.0
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 77:869cf507173a | 1 | /** |
| emilmont | 77:869cf507173a | 2 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 3 | * @file stm32f0xx_dma.h |
| emilmont | 77:869cf507173a | 4 | * @author MCD Application Team |
| emilmont | 77:869cf507173a | 5 | * @version V1.3.0 |
| emilmont | 77:869cf507173a | 6 | * @date 16-January-2014 |
| emilmont | 77:869cf507173a | 7 | * @brief This file contains all the functions prototypes for the DMA firmware |
| emilmont | 77:869cf507173a | 8 | * library. |
| emilmont | 77:869cf507173a | 9 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 10 | * @attention |
| emilmont | 77:869cf507173a | 11 | * |
| bogdanm | 81:7d30d6019079 | 12 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| emilmont | 77:869cf507173a | 13 | * |
| bogdanm | 81:7d30d6019079 | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 81:7d30d6019079 | 15 | * are permitted provided that the following conditions are met: |
| bogdanm | 81:7d30d6019079 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 81:7d30d6019079 | 17 | * this list of conditions and the following disclaimer. |
| bogdanm | 81:7d30d6019079 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 81:7d30d6019079 | 19 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 81:7d30d6019079 | 20 | * and/or other materials provided with the distribution. |
| bogdanm | 81:7d30d6019079 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 81:7d30d6019079 | 22 | * may be used to endorse or promote products derived from this software |
| bogdanm | 81:7d30d6019079 | 23 | * without specific prior written permission. |
| emilmont | 77:869cf507173a | 24 | * |
| bogdanm | 81:7d30d6019079 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 81:7d30d6019079 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 81:7d30d6019079 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 81:7d30d6019079 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 81:7d30d6019079 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 81:7d30d6019079 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 81:7d30d6019079 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 81:7d30d6019079 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 81:7d30d6019079 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 81:7d30d6019079 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| emilmont | 77:869cf507173a | 35 | * |
| emilmont | 77:869cf507173a | 36 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 37 | */ |
| emilmont | 77:869cf507173a | 38 | |
| emilmont | 77:869cf507173a | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| emilmont | 77:869cf507173a | 40 | #ifndef __STM32F0XX_DMA_H |
| emilmont | 77:869cf507173a | 41 | #define __STM32F0XX_DMA_H |
| emilmont | 77:869cf507173a | 42 | |
| emilmont | 77:869cf507173a | 43 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 44 | extern "C" { |
| emilmont | 77:869cf507173a | 45 | #endif |
| emilmont | 77:869cf507173a | 46 | |
| emilmont | 77:869cf507173a | 47 | /* Includes ------------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 48 | #include "stm32f0xx.h" |
| emilmont | 77:869cf507173a | 49 | |
| emilmont | 77:869cf507173a | 50 | /** @addtogroup STM32F0xx_StdPeriph_Driver |
| emilmont | 77:869cf507173a | 51 | * @{ |
| emilmont | 77:869cf507173a | 52 | */ |
| emilmont | 77:869cf507173a | 53 | |
| emilmont | 77:869cf507173a | 54 | /** @addtogroup DMA |
| emilmont | 77:869cf507173a | 55 | * @{ |
| emilmont | 77:869cf507173a | 56 | */ |
| emilmont | 77:869cf507173a | 57 | /* Exported types ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 58 | |
| emilmont | 77:869cf507173a | 59 | /** |
| emilmont | 77:869cf507173a | 60 | * @brief DMA Init structures definition |
| emilmont | 77:869cf507173a | 61 | */ |
| emilmont | 77:869cf507173a | 62 | typedef struct |
| emilmont | 77:869cf507173a | 63 | { |
| emilmont | 77:869cf507173a | 64 | uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ |
| emilmont | 77:869cf507173a | 65 | |
| emilmont | 77:869cf507173a | 66 | uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ |
| emilmont | 77:869cf507173a | 67 | |
| emilmont | 77:869cf507173a | 68 | uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. |
| emilmont | 77:869cf507173a | 69 | This parameter can be a value of @ref DMA_data_transfer_direction */ |
| emilmont | 77:869cf507173a | 70 | |
| emilmont | 77:869cf507173a | 71 | uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. |
| emilmont | 77:869cf507173a | 72 | The data unit is equal to the configuration set in DMA_PeripheralDataSize |
| emilmont | 77:869cf507173a | 73 | or DMA_MemoryDataSize members depending in the transfer direction */ |
| emilmont | 77:869cf507173a | 74 | |
| emilmont | 77:869cf507173a | 75 | uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. |
| emilmont | 77:869cf507173a | 76 | This parameter can be a value of @ref DMA_peripheral_incremented_mode */ |
| emilmont | 77:869cf507173a | 77 | |
| emilmont | 77:869cf507173a | 78 | uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. |
| emilmont | 77:869cf507173a | 79 | This parameter can be a value of @ref DMA_memory_incremented_mode */ |
| emilmont | 77:869cf507173a | 80 | |
| emilmont | 77:869cf507173a | 81 | uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. |
| emilmont | 77:869cf507173a | 82 | This parameter can be a value of @ref DMA_peripheral_data_size */ |
| emilmont | 77:869cf507173a | 83 | |
| emilmont | 77:869cf507173a | 84 | uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. |
| emilmont | 77:869cf507173a | 85 | This parameter can be a value of @ref DMA_memory_data_size */ |
| emilmont | 77:869cf507173a | 86 | |
| emilmont | 77:869cf507173a | 87 | uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. |
| emilmont | 77:869cf507173a | 88 | This parameter can be a value of @ref DMA_circular_normal_mode |
| emilmont | 77:869cf507173a | 89 | @note: The circular buffer mode cannot be used if the memory-to-memory |
| emilmont | 77:869cf507173a | 90 | data transfer is configured on the selected Channel */ |
| emilmont | 77:869cf507173a | 91 | |
| emilmont | 77:869cf507173a | 92 | uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. |
| emilmont | 77:869cf507173a | 93 | This parameter can be a value of @ref DMA_priority_level */ |
| emilmont | 77:869cf507173a | 94 | |
| emilmont | 77:869cf507173a | 95 | uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. |
| emilmont | 77:869cf507173a | 96 | This parameter can be a value of @ref DMA_memory_to_memory */ |
| emilmont | 77:869cf507173a | 97 | }DMA_InitTypeDef; |
| emilmont | 77:869cf507173a | 98 | |
| emilmont | 77:869cf507173a | 99 | /* Exported constants --------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 100 | |
| emilmont | 77:869cf507173a | 101 | /** @defgroup DMA_Exported_Constants |
| emilmont | 77:869cf507173a | 102 | * @{ |
| emilmont | 77:869cf507173a | 103 | */ |
| emilmont | 77:869cf507173a | 104 | |
| emilmont | 77:869cf507173a | 105 | #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ |
| emilmont | 77:869cf507173a | 106 | ((PERIPH) == DMA1_Channel2) || \ |
| emilmont | 77:869cf507173a | 107 | ((PERIPH) == DMA1_Channel3) || \ |
| emilmont | 77:869cf507173a | 108 | ((PERIPH) == DMA1_Channel4) || \ |
| emilmont | 77:869cf507173a | 109 | ((PERIPH) == DMA1_Channel5) || \ |
| emilmont | 77:869cf507173a | 110 | ((PERIPH) == DMA1_Channel6) || \ |
| emilmont | 77:869cf507173a | 111 | ((PERIPH) == DMA1_Channel7)) |
| emilmont | 77:869cf507173a | 112 | |
| emilmont | 77:869cf507173a | 113 | /** @defgroup DMA_data_transfer_direction |
| emilmont | 77:869cf507173a | 114 | * @{ |
| emilmont | 77:869cf507173a | 115 | */ |
| emilmont | 77:869cf507173a | 116 | |
| emilmont | 77:869cf507173a | 117 | #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 118 | #define DMA_DIR_PeripheralDST DMA_CCR_DIR |
| emilmont | 77:869cf507173a | 119 | |
| emilmont | 77:869cf507173a | 120 | #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \ |
| emilmont | 77:869cf507173a | 121 | ((DIR) == DMA_DIR_PeripheralDST)) |
| emilmont | 77:869cf507173a | 122 | /** |
| emilmont | 77:869cf507173a | 123 | * @} |
| emilmont | 77:869cf507173a | 124 | */ |
| emilmont | 77:869cf507173a | 125 | |
| emilmont | 77:869cf507173a | 126 | /** @defgroup DMA_peripheral_incremented_mode |
| emilmont | 77:869cf507173a | 127 | * @{ |
| emilmont | 77:869cf507173a | 128 | */ |
| emilmont | 77:869cf507173a | 129 | |
| emilmont | 77:869cf507173a | 130 | #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 131 | #define DMA_PeripheralInc_Enable DMA_CCR_PINC |
| emilmont | 77:869cf507173a | 132 | |
| emilmont | 77:869cf507173a | 133 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \ |
| emilmont | 77:869cf507173a | 134 | ((STATE) == DMA_PeripheralInc_Enable)) |
| emilmont | 77:869cf507173a | 135 | /** |
| emilmont | 77:869cf507173a | 136 | * @} |
| emilmont | 77:869cf507173a | 137 | */ |
| emilmont | 77:869cf507173a | 138 | |
| emilmont | 77:869cf507173a | 139 | /** @defgroup DMA_memory_incremented_mode |
| emilmont | 77:869cf507173a | 140 | * @{ |
| emilmont | 77:869cf507173a | 141 | */ |
| emilmont | 77:869cf507173a | 142 | |
| emilmont | 77:869cf507173a | 143 | #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 144 | #define DMA_MemoryInc_Enable DMA_CCR_MINC |
| emilmont | 77:869cf507173a | 145 | |
| emilmont | 77:869cf507173a | 146 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \ |
| emilmont | 77:869cf507173a | 147 | ((STATE) == DMA_MemoryInc_Enable)) |
| emilmont | 77:869cf507173a | 148 | /** |
| emilmont | 77:869cf507173a | 149 | * @} |
| emilmont | 77:869cf507173a | 150 | */ |
| emilmont | 77:869cf507173a | 151 | |
| emilmont | 77:869cf507173a | 152 | /** @defgroup DMA_peripheral_data_size |
| emilmont | 77:869cf507173a | 153 | * @{ |
| emilmont | 77:869cf507173a | 154 | */ |
| emilmont | 77:869cf507173a | 155 | |
| emilmont | 77:869cf507173a | 156 | #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 157 | #define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0 |
| emilmont | 77:869cf507173a | 158 | #define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1 |
| emilmont | 77:869cf507173a | 159 | |
| emilmont | 77:869cf507173a | 160 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ |
| emilmont | 77:869cf507173a | 161 | ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ |
| emilmont | 77:869cf507173a | 162 | ((SIZE) == DMA_PeripheralDataSize_Word)) |
| emilmont | 77:869cf507173a | 163 | /** |
| emilmont | 77:869cf507173a | 164 | * @} |
| emilmont | 77:869cf507173a | 165 | */ |
| emilmont | 77:869cf507173a | 166 | |
| emilmont | 77:869cf507173a | 167 | /** @defgroup DMA_memory_data_size |
| emilmont | 77:869cf507173a | 168 | * @{ |
| emilmont | 77:869cf507173a | 169 | */ |
| emilmont | 77:869cf507173a | 170 | |
| emilmont | 77:869cf507173a | 171 | #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 172 | #define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0 |
| emilmont | 77:869cf507173a | 173 | #define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1 |
| emilmont | 77:869cf507173a | 174 | |
| emilmont | 77:869cf507173a | 175 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ |
| emilmont | 77:869cf507173a | 176 | ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ |
| emilmont | 77:869cf507173a | 177 | ((SIZE) == DMA_MemoryDataSize_Word)) |
| emilmont | 77:869cf507173a | 178 | /** |
| emilmont | 77:869cf507173a | 179 | * @} |
| emilmont | 77:869cf507173a | 180 | */ |
| emilmont | 77:869cf507173a | 181 | |
| emilmont | 77:869cf507173a | 182 | /** @defgroup DMA_circular_normal_mode |
| emilmont | 77:869cf507173a | 183 | * @{ |
| emilmont | 77:869cf507173a | 184 | */ |
| emilmont | 77:869cf507173a | 185 | |
| emilmont | 77:869cf507173a | 186 | #define DMA_Mode_Normal ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 187 | #define DMA_Mode_Circular DMA_CCR_CIRC |
| emilmont | 77:869cf507173a | 188 | |
| emilmont | 77:869cf507173a | 189 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular)) |
| emilmont | 77:869cf507173a | 190 | /** |
| emilmont | 77:869cf507173a | 191 | * @} |
| emilmont | 77:869cf507173a | 192 | */ |
| emilmont | 77:869cf507173a | 193 | |
| emilmont | 77:869cf507173a | 194 | /** @defgroup DMA_priority_level |
| emilmont | 77:869cf507173a | 195 | * @{ |
| emilmont | 77:869cf507173a | 196 | */ |
| emilmont | 77:869cf507173a | 197 | |
| emilmont | 77:869cf507173a | 198 | #define DMA_Priority_VeryHigh DMA_CCR_PL |
| emilmont | 77:869cf507173a | 199 | #define DMA_Priority_High DMA_CCR_PL_1 |
| emilmont | 77:869cf507173a | 200 | #define DMA_Priority_Medium DMA_CCR_PL_0 |
| emilmont | 77:869cf507173a | 201 | #define DMA_Priority_Low ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 202 | |
| emilmont | 77:869cf507173a | 203 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ |
| emilmont | 77:869cf507173a | 204 | ((PRIORITY) == DMA_Priority_High) || \ |
| emilmont | 77:869cf507173a | 205 | ((PRIORITY) == DMA_Priority_Medium) || \ |
| emilmont | 77:869cf507173a | 206 | ((PRIORITY) == DMA_Priority_Low)) |
| emilmont | 77:869cf507173a | 207 | /** |
| emilmont | 77:869cf507173a | 208 | * @} |
| emilmont | 77:869cf507173a | 209 | */ |
| emilmont | 77:869cf507173a | 210 | |
| emilmont | 77:869cf507173a | 211 | /** @defgroup DMA_memory_to_memory |
| emilmont | 77:869cf507173a | 212 | * @{ |
| emilmont | 77:869cf507173a | 213 | */ |
| emilmont | 77:869cf507173a | 214 | |
| emilmont | 77:869cf507173a | 215 | #define DMA_M2M_Disable ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 216 | #define DMA_M2M_Enable DMA_CCR_MEM2MEM |
| emilmont | 77:869cf507173a | 217 | |
| emilmont | 77:869cf507173a | 218 | #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable)) |
| emilmont | 77:869cf507173a | 219 | |
| emilmont | 77:869cf507173a | 220 | /** |
| emilmont | 77:869cf507173a | 221 | * @} |
| emilmont | 77:869cf507173a | 222 | */ |
| emilmont | 77:869cf507173a | 223 | |
| emilmont | 77:869cf507173a | 224 | /** @defgroup DMA_interrupts_definition |
| emilmont | 77:869cf507173a | 225 | * @{ |
| emilmont | 77:869cf507173a | 226 | */ |
| emilmont | 77:869cf507173a | 227 | |
| emilmont | 77:869cf507173a | 228 | #define DMA_IT_TC DMA_CCR_TCIE |
| emilmont | 77:869cf507173a | 229 | #define DMA_IT_HT DMA_CCR_HTIE |
| emilmont | 77:869cf507173a | 230 | #define DMA_IT_TE DMA_CCR_TEIE |
| emilmont | 77:869cf507173a | 231 | |
| emilmont | 77:869cf507173a | 232 | #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) |
| emilmont | 77:869cf507173a | 233 | |
| emilmont | 77:869cf507173a | 234 | #define DMA1_IT_GL1 DMA_ISR_GIF1 |
| emilmont | 77:869cf507173a | 235 | #define DMA1_IT_TC1 DMA_ISR_TCIF1 |
| emilmont | 77:869cf507173a | 236 | #define DMA1_IT_HT1 DMA_ISR_HTIF1 |
| emilmont | 77:869cf507173a | 237 | #define DMA1_IT_TE1 DMA_ISR_TEIF1 |
| emilmont | 77:869cf507173a | 238 | #define DMA1_IT_GL2 DMA_ISR_GIF2 |
| emilmont | 77:869cf507173a | 239 | #define DMA1_IT_TC2 DMA_ISR_TCIF2 |
| emilmont | 77:869cf507173a | 240 | #define DMA1_IT_HT2 DMA_ISR_HTIF2 |
| emilmont | 77:869cf507173a | 241 | #define DMA1_IT_TE2 DMA_ISR_TEIF2 |
| emilmont | 77:869cf507173a | 242 | #define DMA1_IT_GL3 DMA_ISR_GIF3 |
| emilmont | 77:869cf507173a | 243 | #define DMA1_IT_TC3 DMA_ISR_TCIF3 |
| emilmont | 77:869cf507173a | 244 | #define DMA1_IT_HT3 DMA_ISR_HTIF3 |
| emilmont | 77:869cf507173a | 245 | #define DMA1_IT_TE3 DMA_ISR_TEIF3 |
| emilmont | 77:869cf507173a | 246 | #define DMA1_IT_GL4 DMA_ISR_GIF4 |
| emilmont | 77:869cf507173a | 247 | #define DMA1_IT_TC4 DMA_ISR_TCIF4 |
| emilmont | 77:869cf507173a | 248 | #define DMA1_IT_HT4 DMA_ISR_HTIF4 |
| emilmont | 77:869cf507173a | 249 | #define DMA1_IT_TE4 DMA_ISR_TEIF4 |
| emilmont | 77:869cf507173a | 250 | #define DMA1_IT_GL5 DMA_ISR_GIF5 |
| emilmont | 77:869cf507173a | 251 | #define DMA1_IT_TC5 DMA_ISR_TCIF5 |
| emilmont | 77:869cf507173a | 252 | #define DMA1_IT_HT5 DMA_ISR_HTIF5 |
| emilmont | 77:869cf507173a | 253 | #define DMA1_IT_TE5 DMA_ISR_TEIF5 |
| emilmont | 77:869cf507173a | 254 | #define DMA1_IT_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 255 | #define DMA1_IT_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 256 | #define DMA1_IT_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 257 | #define DMA1_IT_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 258 | #define DMA1_IT_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 259 | #define DMA1_IT_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 260 | #define DMA1_IT_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 261 | #define DMA1_IT_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 262 | |
| emilmont | 77:869cf507173a | 263 | #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xF0000000) == 0x00) && ((IT) != 0x00)) |
| emilmont | 77:869cf507173a | 264 | |
| emilmont | 77:869cf507173a | 265 | #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ |
| emilmont | 77:869cf507173a | 266 | ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ |
| emilmont | 77:869cf507173a | 267 | ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ |
| emilmont | 77:869cf507173a | 268 | ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ |
| emilmont | 77:869cf507173a | 269 | ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ |
| emilmont | 77:869cf507173a | 270 | ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ |
| emilmont | 77:869cf507173a | 271 | ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ |
| emilmont | 77:869cf507173a | 272 | ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ |
| emilmont | 77:869cf507173a | 273 | ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ |
| emilmont | 77:869cf507173a | 274 | ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ |
| emilmont | 77:869cf507173a | 275 | ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ |
| emilmont | 77:869cf507173a | 276 | ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ |
| emilmont | 77:869cf507173a | 277 | ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ |
| emilmont | 77:869cf507173a | 278 | ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7)) |
| emilmont | 77:869cf507173a | 279 | |
| emilmont | 77:869cf507173a | 280 | /** |
| emilmont | 77:869cf507173a | 281 | * @} |
| emilmont | 77:869cf507173a | 282 | */ |
| emilmont | 77:869cf507173a | 283 | |
| emilmont | 77:869cf507173a | 284 | /** @defgroup DMA_flags_definition |
| emilmont | 77:869cf507173a | 285 | * @{ |
| emilmont | 77:869cf507173a | 286 | */ |
| emilmont | 77:869cf507173a | 287 | #define DMA1_FLAG_GL1 DMA_ISR_GIF1 |
| emilmont | 77:869cf507173a | 288 | #define DMA1_FLAG_TC1 DMA_ISR_TCIF1 |
| emilmont | 77:869cf507173a | 289 | #define DMA1_FLAG_HT1 DMA_ISR_HTIF1 |
| emilmont | 77:869cf507173a | 290 | #define DMA1_FLAG_TE1 DMA_ISR_TEIF1 |
| emilmont | 77:869cf507173a | 291 | #define DMA1_FLAG_GL2 DMA_ISR_GIF2 |
| emilmont | 77:869cf507173a | 292 | #define DMA1_FLAG_TC2 DMA_ISR_TCIF2 |
| emilmont | 77:869cf507173a | 293 | #define DMA1_FLAG_HT2 DMA_ISR_HTIF2 |
| emilmont | 77:869cf507173a | 294 | #define DMA1_FLAG_TE2 DMA_ISR_TEIF2 |
| emilmont | 77:869cf507173a | 295 | #define DMA1_FLAG_GL3 DMA_ISR_GIF3 |
| emilmont | 77:869cf507173a | 296 | #define DMA1_FLAG_TC3 DMA_ISR_TCIF3 |
| emilmont | 77:869cf507173a | 297 | #define DMA1_FLAG_HT3 DMA_ISR_HTIF3 |
| emilmont | 77:869cf507173a | 298 | #define DMA1_FLAG_TE3 DMA_ISR_TEIF3 |
| emilmont | 77:869cf507173a | 299 | #define DMA1_FLAG_GL4 DMA_ISR_GIF4 |
| emilmont | 77:869cf507173a | 300 | #define DMA1_FLAG_TC4 DMA_ISR_TCIF4 |
| emilmont | 77:869cf507173a | 301 | #define DMA1_FLAG_HT4 DMA_ISR_HTIF4 |
| emilmont | 77:869cf507173a | 302 | #define DMA1_FLAG_TE4 DMA_ISR_TEIF4 |
| emilmont | 77:869cf507173a | 303 | #define DMA1_FLAG_GL5 DMA_ISR_GIF5 |
| emilmont | 77:869cf507173a | 304 | #define DMA1_FLAG_TC5 DMA_ISR_TCIF5 |
| emilmont | 77:869cf507173a | 305 | #define DMA1_FLAG_HT5 DMA_ISR_HTIF5 |
| emilmont | 77:869cf507173a | 306 | #define DMA1_FLAG_TE5 DMA_ISR_TEIF5 |
| emilmont | 77:869cf507173a | 307 | #define DMA1_FLAG_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 308 | #define DMA1_FLAG_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 309 | #define DMA1_FLAG_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 310 | #define DMA1_FLAG_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 311 | #define DMA1_FLAG_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 312 | #define DMA1_FLAG_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 313 | #define DMA1_FLAG_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 314 | #define DMA1_FLAG_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 315 | |
| emilmont | 77:869cf507173a | 316 | #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xF0000000) == 0x00) && ((FLAG) != 0x00)) |
| emilmont | 77:869cf507173a | 317 | |
| emilmont | 77:869cf507173a | 318 | #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ |
| emilmont | 77:869cf507173a | 319 | ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ |
| emilmont | 77:869cf507173a | 320 | ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ |
| emilmont | 77:869cf507173a | 321 | ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ |
| emilmont | 77:869cf507173a | 322 | ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ |
| emilmont | 77:869cf507173a | 323 | ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ |
| emilmont | 77:869cf507173a | 324 | ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ |
| emilmont | 77:869cf507173a | 325 | ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ |
| emilmont | 77:869cf507173a | 326 | ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ |
| emilmont | 77:869cf507173a | 327 | ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ |
| emilmont | 77:869cf507173a | 328 | ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ |
| emilmont | 77:869cf507173a | 329 | ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ |
| emilmont | 77:869cf507173a | 330 | ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ |
| emilmont | 77:869cf507173a | 331 | ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7)) |
| emilmont | 77:869cf507173a | 332 | |
| emilmont | 77:869cf507173a | 333 | /** |
| emilmont | 77:869cf507173a | 334 | * @} |
| emilmont | 77:869cf507173a | 335 | */ |
| emilmont | 77:869cf507173a | 336 | |
| emilmont | 77:869cf507173a | 337 | /** @defgroup DMA_Buffer_Size |
| emilmont | 77:869cf507173a | 338 | * @{ |
| emilmont | 77:869cf507173a | 339 | */ |
| emilmont | 77:869cf507173a | 340 | |
| emilmont | 77:869cf507173a | 341 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| emilmont | 77:869cf507173a | 342 | |
| emilmont | 77:869cf507173a | 343 | /** |
| emilmont | 77:869cf507173a | 344 | * @} |
| emilmont | 77:869cf507173a | 345 | */ |
| emilmont | 77:869cf507173a | 346 | |
| emilmont | 77:869cf507173a | 347 | /** |
| emilmont | 77:869cf507173a | 348 | * @} |
| emilmont | 77:869cf507173a | 349 | */ |
| emilmont | 77:869cf507173a | 350 | |
| emilmont | 77:869cf507173a | 351 | /* Exported macro ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 352 | /* Exported functions ------------------------------------------------------- */ |
| emilmont | 77:869cf507173a | 353 | |
| emilmont | 77:869cf507173a | 354 | /* Function used to set the DMA configuration to the default reset state ******/ |
| emilmont | 77:869cf507173a | 355 | void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); |
| emilmont | 77:869cf507173a | 356 | |
| emilmont | 77:869cf507173a | 357 | /* Initialization and Configuration functions *********************************/ |
| emilmont | 77:869cf507173a | 358 | void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); |
| emilmont | 77:869cf507173a | 359 | void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); |
| emilmont | 77:869cf507173a | 360 | void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 361 | |
| emilmont | 77:869cf507173a | 362 | /* Data Counter functions******************************************************/ |
| emilmont | 77:869cf507173a | 363 | void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); |
| emilmont | 77:869cf507173a | 364 | uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); |
| emilmont | 77:869cf507173a | 365 | |
| emilmont | 77:869cf507173a | 366 | /* Interrupts and flags management functions **********************************/ |
| emilmont | 77:869cf507173a | 367 | void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 368 | FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); |
| emilmont | 77:869cf507173a | 369 | void DMA_ClearFlag(uint32_t DMA_FLAG); |
| emilmont | 77:869cf507173a | 370 | ITStatus DMA_GetITStatus(uint32_t DMA_IT); |
| emilmont | 77:869cf507173a | 371 | void DMA_ClearITPendingBit(uint32_t DMA_IT); |
| emilmont | 77:869cf507173a | 372 | |
| emilmont | 77:869cf507173a | 373 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 374 | } |
| emilmont | 77:869cf507173a | 375 | #endif |
| emilmont | 77:869cf507173a | 376 | |
| emilmont | 77:869cf507173a | 377 | #endif /*__STM32F0XX_DMA_H */ |
| emilmont | 77:869cf507173a | 378 | |
| emilmont | 77:869cf507173a | 379 | /** |
| emilmont | 77:869cf507173a | 380 | * @} |
| emilmont | 77:869cf507173a | 381 | */ |
| emilmont | 77:869cf507173a | 382 | |
| emilmont | 77:869cf507173a | 383 | /** |
| emilmont | 77:869cf507173a | 384 | * @} |
| emilmont | 77:869cf507173a | 385 | */ |
| emilmont | 77:869cf507173a | 386 | |
| emilmont | 77:869cf507173a | 387 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |