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TARGET_NUCLEO_F030R8/stm32f0xx_crs.h@86:4f9a848d74c7, 2014-06-25 (annotated)

Committer:
erezi
Date:
Wed Jun 25 06:08:49 2014 +0000
Revision:
86:4f9a848d74c7
Parent:
81:7d30d6019079 
version_2.0

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emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f0xx_crs.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V1.3.0
emilmont 77:869cf507173a 6 * @date 16-January-2014
emilmont 77:869cf507173a 7 * @brief This file contains all the functions prototypes for the CRS firmware
emilmont 77:869cf507173a 8 * library, applicable only for STM32F042 and STM32F072 devices.
emilmont 77:869cf507173a 9 ******************************************************************************
emilmont 77:869cf507173a 10 * @attention
emilmont 77:869cf507173a 11 *
bogdanm 81:7d30d6019079 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 13 *
bogdanm 81:7d30d6019079 14 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 81:7d30d6019079 15 * are permitted provided that the following conditions are met:
bogdanm 81:7d30d6019079 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 81:7d30d6019079 17 * this list of conditions and the following disclaimer.
bogdanm 81:7d30d6019079 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 81:7d30d6019079 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 81:7d30d6019079 20 * and/or other materials provided with the distribution.
bogdanm 81:7d30d6019079 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 81:7d30d6019079 22 * may be used to endorse or promote products derived from this software
bogdanm 81:7d30d6019079 23 * without specific prior written permission.
emilmont 77:869cf507173a 24 *
bogdanm 81:7d30d6019079 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 81:7d30d6019079 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 81:7d30d6019079 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 81:7d30d6019079 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 81:7d30d6019079 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 81:7d30d6019079 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 81:7d30d6019079 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 81:7d30d6019079 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 81:7d30d6019079 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 81:7d30d6019079 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 35 *
emilmont 77:869cf507173a 36 ******************************************************************************
emilmont 77:869cf507173a 37 */
emilmont 77:869cf507173a 38
emilmont 77:869cf507173a 39 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 40 #ifndef __STM32F0XX_CRS_H
emilmont 77:869cf507173a 41 #define __STM32F0XX_CRS_H
emilmont 77:869cf507173a 42
emilmont 77:869cf507173a 43 #ifdef __cplusplus
emilmont 77:869cf507173a 44 extern "C" {
emilmont 77:869cf507173a 45 #endif
emilmont 77:869cf507173a 46
emilmont 77:869cf507173a 47 /*!< Includes ----------------------------------------------------------------*/
emilmont 77:869cf507173a 48 #include "stm32f0xx.h"
emilmont 77:869cf507173a 49
emilmont 77:869cf507173a 50 /** @addtogroup STM32F0xx_StdPeriph_Driver
emilmont 77:869cf507173a 51 * @{
emilmont 77:869cf507173a 52 */
emilmont 77:869cf507173a 53
emilmont 77:869cf507173a 54 /** @addtogroup CRS
emilmont 77:869cf507173a 55 * @{
emilmont 77:869cf507173a 56 */
emilmont 77:869cf507173a 57
emilmont 77:869cf507173a 58 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 59 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 60
emilmont 77:869cf507173a 61 /** @defgroup CRS_Interrupt_Sources
emilmont 77:869cf507173a 62 * @{
emilmont 77:869cf507173a 63 */
emilmont 77:869cf507173a 64 #define CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
emilmont 77:869cf507173a 65 #define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
emilmont 77:869cf507173a 66 #define CRS_IT_ERR CRS_ISR_ERRF /*!< error */
emilmont 77:869cf507173a 67 #define CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
emilmont 77:869cf507173a 68 #define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
emilmont 77:869cf507173a 69 #define CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
emilmont 77:869cf507173a 70 #define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
emilmont 77:869cf507173a 71
emilmont 77:869cf507173a 72 #define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
emilmont 77:869cf507173a 73 ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC))
emilmont 77:869cf507173a 74
emilmont 77:869cf507173a 75 #define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
emilmont 77:869cf507173a 76 ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \
emilmont 77:869cf507173a 77 ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \
emilmont 77:869cf507173a 78 ((IT) == CRS_IT_SYNCMISS))
emilmont 77:869cf507173a 79
emilmont 77:869cf507173a 80 #define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00)
emilmont 77:869cf507173a 81
emilmont 77:869cf507173a 82 /**
emilmont 77:869cf507173a 83 * @}
emilmont 77:869cf507173a 84 */
emilmont 77:869cf507173a 85
emilmont 77:869cf507173a 86 /** @defgroup CRS_Flags
emilmont 77:869cf507173a 87 * @{
emilmont 77:869cf507173a 88 */
emilmont 77:869cf507173a 89 #define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
emilmont 77:869cf507173a 90 #define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
emilmont 77:869cf507173a 91 #define CRS_FLAG_ERR CRS_ISR_ERRF /*!< error */
emilmont 77:869cf507173a 92 #define CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
emilmont 77:869cf507173a 93 #define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
emilmont 77:869cf507173a 94 #define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
emilmont 77:869cf507173a 95 #define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
emilmont 77:869cf507173a 96
emilmont 77:869cf507173a 97 #define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \
emilmont 77:869cf507173a 98 ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \
emilmont 77:869cf507173a 99 ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \
emilmont 77:869cf507173a 100 ((FLAG) == CRS_FLAG_SYNCMISS))
emilmont 77:869cf507173a 101
emilmont 77:869cf507173a 102 /**
emilmont 77:869cf507173a 103 * @}
emilmont 77:869cf507173a 104 */
emilmont 77:869cf507173a 105
emilmont 77:869cf507173a 106 /** @defgroup CRS_Synchro_Source
emilmont 77:869cf507173a 107 * @{
emilmont 77:869cf507173a 108 */
emilmont 77:869cf507173a 109 #define CRS_SYNCSource_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */
emilmont 77:869cf507173a 110 #define CRS_SYNCSource_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
emilmont 77:869cf507173a 111 #define CRS_SYNCSource_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF */
emilmont 77:869cf507173a 112
emilmont 77:869cf507173a 113 #define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \
emilmont 77:869cf507173a 114 ((SOURCE) == CRS_SYNCSource_LSE) ||\
emilmont 77:869cf507173a 115 ((SOURCE) == CRS_SYNCSource_USB))
emilmont 77:869cf507173a 116 /**
emilmont 77:869cf507173a 117 * @}
emilmont 77:869cf507173a 118 */
emilmont 77:869cf507173a 119
emilmont 77:869cf507173a 120 /** @defgroup CRS_SynchroDivider
emilmont 77:869cf507173a 121 * @{
emilmont 77:869cf507173a 122 */
emilmont 77:869cf507173a 123 #define CRS_SYNC_Div1 ((uint32_t)0x00) /*!< Synchro Signal not divided */
emilmont 77:869cf507173a 124 #define CRS_SYNC_Div2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
emilmont 77:869cf507173a 125 #define CRS_SYNC_Div4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
emilmont 77:869cf507173a 126 #define CRS_SYNC_Div8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
emilmont 77:869cf507173a 127 #define CRS_SYNC_Div16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
emilmont 77:869cf507173a 128 #define CRS_SYNC_Div32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
emilmont 77:869cf507173a 129 #define CRS_SYNC_Div64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
emilmont 77:869cf507173a 130 #define CRS_SYNC_Div128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
emilmont 77:869cf507173a 131
emilmont 77:869cf507173a 132 #define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2) ||\
emilmont 77:869cf507173a 133 ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8) || \
emilmont 77:869cf507173a 134 ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \
emilmont 77:869cf507173a 135 ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128))
emilmont 77:869cf507173a 136 /**
emilmont 77:869cf507173a 137 * @}
emilmont 77:869cf507173a 138 */
emilmont 77:869cf507173a 139
emilmont 77:869cf507173a 140 /** @defgroup CRS_SynchroPolarity
emilmont 77:869cf507173a 141 * @{
emilmont 77:869cf507173a 142 */
emilmont 77:869cf507173a 143 #define CRS_SYNCPolarity_Rising ((uint32_t)0x00) /*!< Synchro Active on rising edge */
emilmont 77:869cf507173a 144 #define CRS_SYNCPolarity_Falling CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
emilmont 77:869cf507173a 145
emilmont 77:869cf507173a 146 #define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \
emilmont 77:869cf507173a 147 ((POLARITY) == CRS_SYNCPolarity_Falling))
emilmont 77:869cf507173a 148 /**
emilmont 77:869cf507173a 149 * @}
emilmont 77:869cf507173a 150 */
emilmont 77:869cf507173a 151
emilmont 77:869cf507173a 152
emilmont 77:869cf507173a 153
emilmont 77:869cf507173a 154 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 155 /* Exported functions ------------------------------------------------------- */
emilmont 77:869cf507173a 156 /* Configuration of the CRS **********************************/
emilmont 77:869cf507173a 157 void CRS_DeInit(void);
emilmont 77:869cf507173a 158 void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue);
emilmont 77:869cf507173a 159 void CRS_FrequencyErrorCounterCmd(FunctionalState NewState);
emilmont 77:869cf507173a 160 void CRS_AutomaticCalibrationCmd(FunctionalState NewState);
emilmont 77:869cf507173a 161 void CRS_SoftwareSynchronizationGenerate(void);
emilmont 77:869cf507173a 162 void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue);
emilmont 77:869cf507173a 163 void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue);
emilmont 77:869cf507173a 164 void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler);
emilmont 77:869cf507173a 165 void CRS_SynchronizationSourceConfig(uint32_t CRS_Source);
emilmont 77:869cf507173a 166 void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity);
emilmont 77:869cf507173a 167 uint32_t CRS_GetReloadValue(void);
emilmont 77:869cf507173a 168 uint32_t CRS_GetHSI48CalibrationValue(void);
emilmont 77:869cf507173a 169 uint32_t CRS_GetFrequencyErrorValue(void);
emilmont 77:869cf507173a 170 uint32_t CRS_GetFrequencyErrorDirection(void);
emilmont 77:869cf507173a 171
emilmont 77:869cf507173a 172 /* Interrupts and flags management functions **********************************/
emilmont 77:869cf507173a 173 void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState);
emilmont 77:869cf507173a 174 FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG);
emilmont 77:869cf507173a 175 void CRS_ClearFlag(uint32_t CRS_FLAG);
emilmont 77:869cf507173a 176 ITStatus CRS_GetITStatus(uint32_t CRS_IT);
emilmont 77:869cf507173a 177 void CRS_ClearITPendingBit(uint32_t CRS_IT);
emilmont 77:869cf507173a 178
emilmont 77:869cf507173a 179 #ifdef __cplusplus
emilmont 77:869cf507173a 180 }
emilmont 77:869cf507173a 181 #endif
emilmont 77:869cf507173a 182
emilmont 77:869cf507173a 183 #endif /* __STM32F0XX_CRS_H */
emilmont 77:869cf507173a 184
emilmont 77:869cf507173a 185 /**
emilmont 77:869cf507173a 186 * @}
emilmont 77:869cf507173a 187 */
emilmont 77:869cf507173a 188
emilmont 77:869cf507173a 189 /**
emilmont 77:869cf507173a 190 * @}
emilmont 77:869cf507173a 191 */
emilmont 77:869cf507173a 192
emilmont 77:869cf507173a 193 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/