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TARGET_LPC11U68/core_cm3.h@86:4f9a848d74c7, 2014-06-25 (annotated)

Committer:
erezi
Date:
Wed Jun 25 06:08:49 2014 +0000
Revision:
86:4f9a848d74c7
Parent:
84:0b3ab51c8877 
version_2.0

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bogdanm 84:0b3ab51c8877 1 /**************************************************************************//**
bogdanm 84:0b3ab51c8877 2 * @file core_cm3.h
bogdanm 84:0b3ab51c8877 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
bogdanm 84:0b3ab51c8877 4 * @version V3.20
bogdanm 84:0b3ab51c8877 5 * @date 25. February 2013
bogdanm 84:0b3ab51c8877 6 *
bogdanm 84:0b3ab51c8877 7 * @note
bogdanm 84:0b3ab51c8877 8 *
bogdanm 84:0b3ab51c8877 9 ******************************************************************************/
bogdanm 84:0b3ab51c8877 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 84:0b3ab51c8877 11
bogdanm 84:0b3ab51c8877 12 All rights reserved.
bogdanm 84:0b3ab51c8877 13 Redistribution and use in source and binary forms, with or without
bogdanm 84:0b3ab51c8877 14 modification, are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 - Redistributions of source code must retain the above copyright
bogdanm 84:0b3ab51c8877 16 notice, this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 84:0b3ab51c8877 18 notice, this list of conditions and the following disclaimer in the
bogdanm 84:0b3ab51c8877 19 documentation and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 84:0b3ab51c8877 21 to endorse or promote products derived from this software without
bogdanm 84:0b3ab51c8877 22 specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 84:0b3ab51c8877 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 84:0b3ab51c8877 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 84:0b3ab51c8877 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 84:0b3ab51c8877 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 84:0b3ab51c8877 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 84:0b3ab51c8877 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 84:0b3ab51c8877 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 84:0b3ab51c8877 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 35 ---------------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 36
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 #if defined ( __ICCARM__ )
bogdanm 84:0b3ab51c8877 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 84:0b3ab51c8877 40 #endif
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 #ifndef __CORE_CM3_H_GENERIC
bogdanm 84:0b3ab51c8877 47 #define __CORE_CM3_H_GENERIC
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 84:0b3ab51c8877 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 84:0b3ab51c8877 51
bogdanm 84:0b3ab51c8877 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 84:0b3ab51c8877 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 84:0b3ab51c8877 54
bogdanm 84:0b3ab51c8877 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 84:0b3ab51c8877 56 Unions are used for effective representation of core registers.
bogdanm 84:0b3ab51c8877 57
bogdanm 84:0b3ab51c8877 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 84:0b3ab51c8877 59 Function-like macros are used to allow more efficient code.
bogdanm 84:0b3ab51c8877 60 */
bogdanm 84:0b3ab51c8877 61
bogdanm 84:0b3ab51c8877 62
bogdanm 84:0b3ab51c8877 63 /*******************************************************************************
bogdanm 84:0b3ab51c8877 64 * CMSIS definitions
bogdanm 84:0b3ab51c8877 65 ******************************************************************************/
bogdanm 84:0b3ab51c8877 66 /** \ingroup Cortex_M3
bogdanm 84:0b3ab51c8877 67 @{
bogdanm 84:0b3ab51c8877 68 */
bogdanm 84:0b3ab51c8877 69
bogdanm 84:0b3ab51c8877 70 /* CMSIS CM3 definitions */
bogdanm 84:0b3ab51c8877 71 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
bogdanm 84:0b3ab51c8877 72 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
bogdanm 84:0b3ab51c8877 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
bogdanm 84:0b3ab51c8877 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
bogdanm 84:0b3ab51c8877 75
bogdanm 84:0b3ab51c8877 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
bogdanm 84:0b3ab51c8877 77
bogdanm 84:0b3ab51c8877 78
bogdanm 84:0b3ab51c8877 79 #if defined ( __CC_ARM )
bogdanm 84:0b3ab51c8877 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 84:0b3ab51c8877 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 84:0b3ab51c8877 82 #define __STATIC_INLINE static __inline
bogdanm 84:0b3ab51c8877 83
bogdanm 84:0b3ab51c8877 84 #elif defined ( __ICCARM__ )
bogdanm 84:0b3ab51c8877 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 84:0b3ab51c8877 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 84:0b3ab51c8877 87 #define __STATIC_INLINE static inline
bogdanm 84:0b3ab51c8877 88
bogdanm 84:0b3ab51c8877 89 #elif defined ( __TMS470__ )
bogdanm 84:0b3ab51c8877 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 84:0b3ab51c8877 91 #define __STATIC_INLINE static inline
bogdanm 84:0b3ab51c8877 92
bogdanm 84:0b3ab51c8877 93 #elif defined ( __GNUC__ )
bogdanm 84:0b3ab51c8877 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 84:0b3ab51c8877 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 84:0b3ab51c8877 96 #define __STATIC_INLINE static inline
bogdanm 84:0b3ab51c8877 97
bogdanm 84:0b3ab51c8877 98 #elif defined ( __TASKING__ )
bogdanm 84:0b3ab51c8877 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 84:0b3ab51c8877 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 84:0b3ab51c8877 101 #define __STATIC_INLINE static inline
bogdanm 84:0b3ab51c8877 102
bogdanm 84:0b3ab51c8877 103 #endif
bogdanm 84:0b3ab51c8877 104
bogdanm 84:0b3ab51c8877 105 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
bogdanm 84:0b3ab51c8877 106 */
bogdanm 84:0b3ab51c8877 107 #define __FPU_USED 0
bogdanm 84:0b3ab51c8877 108
bogdanm 84:0b3ab51c8877 109 #if defined ( __CC_ARM )
bogdanm 84:0b3ab51c8877 110 #if defined __TARGET_FPU_VFP
bogdanm 84:0b3ab51c8877 111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 112 #endif
bogdanm 84:0b3ab51c8877 113
bogdanm 84:0b3ab51c8877 114 #elif defined ( __ICCARM__ )
bogdanm 84:0b3ab51c8877 115 #if defined __ARMVFP__
bogdanm 84:0b3ab51c8877 116 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 117 #endif
bogdanm 84:0b3ab51c8877 118
bogdanm 84:0b3ab51c8877 119 #elif defined ( __TMS470__ )
bogdanm 84:0b3ab51c8877 120 #if defined __TI__VFP_SUPPORT____
bogdanm 84:0b3ab51c8877 121 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 122 #endif
bogdanm 84:0b3ab51c8877 123
bogdanm 84:0b3ab51c8877 124 #elif defined ( __GNUC__ )
bogdanm 84:0b3ab51c8877 125 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
bogdanm 84:0b3ab51c8877 126 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 127 #endif
bogdanm 84:0b3ab51c8877 128
bogdanm 84:0b3ab51c8877 129 #elif defined ( __TASKING__ )
bogdanm 84:0b3ab51c8877 130 #if defined __FPU_VFP__
bogdanm 84:0b3ab51c8877 131 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 132 #endif
bogdanm 84:0b3ab51c8877 133 #endif
bogdanm 84:0b3ab51c8877 134
bogdanm 84:0b3ab51c8877 135 #include <stdint.h> /* standard types definitions */
bogdanm 84:0b3ab51c8877 136 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 84:0b3ab51c8877 137 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 84:0b3ab51c8877 138
bogdanm 84:0b3ab51c8877 139 #endif /* __CORE_CM3_H_GENERIC */
bogdanm 84:0b3ab51c8877 140
bogdanm 84:0b3ab51c8877 141 #ifndef __CMSIS_GENERIC
bogdanm 84:0b3ab51c8877 142
bogdanm 84:0b3ab51c8877 143 #ifndef __CORE_CM3_H_DEPENDANT
bogdanm 84:0b3ab51c8877 144 #define __CORE_CM3_H_DEPENDANT
bogdanm 84:0b3ab51c8877 145
bogdanm 84:0b3ab51c8877 146 /* check device defines and use defaults */
bogdanm 84:0b3ab51c8877 147 #if defined __CHECK_DEVICE_DEFINES
bogdanm 84:0b3ab51c8877 148 #ifndef __CM3_REV
bogdanm 84:0b3ab51c8877 149 #define __CM3_REV 0x0200
bogdanm 84:0b3ab51c8877 150 #warning "__CM3_REV not defined in device header file; using default!"
bogdanm 84:0b3ab51c8877 151 #endif
bogdanm 84:0b3ab51c8877 152
bogdanm 84:0b3ab51c8877 153 #ifndef __MPU_PRESENT
bogdanm 84:0b3ab51c8877 154 #define __MPU_PRESENT 0
bogdanm 84:0b3ab51c8877 155 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 84:0b3ab51c8877 156 #endif
bogdanm 84:0b3ab51c8877 157
bogdanm 84:0b3ab51c8877 158 #ifndef __NVIC_PRIO_BITS
bogdanm 84:0b3ab51c8877 159 #define __NVIC_PRIO_BITS 4
bogdanm 84:0b3ab51c8877 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 84:0b3ab51c8877 161 #endif
bogdanm 84:0b3ab51c8877 162
bogdanm 84:0b3ab51c8877 163 #ifndef __Vendor_SysTickConfig
bogdanm 84:0b3ab51c8877 164 #define __Vendor_SysTickConfig 0
bogdanm 84:0b3ab51c8877 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 84:0b3ab51c8877 166 #endif
bogdanm 84:0b3ab51c8877 167 #endif
bogdanm 84:0b3ab51c8877 168
bogdanm 84:0b3ab51c8877 169 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 84:0b3ab51c8877 170 /**
bogdanm 84:0b3ab51c8877 171 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 84:0b3ab51c8877 172
bogdanm 84:0b3ab51c8877 173 <strong>IO Type Qualifiers</strong> are used
bogdanm 84:0b3ab51c8877 174 \li to specify the access to peripheral variables.
bogdanm 84:0b3ab51c8877 175 \li for automatic generation of peripheral register debug information.
bogdanm 84:0b3ab51c8877 176 */
bogdanm 84:0b3ab51c8877 177 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 178 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 84:0b3ab51c8877 179 #else
bogdanm 84:0b3ab51c8877 180 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 84:0b3ab51c8877 181 #endif
bogdanm 84:0b3ab51c8877 182 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 84:0b3ab51c8877 183 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 84:0b3ab51c8877 184
bogdanm 84:0b3ab51c8877 185 /*@} end of group Cortex_M3 */
bogdanm 84:0b3ab51c8877 186
bogdanm 84:0b3ab51c8877 187
bogdanm 84:0b3ab51c8877 188
bogdanm 84:0b3ab51c8877 189 /*******************************************************************************
bogdanm 84:0b3ab51c8877 190 * Register Abstraction
bogdanm 84:0b3ab51c8877 191 Core Register contain:
bogdanm 84:0b3ab51c8877 192 - Core Register
bogdanm 84:0b3ab51c8877 193 - Core NVIC Register
bogdanm 84:0b3ab51c8877 194 - Core SCB Register
bogdanm 84:0b3ab51c8877 195 - Core SysTick Register
bogdanm 84:0b3ab51c8877 196 - Core Debug Register
bogdanm 84:0b3ab51c8877 197 - Core MPU Register
bogdanm 84:0b3ab51c8877 198 ******************************************************************************/
bogdanm 84:0b3ab51c8877 199 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 84:0b3ab51c8877 200 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 84:0b3ab51c8877 201 */
bogdanm 84:0b3ab51c8877 202
bogdanm 84:0b3ab51c8877 203 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 204 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 84:0b3ab51c8877 205 \brief Core Register type definitions.
bogdanm 84:0b3ab51c8877 206 @{
bogdanm 84:0b3ab51c8877 207 */
bogdanm 84:0b3ab51c8877 208
bogdanm 84:0b3ab51c8877 209 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 84:0b3ab51c8877 210 */
bogdanm 84:0b3ab51c8877 211 typedef union
bogdanm 84:0b3ab51c8877 212 {
bogdanm 84:0b3ab51c8877 213 struct
bogdanm 84:0b3ab51c8877 214 {
bogdanm 84:0b3ab51c8877 215 #if (__CORTEX_M != 0x04)
bogdanm 84:0b3ab51c8877 216 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
bogdanm 84:0b3ab51c8877 217 #else
bogdanm 84:0b3ab51c8877 218 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
bogdanm 84:0b3ab51c8877 219 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 84:0b3ab51c8877 220 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
bogdanm 84:0b3ab51c8877 221 #endif
bogdanm 84:0b3ab51c8877 222 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 84:0b3ab51c8877 223 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 84:0b3ab51c8877 224 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 84:0b3ab51c8877 225 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 84:0b3ab51c8877 226 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 84:0b3ab51c8877 227 } b; /*!< Structure used for bit access */
bogdanm 84:0b3ab51c8877 228 uint32_t w; /*!< Type used for word access */
bogdanm 84:0b3ab51c8877 229 } APSR_Type;
bogdanm 84:0b3ab51c8877 230
bogdanm 84:0b3ab51c8877 231
bogdanm 84:0b3ab51c8877 232 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 84:0b3ab51c8877 233 */
bogdanm 84:0b3ab51c8877 234 typedef union
bogdanm 84:0b3ab51c8877 235 {
bogdanm 84:0b3ab51c8877 236 struct
bogdanm 84:0b3ab51c8877 237 {
bogdanm 84:0b3ab51c8877 238 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 84:0b3ab51c8877 239 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 84:0b3ab51c8877 240 } b; /*!< Structure used for bit access */
bogdanm 84:0b3ab51c8877 241 uint32_t w; /*!< Type used for word access */
bogdanm 84:0b3ab51c8877 242 } IPSR_Type;
bogdanm 84:0b3ab51c8877 243
bogdanm 84:0b3ab51c8877 244
bogdanm 84:0b3ab51c8877 245 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 84:0b3ab51c8877 246 */
bogdanm 84:0b3ab51c8877 247 typedef union
bogdanm 84:0b3ab51c8877 248 {
bogdanm 84:0b3ab51c8877 249 struct
bogdanm 84:0b3ab51c8877 250 {
bogdanm 84:0b3ab51c8877 251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 84:0b3ab51c8877 252 #if (__CORTEX_M != 0x04)
bogdanm 84:0b3ab51c8877 253 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 84:0b3ab51c8877 254 #else
bogdanm 84:0b3ab51c8877 255 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
bogdanm 84:0b3ab51c8877 256 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 84:0b3ab51c8877 257 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
bogdanm 84:0b3ab51c8877 258 #endif
bogdanm 84:0b3ab51c8877 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
bogdanm 84:0b3ab51c8877 260 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
bogdanm 84:0b3ab51c8877 261 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 84:0b3ab51c8877 262 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 84:0b3ab51c8877 263 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 84:0b3ab51c8877 264 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 84:0b3ab51c8877 265 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 84:0b3ab51c8877 266 } b; /*!< Structure used for bit access */
bogdanm 84:0b3ab51c8877 267 uint32_t w; /*!< Type used for word access */
bogdanm 84:0b3ab51c8877 268 } xPSR_Type;
bogdanm 84:0b3ab51c8877 269
bogdanm 84:0b3ab51c8877 270
bogdanm 84:0b3ab51c8877 271 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 84:0b3ab51c8877 272 */
bogdanm 84:0b3ab51c8877 273 typedef union
bogdanm 84:0b3ab51c8877 274 {
bogdanm 84:0b3ab51c8877 275 struct
bogdanm 84:0b3ab51c8877 276 {
bogdanm 84:0b3ab51c8877 277 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 84:0b3ab51c8877 278 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
bogdanm 84:0b3ab51c8877 279 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
bogdanm 84:0b3ab51c8877 280 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
bogdanm 84:0b3ab51c8877 281 } b; /*!< Structure used for bit access */
bogdanm 84:0b3ab51c8877 282 uint32_t w; /*!< Type used for word access */
bogdanm 84:0b3ab51c8877 283 } CONTROL_Type;
bogdanm 84:0b3ab51c8877 284
bogdanm 84:0b3ab51c8877 285 /*@} end of group CMSIS_CORE */
bogdanm 84:0b3ab51c8877 286
bogdanm 84:0b3ab51c8877 287
bogdanm 84:0b3ab51c8877 288 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 289 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 84:0b3ab51c8877 290 \brief Type definitions for the NVIC Registers
bogdanm 84:0b3ab51c8877 291 @{
bogdanm 84:0b3ab51c8877 292 */
bogdanm 84:0b3ab51c8877 293
bogdanm 84:0b3ab51c8877 294 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 84:0b3ab51c8877 295 */
bogdanm 84:0b3ab51c8877 296 typedef struct
bogdanm 84:0b3ab51c8877 297 {
bogdanm 84:0b3ab51c8877 298 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 84:0b3ab51c8877 299 uint32_t RESERVED0[24];
bogdanm 84:0b3ab51c8877 300 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 84:0b3ab51c8877 301 uint32_t RSERVED1[24];
bogdanm 84:0b3ab51c8877 302 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 84:0b3ab51c8877 303 uint32_t RESERVED2[24];
bogdanm 84:0b3ab51c8877 304 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 84:0b3ab51c8877 305 uint32_t RESERVED3[24];
bogdanm 84:0b3ab51c8877 306 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
bogdanm 84:0b3ab51c8877 307 uint32_t RESERVED4[56];
bogdanm 84:0b3ab51c8877 308 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
bogdanm 84:0b3ab51c8877 309 uint32_t RESERVED5[644];
bogdanm 84:0b3ab51c8877 310 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
bogdanm 84:0b3ab51c8877 311 } NVIC_Type;
bogdanm 84:0b3ab51c8877 312
bogdanm 84:0b3ab51c8877 313 /* Software Triggered Interrupt Register Definitions */
bogdanm 84:0b3ab51c8877 314 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
bogdanm 84:0b3ab51c8877 315 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
bogdanm 84:0b3ab51c8877 316
bogdanm 84:0b3ab51c8877 317 /*@} end of group CMSIS_NVIC */
bogdanm 84:0b3ab51c8877 318
bogdanm 84:0b3ab51c8877 319
bogdanm 84:0b3ab51c8877 320 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 321 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 84:0b3ab51c8877 322 \brief Type definitions for the System Control Block Registers
bogdanm 84:0b3ab51c8877 323 @{
bogdanm 84:0b3ab51c8877 324 */
bogdanm 84:0b3ab51c8877 325
bogdanm 84:0b3ab51c8877 326 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 84:0b3ab51c8877 327 */
bogdanm 84:0b3ab51c8877 328 typedef struct
bogdanm 84:0b3ab51c8877 329 {
bogdanm 84:0b3ab51c8877 330 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 84:0b3ab51c8877 331 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 84:0b3ab51c8877 332 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 84:0b3ab51c8877 333 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 84:0b3ab51c8877 334 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 84:0b3ab51c8877 335 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 84:0b3ab51c8877 336 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
bogdanm 84:0b3ab51c8877 337 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 84:0b3ab51c8877 338 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
bogdanm 84:0b3ab51c8877 339 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
bogdanm 84:0b3ab51c8877 340 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
bogdanm 84:0b3ab51c8877 341 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
bogdanm 84:0b3ab51c8877 342 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
bogdanm 84:0b3ab51c8877 343 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
bogdanm 84:0b3ab51c8877 344 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
bogdanm 84:0b3ab51c8877 345 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
bogdanm 84:0b3ab51c8877 346 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
bogdanm 84:0b3ab51c8877 347 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
bogdanm 84:0b3ab51c8877 348 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
bogdanm 84:0b3ab51c8877 349 uint32_t RESERVED0[5];
bogdanm 84:0b3ab51c8877 350 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
bogdanm 84:0b3ab51c8877 351 } SCB_Type;
bogdanm 84:0b3ab51c8877 352
bogdanm 84:0b3ab51c8877 353 /* SCB CPUID Register Definitions */
bogdanm 84:0b3ab51c8877 354 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 84:0b3ab51c8877 355 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 84:0b3ab51c8877 356
bogdanm 84:0b3ab51c8877 357 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 84:0b3ab51c8877 358 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 84:0b3ab51c8877 359
bogdanm 84:0b3ab51c8877 360 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 84:0b3ab51c8877 361 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 84:0b3ab51c8877 362
bogdanm 84:0b3ab51c8877 363 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 84:0b3ab51c8877 364 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 84:0b3ab51c8877 365
bogdanm 84:0b3ab51c8877 366 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
bogdanm 84:0b3ab51c8877 367 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
bogdanm 84:0b3ab51c8877 368
bogdanm 84:0b3ab51c8877 369 /* SCB Interrupt Control State Register Definitions */
bogdanm 84:0b3ab51c8877 370 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 84:0b3ab51c8877 371 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 84:0b3ab51c8877 372
bogdanm 84:0b3ab51c8877 373 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 84:0b3ab51c8877 374 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 84:0b3ab51c8877 375
bogdanm 84:0b3ab51c8877 376 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 84:0b3ab51c8877 377 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 84:0b3ab51c8877 378
bogdanm 84:0b3ab51c8877 379 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 84:0b3ab51c8877 380 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 84:0b3ab51c8877 381
bogdanm 84:0b3ab51c8877 382 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 84:0b3ab51c8877 383 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 84:0b3ab51c8877 384
bogdanm 84:0b3ab51c8877 385 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 84:0b3ab51c8877 386 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 84:0b3ab51c8877 387
bogdanm 84:0b3ab51c8877 388 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 84:0b3ab51c8877 389 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 84:0b3ab51c8877 390
bogdanm 84:0b3ab51c8877 391 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 84:0b3ab51c8877 392 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 84:0b3ab51c8877 393
bogdanm 84:0b3ab51c8877 394 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
bogdanm 84:0b3ab51c8877 395 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
bogdanm 84:0b3ab51c8877 396
bogdanm 84:0b3ab51c8877 397 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
bogdanm 84:0b3ab51c8877 398 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 84:0b3ab51c8877 399
bogdanm 84:0b3ab51c8877 400 /* SCB Vector Table Offset Register Definitions */
bogdanm 84:0b3ab51c8877 401 #if (__CM3_REV < 0x0201) /* core r2p1 */
bogdanm 84:0b3ab51c8877 402 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
bogdanm 84:0b3ab51c8877 403 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
bogdanm 84:0b3ab51c8877 404
bogdanm 84:0b3ab51c8877 405 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
bogdanm 84:0b3ab51c8877 406 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 84:0b3ab51c8877 407 #else
bogdanm 84:0b3ab51c8877 408 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
bogdanm 84:0b3ab51c8877 409 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 84:0b3ab51c8877 410 #endif
bogdanm 84:0b3ab51c8877 411
bogdanm 84:0b3ab51c8877 412 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 84:0b3ab51c8877 413 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 84:0b3ab51c8877 414 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 84:0b3ab51c8877 415
bogdanm 84:0b3ab51c8877 416 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 84:0b3ab51c8877 417 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 84:0b3ab51c8877 418
bogdanm 84:0b3ab51c8877 419 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 84:0b3ab51c8877 420 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 84:0b3ab51c8877 421
bogdanm 84:0b3ab51c8877 422 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
bogdanm 84:0b3ab51c8877 423 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
bogdanm 84:0b3ab51c8877 424
bogdanm 84:0b3ab51c8877 425 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 84:0b3ab51c8877 426 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 84:0b3ab51c8877 427
bogdanm 84:0b3ab51c8877 428 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 84:0b3ab51c8877 429 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 84:0b3ab51c8877 430
bogdanm 84:0b3ab51c8877 431 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
bogdanm 84:0b3ab51c8877 432 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
bogdanm 84:0b3ab51c8877 433
bogdanm 84:0b3ab51c8877 434 /* SCB System Control Register Definitions */
bogdanm 84:0b3ab51c8877 435 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 84:0b3ab51c8877 436 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 84:0b3ab51c8877 437
bogdanm 84:0b3ab51c8877 438 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 84:0b3ab51c8877 439 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 84:0b3ab51c8877 440
bogdanm 84:0b3ab51c8877 441 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 84:0b3ab51c8877 442 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 84:0b3ab51c8877 443
bogdanm 84:0b3ab51c8877 444 /* SCB Configuration Control Register Definitions */
bogdanm 84:0b3ab51c8877 445 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 84:0b3ab51c8877 446 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 84:0b3ab51c8877 447
bogdanm 84:0b3ab51c8877 448 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
bogdanm 84:0b3ab51c8877 449 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
bogdanm 84:0b3ab51c8877 450
bogdanm 84:0b3ab51c8877 451 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
bogdanm 84:0b3ab51c8877 452 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
bogdanm 84:0b3ab51c8877 453
bogdanm 84:0b3ab51c8877 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 84:0b3ab51c8877 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 84:0b3ab51c8877 456
bogdanm 84:0b3ab51c8877 457 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
bogdanm 84:0b3ab51c8877 458 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
bogdanm 84:0b3ab51c8877 459
bogdanm 84:0b3ab51c8877 460 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
bogdanm 84:0b3ab51c8877 461 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
bogdanm 84:0b3ab51c8877 462
bogdanm 84:0b3ab51c8877 463 /* SCB System Handler Control and State Register Definitions */
bogdanm 84:0b3ab51c8877 464 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
bogdanm 84:0b3ab51c8877 465 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
bogdanm 84:0b3ab51c8877 466
bogdanm 84:0b3ab51c8877 467 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
bogdanm 84:0b3ab51c8877 468 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
bogdanm 84:0b3ab51c8877 469
bogdanm 84:0b3ab51c8877 470 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
bogdanm 84:0b3ab51c8877 471 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
bogdanm 84:0b3ab51c8877 472
bogdanm 84:0b3ab51c8877 473 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 84:0b3ab51c8877 474 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 84:0b3ab51c8877 475
bogdanm 84:0b3ab51c8877 476 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
bogdanm 84:0b3ab51c8877 477 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
bogdanm 84:0b3ab51c8877 478
bogdanm 84:0b3ab51c8877 479 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
bogdanm 84:0b3ab51c8877 480 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
bogdanm 84:0b3ab51c8877 481
bogdanm 84:0b3ab51c8877 482 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
bogdanm 84:0b3ab51c8877 483 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
bogdanm 84:0b3ab51c8877 484
bogdanm 84:0b3ab51c8877 485 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
bogdanm 84:0b3ab51c8877 486 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
bogdanm 84:0b3ab51c8877 487
bogdanm 84:0b3ab51c8877 488 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
bogdanm 84:0b3ab51c8877 489 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
bogdanm 84:0b3ab51c8877 490
bogdanm 84:0b3ab51c8877 491 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
bogdanm 84:0b3ab51c8877 492 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
bogdanm 84:0b3ab51c8877 493
bogdanm 84:0b3ab51c8877 494 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
bogdanm 84:0b3ab51c8877 495 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
bogdanm 84:0b3ab51c8877 496
bogdanm 84:0b3ab51c8877 497 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
bogdanm 84:0b3ab51c8877 498 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
bogdanm 84:0b3ab51c8877 499
bogdanm 84:0b3ab51c8877 500 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
bogdanm 84:0b3ab51c8877 501 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
bogdanm 84:0b3ab51c8877 502
bogdanm 84:0b3ab51c8877 503 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
bogdanm 84:0b3ab51c8877 504 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
bogdanm 84:0b3ab51c8877 505
bogdanm 84:0b3ab51c8877 506 /* SCB Configurable Fault Status Registers Definitions */
bogdanm 84:0b3ab51c8877 507 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
bogdanm 84:0b3ab51c8877 508 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
bogdanm 84:0b3ab51c8877 509
bogdanm 84:0b3ab51c8877 510 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
bogdanm 84:0b3ab51c8877 511 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
bogdanm 84:0b3ab51c8877 512
bogdanm 84:0b3ab51c8877 513 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
bogdanm 84:0b3ab51c8877 514 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
bogdanm 84:0b3ab51c8877 515
bogdanm 84:0b3ab51c8877 516 /* SCB Hard Fault Status Registers Definitions */
bogdanm 84:0b3ab51c8877 517 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
bogdanm 84:0b3ab51c8877 518 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
bogdanm 84:0b3ab51c8877 519
bogdanm 84:0b3ab51c8877 520 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
bogdanm 84:0b3ab51c8877 521 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
bogdanm 84:0b3ab51c8877 522
bogdanm 84:0b3ab51c8877 523 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
bogdanm 84:0b3ab51c8877 524 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
bogdanm 84:0b3ab51c8877 525
bogdanm 84:0b3ab51c8877 526 /* SCB Debug Fault Status Register Definitions */
bogdanm 84:0b3ab51c8877 527 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
bogdanm 84:0b3ab51c8877 528 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
bogdanm 84:0b3ab51c8877 529
bogdanm 84:0b3ab51c8877 530 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
bogdanm 84:0b3ab51c8877 531 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
bogdanm 84:0b3ab51c8877 532
bogdanm 84:0b3ab51c8877 533 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
bogdanm 84:0b3ab51c8877 534 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
bogdanm 84:0b3ab51c8877 535
bogdanm 84:0b3ab51c8877 536 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
bogdanm 84:0b3ab51c8877 537 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
bogdanm 84:0b3ab51c8877 538
bogdanm 84:0b3ab51c8877 539 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
bogdanm 84:0b3ab51c8877 540 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
bogdanm 84:0b3ab51c8877 541
bogdanm 84:0b3ab51c8877 542 /*@} end of group CMSIS_SCB */
bogdanm 84:0b3ab51c8877 543
bogdanm 84:0b3ab51c8877 544
bogdanm 84:0b3ab51c8877 545 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 546 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
bogdanm 84:0b3ab51c8877 547 \brief Type definitions for the System Control and ID Register not in the SCB
bogdanm 84:0b3ab51c8877 548 @{
bogdanm 84:0b3ab51c8877 549 */
bogdanm 84:0b3ab51c8877 550
bogdanm 84:0b3ab51c8877 551 /** \brief Structure type to access the System Control and ID Register not in the SCB.
bogdanm 84:0b3ab51c8877 552 */
bogdanm 84:0b3ab51c8877 553 typedef struct
bogdanm 84:0b3ab51c8877 554 {
bogdanm 84:0b3ab51c8877 555 uint32_t RESERVED0[1];
bogdanm 84:0b3ab51c8877 556 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
bogdanm 84:0b3ab51c8877 557 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
bogdanm 84:0b3ab51c8877 558 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
bogdanm 84:0b3ab51c8877 559 #else
bogdanm 84:0b3ab51c8877 560 uint32_t RESERVED1[1];
bogdanm 84:0b3ab51c8877 561 #endif
bogdanm 84:0b3ab51c8877 562 } SCnSCB_Type;
bogdanm 84:0b3ab51c8877 563
bogdanm 84:0b3ab51c8877 564 /* Interrupt Controller Type Register Definitions */
bogdanm 84:0b3ab51c8877 565 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
bogdanm 84:0b3ab51c8877 566 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
bogdanm 84:0b3ab51c8877 567
bogdanm 84:0b3ab51c8877 568 /* Auxiliary Control Register Definitions */
bogdanm 84:0b3ab51c8877 569
bogdanm 84:0b3ab51c8877 570 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
bogdanm 84:0b3ab51c8877 571 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
bogdanm 84:0b3ab51c8877 572
bogdanm 84:0b3ab51c8877 573 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
bogdanm 84:0b3ab51c8877 574 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
bogdanm 84:0b3ab51c8877 575
bogdanm 84:0b3ab51c8877 576 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
bogdanm 84:0b3ab51c8877 577 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
bogdanm 84:0b3ab51c8877 578
bogdanm 84:0b3ab51c8877 579 /*@} end of group CMSIS_SCnotSCB */
bogdanm 84:0b3ab51c8877 580
bogdanm 84:0b3ab51c8877 581
bogdanm 84:0b3ab51c8877 582 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 583 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 84:0b3ab51c8877 584 \brief Type definitions for the System Timer Registers.
bogdanm 84:0b3ab51c8877 585 @{
bogdanm 84:0b3ab51c8877 586 */
bogdanm 84:0b3ab51c8877 587
bogdanm 84:0b3ab51c8877 588 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 84:0b3ab51c8877 589 */
bogdanm 84:0b3ab51c8877 590 typedef struct
bogdanm 84:0b3ab51c8877 591 {
bogdanm 84:0b3ab51c8877 592 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 84:0b3ab51c8877 593 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 84:0b3ab51c8877 594 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 84:0b3ab51c8877 595 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 84:0b3ab51c8877 596 } SysTick_Type;
bogdanm 84:0b3ab51c8877 597
bogdanm 84:0b3ab51c8877 598 /* SysTick Control / Status Register Definitions */
bogdanm 84:0b3ab51c8877 599 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 84:0b3ab51c8877 600 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 84:0b3ab51c8877 601
bogdanm 84:0b3ab51c8877 602 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 84:0b3ab51c8877 603 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 84:0b3ab51c8877 604
bogdanm 84:0b3ab51c8877 605 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 84:0b3ab51c8877 606 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 84:0b3ab51c8877 607
bogdanm 84:0b3ab51c8877 608 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
bogdanm 84:0b3ab51c8877 609 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 84:0b3ab51c8877 610
bogdanm 84:0b3ab51c8877 611 /* SysTick Reload Register Definitions */
bogdanm 84:0b3ab51c8877 612 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
bogdanm 84:0b3ab51c8877 613 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 84:0b3ab51c8877 614
bogdanm 84:0b3ab51c8877 615 /* SysTick Current Register Definitions */
bogdanm 84:0b3ab51c8877 616 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
bogdanm 84:0b3ab51c8877 617 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
bogdanm 84:0b3ab51c8877 618
bogdanm 84:0b3ab51c8877 619 /* SysTick Calibration Register Definitions */
bogdanm 84:0b3ab51c8877 620 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 84:0b3ab51c8877 621 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 84:0b3ab51c8877 622
bogdanm 84:0b3ab51c8877 623 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 84:0b3ab51c8877 624 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 84:0b3ab51c8877 625
bogdanm 84:0b3ab51c8877 626 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
bogdanm 84:0b3ab51c8877 627 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
bogdanm 84:0b3ab51c8877 628
bogdanm 84:0b3ab51c8877 629 /*@} end of group CMSIS_SysTick */
bogdanm 84:0b3ab51c8877 630
bogdanm 84:0b3ab51c8877 631
bogdanm 84:0b3ab51c8877 632 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 633 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
bogdanm 84:0b3ab51c8877 634 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
bogdanm 84:0b3ab51c8877 635 @{
bogdanm 84:0b3ab51c8877 636 */
bogdanm 84:0b3ab51c8877 637
bogdanm 84:0b3ab51c8877 638 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
bogdanm 84:0b3ab51c8877 639 */
bogdanm 84:0b3ab51c8877 640 typedef struct
bogdanm 84:0b3ab51c8877 641 {
bogdanm 84:0b3ab51c8877 642 __O union
bogdanm 84:0b3ab51c8877 643 {
bogdanm 84:0b3ab51c8877 644 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
bogdanm 84:0b3ab51c8877 645 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
bogdanm 84:0b3ab51c8877 646 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
bogdanm 84:0b3ab51c8877 647 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
bogdanm 84:0b3ab51c8877 648 uint32_t RESERVED0[864];
bogdanm 84:0b3ab51c8877 649 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
bogdanm 84:0b3ab51c8877 650 uint32_t RESERVED1[15];
bogdanm 84:0b3ab51c8877 651 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
bogdanm 84:0b3ab51c8877 652 uint32_t RESERVED2[15];
bogdanm 84:0b3ab51c8877 653 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
bogdanm 84:0b3ab51c8877 654 uint32_t RESERVED3[29];
bogdanm 84:0b3ab51c8877 655 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
bogdanm 84:0b3ab51c8877 656 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
bogdanm 84:0b3ab51c8877 657 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
bogdanm 84:0b3ab51c8877 658 uint32_t RESERVED4[43];
bogdanm 84:0b3ab51c8877 659 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
bogdanm 84:0b3ab51c8877 660 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
bogdanm 84:0b3ab51c8877 661 uint32_t RESERVED5[6];
bogdanm 84:0b3ab51c8877 662 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
bogdanm 84:0b3ab51c8877 663 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
bogdanm 84:0b3ab51c8877 664 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
bogdanm 84:0b3ab51c8877 665 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
bogdanm 84:0b3ab51c8877 666 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
bogdanm 84:0b3ab51c8877 667 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
bogdanm 84:0b3ab51c8877 668 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
bogdanm 84:0b3ab51c8877 669 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
bogdanm 84:0b3ab51c8877 670 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
bogdanm 84:0b3ab51c8877 671 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
bogdanm 84:0b3ab51c8877 672 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
bogdanm 84:0b3ab51c8877 673 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
bogdanm 84:0b3ab51c8877 674 } ITM_Type;
bogdanm 84:0b3ab51c8877 675
bogdanm 84:0b3ab51c8877 676 /* ITM Trace Privilege Register Definitions */
bogdanm 84:0b3ab51c8877 677 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
bogdanm 84:0b3ab51c8877 678 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
bogdanm 84:0b3ab51c8877 679
bogdanm 84:0b3ab51c8877 680 /* ITM Trace Control Register Definitions */
bogdanm 84:0b3ab51c8877 681 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
bogdanm 84:0b3ab51c8877 682 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
bogdanm 84:0b3ab51c8877 683
bogdanm 84:0b3ab51c8877 684 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
bogdanm 84:0b3ab51c8877 685 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
bogdanm 84:0b3ab51c8877 686
bogdanm 84:0b3ab51c8877 687 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
bogdanm 84:0b3ab51c8877 688 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
bogdanm 84:0b3ab51c8877 689
bogdanm 84:0b3ab51c8877 690 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
bogdanm 84:0b3ab51c8877 691 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
bogdanm 84:0b3ab51c8877 692
bogdanm 84:0b3ab51c8877 693 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
bogdanm 84:0b3ab51c8877 694 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
bogdanm 84:0b3ab51c8877 695
bogdanm 84:0b3ab51c8877 696 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
bogdanm 84:0b3ab51c8877 697 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
bogdanm 84:0b3ab51c8877 698
bogdanm 84:0b3ab51c8877 699 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
bogdanm 84:0b3ab51c8877 700 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
bogdanm 84:0b3ab51c8877 701
bogdanm 84:0b3ab51c8877 702 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
bogdanm 84:0b3ab51c8877 703 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
bogdanm 84:0b3ab51c8877 704
bogdanm 84:0b3ab51c8877 705 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
bogdanm 84:0b3ab51c8877 706 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
bogdanm 84:0b3ab51c8877 707
bogdanm 84:0b3ab51c8877 708 /* ITM Integration Write Register Definitions */
bogdanm 84:0b3ab51c8877 709 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
bogdanm 84:0b3ab51c8877 710 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
bogdanm 84:0b3ab51c8877 711
bogdanm 84:0b3ab51c8877 712 /* ITM Integration Read Register Definitions */
bogdanm 84:0b3ab51c8877 713 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
bogdanm 84:0b3ab51c8877 714 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
bogdanm 84:0b3ab51c8877 715
bogdanm 84:0b3ab51c8877 716 /* ITM Integration Mode Control Register Definitions */
bogdanm 84:0b3ab51c8877 717 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
bogdanm 84:0b3ab51c8877 718 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
bogdanm 84:0b3ab51c8877 719
bogdanm 84:0b3ab51c8877 720 /* ITM Lock Status Register Definitions */
bogdanm 84:0b3ab51c8877 721 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
bogdanm 84:0b3ab51c8877 722 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
bogdanm 84:0b3ab51c8877 723
bogdanm 84:0b3ab51c8877 724 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
bogdanm 84:0b3ab51c8877 725 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
bogdanm 84:0b3ab51c8877 726
bogdanm 84:0b3ab51c8877 727 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
bogdanm 84:0b3ab51c8877 728 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
bogdanm 84:0b3ab51c8877 729
bogdanm 84:0b3ab51c8877 730 /*@}*/ /* end of group CMSIS_ITM */
bogdanm 84:0b3ab51c8877 731
bogdanm 84:0b3ab51c8877 732
bogdanm 84:0b3ab51c8877 733 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 734 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
bogdanm 84:0b3ab51c8877 735 \brief Type definitions for the Data Watchpoint and Trace (DWT)
bogdanm 84:0b3ab51c8877 736 @{
bogdanm 84:0b3ab51c8877 737 */
bogdanm 84:0b3ab51c8877 738
bogdanm 84:0b3ab51c8877 739 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
bogdanm 84:0b3ab51c8877 740 */
bogdanm 84:0b3ab51c8877 741 typedef struct
bogdanm 84:0b3ab51c8877 742 {
bogdanm 84:0b3ab51c8877 743 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
bogdanm 84:0b3ab51c8877 744 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
bogdanm 84:0b3ab51c8877 745 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
bogdanm 84:0b3ab51c8877 746 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
bogdanm 84:0b3ab51c8877 747 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
bogdanm 84:0b3ab51c8877 748 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
bogdanm 84:0b3ab51c8877 749 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
bogdanm 84:0b3ab51c8877 750 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
bogdanm 84:0b3ab51c8877 751 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
bogdanm 84:0b3ab51c8877 752 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
bogdanm 84:0b3ab51c8877 753 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
bogdanm 84:0b3ab51c8877 754 uint32_t RESERVED0[1];
bogdanm 84:0b3ab51c8877 755 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
bogdanm 84:0b3ab51c8877 756 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
bogdanm 84:0b3ab51c8877 757 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
bogdanm 84:0b3ab51c8877 758 uint32_t RESERVED1[1];
bogdanm 84:0b3ab51c8877 759 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
bogdanm 84:0b3ab51c8877 760 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
bogdanm 84:0b3ab51c8877 761 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
bogdanm 84:0b3ab51c8877 762 uint32_t RESERVED2[1];
bogdanm 84:0b3ab51c8877 763 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
bogdanm 84:0b3ab51c8877 764 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
bogdanm 84:0b3ab51c8877 765 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
bogdanm 84:0b3ab51c8877 766 } DWT_Type;
bogdanm 84:0b3ab51c8877 767
bogdanm 84:0b3ab51c8877 768 /* DWT Control Register Definitions */
bogdanm 84:0b3ab51c8877 769 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
bogdanm 84:0b3ab51c8877 770 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
bogdanm 84:0b3ab51c8877 771
bogdanm 84:0b3ab51c8877 772 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
bogdanm 84:0b3ab51c8877 773 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
bogdanm 84:0b3ab51c8877 774
bogdanm 84:0b3ab51c8877 775 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
bogdanm 84:0b3ab51c8877 776 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
bogdanm 84:0b3ab51c8877 777
bogdanm 84:0b3ab51c8877 778 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
bogdanm 84:0b3ab51c8877 779 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
bogdanm 84:0b3ab51c8877 780
bogdanm 84:0b3ab51c8877 781 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
bogdanm 84:0b3ab51c8877 782 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
bogdanm 84:0b3ab51c8877 783
bogdanm 84:0b3ab51c8877 784 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
bogdanm 84:0b3ab51c8877 785 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
bogdanm 84:0b3ab51c8877 786
bogdanm 84:0b3ab51c8877 787 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
bogdanm 84:0b3ab51c8877 788 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
bogdanm 84:0b3ab51c8877 789
bogdanm 84:0b3ab51c8877 790 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
bogdanm 84:0b3ab51c8877 791 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
bogdanm 84:0b3ab51c8877 792
bogdanm 84:0b3ab51c8877 793 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
bogdanm 84:0b3ab51c8877 794 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
bogdanm 84:0b3ab51c8877 795
bogdanm 84:0b3ab51c8877 796 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
bogdanm 84:0b3ab51c8877 797 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
bogdanm 84:0b3ab51c8877 798
bogdanm 84:0b3ab51c8877 799 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
bogdanm 84:0b3ab51c8877 800 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
bogdanm 84:0b3ab51c8877 801
bogdanm 84:0b3ab51c8877 802 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
bogdanm 84:0b3ab51c8877 803 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
bogdanm 84:0b3ab51c8877 804
bogdanm 84:0b3ab51c8877 805 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
bogdanm 84:0b3ab51c8877 806 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
bogdanm 84:0b3ab51c8877 807
bogdanm 84:0b3ab51c8877 808 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
bogdanm 84:0b3ab51c8877 809 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
bogdanm 84:0b3ab51c8877 810
bogdanm 84:0b3ab51c8877 811 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
bogdanm 84:0b3ab51c8877 812 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
bogdanm 84:0b3ab51c8877 813
bogdanm 84:0b3ab51c8877 814 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
bogdanm 84:0b3ab51c8877 815 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
bogdanm 84:0b3ab51c8877 816
bogdanm 84:0b3ab51c8877 817 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
bogdanm 84:0b3ab51c8877 818 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
bogdanm 84:0b3ab51c8877 819
bogdanm 84:0b3ab51c8877 820 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
bogdanm 84:0b3ab51c8877 821 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
bogdanm 84:0b3ab51c8877 822
bogdanm 84:0b3ab51c8877 823 /* DWT CPI Count Register Definitions */
bogdanm 84:0b3ab51c8877 824 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
bogdanm 84:0b3ab51c8877 825 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
bogdanm 84:0b3ab51c8877 826
bogdanm 84:0b3ab51c8877 827 /* DWT Exception Overhead Count Register Definitions */
bogdanm 84:0b3ab51c8877 828 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
bogdanm 84:0b3ab51c8877 829 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
bogdanm 84:0b3ab51c8877 830
bogdanm 84:0b3ab51c8877 831 /* DWT Sleep Count Register Definitions */
bogdanm 84:0b3ab51c8877 832 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
bogdanm 84:0b3ab51c8877 833 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
bogdanm 84:0b3ab51c8877 834
bogdanm 84:0b3ab51c8877 835 /* DWT LSU Count Register Definitions */
bogdanm 84:0b3ab51c8877 836 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
bogdanm 84:0b3ab51c8877 837 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
bogdanm 84:0b3ab51c8877 838
bogdanm 84:0b3ab51c8877 839 /* DWT Folded-instruction Count Register Definitions */
bogdanm 84:0b3ab51c8877 840 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
bogdanm 84:0b3ab51c8877 841 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
bogdanm 84:0b3ab51c8877 842
bogdanm 84:0b3ab51c8877 843 /* DWT Comparator Mask Register Definitions */
bogdanm 84:0b3ab51c8877 844 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
bogdanm 84:0b3ab51c8877 845 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
bogdanm 84:0b3ab51c8877 846
bogdanm 84:0b3ab51c8877 847 /* DWT Comparator Function Register Definitions */
bogdanm 84:0b3ab51c8877 848 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
bogdanm 84:0b3ab51c8877 849 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
bogdanm 84:0b3ab51c8877 850
bogdanm 84:0b3ab51c8877 851 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
bogdanm 84:0b3ab51c8877 852 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
bogdanm 84:0b3ab51c8877 853
bogdanm 84:0b3ab51c8877 854 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
bogdanm 84:0b3ab51c8877 855 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
bogdanm 84:0b3ab51c8877 856
bogdanm 84:0b3ab51c8877 857 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
bogdanm 84:0b3ab51c8877 858 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
bogdanm 84:0b3ab51c8877 859
bogdanm 84:0b3ab51c8877 860 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
bogdanm 84:0b3ab51c8877 861 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
bogdanm 84:0b3ab51c8877 862
bogdanm 84:0b3ab51c8877 863 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
bogdanm 84:0b3ab51c8877 864 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
bogdanm 84:0b3ab51c8877 865
bogdanm 84:0b3ab51c8877 866 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
bogdanm 84:0b3ab51c8877 867 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
bogdanm 84:0b3ab51c8877 868
bogdanm 84:0b3ab51c8877 869 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
bogdanm 84:0b3ab51c8877 870 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
bogdanm 84:0b3ab51c8877 871
bogdanm 84:0b3ab51c8877 872 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
bogdanm 84:0b3ab51c8877 873 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
bogdanm 84:0b3ab51c8877 874
bogdanm 84:0b3ab51c8877 875 /*@}*/ /* end of group CMSIS_DWT */
bogdanm 84:0b3ab51c8877 876
bogdanm 84:0b3ab51c8877 877
bogdanm 84:0b3ab51c8877 878 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 879 \defgroup CMSIS_TPI Trace Port Interface (TPI)
bogdanm 84:0b3ab51c8877 880 \brief Type definitions for the Trace Port Interface (TPI)
bogdanm 84:0b3ab51c8877 881 @{
bogdanm 84:0b3ab51c8877 882 */
bogdanm 84:0b3ab51c8877 883
bogdanm 84:0b3ab51c8877 884 /** \brief Structure type to access the Trace Port Interface Register (TPI).
bogdanm 84:0b3ab51c8877 885 */
bogdanm 84:0b3ab51c8877 886 typedef struct
bogdanm 84:0b3ab51c8877 887 {
bogdanm 84:0b3ab51c8877 888 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
bogdanm 84:0b3ab51c8877 889 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
bogdanm 84:0b3ab51c8877 890 uint32_t RESERVED0[2];
bogdanm 84:0b3ab51c8877 891 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
bogdanm 84:0b3ab51c8877 892 uint32_t RESERVED1[55];
bogdanm 84:0b3ab51c8877 893 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
bogdanm 84:0b3ab51c8877 894 uint32_t RESERVED2[131];
bogdanm 84:0b3ab51c8877 895 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
bogdanm 84:0b3ab51c8877 896 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
bogdanm 84:0b3ab51c8877 897 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
bogdanm 84:0b3ab51c8877 898 uint32_t RESERVED3[759];
bogdanm 84:0b3ab51c8877 899 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
bogdanm 84:0b3ab51c8877 900 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
bogdanm 84:0b3ab51c8877 901 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
bogdanm 84:0b3ab51c8877 902 uint32_t RESERVED4[1];
bogdanm 84:0b3ab51c8877 903 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
bogdanm 84:0b3ab51c8877 904 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
bogdanm 84:0b3ab51c8877 905 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
bogdanm 84:0b3ab51c8877 906 uint32_t RESERVED5[39];
bogdanm 84:0b3ab51c8877 907 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
bogdanm 84:0b3ab51c8877 908 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
bogdanm 84:0b3ab51c8877 909 uint32_t RESERVED7[8];
bogdanm 84:0b3ab51c8877 910 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
bogdanm 84:0b3ab51c8877 911 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
bogdanm 84:0b3ab51c8877 912 } TPI_Type;
bogdanm 84:0b3ab51c8877 913
bogdanm 84:0b3ab51c8877 914 /* TPI Asynchronous Clock Prescaler Register Definitions */
bogdanm 84:0b3ab51c8877 915 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
bogdanm 84:0b3ab51c8877 916 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
bogdanm 84:0b3ab51c8877 917
bogdanm 84:0b3ab51c8877 918 /* TPI Selected Pin Protocol Register Definitions */
bogdanm 84:0b3ab51c8877 919 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
bogdanm 84:0b3ab51c8877 920 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
bogdanm 84:0b3ab51c8877 921
bogdanm 84:0b3ab51c8877 922 /* TPI Formatter and Flush Status Register Definitions */
bogdanm 84:0b3ab51c8877 923 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
bogdanm 84:0b3ab51c8877 924 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
bogdanm 84:0b3ab51c8877 925
bogdanm 84:0b3ab51c8877 926 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
bogdanm 84:0b3ab51c8877 927 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
bogdanm 84:0b3ab51c8877 928
bogdanm 84:0b3ab51c8877 929 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
bogdanm 84:0b3ab51c8877 930 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
bogdanm 84:0b3ab51c8877 931
bogdanm 84:0b3ab51c8877 932 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
bogdanm 84:0b3ab51c8877 933 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
bogdanm 84:0b3ab51c8877 934
bogdanm 84:0b3ab51c8877 935 /* TPI Formatter and Flush Control Register Definitions */
bogdanm 84:0b3ab51c8877 936 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
bogdanm 84:0b3ab51c8877 937 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
bogdanm 84:0b3ab51c8877 938
bogdanm 84:0b3ab51c8877 939 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
bogdanm 84:0b3ab51c8877 940 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
bogdanm 84:0b3ab51c8877 941
bogdanm 84:0b3ab51c8877 942 /* TPI TRIGGER Register Definitions */
bogdanm 84:0b3ab51c8877 943 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
bogdanm 84:0b3ab51c8877 944 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
bogdanm 84:0b3ab51c8877 945
bogdanm 84:0b3ab51c8877 946 /* TPI Integration ETM Data Register Definitions (FIFO0) */
bogdanm 84:0b3ab51c8877 947 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
bogdanm 84:0b3ab51c8877 948 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
bogdanm 84:0b3ab51c8877 949
bogdanm 84:0b3ab51c8877 950 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
bogdanm 84:0b3ab51c8877 951 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
bogdanm 84:0b3ab51c8877 952
bogdanm 84:0b3ab51c8877 953 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
bogdanm 84:0b3ab51c8877 954 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
bogdanm 84:0b3ab51c8877 955
bogdanm 84:0b3ab51c8877 956 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
bogdanm 84:0b3ab51c8877 957 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
bogdanm 84:0b3ab51c8877 958
bogdanm 84:0b3ab51c8877 959 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
bogdanm 84:0b3ab51c8877 960 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
bogdanm 84:0b3ab51c8877 961
bogdanm 84:0b3ab51c8877 962 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
bogdanm 84:0b3ab51c8877 963 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
bogdanm 84:0b3ab51c8877 964
bogdanm 84:0b3ab51c8877 965 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
bogdanm 84:0b3ab51c8877 966 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
bogdanm 84:0b3ab51c8877 967
bogdanm 84:0b3ab51c8877 968 /* TPI ITATBCTR2 Register Definitions */
bogdanm 84:0b3ab51c8877 969 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
bogdanm 84:0b3ab51c8877 970 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
bogdanm 84:0b3ab51c8877 971
bogdanm 84:0b3ab51c8877 972 /* TPI Integration ITM Data Register Definitions (FIFO1) */
bogdanm 84:0b3ab51c8877 973 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
bogdanm 84:0b3ab51c8877 974 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
bogdanm 84:0b3ab51c8877 975
bogdanm 84:0b3ab51c8877 976 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
bogdanm 84:0b3ab51c8877 977 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
bogdanm 84:0b3ab51c8877 978
bogdanm 84:0b3ab51c8877 979 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
bogdanm 84:0b3ab51c8877 980 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
bogdanm 84:0b3ab51c8877 981
bogdanm 84:0b3ab51c8877 982 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
bogdanm 84:0b3ab51c8877 983 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
bogdanm 84:0b3ab51c8877 984
bogdanm 84:0b3ab51c8877 985 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
bogdanm 84:0b3ab51c8877 986 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
bogdanm 84:0b3ab51c8877 987
bogdanm 84:0b3ab51c8877 988 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
bogdanm 84:0b3ab51c8877 989 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
bogdanm 84:0b3ab51c8877 990
bogdanm 84:0b3ab51c8877 991 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
bogdanm 84:0b3ab51c8877 992 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
bogdanm 84:0b3ab51c8877 993
bogdanm 84:0b3ab51c8877 994 /* TPI ITATBCTR0 Register Definitions */
bogdanm 84:0b3ab51c8877 995 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
bogdanm 84:0b3ab51c8877 996 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
bogdanm 84:0b3ab51c8877 997
bogdanm 84:0b3ab51c8877 998 /* TPI Integration Mode Control Register Definitions */
bogdanm 84:0b3ab51c8877 999 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
bogdanm 84:0b3ab51c8877 1000 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
bogdanm 84:0b3ab51c8877 1001
bogdanm 84:0b3ab51c8877 1002 /* TPI DEVID Register Definitions */
bogdanm 84:0b3ab51c8877 1003 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
bogdanm 84:0b3ab51c8877 1004 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
bogdanm 84:0b3ab51c8877 1005
bogdanm 84:0b3ab51c8877 1006 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
bogdanm 84:0b3ab51c8877 1007 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
bogdanm 84:0b3ab51c8877 1008
bogdanm 84:0b3ab51c8877 1009 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
bogdanm 84:0b3ab51c8877 1010 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
bogdanm 84:0b3ab51c8877 1011
bogdanm 84:0b3ab51c8877 1012 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
bogdanm 84:0b3ab51c8877 1013 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
bogdanm 84:0b3ab51c8877 1014
bogdanm 84:0b3ab51c8877 1015 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
bogdanm 84:0b3ab51c8877 1016 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
bogdanm 84:0b3ab51c8877 1017
bogdanm 84:0b3ab51c8877 1018 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
bogdanm 84:0b3ab51c8877 1019 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
bogdanm 84:0b3ab51c8877 1020
bogdanm 84:0b3ab51c8877 1021 /* TPI DEVTYPE Register Definitions */
bogdanm 84:0b3ab51c8877 1022 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
bogdanm 84:0b3ab51c8877 1023 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
bogdanm 84:0b3ab51c8877 1024
bogdanm 84:0b3ab51c8877 1025 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
bogdanm 84:0b3ab51c8877 1026 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
bogdanm 84:0b3ab51c8877 1027
bogdanm 84:0b3ab51c8877 1028 /*@}*/ /* end of group CMSIS_TPI */
bogdanm 84:0b3ab51c8877 1029
bogdanm 84:0b3ab51c8877 1030
bogdanm 84:0b3ab51c8877 1031 #if (__MPU_PRESENT == 1)
bogdanm 84:0b3ab51c8877 1032 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 1033 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 84:0b3ab51c8877 1034 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 84:0b3ab51c8877 1035 @{
bogdanm 84:0b3ab51c8877 1036 */
bogdanm 84:0b3ab51c8877 1037
bogdanm 84:0b3ab51c8877 1038 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 84:0b3ab51c8877 1039 */
bogdanm 84:0b3ab51c8877 1040 typedef struct
bogdanm 84:0b3ab51c8877 1041 {
bogdanm 84:0b3ab51c8877 1042 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 84:0b3ab51c8877 1043 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 84:0b3ab51c8877 1044 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 84:0b3ab51c8877 1045 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 84:0b3ab51c8877 1046 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 84:0b3ab51c8877 1047 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
bogdanm 84:0b3ab51c8877 1048 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
bogdanm 84:0b3ab51c8877 1049 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
bogdanm 84:0b3ab51c8877 1050 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
bogdanm 84:0b3ab51c8877 1051 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
bogdanm 84:0b3ab51c8877 1052 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
bogdanm 84:0b3ab51c8877 1053 } MPU_Type;
bogdanm 84:0b3ab51c8877 1054
bogdanm 84:0b3ab51c8877 1055 /* MPU Type Register */
bogdanm 84:0b3ab51c8877 1056 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 84:0b3ab51c8877 1057 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 84:0b3ab51c8877 1058
bogdanm 84:0b3ab51c8877 1059 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 84:0b3ab51c8877 1060 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 84:0b3ab51c8877 1061
bogdanm 84:0b3ab51c8877 1062 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
bogdanm 84:0b3ab51c8877 1063 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 84:0b3ab51c8877 1064
bogdanm 84:0b3ab51c8877 1065 /* MPU Control Register */
bogdanm 84:0b3ab51c8877 1066 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 84:0b3ab51c8877 1067 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 84:0b3ab51c8877 1068
bogdanm 84:0b3ab51c8877 1069 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 84:0b3ab51c8877 1070 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 84:0b3ab51c8877 1071
bogdanm 84:0b3ab51c8877 1072 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
bogdanm 84:0b3ab51c8877 1073 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
bogdanm 84:0b3ab51c8877 1074
bogdanm 84:0b3ab51c8877 1075 /* MPU Region Number Register */
bogdanm 84:0b3ab51c8877 1076 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
bogdanm 84:0b3ab51c8877 1077 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
bogdanm 84:0b3ab51c8877 1078
bogdanm 84:0b3ab51c8877 1079 /* MPU Region Base Address Register */
bogdanm 84:0b3ab51c8877 1080 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
bogdanm 84:0b3ab51c8877 1081 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 84:0b3ab51c8877 1082
bogdanm 84:0b3ab51c8877 1083 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 84:0b3ab51c8877 1084 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 84:0b3ab51c8877 1085
bogdanm 84:0b3ab51c8877 1086 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
bogdanm 84:0b3ab51c8877 1087 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
bogdanm 84:0b3ab51c8877 1088
bogdanm 84:0b3ab51c8877 1089 /* MPU Region Attribute and Size Register */
bogdanm 84:0b3ab51c8877 1090 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 84:0b3ab51c8877 1091 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 84:0b3ab51c8877 1092
bogdanm 84:0b3ab51c8877 1093 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 84:0b3ab51c8877 1094 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 84:0b3ab51c8877 1095
bogdanm 84:0b3ab51c8877 1096 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 84:0b3ab51c8877 1097 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 84:0b3ab51c8877 1098
bogdanm 84:0b3ab51c8877 1099 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 84:0b3ab51c8877 1100 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 84:0b3ab51c8877 1101
bogdanm 84:0b3ab51c8877 1102 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 84:0b3ab51c8877 1103 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 84:0b3ab51c8877 1104
bogdanm 84:0b3ab51c8877 1105 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 84:0b3ab51c8877 1106 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 84:0b3ab51c8877 1107
bogdanm 84:0b3ab51c8877 1108 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 84:0b3ab51c8877 1109 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 84:0b3ab51c8877 1110
bogdanm 84:0b3ab51c8877 1111 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 84:0b3ab51c8877 1112 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 84:0b3ab51c8877 1113
bogdanm 84:0b3ab51c8877 1114 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 84:0b3ab51c8877 1115 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 84:0b3ab51c8877 1116
bogdanm 84:0b3ab51c8877 1117 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
bogdanm 84:0b3ab51c8877 1118 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 84:0b3ab51c8877 1119
bogdanm 84:0b3ab51c8877 1120 /*@} end of group CMSIS_MPU */
bogdanm 84:0b3ab51c8877 1121 #endif
bogdanm 84:0b3ab51c8877 1122
bogdanm 84:0b3ab51c8877 1123
bogdanm 84:0b3ab51c8877 1124 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 1125 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 84:0b3ab51c8877 1126 \brief Type definitions for the Core Debug Registers
bogdanm 84:0b3ab51c8877 1127 @{
bogdanm 84:0b3ab51c8877 1128 */
bogdanm 84:0b3ab51c8877 1129
bogdanm 84:0b3ab51c8877 1130 /** \brief Structure type to access the Core Debug Register (CoreDebug).
bogdanm 84:0b3ab51c8877 1131 */
bogdanm 84:0b3ab51c8877 1132 typedef struct
bogdanm 84:0b3ab51c8877 1133 {
bogdanm 84:0b3ab51c8877 1134 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
bogdanm 84:0b3ab51c8877 1135 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
bogdanm 84:0b3ab51c8877 1136 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
bogdanm 84:0b3ab51c8877 1137 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
bogdanm 84:0b3ab51c8877 1138 } CoreDebug_Type;
bogdanm 84:0b3ab51c8877 1139
bogdanm 84:0b3ab51c8877 1140 /* Debug Halting Control and Status Register */
bogdanm 84:0b3ab51c8877 1141 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
bogdanm 84:0b3ab51c8877 1142 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
bogdanm 84:0b3ab51c8877 1143
bogdanm 84:0b3ab51c8877 1144 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
bogdanm 84:0b3ab51c8877 1145 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
bogdanm 84:0b3ab51c8877 1146
bogdanm 84:0b3ab51c8877 1147 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
bogdanm 84:0b3ab51c8877 1148 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
bogdanm 84:0b3ab51c8877 1149
bogdanm 84:0b3ab51c8877 1150 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
bogdanm 84:0b3ab51c8877 1151 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
bogdanm 84:0b3ab51c8877 1152
bogdanm 84:0b3ab51c8877 1153 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
bogdanm 84:0b3ab51c8877 1154 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
bogdanm 84:0b3ab51c8877 1155
bogdanm 84:0b3ab51c8877 1156 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
bogdanm 84:0b3ab51c8877 1157 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
bogdanm 84:0b3ab51c8877 1158
bogdanm 84:0b3ab51c8877 1159 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
bogdanm 84:0b3ab51c8877 1160 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
bogdanm 84:0b3ab51c8877 1161
bogdanm 84:0b3ab51c8877 1162 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
bogdanm 84:0b3ab51c8877 1163 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
bogdanm 84:0b3ab51c8877 1164
bogdanm 84:0b3ab51c8877 1165 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
bogdanm 84:0b3ab51c8877 1166 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
bogdanm 84:0b3ab51c8877 1167
bogdanm 84:0b3ab51c8877 1168 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
bogdanm 84:0b3ab51c8877 1169 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
bogdanm 84:0b3ab51c8877 1170
bogdanm 84:0b3ab51c8877 1171 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
bogdanm 84:0b3ab51c8877 1172 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
bogdanm 84:0b3ab51c8877 1173
bogdanm 84:0b3ab51c8877 1174 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
bogdanm 84:0b3ab51c8877 1175 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
bogdanm 84:0b3ab51c8877 1176
bogdanm 84:0b3ab51c8877 1177 /* Debug Core Register Selector Register */
bogdanm 84:0b3ab51c8877 1178 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
bogdanm 84:0b3ab51c8877 1179 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
bogdanm 84:0b3ab51c8877 1180
bogdanm 84:0b3ab51c8877 1181 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
bogdanm 84:0b3ab51c8877 1182 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
bogdanm 84:0b3ab51c8877 1183
bogdanm 84:0b3ab51c8877 1184 /* Debug Exception and Monitor Control Register */
bogdanm 84:0b3ab51c8877 1185 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
bogdanm 84:0b3ab51c8877 1186 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
bogdanm 84:0b3ab51c8877 1187
bogdanm 84:0b3ab51c8877 1188 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
bogdanm 84:0b3ab51c8877 1189 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
bogdanm 84:0b3ab51c8877 1190
bogdanm 84:0b3ab51c8877 1191 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
bogdanm 84:0b3ab51c8877 1192 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
bogdanm 84:0b3ab51c8877 1193
bogdanm 84:0b3ab51c8877 1194 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
bogdanm 84:0b3ab51c8877 1195 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
bogdanm 84:0b3ab51c8877 1196
bogdanm 84:0b3ab51c8877 1197 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
bogdanm 84:0b3ab51c8877 1198 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
bogdanm 84:0b3ab51c8877 1199
bogdanm 84:0b3ab51c8877 1200 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
bogdanm 84:0b3ab51c8877 1201 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
bogdanm 84:0b3ab51c8877 1202
bogdanm 84:0b3ab51c8877 1203 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
bogdanm 84:0b3ab51c8877 1204 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
bogdanm 84:0b3ab51c8877 1205
bogdanm 84:0b3ab51c8877 1206 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
bogdanm 84:0b3ab51c8877 1207 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
bogdanm 84:0b3ab51c8877 1208
bogdanm 84:0b3ab51c8877 1209 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
bogdanm 84:0b3ab51c8877 1210 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
bogdanm 84:0b3ab51c8877 1211
bogdanm 84:0b3ab51c8877 1212 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
bogdanm 84:0b3ab51c8877 1213 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
bogdanm 84:0b3ab51c8877 1214
bogdanm 84:0b3ab51c8877 1215 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
bogdanm 84:0b3ab51c8877 1216 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
bogdanm 84:0b3ab51c8877 1217
bogdanm 84:0b3ab51c8877 1218 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
bogdanm 84:0b3ab51c8877 1219 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
bogdanm 84:0b3ab51c8877 1220
bogdanm 84:0b3ab51c8877 1221 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
bogdanm 84:0b3ab51c8877 1222 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
bogdanm 84:0b3ab51c8877 1223
bogdanm 84:0b3ab51c8877 1224 /*@} end of group CMSIS_CoreDebug */
bogdanm 84:0b3ab51c8877 1225
bogdanm 84:0b3ab51c8877 1226
bogdanm 84:0b3ab51c8877 1227 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 1228 \defgroup CMSIS_core_base Core Definitions
bogdanm 84:0b3ab51c8877 1229 \brief Definitions for base addresses, unions, and structures.
bogdanm 84:0b3ab51c8877 1230 @{
bogdanm 84:0b3ab51c8877 1231 */
bogdanm 84:0b3ab51c8877 1232
bogdanm 84:0b3ab51c8877 1233 /* Memory mapping of Cortex-M3 Hardware */
bogdanm 84:0b3ab51c8877 1234 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 84:0b3ab51c8877 1235 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
bogdanm 84:0b3ab51c8877 1236 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
bogdanm 84:0b3ab51c8877 1237 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
bogdanm 84:0b3ab51c8877 1238 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
bogdanm 84:0b3ab51c8877 1239 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 84:0b3ab51c8877 1240 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 84:0b3ab51c8877 1241 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 84:0b3ab51c8877 1242
bogdanm 84:0b3ab51c8877 1243 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
bogdanm 84:0b3ab51c8877 1244 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 84:0b3ab51c8877 1245 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 84:0b3ab51c8877 1246 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 84:0b3ab51c8877 1247 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
bogdanm 84:0b3ab51c8877 1248 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
bogdanm 84:0b3ab51c8877 1249 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
bogdanm 84:0b3ab51c8877 1250 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
bogdanm 84:0b3ab51c8877 1251
bogdanm 84:0b3ab51c8877 1252 #if (__MPU_PRESENT == 1)
bogdanm 84:0b3ab51c8877 1253 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 84:0b3ab51c8877 1254 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 84:0b3ab51c8877 1255 #endif
bogdanm 84:0b3ab51c8877 1256
bogdanm 84:0b3ab51c8877 1257 /*@} */
bogdanm 84:0b3ab51c8877 1258
bogdanm 84:0b3ab51c8877 1259
bogdanm 84:0b3ab51c8877 1260
bogdanm 84:0b3ab51c8877 1261 /*******************************************************************************
bogdanm 84:0b3ab51c8877 1262 * Hardware Abstraction Layer
bogdanm 84:0b3ab51c8877 1263 Core Function Interface contains:
bogdanm 84:0b3ab51c8877 1264 - Core NVIC Functions
bogdanm 84:0b3ab51c8877 1265 - Core SysTick Functions
bogdanm 84:0b3ab51c8877 1266 - Core Debug Functions
bogdanm 84:0b3ab51c8877 1267 - Core Register Access Functions
bogdanm 84:0b3ab51c8877 1268 ******************************************************************************/
bogdanm 84:0b3ab51c8877 1269 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 84:0b3ab51c8877 1270 */
bogdanm 84:0b3ab51c8877 1271
bogdanm 84:0b3ab51c8877 1272
bogdanm 84:0b3ab51c8877 1273
bogdanm 84:0b3ab51c8877 1274 /* ########################## NVIC functions #################################### */
bogdanm 84:0b3ab51c8877 1275 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 84:0b3ab51c8877 1276 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 84:0b3ab51c8877 1277 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 84:0b3ab51c8877 1278 @{
bogdanm 84:0b3ab51c8877 1279 */
bogdanm 84:0b3ab51c8877 1280
bogdanm 84:0b3ab51c8877 1281 /** \brief Set Priority Grouping
bogdanm 84:0b3ab51c8877 1282
bogdanm 84:0b3ab51c8877 1283 The function sets the priority grouping field using the required unlock sequence.
bogdanm 84:0b3ab51c8877 1284 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
bogdanm 84:0b3ab51c8877 1285 Only values from 0..7 are used.
bogdanm 84:0b3ab51c8877 1286 In case of a conflict between priority grouping and available
bogdanm 84:0b3ab51c8877 1287 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
bogdanm 84:0b3ab51c8877 1288
bogdanm 84:0b3ab51c8877 1289 \param [in] PriorityGroup Priority grouping field.
bogdanm 84:0b3ab51c8877 1290 */
bogdanm 84:0b3ab51c8877 1291 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
bogdanm 84:0b3ab51c8877 1292 {
bogdanm 84:0b3ab51c8877 1293 uint32_t reg_value;
bogdanm 84:0b3ab51c8877 1294 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
bogdanm 84:0b3ab51c8877 1295
bogdanm 84:0b3ab51c8877 1296 reg_value = SCB->AIRCR; /* read old register configuration */
bogdanm 84:0b3ab51c8877 1297 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
bogdanm 84:0b3ab51c8877 1298 reg_value = (reg_value |
bogdanm 84:0b3ab51c8877 1299 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 84:0b3ab51c8877 1300 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
bogdanm 84:0b3ab51c8877 1301 SCB->AIRCR = reg_value;
bogdanm 84:0b3ab51c8877 1302 }
bogdanm 84:0b3ab51c8877 1303
bogdanm 84:0b3ab51c8877 1304
bogdanm 84:0b3ab51c8877 1305 /** \brief Get Priority Grouping
bogdanm 84:0b3ab51c8877 1306
bogdanm 84:0b3ab51c8877 1307 The function reads the priority grouping field from the NVIC Interrupt Controller.
bogdanm 84:0b3ab51c8877 1308
bogdanm 84:0b3ab51c8877 1309 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
bogdanm 84:0b3ab51c8877 1310 */
bogdanm 84:0b3ab51c8877 1311 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
bogdanm 84:0b3ab51c8877 1312 {
bogdanm 84:0b3ab51c8877 1313 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
bogdanm 84:0b3ab51c8877 1314 }
bogdanm 84:0b3ab51c8877 1315
bogdanm 84:0b3ab51c8877 1316
bogdanm 84:0b3ab51c8877 1317 /** \brief Enable External Interrupt
bogdanm 84:0b3ab51c8877 1318
bogdanm 84:0b3ab51c8877 1319 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 84:0b3ab51c8877 1320
bogdanm 84:0b3ab51c8877 1321 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 84:0b3ab51c8877 1322 */
bogdanm 84:0b3ab51c8877 1323 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 1324 {
bogdanm 84:0b3ab51c8877 1325 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
bogdanm 84:0b3ab51c8877 1326 }
bogdanm 84:0b3ab51c8877 1327
bogdanm 84:0b3ab51c8877 1328
bogdanm 84:0b3ab51c8877 1329 /** \brief Disable External Interrupt
bogdanm 84:0b3ab51c8877 1330
bogdanm 84:0b3ab51c8877 1331 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 84:0b3ab51c8877 1332
bogdanm 84:0b3ab51c8877 1333 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 84:0b3ab51c8877 1334 */
bogdanm 84:0b3ab51c8877 1335 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 1336 {
bogdanm 84:0b3ab51c8877 1337 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
bogdanm 84:0b3ab51c8877 1338 }
bogdanm 84:0b3ab51c8877 1339
bogdanm 84:0b3ab51c8877 1340
bogdanm 84:0b3ab51c8877 1341 /** \brief Get Pending Interrupt
bogdanm 84:0b3ab51c8877 1342
bogdanm 84:0b3ab51c8877 1343 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 84:0b3ab51c8877 1344 for the specified interrupt.
bogdanm 84:0b3ab51c8877 1345
bogdanm 84:0b3ab51c8877 1346 \param [in] IRQn Interrupt number.
bogdanm 84:0b3ab51c8877 1347
bogdanm 84:0b3ab51c8877 1348 \return 0 Interrupt status is not pending.
bogdanm 84:0b3ab51c8877 1349 \return 1 Interrupt status is pending.
bogdanm 84:0b3ab51c8877 1350 */
bogdanm 84:0b3ab51c8877 1351 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 1352 {
bogdanm 84:0b3ab51c8877 1353 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
bogdanm 84:0b3ab51c8877 1354 }
bogdanm 84:0b3ab51c8877 1355
bogdanm 84:0b3ab51c8877 1356
bogdanm 84:0b3ab51c8877 1357 /** \brief Set Pending Interrupt
bogdanm 84:0b3ab51c8877 1358
bogdanm 84:0b3ab51c8877 1359 The function sets the pending bit of an external interrupt.
bogdanm 84:0b3ab51c8877 1360
bogdanm 84:0b3ab51c8877 1361 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 84:0b3ab51c8877 1362 */
bogdanm 84:0b3ab51c8877 1363 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 1364 {
bogdanm 84:0b3ab51c8877 1365 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
bogdanm 84:0b3ab51c8877 1366 }
bogdanm 84:0b3ab51c8877 1367
bogdanm 84:0b3ab51c8877 1368
bogdanm 84:0b3ab51c8877 1369 /** \brief Clear Pending Interrupt
bogdanm 84:0b3ab51c8877 1370
bogdanm 84:0b3ab51c8877 1371 The function clears the pending bit of an external interrupt.
bogdanm 84:0b3ab51c8877 1372
bogdanm 84:0b3ab51c8877 1373 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 84:0b3ab51c8877 1374 */
bogdanm 84:0b3ab51c8877 1375 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 1376 {
bogdanm 84:0b3ab51c8877 1377 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
bogdanm 84:0b3ab51c8877 1378 }
bogdanm 84:0b3ab51c8877 1379
bogdanm 84:0b3ab51c8877 1380
bogdanm 84:0b3ab51c8877 1381 /** \brief Get Active Interrupt
bogdanm 84:0b3ab51c8877 1382
bogdanm 84:0b3ab51c8877 1383 The function reads the active register in NVIC and returns the active bit.
bogdanm 84:0b3ab51c8877 1384
bogdanm 84:0b3ab51c8877 1385 \param [in] IRQn Interrupt number.
bogdanm 84:0b3ab51c8877 1386
bogdanm 84:0b3ab51c8877 1387 \return 0 Interrupt status is not active.
bogdanm 84:0b3ab51c8877 1388 \return 1 Interrupt status is active.
bogdanm 84:0b3ab51c8877 1389 */
bogdanm 84:0b3ab51c8877 1390 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 1391 {
bogdanm 84:0b3ab51c8877 1392 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
bogdanm 84:0b3ab51c8877 1393 }
bogdanm 84:0b3ab51c8877 1394
bogdanm 84:0b3ab51c8877 1395
bogdanm 84:0b3ab51c8877 1396 /** \brief Set Interrupt Priority
bogdanm 84:0b3ab51c8877 1397
bogdanm 84:0b3ab51c8877 1398 The function sets the priority of an interrupt.
bogdanm 84:0b3ab51c8877 1399
bogdanm 84:0b3ab51c8877 1400 \note The priority cannot be set for every core interrupt.
bogdanm 84:0b3ab51c8877 1401
bogdanm 84:0b3ab51c8877 1402 \param [in] IRQn Interrupt number.
bogdanm 84:0b3ab51c8877 1403 \param [in] priority Priority to set.
bogdanm 84:0b3ab51c8877 1404 */
bogdanm 84:0b3ab51c8877 1405 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 84:0b3ab51c8877 1406 {
bogdanm 84:0b3ab51c8877 1407 if(IRQn < 0) {
bogdanm 84:0b3ab51c8877 1408 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
bogdanm 84:0b3ab51c8877 1409 else {
bogdanm 84:0b3ab51c8877 1410 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
bogdanm 84:0b3ab51c8877 1411 }
bogdanm 84:0b3ab51c8877 1412
bogdanm 84:0b3ab51c8877 1413
bogdanm 84:0b3ab51c8877 1414 /** \brief Get Interrupt Priority
bogdanm 84:0b3ab51c8877 1415
bogdanm 84:0b3ab51c8877 1416 The function reads the priority of an interrupt. The interrupt
bogdanm 84:0b3ab51c8877 1417 number can be positive to specify an external (device specific)
bogdanm 84:0b3ab51c8877 1418 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 84:0b3ab51c8877 1419
bogdanm 84:0b3ab51c8877 1420
bogdanm 84:0b3ab51c8877 1421 \param [in] IRQn Interrupt number.
bogdanm 84:0b3ab51c8877 1422 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 84:0b3ab51c8877 1423 priority bits of the microcontroller.
bogdanm 84:0b3ab51c8877 1424 */
bogdanm 84:0b3ab51c8877 1425 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 1426 {
bogdanm 84:0b3ab51c8877 1427
bogdanm 84:0b3ab51c8877 1428 if(IRQn < 0) {
bogdanm 84:0b3ab51c8877 1429 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
bogdanm 84:0b3ab51c8877 1430 else {
bogdanm 84:0b3ab51c8877 1431 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
bogdanm 84:0b3ab51c8877 1432 }
bogdanm 84:0b3ab51c8877 1433
bogdanm 84:0b3ab51c8877 1434
bogdanm 84:0b3ab51c8877 1435 /** \brief Encode Priority
bogdanm 84:0b3ab51c8877 1436
bogdanm 84:0b3ab51c8877 1437 The function encodes the priority for an interrupt with the given priority group,
bogdanm 84:0b3ab51c8877 1438 preemptive priority value, and subpriority value.
bogdanm 84:0b3ab51c8877 1439 In case of a conflict between priority grouping and available
bogdanm 84:0b3ab51c8877 1440 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
bogdanm 84:0b3ab51c8877 1441
bogdanm 84:0b3ab51c8877 1442 \param [in] PriorityGroup Used priority group.
bogdanm 84:0b3ab51c8877 1443 \param [in] PreemptPriority Preemptive priority value (starting from 0).
bogdanm 84:0b3ab51c8877 1444 \param [in] SubPriority Subpriority value (starting from 0).
bogdanm 84:0b3ab51c8877 1445 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
bogdanm 84:0b3ab51c8877 1446 */
bogdanm 84:0b3ab51c8877 1447 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
bogdanm 84:0b3ab51c8877 1448 {
bogdanm 84:0b3ab51c8877 1449 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
bogdanm 84:0b3ab51c8877 1450 uint32_t PreemptPriorityBits;
bogdanm 84:0b3ab51c8877 1451 uint32_t SubPriorityBits;
bogdanm 84:0b3ab51c8877 1452
bogdanm 84:0b3ab51c8877 1453 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
bogdanm 84:0b3ab51c8877 1454 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
bogdanm 84:0b3ab51c8877 1455
bogdanm 84:0b3ab51c8877 1456 return (
bogdanm 84:0b3ab51c8877 1457 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
bogdanm 84:0b3ab51c8877 1458 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
bogdanm 84:0b3ab51c8877 1459 );
bogdanm 84:0b3ab51c8877 1460 }
bogdanm 84:0b3ab51c8877 1461
bogdanm 84:0b3ab51c8877 1462
bogdanm 84:0b3ab51c8877 1463 /** \brief Decode Priority
bogdanm 84:0b3ab51c8877 1464
bogdanm 84:0b3ab51c8877 1465 The function decodes an interrupt priority value with a given priority group to
bogdanm 84:0b3ab51c8877 1466 preemptive priority value and subpriority value.
bogdanm 84:0b3ab51c8877 1467 In case of a conflict between priority grouping and available
bogdanm 84:0b3ab51c8877 1468 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
bogdanm 84:0b3ab51c8877 1469
bogdanm 84:0b3ab51c8877 1470 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
bogdanm 84:0b3ab51c8877 1471 \param [in] PriorityGroup Used priority group.
bogdanm 84:0b3ab51c8877 1472 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
bogdanm 84:0b3ab51c8877 1473 \param [out] pSubPriority Subpriority value (starting from 0).
bogdanm 84:0b3ab51c8877 1474 */
bogdanm 84:0b3ab51c8877 1475 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
bogdanm 84:0b3ab51c8877 1476 {
bogdanm 84:0b3ab51c8877 1477 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
bogdanm 84:0b3ab51c8877 1478 uint32_t PreemptPriorityBits;
bogdanm 84:0b3ab51c8877 1479 uint32_t SubPriorityBits;
bogdanm 84:0b3ab51c8877 1480
bogdanm 84:0b3ab51c8877 1481 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
bogdanm 84:0b3ab51c8877 1482 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
bogdanm 84:0b3ab51c8877 1483
bogdanm 84:0b3ab51c8877 1484 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
bogdanm 84:0b3ab51c8877 1485 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
bogdanm 84:0b3ab51c8877 1486 }
bogdanm 84:0b3ab51c8877 1487
bogdanm 84:0b3ab51c8877 1488
bogdanm 84:0b3ab51c8877 1489 /** \brief System Reset
bogdanm 84:0b3ab51c8877 1490
bogdanm 84:0b3ab51c8877 1491 The function initiates a system reset request to reset the MCU.
bogdanm 84:0b3ab51c8877 1492 */
bogdanm 84:0b3ab51c8877 1493 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 84:0b3ab51c8877 1494 {
bogdanm 84:0b3ab51c8877 1495 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 84:0b3ab51c8877 1496 buffered write are completed before reset */
bogdanm 84:0b3ab51c8877 1497 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 84:0b3ab51c8877 1498 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
bogdanm 84:0b3ab51c8877 1499 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
bogdanm 84:0b3ab51c8877 1500 __DSB(); /* Ensure completion of memory access */
bogdanm 84:0b3ab51c8877 1501 while(1); /* wait until reset */
bogdanm 84:0b3ab51c8877 1502 }
bogdanm 84:0b3ab51c8877 1503
bogdanm 84:0b3ab51c8877 1504 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 84:0b3ab51c8877 1505
bogdanm 84:0b3ab51c8877 1506
bogdanm 84:0b3ab51c8877 1507
bogdanm 84:0b3ab51c8877 1508 /* ################################## SysTick function ############################################ */
bogdanm 84:0b3ab51c8877 1509 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 84:0b3ab51c8877 1510 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 84:0b3ab51c8877 1511 \brief Functions that configure the System.
bogdanm 84:0b3ab51c8877 1512 @{
bogdanm 84:0b3ab51c8877 1513 */
bogdanm 84:0b3ab51c8877 1514
bogdanm 84:0b3ab51c8877 1515 #if (__Vendor_SysTickConfig == 0)
bogdanm 84:0b3ab51c8877 1516
bogdanm 84:0b3ab51c8877 1517 /** \brief System Tick Configuration
bogdanm 84:0b3ab51c8877 1518
bogdanm 84:0b3ab51c8877 1519 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 84:0b3ab51c8877 1520 Counter is in free running mode to generate periodic interrupts.
bogdanm 84:0b3ab51c8877 1521
bogdanm 84:0b3ab51c8877 1522 \param [in] ticks Number of ticks between two interrupts.
bogdanm 84:0b3ab51c8877 1523
bogdanm 84:0b3ab51c8877 1524 \return 0 Function succeeded.
bogdanm 84:0b3ab51c8877 1525 \return 1 Function failed.
bogdanm 84:0b3ab51c8877 1526
bogdanm 84:0b3ab51c8877 1527 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 84:0b3ab51c8877 1528 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 84:0b3ab51c8877 1529 must contain a vendor-specific implementation of this function.
bogdanm 84:0b3ab51c8877 1530
bogdanm 84:0b3ab51c8877 1531 */
bogdanm 84:0b3ab51c8877 1532 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 84:0b3ab51c8877 1533 {
bogdanm 84:0b3ab51c8877 1534 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
bogdanm 84:0b3ab51c8877 1535
bogdanm 84:0b3ab51c8877 1536 SysTick->LOAD = ticks - 1; /* set reload register */
bogdanm 84:0b3ab51c8877 1537 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
bogdanm 84:0b3ab51c8877 1538 SysTick->VAL = 0; /* Load the SysTick Counter Value */
bogdanm 84:0b3ab51c8877 1539 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 84:0b3ab51c8877 1540 SysTick_CTRL_TICKINT_Msk |
bogdanm 84:0b3ab51c8877 1541 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
bogdanm 84:0b3ab51c8877 1542 return (0); /* Function successful */
bogdanm 84:0b3ab51c8877 1543 }
bogdanm 84:0b3ab51c8877 1544
bogdanm 84:0b3ab51c8877 1545 #endif
bogdanm 84:0b3ab51c8877 1546
bogdanm 84:0b3ab51c8877 1547 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 84:0b3ab51c8877 1548
bogdanm 84:0b3ab51c8877 1549
bogdanm 84:0b3ab51c8877 1550
bogdanm 84:0b3ab51c8877 1551 /* ##################################### Debug In/Output function ########################################### */
bogdanm 84:0b3ab51c8877 1552 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 84:0b3ab51c8877 1553 \defgroup CMSIS_core_DebugFunctions ITM Functions
bogdanm 84:0b3ab51c8877 1554 \brief Functions that access the ITM debug interface.
bogdanm 84:0b3ab51c8877 1555 @{
bogdanm 84:0b3ab51c8877 1556 */
bogdanm 84:0b3ab51c8877 1557
bogdanm 84:0b3ab51c8877 1558 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
bogdanm 84:0b3ab51c8877 1559 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
bogdanm 84:0b3ab51c8877 1560
bogdanm 84:0b3ab51c8877 1561
bogdanm 84:0b3ab51c8877 1562 /** \brief ITM Send Character
bogdanm 84:0b3ab51c8877 1563
bogdanm 84:0b3ab51c8877 1564 The function transmits a character via the ITM channel 0, and
bogdanm 84:0b3ab51c8877 1565 \li Just returns when no debugger is connected that has booked the output.
bogdanm 84:0b3ab51c8877 1566 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
bogdanm 84:0b3ab51c8877 1567
bogdanm 84:0b3ab51c8877 1568 \param [in] ch Character to transmit.
bogdanm 84:0b3ab51c8877 1569
bogdanm 84:0b3ab51c8877 1570 \returns Character to transmit.
bogdanm 84:0b3ab51c8877 1571 */
bogdanm 84:0b3ab51c8877 1572 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
bogdanm 84:0b3ab51c8877 1573 {
bogdanm 84:0b3ab51c8877 1574 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
bogdanm 84:0b3ab51c8877 1575 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
bogdanm 84:0b3ab51c8877 1576 {
bogdanm 84:0b3ab51c8877 1577 while (ITM->PORT[0].u32 == 0);
bogdanm 84:0b3ab51c8877 1578 ITM->PORT[0].u8 = (uint8_t) ch;
bogdanm 84:0b3ab51c8877 1579 }
bogdanm 84:0b3ab51c8877 1580 return (ch);
bogdanm 84:0b3ab51c8877 1581 }
bogdanm 84:0b3ab51c8877 1582
bogdanm 84:0b3ab51c8877 1583
bogdanm 84:0b3ab51c8877 1584 /** \brief ITM Receive Character
bogdanm 84:0b3ab51c8877 1585
bogdanm 84:0b3ab51c8877 1586 The function inputs a character via the external variable \ref ITM_RxBuffer.
bogdanm 84:0b3ab51c8877 1587
bogdanm 84:0b3ab51c8877 1588 \return Received character.
bogdanm 84:0b3ab51c8877 1589 \return -1 No character pending.
bogdanm 84:0b3ab51c8877 1590 */
bogdanm 84:0b3ab51c8877 1591 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
bogdanm 84:0b3ab51c8877 1592 int32_t ch = -1; /* no character available */
bogdanm 84:0b3ab51c8877 1593
bogdanm 84:0b3ab51c8877 1594 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
bogdanm 84:0b3ab51c8877 1595 ch = ITM_RxBuffer;
bogdanm 84:0b3ab51c8877 1596 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
bogdanm 84:0b3ab51c8877 1597 }
bogdanm 84:0b3ab51c8877 1598
bogdanm 84:0b3ab51c8877 1599 return (ch);
bogdanm 84:0b3ab51c8877 1600 }
bogdanm 84:0b3ab51c8877 1601
bogdanm 84:0b3ab51c8877 1602
bogdanm 84:0b3ab51c8877 1603 /** \brief ITM Check Character
bogdanm 84:0b3ab51c8877 1604
bogdanm 84:0b3ab51c8877 1605 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
bogdanm 84:0b3ab51c8877 1606
bogdanm 84:0b3ab51c8877 1607 \return 0 No character available.
bogdanm 84:0b3ab51c8877 1608 \return 1 Character available.
bogdanm 84:0b3ab51c8877 1609 */
bogdanm 84:0b3ab51c8877 1610 __STATIC_INLINE int32_t ITM_CheckChar (void) {
bogdanm 84:0b3ab51c8877 1611
bogdanm 84:0b3ab51c8877 1612 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
bogdanm 84:0b3ab51c8877 1613 return (0); /* no character available */
bogdanm 84:0b3ab51c8877 1614 } else {
bogdanm 84:0b3ab51c8877 1615 return (1); /* character available */
bogdanm 84:0b3ab51c8877 1616 }
bogdanm 84:0b3ab51c8877 1617 }
bogdanm 84:0b3ab51c8877 1618
bogdanm 84:0b3ab51c8877 1619 /*@} end of CMSIS_core_DebugFunctions */
bogdanm 84:0b3ab51c8877 1620
bogdanm 84:0b3ab51c8877 1621 #endif /* __CORE_CM3_H_DEPENDANT */
bogdanm 84:0b3ab51c8877 1622
bogdanm 84:0b3ab51c8877 1623 #endif /* __CMSIS_GENERIC */
bogdanm 84:0b3ab51c8877 1624
bogdanm 84:0b3ab51c8877 1625 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 1626 }
bogdanm 84:0b3ab51c8877 1627 #endif