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version_2.0

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Fork of mbed by mbed official

TARGET_KL25Z/MKL25Z4.h@86:4f9a848d74c7, 2014-06-25 (annotated)

Committer:
erezi
Date:
Wed Jun 25 06:08:49 2014 +0000
Revision:
86:4f9a848d74c7
Parent:
66:9c8f0e3462fb 
version_2.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 66:9c8f0e3462fb 1 /*
bogdanm 66:9c8f0e3462fb 2 ** ###################################################################
bogdanm 66:9c8f0e3462fb 3 ** Processor: MKL25Z128VLK4
bogdanm 66:9c8f0e3462fb 4 ** Compilers: ARM Compiler
bogdanm 66:9c8f0e3462fb 5 ** Freescale C/C++ for Embedded ARM
bogdanm 66:9c8f0e3462fb 6 ** GNU C Compiler
bogdanm 66:9c8f0e3462fb 7 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 66:9c8f0e3462fb 8 **
bogdanm 66:9c8f0e3462fb 9 ** Reference manual: KL25RM, Rev.1, Jun 2012
bogdanm 66:9c8f0e3462fb 10 ** Version: rev. 1.1, 2012-06-21
bogdanm 66:9c8f0e3462fb 11 **
bogdanm 66:9c8f0e3462fb 12 ** Abstract:
bogdanm 66:9c8f0e3462fb 13 ** CMSIS Peripheral Access Layer for MKL25Z4
bogdanm 66:9c8f0e3462fb 14 **
bogdanm 66:9c8f0e3462fb 15 ** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
bogdanm 66:9c8f0e3462fb 16 **
bogdanm 66:9c8f0e3462fb 17 ** http: www.freescale.com
bogdanm 66:9c8f0e3462fb 18 ** mail: support@freescale.com
bogdanm 66:9c8f0e3462fb 19 **
bogdanm 66:9c8f0e3462fb 20 ** Revisions:
bogdanm 66:9c8f0e3462fb 21 ** - rev. 1.0 (2012-06-13)
bogdanm 66:9c8f0e3462fb 22 ** Initial version.
bogdanm 66:9c8f0e3462fb 23 ** - rev. 1.1 (2012-06-21)
bogdanm 66:9c8f0e3462fb 24 ** Update according to reference manual rev. 1.
bogdanm 66:9c8f0e3462fb 25 **
bogdanm 66:9c8f0e3462fb 26 ** ###################################################################
bogdanm 66:9c8f0e3462fb 27 */
bogdanm 66:9c8f0e3462fb 28
bogdanm 66:9c8f0e3462fb 29 /**
bogdanm 66:9c8f0e3462fb 30 * @file MKL25Z4.h
bogdanm 66:9c8f0e3462fb 31 * @version 1.1
bogdanm 66:9c8f0e3462fb 32 * @date 2012-06-21
bogdanm 66:9c8f0e3462fb 33 * @brief CMSIS Peripheral Access Layer for MKL25Z4
bogdanm 66:9c8f0e3462fb 34 *
bogdanm 66:9c8f0e3462fb 35 * CMSIS Peripheral Access Layer for MKL25Z4
bogdanm 66:9c8f0e3462fb 36 */
bogdanm 66:9c8f0e3462fb 37
bogdanm 66:9c8f0e3462fb 38 #if !defined(MKL25Z4_H_)
bogdanm 66:9c8f0e3462fb 39 #define MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
bogdanm 66:9c8f0e3462fb 40
bogdanm 66:9c8f0e3462fb 41 /** Memory map major version (memory maps with equal major version number are
bogdanm 66:9c8f0e3462fb 42 * compatible) */
bogdanm 66:9c8f0e3462fb 43 #define MCU_MEM_MAP_VERSION 0x0100u
bogdanm 66:9c8f0e3462fb 44 /** Memory map minor version */
bogdanm 66:9c8f0e3462fb 45 #define MCU_MEM_MAP_VERSION_MINOR 0x0001u
bogdanm 66:9c8f0e3462fb 46
bogdanm 66:9c8f0e3462fb 47
bogdanm 66:9c8f0e3462fb 48 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 49 -- Interrupt vector numbers
bogdanm 66:9c8f0e3462fb 50 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 51
bogdanm 66:9c8f0e3462fb 52 /**
bogdanm 66:9c8f0e3462fb 53 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
bogdanm 66:9c8f0e3462fb 54 * @{
bogdanm 66:9c8f0e3462fb 55 */
bogdanm 66:9c8f0e3462fb 56
bogdanm 66:9c8f0e3462fb 57 /** Interrupt Number Definitions */
bogdanm 66:9c8f0e3462fb 58 typedef enum IRQn {
bogdanm 66:9c8f0e3462fb 59 /* Core interrupts */
bogdanm 66:9c8f0e3462fb 60 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
bogdanm 66:9c8f0e3462fb 61 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
bogdanm 66:9c8f0e3462fb 62 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
bogdanm 66:9c8f0e3462fb 63 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
bogdanm 66:9c8f0e3462fb 64 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
bogdanm 66:9c8f0e3462fb 65
bogdanm 66:9c8f0e3462fb 66 /* Device specific interrupts */
bogdanm 66:9c8f0e3462fb 67 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
bogdanm 66:9c8f0e3462fb 68 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
bogdanm 66:9c8f0e3462fb 69 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
bogdanm 66:9c8f0e3462fb 70 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
bogdanm 66:9c8f0e3462fb 71 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
bogdanm 66:9c8f0e3462fb 72 FTFA_IRQn = 5, /**< FTFA interrupt */
bogdanm 66:9c8f0e3462fb 73 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
bogdanm 66:9c8f0e3462fb 74 LLW_IRQn = 7, /**< Low Leakage Wakeup */
bogdanm 66:9c8f0e3462fb 75 I2C0_IRQn = 8, /**< I2C0 interrupt */
bogdanm 66:9c8f0e3462fb 76 I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
bogdanm 66:9c8f0e3462fb 77 SPI0_IRQn = 10, /**< SPI0 interrupt */
bogdanm 66:9c8f0e3462fb 78 SPI1_IRQn = 11, /**< SPI1 interrupt */
bogdanm 66:9c8f0e3462fb 79 UART0_IRQn = 12, /**< UART0 status/error interrupt */
bogdanm 66:9c8f0e3462fb 80 UART1_IRQn = 13, /**< UART1 status/error interrupt */
bogdanm 66:9c8f0e3462fb 81 UART2_IRQn = 14, /**< UART2 status/error interrupt */
bogdanm 66:9c8f0e3462fb 82 ADC0_IRQn = 15, /**< ADC0 interrupt */
bogdanm 66:9c8f0e3462fb 83 CMP0_IRQn = 16, /**< CMP0 interrupt */
bogdanm 66:9c8f0e3462fb 84 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
bogdanm 66:9c8f0e3462fb 85 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
bogdanm 66:9c8f0e3462fb 86 TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
bogdanm 66:9c8f0e3462fb 87 RTC_IRQn = 20, /**< RTC interrupt */
bogdanm 66:9c8f0e3462fb 88 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
bogdanm 66:9c8f0e3462fb 89 PIT_IRQn = 22, /**< PIT timer interrupt */
bogdanm 66:9c8f0e3462fb 90 Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
bogdanm 66:9c8f0e3462fb 91 USB0_IRQn = 24, /**< USB0 interrupt */
bogdanm 66:9c8f0e3462fb 92 DAC0_IRQn = 25, /**< DAC interrupt */
bogdanm 66:9c8f0e3462fb 93 TSI0_IRQn = 26, /**< TSI0 interrupt */
bogdanm 66:9c8f0e3462fb 94 MCG_IRQn = 27, /**< MCG interrupt */
bogdanm 66:9c8f0e3462fb 95 LPTimer_IRQn = 28, /**< LPTimer interrupt */
bogdanm 66:9c8f0e3462fb 96 Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
bogdanm 66:9c8f0e3462fb 97 PORTA_IRQn = 30, /**< Port A interrupt */
bogdanm 66:9c8f0e3462fb 98 PORTD_IRQn = 31 /**< Port D interrupt */
bogdanm 66:9c8f0e3462fb 99 } IRQn_Type;
bogdanm 66:9c8f0e3462fb 100
bogdanm 66:9c8f0e3462fb 101 /**
bogdanm 66:9c8f0e3462fb 102 * @}
bogdanm 66:9c8f0e3462fb 103 */ /* end of group Interrupt_vector_numbers */
bogdanm 66:9c8f0e3462fb 104
bogdanm 66:9c8f0e3462fb 105
bogdanm 66:9c8f0e3462fb 106 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 107 -- Cortex M0 Core Configuration
bogdanm 66:9c8f0e3462fb 108 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 109
bogdanm 66:9c8f0e3462fb 110 /**
bogdanm 66:9c8f0e3462fb 111 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
bogdanm 66:9c8f0e3462fb 112 * @{
bogdanm 66:9c8f0e3462fb 113 */
bogdanm 66:9c8f0e3462fb 114
bogdanm 66:9c8f0e3462fb 115 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
bogdanm 66:9c8f0e3462fb 116 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
bogdanm 66:9c8f0e3462fb 117 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
bogdanm 66:9c8f0e3462fb 118 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
bogdanm 66:9c8f0e3462fb 119 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
bogdanm 66:9c8f0e3462fb 120
bogdanm 66:9c8f0e3462fb 121 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
bogdanm 66:9c8f0e3462fb 122 #include "system_MKL25Z4.h" /* Device specific configuration file */
bogdanm 66:9c8f0e3462fb 123
bogdanm 66:9c8f0e3462fb 124 /**
bogdanm 66:9c8f0e3462fb 125 * @}
bogdanm 66:9c8f0e3462fb 126 */ /* end of group Cortex_Core_Configuration */
bogdanm 66:9c8f0e3462fb 127
bogdanm 66:9c8f0e3462fb 128
bogdanm 66:9c8f0e3462fb 129 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 130 -- Device Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 131 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 132
bogdanm 66:9c8f0e3462fb 133 /**
bogdanm 66:9c8f0e3462fb 134 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 135 * @{
bogdanm 66:9c8f0e3462fb 136 */
bogdanm 66:9c8f0e3462fb 137
bogdanm 66:9c8f0e3462fb 138
bogdanm 66:9c8f0e3462fb 139 /*
bogdanm 66:9c8f0e3462fb 140 ** Start of section using anonymous unions
bogdanm 66:9c8f0e3462fb 141 */
bogdanm 66:9c8f0e3462fb 142
bogdanm 66:9c8f0e3462fb 143 #if defined(__ARMCC_VERSION)
bogdanm 66:9c8f0e3462fb 144 #pragma push
bogdanm 66:9c8f0e3462fb 145 #pragma anon_unions
bogdanm 66:9c8f0e3462fb 146 #elif defined(__CWCC__)
bogdanm 66:9c8f0e3462fb 147 #pragma push
bogdanm 66:9c8f0e3462fb 148 #pragma cpp_extensions on
bogdanm 66:9c8f0e3462fb 149 #elif defined(__GNUC__)
bogdanm 66:9c8f0e3462fb 150 /* anonymous unions are enabled by default */
bogdanm 66:9c8f0e3462fb 151 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 66:9c8f0e3462fb 152 #pragma language=extended
bogdanm 66:9c8f0e3462fb 153 #else
bogdanm 66:9c8f0e3462fb 154 #error Not supported compiler type
bogdanm 66:9c8f0e3462fb 155 #endif
bogdanm 66:9c8f0e3462fb 156
bogdanm 66:9c8f0e3462fb 157 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 158 -- ADC Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 159 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 160
bogdanm 66:9c8f0e3462fb 161 /**
bogdanm 66:9c8f0e3462fb 162 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 163 * @{
bogdanm 66:9c8f0e3462fb 164 */
bogdanm 66:9c8f0e3462fb 165
bogdanm 66:9c8f0e3462fb 166 /** ADC - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 167 typedef struct {
bogdanm 66:9c8f0e3462fb 168 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
bogdanm 66:9c8f0e3462fb 169 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 170 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
bogdanm 66:9c8f0e3462fb 171 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
bogdanm 66:9c8f0e3462fb 172 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
bogdanm 66:9c8f0e3462fb 173 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
bogdanm 66:9c8f0e3462fb 174 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
bogdanm 66:9c8f0e3462fb 175 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
bogdanm 66:9c8f0e3462fb 176 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
bogdanm 66:9c8f0e3462fb 177 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
bogdanm 66:9c8f0e3462fb 178 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
bogdanm 66:9c8f0e3462fb 179 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
bogdanm 66:9c8f0e3462fb 180 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
bogdanm 66:9c8f0e3462fb 181 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
bogdanm 66:9c8f0e3462fb 182 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
bogdanm 66:9c8f0e3462fb 183 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
bogdanm 66:9c8f0e3462fb 184 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
bogdanm 66:9c8f0e3462fb 185 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
bogdanm 66:9c8f0e3462fb 186 uint8_t RESERVED_0[4];
bogdanm 66:9c8f0e3462fb 187 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
bogdanm 66:9c8f0e3462fb 188 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
bogdanm 66:9c8f0e3462fb 189 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
bogdanm 66:9c8f0e3462fb 190 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
bogdanm 66:9c8f0e3462fb 191 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
bogdanm 66:9c8f0e3462fb 192 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
bogdanm 66:9c8f0e3462fb 193 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
bogdanm 66:9c8f0e3462fb 194 } ADC_Type;
bogdanm 66:9c8f0e3462fb 195
bogdanm 66:9c8f0e3462fb 196 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 197 -- ADC Register Masks
bogdanm 66:9c8f0e3462fb 198 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 199
bogdanm 66:9c8f0e3462fb 200 /**
bogdanm 66:9c8f0e3462fb 201 * @addtogroup ADC_Register_Masks ADC Register Masks
bogdanm 66:9c8f0e3462fb 202 * @{
bogdanm 66:9c8f0e3462fb 203 */
bogdanm 66:9c8f0e3462fb 204
bogdanm 66:9c8f0e3462fb 205 /* SC1 Bit Fields */
bogdanm 66:9c8f0e3462fb 206 #define ADC_SC1_ADCH_MASK 0x1Fu
bogdanm 66:9c8f0e3462fb 207 #define ADC_SC1_ADCH_SHIFT 0
bogdanm 66:9c8f0e3462fb 208 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
bogdanm 66:9c8f0e3462fb 209 #define ADC_SC1_DIFF_MASK 0x20u
bogdanm 66:9c8f0e3462fb 210 #define ADC_SC1_DIFF_SHIFT 5
bogdanm 66:9c8f0e3462fb 211 #define ADC_SC1_AIEN_MASK 0x40u
bogdanm 66:9c8f0e3462fb 212 #define ADC_SC1_AIEN_SHIFT 6
bogdanm 66:9c8f0e3462fb 213 #define ADC_SC1_COCO_MASK 0x80u
bogdanm 66:9c8f0e3462fb 214 #define ADC_SC1_COCO_SHIFT 7
bogdanm 66:9c8f0e3462fb 215 /* CFG1 Bit Fields */
bogdanm 66:9c8f0e3462fb 216 #define ADC_CFG1_ADICLK_MASK 0x3u
bogdanm 66:9c8f0e3462fb 217 #define ADC_CFG1_ADICLK_SHIFT 0
bogdanm 66:9c8f0e3462fb 218 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
bogdanm 66:9c8f0e3462fb 219 #define ADC_CFG1_MODE_MASK 0xCu
bogdanm 66:9c8f0e3462fb 220 #define ADC_CFG1_MODE_SHIFT 2
bogdanm 66:9c8f0e3462fb 221 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
bogdanm 66:9c8f0e3462fb 222 #define ADC_CFG1_ADLSMP_MASK 0x10u
bogdanm 66:9c8f0e3462fb 223 #define ADC_CFG1_ADLSMP_SHIFT 4
bogdanm 66:9c8f0e3462fb 224 #define ADC_CFG1_ADIV_MASK 0x60u
bogdanm 66:9c8f0e3462fb 225 #define ADC_CFG1_ADIV_SHIFT 5
bogdanm 66:9c8f0e3462fb 226 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
bogdanm 66:9c8f0e3462fb 227 #define ADC_CFG1_ADLPC_MASK 0x80u
bogdanm 66:9c8f0e3462fb 228 #define ADC_CFG1_ADLPC_SHIFT 7
bogdanm 66:9c8f0e3462fb 229 /* CFG2 Bit Fields */
bogdanm 66:9c8f0e3462fb 230 #define ADC_CFG2_ADLSTS_MASK 0x3u
bogdanm 66:9c8f0e3462fb 231 #define ADC_CFG2_ADLSTS_SHIFT 0
bogdanm 66:9c8f0e3462fb 232 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
bogdanm 66:9c8f0e3462fb 233 #define ADC_CFG2_ADHSC_MASK 0x4u
bogdanm 66:9c8f0e3462fb 234 #define ADC_CFG2_ADHSC_SHIFT 2
bogdanm 66:9c8f0e3462fb 235 #define ADC_CFG2_ADACKEN_MASK 0x8u
bogdanm 66:9c8f0e3462fb 236 #define ADC_CFG2_ADACKEN_SHIFT 3
bogdanm 66:9c8f0e3462fb 237 #define ADC_CFG2_MUXSEL_MASK 0x10u
bogdanm 66:9c8f0e3462fb 238 #define ADC_CFG2_MUXSEL_SHIFT 4
bogdanm 66:9c8f0e3462fb 239 /* R Bit Fields */
bogdanm 66:9c8f0e3462fb 240 #define ADC_R_D_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 241 #define ADC_R_D_SHIFT 0
bogdanm 66:9c8f0e3462fb 242 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
bogdanm 66:9c8f0e3462fb 243 /* CV1 Bit Fields */
bogdanm 66:9c8f0e3462fb 244 #define ADC_CV1_CV_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 245 #define ADC_CV1_CV_SHIFT 0
bogdanm 66:9c8f0e3462fb 246 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
bogdanm 66:9c8f0e3462fb 247 /* CV2 Bit Fields */
bogdanm 66:9c8f0e3462fb 248 #define ADC_CV2_CV_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 249 #define ADC_CV2_CV_SHIFT 0
bogdanm 66:9c8f0e3462fb 250 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
bogdanm 66:9c8f0e3462fb 251 /* SC2 Bit Fields */
bogdanm 66:9c8f0e3462fb 252 #define ADC_SC2_REFSEL_MASK 0x3u
bogdanm 66:9c8f0e3462fb 253 #define ADC_SC2_REFSEL_SHIFT 0
bogdanm 66:9c8f0e3462fb 254 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
bogdanm 66:9c8f0e3462fb 255 #define ADC_SC2_DMAEN_MASK 0x4u
bogdanm 66:9c8f0e3462fb 256 #define ADC_SC2_DMAEN_SHIFT 2
bogdanm 66:9c8f0e3462fb 257 #define ADC_SC2_ACREN_MASK 0x8u
bogdanm 66:9c8f0e3462fb 258 #define ADC_SC2_ACREN_SHIFT 3
bogdanm 66:9c8f0e3462fb 259 #define ADC_SC2_ACFGT_MASK 0x10u
bogdanm 66:9c8f0e3462fb 260 #define ADC_SC2_ACFGT_SHIFT 4
bogdanm 66:9c8f0e3462fb 261 #define ADC_SC2_ACFE_MASK 0x20u
bogdanm 66:9c8f0e3462fb 262 #define ADC_SC2_ACFE_SHIFT 5
bogdanm 66:9c8f0e3462fb 263 #define ADC_SC2_ADTRG_MASK 0x40u
bogdanm 66:9c8f0e3462fb 264 #define ADC_SC2_ADTRG_SHIFT 6
bogdanm 66:9c8f0e3462fb 265 #define ADC_SC2_ADACT_MASK 0x80u
bogdanm 66:9c8f0e3462fb 266 #define ADC_SC2_ADACT_SHIFT 7
bogdanm 66:9c8f0e3462fb 267 /* SC3 Bit Fields */
bogdanm 66:9c8f0e3462fb 268 #define ADC_SC3_AVGS_MASK 0x3u
bogdanm 66:9c8f0e3462fb 269 #define ADC_SC3_AVGS_SHIFT 0
bogdanm 66:9c8f0e3462fb 270 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
bogdanm 66:9c8f0e3462fb 271 #define ADC_SC3_AVGE_MASK 0x4u
bogdanm 66:9c8f0e3462fb 272 #define ADC_SC3_AVGE_SHIFT 2
bogdanm 66:9c8f0e3462fb 273 #define ADC_SC3_ADCO_MASK 0x8u
bogdanm 66:9c8f0e3462fb 274 #define ADC_SC3_ADCO_SHIFT 3
bogdanm 66:9c8f0e3462fb 275 #define ADC_SC3_CALF_MASK 0x40u
bogdanm 66:9c8f0e3462fb 276 #define ADC_SC3_CALF_SHIFT 6
bogdanm 66:9c8f0e3462fb 277 #define ADC_SC3_CAL_MASK 0x80u
bogdanm 66:9c8f0e3462fb 278 #define ADC_SC3_CAL_SHIFT 7
bogdanm 66:9c8f0e3462fb 279 /* OFS Bit Fields */
bogdanm 66:9c8f0e3462fb 280 #define ADC_OFS_OFS_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 281 #define ADC_OFS_OFS_SHIFT 0
bogdanm 66:9c8f0e3462fb 282 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
bogdanm 66:9c8f0e3462fb 283 /* PG Bit Fields */
bogdanm 66:9c8f0e3462fb 284 #define ADC_PG_PG_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 285 #define ADC_PG_PG_SHIFT 0
bogdanm 66:9c8f0e3462fb 286 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
bogdanm 66:9c8f0e3462fb 287 /* MG Bit Fields */
bogdanm 66:9c8f0e3462fb 288 #define ADC_MG_MG_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 289 #define ADC_MG_MG_SHIFT 0
bogdanm 66:9c8f0e3462fb 290 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
bogdanm 66:9c8f0e3462fb 291 /* CLPD Bit Fields */
bogdanm 66:9c8f0e3462fb 292 #define ADC_CLPD_CLPD_MASK 0x3Fu
bogdanm 66:9c8f0e3462fb 293 #define ADC_CLPD_CLPD_SHIFT 0
bogdanm 66:9c8f0e3462fb 294 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
bogdanm 66:9c8f0e3462fb 295 /* CLPS Bit Fields */
bogdanm 66:9c8f0e3462fb 296 #define ADC_CLPS_CLPS_MASK 0x3Fu
bogdanm 66:9c8f0e3462fb 297 #define ADC_CLPS_CLPS_SHIFT 0
bogdanm 66:9c8f0e3462fb 298 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
bogdanm 66:9c8f0e3462fb 299 /* CLP4 Bit Fields */
bogdanm 66:9c8f0e3462fb 300 #define ADC_CLP4_CLP4_MASK 0x3FFu
bogdanm 66:9c8f0e3462fb 301 #define ADC_CLP4_CLP4_SHIFT 0
bogdanm 66:9c8f0e3462fb 302 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
bogdanm 66:9c8f0e3462fb 303 /* CLP3 Bit Fields */
bogdanm 66:9c8f0e3462fb 304 #define ADC_CLP3_CLP3_MASK 0x1FFu
bogdanm 66:9c8f0e3462fb 305 #define ADC_CLP3_CLP3_SHIFT 0
bogdanm 66:9c8f0e3462fb 306 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
bogdanm 66:9c8f0e3462fb 307 /* CLP2 Bit Fields */
bogdanm 66:9c8f0e3462fb 308 #define ADC_CLP2_CLP2_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 309 #define ADC_CLP2_CLP2_SHIFT 0
bogdanm 66:9c8f0e3462fb 310 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
bogdanm 66:9c8f0e3462fb 311 /* CLP1 Bit Fields */
bogdanm 66:9c8f0e3462fb 312 #define ADC_CLP1_CLP1_MASK 0x7Fu
bogdanm 66:9c8f0e3462fb 313 #define ADC_CLP1_CLP1_SHIFT 0
bogdanm 66:9c8f0e3462fb 314 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
bogdanm 66:9c8f0e3462fb 315 /* CLP0 Bit Fields */
bogdanm 66:9c8f0e3462fb 316 #define ADC_CLP0_CLP0_MASK 0x3Fu
bogdanm 66:9c8f0e3462fb 317 #define ADC_CLP0_CLP0_SHIFT 0
bogdanm 66:9c8f0e3462fb 318 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
bogdanm 66:9c8f0e3462fb 319 /* CLMD Bit Fields */
bogdanm 66:9c8f0e3462fb 320 #define ADC_CLMD_CLMD_MASK 0x3Fu
bogdanm 66:9c8f0e3462fb 321 #define ADC_CLMD_CLMD_SHIFT 0
bogdanm 66:9c8f0e3462fb 322 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
bogdanm 66:9c8f0e3462fb 323 /* CLMS Bit Fields */
bogdanm 66:9c8f0e3462fb 324 #define ADC_CLMS_CLMS_MASK 0x3Fu
bogdanm 66:9c8f0e3462fb 325 #define ADC_CLMS_CLMS_SHIFT 0
bogdanm 66:9c8f0e3462fb 326 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
bogdanm 66:9c8f0e3462fb 327 /* CLM4 Bit Fields */
bogdanm 66:9c8f0e3462fb 328 #define ADC_CLM4_CLM4_MASK 0x3FFu
bogdanm 66:9c8f0e3462fb 329 #define ADC_CLM4_CLM4_SHIFT 0
bogdanm 66:9c8f0e3462fb 330 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
bogdanm 66:9c8f0e3462fb 331 /* CLM3 Bit Fields */
bogdanm 66:9c8f0e3462fb 332 #define ADC_CLM3_CLM3_MASK 0x1FFu
bogdanm 66:9c8f0e3462fb 333 #define ADC_CLM3_CLM3_SHIFT 0
bogdanm 66:9c8f0e3462fb 334 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
bogdanm 66:9c8f0e3462fb 335 /* CLM2 Bit Fields */
bogdanm 66:9c8f0e3462fb 336 #define ADC_CLM2_CLM2_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 337 #define ADC_CLM2_CLM2_SHIFT 0
bogdanm 66:9c8f0e3462fb 338 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
bogdanm 66:9c8f0e3462fb 339 /* CLM1 Bit Fields */
bogdanm 66:9c8f0e3462fb 340 #define ADC_CLM1_CLM1_MASK 0x7Fu
bogdanm 66:9c8f0e3462fb 341 #define ADC_CLM1_CLM1_SHIFT 0
bogdanm 66:9c8f0e3462fb 342 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
bogdanm 66:9c8f0e3462fb 343 /* CLM0 Bit Fields */
bogdanm 66:9c8f0e3462fb 344 #define ADC_CLM0_CLM0_MASK 0x3Fu
bogdanm 66:9c8f0e3462fb 345 #define ADC_CLM0_CLM0_SHIFT 0
bogdanm 66:9c8f0e3462fb 346 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
bogdanm 66:9c8f0e3462fb 347
bogdanm 66:9c8f0e3462fb 348 /**
bogdanm 66:9c8f0e3462fb 349 * @}
bogdanm 66:9c8f0e3462fb 350 */ /* end of group ADC_Register_Masks */
bogdanm 66:9c8f0e3462fb 351
bogdanm 66:9c8f0e3462fb 352
bogdanm 66:9c8f0e3462fb 353 /* ADC - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 354 /** Peripheral ADC0 base address */
bogdanm 66:9c8f0e3462fb 355 #define ADC0_BASE (0x4003B000u)
bogdanm 66:9c8f0e3462fb 356 /** Peripheral ADC0 base pointer */
bogdanm 66:9c8f0e3462fb 357 #define ADC0 ((ADC_Type *)ADC0_BASE)
bogdanm 66:9c8f0e3462fb 358 /** Array initializer of ADC peripheral base pointers */
bogdanm 66:9c8f0e3462fb 359 #define ADC_BASES { ADC0 }
bogdanm 66:9c8f0e3462fb 360
bogdanm 66:9c8f0e3462fb 361 /**
bogdanm 66:9c8f0e3462fb 362 * @}
bogdanm 66:9c8f0e3462fb 363 */ /* end of group ADC_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 364
bogdanm 66:9c8f0e3462fb 365
bogdanm 66:9c8f0e3462fb 366 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 367 -- CMP Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 368 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 369
bogdanm 66:9c8f0e3462fb 370 /**
bogdanm 66:9c8f0e3462fb 371 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 372 * @{
bogdanm 66:9c8f0e3462fb 373 */
bogdanm 66:9c8f0e3462fb 374
bogdanm 66:9c8f0e3462fb 375 /** CMP - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 376 typedef struct {
bogdanm 66:9c8f0e3462fb 377 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 378 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
bogdanm 66:9c8f0e3462fb 379 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
bogdanm 66:9c8f0e3462fb 380 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
bogdanm 66:9c8f0e3462fb 381 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 382 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
bogdanm 66:9c8f0e3462fb 383 } CMP_Type;
bogdanm 66:9c8f0e3462fb 384
bogdanm 66:9c8f0e3462fb 385 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 386 -- CMP Register Masks
bogdanm 66:9c8f0e3462fb 387 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 388
bogdanm 66:9c8f0e3462fb 389 /**
bogdanm 66:9c8f0e3462fb 390 * @addtogroup CMP_Register_Masks CMP Register Masks
bogdanm 66:9c8f0e3462fb 391 * @{
bogdanm 66:9c8f0e3462fb 392 */
bogdanm 66:9c8f0e3462fb 393
bogdanm 66:9c8f0e3462fb 394 /* CR0 Bit Fields */
bogdanm 66:9c8f0e3462fb 395 #define CMP_CR0_HYSTCTR_MASK 0x3u
bogdanm 66:9c8f0e3462fb 396 #define CMP_CR0_HYSTCTR_SHIFT 0
bogdanm 66:9c8f0e3462fb 397 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
bogdanm 66:9c8f0e3462fb 398 #define CMP_CR0_FILTER_CNT_MASK 0x70u
bogdanm 66:9c8f0e3462fb 399 #define CMP_CR0_FILTER_CNT_SHIFT 4
bogdanm 66:9c8f0e3462fb 400 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
bogdanm 66:9c8f0e3462fb 401 /* CR1 Bit Fields */
bogdanm 66:9c8f0e3462fb 402 #define CMP_CR1_EN_MASK 0x1u
bogdanm 66:9c8f0e3462fb 403 #define CMP_CR1_EN_SHIFT 0
bogdanm 66:9c8f0e3462fb 404 #define CMP_CR1_OPE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 405 #define CMP_CR1_OPE_SHIFT 1
bogdanm 66:9c8f0e3462fb 406 #define CMP_CR1_COS_MASK 0x4u
bogdanm 66:9c8f0e3462fb 407 #define CMP_CR1_COS_SHIFT 2
bogdanm 66:9c8f0e3462fb 408 #define CMP_CR1_INV_MASK 0x8u
bogdanm 66:9c8f0e3462fb 409 #define CMP_CR1_INV_SHIFT 3
bogdanm 66:9c8f0e3462fb 410 #define CMP_CR1_PMODE_MASK 0x10u
bogdanm 66:9c8f0e3462fb 411 #define CMP_CR1_PMODE_SHIFT 4
bogdanm 66:9c8f0e3462fb 412 #define CMP_CR1_TRIGM_MASK 0x20u
bogdanm 66:9c8f0e3462fb 413 #define CMP_CR1_TRIGM_SHIFT 5
bogdanm 66:9c8f0e3462fb 414 #define CMP_CR1_WE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 415 #define CMP_CR1_WE_SHIFT 6
bogdanm 66:9c8f0e3462fb 416 #define CMP_CR1_SE_MASK 0x80u
bogdanm 66:9c8f0e3462fb 417 #define CMP_CR1_SE_SHIFT 7
bogdanm 66:9c8f0e3462fb 418 /* FPR Bit Fields */
bogdanm 66:9c8f0e3462fb 419 #define CMP_FPR_FILT_PER_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 420 #define CMP_FPR_FILT_PER_SHIFT 0
bogdanm 66:9c8f0e3462fb 421 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
bogdanm 66:9c8f0e3462fb 422 /* SCR Bit Fields */
bogdanm 66:9c8f0e3462fb 423 #define CMP_SCR_COUT_MASK 0x1u
bogdanm 66:9c8f0e3462fb 424 #define CMP_SCR_COUT_SHIFT 0
bogdanm 66:9c8f0e3462fb 425 #define CMP_SCR_CFF_MASK 0x2u
bogdanm 66:9c8f0e3462fb 426 #define CMP_SCR_CFF_SHIFT 1
bogdanm 66:9c8f0e3462fb 427 #define CMP_SCR_CFR_MASK 0x4u
bogdanm 66:9c8f0e3462fb 428 #define CMP_SCR_CFR_SHIFT 2
bogdanm 66:9c8f0e3462fb 429 #define CMP_SCR_IEF_MASK 0x8u
bogdanm 66:9c8f0e3462fb 430 #define CMP_SCR_IEF_SHIFT 3
bogdanm 66:9c8f0e3462fb 431 #define CMP_SCR_IER_MASK 0x10u
bogdanm 66:9c8f0e3462fb 432 #define CMP_SCR_IER_SHIFT 4
bogdanm 66:9c8f0e3462fb 433 #define CMP_SCR_DMAEN_MASK 0x40u
bogdanm 66:9c8f0e3462fb 434 #define CMP_SCR_DMAEN_SHIFT 6
bogdanm 66:9c8f0e3462fb 435 /* DACCR Bit Fields */
bogdanm 66:9c8f0e3462fb 436 #define CMP_DACCR_VOSEL_MASK 0x3Fu
bogdanm 66:9c8f0e3462fb 437 #define CMP_DACCR_VOSEL_SHIFT 0
bogdanm 66:9c8f0e3462fb 438 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
bogdanm 66:9c8f0e3462fb 439 #define CMP_DACCR_VRSEL_MASK 0x40u
bogdanm 66:9c8f0e3462fb 440 #define CMP_DACCR_VRSEL_SHIFT 6
bogdanm 66:9c8f0e3462fb 441 #define CMP_DACCR_DACEN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 442 #define CMP_DACCR_DACEN_SHIFT 7
bogdanm 66:9c8f0e3462fb 443 /* MUXCR Bit Fields */
bogdanm 66:9c8f0e3462fb 444 #define CMP_MUXCR_MSEL_MASK 0x7u
bogdanm 66:9c8f0e3462fb 445 #define CMP_MUXCR_MSEL_SHIFT 0
bogdanm 66:9c8f0e3462fb 446 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
bogdanm 66:9c8f0e3462fb 447 #define CMP_MUXCR_PSEL_MASK 0x38u
bogdanm 66:9c8f0e3462fb 448 #define CMP_MUXCR_PSEL_SHIFT 3
bogdanm 66:9c8f0e3462fb 449 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
bogdanm 66:9c8f0e3462fb 450 #define CMP_MUXCR_PSTM_MASK 0x40u
bogdanm 66:9c8f0e3462fb 451 #define CMP_MUXCR_PSTM_SHIFT 6
bogdanm 66:9c8f0e3462fb 452
bogdanm 66:9c8f0e3462fb 453 /**
bogdanm 66:9c8f0e3462fb 454 * @}
bogdanm 66:9c8f0e3462fb 455 */ /* end of group CMP_Register_Masks */
bogdanm 66:9c8f0e3462fb 456
bogdanm 66:9c8f0e3462fb 457
bogdanm 66:9c8f0e3462fb 458 /* CMP - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 459 /** Peripheral CMP0 base address */
bogdanm 66:9c8f0e3462fb 460 #define CMP0_BASE (0x40073000u)
bogdanm 66:9c8f0e3462fb 461 /** Peripheral CMP0 base pointer */
bogdanm 66:9c8f0e3462fb 462 #define CMP0 ((CMP_Type *)CMP0_BASE)
bogdanm 66:9c8f0e3462fb 463 /** Array initializer of CMP peripheral base pointers */
bogdanm 66:9c8f0e3462fb 464 #define CMP_BASES { CMP0 }
bogdanm 66:9c8f0e3462fb 465
bogdanm 66:9c8f0e3462fb 466 /**
bogdanm 66:9c8f0e3462fb 467 * @}
bogdanm 66:9c8f0e3462fb 468 */ /* end of group CMP_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 469
bogdanm 66:9c8f0e3462fb 470
bogdanm 66:9c8f0e3462fb 471 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 472 -- DAC Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 473 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 474
bogdanm 66:9c8f0e3462fb 475 /**
bogdanm 66:9c8f0e3462fb 476 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 477 * @{
bogdanm 66:9c8f0e3462fb 478 */
bogdanm 66:9c8f0e3462fb 479
bogdanm 66:9c8f0e3462fb 480 /** DAC - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 481 typedef struct {
bogdanm 66:9c8f0e3462fb 482 struct { /* offset: 0x0, array step: 0x2 */
bogdanm 66:9c8f0e3462fb 483 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
bogdanm 66:9c8f0e3462fb 484 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
bogdanm 66:9c8f0e3462fb 485 } DAT[2];
bogdanm 66:9c8f0e3462fb 486 uint8_t RESERVED_0[28];
bogdanm 66:9c8f0e3462fb 487 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
bogdanm 66:9c8f0e3462fb 488 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
bogdanm 66:9c8f0e3462fb 489 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
bogdanm 66:9c8f0e3462fb 490 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
bogdanm 66:9c8f0e3462fb 491 } DAC_Type;
bogdanm 66:9c8f0e3462fb 492
bogdanm 66:9c8f0e3462fb 493 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 494 -- DAC Register Masks
bogdanm 66:9c8f0e3462fb 495 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 496
bogdanm 66:9c8f0e3462fb 497 /**
bogdanm 66:9c8f0e3462fb 498 * @addtogroup DAC_Register_Masks DAC Register Masks
bogdanm 66:9c8f0e3462fb 499 * @{
bogdanm 66:9c8f0e3462fb 500 */
bogdanm 66:9c8f0e3462fb 501
bogdanm 66:9c8f0e3462fb 502 /* DATL Bit Fields */
bogdanm 66:9c8f0e3462fb 503 #define DAC_DATL_DATA0_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 504 #define DAC_DATL_DATA0_SHIFT 0
bogdanm 66:9c8f0e3462fb 505 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
bogdanm 66:9c8f0e3462fb 506 /* DATH Bit Fields */
bogdanm 66:9c8f0e3462fb 507 #define DAC_DATH_DATA1_MASK 0xFu
bogdanm 66:9c8f0e3462fb 508 #define DAC_DATH_DATA1_SHIFT 0
bogdanm 66:9c8f0e3462fb 509 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
bogdanm 66:9c8f0e3462fb 510 /* SR Bit Fields */
bogdanm 66:9c8f0e3462fb 511 #define DAC_SR_DACBFRPBF_MASK 0x1u
bogdanm 66:9c8f0e3462fb 512 #define DAC_SR_DACBFRPBF_SHIFT 0
bogdanm 66:9c8f0e3462fb 513 #define DAC_SR_DACBFRPTF_MASK 0x2u
bogdanm 66:9c8f0e3462fb 514 #define DAC_SR_DACBFRPTF_SHIFT 1
bogdanm 66:9c8f0e3462fb 515 /* C0 Bit Fields */
bogdanm 66:9c8f0e3462fb 516 #define DAC_C0_DACBBIEN_MASK 0x1u
bogdanm 66:9c8f0e3462fb 517 #define DAC_C0_DACBBIEN_SHIFT 0
bogdanm 66:9c8f0e3462fb 518 #define DAC_C0_DACBTIEN_MASK 0x2u
bogdanm 66:9c8f0e3462fb 519 #define DAC_C0_DACBTIEN_SHIFT 1
bogdanm 66:9c8f0e3462fb 520 #define DAC_C0_LPEN_MASK 0x8u
bogdanm 66:9c8f0e3462fb 521 #define DAC_C0_LPEN_SHIFT 3
bogdanm 66:9c8f0e3462fb 522 #define DAC_C0_DACSWTRG_MASK 0x10u
bogdanm 66:9c8f0e3462fb 523 #define DAC_C0_DACSWTRG_SHIFT 4
bogdanm 66:9c8f0e3462fb 524 #define DAC_C0_DACTRGSEL_MASK 0x20u
bogdanm 66:9c8f0e3462fb 525 #define DAC_C0_DACTRGSEL_SHIFT 5
bogdanm 66:9c8f0e3462fb 526 #define DAC_C0_DACRFS_MASK 0x40u
bogdanm 66:9c8f0e3462fb 527 #define DAC_C0_DACRFS_SHIFT 6
bogdanm 66:9c8f0e3462fb 528 #define DAC_C0_DACEN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 529 #define DAC_C0_DACEN_SHIFT 7
bogdanm 66:9c8f0e3462fb 530 /* C1 Bit Fields */
bogdanm 66:9c8f0e3462fb 531 #define DAC_C1_DACBFEN_MASK 0x1u
bogdanm 66:9c8f0e3462fb 532 #define DAC_C1_DACBFEN_SHIFT 0
bogdanm 66:9c8f0e3462fb 533 #define DAC_C1_DACBFMD_MASK 0x4u
bogdanm 66:9c8f0e3462fb 534 #define DAC_C1_DACBFMD_SHIFT 2
bogdanm 66:9c8f0e3462fb 535 #define DAC_C1_DMAEN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 536 #define DAC_C1_DMAEN_SHIFT 7
bogdanm 66:9c8f0e3462fb 537 /* C2 Bit Fields */
bogdanm 66:9c8f0e3462fb 538 #define DAC_C2_DACBFUP_MASK 0x1u
bogdanm 66:9c8f0e3462fb 539 #define DAC_C2_DACBFUP_SHIFT 0
bogdanm 66:9c8f0e3462fb 540 #define DAC_C2_DACBFRP_MASK 0x10u
bogdanm 66:9c8f0e3462fb 541 #define DAC_C2_DACBFRP_SHIFT 4
bogdanm 66:9c8f0e3462fb 542
bogdanm 66:9c8f0e3462fb 543 /**
bogdanm 66:9c8f0e3462fb 544 * @}
bogdanm 66:9c8f0e3462fb 545 */ /* end of group DAC_Register_Masks */
bogdanm 66:9c8f0e3462fb 546
bogdanm 66:9c8f0e3462fb 547
bogdanm 66:9c8f0e3462fb 548 /* DAC - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 549 /** Peripheral DAC0 base address */
bogdanm 66:9c8f0e3462fb 550 #define DAC0_BASE (0x4003F000u)
bogdanm 66:9c8f0e3462fb 551 /** Peripheral DAC0 base pointer */
bogdanm 66:9c8f0e3462fb 552 #define DAC0 ((DAC_Type *)DAC0_BASE)
bogdanm 66:9c8f0e3462fb 553 /** Array initializer of DAC peripheral base pointers */
bogdanm 66:9c8f0e3462fb 554 #define DAC_BASES { DAC0 }
bogdanm 66:9c8f0e3462fb 555
bogdanm 66:9c8f0e3462fb 556 /**
bogdanm 66:9c8f0e3462fb 557 * @}
bogdanm 66:9c8f0e3462fb 558 */ /* end of group DAC_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 559
bogdanm 66:9c8f0e3462fb 560
bogdanm 66:9c8f0e3462fb 561 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 562 -- DMA Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 563 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 564
bogdanm 66:9c8f0e3462fb 565 /**
bogdanm 66:9c8f0e3462fb 566 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 567 * @{
bogdanm 66:9c8f0e3462fb 568 */
bogdanm 66:9c8f0e3462fb 569
bogdanm 66:9c8f0e3462fb 570 /** DMA - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 571 typedef struct {
bogdanm 66:9c8f0e3462fb 572 union { /* offset: 0x0 */
bogdanm 66:9c8f0e3462fb 573 __IO uint8_t REQC_ARR[4]; /**< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 */
bogdanm 66:9c8f0e3462fb 574 };
bogdanm 66:9c8f0e3462fb 575 uint8_t RESERVED_0[252];
bogdanm 66:9c8f0e3462fb 576 struct { /* offset: 0x100, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 577 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 578 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 579 union { /* offset: 0x108, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 580 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 581 struct { /* offset: 0x108, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 582 uint8_t RESERVED_0[3];
bogdanm 66:9c8f0e3462fb 583 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 584 } DMA_DSR_ACCESS8BIT;
bogdanm 66:9c8f0e3462fb 585 };
bogdanm 66:9c8f0e3462fb 586 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 587 } DMA[4];
bogdanm 66:9c8f0e3462fb 588 } DMA_Type;
bogdanm 66:9c8f0e3462fb 589
bogdanm 66:9c8f0e3462fb 590 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 591 -- DMA Register Masks
bogdanm 66:9c8f0e3462fb 592 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 593
bogdanm 66:9c8f0e3462fb 594 /**
bogdanm 66:9c8f0e3462fb 595 * @addtogroup DMA_Register_Masks DMA Register Masks
bogdanm 66:9c8f0e3462fb 596 * @{
bogdanm 66:9c8f0e3462fb 597 */
bogdanm 66:9c8f0e3462fb 598
bogdanm 66:9c8f0e3462fb 599 /* REQC_ARR Bit Fields */
bogdanm 66:9c8f0e3462fb 600 #define DMA_REQC_ARR_DMAC_MASK 0xFu
bogdanm 66:9c8f0e3462fb 601 #define DMA_REQC_ARR_DMAC_SHIFT 0
bogdanm 66:9c8f0e3462fb 602 #define DMA_REQC_ARR_DMAC(x) (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
bogdanm 66:9c8f0e3462fb 603 #define DMA_REQC_ARR_CFSM_MASK 0x80u
bogdanm 66:9c8f0e3462fb 604 #define DMA_REQC_ARR_CFSM_SHIFT 7
bogdanm 66:9c8f0e3462fb 605 /* SAR Bit Fields */
bogdanm 66:9c8f0e3462fb 606 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 607 #define DMA_SAR_SAR_SHIFT 0
bogdanm 66:9c8f0e3462fb 608 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
bogdanm 66:9c8f0e3462fb 609 /* DAR Bit Fields */
bogdanm 66:9c8f0e3462fb 610 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 611 #define DMA_DAR_DAR_SHIFT 0
bogdanm 66:9c8f0e3462fb 612 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
bogdanm 66:9c8f0e3462fb 613 /* DSR_BCR Bit Fields */
bogdanm 66:9c8f0e3462fb 614 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
bogdanm 66:9c8f0e3462fb 615 #define DMA_DSR_BCR_BCR_SHIFT 0
bogdanm 66:9c8f0e3462fb 616 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
bogdanm 66:9c8f0e3462fb 617 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
bogdanm 66:9c8f0e3462fb 618 #define DMA_DSR_BCR_DONE_SHIFT 24
bogdanm 66:9c8f0e3462fb 619 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
bogdanm 66:9c8f0e3462fb 620 #define DMA_DSR_BCR_BSY_SHIFT 25
bogdanm 66:9c8f0e3462fb 621 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
bogdanm 66:9c8f0e3462fb 622 #define DMA_DSR_BCR_REQ_SHIFT 26
bogdanm 66:9c8f0e3462fb 623 #define DMA_DSR_BCR_BED_MASK 0x10000000u
bogdanm 66:9c8f0e3462fb 624 #define DMA_DSR_BCR_BED_SHIFT 28
bogdanm 66:9c8f0e3462fb 625 #define DMA_DSR_BCR_BES_MASK 0x20000000u
bogdanm 66:9c8f0e3462fb 626 #define DMA_DSR_BCR_BES_SHIFT 29
bogdanm 66:9c8f0e3462fb 627 #define DMA_DSR_BCR_CE_MASK 0x40000000u
bogdanm 66:9c8f0e3462fb 628 #define DMA_DSR_BCR_CE_SHIFT 30
bogdanm 66:9c8f0e3462fb 629 /* DCR Bit Fields */
bogdanm 66:9c8f0e3462fb 630 #define DMA_DCR_LCH2_MASK 0x3u
bogdanm 66:9c8f0e3462fb 631 #define DMA_DCR_LCH2_SHIFT 0
bogdanm 66:9c8f0e3462fb 632 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
bogdanm 66:9c8f0e3462fb 633 #define DMA_DCR_LCH1_MASK 0xCu
bogdanm 66:9c8f0e3462fb 634 #define DMA_DCR_LCH1_SHIFT 2
bogdanm 66:9c8f0e3462fb 635 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
bogdanm 66:9c8f0e3462fb 636 #define DMA_DCR_LINKCC_MASK 0x30u
bogdanm 66:9c8f0e3462fb 637 #define DMA_DCR_LINKCC_SHIFT 4
bogdanm 66:9c8f0e3462fb 638 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
bogdanm 66:9c8f0e3462fb 639 #define DMA_DCR_D_REQ_MASK 0x80u
bogdanm 66:9c8f0e3462fb 640 #define DMA_DCR_D_REQ_SHIFT 7
bogdanm 66:9c8f0e3462fb 641 #define DMA_DCR_DMOD_MASK 0xF00u
bogdanm 66:9c8f0e3462fb 642 #define DMA_DCR_DMOD_SHIFT 8
bogdanm 66:9c8f0e3462fb 643 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
bogdanm 66:9c8f0e3462fb 644 #define DMA_DCR_SMOD_MASK 0xF000u
bogdanm 66:9c8f0e3462fb 645 #define DMA_DCR_SMOD_SHIFT 12
bogdanm 66:9c8f0e3462fb 646 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
bogdanm 66:9c8f0e3462fb 647 #define DMA_DCR_START_MASK 0x10000u
bogdanm 66:9c8f0e3462fb 648 #define DMA_DCR_START_SHIFT 16
bogdanm 66:9c8f0e3462fb 649 #define DMA_DCR_DSIZE_MASK 0x60000u
bogdanm 66:9c8f0e3462fb 650 #define DMA_DCR_DSIZE_SHIFT 17
bogdanm 66:9c8f0e3462fb 651 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
bogdanm 66:9c8f0e3462fb 652 #define DMA_DCR_DINC_MASK 0x80000u
bogdanm 66:9c8f0e3462fb 653 #define DMA_DCR_DINC_SHIFT 19
bogdanm 66:9c8f0e3462fb 654 #define DMA_DCR_SSIZE_MASK 0x300000u
bogdanm 66:9c8f0e3462fb 655 #define DMA_DCR_SSIZE_SHIFT 20
bogdanm 66:9c8f0e3462fb 656 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
bogdanm 66:9c8f0e3462fb 657 #define DMA_DCR_SINC_MASK 0x400000u
bogdanm 66:9c8f0e3462fb 658 #define DMA_DCR_SINC_SHIFT 22
bogdanm 66:9c8f0e3462fb 659 #define DMA_DCR_EADREQ_MASK 0x800000u
bogdanm 66:9c8f0e3462fb 660 #define DMA_DCR_EADREQ_SHIFT 23
bogdanm 66:9c8f0e3462fb 661 #define DMA_DCR_AA_MASK 0x10000000u
bogdanm 66:9c8f0e3462fb 662 #define DMA_DCR_AA_SHIFT 28
bogdanm 66:9c8f0e3462fb 663 #define DMA_DCR_CS_MASK 0x20000000u
bogdanm 66:9c8f0e3462fb 664 #define DMA_DCR_CS_SHIFT 29
bogdanm 66:9c8f0e3462fb 665 #define DMA_DCR_ERQ_MASK 0x40000000u
bogdanm 66:9c8f0e3462fb 666 #define DMA_DCR_ERQ_SHIFT 30
bogdanm 66:9c8f0e3462fb 667 #define DMA_DCR_EINT_MASK 0x80000000u
bogdanm 66:9c8f0e3462fb 668 #define DMA_DCR_EINT_SHIFT 31
bogdanm 66:9c8f0e3462fb 669
bogdanm 66:9c8f0e3462fb 670 /**
bogdanm 66:9c8f0e3462fb 671 * @}
bogdanm 66:9c8f0e3462fb 672 */ /* end of group DMA_Register_Masks */
bogdanm 66:9c8f0e3462fb 673
bogdanm 66:9c8f0e3462fb 674
bogdanm 66:9c8f0e3462fb 675 /* DMA - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 676 /** Peripheral DMA base address */
bogdanm 66:9c8f0e3462fb 677 #define DMA_BASE (0x40008000u)
bogdanm 66:9c8f0e3462fb 678 /** Peripheral DMA base pointer */
bogdanm 66:9c8f0e3462fb 679 #define DMA0 ((DMA_Type *)DMA_BASE)
bogdanm 66:9c8f0e3462fb 680 /** Array initializer of DMA peripheral base pointers */
bogdanm 66:9c8f0e3462fb 681 #define DMA_BASES { DMA0 }
bogdanm 66:9c8f0e3462fb 682
bogdanm 66:9c8f0e3462fb 683 /**
bogdanm 66:9c8f0e3462fb 684 * @}
bogdanm 66:9c8f0e3462fb 685 */ /* end of group DMA_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 686
bogdanm 66:9c8f0e3462fb 687
bogdanm 66:9c8f0e3462fb 688 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 689 -- DMAMUX Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 690 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 691
bogdanm 66:9c8f0e3462fb 692 /**
bogdanm 66:9c8f0e3462fb 693 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 694 * @{
bogdanm 66:9c8f0e3462fb 695 */
bogdanm 66:9c8f0e3462fb 696
bogdanm 66:9c8f0e3462fb 697 /** DMAMUX - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 698 typedef struct {
bogdanm 66:9c8f0e3462fb 699 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
bogdanm 66:9c8f0e3462fb 700 } DMAMUX_Type;
bogdanm 66:9c8f0e3462fb 701
bogdanm 66:9c8f0e3462fb 702 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 703 -- DMAMUX Register Masks
bogdanm 66:9c8f0e3462fb 704 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 705
bogdanm 66:9c8f0e3462fb 706 /**
bogdanm 66:9c8f0e3462fb 707 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
bogdanm 66:9c8f0e3462fb 708 * @{
bogdanm 66:9c8f0e3462fb 709 */
bogdanm 66:9c8f0e3462fb 710
bogdanm 66:9c8f0e3462fb 711 /* CHCFG Bit Fields */
bogdanm 66:9c8f0e3462fb 712 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
bogdanm 66:9c8f0e3462fb 713 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
bogdanm 66:9c8f0e3462fb 714 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
bogdanm 66:9c8f0e3462fb 715 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
bogdanm 66:9c8f0e3462fb 716 #define DMAMUX_CHCFG_TRIG_SHIFT 6
bogdanm 66:9c8f0e3462fb 717 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
bogdanm 66:9c8f0e3462fb 718 #define DMAMUX_CHCFG_ENBL_SHIFT 7
bogdanm 66:9c8f0e3462fb 719
bogdanm 66:9c8f0e3462fb 720 /**
bogdanm 66:9c8f0e3462fb 721 * @}
bogdanm 66:9c8f0e3462fb 722 */ /* end of group DMAMUX_Register_Masks */
bogdanm 66:9c8f0e3462fb 723
bogdanm 66:9c8f0e3462fb 724
bogdanm 66:9c8f0e3462fb 725 /* DMAMUX - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 726 /** Peripheral DMAMUX0 base address */
bogdanm 66:9c8f0e3462fb 727 #define DMAMUX0_BASE (0x40021000u)
bogdanm 66:9c8f0e3462fb 728 /** Peripheral DMAMUX0 base pointer */
bogdanm 66:9c8f0e3462fb 729 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
bogdanm 66:9c8f0e3462fb 730 /** Array initializer of DMAMUX peripheral base pointers */
bogdanm 66:9c8f0e3462fb 731 #define DMAMUX_BASES { DMAMUX0 }
bogdanm 66:9c8f0e3462fb 732
bogdanm 66:9c8f0e3462fb 733 /**
bogdanm 66:9c8f0e3462fb 734 * @}
bogdanm 66:9c8f0e3462fb 735 */ /* end of group DMAMUX_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 736
bogdanm 66:9c8f0e3462fb 737
bogdanm 66:9c8f0e3462fb 738 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 739 -- FGPIO Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 740 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 741
bogdanm 66:9c8f0e3462fb 742 /**
bogdanm 66:9c8f0e3462fb 743 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 744 * @{
bogdanm 66:9c8f0e3462fb 745 */
bogdanm 66:9c8f0e3462fb 746
bogdanm 66:9c8f0e3462fb 747 /** FGPIO - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 748 typedef struct {
bogdanm 66:9c8f0e3462fb 749 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 750 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 751 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 752 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
bogdanm 66:9c8f0e3462fb 753 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
bogdanm 66:9c8f0e3462fb 754 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
bogdanm 66:9c8f0e3462fb 755 } FGPIO_Type;
bogdanm 66:9c8f0e3462fb 756
bogdanm 66:9c8f0e3462fb 757 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 758 -- FGPIO Register Masks
bogdanm 66:9c8f0e3462fb 759 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 760
bogdanm 66:9c8f0e3462fb 761 /**
bogdanm 66:9c8f0e3462fb 762 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
bogdanm 66:9c8f0e3462fb 763 * @{
bogdanm 66:9c8f0e3462fb 764 */
bogdanm 66:9c8f0e3462fb 765
bogdanm 66:9c8f0e3462fb 766 /* PDOR Bit Fields */
bogdanm 66:9c8f0e3462fb 767 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 768 #define FGPIO_PDOR_PDO_SHIFT 0
bogdanm 66:9c8f0e3462fb 769 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
bogdanm 66:9c8f0e3462fb 770 /* PSOR Bit Fields */
bogdanm 66:9c8f0e3462fb 771 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 772 #define FGPIO_PSOR_PTSO_SHIFT 0
bogdanm 66:9c8f0e3462fb 773 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
bogdanm 66:9c8f0e3462fb 774 /* PCOR Bit Fields */
bogdanm 66:9c8f0e3462fb 775 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 776 #define FGPIO_PCOR_PTCO_SHIFT 0
bogdanm 66:9c8f0e3462fb 777 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
bogdanm 66:9c8f0e3462fb 778 /* PTOR Bit Fields */
bogdanm 66:9c8f0e3462fb 779 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 780 #define FGPIO_PTOR_PTTO_SHIFT 0
bogdanm 66:9c8f0e3462fb 781 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
bogdanm 66:9c8f0e3462fb 782 /* PDIR Bit Fields */
bogdanm 66:9c8f0e3462fb 783 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 784 #define FGPIO_PDIR_PDI_SHIFT 0
bogdanm 66:9c8f0e3462fb 785 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
bogdanm 66:9c8f0e3462fb 786 /* PDDR Bit Fields */
bogdanm 66:9c8f0e3462fb 787 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 788 #define FGPIO_PDDR_PDD_SHIFT 0
bogdanm 66:9c8f0e3462fb 789 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
bogdanm 66:9c8f0e3462fb 790
bogdanm 66:9c8f0e3462fb 791 /**
bogdanm 66:9c8f0e3462fb 792 * @}
bogdanm 66:9c8f0e3462fb 793 */ /* end of group FGPIO_Register_Masks */
bogdanm 66:9c8f0e3462fb 794
bogdanm 66:9c8f0e3462fb 795
bogdanm 66:9c8f0e3462fb 796 /* FGPIO - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 797 /** Peripheral FPTA base address */
bogdanm 66:9c8f0e3462fb 798 #define FPTA_BASE (0xF80FF000u)
bogdanm 66:9c8f0e3462fb 799 /** Peripheral FPTA base pointer */
bogdanm 66:9c8f0e3462fb 800 #define FPTA ((FGPIO_Type *)FPTA_BASE)
bogdanm 66:9c8f0e3462fb 801 /** Peripheral FPTB base address */
bogdanm 66:9c8f0e3462fb 802 #define FPTB_BASE (0xF80FF040u)
bogdanm 66:9c8f0e3462fb 803 /** Peripheral FPTB base pointer */
bogdanm 66:9c8f0e3462fb 804 #define FPTB ((FGPIO_Type *)FPTB_BASE)
bogdanm 66:9c8f0e3462fb 805 /** Peripheral FPTC base address */
bogdanm 66:9c8f0e3462fb 806 #define FPTC_BASE (0xF80FF080u)
bogdanm 66:9c8f0e3462fb 807 /** Peripheral FPTC base pointer */
bogdanm 66:9c8f0e3462fb 808 #define FPTC ((FGPIO_Type *)FPTC_BASE)
bogdanm 66:9c8f0e3462fb 809 /** Peripheral FPTD base address */
bogdanm 66:9c8f0e3462fb 810 #define FPTD_BASE (0xF80FF0C0u)
bogdanm 66:9c8f0e3462fb 811 /** Peripheral FPTD base pointer */
bogdanm 66:9c8f0e3462fb 812 #define FPTD ((FGPIO_Type *)FPTD_BASE)
bogdanm 66:9c8f0e3462fb 813 /** Peripheral FPTE base address */
bogdanm 66:9c8f0e3462fb 814 #define FPTE_BASE (0xF80FF100u)
bogdanm 66:9c8f0e3462fb 815 /** Peripheral FPTE base pointer */
bogdanm 66:9c8f0e3462fb 816 #define FPTE ((FGPIO_Type *)FPTE_BASE)
bogdanm 66:9c8f0e3462fb 817 /** Array initializer of FGPIO peripheral base pointers */
bogdanm 66:9c8f0e3462fb 818 #define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
bogdanm 66:9c8f0e3462fb 819
bogdanm 66:9c8f0e3462fb 820 /**
bogdanm 66:9c8f0e3462fb 821 * @}
bogdanm 66:9c8f0e3462fb 822 */ /* end of group FGPIO_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 823
bogdanm 66:9c8f0e3462fb 824
bogdanm 66:9c8f0e3462fb 825 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 826 -- FTFA Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 827 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 828
bogdanm 66:9c8f0e3462fb 829 /**
bogdanm 66:9c8f0e3462fb 830 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 831 * @{
bogdanm 66:9c8f0e3462fb 832 */
bogdanm 66:9c8f0e3462fb 833
bogdanm 66:9c8f0e3462fb 834 /** FTFA - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 835 typedef struct {
bogdanm 66:9c8f0e3462fb 836 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 837 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
bogdanm 66:9c8f0e3462fb 838 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
bogdanm 66:9c8f0e3462fb 839 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
bogdanm 66:9c8f0e3462fb 840 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 841 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
bogdanm 66:9c8f0e3462fb 842 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
bogdanm 66:9c8f0e3462fb 843 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
bogdanm 66:9c8f0e3462fb 844 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 845 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
bogdanm 66:9c8f0e3462fb 846 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
bogdanm 66:9c8f0e3462fb 847 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
bogdanm 66:9c8f0e3462fb 848 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
bogdanm 66:9c8f0e3462fb 849 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
bogdanm 66:9c8f0e3462fb 850 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
bogdanm 66:9c8f0e3462fb 851 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
bogdanm 66:9c8f0e3462fb 852 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
bogdanm 66:9c8f0e3462fb 853 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
bogdanm 66:9c8f0e3462fb 854 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
bogdanm 66:9c8f0e3462fb 855 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
bogdanm 66:9c8f0e3462fb 856 } FTFA_Type;
bogdanm 66:9c8f0e3462fb 857
bogdanm 66:9c8f0e3462fb 858 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 859 -- FTFA Register Masks
bogdanm 66:9c8f0e3462fb 860 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 861
bogdanm 66:9c8f0e3462fb 862 /**
bogdanm 66:9c8f0e3462fb 863 * @addtogroup FTFA_Register_Masks FTFA Register Masks
bogdanm 66:9c8f0e3462fb 864 * @{
bogdanm 66:9c8f0e3462fb 865 */
bogdanm 66:9c8f0e3462fb 866
bogdanm 66:9c8f0e3462fb 867 /* FSTAT Bit Fields */
bogdanm 66:9c8f0e3462fb 868 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
bogdanm 66:9c8f0e3462fb 869 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
bogdanm 66:9c8f0e3462fb 870 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
bogdanm 66:9c8f0e3462fb 871 #define FTFA_FSTAT_FPVIOL_SHIFT 4
bogdanm 66:9c8f0e3462fb 872 #define FTFA_FSTAT_ACCERR_MASK 0x20u
bogdanm 66:9c8f0e3462fb 873 #define FTFA_FSTAT_ACCERR_SHIFT 5
bogdanm 66:9c8f0e3462fb 874 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
bogdanm 66:9c8f0e3462fb 875 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
bogdanm 66:9c8f0e3462fb 876 #define FTFA_FSTAT_CCIF_MASK 0x80u
bogdanm 66:9c8f0e3462fb 877 #define FTFA_FSTAT_CCIF_SHIFT 7
bogdanm 66:9c8f0e3462fb 878 /* FCNFG Bit Fields */
bogdanm 66:9c8f0e3462fb 879 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
bogdanm 66:9c8f0e3462fb 880 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
bogdanm 66:9c8f0e3462fb 881 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
bogdanm 66:9c8f0e3462fb 882 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
bogdanm 66:9c8f0e3462fb 883 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 884 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
bogdanm 66:9c8f0e3462fb 885 #define FTFA_FCNFG_CCIE_MASK 0x80u
bogdanm 66:9c8f0e3462fb 886 #define FTFA_FCNFG_CCIE_SHIFT 7
bogdanm 66:9c8f0e3462fb 887 /* FSEC Bit Fields */
bogdanm 66:9c8f0e3462fb 888 #define FTFA_FSEC_SEC_MASK 0x3u
bogdanm 66:9c8f0e3462fb 889 #define FTFA_FSEC_SEC_SHIFT 0
bogdanm 66:9c8f0e3462fb 890 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
bogdanm 66:9c8f0e3462fb 891 #define FTFA_FSEC_FSLACC_MASK 0xCu
bogdanm 66:9c8f0e3462fb 892 #define FTFA_FSEC_FSLACC_SHIFT 2
bogdanm 66:9c8f0e3462fb 893 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
bogdanm 66:9c8f0e3462fb 894 #define FTFA_FSEC_MEEN_MASK 0x30u
bogdanm 66:9c8f0e3462fb 895 #define FTFA_FSEC_MEEN_SHIFT 4
bogdanm 66:9c8f0e3462fb 896 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
bogdanm 66:9c8f0e3462fb 897 #define FTFA_FSEC_KEYEN_MASK 0xC0u
bogdanm 66:9c8f0e3462fb 898 #define FTFA_FSEC_KEYEN_SHIFT 6
bogdanm 66:9c8f0e3462fb 899 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
bogdanm 66:9c8f0e3462fb 900 /* FOPT Bit Fields */
bogdanm 66:9c8f0e3462fb 901 #define FTFA_FOPT_OPT_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 902 #define FTFA_FOPT_OPT_SHIFT 0
bogdanm 66:9c8f0e3462fb 903 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
bogdanm 66:9c8f0e3462fb 904 /* FCCOB3 Bit Fields */
bogdanm 66:9c8f0e3462fb 905 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 906 #define FTFA_FCCOB3_CCOBn_SHIFT 0
bogdanm 66:9c8f0e3462fb 907 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
bogdanm 66:9c8f0e3462fb 908 /* FCCOB2 Bit Fields */
bogdanm 66:9c8f0e3462fb 909 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 910 #define FTFA_FCCOB2_CCOBn_SHIFT 0
bogdanm 66:9c8f0e3462fb 911 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
bogdanm 66:9c8f0e3462fb 912 /* FCCOB1 Bit Fields */
bogdanm 66:9c8f0e3462fb 913 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 914 #define FTFA_FCCOB1_CCOBn_SHIFT 0
bogdanm 66:9c8f0e3462fb 915 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
bogdanm 66:9c8f0e3462fb 916 /* FCCOB0 Bit Fields */
bogdanm 66:9c8f0e3462fb 917 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 918 #define FTFA_FCCOB0_CCOBn_SHIFT 0
bogdanm 66:9c8f0e3462fb 919 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
bogdanm 66:9c8f0e3462fb 920 /* FCCOB7 Bit Fields */
bogdanm 66:9c8f0e3462fb 921 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 922 #define FTFA_FCCOB7_CCOBn_SHIFT 0
bogdanm 66:9c8f0e3462fb 923 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
bogdanm 66:9c8f0e3462fb 924 /* FCCOB6 Bit Fields */
bogdanm 66:9c8f0e3462fb 925 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 926 #define FTFA_FCCOB6_CCOBn_SHIFT 0
bogdanm 66:9c8f0e3462fb 927 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
bogdanm 66:9c8f0e3462fb 928 /* FCCOB5 Bit Fields */
bogdanm 66:9c8f0e3462fb 929 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 930 #define FTFA_FCCOB5_CCOBn_SHIFT 0
bogdanm 66:9c8f0e3462fb 931 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
bogdanm 66:9c8f0e3462fb 932 /* FCCOB4 Bit Fields */
bogdanm 66:9c8f0e3462fb 933 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 934 #define FTFA_FCCOB4_CCOBn_SHIFT 0
bogdanm 66:9c8f0e3462fb 935 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
bogdanm 66:9c8f0e3462fb 936 /* FCCOBB Bit Fields */
bogdanm 66:9c8f0e3462fb 937 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 938 #define FTFA_FCCOBB_CCOBn_SHIFT 0
bogdanm 66:9c8f0e3462fb 939 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
bogdanm 66:9c8f0e3462fb 940 /* FCCOBA Bit Fields */
bogdanm 66:9c8f0e3462fb 941 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 942 #define FTFA_FCCOBA_CCOBn_SHIFT 0
bogdanm 66:9c8f0e3462fb 943 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
bogdanm 66:9c8f0e3462fb 944 /* FCCOB9 Bit Fields */
bogdanm 66:9c8f0e3462fb 945 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 946 #define FTFA_FCCOB9_CCOBn_SHIFT 0
bogdanm 66:9c8f0e3462fb 947 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
bogdanm 66:9c8f0e3462fb 948 /* FCCOB8 Bit Fields */
bogdanm 66:9c8f0e3462fb 949 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 950 #define FTFA_FCCOB8_CCOBn_SHIFT 0
bogdanm 66:9c8f0e3462fb 951 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
bogdanm 66:9c8f0e3462fb 952 /* FPROT3 Bit Fields */
bogdanm 66:9c8f0e3462fb 953 #define FTFA_FPROT3_PROT_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 954 #define FTFA_FPROT3_PROT_SHIFT 0
bogdanm 66:9c8f0e3462fb 955 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
bogdanm 66:9c8f0e3462fb 956 /* FPROT2 Bit Fields */
bogdanm 66:9c8f0e3462fb 957 #define FTFA_FPROT2_PROT_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 958 #define FTFA_FPROT2_PROT_SHIFT 0
bogdanm 66:9c8f0e3462fb 959 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
bogdanm 66:9c8f0e3462fb 960 /* FPROT1 Bit Fields */
bogdanm 66:9c8f0e3462fb 961 #define FTFA_FPROT1_PROT_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 962 #define FTFA_FPROT1_PROT_SHIFT 0
bogdanm 66:9c8f0e3462fb 963 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
bogdanm 66:9c8f0e3462fb 964 /* FPROT0 Bit Fields */
bogdanm 66:9c8f0e3462fb 965 #define FTFA_FPROT0_PROT_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 966 #define FTFA_FPROT0_PROT_SHIFT 0
bogdanm 66:9c8f0e3462fb 967 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
bogdanm 66:9c8f0e3462fb 968
bogdanm 66:9c8f0e3462fb 969 /**
bogdanm 66:9c8f0e3462fb 970 * @}
bogdanm 66:9c8f0e3462fb 971 */ /* end of group FTFA_Register_Masks */
bogdanm 66:9c8f0e3462fb 972
bogdanm 66:9c8f0e3462fb 973
bogdanm 66:9c8f0e3462fb 974 /* FTFA - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 975 /** Peripheral FTFA base address */
bogdanm 66:9c8f0e3462fb 976 #define FTFA_BASE (0x40020000u)
bogdanm 66:9c8f0e3462fb 977 /** Peripheral FTFA base pointer */
bogdanm 66:9c8f0e3462fb 978 #define FTFA ((FTFA_Type *)FTFA_BASE)
bogdanm 66:9c8f0e3462fb 979 /** Array initializer of FTFA peripheral base pointers */
bogdanm 66:9c8f0e3462fb 980 #define FTFA_BASES { FTFA }
bogdanm 66:9c8f0e3462fb 981
bogdanm 66:9c8f0e3462fb 982 /**
bogdanm 66:9c8f0e3462fb 983 * @}
bogdanm 66:9c8f0e3462fb 984 */ /* end of group FTFA_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 985
bogdanm 66:9c8f0e3462fb 986
bogdanm 66:9c8f0e3462fb 987 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 988 -- GPIO Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 989 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 990
bogdanm 66:9c8f0e3462fb 991 /**
bogdanm 66:9c8f0e3462fb 992 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 993 * @{
bogdanm 66:9c8f0e3462fb 994 */
bogdanm 66:9c8f0e3462fb 995
bogdanm 66:9c8f0e3462fb 996 /** GPIO - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 997 typedef struct {
bogdanm 66:9c8f0e3462fb 998 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 999 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 1000 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 1001 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
bogdanm 66:9c8f0e3462fb 1002 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
bogdanm 66:9c8f0e3462fb 1003 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
bogdanm 66:9c8f0e3462fb 1004 } GPIO_Type;
bogdanm 66:9c8f0e3462fb 1005
bogdanm 66:9c8f0e3462fb 1006 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1007 -- GPIO Register Masks
bogdanm 66:9c8f0e3462fb 1008 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1009
bogdanm 66:9c8f0e3462fb 1010 /**
bogdanm 66:9c8f0e3462fb 1011 * @addtogroup GPIO_Register_Masks GPIO Register Masks
bogdanm 66:9c8f0e3462fb 1012 * @{
bogdanm 66:9c8f0e3462fb 1013 */
bogdanm 66:9c8f0e3462fb 1014
bogdanm 66:9c8f0e3462fb 1015 /* PDOR Bit Fields */
bogdanm 66:9c8f0e3462fb 1016 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1017 #define GPIO_PDOR_PDO_SHIFT 0
bogdanm 66:9c8f0e3462fb 1018 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
bogdanm 66:9c8f0e3462fb 1019 /* PSOR Bit Fields */
bogdanm 66:9c8f0e3462fb 1020 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1021 #define GPIO_PSOR_PTSO_SHIFT 0
bogdanm 66:9c8f0e3462fb 1022 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
bogdanm 66:9c8f0e3462fb 1023 /* PCOR Bit Fields */
bogdanm 66:9c8f0e3462fb 1024 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1025 #define GPIO_PCOR_PTCO_SHIFT 0
bogdanm 66:9c8f0e3462fb 1026 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
bogdanm 66:9c8f0e3462fb 1027 /* PTOR Bit Fields */
bogdanm 66:9c8f0e3462fb 1028 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1029 #define GPIO_PTOR_PTTO_SHIFT 0
bogdanm 66:9c8f0e3462fb 1030 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
bogdanm 66:9c8f0e3462fb 1031 /* PDIR Bit Fields */
bogdanm 66:9c8f0e3462fb 1032 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1033 #define GPIO_PDIR_PDI_SHIFT 0
bogdanm 66:9c8f0e3462fb 1034 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
bogdanm 66:9c8f0e3462fb 1035 /* PDDR Bit Fields */
bogdanm 66:9c8f0e3462fb 1036 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1037 #define GPIO_PDDR_PDD_SHIFT 0
bogdanm 66:9c8f0e3462fb 1038 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
bogdanm 66:9c8f0e3462fb 1039
bogdanm 66:9c8f0e3462fb 1040 /**
bogdanm 66:9c8f0e3462fb 1041 * @}
bogdanm 66:9c8f0e3462fb 1042 */ /* end of group GPIO_Register_Masks */
bogdanm 66:9c8f0e3462fb 1043
bogdanm 66:9c8f0e3462fb 1044
bogdanm 66:9c8f0e3462fb 1045 /* GPIO - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 1046 /** Peripheral PTA base address */
bogdanm 66:9c8f0e3462fb 1047 #define PTA_BASE (0x400FF000u)
bogdanm 66:9c8f0e3462fb 1048 /** Peripheral PTA base pointer */
bogdanm 66:9c8f0e3462fb 1049 #define PTA ((GPIO_Type *)PTA_BASE)
bogdanm 66:9c8f0e3462fb 1050 /** Peripheral PTB base address */
bogdanm 66:9c8f0e3462fb 1051 #define PTB_BASE (0x400FF040u)
bogdanm 66:9c8f0e3462fb 1052 /** Peripheral PTB base pointer */
bogdanm 66:9c8f0e3462fb 1053 #define PTB ((GPIO_Type *)PTB_BASE)
bogdanm 66:9c8f0e3462fb 1054 /** Peripheral PTC base address */
bogdanm 66:9c8f0e3462fb 1055 #define PTC_BASE (0x400FF080u)
bogdanm 66:9c8f0e3462fb 1056 /** Peripheral PTC base pointer */
bogdanm 66:9c8f0e3462fb 1057 #define PTC ((GPIO_Type *)PTC_BASE)
bogdanm 66:9c8f0e3462fb 1058 /** Peripheral PTD base address */
bogdanm 66:9c8f0e3462fb 1059 #define PTD_BASE (0x400FF0C0u)
bogdanm 66:9c8f0e3462fb 1060 /** Peripheral PTD base pointer */
bogdanm 66:9c8f0e3462fb 1061 #define PTD ((GPIO_Type *)PTD_BASE)
bogdanm 66:9c8f0e3462fb 1062 /** Peripheral PTE base address */
bogdanm 66:9c8f0e3462fb 1063 #define PTE_BASE (0x400FF100u)
bogdanm 66:9c8f0e3462fb 1064 /** Peripheral PTE base pointer */
bogdanm 66:9c8f0e3462fb 1065 #define PTE ((GPIO_Type *)PTE_BASE)
bogdanm 66:9c8f0e3462fb 1066 /** Array initializer of GPIO peripheral base pointers */
bogdanm 66:9c8f0e3462fb 1067 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
bogdanm 66:9c8f0e3462fb 1068
bogdanm 66:9c8f0e3462fb 1069 /**
bogdanm 66:9c8f0e3462fb 1070 * @}
bogdanm 66:9c8f0e3462fb 1071 */ /* end of group GPIO_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 1072
bogdanm 66:9c8f0e3462fb 1073
bogdanm 66:9c8f0e3462fb 1074 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1075 -- I2C Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1076 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1077
bogdanm 66:9c8f0e3462fb 1078 /**
bogdanm 66:9c8f0e3462fb 1079 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1080 * @{
bogdanm 66:9c8f0e3462fb 1081 */
bogdanm 66:9c8f0e3462fb 1082
bogdanm 66:9c8f0e3462fb 1083 /** I2C - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 1084 typedef struct {
bogdanm 66:9c8f0e3462fb 1085 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 1086 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
bogdanm 66:9c8f0e3462fb 1087 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
bogdanm 66:9c8f0e3462fb 1088 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
bogdanm 66:9c8f0e3462fb 1089 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 1090 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
bogdanm 66:9c8f0e3462fb 1091 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
bogdanm 66:9c8f0e3462fb 1092 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
bogdanm 66:9c8f0e3462fb 1093 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 1094 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
bogdanm 66:9c8f0e3462fb 1095 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
bogdanm 66:9c8f0e3462fb 1096 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
bogdanm 66:9c8f0e3462fb 1097 } I2C_Type;
bogdanm 66:9c8f0e3462fb 1098
bogdanm 66:9c8f0e3462fb 1099 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1100 -- I2C Register Masks
bogdanm 66:9c8f0e3462fb 1101 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1102
bogdanm 66:9c8f0e3462fb 1103 /**
bogdanm 66:9c8f0e3462fb 1104 * @addtogroup I2C_Register_Masks I2C Register Masks
bogdanm 66:9c8f0e3462fb 1105 * @{
bogdanm 66:9c8f0e3462fb 1106 */
bogdanm 66:9c8f0e3462fb 1107
bogdanm 66:9c8f0e3462fb 1108 /* A1 Bit Fields */
bogdanm 66:9c8f0e3462fb 1109 #define I2C_A1_AD_MASK 0xFEu
bogdanm 66:9c8f0e3462fb 1110 #define I2C_A1_AD_SHIFT 1
bogdanm 66:9c8f0e3462fb 1111 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
bogdanm 66:9c8f0e3462fb 1112 /* F Bit Fields */
bogdanm 66:9c8f0e3462fb 1113 #define I2C_F_ICR_MASK 0x3Fu
bogdanm 66:9c8f0e3462fb 1114 #define I2C_F_ICR_SHIFT 0
bogdanm 66:9c8f0e3462fb 1115 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
bogdanm 66:9c8f0e3462fb 1116 #define I2C_F_MULT_MASK 0xC0u
bogdanm 66:9c8f0e3462fb 1117 #define I2C_F_MULT_SHIFT 6
bogdanm 66:9c8f0e3462fb 1118 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
bogdanm 66:9c8f0e3462fb 1119 /* C1 Bit Fields */
bogdanm 66:9c8f0e3462fb 1120 #define I2C_C1_DMAEN_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1121 #define I2C_C1_DMAEN_SHIFT 0
bogdanm 66:9c8f0e3462fb 1122 #define I2C_C1_WUEN_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1123 #define I2C_C1_WUEN_SHIFT 1
bogdanm 66:9c8f0e3462fb 1124 #define I2C_C1_RSTA_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1125 #define I2C_C1_RSTA_SHIFT 2
bogdanm 66:9c8f0e3462fb 1126 #define I2C_C1_TXAK_MASK 0x8u
bogdanm 66:9c8f0e3462fb 1127 #define I2C_C1_TXAK_SHIFT 3
bogdanm 66:9c8f0e3462fb 1128 #define I2C_C1_TX_MASK 0x10u
bogdanm 66:9c8f0e3462fb 1129 #define I2C_C1_TX_SHIFT 4
bogdanm 66:9c8f0e3462fb 1130 #define I2C_C1_MST_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1131 #define I2C_C1_MST_SHIFT 5
bogdanm 66:9c8f0e3462fb 1132 #define I2C_C1_IICIE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1133 #define I2C_C1_IICIE_SHIFT 6
bogdanm 66:9c8f0e3462fb 1134 #define I2C_C1_IICEN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1135 #define I2C_C1_IICEN_SHIFT 7
bogdanm 66:9c8f0e3462fb 1136 /* S Bit Fields */
bogdanm 66:9c8f0e3462fb 1137 #define I2C_S_RXAK_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1138 #define I2C_S_RXAK_SHIFT 0
bogdanm 66:9c8f0e3462fb 1139 #define I2C_S_IICIF_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1140 #define I2C_S_IICIF_SHIFT 1
bogdanm 66:9c8f0e3462fb 1141 #define I2C_S_SRW_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1142 #define I2C_S_SRW_SHIFT 2
bogdanm 66:9c8f0e3462fb 1143 #define I2C_S_RAM_MASK 0x8u
bogdanm 66:9c8f0e3462fb 1144 #define I2C_S_RAM_SHIFT 3
bogdanm 66:9c8f0e3462fb 1145 #define I2C_S_ARBL_MASK 0x10u
bogdanm 66:9c8f0e3462fb 1146 #define I2C_S_ARBL_SHIFT 4
bogdanm 66:9c8f0e3462fb 1147 #define I2C_S_BUSY_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1148 #define I2C_S_BUSY_SHIFT 5
bogdanm 66:9c8f0e3462fb 1149 #define I2C_S_IAAS_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1150 #define I2C_S_IAAS_SHIFT 6
bogdanm 66:9c8f0e3462fb 1151 #define I2C_S_TCF_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1152 #define I2C_S_TCF_SHIFT 7
bogdanm 66:9c8f0e3462fb 1153 /* D Bit Fields */
bogdanm 66:9c8f0e3462fb 1154 #define I2C_D_DATA_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 1155 #define I2C_D_DATA_SHIFT 0
bogdanm 66:9c8f0e3462fb 1156 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
bogdanm 66:9c8f0e3462fb 1157 /* C2 Bit Fields */
bogdanm 66:9c8f0e3462fb 1158 #define I2C_C2_AD_MASK 0x7u
bogdanm 66:9c8f0e3462fb 1159 #define I2C_C2_AD_SHIFT 0
bogdanm 66:9c8f0e3462fb 1160 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
bogdanm 66:9c8f0e3462fb 1161 #define I2C_C2_RMEN_MASK 0x8u
bogdanm 66:9c8f0e3462fb 1162 #define I2C_C2_RMEN_SHIFT 3
bogdanm 66:9c8f0e3462fb 1163 #define I2C_C2_SBRC_MASK 0x10u
bogdanm 66:9c8f0e3462fb 1164 #define I2C_C2_SBRC_SHIFT 4
bogdanm 66:9c8f0e3462fb 1165 #define I2C_C2_HDRS_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1166 #define I2C_C2_HDRS_SHIFT 5
bogdanm 66:9c8f0e3462fb 1167 #define I2C_C2_ADEXT_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1168 #define I2C_C2_ADEXT_SHIFT 6
bogdanm 66:9c8f0e3462fb 1169 #define I2C_C2_GCAEN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1170 #define I2C_C2_GCAEN_SHIFT 7
bogdanm 66:9c8f0e3462fb 1171 /* FLT Bit Fields */
bogdanm 66:9c8f0e3462fb 1172 #define I2C_FLT_FLT_MASK 0x1Fu
bogdanm 66:9c8f0e3462fb 1173 #define I2C_FLT_FLT_SHIFT 0
bogdanm 66:9c8f0e3462fb 1174 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
bogdanm 66:9c8f0e3462fb 1175 #define I2C_FLT_STOPIE_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1176 #define I2C_FLT_STOPIE_SHIFT 5
bogdanm 66:9c8f0e3462fb 1177 #define I2C_FLT_STOPF_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1178 #define I2C_FLT_STOPF_SHIFT 6
bogdanm 66:9c8f0e3462fb 1179 #define I2C_FLT_SHEN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1180 #define I2C_FLT_SHEN_SHIFT 7
bogdanm 66:9c8f0e3462fb 1181 /* RA Bit Fields */
bogdanm 66:9c8f0e3462fb 1182 #define I2C_RA_RAD_MASK 0xFEu
bogdanm 66:9c8f0e3462fb 1183 #define I2C_RA_RAD_SHIFT 1
bogdanm 66:9c8f0e3462fb 1184 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
bogdanm 66:9c8f0e3462fb 1185 /* SMB Bit Fields */
bogdanm 66:9c8f0e3462fb 1186 #define I2C_SMB_SHTF2IE_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1187 #define I2C_SMB_SHTF2IE_SHIFT 0
bogdanm 66:9c8f0e3462fb 1188 #define I2C_SMB_SHTF2_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1189 #define I2C_SMB_SHTF2_SHIFT 1
bogdanm 66:9c8f0e3462fb 1190 #define I2C_SMB_SHTF1_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1191 #define I2C_SMB_SHTF1_SHIFT 2
bogdanm 66:9c8f0e3462fb 1192 #define I2C_SMB_SLTF_MASK 0x8u
bogdanm 66:9c8f0e3462fb 1193 #define I2C_SMB_SLTF_SHIFT 3
bogdanm 66:9c8f0e3462fb 1194 #define I2C_SMB_TCKSEL_MASK 0x10u
bogdanm 66:9c8f0e3462fb 1195 #define I2C_SMB_TCKSEL_SHIFT 4
bogdanm 66:9c8f0e3462fb 1196 #define I2C_SMB_SIICAEN_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1197 #define I2C_SMB_SIICAEN_SHIFT 5
bogdanm 66:9c8f0e3462fb 1198 #define I2C_SMB_ALERTEN_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1199 #define I2C_SMB_ALERTEN_SHIFT 6
bogdanm 66:9c8f0e3462fb 1200 #define I2C_SMB_FACK_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1201 #define I2C_SMB_FACK_SHIFT 7
bogdanm 66:9c8f0e3462fb 1202 /* A2 Bit Fields */
bogdanm 66:9c8f0e3462fb 1203 #define I2C_A2_SAD_MASK 0xFEu
bogdanm 66:9c8f0e3462fb 1204 #define I2C_A2_SAD_SHIFT 1
bogdanm 66:9c8f0e3462fb 1205 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
bogdanm 66:9c8f0e3462fb 1206 /* SLTH Bit Fields */
bogdanm 66:9c8f0e3462fb 1207 #define I2C_SLTH_SSLT_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 1208 #define I2C_SLTH_SSLT_SHIFT 0
bogdanm 66:9c8f0e3462fb 1209 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
bogdanm 66:9c8f0e3462fb 1210 /* SLTL Bit Fields */
bogdanm 66:9c8f0e3462fb 1211 #define I2C_SLTL_SSLT_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 1212 #define I2C_SLTL_SSLT_SHIFT 0
bogdanm 66:9c8f0e3462fb 1213 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
bogdanm 66:9c8f0e3462fb 1214
bogdanm 66:9c8f0e3462fb 1215 /**
bogdanm 66:9c8f0e3462fb 1216 * @}
bogdanm 66:9c8f0e3462fb 1217 */ /* end of group I2C_Register_Masks */
bogdanm 66:9c8f0e3462fb 1218
bogdanm 66:9c8f0e3462fb 1219
bogdanm 66:9c8f0e3462fb 1220 /* I2C - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 1221 /** Peripheral I2C0 base address */
bogdanm 66:9c8f0e3462fb 1222 #define I2C0_BASE (0x40066000u)
bogdanm 66:9c8f0e3462fb 1223 /** Peripheral I2C0 base pointer */
bogdanm 66:9c8f0e3462fb 1224 #define I2C0 ((I2C_Type *)I2C0_BASE)
bogdanm 66:9c8f0e3462fb 1225 /** Peripheral I2C1 base address */
bogdanm 66:9c8f0e3462fb 1226 #define I2C1_BASE (0x40067000u)
bogdanm 66:9c8f0e3462fb 1227 /** Peripheral I2C1 base pointer */
bogdanm 66:9c8f0e3462fb 1228 #define I2C1 ((I2C_Type *)I2C1_BASE)
bogdanm 66:9c8f0e3462fb 1229 /** Array initializer of I2C peripheral base pointers */
bogdanm 66:9c8f0e3462fb 1230 #define I2C_BASES { I2C0, I2C1 }
bogdanm 66:9c8f0e3462fb 1231
bogdanm 66:9c8f0e3462fb 1232 /**
bogdanm 66:9c8f0e3462fb 1233 * @}
bogdanm 66:9c8f0e3462fb 1234 */ /* end of group I2C_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 1235
bogdanm 66:9c8f0e3462fb 1236
bogdanm 66:9c8f0e3462fb 1237 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1238 -- LLWU Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1239 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1240
bogdanm 66:9c8f0e3462fb 1241 /**
bogdanm 66:9c8f0e3462fb 1242 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1243 * @{
bogdanm 66:9c8f0e3462fb 1244 */
bogdanm 66:9c8f0e3462fb 1245
bogdanm 66:9c8f0e3462fb 1246 /** LLWU - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 1247 typedef struct {
bogdanm 66:9c8f0e3462fb 1248 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 1249 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
bogdanm 66:9c8f0e3462fb 1250 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
bogdanm 66:9c8f0e3462fb 1251 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
bogdanm 66:9c8f0e3462fb 1252 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 1253 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
bogdanm 66:9c8f0e3462fb 1254 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
bogdanm 66:9c8f0e3462fb 1255 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
bogdanm 66:9c8f0e3462fb 1256 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 1257 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
bogdanm 66:9c8f0e3462fb 1258 } LLWU_Type;
bogdanm 66:9c8f0e3462fb 1259
bogdanm 66:9c8f0e3462fb 1260 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1261 -- LLWU Register Masks
bogdanm 66:9c8f0e3462fb 1262 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1263
bogdanm 66:9c8f0e3462fb 1264 /**
bogdanm 66:9c8f0e3462fb 1265 * @addtogroup LLWU_Register_Masks LLWU Register Masks
bogdanm 66:9c8f0e3462fb 1266 * @{
bogdanm 66:9c8f0e3462fb 1267 */
bogdanm 66:9c8f0e3462fb 1268
bogdanm 66:9c8f0e3462fb 1269 /* PE1 Bit Fields */
bogdanm 66:9c8f0e3462fb 1270 #define LLWU_PE1_WUPE0_MASK 0x3u
bogdanm 66:9c8f0e3462fb 1271 #define LLWU_PE1_WUPE0_SHIFT 0
bogdanm 66:9c8f0e3462fb 1272 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
bogdanm 66:9c8f0e3462fb 1273 #define LLWU_PE1_WUPE1_MASK 0xCu
bogdanm 66:9c8f0e3462fb 1274 #define LLWU_PE1_WUPE1_SHIFT 2
bogdanm 66:9c8f0e3462fb 1275 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
bogdanm 66:9c8f0e3462fb 1276 #define LLWU_PE1_WUPE2_MASK 0x30u
bogdanm 66:9c8f0e3462fb 1277 #define LLWU_PE1_WUPE2_SHIFT 4
bogdanm 66:9c8f0e3462fb 1278 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
bogdanm 66:9c8f0e3462fb 1279 #define LLWU_PE1_WUPE3_MASK 0xC0u
bogdanm 66:9c8f0e3462fb 1280 #define LLWU_PE1_WUPE3_SHIFT 6
bogdanm 66:9c8f0e3462fb 1281 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
bogdanm 66:9c8f0e3462fb 1282 /* PE2 Bit Fields */
bogdanm 66:9c8f0e3462fb 1283 #define LLWU_PE2_WUPE4_MASK 0x3u
bogdanm 66:9c8f0e3462fb 1284 #define LLWU_PE2_WUPE4_SHIFT 0
bogdanm 66:9c8f0e3462fb 1285 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
bogdanm 66:9c8f0e3462fb 1286 #define LLWU_PE2_WUPE5_MASK 0xCu
bogdanm 66:9c8f0e3462fb 1287 #define LLWU_PE2_WUPE5_SHIFT 2
bogdanm 66:9c8f0e3462fb 1288 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
bogdanm 66:9c8f0e3462fb 1289 #define LLWU_PE2_WUPE6_MASK 0x30u
bogdanm 66:9c8f0e3462fb 1290 #define LLWU_PE2_WUPE6_SHIFT 4
bogdanm 66:9c8f0e3462fb 1291 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
bogdanm 66:9c8f0e3462fb 1292 #define LLWU_PE2_WUPE7_MASK 0xC0u
bogdanm 66:9c8f0e3462fb 1293 #define LLWU_PE2_WUPE7_SHIFT 6
bogdanm 66:9c8f0e3462fb 1294 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
bogdanm 66:9c8f0e3462fb 1295 /* PE3 Bit Fields */
bogdanm 66:9c8f0e3462fb 1296 #define LLWU_PE3_WUPE8_MASK 0x3u
bogdanm 66:9c8f0e3462fb 1297 #define LLWU_PE3_WUPE8_SHIFT 0
bogdanm 66:9c8f0e3462fb 1298 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
bogdanm 66:9c8f0e3462fb 1299 #define LLWU_PE3_WUPE9_MASK 0xCu
bogdanm 66:9c8f0e3462fb 1300 #define LLWU_PE3_WUPE9_SHIFT 2
bogdanm 66:9c8f0e3462fb 1301 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
bogdanm 66:9c8f0e3462fb 1302 #define LLWU_PE3_WUPE10_MASK 0x30u
bogdanm 66:9c8f0e3462fb 1303 #define LLWU_PE3_WUPE10_SHIFT 4
bogdanm 66:9c8f0e3462fb 1304 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
bogdanm 66:9c8f0e3462fb 1305 #define LLWU_PE3_WUPE11_MASK 0xC0u
bogdanm 66:9c8f0e3462fb 1306 #define LLWU_PE3_WUPE11_SHIFT 6
bogdanm 66:9c8f0e3462fb 1307 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
bogdanm 66:9c8f0e3462fb 1308 /* PE4 Bit Fields */
bogdanm 66:9c8f0e3462fb 1309 #define LLWU_PE4_WUPE12_MASK 0x3u
bogdanm 66:9c8f0e3462fb 1310 #define LLWU_PE4_WUPE12_SHIFT 0
bogdanm 66:9c8f0e3462fb 1311 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
bogdanm 66:9c8f0e3462fb 1312 #define LLWU_PE4_WUPE13_MASK 0xCu
bogdanm 66:9c8f0e3462fb 1313 #define LLWU_PE4_WUPE13_SHIFT 2
bogdanm 66:9c8f0e3462fb 1314 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
bogdanm 66:9c8f0e3462fb 1315 #define LLWU_PE4_WUPE14_MASK 0x30u
bogdanm 66:9c8f0e3462fb 1316 #define LLWU_PE4_WUPE14_SHIFT 4
bogdanm 66:9c8f0e3462fb 1317 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
bogdanm 66:9c8f0e3462fb 1318 #define LLWU_PE4_WUPE15_MASK 0xC0u
bogdanm 66:9c8f0e3462fb 1319 #define LLWU_PE4_WUPE15_SHIFT 6
bogdanm 66:9c8f0e3462fb 1320 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
bogdanm 66:9c8f0e3462fb 1321 /* ME Bit Fields */
bogdanm 66:9c8f0e3462fb 1322 #define LLWU_ME_WUME0_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1323 #define LLWU_ME_WUME0_SHIFT 0
bogdanm 66:9c8f0e3462fb 1324 #define LLWU_ME_WUME1_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1325 #define LLWU_ME_WUME1_SHIFT 1
bogdanm 66:9c8f0e3462fb 1326 #define LLWU_ME_WUME2_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1327 #define LLWU_ME_WUME2_SHIFT 2
bogdanm 66:9c8f0e3462fb 1328 #define LLWU_ME_WUME3_MASK 0x8u
bogdanm 66:9c8f0e3462fb 1329 #define LLWU_ME_WUME3_SHIFT 3
bogdanm 66:9c8f0e3462fb 1330 #define LLWU_ME_WUME4_MASK 0x10u
bogdanm 66:9c8f0e3462fb 1331 #define LLWU_ME_WUME4_SHIFT 4
bogdanm 66:9c8f0e3462fb 1332 #define LLWU_ME_WUME5_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1333 #define LLWU_ME_WUME5_SHIFT 5
bogdanm 66:9c8f0e3462fb 1334 #define LLWU_ME_WUME6_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1335 #define LLWU_ME_WUME6_SHIFT 6
bogdanm 66:9c8f0e3462fb 1336 #define LLWU_ME_WUME7_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1337 #define LLWU_ME_WUME7_SHIFT 7
bogdanm 66:9c8f0e3462fb 1338 /* F1 Bit Fields */
bogdanm 66:9c8f0e3462fb 1339 #define LLWU_F1_WUF0_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1340 #define LLWU_F1_WUF0_SHIFT 0
bogdanm 66:9c8f0e3462fb 1341 #define LLWU_F1_WUF1_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1342 #define LLWU_F1_WUF1_SHIFT 1
bogdanm 66:9c8f0e3462fb 1343 #define LLWU_F1_WUF2_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1344 #define LLWU_F1_WUF2_SHIFT 2
bogdanm 66:9c8f0e3462fb 1345 #define LLWU_F1_WUF3_MASK 0x8u
bogdanm 66:9c8f0e3462fb 1346 #define LLWU_F1_WUF3_SHIFT 3
bogdanm 66:9c8f0e3462fb 1347 #define LLWU_F1_WUF4_MASK 0x10u
bogdanm 66:9c8f0e3462fb 1348 #define LLWU_F1_WUF4_SHIFT 4
bogdanm 66:9c8f0e3462fb 1349 #define LLWU_F1_WUF5_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1350 #define LLWU_F1_WUF5_SHIFT 5
bogdanm 66:9c8f0e3462fb 1351 #define LLWU_F1_WUF6_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1352 #define LLWU_F1_WUF6_SHIFT 6
bogdanm 66:9c8f0e3462fb 1353 #define LLWU_F1_WUF7_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1354 #define LLWU_F1_WUF7_SHIFT 7
bogdanm 66:9c8f0e3462fb 1355 /* F2 Bit Fields */
bogdanm 66:9c8f0e3462fb 1356 #define LLWU_F2_WUF8_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1357 #define LLWU_F2_WUF8_SHIFT 0
bogdanm 66:9c8f0e3462fb 1358 #define LLWU_F2_WUF9_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1359 #define LLWU_F2_WUF9_SHIFT 1
bogdanm 66:9c8f0e3462fb 1360 #define LLWU_F2_WUF10_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1361 #define LLWU_F2_WUF10_SHIFT 2
bogdanm 66:9c8f0e3462fb 1362 #define LLWU_F2_WUF11_MASK 0x8u
bogdanm 66:9c8f0e3462fb 1363 #define LLWU_F2_WUF11_SHIFT 3
bogdanm 66:9c8f0e3462fb 1364 #define LLWU_F2_WUF12_MASK 0x10u
bogdanm 66:9c8f0e3462fb 1365 #define LLWU_F2_WUF12_SHIFT 4
bogdanm 66:9c8f0e3462fb 1366 #define LLWU_F2_WUF13_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1367 #define LLWU_F2_WUF13_SHIFT 5
bogdanm 66:9c8f0e3462fb 1368 #define LLWU_F2_WUF14_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1369 #define LLWU_F2_WUF14_SHIFT 6
bogdanm 66:9c8f0e3462fb 1370 #define LLWU_F2_WUF15_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1371 #define LLWU_F2_WUF15_SHIFT 7
bogdanm 66:9c8f0e3462fb 1372 /* F3 Bit Fields */
bogdanm 66:9c8f0e3462fb 1373 #define LLWU_F3_MWUF0_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1374 #define LLWU_F3_MWUF0_SHIFT 0
bogdanm 66:9c8f0e3462fb 1375 #define LLWU_F3_MWUF1_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1376 #define LLWU_F3_MWUF1_SHIFT 1
bogdanm 66:9c8f0e3462fb 1377 #define LLWU_F3_MWUF2_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1378 #define LLWU_F3_MWUF2_SHIFT 2
bogdanm 66:9c8f0e3462fb 1379 #define LLWU_F3_MWUF3_MASK 0x8u
bogdanm 66:9c8f0e3462fb 1380 #define LLWU_F3_MWUF3_SHIFT 3
bogdanm 66:9c8f0e3462fb 1381 #define LLWU_F3_MWUF4_MASK 0x10u
bogdanm 66:9c8f0e3462fb 1382 #define LLWU_F3_MWUF4_SHIFT 4
bogdanm 66:9c8f0e3462fb 1383 #define LLWU_F3_MWUF5_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1384 #define LLWU_F3_MWUF5_SHIFT 5
bogdanm 66:9c8f0e3462fb 1385 #define LLWU_F3_MWUF6_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1386 #define LLWU_F3_MWUF6_SHIFT 6
bogdanm 66:9c8f0e3462fb 1387 #define LLWU_F3_MWUF7_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1388 #define LLWU_F3_MWUF7_SHIFT 7
bogdanm 66:9c8f0e3462fb 1389 /* FILT1 Bit Fields */
bogdanm 66:9c8f0e3462fb 1390 #define LLWU_FILT1_FILTSEL_MASK 0xFu
bogdanm 66:9c8f0e3462fb 1391 #define LLWU_FILT1_FILTSEL_SHIFT 0
bogdanm 66:9c8f0e3462fb 1392 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
bogdanm 66:9c8f0e3462fb 1393 #define LLWU_FILT1_FILTE_MASK 0x60u
bogdanm 66:9c8f0e3462fb 1394 #define LLWU_FILT1_FILTE_SHIFT 5
bogdanm 66:9c8f0e3462fb 1395 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
bogdanm 66:9c8f0e3462fb 1396 #define LLWU_FILT1_FILTF_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1397 #define LLWU_FILT1_FILTF_SHIFT 7
bogdanm 66:9c8f0e3462fb 1398 /* FILT2 Bit Fields */
bogdanm 66:9c8f0e3462fb 1399 #define LLWU_FILT2_FILTSEL_MASK 0xFu
bogdanm 66:9c8f0e3462fb 1400 #define LLWU_FILT2_FILTSEL_SHIFT 0
bogdanm 66:9c8f0e3462fb 1401 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
bogdanm 66:9c8f0e3462fb 1402 #define LLWU_FILT2_FILTE_MASK 0x60u
bogdanm 66:9c8f0e3462fb 1403 #define LLWU_FILT2_FILTE_SHIFT 5
bogdanm 66:9c8f0e3462fb 1404 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
bogdanm 66:9c8f0e3462fb 1405 #define LLWU_FILT2_FILTF_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1406 #define LLWU_FILT2_FILTF_SHIFT 7
bogdanm 66:9c8f0e3462fb 1407
bogdanm 66:9c8f0e3462fb 1408 /**
bogdanm 66:9c8f0e3462fb 1409 * @}
bogdanm 66:9c8f0e3462fb 1410 */ /* end of group LLWU_Register_Masks */
bogdanm 66:9c8f0e3462fb 1411
bogdanm 66:9c8f0e3462fb 1412
bogdanm 66:9c8f0e3462fb 1413 /* LLWU - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 1414 /** Peripheral LLWU base address */
bogdanm 66:9c8f0e3462fb 1415 #define LLWU_BASE (0x4007C000u)
bogdanm 66:9c8f0e3462fb 1416 /** Peripheral LLWU base pointer */
bogdanm 66:9c8f0e3462fb 1417 #define LLWU ((LLWU_Type *)LLWU_BASE)
bogdanm 66:9c8f0e3462fb 1418 /** Array initializer of LLWU peripheral base pointers */
bogdanm 66:9c8f0e3462fb 1419 #define LLWU_BASES { LLWU }
bogdanm 66:9c8f0e3462fb 1420
bogdanm 66:9c8f0e3462fb 1421 /**
bogdanm 66:9c8f0e3462fb 1422 * @}
bogdanm 66:9c8f0e3462fb 1423 */ /* end of group LLWU_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 1424
bogdanm 66:9c8f0e3462fb 1425
bogdanm 66:9c8f0e3462fb 1426 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1427 -- LPTMR Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1428 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1429
bogdanm 66:9c8f0e3462fb 1430 /**
bogdanm 66:9c8f0e3462fb 1431 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1432 * @{
bogdanm 66:9c8f0e3462fb 1433 */
bogdanm 66:9c8f0e3462fb 1434
bogdanm 66:9c8f0e3462fb 1435 /** LPTMR - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 1436 typedef struct {
bogdanm 66:9c8f0e3462fb 1437 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 1438 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 1439 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 1440 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
bogdanm 66:9c8f0e3462fb 1441 } LPTMR_Type;
bogdanm 66:9c8f0e3462fb 1442
bogdanm 66:9c8f0e3462fb 1443 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1444 -- LPTMR Register Masks
bogdanm 66:9c8f0e3462fb 1445 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1446
bogdanm 66:9c8f0e3462fb 1447 /**
bogdanm 66:9c8f0e3462fb 1448 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
bogdanm 66:9c8f0e3462fb 1449 * @{
bogdanm 66:9c8f0e3462fb 1450 */
bogdanm 66:9c8f0e3462fb 1451
bogdanm 66:9c8f0e3462fb 1452 /* CSR Bit Fields */
bogdanm 66:9c8f0e3462fb 1453 #define LPTMR_CSR_TEN_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1454 #define LPTMR_CSR_TEN_SHIFT 0
bogdanm 66:9c8f0e3462fb 1455 #define LPTMR_CSR_TMS_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1456 #define LPTMR_CSR_TMS_SHIFT 1
bogdanm 66:9c8f0e3462fb 1457 #define LPTMR_CSR_TFC_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1458 #define LPTMR_CSR_TFC_SHIFT 2
bogdanm 66:9c8f0e3462fb 1459 #define LPTMR_CSR_TPP_MASK 0x8u
bogdanm 66:9c8f0e3462fb 1460 #define LPTMR_CSR_TPP_SHIFT 3
bogdanm 66:9c8f0e3462fb 1461 #define LPTMR_CSR_TPS_MASK 0x30u
bogdanm 66:9c8f0e3462fb 1462 #define LPTMR_CSR_TPS_SHIFT 4
bogdanm 66:9c8f0e3462fb 1463 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
bogdanm 66:9c8f0e3462fb 1464 #define LPTMR_CSR_TIE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1465 #define LPTMR_CSR_TIE_SHIFT 6
bogdanm 66:9c8f0e3462fb 1466 #define LPTMR_CSR_TCF_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1467 #define LPTMR_CSR_TCF_SHIFT 7
bogdanm 66:9c8f0e3462fb 1468 /* PSR Bit Fields */
bogdanm 66:9c8f0e3462fb 1469 #define LPTMR_PSR_PCS_MASK 0x3u
bogdanm 66:9c8f0e3462fb 1470 #define LPTMR_PSR_PCS_SHIFT 0
bogdanm 66:9c8f0e3462fb 1471 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
bogdanm 66:9c8f0e3462fb 1472 #define LPTMR_PSR_PBYP_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1473 #define LPTMR_PSR_PBYP_SHIFT 2
bogdanm 66:9c8f0e3462fb 1474 #define LPTMR_PSR_PRESCALE_MASK 0x78u
bogdanm 66:9c8f0e3462fb 1475 #define LPTMR_PSR_PRESCALE_SHIFT 3
bogdanm 66:9c8f0e3462fb 1476 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
bogdanm 66:9c8f0e3462fb 1477 /* CMR Bit Fields */
bogdanm 66:9c8f0e3462fb 1478 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 1479 #define LPTMR_CMR_COMPARE_SHIFT 0
bogdanm 66:9c8f0e3462fb 1480 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
bogdanm 66:9c8f0e3462fb 1481 /* CNR Bit Fields */
bogdanm 66:9c8f0e3462fb 1482 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 1483 #define LPTMR_CNR_COUNTER_SHIFT 0
bogdanm 66:9c8f0e3462fb 1484 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
bogdanm 66:9c8f0e3462fb 1485
bogdanm 66:9c8f0e3462fb 1486 /**
bogdanm 66:9c8f0e3462fb 1487 * @}
bogdanm 66:9c8f0e3462fb 1488 */ /* end of group LPTMR_Register_Masks */
bogdanm 66:9c8f0e3462fb 1489
bogdanm 66:9c8f0e3462fb 1490
bogdanm 66:9c8f0e3462fb 1491 /* LPTMR - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 1492 /** Peripheral LPTMR0 base address */
bogdanm 66:9c8f0e3462fb 1493 #define LPTMR0_BASE (0x40040000u)
bogdanm 66:9c8f0e3462fb 1494 /** Peripheral LPTMR0 base pointer */
bogdanm 66:9c8f0e3462fb 1495 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
bogdanm 66:9c8f0e3462fb 1496 /** Array initializer of LPTMR peripheral base pointers */
bogdanm 66:9c8f0e3462fb 1497 #define LPTMR_BASES { LPTMR0 }
bogdanm 66:9c8f0e3462fb 1498
bogdanm 66:9c8f0e3462fb 1499 /**
bogdanm 66:9c8f0e3462fb 1500 * @}
bogdanm 66:9c8f0e3462fb 1501 */ /* end of group LPTMR_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 1502
bogdanm 66:9c8f0e3462fb 1503
bogdanm 66:9c8f0e3462fb 1504 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1505 -- MCG Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1506 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1507
bogdanm 66:9c8f0e3462fb 1508 /**
bogdanm 66:9c8f0e3462fb 1509 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1510 * @{
bogdanm 66:9c8f0e3462fb 1511 */
bogdanm 66:9c8f0e3462fb 1512
bogdanm 66:9c8f0e3462fb 1513 /** MCG - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 1514 typedef struct {
bogdanm 66:9c8f0e3462fb 1515 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 1516 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
bogdanm 66:9c8f0e3462fb 1517 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
bogdanm 66:9c8f0e3462fb 1518 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
bogdanm 66:9c8f0e3462fb 1519 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 1520 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
bogdanm 66:9c8f0e3462fb 1521 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
bogdanm 66:9c8f0e3462fb 1522 uint8_t RESERVED_0[1];
bogdanm 66:9c8f0e3462fb 1523 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 1524 uint8_t RESERVED_1[1];
bogdanm 66:9c8f0e3462fb 1525 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
bogdanm 66:9c8f0e3462fb 1526 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
bogdanm 66:9c8f0e3462fb 1527 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
bogdanm 66:9c8f0e3462fb 1528 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
bogdanm 66:9c8f0e3462fb 1529 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
bogdanm 66:9c8f0e3462fb 1530 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
bogdanm 66:9c8f0e3462fb 1531 } MCG_Type;
bogdanm 66:9c8f0e3462fb 1532
bogdanm 66:9c8f0e3462fb 1533 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1534 -- MCG Register Masks
bogdanm 66:9c8f0e3462fb 1535 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1536
bogdanm 66:9c8f0e3462fb 1537 /**
bogdanm 66:9c8f0e3462fb 1538 * @addtogroup MCG_Register_Masks MCG Register Masks
bogdanm 66:9c8f0e3462fb 1539 * @{
bogdanm 66:9c8f0e3462fb 1540 */
bogdanm 66:9c8f0e3462fb 1541
bogdanm 66:9c8f0e3462fb 1542 /* C1 Bit Fields */
bogdanm 66:9c8f0e3462fb 1543 #define MCG_C1_IREFSTEN_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1544 #define MCG_C1_IREFSTEN_SHIFT 0
bogdanm 66:9c8f0e3462fb 1545 #define MCG_C1_IRCLKEN_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1546 #define MCG_C1_IRCLKEN_SHIFT 1
bogdanm 66:9c8f0e3462fb 1547 #define MCG_C1_IREFS_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1548 #define MCG_C1_IREFS_SHIFT 2
bogdanm 66:9c8f0e3462fb 1549 #define MCG_C1_FRDIV_MASK 0x38u
bogdanm 66:9c8f0e3462fb 1550 #define MCG_C1_FRDIV_SHIFT 3
bogdanm 66:9c8f0e3462fb 1551 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
bogdanm 66:9c8f0e3462fb 1552 #define MCG_C1_CLKS_MASK 0xC0u
bogdanm 66:9c8f0e3462fb 1553 #define MCG_C1_CLKS_SHIFT 6
bogdanm 66:9c8f0e3462fb 1554 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
bogdanm 66:9c8f0e3462fb 1555 /* C2 Bit Fields */
bogdanm 66:9c8f0e3462fb 1556 #define MCG_C2_IRCS_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1557 #define MCG_C2_IRCS_SHIFT 0
bogdanm 66:9c8f0e3462fb 1558 #define MCG_C2_LP_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1559 #define MCG_C2_LP_SHIFT 1
bogdanm 66:9c8f0e3462fb 1560 #define MCG_C2_EREFS0_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1561 #define MCG_C2_EREFS0_SHIFT 2
bogdanm 66:9c8f0e3462fb 1562 #define MCG_C2_HGO0_MASK 0x8u
bogdanm 66:9c8f0e3462fb 1563 #define MCG_C2_HGO0_SHIFT 3
bogdanm 66:9c8f0e3462fb 1564 #define MCG_C2_RANGE0_MASK 0x30u
bogdanm 66:9c8f0e3462fb 1565 #define MCG_C2_RANGE0_SHIFT 4
bogdanm 66:9c8f0e3462fb 1566 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
bogdanm 66:9c8f0e3462fb 1567 #define MCG_C2_LOCRE0_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1568 #define MCG_C2_LOCRE0_SHIFT 7
bogdanm 66:9c8f0e3462fb 1569 /* C3 Bit Fields */
bogdanm 66:9c8f0e3462fb 1570 #define MCG_C3_SCTRIM_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 1571 #define MCG_C3_SCTRIM_SHIFT 0
bogdanm 66:9c8f0e3462fb 1572 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
bogdanm 66:9c8f0e3462fb 1573 /* C4 Bit Fields */
bogdanm 66:9c8f0e3462fb 1574 #define MCG_C4_SCFTRIM_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1575 #define MCG_C4_SCFTRIM_SHIFT 0
bogdanm 66:9c8f0e3462fb 1576 #define MCG_C4_FCTRIM_MASK 0x1Eu
bogdanm 66:9c8f0e3462fb 1577 #define MCG_C4_FCTRIM_SHIFT 1
bogdanm 66:9c8f0e3462fb 1578 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
bogdanm 66:9c8f0e3462fb 1579 #define MCG_C4_DRST_DRS_MASK 0x60u
bogdanm 66:9c8f0e3462fb 1580 #define MCG_C4_DRST_DRS_SHIFT 5
bogdanm 66:9c8f0e3462fb 1581 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
bogdanm 66:9c8f0e3462fb 1582 #define MCG_C4_DMX32_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1583 #define MCG_C4_DMX32_SHIFT 7
bogdanm 66:9c8f0e3462fb 1584 /* C5 Bit Fields */
bogdanm 66:9c8f0e3462fb 1585 #define MCG_C5_PRDIV0_MASK 0x1Fu
bogdanm 66:9c8f0e3462fb 1586 #define MCG_C5_PRDIV0_SHIFT 0
bogdanm 66:9c8f0e3462fb 1587 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
bogdanm 66:9c8f0e3462fb 1588 #define MCG_C5_PLLSTEN0_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1589 #define MCG_C5_PLLSTEN0_SHIFT 5
bogdanm 66:9c8f0e3462fb 1590 #define MCG_C5_PLLCLKEN0_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1591 #define MCG_C5_PLLCLKEN0_SHIFT 6
bogdanm 66:9c8f0e3462fb 1592 /* C6 Bit Fields */
bogdanm 66:9c8f0e3462fb 1593 #define MCG_C6_VDIV0_MASK 0x1Fu
bogdanm 66:9c8f0e3462fb 1594 #define MCG_C6_VDIV0_SHIFT 0
bogdanm 66:9c8f0e3462fb 1595 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
bogdanm 66:9c8f0e3462fb 1596 #define MCG_C6_CME0_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1597 #define MCG_C6_CME0_SHIFT 5
bogdanm 66:9c8f0e3462fb 1598 #define MCG_C6_PLLS_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1599 #define MCG_C6_PLLS_SHIFT 6
bogdanm 66:9c8f0e3462fb 1600 #define MCG_C6_LOLIE0_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1601 #define MCG_C6_LOLIE0_SHIFT 7
bogdanm 66:9c8f0e3462fb 1602 /* S Bit Fields */
bogdanm 66:9c8f0e3462fb 1603 #define MCG_S_IRCST_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1604 #define MCG_S_IRCST_SHIFT 0
bogdanm 66:9c8f0e3462fb 1605 #define MCG_S_OSCINIT0_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1606 #define MCG_S_OSCINIT0_SHIFT 1
bogdanm 66:9c8f0e3462fb 1607 #define MCG_S_CLKST_MASK 0xCu
bogdanm 66:9c8f0e3462fb 1608 #define MCG_S_CLKST_SHIFT 2
bogdanm 66:9c8f0e3462fb 1609 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
bogdanm 66:9c8f0e3462fb 1610 #define MCG_S_IREFST_MASK 0x10u
bogdanm 66:9c8f0e3462fb 1611 #define MCG_S_IREFST_SHIFT 4
bogdanm 66:9c8f0e3462fb 1612 #define MCG_S_PLLST_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1613 #define MCG_S_PLLST_SHIFT 5
bogdanm 66:9c8f0e3462fb 1614 #define MCG_S_LOCK0_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1615 #define MCG_S_LOCK0_SHIFT 6
bogdanm 66:9c8f0e3462fb 1616 #define MCG_S_LOLS_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1617 #define MCG_S_LOLS_SHIFT 7
bogdanm 66:9c8f0e3462fb 1618 /* SC Bit Fields */
bogdanm 66:9c8f0e3462fb 1619 #define MCG_SC_LOCS0_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1620 #define MCG_SC_LOCS0_SHIFT 0
bogdanm 66:9c8f0e3462fb 1621 #define MCG_SC_FCRDIV_MASK 0xEu
bogdanm 66:9c8f0e3462fb 1622 #define MCG_SC_FCRDIV_SHIFT 1
bogdanm 66:9c8f0e3462fb 1623 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
bogdanm 66:9c8f0e3462fb 1624 #define MCG_SC_FLTPRSRV_MASK 0x10u
bogdanm 66:9c8f0e3462fb 1625 #define MCG_SC_FLTPRSRV_SHIFT 4
bogdanm 66:9c8f0e3462fb 1626 #define MCG_SC_ATMF_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1627 #define MCG_SC_ATMF_SHIFT 5
bogdanm 66:9c8f0e3462fb 1628 #define MCG_SC_ATMS_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1629 #define MCG_SC_ATMS_SHIFT 6
bogdanm 66:9c8f0e3462fb 1630 #define MCG_SC_ATME_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1631 #define MCG_SC_ATME_SHIFT 7
bogdanm 66:9c8f0e3462fb 1632 /* ATCVH Bit Fields */
bogdanm 66:9c8f0e3462fb 1633 #define MCG_ATCVH_ATCVH_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 1634 #define MCG_ATCVH_ATCVH_SHIFT 0
bogdanm 66:9c8f0e3462fb 1635 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
bogdanm 66:9c8f0e3462fb 1636 /* ATCVL Bit Fields */
bogdanm 66:9c8f0e3462fb 1637 #define MCG_ATCVL_ATCVL_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 1638 #define MCG_ATCVL_ATCVL_SHIFT 0
bogdanm 66:9c8f0e3462fb 1639 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
bogdanm 66:9c8f0e3462fb 1640 /* C8 Bit Fields */
bogdanm 66:9c8f0e3462fb 1641 #define MCG_C8_LOLRE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1642 #define MCG_C8_LOLRE_SHIFT 6
bogdanm 66:9c8f0e3462fb 1643
bogdanm 66:9c8f0e3462fb 1644 /**
bogdanm 66:9c8f0e3462fb 1645 * @}
bogdanm 66:9c8f0e3462fb 1646 */ /* end of group MCG_Register_Masks */
bogdanm 66:9c8f0e3462fb 1647
bogdanm 66:9c8f0e3462fb 1648
bogdanm 66:9c8f0e3462fb 1649 /* MCG - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 1650 /** Peripheral MCG base address */
bogdanm 66:9c8f0e3462fb 1651 #define MCG_BASE (0x40064000u)
bogdanm 66:9c8f0e3462fb 1652 /** Peripheral MCG base pointer */
bogdanm 66:9c8f0e3462fb 1653 #define MCG ((MCG_Type *)MCG_BASE)
bogdanm 66:9c8f0e3462fb 1654 /** Array initializer of MCG peripheral base pointers */
bogdanm 66:9c8f0e3462fb 1655 #define MCG_BASES { MCG }
bogdanm 66:9c8f0e3462fb 1656
bogdanm 66:9c8f0e3462fb 1657 /**
bogdanm 66:9c8f0e3462fb 1658 * @}
bogdanm 66:9c8f0e3462fb 1659 */ /* end of group MCG_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 1660
bogdanm 66:9c8f0e3462fb 1661
bogdanm 66:9c8f0e3462fb 1662 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1663 -- MCM Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1664 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1665
bogdanm 66:9c8f0e3462fb 1666 /**
bogdanm 66:9c8f0e3462fb 1667 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1668 * @{
bogdanm 66:9c8f0e3462fb 1669 */
bogdanm 66:9c8f0e3462fb 1670
bogdanm 66:9c8f0e3462fb 1671 /** MCM - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 1672 typedef struct {
bogdanm 66:9c8f0e3462fb 1673 uint8_t RESERVED_0[8];
bogdanm 66:9c8f0e3462fb 1674 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 1675 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
bogdanm 66:9c8f0e3462fb 1676 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
bogdanm 66:9c8f0e3462fb 1677 uint8_t RESERVED_1[48];
bogdanm 66:9c8f0e3462fb 1678 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
bogdanm 66:9c8f0e3462fb 1679 } MCM_Type;
bogdanm 66:9c8f0e3462fb 1680
bogdanm 66:9c8f0e3462fb 1681 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1682 -- MCM Register Masks
bogdanm 66:9c8f0e3462fb 1683 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1684
bogdanm 66:9c8f0e3462fb 1685 /**
bogdanm 66:9c8f0e3462fb 1686 * @addtogroup MCM_Register_Masks MCM Register Masks
bogdanm 66:9c8f0e3462fb 1687 * @{
bogdanm 66:9c8f0e3462fb 1688 */
bogdanm 66:9c8f0e3462fb 1689
bogdanm 66:9c8f0e3462fb 1690 /* PLASC Bit Fields */
bogdanm 66:9c8f0e3462fb 1691 #define MCM_PLASC_ASC_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 1692 #define MCM_PLASC_ASC_SHIFT 0
bogdanm 66:9c8f0e3462fb 1693 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
bogdanm 66:9c8f0e3462fb 1694 /* PLAMC Bit Fields */
bogdanm 66:9c8f0e3462fb 1695 #define MCM_PLAMC_AMC_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 1696 #define MCM_PLAMC_AMC_SHIFT 0
bogdanm 66:9c8f0e3462fb 1697 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
bogdanm 66:9c8f0e3462fb 1698 /* PLACR Bit Fields */
bogdanm 66:9c8f0e3462fb 1699 #define MCM_PLACR_ARB_MASK 0x200u
bogdanm 66:9c8f0e3462fb 1700 #define MCM_PLACR_ARB_SHIFT 9
bogdanm 66:9c8f0e3462fb 1701 #define MCM_PLACR_CFCC_MASK 0x400u
bogdanm 66:9c8f0e3462fb 1702 #define MCM_PLACR_CFCC_SHIFT 10
bogdanm 66:9c8f0e3462fb 1703 #define MCM_PLACR_DFCDA_MASK 0x800u
bogdanm 66:9c8f0e3462fb 1704 #define MCM_PLACR_DFCDA_SHIFT 11
bogdanm 66:9c8f0e3462fb 1705 #define MCM_PLACR_DFCIC_MASK 0x1000u
bogdanm 66:9c8f0e3462fb 1706 #define MCM_PLACR_DFCIC_SHIFT 12
bogdanm 66:9c8f0e3462fb 1707 #define MCM_PLACR_DFCC_MASK 0x2000u
bogdanm 66:9c8f0e3462fb 1708 #define MCM_PLACR_DFCC_SHIFT 13
bogdanm 66:9c8f0e3462fb 1709 #define MCM_PLACR_EFDS_MASK 0x4000u
bogdanm 66:9c8f0e3462fb 1710 #define MCM_PLACR_EFDS_SHIFT 14
bogdanm 66:9c8f0e3462fb 1711 #define MCM_PLACR_DFCS_MASK 0x8000u
bogdanm 66:9c8f0e3462fb 1712 #define MCM_PLACR_DFCS_SHIFT 15
bogdanm 66:9c8f0e3462fb 1713 #define MCM_PLACR_ESFC_MASK 0x10000u
bogdanm 66:9c8f0e3462fb 1714 #define MCM_PLACR_ESFC_SHIFT 16
bogdanm 66:9c8f0e3462fb 1715 /* CPO Bit Fields */
bogdanm 66:9c8f0e3462fb 1716 #define MCM_CPO_CPOREQ_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1717 #define MCM_CPO_CPOREQ_SHIFT 0
bogdanm 66:9c8f0e3462fb 1718 #define MCM_CPO_CPOACK_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1719 #define MCM_CPO_CPOACK_SHIFT 1
bogdanm 66:9c8f0e3462fb 1720 #define MCM_CPO_CPOWOI_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1721 #define MCM_CPO_CPOWOI_SHIFT 2
bogdanm 66:9c8f0e3462fb 1722
bogdanm 66:9c8f0e3462fb 1723 /**
bogdanm 66:9c8f0e3462fb 1724 * @}
bogdanm 66:9c8f0e3462fb 1725 */ /* end of group MCM_Register_Masks */
bogdanm 66:9c8f0e3462fb 1726
bogdanm 66:9c8f0e3462fb 1727
bogdanm 66:9c8f0e3462fb 1728 /* MCM - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 1729 /** Peripheral MCM base address */
bogdanm 66:9c8f0e3462fb 1730 #define MCM_BASE (0xF0003000u)
bogdanm 66:9c8f0e3462fb 1731 /** Peripheral MCM base pointer */
bogdanm 66:9c8f0e3462fb 1732 #define MCM ((MCM_Type *)MCM_BASE)
bogdanm 66:9c8f0e3462fb 1733 /** Array initializer of MCM peripheral base pointers */
bogdanm 66:9c8f0e3462fb 1734 #define MCM_BASES { MCM }
bogdanm 66:9c8f0e3462fb 1735
bogdanm 66:9c8f0e3462fb 1736 /**
bogdanm 66:9c8f0e3462fb 1737 * @}
bogdanm 66:9c8f0e3462fb 1738 */ /* end of group MCM_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 1739
bogdanm 66:9c8f0e3462fb 1740
bogdanm 66:9c8f0e3462fb 1741 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1742 -- MTB Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1743 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1744
bogdanm 66:9c8f0e3462fb 1745 /**
bogdanm 66:9c8f0e3462fb 1746 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1747 * @{
bogdanm 66:9c8f0e3462fb 1748 */
bogdanm 66:9c8f0e3462fb 1749
bogdanm 66:9c8f0e3462fb 1750 /** MTB - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 1751 typedef struct {
bogdanm 66:9c8f0e3462fb 1752 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 1753 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 1754 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 1755 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
bogdanm 66:9c8f0e3462fb 1756 uint8_t RESERVED_0[3824];
bogdanm 66:9c8f0e3462fb 1757 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
bogdanm 66:9c8f0e3462fb 1758 uint8_t RESERVED_1[156];
bogdanm 66:9c8f0e3462fb 1759 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
bogdanm 66:9c8f0e3462fb 1760 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
bogdanm 66:9c8f0e3462fb 1761 uint8_t RESERVED_2[8];
bogdanm 66:9c8f0e3462fb 1762 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
bogdanm 66:9c8f0e3462fb 1763 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
bogdanm 66:9c8f0e3462fb 1764 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
bogdanm 66:9c8f0e3462fb 1765 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
bogdanm 66:9c8f0e3462fb 1766 uint8_t RESERVED_3[8];
bogdanm 66:9c8f0e3462fb 1767 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
bogdanm 66:9c8f0e3462fb 1768 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
bogdanm 66:9c8f0e3462fb 1769 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
bogdanm 66:9c8f0e3462fb 1770 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
bogdanm 66:9c8f0e3462fb 1771 } MTB_Type;
bogdanm 66:9c8f0e3462fb 1772
bogdanm 66:9c8f0e3462fb 1773 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1774 -- MTB Register Masks
bogdanm 66:9c8f0e3462fb 1775 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1776
bogdanm 66:9c8f0e3462fb 1777 /**
bogdanm 66:9c8f0e3462fb 1778 * @addtogroup MTB_Register_Masks MTB Register Masks
bogdanm 66:9c8f0e3462fb 1779 * @{
bogdanm 66:9c8f0e3462fb 1780 */
bogdanm 66:9c8f0e3462fb 1781
bogdanm 66:9c8f0e3462fb 1782 /* POSITION Bit Fields */
bogdanm 66:9c8f0e3462fb 1783 #define MTB_POSITION_WRAP_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1784 #define MTB_POSITION_WRAP_SHIFT 2
bogdanm 66:9c8f0e3462fb 1785 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
bogdanm 66:9c8f0e3462fb 1786 #define MTB_POSITION_POINTER_SHIFT 3
bogdanm 66:9c8f0e3462fb 1787 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
bogdanm 66:9c8f0e3462fb 1788 /* MASTER Bit Fields */
bogdanm 66:9c8f0e3462fb 1789 #define MTB_MASTER_MASK_MASK 0x1Fu
bogdanm 66:9c8f0e3462fb 1790 #define MTB_MASTER_MASK_SHIFT 0
bogdanm 66:9c8f0e3462fb 1791 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
bogdanm 66:9c8f0e3462fb 1792 #define MTB_MASTER_TSTARTEN_MASK 0x20u
bogdanm 66:9c8f0e3462fb 1793 #define MTB_MASTER_TSTARTEN_SHIFT 5
bogdanm 66:9c8f0e3462fb 1794 #define MTB_MASTER_TSTOPEN_MASK 0x40u
bogdanm 66:9c8f0e3462fb 1795 #define MTB_MASTER_TSTOPEN_SHIFT 6
bogdanm 66:9c8f0e3462fb 1796 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
bogdanm 66:9c8f0e3462fb 1797 #define MTB_MASTER_SFRWPRIV_SHIFT 7
bogdanm 66:9c8f0e3462fb 1798 #define MTB_MASTER_RAMPRIV_MASK 0x100u
bogdanm 66:9c8f0e3462fb 1799 #define MTB_MASTER_RAMPRIV_SHIFT 8
bogdanm 66:9c8f0e3462fb 1800 #define MTB_MASTER_HALTREQ_MASK 0x200u
bogdanm 66:9c8f0e3462fb 1801 #define MTB_MASTER_HALTREQ_SHIFT 9
bogdanm 66:9c8f0e3462fb 1802 #define MTB_MASTER_EN_MASK 0x80000000u
bogdanm 66:9c8f0e3462fb 1803 #define MTB_MASTER_EN_SHIFT 31
bogdanm 66:9c8f0e3462fb 1804 /* FLOW Bit Fields */
bogdanm 66:9c8f0e3462fb 1805 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1806 #define MTB_FLOW_AUTOSTOP_SHIFT 0
bogdanm 66:9c8f0e3462fb 1807 #define MTB_FLOW_AUTOHALT_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1808 #define MTB_FLOW_AUTOHALT_SHIFT 1
bogdanm 66:9c8f0e3462fb 1809 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
bogdanm 66:9c8f0e3462fb 1810 #define MTB_FLOW_WATERMARK_SHIFT 3
bogdanm 66:9c8f0e3462fb 1811 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
bogdanm 66:9c8f0e3462fb 1812 /* BASE Bit Fields */
bogdanm 66:9c8f0e3462fb 1813 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1814 #define MTB_BASE_BASEADDR_SHIFT 0
bogdanm 66:9c8f0e3462fb 1815 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
bogdanm 66:9c8f0e3462fb 1816 /* MODECTRL Bit Fields */
bogdanm 66:9c8f0e3462fb 1817 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1818 #define MTB_MODECTRL_MODECTRL_SHIFT 0
bogdanm 66:9c8f0e3462fb 1819 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
bogdanm 66:9c8f0e3462fb 1820 /* TAGSET Bit Fields */
bogdanm 66:9c8f0e3462fb 1821 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1822 #define MTB_TAGSET_TAGSET_SHIFT 0
bogdanm 66:9c8f0e3462fb 1823 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
bogdanm 66:9c8f0e3462fb 1824 /* TAGCLEAR Bit Fields */
bogdanm 66:9c8f0e3462fb 1825 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1826 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
bogdanm 66:9c8f0e3462fb 1827 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
bogdanm 66:9c8f0e3462fb 1828 /* LOCKACCESS Bit Fields */
bogdanm 66:9c8f0e3462fb 1829 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1830 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
bogdanm 66:9c8f0e3462fb 1831 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
bogdanm 66:9c8f0e3462fb 1832 /* LOCKSTAT Bit Fields */
bogdanm 66:9c8f0e3462fb 1833 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1834 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
bogdanm 66:9c8f0e3462fb 1835 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
bogdanm 66:9c8f0e3462fb 1836 /* AUTHSTAT Bit Fields */
bogdanm 66:9c8f0e3462fb 1837 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1838 #define MTB_AUTHSTAT_BIT0_SHIFT 0
bogdanm 66:9c8f0e3462fb 1839 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1840 #define MTB_AUTHSTAT_BIT1_SHIFT 1
bogdanm 66:9c8f0e3462fb 1841 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
bogdanm 66:9c8f0e3462fb 1842 #define MTB_AUTHSTAT_BIT2_SHIFT 2
bogdanm 66:9c8f0e3462fb 1843 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
bogdanm 66:9c8f0e3462fb 1844 #define MTB_AUTHSTAT_BIT3_SHIFT 3
bogdanm 66:9c8f0e3462fb 1845 /* DEVICEARCH Bit Fields */
bogdanm 66:9c8f0e3462fb 1846 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1847 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
bogdanm 66:9c8f0e3462fb 1848 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
bogdanm 66:9c8f0e3462fb 1849 /* DEVICECFG Bit Fields */
bogdanm 66:9c8f0e3462fb 1850 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1851 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
bogdanm 66:9c8f0e3462fb 1852 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
bogdanm 66:9c8f0e3462fb 1853 /* DEVICETYPID Bit Fields */
bogdanm 66:9c8f0e3462fb 1854 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1855 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
bogdanm 66:9c8f0e3462fb 1856 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
bogdanm 66:9c8f0e3462fb 1857 /* PERIPHID Bit Fields */
bogdanm 66:9c8f0e3462fb 1858 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1859 #define MTB_PERIPHID_PERIPHID_SHIFT 0
bogdanm 66:9c8f0e3462fb 1860 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
bogdanm 66:9c8f0e3462fb 1861 /* COMPID Bit Fields */
bogdanm 66:9c8f0e3462fb 1862 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1863 #define MTB_COMPID_COMPID_SHIFT 0
bogdanm 66:9c8f0e3462fb 1864 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
bogdanm 66:9c8f0e3462fb 1865
bogdanm 66:9c8f0e3462fb 1866 /**
bogdanm 66:9c8f0e3462fb 1867 * @}
bogdanm 66:9c8f0e3462fb 1868 */ /* end of group MTB_Register_Masks */
bogdanm 66:9c8f0e3462fb 1869
bogdanm 66:9c8f0e3462fb 1870
bogdanm 66:9c8f0e3462fb 1871 /* MTB - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 1872 /** Peripheral MTB base address */
bogdanm 66:9c8f0e3462fb 1873 #define MTB_BASE (0xF0000000u)
bogdanm 66:9c8f0e3462fb 1874 /** Peripheral MTB base pointer */
bogdanm 66:9c8f0e3462fb 1875 #define MTB ((MTB_Type *)MTB_BASE)
bogdanm 66:9c8f0e3462fb 1876 /** Array initializer of MTB peripheral base pointers */
bogdanm 66:9c8f0e3462fb 1877 #define MTB_BASES { MTB }
bogdanm 66:9c8f0e3462fb 1878
bogdanm 66:9c8f0e3462fb 1879 /**
bogdanm 66:9c8f0e3462fb 1880 * @}
bogdanm 66:9c8f0e3462fb 1881 */ /* end of group MTB_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 1882
bogdanm 66:9c8f0e3462fb 1883
bogdanm 66:9c8f0e3462fb 1884 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1885 -- MTBDWT Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1886 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1887
bogdanm 66:9c8f0e3462fb 1888 /**
bogdanm 66:9c8f0e3462fb 1889 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1890 * @{
bogdanm 66:9c8f0e3462fb 1891 */
bogdanm 66:9c8f0e3462fb 1892
bogdanm 66:9c8f0e3462fb 1893 /** MTBDWT - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 1894 typedef struct {
bogdanm 66:9c8f0e3462fb 1895 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 1896 uint8_t RESERVED_0[28];
bogdanm 66:9c8f0e3462fb 1897 struct { /* offset: 0x20, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 1898 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 1899 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 1900 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 1901 uint8_t RESERVED_0[4];
bogdanm 66:9c8f0e3462fb 1902 } COMPARATOR[2];
bogdanm 66:9c8f0e3462fb 1903 uint8_t RESERVED_1[448];
bogdanm 66:9c8f0e3462fb 1904 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
bogdanm 66:9c8f0e3462fb 1905 uint8_t RESERVED_2[3524];
bogdanm 66:9c8f0e3462fb 1906 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
bogdanm 66:9c8f0e3462fb 1907 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
bogdanm 66:9c8f0e3462fb 1908 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
bogdanm 66:9c8f0e3462fb 1909 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
bogdanm 66:9c8f0e3462fb 1910 } MTBDWT_Type;
bogdanm 66:9c8f0e3462fb 1911
bogdanm 66:9c8f0e3462fb 1912 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1913 -- MTBDWT Register Masks
bogdanm 66:9c8f0e3462fb 1914 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1915
bogdanm 66:9c8f0e3462fb 1916 /**
bogdanm 66:9c8f0e3462fb 1917 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
bogdanm 66:9c8f0e3462fb 1918 * @{
bogdanm 66:9c8f0e3462fb 1919 */
bogdanm 66:9c8f0e3462fb 1920
bogdanm 66:9c8f0e3462fb 1921 /* CTRL Bit Fields */
bogdanm 66:9c8f0e3462fb 1922 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
bogdanm 66:9c8f0e3462fb 1923 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
bogdanm 66:9c8f0e3462fb 1924 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
bogdanm 66:9c8f0e3462fb 1925 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
bogdanm 66:9c8f0e3462fb 1926 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
bogdanm 66:9c8f0e3462fb 1927 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
bogdanm 66:9c8f0e3462fb 1928 /* COMP Bit Fields */
bogdanm 66:9c8f0e3462fb 1929 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1930 #define MTBDWT_COMP_COMP_SHIFT 0
bogdanm 66:9c8f0e3462fb 1931 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
bogdanm 66:9c8f0e3462fb 1932 /* MASK Bit Fields */
bogdanm 66:9c8f0e3462fb 1933 #define MTBDWT_MASK_MASK_MASK 0x1Fu
bogdanm 66:9c8f0e3462fb 1934 #define MTBDWT_MASK_MASK_SHIFT 0
bogdanm 66:9c8f0e3462fb 1935 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
bogdanm 66:9c8f0e3462fb 1936 /* FCT Bit Fields */
bogdanm 66:9c8f0e3462fb 1937 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
bogdanm 66:9c8f0e3462fb 1938 #define MTBDWT_FCT_FUNCTION_SHIFT 0
bogdanm 66:9c8f0e3462fb 1939 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
bogdanm 66:9c8f0e3462fb 1940 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
bogdanm 66:9c8f0e3462fb 1941 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
bogdanm 66:9c8f0e3462fb 1942 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
bogdanm 66:9c8f0e3462fb 1943 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
bogdanm 66:9c8f0e3462fb 1944 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
bogdanm 66:9c8f0e3462fb 1945 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
bogdanm 66:9c8f0e3462fb 1946 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
bogdanm 66:9c8f0e3462fb 1947 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
bogdanm 66:9c8f0e3462fb 1948 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
bogdanm 66:9c8f0e3462fb 1949 #define MTBDWT_FCT_MATCHED_SHIFT 24
bogdanm 66:9c8f0e3462fb 1950 /* TBCTRL Bit Fields */
bogdanm 66:9c8f0e3462fb 1951 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
bogdanm 66:9c8f0e3462fb 1952 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
bogdanm 66:9c8f0e3462fb 1953 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
bogdanm 66:9c8f0e3462fb 1954 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
bogdanm 66:9c8f0e3462fb 1955 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
bogdanm 66:9c8f0e3462fb 1956 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
bogdanm 66:9c8f0e3462fb 1957 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
bogdanm 66:9c8f0e3462fb 1958 /* DEVICECFG Bit Fields */
bogdanm 66:9c8f0e3462fb 1959 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1960 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
bogdanm 66:9c8f0e3462fb 1961 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
bogdanm 66:9c8f0e3462fb 1962 /* DEVICETYPID Bit Fields */
bogdanm 66:9c8f0e3462fb 1963 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1964 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
bogdanm 66:9c8f0e3462fb 1965 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
bogdanm 66:9c8f0e3462fb 1966 /* PERIPHID Bit Fields */
bogdanm 66:9c8f0e3462fb 1967 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1968 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
bogdanm 66:9c8f0e3462fb 1969 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
bogdanm 66:9c8f0e3462fb 1970 /* COMPID Bit Fields */
bogdanm 66:9c8f0e3462fb 1971 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 1972 #define MTBDWT_COMPID_COMPID_SHIFT 0
bogdanm 66:9c8f0e3462fb 1973 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
bogdanm 66:9c8f0e3462fb 1974
bogdanm 66:9c8f0e3462fb 1975 /**
bogdanm 66:9c8f0e3462fb 1976 * @}
bogdanm 66:9c8f0e3462fb 1977 */ /* end of group MTBDWT_Register_Masks */
bogdanm 66:9c8f0e3462fb 1978
bogdanm 66:9c8f0e3462fb 1979
bogdanm 66:9c8f0e3462fb 1980 /* MTBDWT - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 1981 /** Peripheral MTBDWT base address */
bogdanm 66:9c8f0e3462fb 1982 #define MTBDWT_BASE (0xF0001000u)
bogdanm 66:9c8f0e3462fb 1983 /** Peripheral MTBDWT base pointer */
bogdanm 66:9c8f0e3462fb 1984 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
bogdanm 66:9c8f0e3462fb 1985 /** Array initializer of MTBDWT peripheral base pointers */
bogdanm 66:9c8f0e3462fb 1986 #define MTBDWT_BASES { MTBDWT }
bogdanm 66:9c8f0e3462fb 1987
bogdanm 66:9c8f0e3462fb 1988 /**
bogdanm 66:9c8f0e3462fb 1989 * @}
bogdanm 66:9c8f0e3462fb 1990 */ /* end of group MTBDWT_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 1991
bogdanm 66:9c8f0e3462fb 1992
bogdanm 66:9c8f0e3462fb 1993 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 1994 -- NV Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1995 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 1996
bogdanm 66:9c8f0e3462fb 1997 /**
bogdanm 66:9c8f0e3462fb 1998 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 1999 * @{
bogdanm 66:9c8f0e3462fb 2000 */
bogdanm 66:9c8f0e3462fb 2001
bogdanm 66:9c8f0e3462fb 2002 /** NV - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 2003 typedef struct {
bogdanm 66:9c8f0e3462fb 2004 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
bogdanm 66:9c8f0e3462fb 2005 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
bogdanm 66:9c8f0e3462fb 2006 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
bogdanm 66:9c8f0e3462fb 2007 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
bogdanm 66:9c8f0e3462fb 2008 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
bogdanm 66:9c8f0e3462fb 2009 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
bogdanm 66:9c8f0e3462fb 2010 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
bogdanm 66:9c8f0e3462fb 2011 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
bogdanm 66:9c8f0e3462fb 2012 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 2013 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
bogdanm 66:9c8f0e3462fb 2014 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
bogdanm 66:9c8f0e3462fb 2015 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
bogdanm 66:9c8f0e3462fb 2016 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
bogdanm 66:9c8f0e3462fb 2017 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
bogdanm 66:9c8f0e3462fb 2018 } NV_Type;
bogdanm 66:9c8f0e3462fb 2019
bogdanm 66:9c8f0e3462fb 2020 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2021 -- NV Register Masks
bogdanm 66:9c8f0e3462fb 2022 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2023
bogdanm 66:9c8f0e3462fb 2024 /**
bogdanm 66:9c8f0e3462fb 2025 * @addtogroup NV_Register_Masks NV Register Masks
bogdanm 66:9c8f0e3462fb 2026 * @{
bogdanm 66:9c8f0e3462fb 2027 */
bogdanm 66:9c8f0e3462fb 2028
bogdanm 66:9c8f0e3462fb 2029 /* BACKKEY3 Bit Fields */
bogdanm 66:9c8f0e3462fb 2030 #define NV_BACKKEY3_KEY_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2031 #define NV_BACKKEY3_KEY_SHIFT 0
bogdanm 66:9c8f0e3462fb 2032 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
bogdanm 66:9c8f0e3462fb 2033 /* BACKKEY2 Bit Fields */
bogdanm 66:9c8f0e3462fb 2034 #define NV_BACKKEY2_KEY_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2035 #define NV_BACKKEY2_KEY_SHIFT 0
bogdanm 66:9c8f0e3462fb 2036 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
bogdanm 66:9c8f0e3462fb 2037 /* BACKKEY1 Bit Fields */
bogdanm 66:9c8f0e3462fb 2038 #define NV_BACKKEY1_KEY_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2039 #define NV_BACKKEY1_KEY_SHIFT 0
bogdanm 66:9c8f0e3462fb 2040 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
bogdanm 66:9c8f0e3462fb 2041 /* BACKKEY0 Bit Fields */
bogdanm 66:9c8f0e3462fb 2042 #define NV_BACKKEY0_KEY_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2043 #define NV_BACKKEY0_KEY_SHIFT 0
bogdanm 66:9c8f0e3462fb 2044 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
bogdanm 66:9c8f0e3462fb 2045 /* BACKKEY7 Bit Fields */
bogdanm 66:9c8f0e3462fb 2046 #define NV_BACKKEY7_KEY_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2047 #define NV_BACKKEY7_KEY_SHIFT 0
bogdanm 66:9c8f0e3462fb 2048 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
bogdanm 66:9c8f0e3462fb 2049 /* BACKKEY6 Bit Fields */
bogdanm 66:9c8f0e3462fb 2050 #define NV_BACKKEY6_KEY_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2051 #define NV_BACKKEY6_KEY_SHIFT 0
bogdanm 66:9c8f0e3462fb 2052 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
bogdanm 66:9c8f0e3462fb 2053 /* BACKKEY5 Bit Fields */
bogdanm 66:9c8f0e3462fb 2054 #define NV_BACKKEY5_KEY_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2055 #define NV_BACKKEY5_KEY_SHIFT 0
bogdanm 66:9c8f0e3462fb 2056 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
bogdanm 66:9c8f0e3462fb 2057 /* BACKKEY4 Bit Fields */
bogdanm 66:9c8f0e3462fb 2058 #define NV_BACKKEY4_KEY_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2059 #define NV_BACKKEY4_KEY_SHIFT 0
bogdanm 66:9c8f0e3462fb 2060 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
bogdanm 66:9c8f0e3462fb 2061 /* FPROT3 Bit Fields */
bogdanm 66:9c8f0e3462fb 2062 #define NV_FPROT3_PROT_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2063 #define NV_FPROT3_PROT_SHIFT 0
bogdanm 66:9c8f0e3462fb 2064 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
bogdanm 66:9c8f0e3462fb 2065 /* FPROT2 Bit Fields */
bogdanm 66:9c8f0e3462fb 2066 #define NV_FPROT2_PROT_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2067 #define NV_FPROT2_PROT_SHIFT 0
bogdanm 66:9c8f0e3462fb 2068 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
bogdanm 66:9c8f0e3462fb 2069 /* FPROT1 Bit Fields */
bogdanm 66:9c8f0e3462fb 2070 #define NV_FPROT1_PROT_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2071 #define NV_FPROT1_PROT_SHIFT 0
bogdanm 66:9c8f0e3462fb 2072 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
bogdanm 66:9c8f0e3462fb 2073 /* FPROT0 Bit Fields */
bogdanm 66:9c8f0e3462fb 2074 #define NV_FPROT0_PROT_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2075 #define NV_FPROT0_PROT_SHIFT 0
bogdanm 66:9c8f0e3462fb 2076 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
bogdanm 66:9c8f0e3462fb 2077 /* FSEC Bit Fields */
bogdanm 66:9c8f0e3462fb 2078 #define NV_FSEC_SEC_MASK 0x3u
bogdanm 66:9c8f0e3462fb 2079 #define NV_FSEC_SEC_SHIFT 0
bogdanm 66:9c8f0e3462fb 2080 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
bogdanm 66:9c8f0e3462fb 2081 #define NV_FSEC_FSLACC_MASK 0xCu
bogdanm 66:9c8f0e3462fb 2082 #define NV_FSEC_FSLACC_SHIFT 2
bogdanm 66:9c8f0e3462fb 2083 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
bogdanm 66:9c8f0e3462fb 2084 #define NV_FSEC_MEEN_MASK 0x30u
bogdanm 66:9c8f0e3462fb 2085 #define NV_FSEC_MEEN_SHIFT 4
bogdanm 66:9c8f0e3462fb 2086 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
bogdanm 66:9c8f0e3462fb 2087 #define NV_FSEC_KEYEN_MASK 0xC0u
bogdanm 66:9c8f0e3462fb 2088 #define NV_FSEC_KEYEN_SHIFT 6
bogdanm 66:9c8f0e3462fb 2089 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
bogdanm 66:9c8f0e3462fb 2090 /* FOPT Bit Fields */
bogdanm 66:9c8f0e3462fb 2091 #define NV_FOPT_LPBOOT0_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2092 #define NV_FOPT_LPBOOT0_SHIFT 0
bogdanm 66:9c8f0e3462fb 2093 #define NV_FOPT_NMI_DIS_MASK 0x4u
bogdanm 66:9c8f0e3462fb 2094 #define NV_FOPT_NMI_DIS_SHIFT 2
bogdanm 66:9c8f0e3462fb 2095 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
bogdanm 66:9c8f0e3462fb 2096 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
bogdanm 66:9c8f0e3462fb 2097 #define NV_FOPT_LPBOOT1_MASK 0x10u
bogdanm 66:9c8f0e3462fb 2098 #define NV_FOPT_LPBOOT1_SHIFT 4
bogdanm 66:9c8f0e3462fb 2099 #define NV_FOPT_FAST_INIT_MASK 0x20u
bogdanm 66:9c8f0e3462fb 2100 #define NV_FOPT_FAST_INIT_SHIFT 5
bogdanm 66:9c8f0e3462fb 2101
bogdanm 66:9c8f0e3462fb 2102 /**
bogdanm 66:9c8f0e3462fb 2103 * @}
bogdanm 66:9c8f0e3462fb 2104 */ /* end of group NV_Register_Masks */
bogdanm 66:9c8f0e3462fb 2105
bogdanm 66:9c8f0e3462fb 2106
bogdanm 66:9c8f0e3462fb 2107 /* NV - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 2108 /** Peripheral FTFA_FlashConfig base address */
bogdanm 66:9c8f0e3462fb 2109 #define FTFA_FlashConfig_BASE (0x400u)
bogdanm 66:9c8f0e3462fb 2110 /** Peripheral FTFA_FlashConfig base pointer */
bogdanm 66:9c8f0e3462fb 2111 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
bogdanm 66:9c8f0e3462fb 2112 /** Array initializer of NV peripheral base pointers */
bogdanm 66:9c8f0e3462fb 2113 #define NV_BASES { FTFA_FlashConfig }
bogdanm 66:9c8f0e3462fb 2114
bogdanm 66:9c8f0e3462fb 2115 /**
bogdanm 66:9c8f0e3462fb 2116 * @}
bogdanm 66:9c8f0e3462fb 2117 */ /* end of group NV_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 2118
bogdanm 66:9c8f0e3462fb 2119
bogdanm 66:9c8f0e3462fb 2120 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2121 -- OSC Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2122 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2123
bogdanm 66:9c8f0e3462fb 2124 /**
bogdanm 66:9c8f0e3462fb 2125 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2126 * @{
bogdanm 66:9c8f0e3462fb 2127 */
bogdanm 66:9c8f0e3462fb 2128
bogdanm 66:9c8f0e3462fb 2129 /** OSC - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 2130 typedef struct {
bogdanm 66:9c8f0e3462fb 2131 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 2132 } OSC_Type;
bogdanm 66:9c8f0e3462fb 2133
bogdanm 66:9c8f0e3462fb 2134 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2135 -- OSC Register Masks
bogdanm 66:9c8f0e3462fb 2136 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2137
bogdanm 66:9c8f0e3462fb 2138 /**
bogdanm 66:9c8f0e3462fb 2139 * @addtogroup OSC_Register_Masks OSC Register Masks
bogdanm 66:9c8f0e3462fb 2140 * @{
bogdanm 66:9c8f0e3462fb 2141 */
bogdanm 66:9c8f0e3462fb 2142
bogdanm 66:9c8f0e3462fb 2143 /* CR Bit Fields */
bogdanm 66:9c8f0e3462fb 2144 #define OSC_CR_SC16P_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2145 #define OSC_CR_SC16P_SHIFT 0
bogdanm 66:9c8f0e3462fb 2146 #define OSC_CR_SC8P_MASK 0x2u
bogdanm 66:9c8f0e3462fb 2147 #define OSC_CR_SC8P_SHIFT 1
bogdanm 66:9c8f0e3462fb 2148 #define OSC_CR_SC4P_MASK 0x4u
bogdanm 66:9c8f0e3462fb 2149 #define OSC_CR_SC4P_SHIFT 2
bogdanm 66:9c8f0e3462fb 2150 #define OSC_CR_SC2P_MASK 0x8u
bogdanm 66:9c8f0e3462fb 2151 #define OSC_CR_SC2P_SHIFT 3
bogdanm 66:9c8f0e3462fb 2152 #define OSC_CR_EREFSTEN_MASK 0x20u
bogdanm 66:9c8f0e3462fb 2153 #define OSC_CR_EREFSTEN_SHIFT 5
bogdanm 66:9c8f0e3462fb 2154 #define OSC_CR_ERCLKEN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 2155 #define OSC_CR_ERCLKEN_SHIFT 7
bogdanm 66:9c8f0e3462fb 2156
bogdanm 66:9c8f0e3462fb 2157 /**
bogdanm 66:9c8f0e3462fb 2158 * @}
bogdanm 66:9c8f0e3462fb 2159 */ /* end of group OSC_Register_Masks */
bogdanm 66:9c8f0e3462fb 2160
bogdanm 66:9c8f0e3462fb 2161
bogdanm 66:9c8f0e3462fb 2162 /* OSC - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 2163 /** Peripheral OSC0 base address */
bogdanm 66:9c8f0e3462fb 2164 #define OSC0_BASE (0x40065000u)
bogdanm 66:9c8f0e3462fb 2165 /** Peripheral OSC0 base pointer */
bogdanm 66:9c8f0e3462fb 2166 #define OSC0 ((OSC_Type *)OSC0_BASE)
bogdanm 66:9c8f0e3462fb 2167 /** Array initializer of OSC peripheral base pointers */
bogdanm 66:9c8f0e3462fb 2168 #define OSC_BASES { OSC0 }
bogdanm 66:9c8f0e3462fb 2169
bogdanm 66:9c8f0e3462fb 2170 /**
bogdanm 66:9c8f0e3462fb 2171 * @}
bogdanm 66:9c8f0e3462fb 2172 */ /* end of group OSC_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 2173
bogdanm 66:9c8f0e3462fb 2174
bogdanm 66:9c8f0e3462fb 2175 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2176 -- PIT Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2177 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2178
bogdanm 66:9c8f0e3462fb 2179 /**
bogdanm 66:9c8f0e3462fb 2180 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2181 * @{
bogdanm 66:9c8f0e3462fb 2182 */
bogdanm 66:9c8f0e3462fb 2183
bogdanm 66:9c8f0e3462fb 2184 /** PIT - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 2185 typedef struct {
bogdanm 66:9c8f0e3462fb 2186 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 2187 uint8_t RESERVED_0[220];
bogdanm 66:9c8f0e3462fb 2188 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
bogdanm 66:9c8f0e3462fb 2189 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
bogdanm 66:9c8f0e3462fb 2190 uint8_t RESERVED_1[24];
bogdanm 66:9c8f0e3462fb 2191 struct { /* offset: 0x100, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 2192 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 2193 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 2194 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 2195 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
bogdanm 66:9c8f0e3462fb 2196 } CHANNEL[2];
bogdanm 66:9c8f0e3462fb 2197 } PIT_Type;
bogdanm 66:9c8f0e3462fb 2198
bogdanm 66:9c8f0e3462fb 2199 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2200 -- PIT Register Masks
bogdanm 66:9c8f0e3462fb 2201 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2202
bogdanm 66:9c8f0e3462fb 2203 /**
bogdanm 66:9c8f0e3462fb 2204 * @addtogroup PIT_Register_Masks PIT Register Masks
bogdanm 66:9c8f0e3462fb 2205 * @{
bogdanm 66:9c8f0e3462fb 2206 */
bogdanm 66:9c8f0e3462fb 2207
bogdanm 66:9c8f0e3462fb 2208 /* MCR Bit Fields */
bogdanm 66:9c8f0e3462fb 2209 #define PIT_MCR_FRZ_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2210 #define PIT_MCR_FRZ_SHIFT 0
bogdanm 66:9c8f0e3462fb 2211 #define PIT_MCR_MDIS_MASK 0x2u
bogdanm 66:9c8f0e3462fb 2212 #define PIT_MCR_MDIS_SHIFT 1
bogdanm 66:9c8f0e3462fb 2213 /* LTMR64H Bit Fields */
bogdanm 66:9c8f0e3462fb 2214 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2215 #define PIT_LTMR64H_LTH_SHIFT 0
bogdanm 66:9c8f0e3462fb 2216 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
bogdanm 66:9c8f0e3462fb 2217 /* LTMR64L Bit Fields */
bogdanm 66:9c8f0e3462fb 2218 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2219 #define PIT_LTMR64L_LTL_SHIFT 0
bogdanm 66:9c8f0e3462fb 2220 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
bogdanm 66:9c8f0e3462fb 2221 /* LDVAL Bit Fields */
bogdanm 66:9c8f0e3462fb 2222 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2223 #define PIT_LDVAL_TSV_SHIFT 0
bogdanm 66:9c8f0e3462fb 2224 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
bogdanm 66:9c8f0e3462fb 2225 /* CVAL Bit Fields */
bogdanm 66:9c8f0e3462fb 2226 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2227 #define PIT_CVAL_TVL_SHIFT 0
bogdanm 66:9c8f0e3462fb 2228 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
bogdanm 66:9c8f0e3462fb 2229 /* TCTRL Bit Fields */
bogdanm 66:9c8f0e3462fb 2230 #define PIT_TCTRL_TEN_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2231 #define PIT_TCTRL_TEN_SHIFT 0
bogdanm 66:9c8f0e3462fb 2232 #define PIT_TCTRL_TIE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 2233 #define PIT_TCTRL_TIE_SHIFT 1
bogdanm 66:9c8f0e3462fb 2234 #define PIT_TCTRL_CHN_MASK 0x4u
bogdanm 66:9c8f0e3462fb 2235 #define PIT_TCTRL_CHN_SHIFT 2
bogdanm 66:9c8f0e3462fb 2236 /* TFLG Bit Fields */
bogdanm 66:9c8f0e3462fb 2237 #define PIT_TFLG_TIF_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2238 #define PIT_TFLG_TIF_SHIFT 0
bogdanm 66:9c8f0e3462fb 2239
bogdanm 66:9c8f0e3462fb 2240 /**
bogdanm 66:9c8f0e3462fb 2241 * @}
bogdanm 66:9c8f0e3462fb 2242 */ /* end of group PIT_Register_Masks */
bogdanm 66:9c8f0e3462fb 2243
bogdanm 66:9c8f0e3462fb 2244
bogdanm 66:9c8f0e3462fb 2245 /* PIT - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 2246 /** Peripheral PIT base address */
bogdanm 66:9c8f0e3462fb 2247 #define PIT_BASE (0x40037000u)
bogdanm 66:9c8f0e3462fb 2248 /** Peripheral PIT base pointer */
bogdanm 66:9c8f0e3462fb 2249 #define PIT ((PIT_Type *)PIT_BASE)
bogdanm 66:9c8f0e3462fb 2250 /** Array initializer of PIT peripheral base pointers */
bogdanm 66:9c8f0e3462fb 2251 #define PIT_BASES { PIT }
bogdanm 66:9c8f0e3462fb 2252
bogdanm 66:9c8f0e3462fb 2253 /**
bogdanm 66:9c8f0e3462fb 2254 * @}
bogdanm 66:9c8f0e3462fb 2255 */ /* end of group PIT_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 2256
bogdanm 66:9c8f0e3462fb 2257
bogdanm 66:9c8f0e3462fb 2258 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2259 -- PMC Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2260 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2261
bogdanm 66:9c8f0e3462fb 2262 /**
bogdanm 66:9c8f0e3462fb 2263 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2264 * @{
bogdanm 66:9c8f0e3462fb 2265 */
bogdanm 66:9c8f0e3462fb 2266
bogdanm 66:9c8f0e3462fb 2267 /** PMC - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 2268 typedef struct {
bogdanm 66:9c8f0e3462fb 2269 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 2270 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
bogdanm 66:9c8f0e3462fb 2271 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
bogdanm 66:9c8f0e3462fb 2272 } PMC_Type;
bogdanm 66:9c8f0e3462fb 2273
bogdanm 66:9c8f0e3462fb 2274 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2275 -- PMC Register Masks
bogdanm 66:9c8f0e3462fb 2276 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2277
bogdanm 66:9c8f0e3462fb 2278 /**
bogdanm 66:9c8f0e3462fb 2279 * @addtogroup PMC_Register_Masks PMC Register Masks
bogdanm 66:9c8f0e3462fb 2280 * @{
bogdanm 66:9c8f0e3462fb 2281 */
bogdanm 66:9c8f0e3462fb 2282
bogdanm 66:9c8f0e3462fb 2283 /* LVDSC1 Bit Fields */
bogdanm 66:9c8f0e3462fb 2284 #define PMC_LVDSC1_LVDV_MASK 0x3u
bogdanm 66:9c8f0e3462fb 2285 #define PMC_LVDSC1_LVDV_SHIFT 0
bogdanm 66:9c8f0e3462fb 2286 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
bogdanm 66:9c8f0e3462fb 2287 #define PMC_LVDSC1_LVDRE_MASK 0x10u
bogdanm 66:9c8f0e3462fb 2288 #define PMC_LVDSC1_LVDRE_SHIFT 4
bogdanm 66:9c8f0e3462fb 2289 #define PMC_LVDSC1_LVDIE_MASK 0x20u
bogdanm 66:9c8f0e3462fb 2290 #define PMC_LVDSC1_LVDIE_SHIFT 5
bogdanm 66:9c8f0e3462fb 2291 #define PMC_LVDSC1_LVDACK_MASK 0x40u
bogdanm 66:9c8f0e3462fb 2292 #define PMC_LVDSC1_LVDACK_SHIFT 6
bogdanm 66:9c8f0e3462fb 2293 #define PMC_LVDSC1_LVDF_MASK 0x80u
bogdanm 66:9c8f0e3462fb 2294 #define PMC_LVDSC1_LVDF_SHIFT 7
bogdanm 66:9c8f0e3462fb 2295 /* LVDSC2 Bit Fields */
bogdanm 66:9c8f0e3462fb 2296 #define PMC_LVDSC2_LVWV_MASK 0x3u
bogdanm 66:9c8f0e3462fb 2297 #define PMC_LVDSC2_LVWV_SHIFT 0
bogdanm 66:9c8f0e3462fb 2298 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
bogdanm 66:9c8f0e3462fb 2299 #define PMC_LVDSC2_LVWIE_MASK 0x20u
bogdanm 66:9c8f0e3462fb 2300 #define PMC_LVDSC2_LVWIE_SHIFT 5
bogdanm 66:9c8f0e3462fb 2301 #define PMC_LVDSC2_LVWACK_MASK 0x40u
bogdanm 66:9c8f0e3462fb 2302 #define PMC_LVDSC2_LVWACK_SHIFT 6
bogdanm 66:9c8f0e3462fb 2303 #define PMC_LVDSC2_LVWF_MASK 0x80u
bogdanm 66:9c8f0e3462fb 2304 #define PMC_LVDSC2_LVWF_SHIFT 7
bogdanm 66:9c8f0e3462fb 2305 /* REGSC Bit Fields */
bogdanm 66:9c8f0e3462fb 2306 #define PMC_REGSC_BGBE_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2307 #define PMC_REGSC_BGBE_SHIFT 0
bogdanm 66:9c8f0e3462fb 2308 #define PMC_REGSC_REGONS_MASK 0x4u
bogdanm 66:9c8f0e3462fb 2309 #define PMC_REGSC_REGONS_SHIFT 2
bogdanm 66:9c8f0e3462fb 2310 #define PMC_REGSC_ACKISO_MASK 0x8u
bogdanm 66:9c8f0e3462fb 2311 #define PMC_REGSC_ACKISO_SHIFT 3
bogdanm 66:9c8f0e3462fb 2312 #define PMC_REGSC_BGEN_MASK 0x10u
bogdanm 66:9c8f0e3462fb 2313 #define PMC_REGSC_BGEN_SHIFT 4
bogdanm 66:9c8f0e3462fb 2314
bogdanm 66:9c8f0e3462fb 2315 /**
bogdanm 66:9c8f0e3462fb 2316 * @}
bogdanm 66:9c8f0e3462fb 2317 */ /* end of group PMC_Register_Masks */
bogdanm 66:9c8f0e3462fb 2318
bogdanm 66:9c8f0e3462fb 2319
bogdanm 66:9c8f0e3462fb 2320 /* PMC - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 2321 /** Peripheral PMC base address */
bogdanm 66:9c8f0e3462fb 2322 #define PMC_BASE (0x4007D000u)
bogdanm 66:9c8f0e3462fb 2323 /** Peripheral PMC base pointer */
bogdanm 66:9c8f0e3462fb 2324 #define PMC ((PMC_Type *)PMC_BASE)
bogdanm 66:9c8f0e3462fb 2325 /** Array initializer of PMC peripheral base pointers */
bogdanm 66:9c8f0e3462fb 2326 #define PMC_BASES { PMC }
bogdanm 66:9c8f0e3462fb 2327
bogdanm 66:9c8f0e3462fb 2328 /**
bogdanm 66:9c8f0e3462fb 2329 * @}
bogdanm 66:9c8f0e3462fb 2330 */ /* end of group PMC_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 2331
bogdanm 66:9c8f0e3462fb 2332
bogdanm 66:9c8f0e3462fb 2333 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2334 -- PORT Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2335 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2336
bogdanm 66:9c8f0e3462fb 2337 /**
bogdanm 66:9c8f0e3462fb 2338 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2339 * @{
bogdanm 66:9c8f0e3462fb 2340 */
bogdanm 66:9c8f0e3462fb 2341
bogdanm 66:9c8f0e3462fb 2342 /** PORT - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 2343 typedef struct {
bogdanm 66:9c8f0e3462fb 2344 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
bogdanm 66:9c8f0e3462fb 2345 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
bogdanm 66:9c8f0e3462fb 2346 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
bogdanm 66:9c8f0e3462fb 2347 uint8_t RESERVED_0[24];
bogdanm 66:9c8f0e3462fb 2348 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
bogdanm 66:9c8f0e3462fb 2349 } PORT_Type;
bogdanm 66:9c8f0e3462fb 2350
bogdanm 66:9c8f0e3462fb 2351 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2352 -- PORT Register Masks
bogdanm 66:9c8f0e3462fb 2353 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2354
bogdanm 66:9c8f0e3462fb 2355 /**
bogdanm 66:9c8f0e3462fb 2356 * @addtogroup PORT_Register_Masks PORT Register Masks
bogdanm 66:9c8f0e3462fb 2357 * @{
bogdanm 66:9c8f0e3462fb 2358 */
bogdanm 66:9c8f0e3462fb 2359
bogdanm 66:9c8f0e3462fb 2360 /* PCR Bit Fields */
bogdanm 66:9c8f0e3462fb 2361 #define PORT_PCR_PS_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2362 #define PORT_PCR_PS_SHIFT 0
bogdanm 66:9c8f0e3462fb 2363 #define PORT_PCR_PE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 2364 #define PORT_PCR_PE_SHIFT 1
bogdanm 66:9c8f0e3462fb 2365 #define PORT_PCR_SRE_MASK 0x4u
bogdanm 66:9c8f0e3462fb 2366 #define PORT_PCR_SRE_SHIFT 2
bogdanm 66:9c8f0e3462fb 2367 #define PORT_PCR_PFE_MASK 0x10u
bogdanm 66:9c8f0e3462fb 2368 #define PORT_PCR_PFE_SHIFT 4
bogdanm 66:9c8f0e3462fb 2369 #define PORT_PCR_DSE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 2370 #define PORT_PCR_DSE_SHIFT 6
bogdanm 66:9c8f0e3462fb 2371 #define PORT_PCR_MUX_MASK 0x700u
bogdanm 66:9c8f0e3462fb 2372 #define PORT_PCR_MUX_SHIFT 8
bogdanm 66:9c8f0e3462fb 2373 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
bogdanm 66:9c8f0e3462fb 2374 #define PORT_PCR_IRQC_MASK 0xF0000u
bogdanm 66:9c8f0e3462fb 2375 #define PORT_PCR_IRQC_SHIFT 16
bogdanm 66:9c8f0e3462fb 2376 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
bogdanm 66:9c8f0e3462fb 2377 #define PORT_PCR_ISF_MASK 0x1000000u
bogdanm 66:9c8f0e3462fb 2378 #define PORT_PCR_ISF_SHIFT 24
bogdanm 66:9c8f0e3462fb 2379 /* GPCLR Bit Fields */
bogdanm 66:9c8f0e3462fb 2380 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 2381 #define PORT_GPCLR_GPWD_SHIFT 0
bogdanm 66:9c8f0e3462fb 2382 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
bogdanm 66:9c8f0e3462fb 2383 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
bogdanm 66:9c8f0e3462fb 2384 #define PORT_GPCLR_GPWE_SHIFT 16
bogdanm 66:9c8f0e3462fb 2385 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
bogdanm 66:9c8f0e3462fb 2386 /* GPCHR Bit Fields */
bogdanm 66:9c8f0e3462fb 2387 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 2388 #define PORT_GPCHR_GPWD_SHIFT 0
bogdanm 66:9c8f0e3462fb 2389 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
bogdanm 66:9c8f0e3462fb 2390 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
bogdanm 66:9c8f0e3462fb 2391 #define PORT_GPCHR_GPWE_SHIFT 16
bogdanm 66:9c8f0e3462fb 2392 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
bogdanm 66:9c8f0e3462fb 2393 /* ISFR Bit Fields */
bogdanm 66:9c8f0e3462fb 2394 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2395 #define PORT_ISFR_ISF_SHIFT 0
bogdanm 66:9c8f0e3462fb 2396 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
bogdanm 66:9c8f0e3462fb 2397
bogdanm 66:9c8f0e3462fb 2398 /**
bogdanm 66:9c8f0e3462fb 2399 * @}
bogdanm 66:9c8f0e3462fb 2400 */ /* end of group PORT_Register_Masks */
bogdanm 66:9c8f0e3462fb 2401
bogdanm 66:9c8f0e3462fb 2402
bogdanm 66:9c8f0e3462fb 2403 /* PORT - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 2404 /** Peripheral PORTA base address */
bogdanm 66:9c8f0e3462fb 2405 #define PORTA_BASE (0x40049000u)
bogdanm 66:9c8f0e3462fb 2406 /** Peripheral PORTA base pointer */
bogdanm 66:9c8f0e3462fb 2407 #define PORTA ((PORT_Type *)PORTA_BASE)
bogdanm 66:9c8f0e3462fb 2408 /** Peripheral PORTB base address */
bogdanm 66:9c8f0e3462fb 2409 #define PORTB_BASE (0x4004A000u)
bogdanm 66:9c8f0e3462fb 2410 /** Peripheral PORTB base pointer */
bogdanm 66:9c8f0e3462fb 2411 #define PORTB ((PORT_Type *)PORTB_BASE)
bogdanm 66:9c8f0e3462fb 2412 /** Peripheral PORTC base address */
bogdanm 66:9c8f0e3462fb 2413 #define PORTC_BASE (0x4004B000u)
bogdanm 66:9c8f0e3462fb 2414 /** Peripheral PORTC base pointer */
bogdanm 66:9c8f0e3462fb 2415 #define PORTC ((PORT_Type *)PORTC_BASE)
bogdanm 66:9c8f0e3462fb 2416 /** Peripheral PORTD base address */
bogdanm 66:9c8f0e3462fb 2417 #define PORTD_BASE (0x4004C000u)
bogdanm 66:9c8f0e3462fb 2418 /** Peripheral PORTD base pointer */
bogdanm 66:9c8f0e3462fb 2419 #define PORTD ((PORT_Type *)PORTD_BASE)
bogdanm 66:9c8f0e3462fb 2420 /** Peripheral PORTE base address */
bogdanm 66:9c8f0e3462fb 2421 #define PORTE_BASE (0x4004D000u)
bogdanm 66:9c8f0e3462fb 2422 /** Peripheral PORTE base pointer */
bogdanm 66:9c8f0e3462fb 2423 #define PORTE ((PORT_Type *)PORTE_BASE)
bogdanm 66:9c8f0e3462fb 2424 /** Array initializer of PORT peripheral base pointers */
bogdanm 66:9c8f0e3462fb 2425 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
bogdanm 66:9c8f0e3462fb 2426
bogdanm 66:9c8f0e3462fb 2427 /**
bogdanm 66:9c8f0e3462fb 2428 * @}
bogdanm 66:9c8f0e3462fb 2429 */ /* end of group PORT_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 2430
bogdanm 66:9c8f0e3462fb 2431
bogdanm 66:9c8f0e3462fb 2432 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2433 -- RCM Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2434 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2435
bogdanm 66:9c8f0e3462fb 2436 /**
bogdanm 66:9c8f0e3462fb 2437 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2438 * @{
bogdanm 66:9c8f0e3462fb 2439 */
bogdanm 66:9c8f0e3462fb 2440
bogdanm 66:9c8f0e3462fb 2441 /** RCM - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 2442 typedef struct {
bogdanm 66:9c8f0e3462fb 2443 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 2444 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
bogdanm 66:9c8f0e3462fb 2445 uint8_t RESERVED_0[2];
bogdanm 66:9c8f0e3462fb 2446 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 2447 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
bogdanm 66:9c8f0e3462fb 2448 } RCM_Type;
bogdanm 66:9c8f0e3462fb 2449
bogdanm 66:9c8f0e3462fb 2450 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2451 -- RCM Register Masks
bogdanm 66:9c8f0e3462fb 2452 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2453
bogdanm 66:9c8f0e3462fb 2454 /**
bogdanm 66:9c8f0e3462fb 2455 * @addtogroup RCM_Register_Masks RCM Register Masks
bogdanm 66:9c8f0e3462fb 2456 * @{
bogdanm 66:9c8f0e3462fb 2457 */
bogdanm 66:9c8f0e3462fb 2458
bogdanm 66:9c8f0e3462fb 2459 /* SRS0 Bit Fields */
bogdanm 66:9c8f0e3462fb 2460 #define RCM_SRS0_WAKEUP_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2461 #define RCM_SRS0_WAKEUP_SHIFT 0
bogdanm 66:9c8f0e3462fb 2462 #define RCM_SRS0_LVD_MASK 0x2u
bogdanm 66:9c8f0e3462fb 2463 #define RCM_SRS0_LVD_SHIFT 1
bogdanm 66:9c8f0e3462fb 2464 #define RCM_SRS0_LOC_MASK 0x4u
bogdanm 66:9c8f0e3462fb 2465 #define RCM_SRS0_LOC_SHIFT 2
bogdanm 66:9c8f0e3462fb 2466 #define RCM_SRS0_LOL_MASK 0x8u
bogdanm 66:9c8f0e3462fb 2467 #define RCM_SRS0_LOL_SHIFT 3
bogdanm 66:9c8f0e3462fb 2468 #define RCM_SRS0_WDOG_MASK 0x20u
bogdanm 66:9c8f0e3462fb 2469 #define RCM_SRS0_WDOG_SHIFT 5
bogdanm 66:9c8f0e3462fb 2470 #define RCM_SRS0_PIN_MASK 0x40u
bogdanm 66:9c8f0e3462fb 2471 #define RCM_SRS0_PIN_SHIFT 6
bogdanm 66:9c8f0e3462fb 2472 #define RCM_SRS0_POR_MASK 0x80u
bogdanm 66:9c8f0e3462fb 2473 #define RCM_SRS0_POR_SHIFT 7
bogdanm 66:9c8f0e3462fb 2474 /* SRS1 Bit Fields */
bogdanm 66:9c8f0e3462fb 2475 #define RCM_SRS1_LOCKUP_MASK 0x2u
bogdanm 66:9c8f0e3462fb 2476 #define RCM_SRS1_LOCKUP_SHIFT 1
bogdanm 66:9c8f0e3462fb 2477 #define RCM_SRS1_SW_MASK 0x4u
bogdanm 66:9c8f0e3462fb 2478 #define RCM_SRS1_SW_SHIFT 2
bogdanm 66:9c8f0e3462fb 2479 #define RCM_SRS1_MDM_AP_MASK 0x8u
bogdanm 66:9c8f0e3462fb 2480 #define RCM_SRS1_MDM_AP_SHIFT 3
bogdanm 66:9c8f0e3462fb 2481 #define RCM_SRS1_SACKERR_MASK 0x20u
bogdanm 66:9c8f0e3462fb 2482 #define RCM_SRS1_SACKERR_SHIFT 5
bogdanm 66:9c8f0e3462fb 2483 /* RPFC Bit Fields */
bogdanm 66:9c8f0e3462fb 2484 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
bogdanm 66:9c8f0e3462fb 2485 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
bogdanm 66:9c8f0e3462fb 2486 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
bogdanm 66:9c8f0e3462fb 2487 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
bogdanm 66:9c8f0e3462fb 2488 #define RCM_RPFC_RSTFLTSS_SHIFT 2
bogdanm 66:9c8f0e3462fb 2489 /* RPFW Bit Fields */
bogdanm 66:9c8f0e3462fb 2490 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
bogdanm 66:9c8f0e3462fb 2491 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
bogdanm 66:9c8f0e3462fb 2492 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
bogdanm 66:9c8f0e3462fb 2493
bogdanm 66:9c8f0e3462fb 2494 /**
bogdanm 66:9c8f0e3462fb 2495 * @}
bogdanm 66:9c8f0e3462fb 2496 */ /* end of group RCM_Register_Masks */
bogdanm 66:9c8f0e3462fb 2497
bogdanm 66:9c8f0e3462fb 2498
bogdanm 66:9c8f0e3462fb 2499 /* RCM - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 2500 /** Peripheral RCM base address */
bogdanm 66:9c8f0e3462fb 2501 #define RCM_BASE (0x4007F000u)
bogdanm 66:9c8f0e3462fb 2502 /** Peripheral RCM base pointer */
bogdanm 66:9c8f0e3462fb 2503 #define RCM ((RCM_Type *)RCM_BASE)
bogdanm 66:9c8f0e3462fb 2504 /** Array initializer of RCM peripheral base pointers */
bogdanm 66:9c8f0e3462fb 2505 #define RCM_BASES { RCM }
bogdanm 66:9c8f0e3462fb 2506
bogdanm 66:9c8f0e3462fb 2507 /**
bogdanm 66:9c8f0e3462fb 2508 * @}
bogdanm 66:9c8f0e3462fb 2509 */ /* end of group RCM_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 2510
bogdanm 66:9c8f0e3462fb 2511
bogdanm 66:9c8f0e3462fb 2512 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2513 -- ROM Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2514 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2515
bogdanm 66:9c8f0e3462fb 2516 /**
bogdanm 66:9c8f0e3462fb 2517 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2518 * @{
bogdanm 66:9c8f0e3462fb 2519 */
bogdanm 66:9c8f0e3462fb 2520
bogdanm 66:9c8f0e3462fb 2521 /** ROM - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 2522 typedef struct {
bogdanm 66:9c8f0e3462fb 2523 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
bogdanm 66:9c8f0e3462fb 2524 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
bogdanm 66:9c8f0e3462fb 2525 uint8_t RESERVED_0[4028];
bogdanm 66:9c8f0e3462fb 2526 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
bogdanm 66:9c8f0e3462fb 2527 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
bogdanm 66:9c8f0e3462fb 2528 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
bogdanm 66:9c8f0e3462fb 2529 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
bogdanm 66:9c8f0e3462fb 2530 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
bogdanm 66:9c8f0e3462fb 2531 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
bogdanm 66:9c8f0e3462fb 2532 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
bogdanm 66:9c8f0e3462fb 2533 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
bogdanm 66:9c8f0e3462fb 2534 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
bogdanm 66:9c8f0e3462fb 2535 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
bogdanm 66:9c8f0e3462fb 2536 } ROM_Type;
bogdanm 66:9c8f0e3462fb 2537
bogdanm 66:9c8f0e3462fb 2538 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2539 -- ROM Register Masks
bogdanm 66:9c8f0e3462fb 2540 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2541
bogdanm 66:9c8f0e3462fb 2542 /**
bogdanm 66:9c8f0e3462fb 2543 * @addtogroup ROM_Register_Masks ROM Register Masks
bogdanm 66:9c8f0e3462fb 2544 * @{
bogdanm 66:9c8f0e3462fb 2545 */
bogdanm 66:9c8f0e3462fb 2546
bogdanm 66:9c8f0e3462fb 2547 /* ENTRY Bit Fields */
bogdanm 66:9c8f0e3462fb 2548 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2549 #define ROM_ENTRY_ENTRY_SHIFT 0
bogdanm 66:9c8f0e3462fb 2550 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
bogdanm 66:9c8f0e3462fb 2551 /* TABLEMARK Bit Fields */
bogdanm 66:9c8f0e3462fb 2552 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2553 #define ROM_TABLEMARK_MARK_SHIFT 0
bogdanm 66:9c8f0e3462fb 2554 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
bogdanm 66:9c8f0e3462fb 2555 /* SYSACCESS Bit Fields */
bogdanm 66:9c8f0e3462fb 2556 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2557 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
bogdanm 66:9c8f0e3462fb 2558 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
bogdanm 66:9c8f0e3462fb 2559 /* PERIPHID4 Bit Fields */
bogdanm 66:9c8f0e3462fb 2560 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2561 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2562 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
bogdanm 66:9c8f0e3462fb 2563 /* PERIPHID5 Bit Fields */
bogdanm 66:9c8f0e3462fb 2564 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2565 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2566 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
bogdanm 66:9c8f0e3462fb 2567 /* PERIPHID6 Bit Fields */
bogdanm 66:9c8f0e3462fb 2568 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2569 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2570 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
bogdanm 66:9c8f0e3462fb 2571 /* PERIPHID7 Bit Fields */
bogdanm 66:9c8f0e3462fb 2572 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2573 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2574 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
bogdanm 66:9c8f0e3462fb 2575 /* PERIPHID0 Bit Fields */
bogdanm 66:9c8f0e3462fb 2576 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2577 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2578 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
bogdanm 66:9c8f0e3462fb 2579 /* PERIPHID1 Bit Fields */
bogdanm 66:9c8f0e3462fb 2580 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2581 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2582 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
bogdanm 66:9c8f0e3462fb 2583 /* PERIPHID2 Bit Fields */
bogdanm 66:9c8f0e3462fb 2584 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2585 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2586 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
bogdanm 66:9c8f0e3462fb 2587 /* PERIPHID3 Bit Fields */
bogdanm 66:9c8f0e3462fb 2588 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2589 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2590 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
bogdanm 66:9c8f0e3462fb 2591 /* COMPID Bit Fields */
bogdanm 66:9c8f0e3462fb 2592 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2593 #define ROM_COMPID_COMPID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2594 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
bogdanm 66:9c8f0e3462fb 2595
bogdanm 66:9c8f0e3462fb 2596 /**
bogdanm 66:9c8f0e3462fb 2597 * @}
bogdanm 66:9c8f0e3462fb 2598 */ /* end of group ROM_Register_Masks */
bogdanm 66:9c8f0e3462fb 2599
bogdanm 66:9c8f0e3462fb 2600
bogdanm 66:9c8f0e3462fb 2601 /* ROM - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 2602 /** Peripheral ROM base address */
bogdanm 66:9c8f0e3462fb 2603 #define ROM_BASE (0xF0002000u)
bogdanm 66:9c8f0e3462fb 2604 /** Peripheral ROM base pointer */
bogdanm 66:9c8f0e3462fb 2605 #define ROM ((ROM_Type *)ROM_BASE)
bogdanm 66:9c8f0e3462fb 2606 /** Array initializer of ROM peripheral base pointers */
bogdanm 66:9c8f0e3462fb 2607 #define ROM_BASES { ROM }
bogdanm 66:9c8f0e3462fb 2608
bogdanm 66:9c8f0e3462fb 2609 /**
bogdanm 66:9c8f0e3462fb 2610 * @}
bogdanm 66:9c8f0e3462fb 2611 */ /* end of group ROM_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 2612
bogdanm 66:9c8f0e3462fb 2613
bogdanm 66:9c8f0e3462fb 2614 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2615 -- RTC Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2616 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2617
bogdanm 66:9c8f0e3462fb 2618 /**
bogdanm 66:9c8f0e3462fb 2619 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2620 * @{
bogdanm 66:9c8f0e3462fb 2621 */
bogdanm 66:9c8f0e3462fb 2622
bogdanm 66:9c8f0e3462fb 2623 /** RTC - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 2624 typedef struct {
bogdanm 66:9c8f0e3462fb 2625 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 2626 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 2627 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 2628 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
bogdanm 66:9c8f0e3462fb 2629 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
bogdanm 66:9c8f0e3462fb 2630 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
bogdanm 66:9c8f0e3462fb 2631 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
bogdanm 66:9c8f0e3462fb 2632 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
bogdanm 66:9c8f0e3462fb 2633 } RTC_Type;
bogdanm 66:9c8f0e3462fb 2634
bogdanm 66:9c8f0e3462fb 2635 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2636 -- RTC Register Masks
bogdanm 66:9c8f0e3462fb 2637 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2638
bogdanm 66:9c8f0e3462fb 2639 /**
bogdanm 66:9c8f0e3462fb 2640 * @addtogroup RTC_Register_Masks RTC Register Masks
bogdanm 66:9c8f0e3462fb 2641 * @{
bogdanm 66:9c8f0e3462fb 2642 */
bogdanm 66:9c8f0e3462fb 2643
bogdanm 66:9c8f0e3462fb 2644 /* TSR Bit Fields */
bogdanm 66:9c8f0e3462fb 2645 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2646 #define RTC_TSR_TSR_SHIFT 0
bogdanm 66:9c8f0e3462fb 2647 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
bogdanm 66:9c8f0e3462fb 2648 /* TPR Bit Fields */
bogdanm 66:9c8f0e3462fb 2649 #define RTC_TPR_TPR_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 2650 #define RTC_TPR_TPR_SHIFT 0
bogdanm 66:9c8f0e3462fb 2651 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
bogdanm 66:9c8f0e3462fb 2652 /* TAR Bit Fields */
bogdanm 66:9c8f0e3462fb 2653 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2654 #define RTC_TAR_TAR_SHIFT 0
bogdanm 66:9c8f0e3462fb 2655 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
bogdanm 66:9c8f0e3462fb 2656 /* TCR Bit Fields */
bogdanm 66:9c8f0e3462fb 2657 #define RTC_TCR_TCR_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2658 #define RTC_TCR_TCR_SHIFT 0
bogdanm 66:9c8f0e3462fb 2659 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
bogdanm 66:9c8f0e3462fb 2660 #define RTC_TCR_CIR_MASK 0xFF00u
bogdanm 66:9c8f0e3462fb 2661 #define RTC_TCR_CIR_SHIFT 8
bogdanm 66:9c8f0e3462fb 2662 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
bogdanm 66:9c8f0e3462fb 2663 #define RTC_TCR_TCV_MASK 0xFF0000u
bogdanm 66:9c8f0e3462fb 2664 #define RTC_TCR_TCV_SHIFT 16
bogdanm 66:9c8f0e3462fb 2665 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
bogdanm 66:9c8f0e3462fb 2666 #define RTC_TCR_CIC_MASK 0xFF000000u
bogdanm 66:9c8f0e3462fb 2667 #define RTC_TCR_CIC_SHIFT 24
bogdanm 66:9c8f0e3462fb 2668 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
bogdanm 66:9c8f0e3462fb 2669 /* CR Bit Fields */
bogdanm 66:9c8f0e3462fb 2670 #define RTC_CR_SWR_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2671 #define RTC_CR_SWR_SHIFT 0
bogdanm 66:9c8f0e3462fb 2672 #define RTC_CR_WPE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 2673 #define RTC_CR_WPE_SHIFT 1
bogdanm 66:9c8f0e3462fb 2674 #define RTC_CR_SUP_MASK 0x4u
bogdanm 66:9c8f0e3462fb 2675 #define RTC_CR_SUP_SHIFT 2
bogdanm 66:9c8f0e3462fb 2676 #define RTC_CR_UM_MASK 0x8u
bogdanm 66:9c8f0e3462fb 2677 #define RTC_CR_UM_SHIFT 3
bogdanm 66:9c8f0e3462fb 2678 #define RTC_CR_OSCE_MASK 0x100u
bogdanm 66:9c8f0e3462fb 2679 #define RTC_CR_OSCE_SHIFT 8
bogdanm 66:9c8f0e3462fb 2680 #define RTC_CR_CLKO_MASK 0x200u
bogdanm 66:9c8f0e3462fb 2681 #define RTC_CR_CLKO_SHIFT 9
bogdanm 66:9c8f0e3462fb 2682 #define RTC_CR_SC16P_MASK 0x400u
bogdanm 66:9c8f0e3462fb 2683 #define RTC_CR_SC16P_SHIFT 10
bogdanm 66:9c8f0e3462fb 2684 #define RTC_CR_SC8P_MASK 0x800u
bogdanm 66:9c8f0e3462fb 2685 #define RTC_CR_SC8P_SHIFT 11
bogdanm 66:9c8f0e3462fb 2686 #define RTC_CR_SC4P_MASK 0x1000u
bogdanm 66:9c8f0e3462fb 2687 #define RTC_CR_SC4P_SHIFT 12
bogdanm 66:9c8f0e3462fb 2688 #define RTC_CR_SC2P_MASK 0x2000u
bogdanm 66:9c8f0e3462fb 2689 #define RTC_CR_SC2P_SHIFT 13
bogdanm 66:9c8f0e3462fb 2690 /* SR Bit Fields */
bogdanm 66:9c8f0e3462fb 2691 #define RTC_SR_TIF_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2692 #define RTC_SR_TIF_SHIFT 0
bogdanm 66:9c8f0e3462fb 2693 #define RTC_SR_TOF_MASK 0x2u
bogdanm 66:9c8f0e3462fb 2694 #define RTC_SR_TOF_SHIFT 1
bogdanm 66:9c8f0e3462fb 2695 #define RTC_SR_TAF_MASK 0x4u
bogdanm 66:9c8f0e3462fb 2696 #define RTC_SR_TAF_SHIFT 2
bogdanm 66:9c8f0e3462fb 2697 #define RTC_SR_TCE_MASK 0x10u
bogdanm 66:9c8f0e3462fb 2698 #define RTC_SR_TCE_SHIFT 4
bogdanm 66:9c8f0e3462fb 2699 /* LR Bit Fields */
bogdanm 66:9c8f0e3462fb 2700 #define RTC_LR_TCL_MASK 0x8u
bogdanm 66:9c8f0e3462fb 2701 #define RTC_LR_TCL_SHIFT 3
bogdanm 66:9c8f0e3462fb 2702 #define RTC_LR_CRL_MASK 0x10u
bogdanm 66:9c8f0e3462fb 2703 #define RTC_LR_CRL_SHIFT 4
bogdanm 66:9c8f0e3462fb 2704 #define RTC_LR_SRL_MASK 0x20u
bogdanm 66:9c8f0e3462fb 2705 #define RTC_LR_SRL_SHIFT 5
bogdanm 66:9c8f0e3462fb 2706 #define RTC_LR_LRL_MASK 0x40u
bogdanm 66:9c8f0e3462fb 2707 #define RTC_LR_LRL_SHIFT 6
bogdanm 66:9c8f0e3462fb 2708 /* IER Bit Fields */
bogdanm 66:9c8f0e3462fb 2709 #define RTC_IER_TIIE_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2710 #define RTC_IER_TIIE_SHIFT 0
bogdanm 66:9c8f0e3462fb 2711 #define RTC_IER_TOIE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 2712 #define RTC_IER_TOIE_SHIFT 1
bogdanm 66:9c8f0e3462fb 2713 #define RTC_IER_TAIE_MASK 0x4u
bogdanm 66:9c8f0e3462fb 2714 #define RTC_IER_TAIE_SHIFT 2
bogdanm 66:9c8f0e3462fb 2715 #define RTC_IER_TSIE_MASK 0x10u
bogdanm 66:9c8f0e3462fb 2716 #define RTC_IER_TSIE_SHIFT 4
bogdanm 66:9c8f0e3462fb 2717 #define RTC_IER_WPON_MASK 0x80u
bogdanm 66:9c8f0e3462fb 2718 #define RTC_IER_WPON_SHIFT 7
bogdanm 66:9c8f0e3462fb 2719
bogdanm 66:9c8f0e3462fb 2720 /**
bogdanm 66:9c8f0e3462fb 2721 * @}
bogdanm 66:9c8f0e3462fb 2722 */ /* end of group RTC_Register_Masks */
bogdanm 66:9c8f0e3462fb 2723
bogdanm 66:9c8f0e3462fb 2724
bogdanm 66:9c8f0e3462fb 2725 /* RTC - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 2726 /** Peripheral RTC base address */
bogdanm 66:9c8f0e3462fb 2727 #define RTC_BASE (0x4003D000u)
bogdanm 66:9c8f0e3462fb 2728 /** Peripheral RTC base pointer */
bogdanm 66:9c8f0e3462fb 2729 #define RTC ((RTC_Type *)RTC_BASE)
bogdanm 66:9c8f0e3462fb 2730 /** Array initializer of RTC peripheral base pointers */
bogdanm 66:9c8f0e3462fb 2731 #define RTC_BASES { RTC }
bogdanm 66:9c8f0e3462fb 2732
bogdanm 66:9c8f0e3462fb 2733 /**
bogdanm 66:9c8f0e3462fb 2734 * @}
bogdanm 66:9c8f0e3462fb 2735 */ /* end of group RTC_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 2736
bogdanm 66:9c8f0e3462fb 2737
bogdanm 66:9c8f0e3462fb 2738 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2739 -- SIM Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2740 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2741
bogdanm 66:9c8f0e3462fb 2742 /**
bogdanm 66:9c8f0e3462fb 2743 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2744 * @{
bogdanm 66:9c8f0e3462fb 2745 */
bogdanm 66:9c8f0e3462fb 2746
bogdanm 66:9c8f0e3462fb 2747 /** SIM - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 2748 typedef struct {
bogdanm 66:9c8f0e3462fb 2749 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 2750 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 2751 uint8_t RESERVED_0[4092];
bogdanm 66:9c8f0e3462fb 2752 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
bogdanm 66:9c8f0e3462fb 2753 uint8_t RESERVED_1[4];
bogdanm 66:9c8f0e3462fb 2754 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
bogdanm 66:9c8f0e3462fb 2755 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
bogdanm 66:9c8f0e3462fb 2756 uint8_t RESERVED_2[4];
bogdanm 66:9c8f0e3462fb 2757 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
bogdanm 66:9c8f0e3462fb 2758 uint8_t RESERVED_3[8];
bogdanm 66:9c8f0e3462fb 2759 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
bogdanm 66:9c8f0e3462fb 2760 uint8_t RESERVED_4[12];
bogdanm 66:9c8f0e3462fb 2761 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
bogdanm 66:9c8f0e3462fb 2762 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
bogdanm 66:9c8f0e3462fb 2763 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
bogdanm 66:9c8f0e3462fb 2764 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
bogdanm 66:9c8f0e3462fb 2765 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
bogdanm 66:9c8f0e3462fb 2766 uint8_t RESERVED_5[4];
bogdanm 66:9c8f0e3462fb 2767 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
bogdanm 66:9c8f0e3462fb 2768 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
bogdanm 66:9c8f0e3462fb 2769 uint8_t RESERVED_6[4];
bogdanm 66:9c8f0e3462fb 2770 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
bogdanm 66:9c8f0e3462fb 2771 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
bogdanm 66:9c8f0e3462fb 2772 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
bogdanm 66:9c8f0e3462fb 2773 uint8_t RESERVED_7[156];
bogdanm 66:9c8f0e3462fb 2774 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
bogdanm 66:9c8f0e3462fb 2775 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
bogdanm 66:9c8f0e3462fb 2776 } SIM_Type;
bogdanm 66:9c8f0e3462fb 2777
bogdanm 66:9c8f0e3462fb 2778 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2779 -- SIM Register Masks
bogdanm 66:9c8f0e3462fb 2780 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2781
bogdanm 66:9c8f0e3462fb 2782 /**
bogdanm 66:9c8f0e3462fb 2783 * @addtogroup SIM_Register_Masks SIM Register Masks
bogdanm 66:9c8f0e3462fb 2784 * @{
bogdanm 66:9c8f0e3462fb 2785 */
bogdanm 66:9c8f0e3462fb 2786
bogdanm 66:9c8f0e3462fb 2787 /* SOPT1 Bit Fields */
bogdanm 66:9c8f0e3462fb 2788 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
bogdanm 66:9c8f0e3462fb 2789 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
bogdanm 66:9c8f0e3462fb 2790 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
bogdanm 66:9c8f0e3462fb 2791 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
bogdanm 66:9c8f0e3462fb 2792 #define SIM_SOPT1_USBVSTBY_SHIFT 29
bogdanm 66:9c8f0e3462fb 2793 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
bogdanm 66:9c8f0e3462fb 2794 #define SIM_SOPT1_USBSSTBY_SHIFT 30
bogdanm 66:9c8f0e3462fb 2795 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
bogdanm 66:9c8f0e3462fb 2796 #define SIM_SOPT1_USBREGEN_SHIFT 31
bogdanm 66:9c8f0e3462fb 2797 /* SOPT1CFG Bit Fields */
bogdanm 66:9c8f0e3462fb 2798 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
bogdanm 66:9c8f0e3462fb 2799 #define SIM_SOPT1CFG_URWE_SHIFT 24
bogdanm 66:9c8f0e3462fb 2800 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
bogdanm 66:9c8f0e3462fb 2801 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
bogdanm 66:9c8f0e3462fb 2802 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
bogdanm 66:9c8f0e3462fb 2803 #define SIM_SOPT1CFG_USSWE_SHIFT 26
bogdanm 66:9c8f0e3462fb 2804 /* SOPT2 Bit Fields */
bogdanm 66:9c8f0e3462fb 2805 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
bogdanm 66:9c8f0e3462fb 2806 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
bogdanm 66:9c8f0e3462fb 2807 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
bogdanm 66:9c8f0e3462fb 2808 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
bogdanm 66:9c8f0e3462fb 2809 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
bogdanm 66:9c8f0e3462fb 2810 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
bogdanm 66:9c8f0e3462fb 2811 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
bogdanm 66:9c8f0e3462fb 2812 #define SIM_SOPT2_USBSRC_MASK 0x40000u
bogdanm 66:9c8f0e3462fb 2813 #define SIM_SOPT2_USBSRC_SHIFT 18
bogdanm 66:9c8f0e3462fb 2814 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
bogdanm 66:9c8f0e3462fb 2815 #define SIM_SOPT2_TPMSRC_SHIFT 24
bogdanm 66:9c8f0e3462fb 2816 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
bogdanm 66:9c8f0e3462fb 2817 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
bogdanm 66:9c8f0e3462fb 2818 #define SIM_SOPT2_UART0SRC_SHIFT 26
bogdanm 66:9c8f0e3462fb 2819 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
bogdanm 66:9c8f0e3462fb 2820 /* SOPT4 Bit Fields */
bogdanm 66:9c8f0e3462fb 2821 #define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
bogdanm 66:9c8f0e3462fb 2822 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
bogdanm 66:9c8f0e3462fb 2823 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
bogdanm 66:9c8f0e3462fb 2824 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
bogdanm 66:9c8f0e3462fb 2825 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
bogdanm 66:9c8f0e3462fb 2826 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
bogdanm 66:9c8f0e3462fb 2827 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
bogdanm 66:9c8f0e3462fb 2828 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
bogdanm 66:9c8f0e3462fb 2829 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
bogdanm 66:9c8f0e3462fb 2830 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
bogdanm 66:9c8f0e3462fb 2831 /* SOPT5 Bit Fields */
bogdanm 66:9c8f0e3462fb 2832 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
bogdanm 66:9c8f0e3462fb 2833 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
bogdanm 66:9c8f0e3462fb 2834 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
bogdanm 66:9c8f0e3462fb 2835 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
bogdanm 66:9c8f0e3462fb 2836 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
bogdanm 66:9c8f0e3462fb 2837 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
bogdanm 66:9c8f0e3462fb 2838 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
bogdanm 66:9c8f0e3462fb 2839 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
bogdanm 66:9c8f0e3462fb 2840 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u
bogdanm 66:9c8f0e3462fb 2841 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
bogdanm 66:9c8f0e3462fb 2842 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
bogdanm 66:9c8f0e3462fb 2843 #define SIM_SOPT5_UART0ODE_SHIFT 16
bogdanm 66:9c8f0e3462fb 2844 #define SIM_SOPT5_UART1ODE_MASK 0x20000u
bogdanm 66:9c8f0e3462fb 2845 #define SIM_SOPT5_UART1ODE_SHIFT 17
bogdanm 66:9c8f0e3462fb 2846 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
bogdanm 66:9c8f0e3462fb 2847 #define SIM_SOPT5_UART2ODE_SHIFT 18
bogdanm 66:9c8f0e3462fb 2848 /* SOPT7 Bit Fields */
bogdanm 66:9c8f0e3462fb 2849 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
bogdanm 66:9c8f0e3462fb 2850 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
bogdanm 66:9c8f0e3462fb 2851 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
bogdanm 66:9c8f0e3462fb 2852 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
bogdanm 66:9c8f0e3462fb 2853 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
bogdanm 66:9c8f0e3462fb 2854 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 2855 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
bogdanm 66:9c8f0e3462fb 2856 /* SDID Bit Fields */
bogdanm 66:9c8f0e3462fb 2857 #define SIM_SDID_PINID_MASK 0xFu
bogdanm 66:9c8f0e3462fb 2858 #define SIM_SDID_PINID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2859 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
bogdanm 66:9c8f0e3462fb 2860 #define SIM_SDID_DIEID_MASK 0xF80u
bogdanm 66:9c8f0e3462fb 2861 #define SIM_SDID_DIEID_SHIFT 7
bogdanm 66:9c8f0e3462fb 2862 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
bogdanm 66:9c8f0e3462fb 2863 #define SIM_SDID_REVID_MASK 0xF000u
bogdanm 66:9c8f0e3462fb 2864 #define SIM_SDID_REVID_SHIFT 12
bogdanm 66:9c8f0e3462fb 2865 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
bogdanm 66:9c8f0e3462fb 2866 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
bogdanm 66:9c8f0e3462fb 2867 #define SIM_SDID_SRAMSIZE_SHIFT 16
bogdanm 66:9c8f0e3462fb 2868 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
bogdanm 66:9c8f0e3462fb 2869 #define SIM_SDID_SERIESID_MASK 0xF00000u
bogdanm 66:9c8f0e3462fb 2870 #define SIM_SDID_SERIESID_SHIFT 20
bogdanm 66:9c8f0e3462fb 2871 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
bogdanm 66:9c8f0e3462fb 2872 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
bogdanm 66:9c8f0e3462fb 2873 #define SIM_SDID_SUBFAMID_SHIFT 24
bogdanm 66:9c8f0e3462fb 2874 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
bogdanm 66:9c8f0e3462fb 2875 #define SIM_SDID_FAMID_MASK 0xF0000000u
bogdanm 66:9c8f0e3462fb 2876 #define SIM_SDID_FAMID_SHIFT 28
bogdanm 66:9c8f0e3462fb 2877 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
bogdanm 66:9c8f0e3462fb 2878 /* SCGC4 Bit Fields */
bogdanm 66:9c8f0e3462fb 2879 #define SIM_SCGC4_I2C0_MASK 0x40u
bogdanm 66:9c8f0e3462fb 2880 #define SIM_SCGC4_I2C0_SHIFT 6
bogdanm 66:9c8f0e3462fb 2881 #define SIM_SCGC4_I2C1_MASK 0x80u
bogdanm 66:9c8f0e3462fb 2882 #define SIM_SCGC4_I2C1_SHIFT 7
bogdanm 66:9c8f0e3462fb 2883 #define SIM_SCGC4_UART0_MASK 0x400u
bogdanm 66:9c8f0e3462fb 2884 #define SIM_SCGC4_UART0_SHIFT 10
bogdanm 66:9c8f0e3462fb 2885 #define SIM_SCGC4_UART1_MASK 0x800u
bogdanm 66:9c8f0e3462fb 2886 #define SIM_SCGC4_UART1_SHIFT 11
bogdanm 66:9c8f0e3462fb 2887 #define SIM_SCGC4_UART2_MASK 0x1000u
bogdanm 66:9c8f0e3462fb 2888 #define SIM_SCGC4_UART2_SHIFT 12
bogdanm 66:9c8f0e3462fb 2889 #define SIM_SCGC4_USBOTG_MASK 0x40000u
bogdanm 66:9c8f0e3462fb 2890 #define SIM_SCGC4_USBOTG_SHIFT 18
bogdanm 66:9c8f0e3462fb 2891 #define SIM_SCGC4_CMP_MASK 0x80000u
bogdanm 66:9c8f0e3462fb 2892 #define SIM_SCGC4_CMP_SHIFT 19
bogdanm 66:9c8f0e3462fb 2893 #define SIM_SCGC4_SPI0_MASK 0x400000u
bogdanm 66:9c8f0e3462fb 2894 #define SIM_SCGC4_SPI0_SHIFT 22
bogdanm 66:9c8f0e3462fb 2895 #define SIM_SCGC4_SPI1_MASK 0x800000u
bogdanm 66:9c8f0e3462fb 2896 #define SIM_SCGC4_SPI1_SHIFT 23
bogdanm 66:9c8f0e3462fb 2897 /* SCGC5 Bit Fields */
bogdanm 66:9c8f0e3462fb 2898 #define SIM_SCGC5_LPTMR_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2899 #define SIM_SCGC5_LPTMR_SHIFT 0
bogdanm 66:9c8f0e3462fb 2900 #define SIM_SCGC5_TSI_MASK 0x20u
bogdanm 66:9c8f0e3462fb 2901 #define SIM_SCGC5_TSI_SHIFT 5
bogdanm 66:9c8f0e3462fb 2902 #define SIM_SCGC5_PORTA_MASK 0x200u
bogdanm 66:9c8f0e3462fb 2903 #define SIM_SCGC5_PORTA_SHIFT 9
bogdanm 66:9c8f0e3462fb 2904 #define SIM_SCGC5_PORTB_MASK 0x400u
bogdanm 66:9c8f0e3462fb 2905 #define SIM_SCGC5_PORTB_SHIFT 10
bogdanm 66:9c8f0e3462fb 2906 #define SIM_SCGC5_PORTC_MASK 0x800u
bogdanm 66:9c8f0e3462fb 2907 #define SIM_SCGC5_PORTC_SHIFT 11
bogdanm 66:9c8f0e3462fb 2908 #define SIM_SCGC5_PORTD_MASK 0x1000u
bogdanm 66:9c8f0e3462fb 2909 #define SIM_SCGC5_PORTD_SHIFT 12
bogdanm 66:9c8f0e3462fb 2910 #define SIM_SCGC5_PORTE_MASK 0x2000u
bogdanm 66:9c8f0e3462fb 2911 #define SIM_SCGC5_PORTE_SHIFT 13
bogdanm 66:9c8f0e3462fb 2912 /* SCGC6 Bit Fields */
bogdanm 66:9c8f0e3462fb 2913 #define SIM_SCGC6_FTF_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2914 #define SIM_SCGC6_FTF_SHIFT 0
bogdanm 66:9c8f0e3462fb 2915 #define SIM_SCGC6_DMAMUX_MASK 0x2u
bogdanm 66:9c8f0e3462fb 2916 #define SIM_SCGC6_DMAMUX_SHIFT 1
bogdanm 66:9c8f0e3462fb 2917 #define SIM_SCGC6_PIT_MASK 0x800000u
bogdanm 66:9c8f0e3462fb 2918 #define SIM_SCGC6_PIT_SHIFT 23
bogdanm 66:9c8f0e3462fb 2919 #define SIM_SCGC6_TPM0_MASK 0x1000000u
bogdanm 66:9c8f0e3462fb 2920 #define SIM_SCGC6_TPM0_SHIFT 24
bogdanm 66:9c8f0e3462fb 2921 #define SIM_SCGC6_TPM1_MASK 0x2000000u
bogdanm 66:9c8f0e3462fb 2922 #define SIM_SCGC6_TPM1_SHIFT 25
bogdanm 66:9c8f0e3462fb 2923 #define SIM_SCGC6_TPM2_MASK 0x4000000u
bogdanm 66:9c8f0e3462fb 2924 #define SIM_SCGC6_TPM2_SHIFT 26
bogdanm 66:9c8f0e3462fb 2925 #define SIM_SCGC6_ADC0_MASK 0x8000000u
bogdanm 66:9c8f0e3462fb 2926 #define SIM_SCGC6_ADC0_SHIFT 27
bogdanm 66:9c8f0e3462fb 2927 #define SIM_SCGC6_RTC_MASK 0x20000000u
bogdanm 66:9c8f0e3462fb 2928 #define SIM_SCGC6_RTC_SHIFT 29
bogdanm 66:9c8f0e3462fb 2929 #define SIM_SCGC6_DAC0_MASK 0x80000000u
bogdanm 66:9c8f0e3462fb 2930 #define SIM_SCGC6_DAC0_SHIFT 31
bogdanm 66:9c8f0e3462fb 2931 /* SCGC7 Bit Fields */
bogdanm 66:9c8f0e3462fb 2932 #define SIM_SCGC7_DMA_MASK 0x100u
bogdanm 66:9c8f0e3462fb 2933 #define SIM_SCGC7_DMA_SHIFT 8
bogdanm 66:9c8f0e3462fb 2934 /* CLKDIV1 Bit Fields */
bogdanm 66:9c8f0e3462fb 2935 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
bogdanm 66:9c8f0e3462fb 2936 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
bogdanm 66:9c8f0e3462fb 2937 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
bogdanm 66:9c8f0e3462fb 2938 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
bogdanm 66:9c8f0e3462fb 2939 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
bogdanm 66:9c8f0e3462fb 2940 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
bogdanm 66:9c8f0e3462fb 2941 /* FCFG1 Bit Fields */
bogdanm 66:9c8f0e3462fb 2942 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2943 #define SIM_FCFG1_FLASHDIS_SHIFT 0
bogdanm 66:9c8f0e3462fb 2944 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 2945 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
bogdanm 66:9c8f0e3462fb 2946 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
bogdanm 66:9c8f0e3462fb 2947 #define SIM_FCFG1_PFSIZE_SHIFT 24
bogdanm 66:9c8f0e3462fb 2948 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
bogdanm 66:9c8f0e3462fb 2949 /* FCFG2 Bit Fields */
bogdanm 66:9c8f0e3462fb 2950 #define SIM_FCFG2_MAXADDR_MASK 0x7F000000u
bogdanm 66:9c8f0e3462fb 2951 #define SIM_FCFG2_MAXADDR_SHIFT 24
bogdanm 66:9c8f0e3462fb 2952 #define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
bogdanm 66:9c8f0e3462fb 2953 /* UIDMH Bit Fields */
bogdanm 66:9c8f0e3462fb 2954 #define SIM_UIDMH_UID_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 2955 #define SIM_UIDMH_UID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2956 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
bogdanm 66:9c8f0e3462fb 2957 /* UIDML Bit Fields */
bogdanm 66:9c8f0e3462fb 2958 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2959 #define SIM_UIDML_UID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2960 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
bogdanm 66:9c8f0e3462fb 2961 /* UIDL Bit Fields */
bogdanm 66:9c8f0e3462fb 2962 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
bogdanm 66:9c8f0e3462fb 2963 #define SIM_UIDL_UID_SHIFT 0
bogdanm 66:9c8f0e3462fb 2964 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
bogdanm 66:9c8f0e3462fb 2965 /* COPC Bit Fields */
bogdanm 66:9c8f0e3462fb 2966 #define SIM_COPC_COPW_MASK 0x1u
bogdanm 66:9c8f0e3462fb 2967 #define SIM_COPC_COPW_SHIFT 0
bogdanm 66:9c8f0e3462fb 2968 #define SIM_COPC_COPCLKS_MASK 0x2u
bogdanm 66:9c8f0e3462fb 2969 #define SIM_COPC_COPCLKS_SHIFT 1
bogdanm 66:9c8f0e3462fb 2970 #define SIM_COPC_COPT_MASK 0xCu
bogdanm 66:9c8f0e3462fb 2971 #define SIM_COPC_COPT_SHIFT 2
bogdanm 66:9c8f0e3462fb 2972 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
bogdanm 66:9c8f0e3462fb 2973 /* SRVCOP Bit Fields */
bogdanm 66:9c8f0e3462fb 2974 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 2975 #define SIM_SRVCOP_SRVCOP_SHIFT 0
bogdanm 66:9c8f0e3462fb 2976 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
bogdanm 66:9c8f0e3462fb 2977
bogdanm 66:9c8f0e3462fb 2978 /**
bogdanm 66:9c8f0e3462fb 2979 * @}
bogdanm 66:9c8f0e3462fb 2980 */ /* end of group SIM_Register_Masks */
bogdanm 66:9c8f0e3462fb 2981
bogdanm 66:9c8f0e3462fb 2982
bogdanm 66:9c8f0e3462fb 2983 /* SIM - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 2984 /** Peripheral SIM base address */
bogdanm 66:9c8f0e3462fb 2985 #define SIM_BASE (0x40047000u)
bogdanm 66:9c8f0e3462fb 2986 /** Peripheral SIM base pointer */
bogdanm 66:9c8f0e3462fb 2987 #define SIM ((SIM_Type *)SIM_BASE)
bogdanm 66:9c8f0e3462fb 2988 /** Array initializer of SIM peripheral base pointers */
bogdanm 66:9c8f0e3462fb 2989 #define SIM_BASES { SIM }
bogdanm 66:9c8f0e3462fb 2990
bogdanm 66:9c8f0e3462fb 2991 /**
bogdanm 66:9c8f0e3462fb 2992 * @}
bogdanm 66:9c8f0e3462fb 2993 */ /* end of group SIM_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 2994
bogdanm 66:9c8f0e3462fb 2995
bogdanm 66:9c8f0e3462fb 2996 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 2997 -- SMC Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 2998 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 2999
bogdanm 66:9c8f0e3462fb 3000 /**
bogdanm 66:9c8f0e3462fb 3001 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3002 * @{
bogdanm 66:9c8f0e3462fb 3003 */
bogdanm 66:9c8f0e3462fb 3004
bogdanm 66:9c8f0e3462fb 3005 /** SMC - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 3006 typedef struct {
bogdanm 66:9c8f0e3462fb 3007 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 3008 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
bogdanm 66:9c8f0e3462fb 3009 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
bogdanm 66:9c8f0e3462fb 3010 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
bogdanm 66:9c8f0e3462fb 3011 } SMC_Type;
bogdanm 66:9c8f0e3462fb 3012
bogdanm 66:9c8f0e3462fb 3013 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3014 -- SMC Register Masks
bogdanm 66:9c8f0e3462fb 3015 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3016
bogdanm 66:9c8f0e3462fb 3017 /**
bogdanm 66:9c8f0e3462fb 3018 * @addtogroup SMC_Register_Masks SMC Register Masks
bogdanm 66:9c8f0e3462fb 3019 * @{
bogdanm 66:9c8f0e3462fb 3020 */
bogdanm 66:9c8f0e3462fb 3021
bogdanm 66:9c8f0e3462fb 3022 /* PMPROT Bit Fields */
bogdanm 66:9c8f0e3462fb 3023 #define SMC_PMPROT_AVLLS_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3024 #define SMC_PMPROT_AVLLS_SHIFT 1
bogdanm 66:9c8f0e3462fb 3025 #define SMC_PMPROT_ALLS_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3026 #define SMC_PMPROT_ALLS_SHIFT 3
bogdanm 66:9c8f0e3462fb 3027 #define SMC_PMPROT_AVLP_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3028 #define SMC_PMPROT_AVLP_SHIFT 5
bogdanm 66:9c8f0e3462fb 3029 /* PMCTRL Bit Fields */
bogdanm 66:9c8f0e3462fb 3030 #define SMC_PMCTRL_STOPM_MASK 0x7u
bogdanm 66:9c8f0e3462fb 3031 #define SMC_PMCTRL_STOPM_SHIFT 0
bogdanm 66:9c8f0e3462fb 3032 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
bogdanm 66:9c8f0e3462fb 3033 #define SMC_PMCTRL_STOPA_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3034 #define SMC_PMCTRL_STOPA_SHIFT 3
bogdanm 66:9c8f0e3462fb 3035 #define SMC_PMCTRL_RUNM_MASK 0x60u
bogdanm 66:9c8f0e3462fb 3036 #define SMC_PMCTRL_RUNM_SHIFT 5
bogdanm 66:9c8f0e3462fb 3037 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
bogdanm 66:9c8f0e3462fb 3038 /* STOPCTRL Bit Fields */
bogdanm 66:9c8f0e3462fb 3039 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
bogdanm 66:9c8f0e3462fb 3040 #define SMC_STOPCTRL_VLLSM_SHIFT 0
bogdanm 66:9c8f0e3462fb 3041 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
bogdanm 66:9c8f0e3462fb 3042 #define SMC_STOPCTRL_PORPO_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3043 #define SMC_STOPCTRL_PORPO_SHIFT 5
bogdanm 66:9c8f0e3462fb 3044 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
bogdanm 66:9c8f0e3462fb 3045 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
bogdanm 66:9c8f0e3462fb 3046 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
bogdanm 66:9c8f0e3462fb 3047 /* PMSTAT Bit Fields */
bogdanm 66:9c8f0e3462fb 3048 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
bogdanm 66:9c8f0e3462fb 3049 #define SMC_PMSTAT_PMSTAT_SHIFT 0
bogdanm 66:9c8f0e3462fb 3050 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
bogdanm 66:9c8f0e3462fb 3051
bogdanm 66:9c8f0e3462fb 3052 /**
bogdanm 66:9c8f0e3462fb 3053 * @}
bogdanm 66:9c8f0e3462fb 3054 */ /* end of group SMC_Register_Masks */
bogdanm 66:9c8f0e3462fb 3055
bogdanm 66:9c8f0e3462fb 3056
bogdanm 66:9c8f0e3462fb 3057 /* SMC - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 3058 /** Peripheral SMC base address */
bogdanm 66:9c8f0e3462fb 3059 #define SMC_BASE (0x4007E000u)
bogdanm 66:9c8f0e3462fb 3060 /** Peripheral SMC base pointer */
bogdanm 66:9c8f0e3462fb 3061 #define SMC ((SMC_Type *)SMC_BASE)
bogdanm 66:9c8f0e3462fb 3062 /** Array initializer of SMC peripheral base pointers */
bogdanm 66:9c8f0e3462fb 3063 #define SMC_BASES { SMC }
bogdanm 66:9c8f0e3462fb 3064
bogdanm 66:9c8f0e3462fb 3065 /**
bogdanm 66:9c8f0e3462fb 3066 * @}
bogdanm 66:9c8f0e3462fb 3067 */ /* end of group SMC_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 3068
bogdanm 66:9c8f0e3462fb 3069
bogdanm 66:9c8f0e3462fb 3070 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3071 -- SPI Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3072 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3073
bogdanm 66:9c8f0e3462fb 3074 /**
bogdanm 66:9c8f0e3462fb 3075 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3076 * @{
bogdanm 66:9c8f0e3462fb 3077 */
bogdanm 66:9c8f0e3462fb 3078
bogdanm 66:9c8f0e3462fb 3079 /** SPI - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 3080 typedef struct {
bogdanm 66:9c8f0e3462fb 3081 __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 3082 __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
bogdanm 66:9c8f0e3462fb 3083 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
bogdanm 66:9c8f0e3462fb 3084 __I uint8_t S; /**< SPI status register, offset: 0x3 */
bogdanm 66:9c8f0e3462fb 3085 uint8_t RESERVED_0[1];
bogdanm 66:9c8f0e3462fb 3086 __IO uint8_t D; /**< SPI data register, offset: 0x5 */
bogdanm 66:9c8f0e3462fb 3087 uint8_t RESERVED_1[1];
bogdanm 66:9c8f0e3462fb 3088 __IO uint8_t M; /**< SPI match register, offset: 0x7 */
bogdanm 66:9c8f0e3462fb 3089 } SPI_Type;
bogdanm 66:9c8f0e3462fb 3090
bogdanm 66:9c8f0e3462fb 3091 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3092 -- SPI Register Masks
bogdanm 66:9c8f0e3462fb 3093 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3094
bogdanm 66:9c8f0e3462fb 3095 /**
bogdanm 66:9c8f0e3462fb 3096 * @addtogroup SPI_Register_Masks SPI Register Masks
bogdanm 66:9c8f0e3462fb 3097 * @{
bogdanm 66:9c8f0e3462fb 3098 */
bogdanm 66:9c8f0e3462fb 3099
bogdanm 66:9c8f0e3462fb 3100 /* C1 Bit Fields */
bogdanm 66:9c8f0e3462fb 3101 #define SPI_C1_LSBFE_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3102 #define SPI_C1_LSBFE_SHIFT 0
bogdanm 66:9c8f0e3462fb 3103 #define SPI_C1_SSOE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3104 #define SPI_C1_SSOE_SHIFT 1
bogdanm 66:9c8f0e3462fb 3105 #define SPI_C1_CPHA_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3106 #define SPI_C1_CPHA_SHIFT 2
bogdanm 66:9c8f0e3462fb 3107 #define SPI_C1_CPOL_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3108 #define SPI_C1_CPOL_SHIFT 3
bogdanm 66:9c8f0e3462fb 3109 #define SPI_C1_MSTR_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3110 #define SPI_C1_MSTR_SHIFT 4
bogdanm 66:9c8f0e3462fb 3111 #define SPI_C1_SPTIE_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3112 #define SPI_C1_SPTIE_SHIFT 5
bogdanm 66:9c8f0e3462fb 3113 #define SPI_C1_SPE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3114 #define SPI_C1_SPE_SHIFT 6
bogdanm 66:9c8f0e3462fb 3115 #define SPI_C1_SPIE_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3116 #define SPI_C1_SPIE_SHIFT 7
bogdanm 66:9c8f0e3462fb 3117 /* C2 Bit Fields */
bogdanm 66:9c8f0e3462fb 3118 #define SPI_C2_SPC0_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3119 #define SPI_C2_SPC0_SHIFT 0
bogdanm 66:9c8f0e3462fb 3120 #define SPI_C2_SPISWAI_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3121 #define SPI_C2_SPISWAI_SHIFT 1
bogdanm 66:9c8f0e3462fb 3122 #define SPI_C2_RXDMAE_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3123 #define SPI_C2_RXDMAE_SHIFT 2
bogdanm 66:9c8f0e3462fb 3124 #define SPI_C2_BIDIROE_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3125 #define SPI_C2_BIDIROE_SHIFT 3
bogdanm 66:9c8f0e3462fb 3126 #define SPI_C2_MODFEN_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3127 #define SPI_C2_MODFEN_SHIFT 4
bogdanm 66:9c8f0e3462fb 3128 #define SPI_C2_TXDMAE_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3129 #define SPI_C2_TXDMAE_SHIFT 5
bogdanm 66:9c8f0e3462fb 3130 #define SPI_C2_SPLPIE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3131 #define SPI_C2_SPLPIE_SHIFT 6
bogdanm 66:9c8f0e3462fb 3132 #define SPI_C2_SPMIE_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3133 #define SPI_C2_SPMIE_SHIFT 7
bogdanm 66:9c8f0e3462fb 3134 /* BR Bit Fields */
bogdanm 66:9c8f0e3462fb 3135 #define SPI_BR_SPR_MASK 0xFu
bogdanm 66:9c8f0e3462fb 3136 #define SPI_BR_SPR_SHIFT 0
bogdanm 66:9c8f0e3462fb 3137 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
bogdanm 66:9c8f0e3462fb 3138 #define SPI_BR_SPPR_MASK 0x70u
bogdanm 66:9c8f0e3462fb 3139 #define SPI_BR_SPPR_SHIFT 4
bogdanm 66:9c8f0e3462fb 3140 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
bogdanm 66:9c8f0e3462fb 3141 /* S Bit Fields */
bogdanm 66:9c8f0e3462fb 3142 #define SPI_S_MODF_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3143 #define SPI_S_MODF_SHIFT 4
bogdanm 66:9c8f0e3462fb 3144 #define SPI_S_SPTEF_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3145 #define SPI_S_SPTEF_SHIFT 5
bogdanm 66:9c8f0e3462fb 3146 #define SPI_S_SPMF_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3147 #define SPI_S_SPMF_SHIFT 6
bogdanm 66:9c8f0e3462fb 3148 #define SPI_S_SPRF_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3149 #define SPI_S_SPRF_SHIFT 7
bogdanm 66:9c8f0e3462fb 3150 /* D Bit Fields */
bogdanm 66:9c8f0e3462fb 3151 #define SPI_D_Bits_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 3152 #define SPI_D_Bits_SHIFT 0
bogdanm 66:9c8f0e3462fb 3153 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
bogdanm 66:9c8f0e3462fb 3154 /* M Bit Fields */
bogdanm 66:9c8f0e3462fb 3155 #define SPI_M_Bits_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 3156 #define SPI_M_Bits_SHIFT 0
bogdanm 66:9c8f0e3462fb 3157 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
bogdanm 66:9c8f0e3462fb 3158
bogdanm 66:9c8f0e3462fb 3159 /**
bogdanm 66:9c8f0e3462fb 3160 * @}
bogdanm 66:9c8f0e3462fb 3161 */ /* end of group SPI_Register_Masks */
bogdanm 66:9c8f0e3462fb 3162
bogdanm 66:9c8f0e3462fb 3163
bogdanm 66:9c8f0e3462fb 3164 /* SPI - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 3165 /** Peripheral SPI0 base address */
bogdanm 66:9c8f0e3462fb 3166 #define SPI0_BASE (0x40076000u)
bogdanm 66:9c8f0e3462fb 3167 /** Peripheral SPI0 base pointer */
bogdanm 66:9c8f0e3462fb 3168 #define SPI0 ((SPI_Type *)SPI0_BASE)
bogdanm 66:9c8f0e3462fb 3169 /** Peripheral SPI1 base address */
bogdanm 66:9c8f0e3462fb 3170 #define SPI1_BASE (0x40077000u)
bogdanm 66:9c8f0e3462fb 3171 /** Peripheral SPI1 base pointer */
bogdanm 66:9c8f0e3462fb 3172 #define SPI1 ((SPI_Type *)SPI1_BASE)
bogdanm 66:9c8f0e3462fb 3173 /** Array initializer of SPI peripheral base pointers */
bogdanm 66:9c8f0e3462fb 3174 #define SPI_BASES { SPI0, SPI1 }
bogdanm 66:9c8f0e3462fb 3175
bogdanm 66:9c8f0e3462fb 3176 /**
bogdanm 66:9c8f0e3462fb 3177 * @}
bogdanm 66:9c8f0e3462fb 3178 */ /* end of group SPI_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 3179
bogdanm 66:9c8f0e3462fb 3180
bogdanm 66:9c8f0e3462fb 3181 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3182 -- TPM Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3183 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3184
bogdanm 66:9c8f0e3462fb 3185 /**
bogdanm 66:9c8f0e3462fb 3186 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3187 * @{
bogdanm 66:9c8f0e3462fb 3188 */
bogdanm 66:9c8f0e3462fb 3189
bogdanm 66:9c8f0e3462fb 3190 /** TPM - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 3191 typedef struct {
bogdanm 66:9c8f0e3462fb 3192 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 3193 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 3194 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 3195 struct { /* offset: 0xC, array step: 0x8 */
bogdanm 66:9c8f0e3462fb 3196 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
bogdanm 66:9c8f0e3462fb 3197 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
bogdanm 66:9c8f0e3462fb 3198 } CONTROLS[6];
bogdanm 66:9c8f0e3462fb 3199 uint8_t RESERVED_0[20];
bogdanm 66:9c8f0e3462fb 3200 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
bogdanm 66:9c8f0e3462fb 3201 uint8_t RESERVED_1[48];
bogdanm 66:9c8f0e3462fb 3202 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
bogdanm 66:9c8f0e3462fb 3203 } TPM_Type;
bogdanm 66:9c8f0e3462fb 3204
bogdanm 66:9c8f0e3462fb 3205 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3206 -- TPM Register Masks
bogdanm 66:9c8f0e3462fb 3207 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3208
bogdanm 66:9c8f0e3462fb 3209 /**
bogdanm 66:9c8f0e3462fb 3210 * @addtogroup TPM_Register_Masks TPM Register Masks
bogdanm 66:9c8f0e3462fb 3211 * @{
bogdanm 66:9c8f0e3462fb 3212 */
bogdanm 66:9c8f0e3462fb 3213
bogdanm 66:9c8f0e3462fb 3214 /* SC Bit Fields */
bogdanm 66:9c8f0e3462fb 3215 #define TPM_SC_PS_MASK 0x7u
bogdanm 66:9c8f0e3462fb 3216 #define TPM_SC_PS_SHIFT 0
bogdanm 66:9c8f0e3462fb 3217 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
bogdanm 66:9c8f0e3462fb 3218 #define TPM_SC_CMOD_MASK 0x18u
bogdanm 66:9c8f0e3462fb 3219 #define TPM_SC_CMOD_SHIFT 3
bogdanm 66:9c8f0e3462fb 3220 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
bogdanm 66:9c8f0e3462fb 3221 #define TPM_SC_CPWMS_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3222 #define TPM_SC_CPWMS_SHIFT 5
bogdanm 66:9c8f0e3462fb 3223 #define TPM_SC_TOIE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3224 #define TPM_SC_TOIE_SHIFT 6
bogdanm 66:9c8f0e3462fb 3225 #define TPM_SC_TOF_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3226 #define TPM_SC_TOF_SHIFT 7
bogdanm 66:9c8f0e3462fb 3227 #define TPM_SC_DMA_MASK 0x100u
bogdanm 66:9c8f0e3462fb 3228 #define TPM_SC_DMA_SHIFT 8
bogdanm 66:9c8f0e3462fb 3229 /* CNT Bit Fields */
bogdanm 66:9c8f0e3462fb 3230 #define TPM_CNT_COUNT_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 3231 #define TPM_CNT_COUNT_SHIFT 0
bogdanm 66:9c8f0e3462fb 3232 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
bogdanm 66:9c8f0e3462fb 3233 /* MOD Bit Fields */
bogdanm 66:9c8f0e3462fb 3234 #define TPM_MOD_MOD_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 3235 #define TPM_MOD_MOD_SHIFT 0
bogdanm 66:9c8f0e3462fb 3236 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
bogdanm 66:9c8f0e3462fb 3237 /* CnSC Bit Fields */
bogdanm 66:9c8f0e3462fb 3238 #define TPM_CnSC_DMA_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3239 #define TPM_CnSC_DMA_SHIFT 0
bogdanm 66:9c8f0e3462fb 3240 #define TPM_CnSC_ELSA_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3241 #define TPM_CnSC_ELSA_SHIFT 2
bogdanm 66:9c8f0e3462fb 3242 #define TPM_CnSC_ELSB_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3243 #define TPM_CnSC_ELSB_SHIFT 3
bogdanm 66:9c8f0e3462fb 3244 #define TPM_CnSC_MSA_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3245 #define TPM_CnSC_MSA_SHIFT 4
bogdanm 66:9c8f0e3462fb 3246 #define TPM_CnSC_MSB_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3247 #define TPM_CnSC_MSB_SHIFT 5
bogdanm 66:9c8f0e3462fb 3248 #define TPM_CnSC_CHIE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3249 #define TPM_CnSC_CHIE_SHIFT 6
bogdanm 66:9c8f0e3462fb 3250 #define TPM_CnSC_CHF_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3251 #define TPM_CnSC_CHF_SHIFT 7
bogdanm 66:9c8f0e3462fb 3252 /* CnV Bit Fields */
bogdanm 66:9c8f0e3462fb 3253 #define TPM_CnV_VAL_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 3254 #define TPM_CnV_VAL_SHIFT 0
bogdanm 66:9c8f0e3462fb 3255 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
bogdanm 66:9c8f0e3462fb 3256 /* STATUS Bit Fields */
bogdanm 66:9c8f0e3462fb 3257 #define TPM_STATUS_CH0F_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3258 #define TPM_STATUS_CH0F_SHIFT 0
bogdanm 66:9c8f0e3462fb 3259 #define TPM_STATUS_CH1F_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3260 #define TPM_STATUS_CH1F_SHIFT 1
bogdanm 66:9c8f0e3462fb 3261 #define TPM_STATUS_CH2F_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3262 #define TPM_STATUS_CH2F_SHIFT 2
bogdanm 66:9c8f0e3462fb 3263 #define TPM_STATUS_CH3F_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3264 #define TPM_STATUS_CH3F_SHIFT 3
bogdanm 66:9c8f0e3462fb 3265 #define TPM_STATUS_CH4F_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3266 #define TPM_STATUS_CH4F_SHIFT 4
bogdanm 66:9c8f0e3462fb 3267 #define TPM_STATUS_CH5F_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3268 #define TPM_STATUS_CH5F_SHIFT 5
bogdanm 66:9c8f0e3462fb 3269 #define TPM_STATUS_TOF_MASK 0x100u
bogdanm 66:9c8f0e3462fb 3270 #define TPM_STATUS_TOF_SHIFT 8
bogdanm 66:9c8f0e3462fb 3271 /* CONF Bit Fields */
bogdanm 66:9c8f0e3462fb 3272 #define TPM_CONF_DOZEEN_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3273 #define TPM_CONF_DOZEEN_SHIFT 5
bogdanm 66:9c8f0e3462fb 3274 #define TPM_CONF_DBGMODE_MASK 0xC0u
bogdanm 66:9c8f0e3462fb 3275 #define TPM_CONF_DBGMODE_SHIFT 6
bogdanm 66:9c8f0e3462fb 3276 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
bogdanm 66:9c8f0e3462fb 3277 #define TPM_CONF_GTBEEN_MASK 0x200u
bogdanm 66:9c8f0e3462fb 3278 #define TPM_CONF_GTBEEN_SHIFT 9
bogdanm 66:9c8f0e3462fb 3279 #define TPM_CONF_CSOT_MASK 0x10000u
bogdanm 66:9c8f0e3462fb 3280 #define TPM_CONF_CSOT_SHIFT 16
bogdanm 66:9c8f0e3462fb 3281 #define TPM_CONF_CSOO_MASK 0x20000u
bogdanm 66:9c8f0e3462fb 3282 #define TPM_CONF_CSOO_SHIFT 17
bogdanm 66:9c8f0e3462fb 3283 #define TPM_CONF_CROT_MASK 0x40000u
bogdanm 66:9c8f0e3462fb 3284 #define TPM_CONF_CROT_SHIFT 18
bogdanm 66:9c8f0e3462fb 3285 #define TPM_CONF_TRGSEL_MASK 0xF000000u
bogdanm 66:9c8f0e3462fb 3286 #define TPM_CONF_TRGSEL_SHIFT 24
bogdanm 66:9c8f0e3462fb 3287 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
bogdanm 66:9c8f0e3462fb 3288
bogdanm 66:9c8f0e3462fb 3289 /**
bogdanm 66:9c8f0e3462fb 3290 * @}
bogdanm 66:9c8f0e3462fb 3291 */ /* end of group TPM_Register_Masks */
bogdanm 66:9c8f0e3462fb 3292
bogdanm 66:9c8f0e3462fb 3293
bogdanm 66:9c8f0e3462fb 3294 /* TPM - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 3295 /** Peripheral TPM0 base address */
bogdanm 66:9c8f0e3462fb 3296 #define TPM0_BASE (0x40038000u)
bogdanm 66:9c8f0e3462fb 3297 /** Peripheral TPM0 base pointer */
bogdanm 66:9c8f0e3462fb 3298 #define TPM0 ((TPM_Type *)TPM0_BASE)
bogdanm 66:9c8f0e3462fb 3299 /** Peripheral TPM1 base address */
bogdanm 66:9c8f0e3462fb 3300 #define TPM1_BASE (0x40039000u)
bogdanm 66:9c8f0e3462fb 3301 /** Peripheral TPM1 base pointer */
bogdanm 66:9c8f0e3462fb 3302 #define TPM1 ((TPM_Type *)TPM1_BASE)
bogdanm 66:9c8f0e3462fb 3303 /** Peripheral TPM2 base address */
bogdanm 66:9c8f0e3462fb 3304 #define TPM2_BASE (0x4003A000u)
bogdanm 66:9c8f0e3462fb 3305 /** Peripheral TPM2 base pointer */
bogdanm 66:9c8f0e3462fb 3306 #define TPM2 ((TPM_Type *)TPM2_BASE)
bogdanm 66:9c8f0e3462fb 3307 /** Array initializer of TPM peripheral base pointers */
bogdanm 66:9c8f0e3462fb 3308 #define TPM_BASES { TPM0, TPM1, TPM2 }
bogdanm 66:9c8f0e3462fb 3309
bogdanm 66:9c8f0e3462fb 3310 /**
bogdanm 66:9c8f0e3462fb 3311 * @}
bogdanm 66:9c8f0e3462fb 3312 */ /* end of group TPM_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 3313
bogdanm 66:9c8f0e3462fb 3314
bogdanm 66:9c8f0e3462fb 3315 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3316 -- TSI Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3317 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3318
bogdanm 66:9c8f0e3462fb 3319 /**
bogdanm 66:9c8f0e3462fb 3320 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3321 * @{
bogdanm 66:9c8f0e3462fb 3322 */
bogdanm 66:9c8f0e3462fb 3323
bogdanm 66:9c8f0e3462fb 3324 /** TSI - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 3325 typedef struct {
bogdanm 66:9c8f0e3462fb 3326 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 3327 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 3328 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 3329 } TSI_Type;
bogdanm 66:9c8f0e3462fb 3330
bogdanm 66:9c8f0e3462fb 3331 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3332 -- TSI Register Masks
bogdanm 66:9c8f0e3462fb 3333 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3334
bogdanm 66:9c8f0e3462fb 3335 /**
bogdanm 66:9c8f0e3462fb 3336 * @addtogroup TSI_Register_Masks TSI Register Masks
bogdanm 66:9c8f0e3462fb 3337 * @{
bogdanm 66:9c8f0e3462fb 3338 */
bogdanm 66:9c8f0e3462fb 3339
bogdanm 66:9c8f0e3462fb 3340 /* GENCS Bit Fields */
bogdanm 66:9c8f0e3462fb 3341 #define TSI_GENCS_CURSW_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3342 #define TSI_GENCS_CURSW_SHIFT 1
bogdanm 66:9c8f0e3462fb 3343 #define TSI_GENCS_EOSF_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3344 #define TSI_GENCS_EOSF_SHIFT 2
bogdanm 66:9c8f0e3462fb 3345 #define TSI_GENCS_SCNIP_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3346 #define TSI_GENCS_SCNIP_SHIFT 3
bogdanm 66:9c8f0e3462fb 3347 #define TSI_GENCS_STM_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3348 #define TSI_GENCS_STM_SHIFT 4
bogdanm 66:9c8f0e3462fb 3349 #define TSI_GENCS_STPE_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3350 #define TSI_GENCS_STPE_SHIFT 5
bogdanm 66:9c8f0e3462fb 3351 #define TSI_GENCS_TSIIEN_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3352 #define TSI_GENCS_TSIIEN_SHIFT 6
bogdanm 66:9c8f0e3462fb 3353 #define TSI_GENCS_TSIEN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3354 #define TSI_GENCS_TSIEN_SHIFT 7
bogdanm 66:9c8f0e3462fb 3355 #define TSI_GENCS_NSCN_MASK 0x1F00u
bogdanm 66:9c8f0e3462fb 3356 #define TSI_GENCS_NSCN_SHIFT 8
bogdanm 66:9c8f0e3462fb 3357 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
bogdanm 66:9c8f0e3462fb 3358 #define TSI_GENCS_PS_MASK 0xE000u
bogdanm 66:9c8f0e3462fb 3359 #define TSI_GENCS_PS_SHIFT 13
bogdanm 66:9c8f0e3462fb 3360 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
bogdanm 66:9c8f0e3462fb 3361 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
bogdanm 66:9c8f0e3462fb 3362 #define TSI_GENCS_EXTCHRG_SHIFT 16
bogdanm 66:9c8f0e3462fb 3363 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
bogdanm 66:9c8f0e3462fb 3364 #define TSI_GENCS_DVOLT_MASK 0x180000u
bogdanm 66:9c8f0e3462fb 3365 #define TSI_GENCS_DVOLT_SHIFT 19
bogdanm 66:9c8f0e3462fb 3366 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
bogdanm 66:9c8f0e3462fb 3367 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
bogdanm 66:9c8f0e3462fb 3368 #define TSI_GENCS_REFCHRG_SHIFT 21
bogdanm 66:9c8f0e3462fb 3369 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
bogdanm 66:9c8f0e3462fb 3370 #define TSI_GENCS_MODE_MASK 0xF000000u
bogdanm 66:9c8f0e3462fb 3371 #define TSI_GENCS_MODE_SHIFT 24
bogdanm 66:9c8f0e3462fb 3372 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
bogdanm 66:9c8f0e3462fb 3373 #define TSI_GENCS_ESOR_MASK 0x10000000u
bogdanm 66:9c8f0e3462fb 3374 #define TSI_GENCS_ESOR_SHIFT 28
bogdanm 66:9c8f0e3462fb 3375 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
bogdanm 66:9c8f0e3462fb 3376 #define TSI_GENCS_OUTRGF_SHIFT 31
bogdanm 66:9c8f0e3462fb 3377 /* DATA Bit Fields */
bogdanm 66:9c8f0e3462fb 3378 #define TSI_DATA_TSICNT_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 3379 #define TSI_DATA_TSICNT_SHIFT 0
bogdanm 66:9c8f0e3462fb 3380 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
bogdanm 66:9c8f0e3462fb 3381 #define TSI_DATA_SWTS_MASK 0x400000u
bogdanm 66:9c8f0e3462fb 3382 #define TSI_DATA_SWTS_SHIFT 22
bogdanm 66:9c8f0e3462fb 3383 #define TSI_DATA_DMAEN_MASK 0x800000u
bogdanm 66:9c8f0e3462fb 3384 #define TSI_DATA_DMAEN_SHIFT 23
bogdanm 66:9c8f0e3462fb 3385 #define TSI_DATA_TSICH_MASK 0xF0000000u
bogdanm 66:9c8f0e3462fb 3386 #define TSI_DATA_TSICH_SHIFT 28
bogdanm 66:9c8f0e3462fb 3387 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
bogdanm 66:9c8f0e3462fb 3388 /* TSHD Bit Fields */
bogdanm 66:9c8f0e3462fb 3389 #define TSI_TSHD_THRESL_MASK 0xFFFFu
bogdanm 66:9c8f0e3462fb 3390 #define TSI_TSHD_THRESL_SHIFT 0
bogdanm 66:9c8f0e3462fb 3391 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
bogdanm 66:9c8f0e3462fb 3392 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
bogdanm 66:9c8f0e3462fb 3393 #define TSI_TSHD_THRESH_SHIFT 16
bogdanm 66:9c8f0e3462fb 3394 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
bogdanm 66:9c8f0e3462fb 3395
bogdanm 66:9c8f0e3462fb 3396 /**
bogdanm 66:9c8f0e3462fb 3397 * @}
bogdanm 66:9c8f0e3462fb 3398 */ /* end of group TSI_Register_Masks */
bogdanm 66:9c8f0e3462fb 3399
bogdanm 66:9c8f0e3462fb 3400
bogdanm 66:9c8f0e3462fb 3401 /* TSI - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 3402 /** Peripheral TSI0 base address */
bogdanm 66:9c8f0e3462fb 3403 #define TSI0_BASE (0x40045000u)
bogdanm 66:9c8f0e3462fb 3404 /** Peripheral TSI0 base pointer */
bogdanm 66:9c8f0e3462fb 3405 #define TSI0 ((TSI_Type *)TSI0_BASE)
bogdanm 66:9c8f0e3462fb 3406 /** Array initializer of TSI peripheral base pointers */
bogdanm 66:9c8f0e3462fb 3407 #define TSI_BASES { TSI0 }
bogdanm 66:9c8f0e3462fb 3408
bogdanm 66:9c8f0e3462fb 3409 /**
bogdanm 66:9c8f0e3462fb 3410 * @}
bogdanm 66:9c8f0e3462fb 3411 */ /* end of group TSI_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 3412
bogdanm 66:9c8f0e3462fb 3413
bogdanm 66:9c8f0e3462fb 3414 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3415 -- UART Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3416 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3417
bogdanm 66:9c8f0e3462fb 3418 /**
bogdanm 66:9c8f0e3462fb 3419 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3420 * @{
bogdanm 66:9c8f0e3462fb 3421 */
bogdanm 66:9c8f0e3462fb 3422
bogdanm 66:9c8f0e3462fb 3423 /** UART - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 3424 typedef struct {
bogdanm 66:9c8f0e3462fb 3425 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 3426 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
bogdanm 66:9c8f0e3462fb 3427 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
bogdanm 66:9c8f0e3462fb 3428 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
bogdanm 66:9c8f0e3462fb 3429 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 3430 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
bogdanm 66:9c8f0e3462fb 3431 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
bogdanm 66:9c8f0e3462fb 3432 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
bogdanm 66:9c8f0e3462fb 3433 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 3434 } UART_Type;
bogdanm 66:9c8f0e3462fb 3435
bogdanm 66:9c8f0e3462fb 3436 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3437 -- UART Register Masks
bogdanm 66:9c8f0e3462fb 3438 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3439
bogdanm 66:9c8f0e3462fb 3440 /**
bogdanm 66:9c8f0e3462fb 3441 * @addtogroup UART_Register_Masks UART Register Masks
bogdanm 66:9c8f0e3462fb 3442 * @{
bogdanm 66:9c8f0e3462fb 3443 */
bogdanm 66:9c8f0e3462fb 3444
bogdanm 66:9c8f0e3462fb 3445 /* BDH Bit Fields */
bogdanm 66:9c8f0e3462fb 3446 #define UART_BDH_SBR_MASK 0x1Fu
bogdanm 66:9c8f0e3462fb 3447 #define UART_BDH_SBR_SHIFT 0
bogdanm 66:9c8f0e3462fb 3448 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
bogdanm 66:9c8f0e3462fb 3449 #define UART_BDH_SBNS_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3450 #define UART_BDH_SBNS_SHIFT 5
bogdanm 66:9c8f0e3462fb 3451 #define UART_BDH_RXEDGIE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3452 #define UART_BDH_RXEDGIE_SHIFT 6
bogdanm 66:9c8f0e3462fb 3453 #define UART_BDH_LBKDIE_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3454 #define UART_BDH_LBKDIE_SHIFT 7
bogdanm 66:9c8f0e3462fb 3455 /* BDL Bit Fields */
bogdanm 66:9c8f0e3462fb 3456 #define UART_BDL_SBR_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 3457 #define UART_BDL_SBR_SHIFT 0
bogdanm 66:9c8f0e3462fb 3458 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
bogdanm 66:9c8f0e3462fb 3459 /* C1 Bit Fields */
bogdanm 66:9c8f0e3462fb 3460 #define UART_C1_PT_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3461 #define UART_C1_PT_SHIFT 0
bogdanm 66:9c8f0e3462fb 3462 #define UART_C1_PE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3463 #define UART_C1_PE_SHIFT 1
bogdanm 66:9c8f0e3462fb 3464 #define UART_C1_ILT_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3465 #define UART_C1_ILT_SHIFT 2
bogdanm 66:9c8f0e3462fb 3466 #define UART_C1_WAKE_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3467 #define UART_C1_WAKE_SHIFT 3
bogdanm 66:9c8f0e3462fb 3468 #define UART_C1_M_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3469 #define UART_C1_M_SHIFT 4
bogdanm 66:9c8f0e3462fb 3470 #define UART_C1_RSRC_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3471 #define UART_C1_RSRC_SHIFT 5
bogdanm 66:9c8f0e3462fb 3472 #define UART_C1_UARTSWAI_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3473 #define UART_C1_UARTSWAI_SHIFT 6
bogdanm 66:9c8f0e3462fb 3474 #define UART_C1_LOOPS_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3475 #define UART_C1_LOOPS_SHIFT 7
bogdanm 66:9c8f0e3462fb 3476 /* C2 Bit Fields */
bogdanm 66:9c8f0e3462fb 3477 #define UART_C2_SBK_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3478 #define UART_C2_SBK_SHIFT 0
bogdanm 66:9c8f0e3462fb 3479 #define UART_C2_RWU_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3480 #define UART_C2_RWU_SHIFT 1
bogdanm 66:9c8f0e3462fb 3481 #define UART_C2_RE_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3482 #define UART_C2_RE_SHIFT 2
bogdanm 66:9c8f0e3462fb 3483 #define UART_C2_TE_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3484 #define UART_C2_TE_SHIFT 3
bogdanm 66:9c8f0e3462fb 3485 #define UART_C2_ILIE_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3486 #define UART_C2_ILIE_SHIFT 4
bogdanm 66:9c8f0e3462fb 3487 #define UART_C2_RIE_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3488 #define UART_C2_RIE_SHIFT 5
bogdanm 66:9c8f0e3462fb 3489 #define UART_C2_TCIE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3490 #define UART_C2_TCIE_SHIFT 6
bogdanm 66:9c8f0e3462fb 3491 #define UART_C2_TIE_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3492 #define UART_C2_TIE_SHIFT 7
bogdanm 66:9c8f0e3462fb 3493 /* S1 Bit Fields */
bogdanm 66:9c8f0e3462fb 3494 #define UART_S1_PF_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3495 #define UART_S1_PF_SHIFT 0
bogdanm 66:9c8f0e3462fb 3496 #define UART_S1_FE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3497 #define UART_S1_FE_SHIFT 1
bogdanm 66:9c8f0e3462fb 3498 #define UART_S1_NF_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3499 #define UART_S1_NF_SHIFT 2
bogdanm 66:9c8f0e3462fb 3500 #define UART_S1_OR_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3501 #define UART_S1_OR_SHIFT 3
bogdanm 66:9c8f0e3462fb 3502 #define UART_S1_IDLE_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3503 #define UART_S1_IDLE_SHIFT 4
bogdanm 66:9c8f0e3462fb 3504 #define UART_S1_RDRF_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3505 #define UART_S1_RDRF_SHIFT 5
bogdanm 66:9c8f0e3462fb 3506 #define UART_S1_TC_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3507 #define UART_S1_TC_SHIFT 6
bogdanm 66:9c8f0e3462fb 3508 #define UART_S1_TDRE_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3509 #define UART_S1_TDRE_SHIFT 7
bogdanm 66:9c8f0e3462fb 3510 /* S2 Bit Fields */
bogdanm 66:9c8f0e3462fb 3511 #define UART_S2_RAF_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3512 #define UART_S2_RAF_SHIFT 0
bogdanm 66:9c8f0e3462fb 3513 #define UART_S2_LBKDE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3514 #define UART_S2_LBKDE_SHIFT 1
bogdanm 66:9c8f0e3462fb 3515 #define UART_S2_BRK13_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3516 #define UART_S2_BRK13_SHIFT 2
bogdanm 66:9c8f0e3462fb 3517 #define UART_S2_RWUID_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3518 #define UART_S2_RWUID_SHIFT 3
bogdanm 66:9c8f0e3462fb 3519 #define UART_S2_RXINV_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3520 #define UART_S2_RXINV_SHIFT 4
bogdanm 66:9c8f0e3462fb 3521 #define UART_S2_RXEDGIF_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3522 #define UART_S2_RXEDGIF_SHIFT 6
bogdanm 66:9c8f0e3462fb 3523 #define UART_S2_LBKDIF_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3524 #define UART_S2_LBKDIF_SHIFT 7
bogdanm 66:9c8f0e3462fb 3525 /* C3 Bit Fields */
bogdanm 66:9c8f0e3462fb 3526 #define UART_C3_PEIE_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3527 #define UART_C3_PEIE_SHIFT 0
bogdanm 66:9c8f0e3462fb 3528 #define UART_C3_FEIE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3529 #define UART_C3_FEIE_SHIFT 1
bogdanm 66:9c8f0e3462fb 3530 #define UART_C3_NEIE_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3531 #define UART_C3_NEIE_SHIFT 2
bogdanm 66:9c8f0e3462fb 3532 #define UART_C3_ORIE_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3533 #define UART_C3_ORIE_SHIFT 3
bogdanm 66:9c8f0e3462fb 3534 #define UART_C3_TXINV_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3535 #define UART_C3_TXINV_SHIFT 4
bogdanm 66:9c8f0e3462fb 3536 #define UART_C3_TXDIR_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3537 #define UART_C3_TXDIR_SHIFT 5
bogdanm 66:9c8f0e3462fb 3538 #define UART_C3_T8_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3539 #define UART_C3_T8_SHIFT 6
bogdanm 66:9c8f0e3462fb 3540 #define UART_C3_R8_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3541 #define UART_C3_R8_SHIFT 7
bogdanm 66:9c8f0e3462fb 3542 /* D Bit Fields */
bogdanm 66:9c8f0e3462fb 3543 #define UART_D_R0T0_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3544 #define UART_D_R0T0_SHIFT 0
bogdanm 66:9c8f0e3462fb 3545 #define UART_D_R1T1_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3546 #define UART_D_R1T1_SHIFT 1
bogdanm 66:9c8f0e3462fb 3547 #define UART_D_R2T2_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3548 #define UART_D_R2T2_SHIFT 2
bogdanm 66:9c8f0e3462fb 3549 #define UART_D_R3T3_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3550 #define UART_D_R3T3_SHIFT 3
bogdanm 66:9c8f0e3462fb 3551 #define UART_D_R4T4_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3552 #define UART_D_R4T4_SHIFT 4
bogdanm 66:9c8f0e3462fb 3553 #define UART_D_R5T5_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3554 #define UART_D_R5T5_SHIFT 5
bogdanm 66:9c8f0e3462fb 3555 #define UART_D_R6T6_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3556 #define UART_D_R6T6_SHIFT 6
bogdanm 66:9c8f0e3462fb 3557 #define UART_D_R7T7_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3558 #define UART_D_R7T7_SHIFT 7
bogdanm 66:9c8f0e3462fb 3559 /* C4 Bit Fields */
bogdanm 66:9c8f0e3462fb 3560 #define UART_C4_LBKDDMAS_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3561 #define UART_C4_LBKDDMAS_SHIFT 3
bogdanm 66:9c8f0e3462fb 3562 #define UART_C4_ILDMAS_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3563 #define UART_C4_ILDMAS_SHIFT 4
bogdanm 66:9c8f0e3462fb 3564 #define UART_C4_RDMAS_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3565 #define UART_C4_RDMAS_SHIFT 5
bogdanm 66:9c8f0e3462fb 3566 #define UART_C4_TCDMAS_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3567 #define UART_C4_TCDMAS_SHIFT 6
bogdanm 66:9c8f0e3462fb 3568 #define UART_C4_TDMAS_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3569 #define UART_C4_TDMAS_SHIFT 7
bogdanm 66:9c8f0e3462fb 3570
bogdanm 66:9c8f0e3462fb 3571 /**
bogdanm 66:9c8f0e3462fb 3572 * @}
bogdanm 66:9c8f0e3462fb 3573 */ /* end of group UART_Register_Masks */
bogdanm 66:9c8f0e3462fb 3574
bogdanm 66:9c8f0e3462fb 3575
bogdanm 66:9c8f0e3462fb 3576 /* UART - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 3577 /** Peripheral UART1 base address */
bogdanm 66:9c8f0e3462fb 3578 #define UART1_BASE (0x4006B000u)
bogdanm 66:9c8f0e3462fb 3579 /** Peripheral UART1 base pointer */
bogdanm 66:9c8f0e3462fb 3580 #define UART1 ((UART_Type *)UART1_BASE)
bogdanm 66:9c8f0e3462fb 3581 /** Peripheral UART2 base address */
bogdanm 66:9c8f0e3462fb 3582 #define UART2_BASE (0x4006C000u)
bogdanm 66:9c8f0e3462fb 3583 /** Peripheral UART2 base pointer */
bogdanm 66:9c8f0e3462fb 3584 #define UART2 ((UART_Type *)UART2_BASE)
bogdanm 66:9c8f0e3462fb 3585 /** Array initializer of UART peripheral base pointers */
bogdanm 66:9c8f0e3462fb 3586 #define UART_BASES { UART1, UART2 }
bogdanm 66:9c8f0e3462fb 3587
bogdanm 66:9c8f0e3462fb 3588 /**
bogdanm 66:9c8f0e3462fb 3589 * @}
bogdanm 66:9c8f0e3462fb 3590 */ /* end of group UART_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 3591
bogdanm 66:9c8f0e3462fb 3592
bogdanm 66:9c8f0e3462fb 3593 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3594 -- UARTLP Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3595 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3596
bogdanm 66:9c8f0e3462fb 3597 /**
bogdanm 66:9c8f0e3462fb 3598 * @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3599 * @{
bogdanm 66:9c8f0e3462fb 3600 */
bogdanm 66:9c8f0e3462fb 3601
bogdanm 66:9c8f0e3462fb 3602 /** UARTLP - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 3603 typedef struct {
bogdanm 66:9c8f0e3462fb 3604 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 3605 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
bogdanm 66:9c8f0e3462fb 3606 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
bogdanm 66:9c8f0e3462fb 3607 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
bogdanm 66:9c8f0e3462fb 3608 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 3609 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
bogdanm 66:9c8f0e3462fb 3610 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
bogdanm 66:9c8f0e3462fb 3611 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
bogdanm 66:9c8f0e3462fb 3612 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 3613 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
bogdanm 66:9c8f0e3462fb 3614 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
bogdanm 66:9c8f0e3462fb 3615 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
bogdanm 66:9c8f0e3462fb 3616 } UARTLP_Type;
bogdanm 66:9c8f0e3462fb 3617
bogdanm 66:9c8f0e3462fb 3618 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3619 -- UARTLP Register Masks
bogdanm 66:9c8f0e3462fb 3620 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3621
bogdanm 66:9c8f0e3462fb 3622 /**
bogdanm 66:9c8f0e3462fb 3623 * @addtogroup UARTLP_Register_Masks UARTLP Register Masks
bogdanm 66:9c8f0e3462fb 3624 * @{
bogdanm 66:9c8f0e3462fb 3625 */
bogdanm 66:9c8f0e3462fb 3626
bogdanm 66:9c8f0e3462fb 3627 /* BDH Bit Fields */
bogdanm 66:9c8f0e3462fb 3628 #define UARTLP_BDH_SBR_MASK 0x1Fu
bogdanm 66:9c8f0e3462fb 3629 #define UARTLP_BDH_SBR_SHIFT 0
bogdanm 66:9c8f0e3462fb 3630 #define UARTLP_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
bogdanm 66:9c8f0e3462fb 3631 #define UARTLP_BDH_SBNS_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3632 #define UARTLP_BDH_SBNS_SHIFT 5
bogdanm 66:9c8f0e3462fb 3633 #define UARTLP_BDH_RXEDGIE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3634 #define UARTLP_BDH_RXEDGIE_SHIFT 6
bogdanm 66:9c8f0e3462fb 3635 #define UARTLP_BDH_LBKDIE_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3636 #define UARTLP_BDH_LBKDIE_SHIFT 7
bogdanm 66:9c8f0e3462fb 3637 /* BDL Bit Fields */
bogdanm 66:9c8f0e3462fb 3638 #define UARTLP_BDL_SBR_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 3639 #define UARTLP_BDL_SBR_SHIFT 0
bogdanm 66:9c8f0e3462fb 3640 #define UARTLP_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
bogdanm 66:9c8f0e3462fb 3641 /* C1 Bit Fields */
bogdanm 66:9c8f0e3462fb 3642 #define UARTLP_C1_PT_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3643 #define UARTLP_C1_PT_SHIFT 0
bogdanm 66:9c8f0e3462fb 3644 #define UARTLP_C1_PE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3645 #define UARTLP_C1_PE_SHIFT 1
bogdanm 66:9c8f0e3462fb 3646 #define UARTLP_C1_ILT_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3647 #define UARTLP_C1_ILT_SHIFT 2
bogdanm 66:9c8f0e3462fb 3648 #define UARTLP_C1_WAKE_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3649 #define UARTLP_C1_WAKE_SHIFT 3
bogdanm 66:9c8f0e3462fb 3650 #define UARTLP_C1_M_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3651 #define UARTLP_C1_M_SHIFT 4
bogdanm 66:9c8f0e3462fb 3652 #define UARTLP_C1_RSRC_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3653 #define UARTLP_C1_RSRC_SHIFT 5
bogdanm 66:9c8f0e3462fb 3654 #define UARTLP_C1_DOZEEN_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3655 #define UARTLP_C1_DOZEEN_SHIFT 6
bogdanm 66:9c8f0e3462fb 3656 #define UARTLP_C1_LOOPS_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3657 #define UARTLP_C1_LOOPS_SHIFT 7
bogdanm 66:9c8f0e3462fb 3658 /* C2 Bit Fields */
bogdanm 66:9c8f0e3462fb 3659 #define UARTLP_C2_SBK_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3660 #define UARTLP_C2_SBK_SHIFT 0
bogdanm 66:9c8f0e3462fb 3661 #define UARTLP_C2_RWU_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3662 #define UARTLP_C2_RWU_SHIFT 1
bogdanm 66:9c8f0e3462fb 3663 #define UARTLP_C2_RE_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3664 #define UARTLP_C2_RE_SHIFT 2
bogdanm 66:9c8f0e3462fb 3665 #define UARTLP_C2_TE_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3666 #define UARTLP_C2_TE_SHIFT 3
bogdanm 66:9c8f0e3462fb 3667 #define UARTLP_C2_ILIE_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3668 #define UARTLP_C2_ILIE_SHIFT 4
bogdanm 66:9c8f0e3462fb 3669 #define UARTLP_C2_RIE_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3670 #define UARTLP_C2_RIE_SHIFT 5
bogdanm 66:9c8f0e3462fb 3671 #define UARTLP_C2_TCIE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3672 #define UARTLP_C2_TCIE_SHIFT 6
bogdanm 66:9c8f0e3462fb 3673 #define UARTLP_C2_TIE_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3674 #define UARTLP_C2_TIE_SHIFT 7
bogdanm 66:9c8f0e3462fb 3675 /* S1 Bit Fields */
bogdanm 66:9c8f0e3462fb 3676 #define UARTLP_S1_PF_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3677 #define UARTLP_S1_PF_SHIFT 0
bogdanm 66:9c8f0e3462fb 3678 #define UARTLP_S1_FE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3679 #define UARTLP_S1_FE_SHIFT 1
bogdanm 66:9c8f0e3462fb 3680 #define UARTLP_S1_NF_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3681 #define UARTLP_S1_NF_SHIFT 2
bogdanm 66:9c8f0e3462fb 3682 #define UARTLP_S1_OR_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3683 #define UARTLP_S1_OR_SHIFT 3
bogdanm 66:9c8f0e3462fb 3684 #define UARTLP_S1_IDLE_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3685 #define UARTLP_S1_IDLE_SHIFT 4
bogdanm 66:9c8f0e3462fb 3686 #define UARTLP_S1_RDRF_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3687 #define UARTLP_S1_RDRF_SHIFT 5
bogdanm 66:9c8f0e3462fb 3688 #define UARTLP_S1_TC_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3689 #define UARTLP_S1_TC_SHIFT 6
bogdanm 66:9c8f0e3462fb 3690 #define UARTLP_S1_TDRE_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3691 #define UARTLP_S1_TDRE_SHIFT 7
bogdanm 66:9c8f0e3462fb 3692 /* S2 Bit Fields */
bogdanm 66:9c8f0e3462fb 3693 #define UARTLP_S2_RAF_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3694 #define UARTLP_S2_RAF_SHIFT 0
bogdanm 66:9c8f0e3462fb 3695 #define UARTLP_S2_LBKDE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3696 #define UARTLP_S2_LBKDE_SHIFT 1
bogdanm 66:9c8f0e3462fb 3697 #define UARTLP_S2_BRK13_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3698 #define UARTLP_S2_BRK13_SHIFT 2
bogdanm 66:9c8f0e3462fb 3699 #define UARTLP_S2_RWUID_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3700 #define UARTLP_S2_RWUID_SHIFT 3
bogdanm 66:9c8f0e3462fb 3701 #define UARTLP_S2_RXINV_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3702 #define UARTLP_S2_RXINV_SHIFT 4
bogdanm 66:9c8f0e3462fb 3703 #define UARTLP_S2_MSBF_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3704 #define UARTLP_S2_MSBF_SHIFT 5
bogdanm 66:9c8f0e3462fb 3705 #define UARTLP_S2_RXEDGIF_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3706 #define UARTLP_S2_RXEDGIF_SHIFT 6
bogdanm 66:9c8f0e3462fb 3707 #define UARTLP_S2_LBKDIF_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3708 #define UARTLP_S2_LBKDIF_SHIFT 7
bogdanm 66:9c8f0e3462fb 3709 /* C3 Bit Fields */
bogdanm 66:9c8f0e3462fb 3710 #define UARTLP_C3_PEIE_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3711 #define UARTLP_C3_PEIE_SHIFT 0
bogdanm 66:9c8f0e3462fb 3712 #define UARTLP_C3_FEIE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3713 #define UARTLP_C3_FEIE_SHIFT 1
bogdanm 66:9c8f0e3462fb 3714 #define UARTLP_C3_NEIE_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3715 #define UARTLP_C3_NEIE_SHIFT 2
bogdanm 66:9c8f0e3462fb 3716 #define UARTLP_C3_ORIE_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3717 #define UARTLP_C3_ORIE_SHIFT 3
bogdanm 66:9c8f0e3462fb 3718 #define UARTLP_C3_TXINV_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3719 #define UARTLP_C3_TXINV_SHIFT 4
bogdanm 66:9c8f0e3462fb 3720 #define UARTLP_C3_TXDIR_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3721 #define UARTLP_C3_TXDIR_SHIFT 5
bogdanm 66:9c8f0e3462fb 3722 #define UARTLP_C3_R9T8_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3723 #define UARTLP_C3_R9T8_SHIFT 6
bogdanm 66:9c8f0e3462fb 3724 #define UARTLP_C3_R8T9_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3725 #define UARTLP_C3_R8T9_SHIFT 7
bogdanm 66:9c8f0e3462fb 3726 /* D Bit Fields */
bogdanm 66:9c8f0e3462fb 3727 #define UARTLP_D_R0T0_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3728 #define UARTLP_D_R0T0_SHIFT 0
bogdanm 66:9c8f0e3462fb 3729 #define UARTLP_D_R1T1_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3730 #define UARTLP_D_R1T1_SHIFT 1
bogdanm 66:9c8f0e3462fb 3731 #define UARTLP_D_R2T2_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3732 #define UARTLP_D_R2T2_SHIFT 2
bogdanm 66:9c8f0e3462fb 3733 #define UARTLP_D_R3T3_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3734 #define UARTLP_D_R3T3_SHIFT 3
bogdanm 66:9c8f0e3462fb 3735 #define UARTLP_D_R4T4_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3736 #define UARTLP_D_R4T4_SHIFT 4
bogdanm 66:9c8f0e3462fb 3737 #define UARTLP_D_R5T5_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3738 #define UARTLP_D_R5T5_SHIFT 5
bogdanm 66:9c8f0e3462fb 3739 #define UARTLP_D_R6T6_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3740 #define UARTLP_D_R6T6_SHIFT 6
bogdanm 66:9c8f0e3462fb 3741 #define UARTLP_D_R7T7_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3742 #define UARTLP_D_R7T7_SHIFT 7
bogdanm 66:9c8f0e3462fb 3743 /* MA1 Bit Fields */
bogdanm 66:9c8f0e3462fb 3744 #define UARTLP_MA1_MA_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 3745 #define UARTLP_MA1_MA_SHIFT 0
bogdanm 66:9c8f0e3462fb 3746 #define UARTLP_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
bogdanm 66:9c8f0e3462fb 3747 /* MA2 Bit Fields */
bogdanm 66:9c8f0e3462fb 3748 #define UARTLP_MA2_MA_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 3749 #define UARTLP_MA2_MA_SHIFT 0
bogdanm 66:9c8f0e3462fb 3750 #define UARTLP_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
bogdanm 66:9c8f0e3462fb 3751 /* C4 Bit Fields */
bogdanm 66:9c8f0e3462fb 3752 #define UARTLP_C4_OSR_MASK 0x1Fu
bogdanm 66:9c8f0e3462fb 3753 #define UARTLP_C4_OSR_SHIFT 0
bogdanm 66:9c8f0e3462fb 3754 #define UARTLP_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
bogdanm 66:9c8f0e3462fb 3755 #define UARTLP_C4_M10_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3756 #define UARTLP_C4_M10_SHIFT 5
bogdanm 66:9c8f0e3462fb 3757 #define UARTLP_C4_MAEN2_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3758 #define UARTLP_C4_MAEN2_SHIFT 6
bogdanm 66:9c8f0e3462fb 3759 #define UARTLP_C4_MAEN1_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3760 #define UARTLP_C4_MAEN1_SHIFT 7
bogdanm 66:9c8f0e3462fb 3761 /* C5 Bit Fields */
bogdanm 66:9c8f0e3462fb 3762 #define UARTLP_C5_RESYNCDIS_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3763 #define UARTLP_C5_RESYNCDIS_SHIFT 0
bogdanm 66:9c8f0e3462fb 3764 #define UARTLP_C5_BOTHEDGE_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3765 #define UARTLP_C5_BOTHEDGE_SHIFT 1
bogdanm 66:9c8f0e3462fb 3766 #define UARTLP_C5_RDMAE_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3767 #define UARTLP_C5_RDMAE_SHIFT 5
bogdanm 66:9c8f0e3462fb 3768 #define UARTLP_C5_TDMAE_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3769 #define UARTLP_C5_TDMAE_SHIFT 7
bogdanm 66:9c8f0e3462fb 3770
bogdanm 66:9c8f0e3462fb 3771 /**
bogdanm 66:9c8f0e3462fb 3772 * @}
bogdanm 66:9c8f0e3462fb 3773 */ /* end of group UARTLP_Register_Masks */
bogdanm 66:9c8f0e3462fb 3774
bogdanm 66:9c8f0e3462fb 3775
bogdanm 66:9c8f0e3462fb 3776 /* UARTLP - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 3777 /** Peripheral UART0 base address */
bogdanm 66:9c8f0e3462fb 3778 #define UART0_BASE (0x4006A000u)
bogdanm 66:9c8f0e3462fb 3779 /** Peripheral UART0 base pointer */
bogdanm 66:9c8f0e3462fb 3780 #define UART0 ((UARTLP_Type *)UART0_BASE)
bogdanm 66:9c8f0e3462fb 3781 /** Array initializer of UARTLP peripheral base pointers */
bogdanm 66:9c8f0e3462fb 3782 #define UARTLP_BASES { UART0 }
bogdanm 66:9c8f0e3462fb 3783
bogdanm 66:9c8f0e3462fb 3784 /**
bogdanm 66:9c8f0e3462fb 3785 * @}
bogdanm 66:9c8f0e3462fb 3786 */ /* end of group UARTLP_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 3787
bogdanm 66:9c8f0e3462fb 3788
bogdanm 66:9c8f0e3462fb 3789 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3790 -- USB Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3791 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3792
bogdanm 66:9c8f0e3462fb 3793 /**
bogdanm 66:9c8f0e3462fb 3794 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
bogdanm 66:9c8f0e3462fb 3795 * @{
bogdanm 66:9c8f0e3462fb 3796 */
bogdanm 66:9c8f0e3462fb 3797
bogdanm 66:9c8f0e3462fb 3798 /** USB - Register Layout Typedef */
bogdanm 66:9c8f0e3462fb 3799 typedef struct {
bogdanm 66:9c8f0e3462fb 3800 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
bogdanm 66:9c8f0e3462fb 3801 uint8_t RESERVED_0[3];
bogdanm 66:9c8f0e3462fb 3802 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
bogdanm 66:9c8f0e3462fb 3803 uint8_t RESERVED_1[3];
bogdanm 66:9c8f0e3462fb 3804 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
bogdanm 66:9c8f0e3462fb 3805 uint8_t RESERVED_2[3];
bogdanm 66:9c8f0e3462fb 3806 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
bogdanm 66:9c8f0e3462fb 3807 uint8_t RESERVED_3[3];
bogdanm 66:9c8f0e3462fb 3808 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
bogdanm 66:9c8f0e3462fb 3809 uint8_t RESERVED_4[3];
bogdanm 66:9c8f0e3462fb 3810 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
bogdanm 66:9c8f0e3462fb 3811 uint8_t RESERVED_5[3];
bogdanm 66:9c8f0e3462fb 3812 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
bogdanm 66:9c8f0e3462fb 3813 uint8_t RESERVED_6[3];
bogdanm 66:9c8f0e3462fb 3814 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
bogdanm 66:9c8f0e3462fb 3815 uint8_t RESERVED_7[99];
bogdanm 66:9c8f0e3462fb 3816 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
bogdanm 66:9c8f0e3462fb 3817 uint8_t RESERVED_8[3];
bogdanm 66:9c8f0e3462fb 3818 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
bogdanm 66:9c8f0e3462fb 3819 uint8_t RESERVED_9[3];
bogdanm 66:9c8f0e3462fb 3820 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
bogdanm 66:9c8f0e3462fb 3821 uint8_t RESERVED_10[3];
bogdanm 66:9c8f0e3462fb 3822 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
bogdanm 66:9c8f0e3462fb 3823 uint8_t RESERVED_11[3];
bogdanm 66:9c8f0e3462fb 3824 __I uint8_t STAT; /**< Status register, offset: 0x90 */
bogdanm 66:9c8f0e3462fb 3825 uint8_t RESERVED_12[3];
bogdanm 66:9c8f0e3462fb 3826 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
bogdanm 66:9c8f0e3462fb 3827 uint8_t RESERVED_13[3];
bogdanm 66:9c8f0e3462fb 3828 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
bogdanm 66:9c8f0e3462fb 3829 uint8_t RESERVED_14[3];
bogdanm 66:9c8f0e3462fb 3830 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
bogdanm 66:9c8f0e3462fb 3831 uint8_t RESERVED_15[3];
bogdanm 66:9c8f0e3462fb 3832 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
bogdanm 66:9c8f0e3462fb 3833 uint8_t RESERVED_16[3];
bogdanm 66:9c8f0e3462fb 3834 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
bogdanm 66:9c8f0e3462fb 3835 uint8_t RESERVED_17[3];
bogdanm 66:9c8f0e3462fb 3836 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
bogdanm 66:9c8f0e3462fb 3837 uint8_t RESERVED_18[3];
bogdanm 66:9c8f0e3462fb 3838 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
bogdanm 66:9c8f0e3462fb 3839 uint8_t RESERVED_19[3];
bogdanm 66:9c8f0e3462fb 3840 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
bogdanm 66:9c8f0e3462fb 3841 uint8_t RESERVED_20[3];
bogdanm 66:9c8f0e3462fb 3842 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
bogdanm 66:9c8f0e3462fb 3843 uint8_t RESERVED_21[11];
bogdanm 66:9c8f0e3462fb 3844 struct { /* offset: 0xC0, array step: 0x4 */
bogdanm 66:9c8f0e3462fb 3845 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
bogdanm 66:9c8f0e3462fb 3846 uint8_t RESERVED_0[3];
bogdanm 66:9c8f0e3462fb 3847 } ENDPOINT[16];
bogdanm 66:9c8f0e3462fb 3848 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
bogdanm 66:9c8f0e3462fb 3849 uint8_t RESERVED_22[3];
bogdanm 66:9c8f0e3462fb 3850 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
bogdanm 66:9c8f0e3462fb 3851 uint8_t RESERVED_23[3];
bogdanm 66:9c8f0e3462fb 3852 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
bogdanm 66:9c8f0e3462fb 3853 uint8_t RESERVED_24[3];
bogdanm 66:9c8f0e3462fb 3854 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
bogdanm 66:9c8f0e3462fb 3855 } USB_Type;
bogdanm 66:9c8f0e3462fb 3856
bogdanm 66:9c8f0e3462fb 3857 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 3858 -- USB Register Masks
bogdanm 66:9c8f0e3462fb 3859 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 3860
bogdanm 66:9c8f0e3462fb 3861 /**
bogdanm 66:9c8f0e3462fb 3862 * @addtogroup USB_Register_Masks USB Register Masks
bogdanm 66:9c8f0e3462fb 3863 * @{
bogdanm 66:9c8f0e3462fb 3864 */
bogdanm 66:9c8f0e3462fb 3865
bogdanm 66:9c8f0e3462fb 3866 /* PERID Bit Fields */
bogdanm 66:9c8f0e3462fb 3867 #define USB_PERID_ID_MASK 0x3Fu
bogdanm 66:9c8f0e3462fb 3868 #define USB_PERID_ID_SHIFT 0
bogdanm 66:9c8f0e3462fb 3869 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
bogdanm 66:9c8f0e3462fb 3870 /* IDCOMP Bit Fields */
bogdanm 66:9c8f0e3462fb 3871 #define USB_IDCOMP_NID_MASK 0x3Fu
bogdanm 66:9c8f0e3462fb 3872 #define USB_IDCOMP_NID_SHIFT 0
bogdanm 66:9c8f0e3462fb 3873 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
bogdanm 66:9c8f0e3462fb 3874 /* REV Bit Fields */
bogdanm 66:9c8f0e3462fb 3875 #define USB_REV_REV_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 3876 #define USB_REV_REV_SHIFT 0
bogdanm 66:9c8f0e3462fb 3877 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
bogdanm 66:9c8f0e3462fb 3878 /* ADDINFO Bit Fields */
bogdanm 66:9c8f0e3462fb 3879 #define USB_ADDINFO_IEHOST_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3880 #define USB_ADDINFO_IEHOST_SHIFT 0
bogdanm 66:9c8f0e3462fb 3881 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
bogdanm 66:9c8f0e3462fb 3882 #define USB_ADDINFO_IRQNUM_SHIFT 3
bogdanm 66:9c8f0e3462fb 3883 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
bogdanm 66:9c8f0e3462fb 3884 /* OTGISTAT Bit Fields */
bogdanm 66:9c8f0e3462fb 3885 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3886 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
bogdanm 66:9c8f0e3462fb 3887 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3888 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
bogdanm 66:9c8f0e3462fb 3889 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3890 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
bogdanm 66:9c8f0e3462fb 3891 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3892 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
bogdanm 66:9c8f0e3462fb 3893 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3894 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
bogdanm 66:9c8f0e3462fb 3895 #define USB_OTGISTAT_IDCHG_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3896 #define USB_OTGISTAT_IDCHG_SHIFT 7
bogdanm 66:9c8f0e3462fb 3897 /* OTGICR Bit Fields */
bogdanm 66:9c8f0e3462fb 3898 #define USB_OTGICR_AVBUSEN_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3899 #define USB_OTGICR_AVBUSEN_SHIFT 0
bogdanm 66:9c8f0e3462fb 3900 #define USB_OTGICR_BSESSEN_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3901 #define USB_OTGICR_BSESSEN_SHIFT 2
bogdanm 66:9c8f0e3462fb 3902 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3903 #define USB_OTGICR_SESSVLDEN_SHIFT 3
bogdanm 66:9c8f0e3462fb 3904 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3905 #define USB_OTGICR_LINESTATEEN_SHIFT 5
bogdanm 66:9c8f0e3462fb 3906 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3907 #define USB_OTGICR_ONEMSECEN_SHIFT 6
bogdanm 66:9c8f0e3462fb 3908 #define USB_OTGICR_IDEN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3909 #define USB_OTGICR_IDEN_SHIFT 7
bogdanm 66:9c8f0e3462fb 3910 /* OTGSTAT Bit Fields */
bogdanm 66:9c8f0e3462fb 3911 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3912 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
bogdanm 66:9c8f0e3462fb 3913 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3914 #define USB_OTGSTAT_BSESSEND_SHIFT 2
bogdanm 66:9c8f0e3462fb 3915 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3916 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
bogdanm 66:9c8f0e3462fb 3917 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3918 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
bogdanm 66:9c8f0e3462fb 3919 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3920 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
bogdanm 66:9c8f0e3462fb 3921 #define USB_OTGSTAT_ID_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3922 #define USB_OTGSTAT_ID_SHIFT 7
bogdanm 66:9c8f0e3462fb 3923 /* OTGCTL Bit Fields */
bogdanm 66:9c8f0e3462fb 3924 #define USB_OTGCTL_OTGEN_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3925 #define USB_OTGCTL_OTGEN_SHIFT 2
bogdanm 66:9c8f0e3462fb 3926 #define USB_OTGCTL_DMLOW_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3927 #define USB_OTGCTL_DMLOW_SHIFT 4
bogdanm 66:9c8f0e3462fb 3928 #define USB_OTGCTL_DPLOW_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3929 #define USB_OTGCTL_DPLOW_SHIFT 5
bogdanm 66:9c8f0e3462fb 3930 #define USB_OTGCTL_DPHIGH_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3931 #define USB_OTGCTL_DPHIGH_SHIFT 7
bogdanm 66:9c8f0e3462fb 3932 /* ISTAT Bit Fields */
bogdanm 66:9c8f0e3462fb 3933 #define USB_ISTAT_USBRST_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3934 #define USB_ISTAT_USBRST_SHIFT 0
bogdanm 66:9c8f0e3462fb 3935 #define USB_ISTAT_ERROR_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3936 #define USB_ISTAT_ERROR_SHIFT 1
bogdanm 66:9c8f0e3462fb 3937 #define USB_ISTAT_SOFTOK_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3938 #define USB_ISTAT_SOFTOK_SHIFT 2
bogdanm 66:9c8f0e3462fb 3939 #define USB_ISTAT_TOKDNE_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3940 #define USB_ISTAT_TOKDNE_SHIFT 3
bogdanm 66:9c8f0e3462fb 3941 #define USB_ISTAT_SLEEP_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3942 #define USB_ISTAT_SLEEP_SHIFT 4
bogdanm 66:9c8f0e3462fb 3943 #define USB_ISTAT_RESUME_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3944 #define USB_ISTAT_RESUME_SHIFT 5
bogdanm 66:9c8f0e3462fb 3945 #define USB_ISTAT_ATTACH_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3946 #define USB_ISTAT_ATTACH_SHIFT 6
bogdanm 66:9c8f0e3462fb 3947 #define USB_ISTAT_STALL_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3948 #define USB_ISTAT_STALL_SHIFT 7
bogdanm 66:9c8f0e3462fb 3949 /* INTEN Bit Fields */
bogdanm 66:9c8f0e3462fb 3950 #define USB_INTEN_USBRSTEN_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3951 #define USB_INTEN_USBRSTEN_SHIFT 0
bogdanm 66:9c8f0e3462fb 3952 #define USB_INTEN_ERROREN_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3953 #define USB_INTEN_ERROREN_SHIFT 1
bogdanm 66:9c8f0e3462fb 3954 #define USB_INTEN_SOFTOKEN_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3955 #define USB_INTEN_SOFTOKEN_SHIFT 2
bogdanm 66:9c8f0e3462fb 3956 #define USB_INTEN_TOKDNEEN_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3957 #define USB_INTEN_TOKDNEEN_SHIFT 3
bogdanm 66:9c8f0e3462fb 3958 #define USB_INTEN_SLEEPEN_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3959 #define USB_INTEN_SLEEPEN_SHIFT 4
bogdanm 66:9c8f0e3462fb 3960 #define USB_INTEN_RESUMEEN_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3961 #define USB_INTEN_RESUMEEN_SHIFT 5
bogdanm 66:9c8f0e3462fb 3962 #define USB_INTEN_ATTACHEN_MASK 0x40u
bogdanm 66:9c8f0e3462fb 3963 #define USB_INTEN_ATTACHEN_SHIFT 6
bogdanm 66:9c8f0e3462fb 3964 #define USB_INTEN_STALLEN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3965 #define USB_INTEN_STALLEN_SHIFT 7
bogdanm 66:9c8f0e3462fb 3966 /* ERRSTAT Bit Fields */
bogdanm 66:9c8f0e3462fb 3967 #define USB_ERRSTAT_PIDERR_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3968 #define USB_ERRSTAT_PIDERR_SHIFT 0
bogdanm 66:9c8f0e3462fb 3969 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3970 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
bogdanm 66:9c8f0e3462fb 3971 #define USB_ERRSTAT_CRC16_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3972 #define USB_ERRSTAT_CRC16_SHIFT 2
bogdanm 66:9c8f0e3462fb 3973 #define USB_ERRSTAT_DFN8_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3974 #define USB_ERRSTAT_DFN8_SHIFT 3
bogdanm 66:9c8f0e3462fb 3975 #define USB_ERRSTAT_BTOERR_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3976 #define USB_ERRSTAT_BTOERR_SHIFT 4
bogdanm 66:9c8f0e3462fb 3977 #define USB_ERRSTAT_DMAERR_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3978 #define USB_ERRSTAT_DMAERR_SHIFT 5
bogdanm 66:9c8f0e3462fb 3979 #define USB_ERRSTAT_BTSERR_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3980 #define USB_ERRSTAT_BTSERR_SHIFT 7
bogdanm 66:9c8f0e3462fb 3981 /* ERREN Bit Fields */
bogdanm 66:9c8f0e3462fb 3982 #define USB_ERREN_PIDERREN_MASK 0x1u
bogdanm 66:9c8f0e3462fb 3983 #define USB_ERREN_PIDERREN_SHIFT 0
bogdanm 66:9c8f0e3462fb 3984 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
bogdanm 66:9c8f0e3462fb 3985 #define USB_ERREN_CRC5EOFEN_SHIFT 1
bogdanm 66:9c8f0e3462fb 3986 #define USB_ERREN_CRC16EN_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3987 #define USB_ERREN_CRC16EN_SHIFT 2
bogdanm 66:9c8f0e3462fb 3988 #define USB_ERREN_DFN8EN_MASK 0x8u
bogdanm 66:9c8f0e3462fb 3989 #define USB_ERREN_DFN8EN_SHIFT 3
bogdanm 66:9c8f0e3462fb 3990 #define USB_ERREN_BTOERREN_MASK 0x10u
bogdanm 66:9c8f0e3462fb 3991 #define USB_ERREN_BTOERREN_SHIFT 4
bogdanm 66:9c8f0e3462fb 3992 #define USB_ERREN_DMAERREN_MASK 0x20u
bogdanm 66:9c8f0e3462fb 3993 #define USB_ERREN_DMAERREN_SHIFT 5
bogdanm 66:9c8f0e3462fb 3994 #define USB_ERREN_BTSERREN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 3995 #define USB_ERREN_BTSERREN_SHIFT 7
bogdanm 66:9c8f0e3462fb 3996 /* STAT Bit Fields */
bogdanm 66:9c8f0e3462fb 3997 #define USB_STAT_ODD_MASK 0x4u
bogdanm 66:9c8f0e3462fb 3998 #define USB_STAT_ODD_SHIFT 2
bogdanm 66:9c8f0e3462fb 3999 #define USB_STAT_TX_MASK 0x8u
bogdanm 66:9c8f0e3462fb 4000 #define USB_STAT_TX_SHIFT 3
bogdanm 66:9c8f0e3462fb 4001 #define USB_STAT_ENDP_MASK 0xF0u
bogdanm 66:9c8f0e3462fb 4002 #define USB_STAT_ENDP_SHIFT 4
bogdanm 66:9c8f0e3462fb 4003 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
bogdanm 66:9c8f0e3462fb 4004 /* CTL Bit Fields */
bogdanm 66:9c8f0e3462fb 4005 #define USB_CTL_USBENSOFEN_MASK 0x1u
bogdanm 66:9c8f0e3462fb 4006 #define USB_CTL_USBENSOFEN_SHIFT 0
bogdanm 66:9c8f0e3462fb 4007 #define USB_CTL_ODDRST_MASK 0x2u
bogdanm 66:9c8f0e3462fb 4008 #define USB_CTL_ODDRST_SHIFT 1
bogdanm 66:9c8f0e3462fb 4009 #define USB_CTL_RESUME_MASK 0x4u
bogdanm 66:9c8f0e3462fb 4010 #define USB_CTL_RESUME_SHIFT 2
bogdanm 66:9c8f0e3462fb 4011 #define USB_CTL_HOSTMODEEN_MASK 0x8u
bogdanm 66:9c8f0e3462fb 4012 #define USB_CTL_HOSTMODEEN_SHIFT 3
bogdanm 66:9c8f0e3462fb 4013 #define USB_CTL_RESET_MASK 0x10u
bogdanm 66:9c8f0e3462fb 4014 #define USB_CTL_RESET_SHIFT 4
bogdanm 66:9c8f0e3462fb 4015 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
bogdanm 66:9c8f0e3462fb 4016 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
bogdanm 66:9c8f0e3462fb 4017 #define USB_CTL_SE0_MASK 0x40u
bogdanm 66:9c8f0e3462fb 4018 #define USB_CTL_SE0_SHIFT 6
bogdanm 66:9c8f0e3462fb 4019 #define USB_CTL_JSTATE_MASK 0x80u
bogdanm 66:9c8f0e3462fb 4020 #define USB_CTL_JSTATE_SHIFT 7
bogdanm 66:9c8f0e3462fb 4021 /* ADDR Bit Fields */
bogdanm 66:9c8f0e3462fb 4022 #define USB_ADDR_ADDR_MASK 0x7Fu
bogdanm 66:9c8f0e3462fb 4023 #define USB_ADDR_ADDR_SHIFT 0
bogdanm 66:9c8f0e3462fb 4024 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
bogdanm 66:9c8f0e3462fb 4025 #define USB_ADDR_LSEN_MASK 0x80u
bogdanm 66:9c8f0e3462fb 4026 #define USB_ADDR_LSEN_SHIFT 7
bogdanm 66:9c8f0e3462fb 4027 /* BDTPAGE1 Bit Fields */
bogdanm 66:9c8f0e3462fb 4028 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
bogdanm 66:9c8f0e3462fb 4029 #define USB_BDTPAGE1_BDTBA_SHIFT 1
bogdanm 66:9c8f0e3462fb 4030 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
bogdanm 66:9c8f0e3462fb 4031 /* FRMNUML Bit Fields */
bogdanm 66:9c8f0e3462fb 4032 #define USB_FRMNUML_FRM_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 4033 #define USB_FRMNUML_FRM_SHIFT 0
bogdanm 66:9c8f0e3462fb 4034 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
bogdanm 66:9c8f0e3462fb 4035 /* FRMNUMH Bit Fields */
bogdanm 66:9c8f0e3462fb 4036 #define USB_FRMNUMH_FRM_MASK 0x7u
bogdanm 66:9c8f0e3462fb 4037 #define USB_FRMNUMH_FRM_SHIFT 0
bogdanm 66:9c8f0e3462fb 4038 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
bogdanm 66:9c8f0e3462fb 4039 /* TOKEN Bit Fields */
bogdanm 66:9c8f0e3462fb 4040 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
bogdanm 66:9c8f0e3462fb 4041 #define USB_TOKEN_TOKENENDPT_SHIFT 0
bogdanm 66:9c8f0e3462fb 4042 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
bogdanm 66:9c8f0e3462fb 4043 #define USB_TOKEN_TOKENPID_MASK 0xF0u
bogdanm 66:9c8f0e3462fb 4044 #define USB_TOKEN_TOKENPID_SHIFT 4
bogdanm 66:9c8f0e3462fb 4045 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
bogdanm 66:9c8f0e3462fb 4046 /* SOFTHLD Bit Fields */
bogdanm 66:9c8f0e3462fb 4047 #define USB_SOFTHLD_CNT_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 4048 #define USB_SOFTHLD_CNT_SHIFT 0
bogdanm 66:9c8f0e3462fb 4049 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
bogdanm 66:9c8f0e3462fb 4050 /* BDTPAGE2 Bit Fields */
bogdanm 66:9c8f0e3462fb 4051 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 4052 #define USB_BDTPAGE2_BDTBA_SHIFT 0
bogdanm 66:9c8f0e3462fb 4053 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
bogdanm 66:9c8f0e3462fb 4054 /* BDTPAGE3 Bit Fields */
bogdanm 66:9c8f0e3462fb 4055 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
bogdanm 66:9c8f0e3462fb 4056 #define USB_BDTPAGE3_BDTBA_SHIFT 0
bogdanm 66:9c8f0e3462fb 4057 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
bogdanm 66:9c8f0e3462fb 4058 /* ENDPT Bit Fields */
bogdanm 66:9c8f0e3462fb 4059 #define USB_ENDPT_EPHSHK_MASK 0x1u
bogdanm 66:9c8f0e3462fb 4060 #define USB_ENDPT_EPHSHK_SHIFT 0
bogdanm 66:9c8f0e3462fb 4061 #define USB_ENDPT_EPSTALL_MASK 0x2u
bogdanm 66:9c8f0e3462fb 4062 #define USB_ENDPT_EPSTALL_SHIFT 1
bogdanm 66:9c8f0e3462fb 4063 #define USB_ENDPT_EPTXEN_MASK 0x4u
bogdanm 66:9c8f0e3462fb 4064 #define USB_ENDPT_EPTXEN_SHIFT 2
bogdanm 66:9c8f0e3462fb 4065 #define USB_ENDPT_EPRXEN_MASK 0x8u
bogdanm 66:9c8f0e3462fb 4066 #define USB_ENDPT_EPRXEN_SHIFT 3
bogdanm 66:9c8f0e3462fb 4067 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
bogdanm 66:9c8f0e3462fb 4068 #define USB_ENDPT_EPCTLDIS_SHIFT 4
bogdanm 66:9c8f0e3462fb 4069 #define USB_ENDPT_RETRYDIS_MASK 0x40u
bogdanm 66:9c8f0e3462fb 4070 #define USB_ENDPT_RETRYDIS_SHIFT 6
bogdanm 66:9c8f0e3462fb 4071 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
bogdanm 66:9c8f0e3462fb 4072 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
bogdanm 66:9c8f0e3462fb 4073 /* USBCTRL Bit Fields */
bogdanm 66:9c8f0e3462fb 4074 #define USB_USBCTRL_PDE_MASK 0x40u
bogdanm 66:9c8f0e3462fb 4075 #define USB_USBCTRL_PDE_SHIFT 6
bogdanm 66:9c8f0e3462fb 4076 #define USB_USBCTRL_SUSP_MASK 0x80u
bogdanm 66:9c8f0e3462fb 4077 #define USB_USBCTRL_SUSP_SHIFT 7
bogdanm 66:9c8f0e3462fb 4078 /* OBSERVE Bit Fields */
bogdanm 66:9c8f0e3462fb 4079 #define USB_OBSERVE_DMPD_MASK 0x10u
bogdanm 66:9c8f0e3462fb 4080 #define USB_OBSERVE_DMPD_SHIFT 4
bogdanm 66:9c8f0e3462fb 4081 #define USB_OBSERVE_DPPD_MASK 0x40u
bogdanm 66:9c8f0e3462fb 4082 #define USB_OBSERVE_DPPD_SHIFT 6
bogdanm 66:9c8f0e3462fb 4083 #define USB_OBSERVE_DPPU_MASK 0x80u
bogdanm 66:9c8f0e3462fb 4084 #define USB_OBSERVE_DPPU_SHIFT 7
bogdanm 66:9c8f0e3462fb 4085 /* CONTROL Bit Fields */
bogdanm 66:9c8f0e3462fb 4086 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
bogdanm 66:9c8f0e3462fb 4087 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
bogdanm 66:9c8f0e3462fb 4088 /* USBTRC0 Bit Fields */
bogdanm 66:9c8f0e3462fb 4089 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
bogdanm 66:9c8f0e3462fb 4090 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
bogdanm 66:9c8f0e3462fb 4091 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
bogdanm 66:9c8f0e3462fb 4092 #define USB_USBTRC0_SYNC_DET_SHIFT 1
bogdanm 66:9c8f0e3462fb 4093 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
bogdanm 66:9c8f0e3462fb 4094 #define USB_USBTRC0_USBRESMEN_SHIFT 5
bogdanm 66:9c8f0e3462fb 4095 #define USB_USBTRC0_USBRESET_MASK 0x80u
bogdanm 66:9c8f0e3462fb 4096 #define USB_USBTRC0_USBRESET_SHIFT 7
bogdanm 66:9c8f0e3462fb 4097
bogdanm 66:9c8f0e3462fb 4098 /**
bogdanm 66:9c8f0e3462fb 4099 * @}
bogdanm 66:9c8f0e3462fb 4100 */ /* end of group USB_Register_Masks */
bogdanm 66:9c8f0e3462fb 4101
bogdanm 66:9c8f0e3462fb 4102
bogdanm 66:9c8f0e3462fb 4103 /* USB - Peripheral instance base addresses */
bogdanm 66:9c8f0e3462fb 4104 /** Peripheral USB0 base address */
bogdanm 66:9c8f0e3462fb 4105 #define USB0_BASE (0x40072000u)
bogdanm 66:9c8f0e3462fb 4106 /** Peripheral USB0 base pointer */
bogdanm 66:9c8f0e3462fb 4107 #define USB0 ((USB_Type *)USB0_BASE)
bogdanm 66:9c8f0e3462fb 4108 /** Array initializer of USB peripheral base pointers */
bogdanm 66:9c8f0e3462fb 4109 #define USB_BASES { USB0 }
bogdanm 66:9c8f0e3462fb 4110
bogdanm 66:9c8f0e3462fb 4111 /**
bogdanm 66:9c8f0e3462fb 4112 * @}
bogdanm 66:9c8f0e3462fb 4113 */ /* end of group USB_Peripheral_Access_Layer */
bogdanm 66:9c8f0e3462fb 4114
bogdanm 66:9c8f0e3462fb 4115
bogdanm 66:9c8f0e3462fb 4116 /*
bogdanm 66:9c8f0e3462fb 4117 ** End of section using anonymous unions
bogdanm 66:9c8f0e3462fb 4118 */
bogdanm 66:9c8f0e3462fb 4119
bogdanm 66:9c8f0e3462fb 4120 #if defined(__ARMCC_VERSION)
bogdanm 66:9c8f0e3462fb 4121 #pragma pop
bogdanm 66:9c8f0e3462fb 4122 #elif defined(__CWCC__)
bogdanm 66:9c8f0e3462fb 4123 #pragma pop
bogdanm 66:9c8f0e3462fb 4124 #elif defined(__GNUC__)
bogdanm 66:9c8f0e3462fb 4125 /* leave anonymous unions enabled */
bogdanm 66:9c8f0e3462fb 4126 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 66:9c8f0e3462fb 4127 #pragma language=default
bogdanm 66:9c8f0e3462fb 4128 #else
bogdanm 66:9c8f0e3462fb 4129 #error Not supported compiler type
bogdanm 66:9c8f0e3462fb 4130 #endif
bogdanm 66:9c8f0e3462fb 4131
bogdanm 66:9c8f0e3462fb 4132 /**
bogdanm 66:9c8f0e3462fb 4133 * @}
bogdanm 66:9c8f0e3462fb 4134 */ /* end of group Peripheral_access_layer */
bogdanm 66:9c8f0e3462fb 4135
bogdanm 66:9c8f0e3462fb 4136
bogdanm 66:9c8f0e3462fb 4137 /* ----------------------------------------------------------------------------
bogdanm 66:9c8f0e3462fb 4138 -- Backward Compatibility
bogdanm 66:9c8f0e3462fb 4139 ---------------------------------------------------------------------------- */
bogdanm 66:9c8f0e3462fb 4140
bogdanm 66:9c8f0e3462fb 4141 /**
bogdanm 66:9c8f0e3462fb 4142 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
bogdanm 66:9c8f0e3462fb 4143 * @{
bogdanm 66:9c8f0e3462fb 4144 */
bogdanm 66:9c8f0e3462fb 4145
bogdanm 66:9c8f0e3462fb 4146 /* No backward compatibility issues. */
bogdanm 66:9c8f0e3462fb 4147
bogdanm 66:9c8f0e3462fb 4148 /**
bogdanm 66:9c8f0e3462fb 4149 * @}
bogdanm 66:9c8f0e3462fb 4150 */ /* end of group Backward_Compatibility_Symbols */
bogdanm 66:9c8f0e3462fb 4151
bogdanm 66:9c8f0e3462fb 4152
bogdanm 66:9c8f0e3462fb 4153 #endif /* #if !defined(MKL25Z4_H_) */
bogdanm 66:9c8f0e3462fb 4154
bogdanm 66:9c8f0e3462fb 4155 /* MKL25Z4.h, eof. */