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TARGET_LPC1549/core_cm0.h@79:0c05e21ae27e, 2014-02-21 (annotated)
- Committer:
- emilmont
- Date:
- Fri Feb 21 10:26:12 2014 +0000
- Revision:
- 79:0c05e21ae27e
Add LPC1549 Target
Change "us_ticker" implementation to 32-bit timer for NUCLEO_L152RE and NUCLEO_F401RE
Update KL05Z CMSIS-CORE
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 79:0c05e21ae27e | 1 | /**************************************************************************//** |
| emilmont | 79:0c05e21ae27e | 2 | * @file core_cm0.h |
| emilmont | 79:0c05e21ae27e | 3 | * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File |
| emilmont | 79:0c05e21ae27e | 4 | * @version V3.20 |
| emilmont | 79:0c05e21ae27e | 5 | * @date 25. February 2013 |
| emilmont | 79:0c05e21ae27e | 6 | * |
| emilmont | 79:0c05e21ae27e | 7 | * @note |
| emilmont | 79:0c05e21ae27e | 8 | * |
| emilmont | 79:0c05e21ae27e | 9 | ******************************************************************************/ |
| emilmont | 79:0c05e21ae27e | 10 | /* Copyright (c) 2009 - 2013 ARM LIMITED |
| emilmont | 79:0c05e21ae27e | 11 | |
| emilmont | 79:0c05e21ae27e | 12 | All rights reserved. |
| emilmont | 79:0c05e21ae27e | 13 | Redistribution and use in source and binary forms, with or without |
| emilmont | 79:0c05e21ae27e | 14 | modification, are permitted provided that the following conditions are met: |
| emilmont | 79:0c05e21ae27e | 15 | - Redistributions of source code must retain the above copyright |
| emilmont | 79:0c05e21ae27e | 16 | notice, this list of conditions and the following disclaimer. |
| emilmont | 79:0c05e21ae27e | 17 | - Redistributions in binary form must reproduce the above copyright |
| emilmont | 79:0c05e21ae27e | 18 | notice, this list of conditions and the following disclaimer in the |
| emilmont | 79:0c05e21ae27e | 19 | documentation and/or other materials provided with the distribution. |
| emilmont | 79:0c05e21ae27e | 20 | - Neither the name of ARM nor the names of its contributors may be used |
| emilmont | 79:0c05e21ae27e | 21 | to endorse or promote products derived from this software without |
| emilmont | 79:0c05e21ae27e | 22 | specific prior written permission. |
| emilmont | 79:0c05e21ae27e | 23 | * |
| emilmont | 79:0c05e21ae27e | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| emilmont | 79:0c05e21ae27e | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| emilmont | 79:0c05e21ae27e | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| emilmont | 79:0c05e21ae27e | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
| emilmont | 79:0c05e21ae27e | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| emilmont | 79:0c05e21ae27e | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| emilmont | 79:0c05e21ae27e | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| emilmont | 79:0c05e21ae27e | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| emilmont | 79:0c05e21ae27e | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| emilmont | 79:0c05e21ae27e | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| emilmont | 79:0c05e21ae27e | 34 | POSSIBILITY OF SUCH DAMAGE. |
| emilmont | 79:0c05e21ae27e | 35 | ---------------------------------------------------------------------------*/ |
| emilmont | 79:0c05e21ae27e | 36 | |
| emilmont | 79:0c05e21ae27e | 37 | |
| emilmont | 79:0c05e21ae27e | 38 | #if defined ( __ICCARM__ ) |
| emilmont | 79:0c05e21ae27e | 39 | #pragma system_include /* treat file as system include file for MISRA check */ |
| emilmont | 79:0c05e21ae27e | 40 | #endif |
| emilmont | 79:0c05e21ae27e | 41 | |
| emilmont | 79:0c05e21ae27e | 42 | #ifdef __cplusplus |
| emilmont | 79:0c05e21ae27e | 43 | extern "C" { |
| emilmont | 79:0c05e21ae27e | 44 | #endif |
| emilmont | 79:0c05e21ae27e | 45 | |
| emilmont | 79:0c05e21ae27e | 46 | #ifndef __CORE_CM0_H_GENERIC |
| emilmont | 79:0c05e21ae27e | 47 | #define __CORE_CM0_H_GENERIC |
| emilmont | 79:0c05e21ae27e | 48 | |
| emilmont | 79:0c05e21ae27e | 49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
| emilmont | 79:0c05e21ae27e | 50 | CMSIS violates the following MISRA-C:2004 rules: |
| emilmont | 79:0c05e21ae27e | 51 | |
| emilmont | 79:0c05e21ae27e | 52 | \li Required Rule 8.5, object/function definition in header file.<br> |
| emilmont | 79:0c05e21ae27e | 53 | Function definitions in header files are used to allow 'inlining'. |
| emilmont | 79:0c05e21ae27e | 54 | |
| emilmont | 79:0c05e21ae27e | 55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
| emilmont | 79:0c05e21ae27e | 56 | Unions are used for effective representation of core registers. |
| emilmont | 79:0c05e21ae27e | 57 | |
| emilmont | 79:0c05e21ae27e | 58 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
| emilmont | 79:0c05e21ae27e | 59 | Function-like macros are used to allow more efficient code. |
| emilmont | 79:0c05e21ae27e | 60 | */ |
| emilmont | 79:0c05e21ae27e | 61 | |
| emilmont | 79:0c05e21ae27e | 62 | |
| emilmont | 79:0c05e21ae27e | 63 | /******************************************************************************* |
| emilmont | 79:0c05e21ae27e | 64 | * CMSIS definitions |
| emilmont | 79:0c05e21ae27e | 65 | ******************************************************************************/ |
| emilmont | 79:0c05e21ae27e | 66 | /** \ingroup Cortex_M0 |
| emilmont | 79:0c05e21ae27e | 67 | @{ |
| emilmont | 79:0c05e21ae27e | 68 | */ |
| emilmont | 79:0c05e21ae27e | 69 | |
| emilmont | 79:0c05e21ae27e | 70 | /* CMSIS CM0 definitions */ |
| emilmont | 79:0c05e21ae27e | 71 | #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ |
| emilmont | 79:0c05e21ae27e | 72 | #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ |
| emilmont | 79:0c05e21ae27e | 73 | #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ |
| emilmont | 79:0c05e21ae27e | 74 | __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
| emilmont | 79:0c05e21ae27e | 75 | |
| emilmont | 79:0c05e21ae27e | 76 | #define __CORTEX_M (0x00) /*!< Cortex-M Core */ |
| emilmont | 79:0c05e21ae27e | 77 | |
| emilmont | 79:0c05e21ae27e | 78 | |
| emilmont | 79:0c05e21ae27e | 79 | #if defined ( __CC_ARM ) |
| emilmont | 79:0c05e21ae27e | 80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
| emilmont | 79:0c05e21ae27e | 81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
| emilmont | 79:0c05e21ae27e | 82 | #define __STATIC_INLINE static __inline |
| emilmont | 79:0c05e21ae27e | 83 | |
| emilmont | 79:0c05e21ae27e | 84 | #elif defined ( __ICCARM__ ) |
| emilmont | 79:0c05e21ae27e | 85 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
| emilmont | 79:0c05e21ae27e | 86 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
| emilmont | 79:0c05e21ae27e | 87 | #define __STATIC_INLINE static inline |
| emilmont | 79:0c05e21ae27e | 88 | |
| emilmont | 79:0c05e21ae27e | 89 | #elif defined ( __GNUC__ ) |
| emilmont | 79:0c05e21ae27e | 90 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
| emilmont | 79:0c05e21ae27e | 91 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
| emilmont | 79:0c05e21ae27e | 92 | #define __STATIC_INLINE static inline |
| emilmont | 79:0c05e21ae27e | 93 | |
| emilmont | 79:0c05e21ae27e | 94 | #elif defined ( __TASKING__ ) |
| emilmont | 79:0c05e21ae27e | 95 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
| emilmont | 79:0c05e21ae27e | 96 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
| emilmont | 79:0c05e21ae27e | 97 | #define __STATIC_INLINE static inline |
| emilmont | 79:0c05e21ae27e | 98 | |
| emilmont | 79:0c05e21ae27e | 99 | #endif |
| emilmont | 79:0c05e21ae27e | 100 | |
| emilmont | 79:0c05e21ae27e | 101 | /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all |
| emilmont | 79:0c05e21ae27e | 102 | */ |
| emilmont | 79:0c05e21ae27e | 103 | #define __FPU_USED 0 |
| emilmont | 79:0c05e21ae27e | 104 | |
| emilmont | 79:0c05e21ae27e | 105 | #if defined ( __CC_ARM ) |
| emilmont | 79:0c05e21ae27e | 106 | #if defined __TARGET_FPU_VFP |
| emilmont | 79:0c05e21ae27e | 107 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| emilmont | 79:0c05e21ae27e | 108 | #endif |
| emilmont | 79:0c05e21ae27e | 109 | |
| emilmont | 79:0c05e21ae27e | 110 | #elif defined ( __ICCARM__ ) |
| emilmont | 79:0c05e21ae27e | 111 | #if defined __ARMVFP__ |
| emilmont | 79:0c05e21ae27e | 112 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| emilmont | 79:0c05e21ae27e | 113 | #endif |
| emilmont | 79:0c05e21ae27e | 114 | |
| emilmont | 79:0c05e21ae27e | 115 | #elif defined ( __GNUC__ ) |
| emilmont | 79:0c05e21ae27e | 116 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
| emilmont | 79:0c05e21ae27e | 117 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| emilmont | 79:0c05e21ae27e | 118 | #endif |
| emilmont | 79:0c05e21ae27e | 119 | |
| emilmont | 79:0c05e21ae27e | 120 | #elif defined ( __TASKING__ ) |
| emilmont | 79:0c05e21ae27e | 121 | #if defined __FPU_VFP__ |
| emilmont | 79:0c05e21ae27e | 122 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| emilmont | 79:0c05e21ae27e | 123 | #endif |
| emilmont | 79:0c05e21ae27e | 124 | #endif |
| emilmont | 79:0c05e21ae27e | 125 | |
| emilmont | 79:0c05e21ae27e | 126 | #include <stdint.h> /* standard types definitions */ |
| emilmont | 79:0c05e21ae27e | 127 | #include <core_cmInstr.h> /* Core Instruction Access */ |
| emilmont | 79:0c05e21ae27e | 128 | #include <core_cmFunc.h> /* Core Function Access */ |
| emilmont | 79:0c05e21ae27e | 129 | |
| emilmont | 79:0c05e21ae27e | 130 | #endif /* __CORE_CM0_H_GENERIC */ |
| emilmont | 79:0c05e21ae27e | 131 | |
| emilmont | 79:0c05e21ae27e | 132 | #ifndef __CMSIS_GENERIC |
| emilmont | 79:0c05e21ae27e | 133 | |
| emilmont | 79:0c05e21ae27e | 134 | #ifndef __CORE_CM0_H_DEPENDANT |
| emilmont | 79:0c05e21ae27e | 135 | #define __CORE_CM0_H_DEPENDANT |
| emilmont | 79:0c05e21ae27e | 136 | |
| emilmont | 79:0c05e21ae27e | 137 | /* check device defines and use defaults */ |
| emilmont | 79:0c05e21ae27e | 138 | #if defined __CHECK_DEVICE_DEFINES |
| emilmont | 79:0c05e21ae27e | 139 | #ifndef __CM0_REV |
| emilmont | 79:0c05e21ae27e | 140 | #define __CM0_REV 0x0000 |
| emilmont | 79:0c05e21ae27e | 141 | #warning "__CM0_REV not defined in device header file; using default!" |
| emilmont | 79:0c05e21ae27e | 142 | #endif |
| emilmont | 79:0c05e21ae27e | 143 | |
| emilmont | 79:0c05e21ae27e | 144 | #ifndef __NVIC_PRIO_BITS |
| emilmont | 79:0c05e21ae27e | 145 | #define __NVIC_PRIO_BITS 2 |
| emilmont | 79:0c05e21ae27e | 146 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
| emilmont | 79:0c05e21ae27e | 147 | #endif |
| emilmont | 79:0c05e21ae27e | 148 | |
| emilmont | 79:0c05e21ae27e | 149 | #ifndef __Vendor_SysTickConfig |
| emilmont | 79:0c05e21ae27e | 150 | #define __Vendor_SysTickConfig 0 |
| emilmont | 79:0c05e21ae27e | 151 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
| emilmont | 79:0c05e21ae27e | 152 | #endif |
| emilmont | 79:0c05e21ae27e | 153 | #endif |
| emilmont | 79:0c05e21ae27e | 154 | |
| emilmont | 79:0c05e21ae27e | 155 | /* IO definitions (access restrictions to peripheral registers) */ |
| emilmont | 79:0c05e21ae27e | 156 | /** |
| emilmont | 79:0c05e21ae27e | 157 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
| emilmont | 79:0c05e21ae27e | 158 | |
| emilmont | 79:0c05e21ae27e | 159 | <strong>IO Type Qualifiers</strong> are used |
| emilmont | 79:0c05e21ae27e | 160 | \li to specify the access to peripheral variables. |
| emilmont | 79:0c05e21ae27e | 161 | \li for automatic generation of peripheral register debug information. |
| emilmont | 79:0c05e21ae27e | 162 | */ |
| emilmont | 79:0c05e21ae27e | 163 | #ifdef __cplusplus |
| emilmont | 79:0c05e21ae27e | 164 | #define __I volatile /*!< Defines 'read only' permissions */ |
| emilmont | 79:0c05e21ae27e | 165 | #else |
| emilmont | 79:0c05e21ae27e | 166 | #define __I volatile const /*!< Defines 'read only' permissions */ |
| emilmont | 79:0c05e21ae27e | 167 | #endif |
| emilmont | 79:0c05e21ae27e | 168 | #define __O volatile /*!< Defines 'write only' permissions */ |
| emilmont | 79:0c05e21ae27e | 169 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
| emilmont | 79:0c05e21ae27e | 170 | |
| emilmont | 79:0c05e21ae27e | 171 | /*@} end of group Cortex_M0 */ |
| emilmont | 79:0c05e21ae27e | 172 | |
| emilmont | 79:0c05e21ae27e | 173 | |
| emilmont | 79:0c05e21ae27e | 174 | |
| emilmont | 79:0c05e21ae27e | 175 | /******************************************************************************* |
| emilmont | 79:0c05e21ae27e | 176 | * Register Abstraction |
| emilmont | 79:0c05e21ae27e | 177 | Core Register contain: |
| emilmont | 79:0c05e21ae27e | 178 | - Core Register |
| emilmont | 79:0c05e21ae27e | 179 | - Core NVIC Register |
| emilmont | 79:0c05e21ae27e | 180 | - Core SCB Register |
| emilmont | 79:0c05e21ae27e | 181 | - Core SysTick Register |
| emilmont | 79:0c05e21ae27e | 182 | ******************************************************************************/ |
| emilmont | 79:0c05e21ae27e | 183 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
| emilmont | 79:0c05e21ae27e | 184 | \brief Type definitions and defines for Cortex-M processor based devices. |
| emilmont | 79:0c05e21ae27e | 185 | */ |
| emilmont | 79:0c05e21ae27e | 186 | |
| emilmont | 79:0c05e21ae27e | 187 | /** \ingroup CMSIS_core_register |
| emilmont | 79:0c05e21ae27e | 188 | \defgroup CMSIS_CORE Status and Control Registers |
| emilmont | 79:0c05e21ae27e | 189 | \brief Core Register type definitions. |
| emilmont | 79:0c05e21ae27e | 190 | @{ |
| emilmont | 79:0c05e21ae27e | 191 | */ |
| emilmont | 79:0c05e21ae27e | 192 | |
| emilmont | 79:0c05e21ae27e | 193 | /** \brief Union type to access the Application Program Status Register (APSR). |
| emilmont | 79:0c05e21ae27e | 194 | */ |
| emilmont | 79:0c05e21ae27e | 195 | typedef union |
| emilmont | 79:0c05e21ae27e | 196 | { |
| emilmont | 79:0c05e21ae27e | 197 | struct |
| emilmont | 79:0c05e21ae27e | 198 | { |
| emilmont | 79:0c05e21ae27e | 199 | #if (__CORTEX_M != 0x04) |
| emilmont | 79:0c05e21ae27e | 200 | uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ |
| emilmont | 79:0c05e21ae27e | 201 | #else |
| emilmont | 79:0c05e21ae27e | 202 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ |
| emilmont | 79:0c05e21ae27e | 203 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
| emilmont | 79:0c05e21ae27e | 204 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ |
| emilmont | 79:0c05e21ae27e | 205 | #endif |
| emilmont | 79:0c05e21ae27e | 206 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
| emilmont | 79:0c05e21ae27e | 207 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| emilmont | 79:0c05e21ae27e | 208 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| emilmont | 79:0c05e21ae27e | 209 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| emilmont | 79:0c05e21ae27e | 210 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| emilmont | 79:0c05e21ae27e | 211 | } b; /*!< Structure used for bit access */ |
| emilmont | 79:0c05e21ae27e | 212 | uint32_t w; /*!< Type used for word access */ |
| emilmont | 79:0c05e21ae27e | 213 | } APSR_Type; |
| emilmont | 79:0c05e21ae27e | 214 | |
| emilmont | 79:0c05e21ae27e | 215 | |
| emilmont | 79:0c05e21ae27e | 216 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
| emilmont | 79:0c05e21ae27e | 217 | */ |
| emilmont | 79:0c05e21ae27e | 218 | typedef union |
| emilmont | 79:0c05e21ae27e | 219 | { |
| emilmont | 79:0c05e21ae27e | 220 | struct |
| emilmont | 79:0c05e21ae27e | 221 | { |
| emilmont | 79:0c05e21ae27e | 222 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| emilmont | 79:0c05e21ae27e | 223 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
| emilmont | 79:0c05e21ae27e | 224 | } b; /*!< Structure used for bit access */ |
| emilmont | 79:0c05e21ae27e | 225 | uint32_t w; /*!< Type used for word access */ |
| emilmont | 79:0c05e21ae27e | 226 | } IPSR_Type; |
| emilmont | 79:0c05e21ae27e | 227 | |
| emilmont | 79:0c05e21ae27e | 228 | |
| emilmont | 79:0c05e21ae27e | 229 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
| emilmont | 79:0c05e21ae27e | 230 | */ |
| emilmont | 79:0c05e21ae27e | 231 | typedef union |
| emilmont | 79:0c05e21ae27e | 232 | { |
| emilmont | 79:0c05e21ae27e | 233 | struct |
| emilmont | 79:0c05e21ae27e | 234 | { |
| emilmont | 79:0c05e21ae27e | 235 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| emilmont | 79:0c05e21ae27e | 236 | #if (__CORTEX_M != 0x04) |
| emilmont | 79:0c05e21ae27e | 237 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
| emilmont | 79:0c05e21ae27e | 238 | #else |
| emilmont | 79:0c05e21ae27e | 239 | uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ |
| emilmont | 79:0c05e21ae27e | 240 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
| emilmont | 79:0c05e21ae27e | 241 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ |
| emilmont | 79:0c05e21ae27e | 242 | #endif |
| emilmont | 79:0c05e21ae27e | 243 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
| emilmont | 79:0c05e21ae27e | 244 | uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ |
| emilmont | 79:0c05e21ae27e | 245 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
| emilmont | 79:0c05e21ae27e | 246 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| emilmont | 79:0c05e21ae27e | 247 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| emilmont | 79:0c05e21ae27e | 248 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| emilmont | 79:0c05e21ae27e | 249 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| emilmont | 79:0c05e21ae27e | 250 | } b; /*!< Structure used for bit access */ |
| emilmont | 79:0c05e21ae27e | 251 | uint32_t w; /*!< Type used for word access */ |
| emilmont | 79:0c05e21ae27e | 252 | } xPSR_Type; |
| emilmont | 79:0c05e21ae27e | 253 | |
| emilmont | 79:0c05e21ae27e | 254 | |
| emilmont | 79:0c05e21ae27e | 255 | /** \brief Union type to access the Control Registers (CONTROL). |
| emilmont | 79:0c05e21ae27e | 256 | */ |
| emilmont | 79:0c05e21ae27e | 257 | typedef union |
| emilmont | 79:0c05e21ae27e | 258 | { |
| emilmont | 79:0c05e21ae27e | 259 | struct |
| emilmont | 79:0c05e21ae27e | 260 | { |
| emilmont | 79:0c05e21ae27e | 261 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
| emilmont | 79:0c05e21ae27e | 262 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
| emilmont | 79:0c05e21ae27e | 263 | uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ |
| emilmont | 79:0c05e21ae27e | 264 | uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ |
| emilmont | 79:0c05e21ae27e | 265 | } b; /*!< Structure used for bit access */ |
| emilmont | 79:0c05e21ae27e | 266 | uint32_t w; /*!< Type used for word access */ |
| emilmont | 79:0c05e21ae27e | 267 | } CONTROL_Type; |
| emilmont | 79:0c05e21ae27e | 268 | |
| emilmont | 79:0c05e21ae27e | 269 | /*@} end of group CMSIS_CORE */ |
| emilmont | 79:0c05e21ae27e | 270 | |
| emilmont | 79:0c05e21ae27e | 271 | |
| emilmont | 79:0c05e21ae27e | 272 | /** \ingroup CMSIS_core_register |
| emilmont | 79:0c05e21ae27e | 273 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
| emilmont | 79:0c05e21ae27e | 274 | \brief Type definitions for the NVIC Registers |
| emilmont | 79:0c05e21ae27e | 275 | @{ |
| emilmont | 79:0c05e21ae27e | 276 | */ |
| emilmont | 79:0c05e21ae27e | 277 | |
| emilmont | 79:0c05e21ae27e | 278 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
| emilmont | 79:0c05e21ae27e | 279 | */ |
| emilmont | 79:0c05e21ae27e | 280 | typedef struct |
| emilmont | 79:0c05e21ae27e | 281 | { |
| emilmont | 79:0c05e21ae27e | 282 | __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
| emilmont | 79:0c05e21ae27e | 283 | uint32_t RESERVED0[31]; |
| emilmont | 79:0c05e21ae27e | 284 | __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
| emilmont | 79:0c05e21ae27e | 285 | uint32_t RSERVED1[31]; |
| emilmont | 79:0c05e21ae27e | 286 | __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
| emilmont | 79:0c05e21ae27e | 287 | uint32_t RESERVED2[31]; |
| emilmont | 79:0c05e21ae27e | 288 | __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
| emilmont | 79:0c05e21ae27e | 289 | uint32_t RESERVED3[31]; |
| emilmont | 79:0c05e21ae27e | 290 | uint32_t RESERVED4[64]; |
| emilmont | 79:0c05e21ae27e | 291 | __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
| emilmont | 79:0c05e21ae27e | 292 | } NVIC_Type; |
| emilmont | 79:0c05e21ae27e | 293 | |
| emilmont | 79:0c05e21ae27e | 294 | /*@} end of group CMSIS_NVIC */ |
| emilmont | 79:0c05e21ae27e | 295 | |
| emilmont | 79:0c05e21ae27e | 296 | |
| emilmont | 79:0c05e21ae27e | 297 | /** \ingroup CMSIS_core_register |
| emilmont | 79:0c05e21ae27e | 298 | \defgroup CMSIS_SCB System Control Block (SCB) |
| emilmont | 79:0c05e21ae27e | 299 | \brief Type definitions for the System Control Block Registers |
| emilmont | 79:0c05e21ae27e | 300 | @{ |
| emilmont | 79:0c05e21ae27e | 301 | */ |
| emilmont | 79:0c05e21ae27e | 302 | |
| emilmont | 79:0c05e21ae27e | 303 | /** \brief Structure type to access the System Control Block (SCB). |
| emilmont | 79:0c05e21ae27e | 304 | */ |
| emilmont | 79:0c05e21ae27e | 305 | typedef struct |
| emilmont | 79:0c05e21ae27e | 306 | { |
| emilmont | 79:0c05e21ae27e | 307 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
| emilmont | 79:0c05e21ae27e | 308 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
| emilmont | 79:0c05e21ae27e | 309 | uint32_t RESERVED0; |
| emilmont | 79:0c05e21ae27e | 310 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
| emilmont | 79:0c05e21ae27e | 311 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
| emilmont | 79:0c05e21ae27e | 312 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
| emilmont | 79:0c05e21ae27e | 313 | uint32_t RESERVED1; |
| emilmont | 79:0c05e21ae27e | 314 | __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
| emilmont | 79:0c05e21ae27e | 315 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
| emilmont | 79:0c05e21ae27e | 316 | } SCB_Type; |
| emilmont | 79:0c05e21ae27e | 317 | |
| emilmont | 79:0c05e21ae27e | 318 | /* SCB CPUID Register Definitions */ |
| emilmont | 79:0c05e21ae27e | 319 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
| emilmont | 79:0c05e21ae27e | 320 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
| emilmont | 79:0c05e21ae27e | 321 | |
| emilmont | 79:0c05e21ae27e | 322 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
| emilmont | 79:0c05e21ae27e | 323 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
| emilmont | 79:0c05e21ae27e | 324 | |
| emilmont | 79:0c05e21ae27e | 325 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
| emilmont | 79:0c05e21ae27e | 326 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
| emilmont | 79:0c05e21ae27e | 327 | |
| emilmont | 79:0c05e21ae27e | 328 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
| emilmont | 79:0c05e21ae27e | 329 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
| emilmont | 79:0c05e21ae27e | 330 | |
| emilmont | 79:0c05e21ae27e | 331 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
| emilmont | 79:0c05e21ae27e | 332 | #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ |
| emilmont | 79:0c05e21ae27e | 333 | |
| emilmont | 79:0c05e21ae27e | 334 | /* SCB Interrupt Control State Register Definitions */ |
| emilmont | 79:0c05e21ae27e | 335 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
| emilmont | 79:0c05e21ae27e | 336 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
| emilmont | 79:0c05e21ae27e | 337 | |
| emilmont | 79:0c05e21ae27e | 338 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
| emilmont | 79:0c05e21ae27e | 339 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
| emilmont | 79:0c05e21ae27e | 340 | |
| emilmont | 79:0c05e21ae27e | 341 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
| emilmont | 79:0c05e21ae27e | 342 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
| emilmont | 79:0c05e21ae27e | 343 | |
| emilmont | 79:0c05e21ae27e | 344 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
| emilmont | 79:0c05e21ae27e | 345 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
| emilmont | 79:0c05e21ae27e | 346 | |
| emilmont | 79:0c05e21ae27e | 347 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
| emilmont | 79:0c05e21ae27e | 348 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
| emilmont | 79:0c05e21ae27e | 349 | |
| emilmont | 79:0c05e21ae27e | 350 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
| emilmont | 79:0c05e21ae27e | 351 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
| emilmont | 79:0c05e21ae27e | 352 | |
| emilmont | 79:0c05e21ae27e | 353 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
| emilmont | 79:0c05e21ae27e | 354 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
| emilmont | 79:0c05e21ae27e | 355 | |
| emilmont | 79:0c05e21ae27e | 356 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
| emilmont | 79:0c05e21ae27e | 357 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
| emilmont | 79:0c05e21ae27e | 358 | |
| emilmont | 79:0c05e21ae27e | 359 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
| emilmont | 79:0c05e21ae27e | 360 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ |
| emilmont | 79:0c05e21ae27e | 361 | |
| emilmont | 79:0c05e21ae27e | 362 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
| emilmont | 79:0c05e21ae27e | 363 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
| emilmont | 79:0c05e21ae27e | 364 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
| emilmont | 79:0c05e21ae27e | 365 | |
| emilmont | 79:0c05e21ae27e | 366 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
| emilmont | 79:0c05e21ae27e | 367 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
| emilmont | 79:0c05e21ae27e | 368 | |
| emilmont | 79:0c05e21ae27e | 369 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
| emilmont | 79:0c05e21ae27e | 370 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
| emilmont | 79:0c05e21ae27e | 371 | |
| emilmont | 79:0c05e21ae27e | 372 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
| emilmont | 79:0c05e21ae27e | 373 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
| emilmont | 79:0c05e21ae27e | 374 | |
| emilmont | 79:0c05e21ae27e | 375 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
| emilmont | 79:0c05e21ae27e | 376 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
| emilmont | 79:0c05e21ae27e | 377 | |
| emilmont | 79:0c05e21ae27e | 378 | /* SCB System Control Register Definitions */ |
| emilmont | 79:0c05e21ae27e | 379 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
| emilmont | 79:0c05e21ae27e | 380 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
| emilmont | 79:0c05e21ae27e | 381 | |
| emilmont | 79:0c05e21ae27e | 382 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
| emilmont | 79:0c05e21ae27e | 383 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
| emilmont | 79:0c05e21ae27e | 384 | |
| emilmont | 79:0c05e21ae27e | 385 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
| emilmont | 79:0c05e21ae27e | 386 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
| emilmont | 79:0c05e21ae27e | 387 | |
| emilmont | 79:0c05e21ae27e | 388 | /* SCB Configuration Control Register Definitions */ |
| emilmont | 79:0c05e21ae27e | 389 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
| emilmont | 79:0c05e21ae27e | 390 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
| emilmont | 79:0c05e21ae27e | 391 | |
| emilmont | 79:0c05e21ae27e | 392 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
| emilmont | 79:0c05e21ae27e | 393 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
| emilmont | 79:0c05e21ae27e | 394 | |
| emilmont | 79:0c05e21ae27e | 395 | /* SCB System Handler Control and State Register Definitions */ |
| emilmont | 79:0c05e21ae27e | 396 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
| emilmont | 79:0c05e21ae27e | 397 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
| emilmont | 79:0c05e21ae27e | 398 | |
| emilmont | 79:0c05e21ae27e | 399 | /*@} end of group CMSIS_SCB */ |
| emilmont | 79:0c05e21ae27e | 400 | |
| emilmont | 79:0c05e21ae27e | 401 | |
| emilmont | 79:0c05e21ae27e | 402 | /** \ingroup CMSIS_core_register |
| emilmont | 79:0c05e21ae27e | 403 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
| emilmont | 79:0c05e21ae27e | 404 | \brief Type definitions for the System Timer Registers. |
| emilmont | 79:0c05e21ae27e | 405 | @{ |
| emilmont | 79:0c05e21ae27e | 406 | */ |
| emilmont | 79:0c05e21ae27e | 407 | |
| emilmont | 79:0c05e21ae27e | 408 | /** \brief Structure type to access the System Timer (SysTick). |
| emilmont | 79:0c05e21ae27e | 409 | */ |
| emilmont | 79:0c05e21ae27e | 410 | typedef struct |
| emilmont | 79:0c05e21ae27e | 411 | { |
| emilmont | 79:0c05e21ae27e | 412 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
| emilmont | 79:0c05e21ae27e | 413 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
| emilmont | 79:0c05e21ae27e | 414 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
| emilmont | 79:0c05e21ae27e | 415 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
| emilmont | 79:0c05e21ae27e | 416 | } SysTick_Type; |
| emilmont | 79:0c05e21ae27e | 417 | |
| emilmont | 79:0c05e21ae27e | 418 | /* SysTick Control / Status Register Definitions */ |
| emilmont | 79:0c05e21ae27e | 419 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
| emilmont | 79:0c05e21ae27e | 420 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
| emilmont | 79:0c05e21ae27e | 421 | |
| emilmont | 79:0c05e21ae27e | 422 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
| emilmont | 79:0c05e21ae27e | 423 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
| emilmont | 79:0c05e21ae27e | 424 | |
| emilmont | 79:0c05e21ae27e | 425 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
| emilmont | 79:0c05e21ae27e | 426 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
| emilmont | 79:0c05e21ae27e | 427 | |
| emilmont | 79:0c05e21ae27e | 428 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
| emilmont | 79:0c05e21ae27e | 429 | #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ |
| emilmont | 79:0c05e21ae27e | 430 | |
| emilmont | 79:0c05e21ae27e | 431 | /* SysTick Reload Register Definitions */ |
| emilmont | 79:0c05e21ae27e | 432 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
| emilmont | 79:0c05e21ae27e | 433 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ |
| emilmont | 79:0c05e21ae27e | 434 | |
| emilmont | 79:0c05e21ae27e | 435 | /* SysTick Current Register Definitions */ |
| emilmont | 79:0c05e21ae27e | 436 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
| emilmont | 79:0c05e21ae27e | 437 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ |
| emilmont | 79:0c05e21ae27e | 438 | |
| emilmont | 79:0c05e21ae27e | 439 | /* SysTick Calibration Register Definitions */ |
| emilmont | 79:0c05e21ae27e | 440 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
| emilmont | 79:0c05e21ae27e | 441 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
| emilmont | 79:0c05e21ae27e | 442 | |
| emilmont | 79:0c05e21ae27e | 443 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
| emilmont | 79:0c05e21ae27e | 444 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
| emilmont | 79:0c05e21ae27e | 445 | |
| emilmont | 79:0c05e21ae27e | 446 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
| emilmont | 79:0c05e21ae27e | 447 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ |
| emilmont | 79:0c05e21ae27e | 448 | |
| emilmont | 79:0c05e21ae27e | 449 | /*@} end of group CMSIS_SysTick */ |
| emilmont | 79:0c05e21ae27e | 450 | |
| emilmont | 79:0c05e21ae27e | 451 | |
| emilmont | 79:0c05e21ae27e | 452 | /** \ingroup CMSIS_core_register |
| emilmont | 79:0c05e21ae27e | 453 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
| emilmont | 79:0c05e21ae27e | 454 | \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) |
| emilmont | 79:0c05e21ae27e | 455 | are only accessible over DAP and not via processor. Therefore |
| emilmont | 79:0c05e21ae27e | 456 | they are not covered by the Cortex-M0 header file. |
| emilmont | 79:0c05e21ae27e | 457 | @{ |
| emilmont | 79:0c05e21ae27e | 458 | */ |
| emilmont | 79:0c05e21ae27e | 459 | /*@} end of group CMSIS_CoreDebug */ |
| emilmont | 79:0c05e21ae27e | 460 | |
| emilmont | 79:0c05e21ae27e | 461 | |
| emilmont | 79:0c05e21ae27e | 462 | /** \ingroup CMSIS_core_register |
| emilmont | 79:0c05e21ae27e | 463 | \defgroup CMSIS_core_base Core Definitions |
| emilmont | 79:0c05e21ae27e | 464 | \brief Definitions for base addresses, unions, and structures. |
| emilmont | 79:0c05e21ae27e | 465 | @{ |
| emilmont | 79:0c05e21ae27e | 466 | */ |
| emilmont | 79:0c05e21ae27e | 467 | |
| emilmont | 79:0c05e21ae27e | 468 | /* Memory mapping of Cortex-M0 Hardware */ |
| emilmont | 79:0c05e21ae27e | 469 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
| emilmont | 79:0c05e21ae27e | 470 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
| emilmont | 79:0c05e21ae27e | 471 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
| emilmont | 79:0c05e21ae27e | 472 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
| emilmont | 79:0c05e21ae27e | 473 | |
| emilmont | 79:0c05e21ae27e | 474 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
| emilmont | 79:0c05e21ae27e | 475 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
| emilmont | 79:0c05e21ae27e | 476 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
| emilmont | 79:0c05e21ae27e | 477 | |
| emilmont | 79:0c05e21ae27e | 478 | |
| emilmont | 79:0c05e21ae27e | 479 | /*@} */ |
| emilmont | 79:0c05e21ae27e | 480 | |
| emilmont | 79:0c05e21ae27e | 481 | |
| emilmont | 79:0c05e21ae27e | 482 | |
| emilmont | 79:0c05e21ae27e | 483 | /******************************************************************************* |
| emilmont | 79:0c05e21ae27e | 484 | * Hardware Abstraction Layer |
| emilmont | 79:0c05e21ae27e | 485 | Core Function Interface contains: |
| emilmont | 79:0c05e21ae27e | 486 | - Core NVIC Functions |
| emilmont | 79:0c05e21ae27e | 487 | - Core SysTick Functions |
| emilmont | 79:0c05e21ae27e | 488 | - Core Register Access Functions |
| emilmont | 79:0c05e21ae27e | 489 | ******************************************************************************/ |
| emilmont | 79:0c05e21ae27e | 490 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
| emilmont | 79:0c05e21ae27e | 491 | */ |
| emilmont | 79:0c05e21ae27e | 492 | |
| emilmont | 79:0c05e21ae27e | 493 | |
| emilmont | 79:0c05e21ae27e | 494 | |
| emilmont | 79:0c05e21ae27e | 495 | /* ########################## NVIC functions #################################### */ |
| emilmont | 79:0c05e21ae27e | 496 | /** \ingroup CMSIS_Core_FunctionInterface |
| emilmont | 79:0c05e21ae27e | 497 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
| emilmont | 79:0c05e21ae27e | 498 | \brief Functions that manage interrupts and exceptions via the NVIC. |
| emilmont | 79:0c05e21ae27e | 499 | @{ |
| emilmont | 79:0c05e21ae27e | 500 | */ |
| emilmont | 79:0c05e21ae27e | 501 | |
| emilmont | 79:0c05e21ae27e | 502 | /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
| emilmont | 79:0c05e21ae27e | 503 | /* The following MACROS handle generation of the register offset and byte masks */ |
| emilmont | 79:0c05e21ae27e | 504 | #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) |
| emilmont | 79:0c05e21ae27e | 505 | #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) |
| emilmont | 79:0c05e21ae27e | 506 | #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) |
| emilmont | 79:0c05e21ae27e | 507 | |
| emilmont | 79:0c05e21ae27e | 508 | |
| emilmont | 79:0c05e21ae27e | 509 | /** \brief Enable External Interrupt |
| emilmont | 79:0c05e21ae27e | 510 | |
| emilmont | 79:0c05e21ae27e | 511 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
| emilmont | 79:0c05e21ae27e | 512 | |
| emilmont | 79:0c05e21ae27e | 513 | \param [in] IRQn External interrupt number. Value cannot be negative. |
| emilmont | 79:0c05e21ae27e | 514 | */ |
| emilmont | 79:0c05e21ae27e | 515 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
| emilmont | 79:0c05e21ae27e | 516 | { |
| emilmont | 79:0c05e21ae27e | 517 | NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); |
| emilmont | 79:0c05e21ae27e | 518 | } |
| emilmont | 79:0c05e21ae27e | 519 | |
| emilmont | 79:0c05e21ae27e | 520 | |
| emilmont | 79:0c05e21ae27e | 521 | /** \brief Disable External Interrupt |
| emilmont | 79:0c05e21ae27e | 522 | |
| emilmont | 79:0c05e21ae27e | 523 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
| emilmont | 79:0c05e21ae27e | 524 | |
| emilmont | 79:0c05e21ae27e | 525 | \param [in] IRQn External interrupt number. Value cannot be negative. |
| emilmont | 79:0c05e21ae27e | 526 | */ |
| emilmont | 79:0c05e21ae27e | 527 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
| emilmont | 79:0c05e21ae27e | 528 | { |
| emilmont | 79:0c05e21ae27e | 529 | NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); |
| emilmont | 79:0c05e21ae27e | 530 | } |
| emilmont | 79:0c05e21ae27e | 531 | |
| emilmont | 79:0c05e21ae27e | 532 | |
| emilmont | 79:0c05e21ae27e | 533 | /** \brief Get Pending Interrupt |
| emilmont | 79:0c05e21ae27e | 534 | |
| emilmont | 79:0c05e21ae27e | 535 | The function reads the pending register in the NVIC and returns the pending bit |
| emilmont | 79:0c05e21ae27e | 536 | for the specified interrupt. |
| emilmont | 79:0c05e21ae27e | 537 | |
| emilmont | 79:0c05e21ae27e | 538 | \param [in] IRQn Interrupt number. |
| emilmont | 79:0c05e21ae27e | 539 | |
| emilmont | 79:0c05e21ae27e | 540 | \return 0 Interrupt status is not pending. |
| emilmont | 79:0c05e21ae27e | 541 | \return 1 Interrupt status is pending. |
| emilmont | 79:0c05e21ae27e | 542 | */ |
| emilmont | 79:0c05e21ae27e | 543 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
| emilmont | 79:0c05e21ae27e | 544 | { |
| emilmont | 79:0c05e21ae27e | 545 | return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); |
| emilmont | 79:0c05e21ae27e | 546 | } |
| emilmont | 79:0c05e21ae27e | 547 | |
| emilmont | 79:0c05e21ae27e | 548 | |
| emilmont | 79:0c05e21ae27e | 549 | /** \brief Set Pending Interrupt |
| emilmont | 79:0c05e21ae27e | 550 | |
| emilmont | 79:0c05e21ae27e | 551 | The function sets the pending bit of an external interrupt. |
| emilmont | 79:0c05e21ae27e | 552 | |
| emilmont | 79:0c05e21ae27e | 553 | \param [in] IRQn Interrupt number. Value cannot be negative. |
| emilmont | 79:0c05e21ae27e | 554 | */ |
| emilmont | 79:0c05e21ae27e | 555 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
| emilmont | 79:0c05e21ae27e | 556 | { |
| emilmont | 79:0c05e21ae27e | 557 | NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); |
| emilmont | 79:0c05e21ae27e | 558 | } |
| emilmont | 79:0c05e21ae27e | 559 | |
| emilmont | 79:0c05e21ae27e | 560 | |
| emilmont | 79:0c05e21ae27e | 561 | /** \brief Clear Pending Interrupt |
| emilmont | 79:0c05e21ae27e | 562 | |
| emilmont | 79:0c05e21ae27e | 563 | The function clears the pending bit of an external interrupt. |
| emilmont | 79:0c05e21ae27e | 564 | |
| emilmont | 79:0c05e21ae27e | 565 | \param [in] IRQn External interrupt number. Value cannot be negative. |
| emilmont | 79:0c05e21ae27e | 566 | */ |
| emilmont | 79:0c05e21ae27e | 567 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
| emilmont | 79:0c05e21ae27e | 568 | { |
| emilmont | 79:0c05e21ae27e | 569 | NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ |
| emilmont | 79:0c05e21ae27e | 570 | } |
| emilmont | 79:0c05e21ae27e | 571 | |
| emilmont | 79:0c05e21ae27e | 572 | |
| emilmont | 79:0c05e21ae27e | 573 | /** \brief Set Interrupt Priority |
| emilmont | 79:0c05e21ae27e | 574 | |
| emilmont | 79:0c05e21ae27e | 575 | The function sets the priority of an interrupt. |
| emilmont | 79:0c05e21ae27e | 576 | |
| emilmont | 79:0c05e21ae27e | 577 | \note The priority cannot be set for every core interrupt. |
| emilmont | 79:0c05e21ae27e | 578 | |
| emilmont | 79:0c05e21ae27e | 579 | \param [in] IRQn Interrupt number. |
| emilmont | 79:0c05e21ae27e | 580 | \param [in] priority Priority to set. |
| emilmont | 79:0c05e21ae27e | 581 | */ |
| emilmont | 79:0c05e21ae27e | 582 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
| emilmont | 79:0c05e21ae27e | 583 | { |
| emilmont | 79:0c05e21ae27e | 584 | if(IRQn < 0) { |
| emilmont | 79:0c05e21ae27e | 585 | SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | |
| emilmont | 79:0c05e21ae27e | 586 | (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } |
| emilmont | 79:0c05e21ae27e | 587 | else { |
| emilmont | 79:0c05e21ae27e | 588 | NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | |
| emilmont | 79:0c05e21ae27e | 589 | (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } |
| emilmont | 79:0c05e21ae27e | 590 | } |
| emilmont | 79:0c05e21ae27e | 591 | |
| emilmont | 79:0c05e21ae27e | 592 | |
| emilmont | 79:0c05e21ae27e | 593 | /** \brief Get Interrupt Priority |
| emilmont | 79:0c05e21ae27e | 594 | |
| emilmont | 79:0c05e21ae27e | 595 | The function reads the priority of an interrupt. The interrupt |
| emilmont | 79:0c05e21ae27e | 596 | number can be positive to specify an external (device specific) |
| emilmont | 79:0c05e21ae27e | 597 | interrupt, or negative to specify an internal (core) interrupt. |
| emilmont | 79:0c05e21ae27e | 598 | |
| emilmont | 79:0c05e21ae27e | 599 | |
| emilmont | 79:0c05e21ae27e | 600 | \param [in] IRQn Interrupt number. |
| emilmont | 79:0c05e21ae27e | 601 | \return Interrupt Priority. Value is aligned automatically to the implemented |
| emilmont | 79:0c05e21ae27e | 602 | priority bits of the microcontroller. |
| emilmont | 79:0c05e21ae27e | 603 | */ |
| emilmont | 79:0c05e21ae27e | 604 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
| emilmont | 79:0c05e21ae27e | 605 | { |
| emilmont | 79:0c05e21ae27e | 606 | |
| emilmont | 79:0c05e21ae27e | 607 | if(IRQn < 0) { |
| emilmont | 79:0c05e21ae27e | 608 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ |
| emilmont | 79:0c05e21ae27e | 609 | else { |
| emilmont | 79:0c05e21ae27e | 610 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ |
| emilmont | 79:0c05e21ae27e | 611 | } |
| emilmont | 79:0c05e21ae27e | 612 | |
| emilmont | 79:0c05e21ae27e | 613 | |
| emilmont | 79:0c05e21ae27e | 614 | /** \brief System Reset |
| emilmont | 79:0c05e21ae27e | 615 | |
| emilmont | 79:0c05e21ae27e | 616 | The function initiates a system reset request to reset the MCU. |
| emilmont | 79:0c05e21ae27e | 617 | */ |
| emilmont | 79:0c05e21ae27e | 618 | __STATIC_INLINE void NVIC_SystemReset(void) |
| emilmont | 79:0c05e21ae27e | 619 | { |
| emilmont | 79:0c05e21ae27e | 620 | __DSB(); /* Ensure all outstanding memory accesses included |
| emilmont | 79:0c05e21ae27e | 621 | buffered write are completed before reset */ |
| emilmont | 79:0c05e21ae27e | 622 | SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
| emilmont | 79:0c05e21ae27e | 623 | SCB_AIRCR_SYSRESETREQ_Msk); |
| emilmont | 79:0c05e21ae27e | 624 | __DSB(); /* Ensure completion of memory access */ |
| emilmont | 79:0c05e21ae27e | 625 | while(1); /* wait until reset */ |
| emilmont | 79:0c05e21ae27e | 626 | } |
| emilmont | 79:0c05e21ae27e | 627 | |
| emilmont | 79:0c05e21ae27e | 628 | /*@} end of CMSIS_Core_NVICFunctions */ |
| emilmont | 79:0c05e21ae27e | 629 | |
| emilmont | 79:0c05e21ae27e | 630 | |
| emilmont | 79:0c05e21ae27e | 631 | |
| emilmont | 79:0c05e21ae27e | 632 | /* ################################## SysTick function ############################################ */ |
| emilmont | 79:0c05e21ae27e | 633 | /** \ingroup CMSIS_Core_FunctionInterface |
| emilmont | 79:0c05e21ae27e | 634 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
| emilmont | 79:0c05e21ae27e | 635 | \brief Functions that configure the System. |
| emilmont | 79:0c05e21ae27e | 636 | @{ |
| emilmont | 79:0c05e21ae27e | 637 | */ |
| emilmont | 79:0c05e21ae27e | 638 | |
| emilmont | 79:0c05e21ae27e | 639 | #if (__Vendor_SysTickConfig == 0) |
| emilmont | 79:0c05e21ae27e | 640 | |
| emilmont | 79:0c05e21ae27e | 641 | /** \brief System Tick Configuration |
| emilmont | 79:0c05e21ae27e | 642 | |
| emilmont | 79:0c05e21ae27e | 643 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
| emilmont | 79:0c05e21ae27e | 644 | Counter is in free running mode to generate periodic interrupts. |
| emilmont | 79:0c05e21ae27e | 645 | |
| emilmont | 79:0c05e21ae27e | 646 | \param [in] ticks Number of ticks between two interrupts. |
| emilmont | 79:0c05e21ae27e | 647 | |
| emilmont | 79:0c05e21ae27e | 648 | \return 0 Function succeeded. |
| emilmont | 79:0c05e21ae27e | 649 | \return 1 Function failed. |
| emilmont | 79:0c05e21ae27e | 650 | |
| emilmont | 79:0c05e21ae27e | 651 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
| emilmont | 79:0c05e21ae27e | 652 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
| emilmont | 79:0c05e21ae27e | 653 | must contain a vendor-specific implementation of this function. |
| emilmont | 79:0c05e21ae27e | 654 | |
| emilmont | 79:0c05e21ae27e | 655 | */ |
| emilmont | 79:0c05e21ae27e | 656 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
| emilmont | 79:0c05e21ae27e | 657 | { |
| emilmont | 79:0c05e21ae27e | 658 | if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ |
| emilmont | 79:0c05e21ae27e | 659 | |
| emilmont | 79:0c05e21ae27e | 660 | SysTick->LOAD = ticks - 1; /* set reload register */ |
| emilmont | 79:0c05e21ae27e | 661 | NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ |
| emilmont | 79:0c05e21ae27e | 662 | SysTick->VAL = 0; /* Load the SysTick Counter Value */ |
| emilmont | 79:0c05e21ae27e | 663 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
| emilmont | 79:0c05e21ae27e | 664 | SysTick_CTRL_TICKINT_Msk | |
| emilmont | 79:0c05e21ae27e | 665 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
| emilmont | 79:0c05e21ae27e | 666 | return (0); /* Function successful */ |
| emilmont | 79:0c05e21ae27e | 667 | } |
| emilmont | 79:0c05e21ae27e | 668 | |
| emilmont | 79:0c05e21ae27e | 669 | #endif |
| emilmont | 79:0c05e21ae27e | 670 | |
| emilmont | 79:0c05e21ae27e | 671 | /*@} end of CMSIS_Core_SysTickFunctions */ |
| emilmont | 79:0c05e21ae27e | 672 | |
| emilmont | 79:0c05e21ae27e | 673 | |
| emilmont | 79:0c05e21ae27e | 674 | |
| emilmont | 79:0c05e21ae27e | 675 | |
| emilmont | 79:0c05e21ae27e | 676 | #endif /* __CORE_CM0_H_DEPENDANT */ |
| emilmont | 79:0c05e21ae27e | 677 | |
| emilmont | 79:0c05e21ae27e | 678 | #endif /* __CMSIS_GENERIC */ |
| emilmont | 79:0c05e21ae27e | 679 | |
| emilmont | 79:0c05e21ae27e | 680 | #ifdef __cplusplus |
| emilmont | 79:0c05e21ae27e | 681 | } |
| emilmont | 79:0c05e21ae27e | 682 | #endif |