Eric Pena
AD7768-1 MBED IIO Application Example
Dependencies: platform_drivers
app/ad77681.h@2:eb624ef78449, 2021-09-24 (annotated)
- Committer:
- epena
- Date:
- Fri Sep 24 19:07:29 2021 +0800
- Revision:
- 2:eb624ef78449
- Parent:
- 1:c0429edee15b
Deleting the redefinition of data_capture_ops
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| epena | 1:c0429edee15b | 1 | /***************************************************************************//** |
| epena | 1:c0429edee15b | 2 | * @file ad77681.h |
| epena | 1:c0429edee15b | 3 | * @brief Header file of the AD7768-1 Driver. |
| epena | 1:c0429edee15b | 4 | * @author SPopa (stefan.popa@analog.com) |
| epena | 1:c0429edee15b | 5 | ******************************************************************************** |
| epena | 1:c0429edee15b | 6 | * Copyright 2017(c) Analog Devices, Inc. |
| epena | 1:c0429edee15b | 7 | * |
| epena | 1:c0429edee15b | 8 | * All rights reserved. |
| epena | 1:c0429edee15b | 9 | * |
| epena | 1:c0429edee15b | 10 | * Redistribution and use in source and binary forms, with or without |
| epena | 1:c0429edee15b | 11 | * modification, are permitted provided that the following conditions are met: |
| epena | 1:c0429edee15b | 12 | * - Redistributions of source code must retain the above copyright |
| epena | 1:c0429edee15b | 13 | * notice, this list of conditions and the following disclaimer. |
| epena | 1:c0429edee15b | 14 | * - Redistributions in binary form must reproduce the above copyright |
| epena | 1:c0429edee15b | 15 | * notice, this list of conditions and the following disclaimer in |
| epena | 1:c0429edee15b | 16 | * the documentation and/or other materials provided with the |
| epena | 1:c0429edee15b | 17 | * distribution. |
| epena | 1:c0429edee15b | 18 | * - Neither the name of Analog Devices, Inc. nor the names of its |
| epena | 1:c0429edee15b | 19 | * contributors may be used to endorse or promote products derived |
| epena | 1:c0429edee15b | 20 | * from this software without specific prior written permission. |
| epena | 1:c0429edee15b | 21 | * - The use of this software may or may not infringe the patent rights |
| epena | 1:c0429edee15b | 22 | * of one or more patent holders. This license does not release you |
| epena | 1:c0429edee15b | 23 | * from the requirement that you obtain separate licenses from these |
| epena | 1:c0429edee15b | 24 | * patent holders to use this software. |
| epena | 1:c0429edee15b | 25 | * - Use of the software either in source or binary form, must be run |
| epena | 1:c0429edee15b | 26 | * on or directly connected to an Analog Devices Inc. component. |
| epena | 1:c0429edee15b | 27 | * |
| epena | 1:c0429edee15b | 28 | * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR |
| epena | 1:c0429edee15b | 29 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, |
| epena | 1:c0429edee15b | 30 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| epena | 1:c0429edee15b | 31 | * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, |
| epena | 1:c0429edee15b | 32 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| epena | 1:c0429edee15b | 33 | * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR |
| epena | 1:c0429edee15b | 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| epena | 1:c0429edee15b | 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| epena | 1:c0429edee15b | 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| epena | 1:c0429edee15b | 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| epena | 1:c0429edee15b | 38 | *******************************************************************************/ |
| epena | 1:c0429edee15b | 39 | |
| epena | 1:c0429edee15b | 40 | #ifndef SRC_AD77681_H_ |
| epena | 1:c0429edee15b | 41 | #define SRC_AD77681_H_ |
| epena | 1:c0429edee15b | 42 | |
| epena | 1:c0429edee15b | 43 | //#include "spi_engine.h" |
| epena | 1:c0429edee15b | 44 | |
| epena | 1:c0429edee15b | 45 | #include "spi.h" |
| epena | 1:c0429edee15b | 46 | #include <stdbool.h> |
| epena | 1:c0429edee15b | 47 | |
| epena | 1:c0429edee15b | 48 | /******************************************************************************/ |
| epena | 1:c0429edee15b | 49 | /********************** Macros and Constants Definitions **********************/ |
| epena | 1:c0429edee15b | 50 | /******************************************************************************/ |
| epena | 1:c0429edee15b | 51 | #define AD77681_REG_CHIP_TYPE 0x3 |
| epena | 1:c0429edee15b | 52 | #define AD77681_REG_PROD_ID_L 0x4 |
| epena | 1:c0429edee15b | 53 | #define AD77681_REG_PROD_ID_H 0x5 |
| epena | 1:c0429edee15b | 54 | #define AD77681_REG_CHIP_GRADE 0x6 |
| epena | 1:c0429edee15b | 55 | #define AD77681_REG_SCRATCH_PAD 0x0A |
| epena | 1:c0429edee15b | 56 | #define AD77681_REG_VENDOR_L 0x0C |
| epena | 1:c0429edee15b | 57 | #define AD77681_REG_VENDOR_H 0x0D |
| epena | 1:c0429edee15b | 58 | #define AD77681_REG_INTERFACE_FORMAT 0x14 |
| epena | 1:c0429edee15b | 59 | #define AD77681_REG_POWER_CLOCK 0x15 |
| epena | 1:c0429edee15b | 60 | #define AD77681_REG_ANALOG 0x16 |
| epena | 1:c0429edee15b | 61 | #define AD77681_REG_ANALOG2 0x17 |
| epena | 1:c0429edee15b | 62 | #define AD77681_REG_CONVERSION 0x18 |
| epena | 1:c0429edee15b | 63 | #define AD77681_REG_DIGITAL_FILTER 0x19 |
| epena | 1:c0429edee15b | 64 | #define AD77681_REG_SINC3_DEC_RATE_MSB 0x1A |
| epena | 1:c0429edee15b | 65 | #define AD77681_REG_SINC3_DEC_RATE_LSB 0x1B |
| epena | 1:c0429edee15b | 66 | #define AD77681_REG_DUTY_CYCLE_RATIO 0x1C |
| epena | 1:c0429edee15b | 67 | #define AD77681_REG_SYNC_RESET 0x1D |
| epena | 1:c0429edee15b | 68 | #define AD77681_REG_GPIO_CONTROL 0x1E |
| epena | 1:c0429edee15b | 69 | #define AD77681_REG_GPIO_WRITE 0x1F |
| epena | 1:c0429edee15b | 70 | #define AD77681_REG_GPIO_READ 0x20 |
| epena | 1:c0429edee15b | 71 | #define AD77681_REG_OFFSET_HI 0x21 |
| epena | 1:c0429edee15b | 72 | #define AD77681_REG_OFFSET_MID 0x22 |
| epena | 1:c0429edee15b | 73 | #define AD77681_REG_OFFSET_LO 0x23 |
| epena | 1:c0429edee15b | 74 | #define AD77681_REG_GAIN_HI 0x24 |
| epena | 1:c0429edee15b | 75 | #define AD77681_REG_GAIN_MID 0x25 |
| epena | 1:c0429edee15b | 76 | #define AD77681_REG_GAIN_LO 0x26 |
| epena | 1:c0429edee15b | 77 | #define AD77681_REG_SPI_DIAG_ENABLE 0x28 |
| epena | 1:c0429edee15b | 78 | #define AD77681_REG_ADC_DIAG_ENABLE 0x29 |
| epena | 1:c0429edee15b | 79 | #define AD77681_REG_DIG_DIAG_ENABLE 0x2A |
| epena | 1:c0429edee15b | 80 | #define AD77681_REG_ADC_DATA 0x2C |
| epena | 1:c0429edee15b | 81 | #define AD77681_REG_MASTER_STATUS 0x2D |
| epena | 1:c0429edee15b | 82 | #define AD77681_REG_SPI_DIAG_STATUS 0x2E |
| epena | 1:c0429edee15b | 83 | #define AD77681_REG_ADC_DIAG_STATUS 0x2F |
| epena | 1:c0429edee15b | 84 | #define AD77681_REG_DIG_DIAG_STATUS 0x30 |
| epena | 1:c0429edee15b | 85 | #define AD77681_REG_MCLK_COUNTER 0x31 |
| epena | 1:c0429edee15b | 86 | |
| epena | 1:c0429edee15b | 87 | /* AD77681_REG_INTERFACE_FORMAT */ |
| epena | 1:c0429edee15b | 88 | #define AD77681_INTERFACE_CRC_EN_MSK (0x1 << 6) |
| epena | 1:c0429edee15b | 89 | #define AD77681_INTERFACE_CRC_EN(x) (((x) & 0x1) << 6) |
| epena | 1:c0429edee15b | 90 | #define AD77681_INTERFACE_CRC_TYPE_MSK (0x1 << 5) |
| epena | 1:c0429edee15b | 91 | #define AD77681_INTERFACE_CRC_TYPE(x) (((x) & 0x1) << 5) |
| epena | 1:c0429edee15b | 92 | #define AD77681_INTERFACE_STATUS_EN_MSK (0x1 << 4) |
| epena | 1:c0429edee15b | 93 | #define AD77681_INTERFACE_STATUS_EN(x) (((x) & 0x1) << 4) |
| epena | 1:c0429edee15b | 94 | #define AD77681_INTERFACE_CONVLEN_MSK (0x1 << 3) |
| epena | 1:c0429edee15b | 95 | #define AD77681_INTERFACE_CONVLEN(x) (((x) & 0x1) << 3) |
| epena | 1:c0429edee15b | 96 | #define AD77681_INTERFACE_RDY_EN_MSK (0x1 << 2) |
| epena | 1:c0429edee15b | 97 | #define AD77681_INTERFACE_RDY_EN(x) (((x) & 0x1) << 3) |
| epena | 1:c0429edee15b | 98 | #define AD77681_INTERFACE_CONT_READ_MSK (0x1 << 0) |
| epena | 1:c0429edee15b | 99 | #define AD77681_INTERFACE_CONT_READ_EN(x) (((x) & 0x1) << 0) |
| epena | 1:c0429edee15b | 100 | #define AD77681_REG_COEFF_CONTROL 0x32 |
| epena | 1:c0429edee15b | 101 | #define AD77681_REG_COEFF_DATA 0x33 |
| epena | 1:c0429edee15b | 102 | #define AD77681_REG_ACCESS_KEY 0x34 |
| epena | 1:c0429edee15b | 103 | |
| epena | 1:c0429edee15b | 104 | /* AD77681_REG_SCRATCH_PAD*/ |
| epena | 1:c0429edee15b | 105 | #define AD77681_SCRATCHPAD_MSK (0xFF << 0) |
| epena | 1:c0429edee15b | 106 | #define AD77681_SCRATCHPAD(x) (((x) & 0xFF) << 0) |
| epena | 1:c0429edee15b | 107 | |
| epena | 1:c0429edee15b | 108 | /* AD77681_REG_POWER_CLOCK */ |
| epena | 1:c0429edee15b | 109 | #define AD77681_POWER_CLK_PWRMODE_MSK 0x3 |
| epena | 1:c0429edee15b | 110 | #define AD77681_POWER_CLK_PWRMODE(x) (((x) & 0x3) << 0) |
| epena | 1:c0429edee15b | 111 | #define AD77681_POWER_CLK_MOD_OUT_MSK (0x1 << 2) |
| epena | 1:c0429edee15b | 112 | #define AD77681_POWER_CLK_MOD_OUT(x) (((x) & 0x1) << 2) |
| epena | 1:c0429edee15b | 113 | #define AD77681_POWER_CLK_POWER_DOWN 0x08 |
| epena | 1:c0429edee15b | 114 | #define AD77681_POWER_CLK_MCLK_DIV_MSK (0x3 << 4) |
| epena | 1:c0429edee15b | 115 | #define AD77681_POWER_CLK_MCLK_DIV(x) (((x) & 0x3) << 4) |
| epena | 1:c0429edee15b | 116 | #define AD77681_POWER_CLK_CLOCK_SEL_MSK (0x3 << 6) |
| epena | 1:c0429edee15b | 117 | #define AD77681_POWER_CLK_CLOCK_SEL(x) (((x) & 0x3) << 6) |
| epena | 1:c0429edee15b | 118 | |
| epena | 1:c0429edee15b | 119 | /* AD77681_CONVERSION_REG */ |
| epena | 1:c0429edee15b | 120 | #define AD77681_CONVERSION_DIAG_MUX_MSK (0xF << 4) |
| epena | 1:c0429edee15b | 121 | #define AD77681_CONVERSION_DIAG_MUX_SEL(x) (((x) & 0xF) << 4) |
| epena | 1:c0429edee15b | 122 | #define AD77681_CONVERSION_DIAG_SEL_MSK (0x1 << 3) |
| epena | 1:c0429edee15b | 123 | #define AD77681_CONVERSION_DIAG_SEL(x) (((x) & 0x1) << 3) |
| epena | 1:c0429edee15b | 124 | #define AD77681_CONVERSION_MODE_MSK (0x7 << 0) |
| epena | 1:c0429edee15b | 125 | #define AD77681_CONVERSION_MODE(x) (((x) & 0x7) << 0) |
| epena | 1:c0429edee15b | 126 | |
| epena | 1:c0429edee15b | 127 | /* AD77681_REG_ANALOG */ |
| epena | 1:c0429edee15b | 128 | #define AD77681_ANALOG_REF_BUF_POS_MSK (0x3 << 6) |
| epena | 1:c0429edee15b | 129 | #define AD77681_ANALOG_REF_BUF_POS(x) (((x) & 0x3) << 6) |
| epena | 1:c0429edee15b | 130 | #define AD77681_ANALOG_REF_BUF_NEG_MSK (0x3 << 4) |
| epena | 1:c0429edee15b | 131 | #define AD77681_ANALOG_REF_BUF_NEG(x) (((x) & 0x3) << 4) |
| epena | 1:c0429edee15b | 132 | #define AD77681_ANALOG_AIN_BUF_POS_OFF_MSK (0x1 << 1) |
| epena | 1:c0429edee15b | 133 | #define AD77681_ANALOG_AIN_BUF_POS_OFF(x) (((x) & 0x1) << 1) |
| epena | 1:c0429edee15b | 134 | #define AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK (0x1 << 0) |
| epena | 1:c0429edee15b | 135 | #define AD77681_ANALOG_AIN_BUF_NEG_OFF(x) (((x) & 0x1) << 0) |
| epena | 1:c0429edee15b | 136 | |
| epena | 1:c0429edee15b | 137 | /* AD77681_REG_ANALOG2 */ |
| epena | 1:c0429edee15b | 138 | #define AD77681_ANALOG2_VCM_MSK (0x7 << 0) |
| epena | 1:c0429edee15b | 139 | #define AD77681_ANALOG2_VCM(x) (((x) & 0x7) << 0) |
| epena | 1:c0429edee15b | 140 | |
| epena | 1:c0429edee15b | 141 | /* AD77681_REG_DIGITAL_FILTER */ |
| epena | 1:c0429edee15b | 142 | #define AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK (0x1 << 7) |
| epena | 1:c0429edee15b | 143 | #define AD77681_DIGI_FILTER_60HZ_REJ_EN(x) (((x) & 0x1) << 7) |
| epena | 1:c0429edee15b | 144 | #define AD77681_DIGI_FILTER_FILTER_MSK (0x7 << 4) |
| epena | 1:c0429edee15b | 145 | #define AD77681_DIGI_FILTER_FILTER(x) (((x) & 0x7) << 4) |
| epena | 1:c0429edee15b | 146 | #define AD77681_DIGI_FILTER_DEC_RATE_MSK (0x7 << 0) |
| epena | 1:c0429edee15b | 147 | #define AD77681_DIGI_FILTER_DEC_RATE(x) (((x) & 0x7) << 0) |
| epena | 1:c0429edee15b | 148 | |
| epena | 1:c0429edee15b | 149 | /* AD77681_REG_SINC3_DEC_RATE_MSB */ |
| epena | 1:c0429edee15b | 150 | #define AD77681_SINC3_DEC_RATE_MSB_MSK (0x0F << 0) |
| epena | 1:c0429edee15b | 151 | #define AD77681_SINC3_DEC_RATE_MSB(x) (((x) & 0x0F) << 0) |
| epena | 1:c0429edee15b | 152 | |
| epena | 1:c0429edee15b | 153 | /* AD77681_REG_SINC3_DEC_RATE_LSB */ |
| epena | 1:c0429edee15b | 154 | #define AD77681_SINC3_DEC_RATE_LSB_MSK (0xFF << 0) |
| epena | 1:c0429edee15b | 155 | #define AD77681_SINC3_DEC_RATE_LSB(x) (((x) & 0xFF) << 0) |
| epena | 1:c0429edee15b | 156 | |
| epena | 1:c0429edee15b | 157 | /* AD77681_REG_DUTY_CYCLE_RATIO */ |
| epena | 1:c0429edee15b | 158 | #define AD77681_DC_RATIO_IDLE_TIME_MSK (0xFF << 0) |
| epena | 1:c0429edee15b | 159 | #define AD77681_DC_RATIO_IDLE_TIME(x) (((x) & 0xFF) << 0) |
| epena | 1:c0429edee15b | 160 | |
| epena | 1:c0429edee15b | 161 | /* AD77681_REG_SYNC_RESET */ |
| epena | 1:c0429edee15b | 162 | #define AD77681_SYNC_RST_SPI_STARTB_MSK (0x1 << 7) |
| epena | 1:c0429edee15b | 163 | #define AD77681_SYNC_RST_SPI_STARTB(x) (((x) & 0x1) << 7) |
| epena | 1:c0429edee15b | 164 | #define AD77681_SYNC_RST_SYNCOUT_EDGE_MSK (0x1 << 6) |
| epena | 1:c0429edee15b | 165 | #define AD77681_SYNC_RST_SYNCOUT_EDGE(x) (((x) & 0x1) << 6) |
| epena | 1:c0429edee15b | 166 | #define AD77681_SYNC_RST_GPIO_START_EN_MSK (0x1 << 3) |
| epena | 1:c0429edee15b | 167 | #define AD77681_SYNC_RST_GPIO_START_EN(x) (((x) & 0x1) << 3) |
| epena | 1:c0429edee15b | 168 | #define AD77681_SYNC_RST_SPI_RESET_MSK (0x3 << 0) |
| epena | 1:c0429edee15b | 169 | #define AD77681_SYNC_RST_SPI_RESET(x) (((x) & 0x3) << 0) |
| epena | 1:c0429edee15b | 170 | |
| epena | 1:c0429edee15b | 171 | /* AD77681_REG_GPIO_CONTROL */ |
| epena | 1:c0429edee15b | 172 | #define AD77681_GPIO_CNTRL_UGPIO_EN_MSK (0x1 << 7) |
| epena | 1:c0429edee15b | 173 | #define AD77681_GPIO_CNTRL_UGPIO_EN(x) (((x) & 0x1) << 7) |
| epena | 1:c0429edee15b | 174 | #define AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK (0x1 << 6) |
| epena | 1:c0429edee15b | 175 | #define AD77681_GPIO_CNTRL_GPIO2_OD_EN(x) (((x) & 0x1) << 6) |
| epena | 1:c0429edee15b | 176 | #define AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK (0x1 << 5) |
| epena | 1:c0429edee15b | 177 | #define AD77681_GPIO_CNTRL_GPIO1_OD_EN(x) (((x) & 0x1) << 5) |
| epena | 1:c0429edee15b | 178 | #define AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK (0x1 << 4) |
| epena | 1:c0429edee15b | 179 | #define AD77681_GPIO_CNTRL_GPIO0_OD_EN(x) (((x) & 0x1) << 4) |
| epena | 1:c0429edee15b | 180 | #define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK (0x7 << 4) |
| epena | 1:c0429edee15b | 181 | #define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN(x) (((x) & 0x7) << 4) |
| epena | 1:c0429edee15b | 182 | #define AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK (0x1 << 3) |
| epena | 1:c0429edee15b | 183 | #define AD77681_GPIO_CNTRL_GPIO3_OP_EN(x) (((x) & 0x1) << 3) |
| epena | 1:c0429edee15b | 184 | #define AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK (0x1 << 2) |
| epena | 1:c0429edee15b | 185 | #define AD77681_GPIO_CNTRL_GPIO2_OP_EN(x) (((x) & 0x1) << 2) |
| epena | 1:c0429edee15b | 186 | #define AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK (0x1 << 1) |
| epena | 1:c0429edee15b | 187 | #define AD77681_GPIO_CNTRL_GPIO1_OP_EN(x) (((x) & 0x1) << 1) |
| epena | 1:c0429edee15b | 188 | #define AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK (0x1 << 0) |
| epena | 1:c0429edee15b | 189 | #define AD77681_GPIO_CNTRL_GPIO0_OP_EN(x) (((x) & 0x1) << 0) |
| epena | 1:c0429edee15b | 190 | #define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK (0xF << 0) |
| epena | 1:c0429edee15b | 191 | #define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN(x) (((x) & 0xF) << 0) |
| epena | 1:c0429edee15b | 192 | |
| epena | 1:c0429edee15b | 193 | /* AD77681_REG_GPIO_WRITE */ |
| epena | 1:c0429edee15b | 194 | #define AD77681_GPIO_WRITE_3_MSK (0x1 << 3) |
| epena | 1:c0429edee15b | 195 | #define AD77681_GPIO_WRITE_3(x) (((x) & 0x1) << 3) |
| epena | 1:c0429edee15b | 196 | #define AD77681_GPIO_WRITE_2_MSK (0x1 << 2) |
| epena | 1:c0429edee15b | 197 | #define AD77681_GPIO_WRITE_2(x) (((x) & 0x1) << 2) |
| epena | 1:c0429edee15b | 198 | #define AD77681_GPIO_WRITE_1_MSK (0x1 << 1) |
| epena | 1:c0429edee15b | 199 | #define AD77681_GPIO_WRITE_1(x) (((x) & 0x1) << 1) |
| epena | 1:c0429edee15b | 200 | #define AD77681_GPIO_WRITE_0_MSK (0x1 << 0) |
| epena | 1:c0429edee15b | 201 | #define AD77681_GPIO_WRITE_0(x) (((x) & 0x1) << 0) |
| epena | 1:c0429edee15b | 202 | #define AD77681_GPIO_WRITE_ALL_MSK (0xF << 0) |
| epena | 1:c0429edee15b | 203 | #define AD77681_GPIO_WRITE_ALL(x) (((x) & 0xF)) |
| epena | 1:c0429edee15b | 204 | |
| epena | 1:c0429edee15b | 205 | /* AD77681_REG_GPIO_READ */ |
| epena | 1:c0429edee15b | 206 | #define AD77681_GPIO_READ_3_MSK (0x1 << 3) |
| epena | 1:c0429edee15b | 207 | #define AD77681_GPIO_READ_2_MSK (0x1 << 2) |
| epena | 1:c0429edee15b | 208 | #define AD77681_GPIO_READ_1_MSK (0x1 << 1) |
| epena | 1:c0429edee15b | 209 | #define AD77681_GPIO_READ_0_MSK (0x1 << 0) |
| epena | 1:c0429edee15b | 210 | #define AD77681_GPIO_READ_ALL_MSK (0xF << 0) |
| epena | 1:c0429edee15b | 211 | |
| epena | 1:c0429edee15b | 212 | /* AD77681_REG_OFFSET_HI */ |
| epena | 1:c0429edee15b | 213 | #define AD77681_OFFSET_HI_MSK (0xFF << 0) |
| epena | 1:c0429edee15b | 214 | #define AD77681_OFFSET_HI(x) (((x) & 0xFF) << 0) |
| epena | 1:c0429edee15b | 215 | |
| epena | 1:c0429edee15b | 216 | /* AD77681_REG_OFFSET_MID */ |
| epena | 1:c0429edee15b | 217 | #define AD77681_OFFSET_MID_MSK (0xFF << 0) |
| epena | 1:c0429edee15b | 218 | #define AD77681_OFFSET_MID(x) (((x) & 0xFF) << 0) |
| epena | 1:c0429edee15b | 219 | |
| epena | 1:c0429edee15b | 220 | /* AD77681_REG_OFFSET_LO */ |
| epena | 1:c0429edee15b | 221 | #define AD77681_OFFSET_LO_MSK (0xFF << 0) |
| epena | 1:c0429edee15b | 222 | #define AD77681_OFFSET_LO(x) (((x) & 0xFF) << 0) |
| epena | 1:c0429edee15b | 223 | |
| epena | 1:c0429edee15b | 224 | /* AD77681_REG_GAIN_HI */ |
| epena | 1:c0429edee15b | 225 | #define AD77681_GAIN_HI_MSK (0xFF << 0) |
| epena | 1:c0429edee15b | 226 | #define AD77681_GAIN_HI(x) (((x) & 0xFF) << 0) |
| epena | 1:c0429edee15b | 227 | |
| epena | 1:c0429edee15b | 228 | /* AD77681_REG_GAIN_MID */ |
| epena | 1:c0429edee15b | 229 | #define AD77681_GAIN_MID_MSK (0xFF << 0) |
| epena | 1:c0429edee15b | 230 | #define AD77681_GAIN_MID(x) (((x) & 0xFF) << 0) |
| epena | 1:c0429edee15b | 231 | |
| epena | 1:c0429edee15b | 232 | /* AD77681_REG_GAIN_HI */ |
| epena | 1:c0429edee15b | 233 | #define AD77681_GAIN_LOW_MSK (0xFF << 0) |
| epena | 1:c0429edee15b | 234 | #define AD77681_GAIN_LOW(x) (((x) & 0xFF) << 0) |
| epena | 1:c0429edee15b | 235 | |
| epena | 1:c0429edee15b | 236 | /* AD77681_REG_SPI_DIAG_ENABLE */ |
| epena | 1:c0429edee15b | 237 | #define AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK (0x1 << 4) |
| epena | 1:c0429edee15b | 238 | #define AD77681_SPI_DIAG_ERR_SPI_IGNORE(x) (((x) & 0x1) << 4) |
| epena | 1:c0429edee15b | 239 | #define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK (0x1 << 3) |
| epena | 1:c0429edee15b | 240 | #define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT(x) (((x) & 0x1) << 3) |
| epena | 1:c0429edee15b | 241 | #define AD77681_SPI_DIAG_ERR_SPI_RD_MSK (0x1 << 2) |
| epena | 1:c0429edee15b | 242 | #define AD77681_SPI_DIAG_ERR_SPI_RD(x) (((x) & 0x1) << 2) |
| epena | 1:c0429edee15b | 243 | #define AD77681_SPI_DIAG_ERR_SPI_WR_MSK (0x1 << 1) |
| epena | 1:c0429edee15b | 244 | #define AD77681_SPI_DIAG_ERR_SPI_WR(x) (((x) & 0x1) << 1) |
| epena | 1:c0429edee15b | 245 | |
| epena | 1:c0429edee15b | 246 | /* AD77681_REG_ADC_DIAG_ENABLE */ |
| epena | 1:c0429edee15b | 247 | #define AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK (0x1 << 5) |
| epena | 1:c0429edee15b | 248 | #define AD77681_ADC_DIAG_ERR_DLDO_PSM(x) (((x) & 0x1) << 5) |
| epena | 1:c0429edee15b | 249 | #define AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK (0x1 << 4) |
| epena | 1:c0429edee15b | 250 | #define AD77681_ADC_DIAG_ERR_ALDO_PSM(x) (((x) & 0x1) << 4) |
| epena | 1:c0429edee15b | 251 | #define AD77681_ADC_DIAG_ERR_FILT_SAT_MSK (0x1 << 2) |
| epena | 1:c0429edee15b | 252 | #define AD77681_ADC_DIAG_ERR_FILT_SAT(x) (((x) & 0x1) << 2) |
| epena | 1:c0429edee15b | 253 | #define AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK (0x1 << 1) |
| epena | 1:c0429edee15b | 254 | #define AD77681_ADC_DIAG_ERR_FILT_NOT_SET(x) (((x) & 0x1) << 1) |
| epena | 1:c0429edee15b | 255 | #define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK (0x1 << 0) |
| epena | 1:c0429edee15b | 256 | #define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL(x) (((x) & 0x1) << 0) |
| epena | 1:c0429edee15b | 257 | |
| epena | 1:c0429edee15b | 258 | /* AD77681_REG_DIG_DIAG_ENABLE */ |
| epena | 1:c0429edee15b | 259 | #define AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK (0x1 << 4) |
| epena | 1:c0429edee15b | 260 | #define AD77681_DIG_DIAG_ERR_MEMMAP_CRC(x) (((x) & 0x1) << 4) |
| epena | 1:c0429edee15b | 261 | #define AD77681_DIG_DIAG_ERR_RAM_CRC_MSK (0x1 << 3) |
| epena | 1:c0429edee15b | 262 | #define AD77681_DIG_DIAG_ERR_RAM_CRC(x) (((x) & 0x1) << 3) |
| epena | 1:c0429edee15b | 263 | #define AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK (0x1 << 2) |
| epena | 1:c0429edee15b | 264 | #define AD77681_DIG_DIAG_ERR_FUSE_CRC(x) (((x) & 0x1) << 2) |
| epena | 1:c0429edee15b | 265 | #define AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK (0x1 << 0) |
| epena | 1:c0429edee15b | 266 | #define AD77681_DIG_DIAG_FREQ_COUNT_EN(x) (((x) & 0x1) << 0) |
| epena | 1:c0429edee15b | 267 | |
| epena | 1:c0429edee15b | 268 | /* AD77681_REG_MASTER_STATUS */ |
| epena | 1:c0429edee15b | 269 | #define AD77681_MASTER_ERROR_MSK (0x1 << 7) |
| epena | 1:c0429edee15b | 270 | #define AD77681_MASTER_ADC_ERROR_MSK (0x1 << 6) |
| epena | 1:c0429edee15b | 271 | #define AD77681_MASTER_DIG_ERROR_MSK (0x1 << 5) |
| epena | 1:c0429edee15b | 272 | #define AD77681_MASTER_DIG_ERR_EXT_CLK_MSK (0x1 << 4) |
| epena | 1:c0429edee15b | 273 | #define AD77681_MASTER_FILT_SAT_MSK (0x1 << 3) |
| epena | 1:c0429edee15b | 274 | #define AD77681_MASTER_FILT_NOT_SET_MSK (0x1 << 2) |
| epena | 1:c0429edee15b | 275 | #define AD77681_MASTER_SPI_ERROR_MSK (0x1 << 1) |
| epena | 1:c0429edee15b | 276 | #define AD77681_MASTER_POR_FLAG_MSK (0x1 << 0) |
| epena | 1:c0429edee15b | 277 | |
| epena | 1:c0429edee15b | 278 | /* AD77681_REG_SPI_DIAG_STATUS */ |
| epena | 1:c0429edee15b | 279 | #define AD77681_SPI_IGNORE_ERROR_MSK (0x1 << 4) |
| epena | 1:c0429edee15b | 280 | #define AD77681_SPI_IGNORE_ERROR_CLR(x) (((x) & 0x1) << 4) |
| epena | 1:c0429edee15b | 281 | #define AD77681_SPI_CLK_CNT_ERROR_MSK (0x1 << 3) |
| epena | 1:c0429edee15b | 282 | #define AD77681_SPI_READ_ERROR_MSK (0x1 << 2) |
| epena | 1:c0429edee15b | 283 | #define AD77681_SPI_READ_ERROR_CLR(x) (((x) & 0x1) << 2) |
| epena | 1:c0429edee15b | 284 | #define AD77681_SPI_WRITE_ERROR_MSK (0x1 << 1) |
| epena | 1:c0429edee15b | 285 | #define AD77681_SPI_WRITE_ERROR_CLR(x) (((x) & 0x1) << 1) |
| epena | 1:c0429edee15b | 286 | #define AD77681_SPI_CRC_ERROR_MSK (0x1 << 0) |
| epena | 1:c0429edee15b | 287 | #define AD77681_SPI_CRC_ERROR_CLR(x) (((x) & 0x1) << 0) |
| epena | 1:c0429edee15b | 288 | |
| epena | 1:c0429edee15b | 289 | /* AD77681_REG_ADC_DIAG_STATUS */ |
| epena | 1:c0429edee15b | 290 | #define AD77681_ADC_DLDO_PSM_ERROR_MSK (0x1 << 5) |
| epena | 1:c0429edee15b | 291 | #define AD77681_ADC_ALDO_PSM_ERROR_MSK (0x1 << 4) |
| epena | 1:c0429edee15b | 292 | #define AD77681_ADC_REF_DET_ERROR_MSK (0x1 << 3) |
| epena | 1:c0429edee15b | 293 | #define AD77681_ADC_FILT_SAT_MSK (0x1 << 2) |
| epena | 1:c0429edee15b | 294 | #define AD77681_ADC_FILT_NOT_SET_MSK (0x1 << 1) |
| epena | 1:c0429edee15b | 295 | #define AD77681_ADC_DIG_ERR_EXT_CLK_MSK (0x1 << 0) |
| epena | 1:c0429edee15b | 296 | |
| epena | 1:c0429edee15b | 297 | /* AD77681_REG_DIG_DIAG_STATUS */ |
| epena | 1:c0429edee15b | 298 | #define AD77681_DIG_MEMMAP_CRC_ERROR_MSK (0x1 << 4) |
| epena | 1:c0429edee15b | 299 | #define AD77681_DIG_RAM_CRC_ERROR_MSK (0x1 << 3) |
| epena | 1:c0429edee15b | 300 | #define AD77681_DIG_FUS_CRC_ERROR_MSK (0x1 << 2) |
| epena | 1:c0429edee15b | 301 | |
| epena | 1:c0429edee15b | 302 | /* AD77681_REG_MCLK_COUNTER */ |
| epena | 1:c0429edee15b | 303 | #define AD77681_MCLK_COUNTER_MSK (0xFF << 0) |
| epena | 1:c0429edee15b | 304 | #define AD77681_MCLK_COUNTER(x) (((x) & 0xFF) << 0) |
| epena | 1:c0429edee15b | 305 | |
| epena | 1:c0429edee15b | 306 | /* AD77681_REG_COEFF_CONTROL */ |
| epena | 1:c0429edee15b | 307 | #define AD77681_COEF_CONTROL_COEFFACCESSEN_MSK (0x1 << 7) |
| epena | 1:c0429edee15b | 308 | #define AD77681_COEF_CONTROL_COEFFACCESSEN(x) (((x) & 0x1) << 7) |
| epena | 1:c0429edee15b | 309 | #define AD77681_COEF_CONTROL_COEFFWRITEEN_MSK (0x1 << 6) |
| epena | 1:c0429edee15b | 310 | #define AD77681_COEF_CONTROL_COEFFWRITEEN(x) (((x) & 0x1) << 6) |
| epena | 1:c0429edee15b | 311 | #define AD77681_COEF_CONTROL_COEFFADDR_MSK (0x3F << 5) |
| epena | 1:c0429edee15b | 312 | #define AD77681_COEF_CONTROL_COEFFADDR(x) (((x) & 0x3F) << 5) |
| epena | 1:c0429edee15b | 313 | |
| epena | 1:c0429edee15b | 314 | /* AD77681_REG_COEFF_DATA */ |
| epena | 1:c0429edee15b | 315 | #define AD77681_COEFF_DATA_USERCOEFFEN_MSK (0x1 << 23) |
| epena | 1:c0429edee15b | 316 | #define AD77681_COEFF_DATA_USERCOEFFEN(x) (((x) & 0x1) << 23) |
| epena | 1:c0429edee15b | 317 | #define AD77681_COEFF_DATA_COEFFDATA_MSK (0x7FFFFF << 22) |
| epena | 1:c0429edee15b | 318 | #define AD77681_COEFF_DATA_COEFFDATA(x) (((x) & 0x7FFFFF) << 22) |
| epena | 1:c0429edee15b | 319 | |
| epena | 1:c0429edee15b | 320 | /* AD77681_REG_ACCESS_KEY */ |
| epena | 1:c0429edee15b | 321 | #define AD77681_ACCESS_KEY_MSK (0xFF << 0) |
| epena | 1:c0429edee15b | 322 | #define AD77681_ACCESS_KEY(x) (((x) & 0xFF) << 0) |
| epena | 1:c0429edee15b | 323 | #define AD77681_ACCESS_KEY_CHECK_MSK (0x1 << 0) |
| epena | 1:c0429edee15b | 324 | |
| epena | 1:c0429edee15b | 325 | #define AD77681_REG_READ(x) ( (1 << 6) | (x & 0xFF) ) // Read from register x |
| epena | 1:c0429edee15b | 326 | #define AD77681_REG_WRITE(x) ( (~(1 << 6)) & (x & 0xFF) ) // Write to register x |
| epena | 1:c0429edee15b | 327 | |
| epena | 1:c0429edee15b | 328 | /* 8-bits wide checksum generated using the polynomial */ |
| epena | 1:c0429edee15b | 329 | #define AD77681_CRC8_POLY 0x07 // x^8 + x^2 + x^1 + x^0 |
| epena | 1:c0429edee15b | 330 | |
| epena | 1:c0429edee15b | 331 | /* Initial CRC for continuous read mode */ |
| epena | 1:c0429edee15b | 332 | #define INITIAL_CRC_CRC8 0x03 |
| epena | 1:c0429edee15b | 333 | #define INITIAL_CRC_XOR 0x6C |
| epena | 1:c0429edee15b | 334 | #define INITIAL_CRC 0x00 |
| epena | 1:c0429edee15b | 335 | |
| epena | 1:c0429edee15b | 336 | #define CRC_DEBUG |
| epena | 1:c0429edee15b | 337 | |
| epena | 1:c0429edee15b | 338 | /* AD7768-1 */ |
| epena | 1:c0429edee15b | 339 | /* A special key for exit the contiuous read mode, taken from the AD7768-1 datasheet */ |
| epena | 1:c0429edee15b | 340 | #define EXIT_CONT_READ 0x6C |
| epena | 1:c0429edee15b | 341 | /* Bit resolution of the AD7768-1 */ |
| epena | 1:c0429edee15b | 342 | #define AD7768_N_BITS 24 |
| epena | 1:c0429edee15b | 343 | /* Full scale of the AD7768-1 = 2^24 = 16777216 */ |
| epena | 1:c0429edee15b | 344 | #define AD7768_FULL_SCALE (1 << AD7768_N_BITS) |
| epena | 1:c0429edee15b | 345 | /* Half scale of the AD7768-1 = 2^23 = 8388608 */ |
| epena | 1:c0429edee15b | 346 | #define AD7768_HALF_SCALE (1 << (AD7768_N_BITS - 1)) |
| epena | 1:c0429edee15b | 347 | |
| epena | 1:c0429edee15b | 348 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) |
| epena | 1:c0429edee15b | 349 | |
| epena | 1:c0429edee15b | 350 | #define ENABLE 1 |
| epena | 1:c0429edee15b | 351 | #define DISABLE 0 |
| epena | 1:c0429edee15b | 352 | |
| epena | 1:c0429edee15b | 353 | /*****************************************************************************/ |
| epena | 1:c0429edee15b | 354 | /*************************** Types Declarations *******************************/ |
| epena | 1:c0429edee15b | 355 | /******************************************************************************/ |
| epena | 1:c0429edee15b | 356 | enum ad77681_power_mode { |
| epena | 1:c0429edee15b | 357 | AD77681_ECO = 0, |
| epena | 1:c0429edee15b | 358 | AD77681_MEDIAN = 2, |
| epena | 1:c0429edee15b | 359 | AD77681_FAST = 3, |
| epena | 1:c0429edee15b | 360 | }; |
| epena | 1:c0429edee15b | 361 | |
| epena | 1:c0429edee15b | 362 | enum ad77681_mclk_div { |
| epena | 1:c0429edee15b | 363 | AD77681_MCLK_DIV_16 = 0, |
| epena | 1:c0429edee15b | 364 | AD77681_MCLK_DIV_8 = 1, |
| epena | 1:c0429edee15b | 365 | AD77681_MCLK_DIV_4 = 2, |
| epena | 1:c0429edee15b | 366 | AD77681_MCLK_DIV_2 = 3 |
| epena | 1:c0429edee15b | 367 | }; |
| epena | 1:c0429edee15b | 368 | |
| epena | 1:c0429edee15b | 369 | enum ad77681_conv_mode { |
| epena | 1:c0429edee15b | 370 | AD77681_CONV_CONTINUOUS = 0, |
| epena | 1:c0429edee15b | 371 | AD77681_CONV_ONE_SHOT = 1, |
| epena | 1:c0429edee15b | 372 | AD77681_CONV_SINGLE = 2, |
| epena | 1:c0429edee15b | 373 | AD77681_CONV_PERIODIC = 3, |
| epena | 1:c0429edee15b | 374 | AD77681_CONV_STANDBY = 4 |
| epena | 1:c0429edee15b | 375 | }; |
| epena | 1:c0429edee15b | 376 | |
| epena | 1:c0429edee15b | 377 | enum ad77681_conv_len { |
| epena | 1:c0429edee15b | 378 | AD77681_CONV_24BIT = 0, |
| epena | 1:c0429edee15b | 379 | AD77681_CONV_16BIT = 1 |
| epena | 1:c0429edee15b | 380 | }; |
| epena | 1:c0429edee15b | 381 | |
| epena | 1:c0429edee15b | 382 | enum ad77681_rdy_dout { |
| epena | 1:c0429edee15b | 383 | AD77681_RDY_DOUT_EN, |
| epena | 1:c0429edee15b | 384 | AD77681_RDY_DOUT_DIS |
| epena | 1:c0429edee15b | 385 | }; |
| epena | 1:c0429edee15b | 386 | |
| epena | 1:c0429edee15b | 387 | enum ad77681_conv_diag_mux { |
| epena | 1:c0429edee15b | 388 | AD77681_TEMP_SENSOR = 0x0, |
| epena | 1:c0429edee15b | 389 | AD77681_AIN_SHORT= 0x8, |
| epena | 1:c0429edee15b | 390 | AD77681_POSITIVE_FS = 0x9, |
| epena | 1:c0429edee15b | 391 | AD77681_NEGATIVE_FS = 0xA |
| epena | 1:c0429edee15b | 392 | }; |
| epena | 1:c0429edee15b | 393 | |
| epena | 1:c0429edee15b | 394 | enum ad77681_crc_sel { |
| epena | 1:c0429edee15b | 395 | AD77681_CRC, |
| epena | 1:c0429edee15b | 396 | AD77681_XOR, |
| epena | 1:c0429edee15b | 397 | AD77681_NO_CRC |
| epena | 1:c0429edee15b | 398 | }; |
| epena | 1:c0429edee15b | 399 | |
| epena | 1:c0429edee15b | 400 | /* Filter tye FIR, SINC3, SINC5 */ |
| epena | 1:c0429edee15b | 401 | enum ad77681_filter_type { |
| epena | 1:c0429edee15b | 402 | AD77681_SINC5 = 0, |
| epena | 1:c0429edee15b | 403 | AD77681_SINC5_DECx8 = 1, |
| epena | 1:c0429edee15b | 404 | AD77681_SINC5_DECx16 = 2, |
| epena | 1:c0429edee15b | 405 | AD77681_SINC3 = 3, |
| epena | 1:c0429edee15b | 406 | AD77681_FIR = 4 |
| epena | 1:c0429edee15b | 407 | }; |
| epena | 1:c0429edee15b | 408 | |
| epena | 1:c0429edee15b | 409 | /* Dectimation ratios for SINC5 and FIR */ |
| epena | 1:c0429edee15b | 410 | enum ad77681_sinc5_fir_decimate { |
| epena | 1:c0429edee15b | 411 | AD77681_SINC5_FIR_DECx32 = 0, |
| epena | 1:c0429edee15b | 412 | AD77681_SINC5_FIR_DECx64 = 1, |
| epena | 1:c0429edee15b | 413 | AD77681_SINC5_FIR_DECx128 = 2, |
| epena | 1:c0429edee15b | 414 | AD77681_SINC5_FIR_DECx256 = 3, |
| epena | 1:c0429edee15b | 415 | AD77681_SINC5_FIR_DECx512 = 4, |
| epena | 1:c0429edee15b | 416 | AD77681_SINC5_FIR_DECx1024 = 5 |
| epena | 1:c0429edee15b | 417 | }; |
| epena | 1:c0429edee15b | 418 | |
| epena | 1:c0429edee15b | 419 | /* Sleep / Power up */ |
| epena | 1:c0429edee15b | 420 | enum ad77681_sleep_wake { |
| epena | 1:c0429edee15b | 421 | AD77681_SLEEP = 1, |
| epena | 1:c0429edee15b | 422 | AD77681_WAKE = 0 |
| epena | 1:c0429edee15b | 423 | }; |
| epena | 1:c0429edee15b | 424 | |
| epena | 1:c0429edee15b | 425 | /* Reset option */ |
| epena | 1:c0429edee15b | 426 | enum ad7761_reset_option { |
| epena | 1:c0429edee15b | 427 | AD77681_SOFT_RESET, |
| epena | 1:c0429edee15b | 428 | AD77681_HARD_RESET |
| epena | 1:c0429edee15b | 429 | }; |
| epena | 1:c0429edee15b | 430 | /* AIN- precharge */ |
| epena | 1:c0429edee15b | 431 | enum ad77681_AINn_precharge { |
| epena | 1:c0429edee15b | 432 | AD77681_AINn_ENABLED = 0, |
| epena | 1:c0429edee15b | 433 | AD77681_AINn_DISABLED = 1 |
| epena | 1:c0429edee15b | 434 | }; |
| epena | 1:c0429edee15b | 435 | |
| epena | 1:c0429edee15b | 436 | /* AIN+ precharge */ |
| epena | 1:c0429edee15b | 437 | enum ad77681_AINp_precharge { |
| epena | 1:c0429edee15b | 438 | AD77681_AINp_ENABLED = 0, |
| epena | 1:c0429edee15b | 439 | AD77681_AINp_DISABLED = 1 |
| epena | 1:c0429edee15b | 440 | }; |
| epena | 1:c0429edee15b | 441 | |
| epena | 1:c0429edee15b | 442 | /* REF- buffer */ |
| epena | 1:c0429edee15b | 443 | enum ad77681_REFn_buffer { |
| epena | 1:c0429edee15b | 444 | AD77681_BUFn_ENABLED = 0, |
| epena | 1:c0429edee15b | 445 | AD77681_BUFn_DISABLED = 1, |
| epena | 1:c0429edee15b | 446 | AD77681_BUFn_FULL_BUFFER_ON = 2 |
| epena | 1:c0429edee15b | 447 | }; |
| epena | 1:c0429edee15b | 448 | |
| epena | 1:c0429edee15b | 449 | /* REF+ buffer */ |
| epena | 1:c0429edee15b | 450 | enum ad77681_REFp_buffer { |
| epena | 1:c0429edee15b | 451 | AD77681_BUFp_ENABLED = 0, |
| epena | 1:c0429edee15b | 452 | AD77681_BUFp_DISABLED = 1, |
| epena | 1:c0429edee15b | 453 | AD77681_BUFp_FULL_BUFFER_ON = 2 |
| epena | 1:c0429edee15b | 454 | }; |
| epena | 1:c0429edee15b | 455 | |
| epena | 1:c0429edee15b | 456 | /* VCM output voltage */ |
| epena | 1:c0429edee15b | 457 | enum ad77681_VCM_out { |
| epena | 1:c0429edee15b | 458 | AD77681_VCM_HALF_VCC = 0, |
| epena | 1:c0429edee15b | 459 | AD77681_VCM_2_5V = 1, |
| epena | 1:c0429edee15b | 460 | AD77681_VCM_2_05V = 2, |
| epena | 1:c0429edee15b | 461 | AD77681_VCM_1_9V = 3, |
| epena | 1:c0429edee15b | 462 | AD77681_VCM_1_65V = 4, |
| epena | 1:c0429edee15b | 463 | AD77681_VCM_1_1V = 5, |
| epena | 1:c0429edee15b | 464 | AD77681_VCM_0_9V = 6, |
| epena | 1:c0429edee15b | 465 | AD77681_VCM_OFF = 7 |
| epena | 1:c0429edee15b | 466 | }; |
| epena | 1:c0429edee15b | 467 | |
| epena | 1:c0429edee15b | 468 | /* Global GPIO enable/disable */ |
| epena | 1:c0429edee15b | 469 | enum ad77681_gobal_gpio_enable { |
| epena | 1:c0429edee15b | 470 | AD77681_GLOBAL_GPIO_ENABLE = 1, |
| epena | 1:c0429edee15b | 471 | AD77681_GLOBAL_GPIO_DISABLE = 0 |
| epena | 1:c0429edee15b | 472 | }; |
| epena | 1:c0429edee15b | 473 | |
| epena | 1:c0429edee15b | 474 | /* ADCs GPIO numbering */ |
| epena | 1:c0429edee15b | 475 | enum ad77681_gpios { |
| epena | 1:c0429edee15b | 476 | AD77681_GPIO0 = 0, |
| epena | 1:c0429edee15b | 477 | AD77681_GPIO1 = 1, |
| epena | 1:c0429edee15b | 478 | AD77681_GPIO2 = 2, |
| epena | 1:c0429edee15b | 479 | AD77681_GPIO3 = 3, |
| epena | 1:c0429edee15b | 480 | AD77681_ALL_GPIOS = 4 |
| epena | 1:c0429edee15b | 481 | }; |
| epena | 1:c0429edee15b | 482 | |
| epena | 1:c0429edee15b | 483 | enum ad77681_gpio_output_type { |
| epena | 1:c0429edee15b | 484 | AD77681_GPIO_STRONG_DRIVER = 0, |
| epena | 1:c0429edee15b | 485 | AD77681_GPIO_OPEN_DRAIN = 1 |
| epena | 1:c0429edee15b | 486 | }; |
| epena | 1:c0429edee15b | 487 | |
| epena | 1:c0429edee15b | 488 | /* Continuous ADC read */ |
| epena | 1:c0429edee15b | 489 | enum ad77681_continuous_read { |
| epena | 1:c0429edee15b | 490 | AD77681_CONTINUOUS_READ_ENABLE = 1, |
| epena | 1:c0429edee15b | 491 | AD77681_CONTINUOUS_READ_DISABLE = 0, |
| epena | 1:c0429edee15b | 492 | }; |
| epena | 1:c0429edee15b | 493 | |
| epena | 1:c0429edee15b | 494 | /* ADC data read mode */ |
| epena | 1:c0429edee15b | 495 | enum ad77681_data_read_mode { |
| epena | 1:c0429edee15b | 496 | AD77681_REGISTER_DATA_READ = 0, |
| epena | 1:c0429edee15b | 497 | AD77681_CONTINUOUS_DATA_READ = 1, |
| epena | 1:c0429edee15b | 498 | }; |
| epena | 1:c0429edee15b | 499 | |
| epena | 1:c0429edee15b | 500 | /* ADC data structure */ |
| epena | 1:c0429edee15b | 501 | struct adc_data { |
| epena | 1:c0429edee15b | 502 | bool finish; |
| epena | 1:c0429edee15b | 503 | uint16_t count; |
| epena | 1:c0429edee15b | 504 | uint16_t samples; |
| epena | 1:c0429edee15b | 505 | uint32_t raw_data[4096]; |
| epena | 1:c0429edee15b | 506 | }; |
| epena | 1:c0429edee15b | 507 | /* ADC status registers structure */ |
| epena | 1:c0429edee15b | 508 | struct ad77681_status_registers { |
| epena | 1:c0429edee15b | 509 | bool master_error; |
| epena | 1:c0429edee15b | 510 | bool adc_error; |
| epena | 1:c0429edee15b | 511 | bool dig_error; |
| epena | 1:c0429edee15b | 512 | bool adc_err_ext_clk_qual; |
| epena | 1:c0429edee15b | 513 | bool adc_filt_saturated; |
| epena | 1:c0429edee15b | 514 | bool adc_filt_not_settled; |
| epena | 1:c0429edee15b | 515 | bool spi_error; |
| epena | 1:c0429edee15b | 516 | bool por_flag; |
| epena | 1:c0429edee15b | 517 | bool spi_ignore; |
| epena | 1:c0429edee15b | 518 | bool spi_clock_count; |
| epena | 1:c0429edee15b | 519 | bool spi_read_error; |
| epena | 1:c0429edee15b | 520 | bool spi_write_error; |
| epena | 1:c0429edee15b | 521 | bool spi_crc_error; |
| epena | 1:c0429edee15b | 522 | bool dldo_psm_error; |
| epena | 1:c0429edee15b | 523 | bool aldo_psm_error; |
| epena | 1:c0429edee15b | 524 | bool ref_det_error; |
| epena | 1:c0429edee15b | 525 | bool filt_sat_error; |
| epena | 1:c0429edee15b | 526 | bool filt_not_set_error; |
| epena | 1:c0429edee15b | 527 | bool ext_clk_qual_error; |
| epena | 1:c0429edee15b | 528 | bool memoy_map_crc_error; |
| epena | 1:c0429edee15b | 529 | bool ram_crc_error; |
| epena | 1:c0429edee15b | 530 | bool fuse_crc_error; |
| epena | 1:c0429edee15b | 531 | }; |
| epena | 1:c0429edee15b | 532 | |
| epena | 1:c0429edee15b | 533 | struct ad77681_dev { |
| epena | 1:c0429edee15b | 534 | /* SPI */ |
| epena | 1:c0429edee15b | 535 | spi_desc *spi_desc; |
| epena | 1:c0429edee15b | 536 | /* Configuration */ |
| epena | 1:c0429edee15b | 537 | enum ad77681_power_mode power_mode; |
| epena | 1:c0429edee15b | 538 | enum ad77681_mclk_div mclk_div; |
| epena | 1:c0429edee15b | 539 | enum ad77681_conv_mode conv_mode; |
| epena | 1:c0429edee15b | 540 | enum ad77681_conv_diag_mux diag_mux_sel; |
| epena | 1:c0429edee15b | 541 | bool conv_diag_sel; |
| epena | 1:c0429edee15b | 542 | enum ad77681_conv_len conv_len; |
| epena | 1:c0429edee15b | 543 | enum ad77681_crc_sel crc_sel; |
| epena | 1:c0429edee15b | 544 | uint8_t status_bit; |
| epena | 1:c0429edee15b | 545 | enum ad77681_VCM_out VCM_out; |
| epena | 1:c0429edee15b | 546 | enum ad77681_AINn_precharge AINn; |
| epena | 1:c0429edee15b | 547 | enum ad77681_AINp_precharge AINp; |
| epena | 1:c0429edee15b | 548 | enum ad77681_REFn_buffer REFn; |
| epena | 1:c0429edee15b | 549 | enum ad77681_REFp_buffer REFp; |
| epena | 1:c0429edee15b | 550 | enum ad77681_filter_type filter; |
| epena | 1:c0429edee15b | 551 | enum ad77681_sinc5_fir_decimate decimate; |
| epena | 1:c0429edee15b | 552 | uint16_t sinc3_osr; |
| epena | 1:c0429edee15b | 553 | uint16_t vref; /* Reference voltage*/ |
| epena | 1:c0429edee15b | 554 | uint16_t mclk; /* Mater clock*/ |
| epena | 1:c0429edee15b | 555 | uint32_t sample_rate; /* Sample rate*/ |
| epena | 1:c0429edee15b | 556 | uint8_t data_frame_byte; /* SPI 8bit frames*/ |
| epena | 1:c0429edee15b | 557 | }; |
| epena | 1:c0429edee15b | 558 | |
| epena | 1:c0429edee15b | 559 | struct ad77681_init_param { |
| epena | 1:c0429edee15b | 560 | /* SPI */ |
| epena | 1:c0429edee15b | 561 | spi_init_param spi_eng_dev_init; |
| epena | 1:c0429edee15b | 562 | /* Configuration */ |
| epena | 1:c0429edee15b | 563 | enum ad77681_power_mode power_mode; |
| epena | 1:c0429edee15b | 564 | enum ad77681_mclk_div mclk_div; |
| epena | 1:c0429edee15b | 565 | enum ad77681_conv_mode conv_mode; |
| epena | 1:c0429edee15b | 566 | enum ad77681_conv_diag_mux diag_mux_sel; |
| epena | 1:c0429edee15b | 567 | bool conv_diag_sel; |
| epena | 1:c0429edee15b | 568 | enum ad77681_conv_len conv_len; |
| epena | 1:c0429edee15b | 569 | enum ad77681_crc_sel crc_sel; |
| epena | 1:c0429edee15b | 570 | uint8_t status_bit; |
| epena | 1:c0429edee15b | 571 | enum ad77681_VCM_out VCM_out; |
| epena | 1:c0429edee15b | 572 | enum ad77681_AINn_precharge AINn; |
| epena | 1:c0429edee15b | 573 | enum ad77681_AINp_precharge AINp; |
| epena | 1:c0429edee15b | 574 | enum ad77681_REFn_buffer REFn; |
| epena | 1:c0429edee15b | 575 | enum ad77681_REFp_buffer REFp; |
| epena | 1:c0429edee15b | 576 | enum ad77681_filter_type filter; |
| epena | 1:c0429edee15b | 577 | enum ad77681_sinc5_fir_decimate decimate; |
| epena | 1:c0429edee15b | 578 | uint16_t sinc3_osr; |
| epena | 1:c0429edee15b | 579 | uint16_t vref; |
| epena | 1:c0429edee15b | 580 | uint16_t mclk; |
| epena | 1:c0429edee15b | 581 | uint32_t sample_rate; |
| epena | 1:c0429edee15b | 582 | uint8_t data_frame_byte; |
| epena | 1:c0429edee15b | 583 | }; |
| epena | 1:c0429edee15b | 584 | |
| epena | 1:c0429edee15b | 585 | /******************************************************************************/ |
| epena | 1:c0429edee15b | 586 | /************************ Functions Declarations ******************************/ |
| epena | 1:c0429edee15b | 587 | /******************************************************************************/ |
| epena | 1:c0429edee15b | 588 | uint8_t ad77681_compute_crc8(uint8_t *data, |
| epena | 1:c0429edee15b | 589 | uint8_t data_size, |
| epena | 1:c0429edee15b | 590 | uint8_t init_val); |
| epena | 1:c0429edee15b | 591 | uint8_t ad77681_compute_xor(uint8_t *data, |
| epena | 1:c0429edee15b | 592 | uint8_t data_size, |
| epena | 1:c0429edee15b | 593 | uint8_t init_val); |
| epena | 1:c0429edee15b | 594 | int32_t ad77681_setup(struct ad77681_dev **device, |
| epena | 1:c0429edee15b | 595 | struct ad77681_init_param init_param, |
| epena | 1:c0429edee15b | 596 | struct ad77681_status_registers **status); |
| epena | 1:c0429edee15b | 597 | int32_t ad77681_spi_reg_read(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 598 | uint8_t reg_addr, |
| epena | 1:c0429edee15b | 599 | uint8_t *reg_data); |
| epena | 1:c0429edee15b | 600 | int32_t ad77681_spi_read_mask(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 601 | uint8_t reg_addr, |
| epena | 1:c0429edee15b | 602 | uint8_t mask, |
| epena | 1:c0429edee15b | 603 | uint8_t *data); |
| epena | 1:c0429edee15b | 604 | int32_t ad77681_spi_reg_write(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 605 | uint8_t reg_addr, |
| epena | 1:c0429edee15b | 606 | uint8_t reg_data); |
| epena | 1:c0429edee15b | 607 | int32_t ad77681_spi_write_mask(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 608 | uint8_t reg_addr, |
| epena | 1:c0429edee15b | 609 | uint8_t mask, |
| epena | 1:c0429edee15b | 610 | uint8_t data); |
| epena | 1:c0429edee15b | 611 | int32_t ad77681_set_power_mode(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 612 | enum ad77681_power_mode mode); |
| epena | 1:c0429edee15b | 613 | int32_t ad77681_set_mclk_div(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 614 | enum ad77681_mclk_div clk_div); |
| epena | 1:c0429edee15b | 615 | int32_t ad77681_spi_read_adc_data(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 616 | uint8_t *adc_data, |
| epena | 1:c0429edee15b | 617 | enum ad77681_data_read_mode mode); |
| epena | 1:c0429edee15b | 618 | int32_t ad77681_set_conv_mode(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 619 | enum ad77681_conv_mode conv_mode, |
| epena | 1:c0429edee15b | 620 | enum ad77681_conv_diag_mux diag_mux_sel, |
| epena | 1:c0429edee15b | 621 | bool conv_diag_sel); |
| epena | 1:c0429edee15b | 622 | int32_t ad77681_set_convlen(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 623 | enum ad77681_conv_len conv_len); |
| epena | 1:c0429edee15b | 624 | int32_t ad77681_soft_reset(struct ad77681_dev *dev); |
| epena | 1:c0429edee15b | 625 | int32_t ad77681_initiate_sync(struct ad77681_dev *dev); |
| epena | 1:c0429edee15b | 626 | int32_t ad77681_programmable_filter(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 627 | const float *coeffs, |
| epena | 1:c0429edee15b | 628 | uint8_t num_coeffs); |
| epena | 1:c0429edee15b | 629 | int32_t ad77681_gpio_read(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 630 | uint8_t *value, |
| epena | 1:c0429edee15b | 631 | enum ad77681_gpios gpio_number); |
| epena | 1:c0429edee15b | 632 | int32_t ad77681_apply_offset(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 633 | uint32_t value); |
| epena | 1:c0429edee15b | 634 | int32_t ad77681_apply_gain(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 635 | uint32_t value); |
| epena | 1:c0429edee15b | 636 | int32_t ad77681_set_crc_sel(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 637 | enum ad77681_crc_sel crc_sel); |
| epena | 1:c0429edee15b | 638 | int32_t ad77681_gpio_open_drain(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 639 | enum ad77681_gpios gpio_number, |
| epena | 1:c0429edee15b | 640 | enum ad77681_gpio_output_type output_type); |
| epena | 1:c0429edee15b | 641 | int32_t ad77681_set_continuos_read(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 642 | enum ad77681_continuous_read continuous_enable); |
| epena | 1:c0429edee15b | 643 | int32_t ad77681_clear_error_flags(struct ad77681_dev *dev); |
| epena | 1:c0429edee15b | 644 | int32_t ad77681_data_to_voltage(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 645 | uint32_t *raw_code, |
| epena | 1:c0429edee15b | 646 | double *voltage); |
| epena | 1:c0429edee15b | 647 | int32_t ad77681_CRC_status_handling(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 648 | uint16_t *data_buffer); |
| epena | 1:c0429edee15b | 649 | int32_t ad77681_set_AINn_buffer(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 650 | enum ad77681_AINn_precharge AINn); |
| epena | 1:c0429edee15b | 651 | int32_t ad77681_set_AINp_buffer(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 652 | enum ad77681_AINp_precharge AINp); |
| epena | 1:c0429edee15b | 653 | int32_t ad77681_set_REFn_buffer(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 654 | enum ad77681_REFn_buffer REFn); |
| epena | 1:c0429edee15b | 655 | int32_t ad77681_set_REFp_buffer(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 656 | enum ad77681_REFp_buffer REFp); |
| epena | 1:c0429edee15b | 657 | int32_t ad77681_set_filter_type(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 658 | enum ad77681_sinc5_fir_decimate decimate, |
| epena | 1:c0429edee15b | 659 | enum ad77681_filter_type filter, |
| epena | 1:c0429edee15b | 660 | uint16_t sinc3_osr); |
| epena | 1:c0429edee15b | 661 | int32_t ad77681_set_50HZ_rejection(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 662 | uint8_t enable); |
| epena | 1:c0429edee15b | 663 | int32_t ad77681_power_down(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 664 | enum ad77681_sleep_wake sleep_wake); |
| epena | 1:c0429edee15b | 665 | int32_t ad77681_set_status_bit(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 666 | bool status_bit); |
| epena | 1:c0429edee15b | 667 | int32_t ad77681_set_VCM_output(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 668 | enum ad77681_VCM_out VCM_out); |
| epena | 1:c0429edee15b | 669 | int32_t ad77681_gpio_write(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 670 | uint8_t value, |
| epena | 1:c0429edee15b | 671 | enum ad77681_gpios gpio_number); |
| epena | 1:c0429edee15b | 672 | int32_t ad77681_gpio_inout(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 673 | uint8_t direction, |
| epena | 1:c0429edee15b | 674 | enum ad77681_gpios gpio_number); |
| epena | 1:c0429edee15b | 675 | int32_t ad77681_global_gpio(struct ad77681_dev *devices, |
| epena | 1:c0429edee15b | 676 | enum ad77681_gobal_gpio_enable gpio_enable); |
| epena | 1:c0429edee15b | 677 | int32_t ad77681_scratchpad(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 678 | uint8_t *sequence); |
| epena | 1:c0429edee15b | 679 | int32_t ad77681_error_flags_enabe(struct ad77681_dev *dev); |
| epena | 1:c0429edee15b | 680 | int32_t ad77681_update_sample_rate(struct ad77681_dev *dev); |
| epena | 1:c0429edee15b | 681 | int32_t ad77681_SINC3_ODR(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 682 | uint16_t *sinc3_dec_reg, |
| epena | 1:c0429edee15b | 683 | float sinc3_odr); |
| epena | 1:c0429edee15b | 684 | int32_t ad77681_status(struct ad77681_dev *dev, |
| epena | 1:c0429edee15b | 685 | struct ad77681_status_registers *status); |
| epena | 1:c0429edee15b | 686 | #endif /* SRC_AD77681_H_ */ |