Eric Pena / Mbed OS EVAL-AD7768-1

AD7768-1 MBED IIO Application Example

Dependencies:   platform_drivers

app/ad77681.c@2:eb624ef78449, 2021-09-24 (annotated)

Committer:
epena
Date:
Fri Sep 24 19:07:29 2021 +0800
Revision:
2:eb624ef78449
Parent:
1:c0429edee15b 
Deleting the redefinition of data_capture_ops

Who changed what in which revision?

UserRevisionLine numberNew contents of line
epena 1:c0429edee15b 1 /***************************************************************************//**
epena 1:c0429edee15b 2 * @file ad77681.c
epena 1:c0429edee15b 3 * @brief Implementation of AD7768-1 Driver.
epena 1:c0429edee15b 4 * @author SPopa (stefan.popa@analog.com)
epena 1:c0429edee15b 5 ********************************************************************************
epena 1:c0429edee15b 6 * Copyright 2017(c) Analog Devices, Inc.
epena 1:c0429edee15b 7 *
epena 1:c0429edee15b 8 * All rights reserved.
epena 1:c0429edee15b 9 *
epena 1:c0429edee15b 10 * Redistribution and use in source and binary forms, with or without
epena 1:c0429edee15b 11 * modification, are permitted provided that the following conditions are met:
epena 1:c0429edee15b 12 * - Redistributions of source code must retain the above copyright
epena 1:c0429edee15b 13 * notice, this list of conditions and the following disclaimer.
epena 1:c0429edee15b 14 * - Redistributions in binary form must reproduce the above copyright
epena 1:c0429edee15b 15 * notice, this list of conditions and the following disclaimer in
epena 1:c0429edee15b 16 * the documentation and/or other materials provided with the
epena 1:c0429edee15b 17 * distribution.
epena 1:c0429edee15b 18 * - Neither the name of Analog Devices, Inc. nor the names of its
epena 1:c0429edee15b 19 * contributors may be used to endorse or promote products derived
epena 1:c0429edee15b 20 * from this software without specific prior written permission.
epena 1:c0429edee15b 21 * - The use of this software may or may not infringe the patent rights
epena 1:c0429edee15b 22 * of one or more patent holders. This license does not release you
epena 1:c0429edee15b 23 * from the requirement that you obtain separate licenses from these
epena 1:c0429edee15b 24 * patent holders to use this software.
epena 1:c0429edee15b 25 * - Use of the software either in source or binary form, must be run
epena 1:c0429edee15b 26 * on or directly connected to an Analog Devices Inc. component.
epena 1:c0429edee15b 27 *
epena 1:c0429edee15b 28 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
epena 1:c0429edee15b 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
epena 1:c0429edee15b 30 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
epena 1:c0429edee15b 31 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
epena 1:c0429edee15b 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
epena 1:c0429edee15b 33 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
epena 1:c0429edee15b 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
epena 1:c0429edee15b 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
epena 1:c0429edee15b 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
epena 1:c0429edee15b 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
epena 1:c0429edee15b 38 *******************************************************************************/
epena 1:c0429edee15b 39
epena 1:c0429edee15b 40 /******************************************************************************/
epena 1:c0429edee15b 41 /***************************** Include Files **********************************/
epena 1:c0429edee15b 42 /******************************************************************************/
epena 1:c0429edee15b 43 #include "stdio.h"
epena 1:c0429edee15b 44 #include "stdlib.h"
epena 1:c0429edee15b 45 #include "stdbool.h"
epena 1:c0429edee15b 46 #include <string.h>
epena 1:c0429edee15b 47 #include "ad77681.h"
epena 1:c0429edee15b 48 #include "error.h"
epena 1:c0429edee15b 49 #include "delay.h"
epena 1:c0429edee15b 50
epena 1:c0429edee15b 51 /******************************************************************************/
epena 1:c0429edee15b 52 /************************** Functions Implementation **************************/
epena 1:c0429edee15b 53 /******************************************************************************/
epena 1:c0429edee15b 54 /**
epena 1:c0429edee15b 55 * Compute CRC8 checksum.
epena 1:c0429edee15b 56 * @param data - The data buffer.
epena 1:c0429edee15b 57 * @param data_size - The size of the data buffer.
epena 1:c0429edee15b 58 * @param init_val - CRC initial value.
epena 1:c0429edee15b 59 * @return CRC8 checksum.
epena 1:c0429edee15b 60 */
epena 1:c0429edee15b 61 uint8_t ad77681_compute_crc8(uint8_t *data,
epena 1:c0429edee15b 62 uint8_t data_size,
epena 1:c0429edee15b 63 uint8_t init_val)
epena 1:c0429edee15b 64 {
epena 1:c0429edee15b 65 uint8_t i;
epena 1:c0429edee15b 66 uint8_t crc = init_val;
epena 1:c0429edee15b 67
epena 1:c0429edee15b 68 while (data_size) {
epena 1:c0429edee15b 69 for (i = 0x80; i != 0; i >>= 1) {
epena 1:c0429edee15b 70 if (((crc & 0x80) != 0) != ((*data & i) != 0)) {
epena 1:c0429edee15b 71 crc <<= 1;
epena 1:c0429edee15b 72 crc ^= AD77681_CRC8_POLY;
epena 1:c0429edee15b 73 } else
epena 1:c0429edee15b 74 crc <<= 1;
epena 1:c0429edee15b 75 }
epena 1:c0429edee15b 76 data++;
epena 1:c0429edee15b 77 data_size--;
epena 1:c0429edee15b 78 }
epena 1:c0429edee15b 79 return crc;
epena 1:c0429edee15b 80 }
epena 1:c0429edee15b 81
epena 1:c0429edee15b 82 /**
epena 1:c0429edee15b 83 * Compute XOR checksum.
epena 1:c0429edee15b 84 * @param data - The data buffer.
epena 1:c0429edee15b 85 * @param data_size - The size of the data buffer.
epena 1:c0429edee15b 86 * @param init_val - CRC initial value.
epena 1:c0429edee15b 87 * @return XOR checksum.
epena 1:c0429edee15b 88 */
epena 1:c0429edee15b 89 uint8_t ad77681_compute_xor(uint8_t *data,
epena 1:c0429edee15b 90 uint8_t data_size,
epena 1:c0429edee15b 91 uint8_t init_val)
epena 1:c0429edee15b 92 {
epena 1:c0429edee15b 93 uint8_t crc = init_val;
epena 1:c0429edee15b 94 uint8_t buf[3];
epena 1:c0429edee15b 95 uint8_t i;
epena 1:c0429edee15b 96
epena 1:c0429edee15b 97 for (i = 0; i < data_size; i++) {
epena 1:c0429edee15b 98 buf[i] = *data;
epena 1:c0429edee15b 99 crc ^= buf[i];
epena 1:c0429edee15b 100 data++;
epena 1:c0429edee15b 101 }
epena 1:c0429edee15b 102 return crc;
epena 1:c0429edee15b 103 }
epena 1:c0429edee15b 104
epena 1:c0429edee15b 105 /**
epena 1:c0429edee15b 106 * Read from device.
epena 1:c0429edee15b 107 * @param dev - The device structure.
epena 1:c0429edee15b 108 * @param reg_addr - The register address.
epena 1:c0429edee15b 109 * @param reg_data - The register data.
epena 1:c0429edee15b 110 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 111 */
epena 1:c0429edee15b 112 int32_t ad77681_spi_reg_read(struct ad77681_dev *dev,
epena 1:c0429edee15b 113 uint8_t reg_addr,
epena 1:c0429edee15b 114 uint8_t *reg_data)
epena 1:c0429edee15b 115 {
epena 1:c0429edee15b 116 int32_t ret;
epena 1:c0429edee15b 117 uint8_t crc;
epena 1:c0429edee15b 118 uint8_t buf[3], crc_buf[2];
epena 1:c0429edee15b 119 uint8_t buf_len = (dev->crc_sel == AD77681_NO_CRC) ? 2 : 3;
epena 1:c0429edee15b 120
epena 1:c0429edee15b 121 buf[0] = AD77681_REG_READ(reg_addr);
epena 1:c0429edee15b 122 buf[1] = 0x00;
epena 1:c0429edee15b 123
epena 1:c0429edee15b 124 ret = spi_write_and_read(dev->spi_desc, buf, buf_len);
epena 1:c0429edee15b 125 if (ret < 0)
epena 1:c0429edee15b 126 return ret;
epena 1:c0429edee15b 127
epena 1:c0429edee15b 128 /* XOR or CRC checksum for read transactions */
epena 1:c0429edee15b 129 if (dev->crc_sel != AD77681_NO_CRC) {
epena 1:c0429edee15b 130 crc_buf[0] = AD77681_REG_READ(reg_addr);
epena 1:c0429edee15b 131 crc_buf[1] = buf[1];
epena 1:c0429edee15b 132
epena 1:c0429edee15b 133 if (dev->crc_sel == AD77681_XOR)
epena 1:c0429edee15b 134 /* INITIAL_CRC is 0, when ADC is not in continuous-read mode */
epena 1:c0429edee15b 135 crc = ad77681_compute_xor(crc_buf, 2, INITIAL_CRC);
epena 1:c0429edee15b 136 else if(dev->crc_sel == AD77681_CRC)
epena 1:c0429edee15b 137 /* INITIAL_CRC is 0, when ADC is not in continuous-read mode */
epena 1:c0429edee15b 138 crc = ad77681_compute_crc8(crc_buf, 2, INITIAL_CRC);
epena 1:c0429edee15b 139
epena 1:c0429edee15b 140 /* In buf[2] is CRC from the ADC */
epena 1:c0429edee15b 141 if (crc != buf[2])
epena 1:c0429edee15b 142 ret = FAILURE;
epena 1:c0429edee15b 143 #ifdef CRC_DEBUG
epena 1:c0429edee15b 144 printf("\n%x\t%x\tCRC/XOR: %s\n", crc,
epena 1:c0429edee15b 145 buf[2], ((crc != buf[2]) ? "FAULT" : "OK"));
epena 1:c0429edee15b 146 #endif /* CRC_DEBUG */
epena 1:c0429edee15b 147 }
epena 1:c0429edee15b 148
epena 1:c0429edee15b 149 reg_data[0] = AD77681_REG_READ(reg_addr);
epena 1:c0429edee15b 150 memcpy(reg_data + 1, buf + 1, ARRAY_SIZE(buf) - 1);
epena 1:c0429edee15b 151
epena 1:c0429edee15b 152 return ret;
epena 1:c0429edee15b 153 }
epena 1:c0429edee15b 154
epena 1:c0429edee15b 155 /**
epena 1:c0429edee15b 156 * Write to device.
epena 1:c0429edee15b 157 * @param dev - The device structure.
epena 1:c0429edee15b 158 * @param reg_addr - The register address.
epena 1:c0429edee15b 159 * @param reg_data - The register data.
epena 1:c0429edee15b 160 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 161 */
epena 1:c0429edee15b 162 int32_t ad77681_spi_reg_write(struct ad77681_dev *dev,
epena 1:c0429edee15b 163 uint8_t reg_addr,
epena 1:c0429edee15b 164 uint8_t reg_data)
epena 1:c0429edee15b 165 {
epena 1:c0429edee15b 166 uint8_t buf[3];
epena 1:c0429edee15b 167 /* Buffer length in case of checksum usage */
epena 1:c0429edee15b 168 uint8_t buf_len = (dev->crc_sel == AD77681_NO_CRC) ? 2 : 3;
epena 1:c0429edee15b 169
epena 1:c0429edee15b 170 buf[0] = AD77681_REG_WRITE(reg_addr);
epena 1:c0429edee15b 171 buf[1] = reg_data;
epena 1:c0429edee15b 172
epena 1:c0429edee15b 173 /* CRC only for read transactions, CRC and XOR for write transactions*/
epena 1:c0429edee15b 174 if (dev->crc_sel != AD77681_NO_CRC)
epena 1:c0429edee15b 175 buf[2] = ad77681_compute_crc8(buf, 2, INITIAL_CRC);
epena 1:c0429edee15b 176
epena 1:c0429edee15b 177 return spi_write_and_read(dev->spi_desc, buf, buf_len);
epena 1:c0429edee15b 178 }
epena 1:c0429edee15b 179
epena 1:c0429edee15b 180 /**
epena 1:c0429edee15b 181 * SPI read from device using a mask.
epena 1:c0429edee15b 182 * @param dev - The device structure.
epena 1:c0429edee15b 183 * @param reg_addr - The register address.
epena 1:c0429edee15b 184 * @param mask - The mask.
epena 1:c0429edee15b 185 * @param data - The register data.
epena 1:c0429edee15b 186 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 187 */
epena 1:c0429edee15b 188 int32_t ad77681_spi_read_mask(struct ad77681_dev *dev,
epena 1:c0429edee15b 189 uint8_t reg_addr,
epena 1:c0429edee15b 190 uint8_t mask,
epena 1:c0429edee15b 191 uint8_t *data)
epena 1:c0429edee15b 192 {
epena 1:c0429edee15b 193 uint8_t reg_data[3];
epena 1:c0429edee15b 194 int32_t ret;
epena 1:c0429edee15b 195
epena 1:c0429edee15b 196 ret = ad77681_spi_reg_read(dev, reg_addr, reg_data);
epena 1:c0429edee15b 197 *data = (reg_data[1] & mask);
epena 1:c0429edee15b 198
epena 1:c0429edee15b 199 return ret;
epena 1:c0429edee15b 200 }
epena 1:c0429edee15b 201
epena 1:c0429edee15b 202 /**
epena 1:c0429edee15b 203 * SPI write to device using a mask.
epena 1:c0429edee15b 204 * @param dev - The device structure.
epena 1:c0429edee15b 205 * @param reg_addr - The register address.
epena 1:c0429edee15b 206 * @param mask - The mask.
epena 1:c0429edee15b 207 * @param data - The register data.
epena 1:c0429edee15b 208 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 209 */
epena 1:c0429edee15b 210 int32_t ad77681_spi_write_mask(struct ad77681_dev *dev,
epena 1:c0429edee15b 211 uint8_t reg_addr,
epena 1:c0429edee15b 212 uint8_t mask,
epena 1:c0429edee15b 213 uint8_t data)
epena 1:c0429edee15b 214 {
epena 1:c0429edee15b 215 uint8_t reg_data[3];
epena 1:c0429edee15b 216 int32_t ret;
epena 1:c0429edee15b 217
epena 1:c0429edee15b 218 ret = ad77681_spi_reg_read(dev, reg_addr, reg_data);
epena 1:c0429edee15b 219 reg_data[1] &= ~mask;
epena 1:c0429edee15b 220 reg_data[1] |= data;
epena 1:c0429edee15b 221 ret |= ad77681_spi_reg_write(dev, reg_addr, reg_data[1]);
epena 1:c0429edee15b 222
epena 1:c0429edee15b 223 return ret;
epena 1:c0429edee15b 224 }
epena 1:c0429edee15b 225
epena 1:c0429edee15b 226 /**
epena 1:c0429edee15b 227 * Helper function to get the number of rx bytes
epena 1:c0429edee15b 228 * @param dev - The device structure.
epena 1:c0429edee15b 229 * @return rx_buf_len - the number of rx bytes
epena 1:c0429edee15b 230 */
epena 1:c0429edee15b 231 uint8_t ad77681_get_rx_buf_len(struct ad77681_dev *dev)
epena 1:c0429edee15b 232 {
epena 1:c0429edee15b 233 uint8_t rx_buf_len = 0;
epena 1:c0429edee15b 234 uint8_t data_len = 0;
epena 1:c0429edee15b 235 uint8_t crc = 0;
epena 1:c0429edee15b 236 uint8_t status_bit = 0;
epena 1:c0429edee15b 237
epena 1:c0429edee15b 238 data_len = 3;
epena 1:c0429edee15b 239 crc = (dev->crc_sel == AD77681_NO_CRC) ? 0 : 1; // 1 byte for crc
epena 1:c0429edee15b 240 status_bit = dev->status_bit; // one byte for status
epena 1:c0429edee15b 241
epena 1:c0429edee15b 242 rx_buf_len = data_len + crc + status_bit;
epena 1:c0429edee15b 243
epena 1:c0429edee15b 244 return rx_buf_len;
epena 1:c0429edee15b 245 }
epena 1:c0429edee15b 246
epena 1:c0429edee15b 247 /**
epena 1:c0429edee15b 248 * Helper function to get the number of SPI 16bit frames for INTERRUPT ADC DATA READ
epena 1:c0429edee15b 249 * @param dev - The device structure.
epena 1:c0429edee15b 250 * @return frame_16bit - the number of 16 bit SPI frames
epena 1:c0429edee15b 251 */
epena 1:c0429edee15b 252 uint8_t ad77681_get_frame_byte(struct ad77681_dev *dev)
epena 1:c0429edee15b 253 {
epena 1:c0429edee15b 254 /* number of 8bit frames */
epena 1:c0429edee15b 255 uint8_t frame_bytes;
epena 1:c0429edee15b 256 if (dev->conv_len == AD77681_CONV_24BIT)
epena 1:c0429edee15b 257 frame_bytes = 3;
epena 1:c0429edee15b 258 else
epena 1:c0429edee15b 259 frame_bytes = 2;
epena 1:c0429edee15b 260 if (dev->crc_sel != AD77681_NO_CRC)
epena 1:c0429edee15b 261 frame_bytes++;
epena 1:c0429edee15b 262 if (dev->status_bit)
epena 1:c0429edee15b 263 frame_bytes++;
epena 1:c0429edee15b 264
epena 1:c0429edee15b 265 dev->data_frame_byte = frame_bytes;
epena 1:c0429edee15b 266
epena 1:c0429edee15b 267 return frame_bytes;
epena 1:c0429edee15b 268 }
epena 1:c0429edee15b 269
epena 1:c0429edee15b 270 /**
epena 1:c0429edee15b 271 * Read conversion result from device.
epena 1:c0429edee15b 272 * @param dev - The device structure.
epena 1:c0429edee15b 273 * @param adc_data - The conversion result data
epena 1:c0429edee15b 274 * @param mode - Data read mode
epena 1:c0429edee15b 275 * Accepted values: AD77681_REGISTER_DATA_READ
epena 1:c0429edee15b 276 * AD77681_CONTINUOUS_DATA_READ
epena 1:c0429edee15b 277 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 278 */
epena 1:c0429edee15b 279 int32_t ad77681_spi_read_adc_data(struct ad77681_dev *dev,
epena 1:c0429edee15b 280 uint8_t *adc_data,
epena 1:c0429edee15b 281 enum ad77681_data_read_mode mode)
epena 1:c0429edee15b 282 {
epena 1:c0429edee15b 283 uint8_t buf[6], crc_xor, add_buff;
epena 1:c0429edee15b 284 int32_t ret;
epena 1:c0429edee15b 285
epena 1:c0429edee15b 286 if (mode == AD77681_REGISTER_DATA_READ) {
epena 1:c0429edee15b 287 buf[0] = AD77681_REG_READ(AD77681_REG_ADC_DATA);
epena 1:c0429edee15b 288 add_buff = 1;
epena 1:c0429edee15b 289 } else {
epena 1:c0429edee15b 290 buf[0] = 0x00;
epena 1:c0429edee15b 291 add_buff = 0;
epena 1:c0429edee15b 292 }
epena 1:c0429edee15b 293 buf[1] = 0x00; /* added 2 more array places for max data length read */
epena 1:c0429edee15b 294 buf[2] = 0x00; /* For register data read */
epena 1:c0429edee15b 295 buf[3] = 0x00; /* register address + 3 bytes of data (24bit format) + Status bit + CRC */
epena 1:c0429edee15b 296 buf[4] = 0x00; /* For continuous data read */
epena 1:c0429edee15b 297 buf[5] = 0x00; /* 3 bytes of data (24bit format) + Status bit + CRC */
epena 1:c0429edee15b 298
epena 1:c0429edee15b 299
epena 1:c0429edee15b 300 ret = spi_write_and_read(dev->spi_desc, buf, dev->data_frame_byte + add_buff);
epena 1:c0429edee15b 301 if (ret < 0)
epena 1:c0429edee15b 302 return ret;
epena 1:c0429edee15b 303
epena 1:c0429edee15b 304 if (dev->crc_sel != AD77681_NO_CRC) {
epena 1:c0429edee15b 305 if (dev->crc_sel == AD77681_CRC)
epena 1:c0429edee15b 306 crc_xor = ad77681_compute_crc8(buf + add_buff, dev->data_frame_byte - 1,
epena 1:c0429edee15b 307 INITIAL_CRC_CRC8);
epena 1:c0429edee15b 308 else
epena 1:c0429edee15b 309 crc_xor = ad77681_compute_xor(buf + add_buff, dev->data_frame_byte - 1,
epena 1:c0429edee15b 310 INITIAL_CRC_XOR);
epena 1:c0429edee15b 311
epena 1:c0429edee15b 312 if (crc_xor != buf[dev->data_frame_byte - (1 - add_buff)]) {
epena 1:c0429edee15b 313 printf("%s: CRC Error.\n", __func__);
epena 1:c0429edee15b 314 ret = FAILURE;
epena 1:c0429edee15b 315 }
epena 1:c0429edee15b 316 #ifdef CRC_DEBUG
epena 1:c0429edee15b 317 printf("\n%x\t%x\tCRC/XOR: %s\n", crc_xor,
epena 1:c0429edee15b 318 buf[dev->data_frame_byte - (1 - add_buff)],
epena 1:c0429edee15b 319 ((crc_xor != buf[dev->data_frame_byte - (1 - add_buff)]) ? "FAULT" : "OK"));
epena 1:c0429edee15b 320 #endif /* CRC_DEBUG */
epena 1:c0429edee15b 321 }
epena 1:c0429edee15b 322
epena 1:c0429edee15b 323 /* Fill the adc_data buffer */
epena 1:c0429edee15b 324 memcpy(adc_data, buf, ARRAY_SIZE(buf));
epena 1:c0429edee15b 325
epena 1:c0429edee15b 326 return ret;
epena 1:c0429edee15b 327 }
epena 1:c0429edee15b 328
epena 1:c0429edee15b 329 /**
epena 1:c0429edee15b 330 * CRC and status bit handling after each readout form the ADC
epena 1:c0429edee15b 331 * @param dev - The device structure.
epena 1:c0429edee15b 332 * @param *data_buffer - 16-bit buffer readed from the ADC containing the CRC,
epena 1:c0429edee15b 333 * data and the stattus bit.
epena 1:c0429edee15b 334 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 335 */
epena 1:c0429edee15b 336 int32_t ad77681_CRC_status_handling(struct ad77681_dev *dev,
epena 1:c0429edee15b 337 uint16_t *data_buffer)
epena 1:c0429edee15b 338 {
epena 1:c0429edee15b 339 int32_t ret = 0;
epena 1:c0429edee15b 340 uint8_t status_byte = 0, checksum = 0, checksum_byte = 0, checksum_buf[5],
epena 1:c0429edee15b 341 checksum_length = 0, i;
epena 1:c0429edee15b 342 char print_buf[50];
epena 1:c0429edee15b 343
epena 1:c0429edee15b 344 /* Status bit handling */
epena 1:c0429edee15b 345 if (dev->status_bit) {
epena 1:c0429edee15b 346 /* 24bit ADC data + 8bit of status = 2 16bit frames */
epena 1:c0429edee15b 347 if (dev->conv_len == AD77681_CONV_24BIT)
epena 1:c0429edee15b 348 status_byte = data_buffer[1] & 0xFF;
epena 1:c0429edee15b 349 /* 16bit ADC data + 8bit of status = 2 16bit frames */
epena 1:c0429edee15b 350 else
epena 1:c0429edee15b 351 status_byte = data_buffer[1] >> 8;
epena 1:c0429edee15b 352 }
epena 1:c0429edee15b 353
epena 1:c0429edee15b 354 /* Checksum bit handling */
epena 1:c0429edee15b 355 if (dev->crc_sel != AD77681_NO_CRC) {
epena 1:c0429edee15b 356 if ((dev->status_bit == true) & (dev->conv_len == AD77681_CONV_24BIT)) {
epena 1:c0429edee15b 357 /* 24bit ADC data + 8bit of status + 8bit of CRC = 3 16bit frames */
epena 1:c0429edee15b 358 checksum_byte = data_buffer[2] >> 8;
epena 1:c0429edee15b 359 checksum_length = 4;
epena 1:c0429edee15b 360 } else if ((dev->status_bit == true) & (dev->conv_len == AD77681_CONV_16BIT)) {
epena 1:c0429edee15b 361 /* 16bit ADC data + 8bit of status + 8bit of CRC = 2 16bit frames */
epena 1:c0429edee15b 362 checksum_byte = data_buffer[1] & 0xFF;
epena 1:c0429edee15b 363 checksum_length = 3;
epena 1:c0429edee15b 364 } else if ((dev->status_bit == false) & (dev->conv_len == AD77681_CONV_24BIT)) {
epena 1:c0429edee15b 365 /* 24bit ADC data + 8bit of CRC = 2 16bit frames */
epena 1:c0429edee15b 366 checksum_byte = data_buffer[1] & 0xFF;
epena 1:c0429edee15b 367 checksum_length = 3;
epena 1:c0429edee15b 368 } else if ((dev->status_bit == false) & (dev->conv_len == AD77681_CONV_16BIT)) {
epena 1:c0429edee15b 369 /* 16bit ADC data + 8bit of CRC = 2 16bit frames */
epena 1:c0429edee15b 370 checksum_byte = data_buffer[1] >> 8;
epena 1:c0429edee15b 371 checksum_length = 2;
epena 1:c0429edee15b 372 }
epena 1:c0429edee15b 373
epena 1:c0429edee15b 374 for (i = 0; i < checksum_length; i++) {
epena 1:c0429edee15b 375 if (i % 2)
epena 1:c0429edee15b 376 checksum_buf[i] = data_buffer[i / 2] & 0xFF;
epena 1:c0429edee15b 377 else
epena 1:c0429edee15b 378 checksum_buf[i] = data_buffer[i / 2] >> 8;
epena 1:c0429edee15b 379 }
epena 1:c0429edee15b 380
epena 1:c0429edee15b 381 if (dev->crc_sel == AD77681_CRC)
epena 1:c0429edee15b 382 checksum = ad77681_compute_crc8(checksum_buf, checksum_length,
epena 1:c0429edee15b 383 INITIAL_CRC_CRC8);
epena 1:c0429edee15b 384 else if (dev->crc_sel == AD77681_XOR)
epena 1:c0429edee15b 385 checksum = ad77681_compute_xor(checksum_buf, checksum_length, INITIAL_CRC_XOR);
epena 1:c0429edee15b 386
epena 1:c0429edee15b 387 if (checksum != checksum_byte)
epena 1:c0429edee15b 388 ret = FAILURE;
epena 1:c0429edee15b 389
epena 1:c0429edee15b 390 #ifdef CRC_DEBUG
epena 1:c0429edee15b 391
epena 1:c0429edee15b 392 char ok[3] = { 'O', 'K' }, fault[6] = { 'F', 'A', 'U', 'L', 'T' };
epena 1:c0429edee15b 393 sprintf(print_buf, "\n%x\t%x\t%x\tCRC %s", checksum_byte, checksum, status_byte,
epena 1:c0429edee15b 394 ((ret == FAILURE) ? (fault) : (ok)));
epena 1:c0429edee15b 395 printf(print_buf);
epena 1:c0429edee15b 396
epena 1:c0429edee15b 397 #endif /* CRC_DEBUG */
epena 1:c0429edee15b 398 }
epena 1:c0429edee15b 399
epena 1:c0429edee15b 400 return ret;
epena 1:c0429edee15b 401 }
epena 1:c0429edee15b 402
epena 1:c0429edee15b 403 /**
epena 1:c0429edee15b 404 * Conversion from measured data to voltage
epena 1:c0429edee15b 405 * @param dev - The device structure.
epena 1:c0429edee15b 406 * @param raw_code - ADC raw code measurements
epena 1:c0429edee15b 407 * @param voltage - Converted ADC code to voltage
epena 1:c0429edee15b 408 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 409 */
epena 1:c0429edee15b 410 int32_t ad77681_data_to_voltage(struct ad77681_dev *dev,
epena 1:c0429edee15b 411 uint32_t *raw_code,
epena 1:c0429edee15b 412 double *voltage)
epena 1:c0429edee15b 413 {
epena 1:c0429edee15b 414 int32_t converted_data;
epena 1:c0429edee15b 415
epena 1:c0429edee15b 416 if (*raw_code & 0x800000)
epena 1:c0429edee15b 417 converted_data = (int32_t)((0xFF << 24) | *raw_code);
epena 1:c0429edee15b 418 else
epena 1:c0429edee15b 419 converted_data = (int32_t)((0x00 << 24) | *raw_code);
epena 1:c0429edee15b 420
epena 1:c0429edee15b 421 /* ((2*Vref)*code)/2^24 */
epena 1:c0429edee15b 422 *voltage = (double)(((2.0 * (((double)(dev->vref)) / 1000.0)) /
epena 1:c0429edee15b 423 AD7768_FULL_SCALE) * converted_data);
epena 1:c0429edee15b 424
epena 1:c0429edee15b 425 return SUCCESS;
epena 1:c0429edee15b 426 }
epena 1:c0429edee15b 427
epena 1:c0429edee15b 428 /**
epena 1:c0429edee15b 429 * Update ADCs sample rate depending on MCLK, MCLK_DIV and filter settings
epena 1:c0429edee15b 430 * @param dev - The device structure.
epena 1:c0429edee15b 431 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 432 */
epena 1:c0429edee15b 433 int32_t ad77681_update_sample_rate(struct ad77681_dev *dev)
epena 1:c0429edee15b 434 {
epena 1:c0429edee15b 435 uint8_t mclk_div;
epena 1:c0429edee15b 436 uint16_t osr;
epena 1:c0429edee15b 437
epena 1:c0429edee15b 438 /* Finding out MCLK divider */
epena 1:c0429edee15b 439 switch (dev->mclk_div) {
epena 1:c0429edee15b 440 case AD77681_MCLK_DIV_16:
epena 1:c0429edee15b 441 mclk_div = 16;
epena 1:c0429edee15b 442 break;
epena 1:c0429edee15b 443 case AD77681_MCLK_DIV_8:
epena 1:c0429edee15b 444 mclk_div = 8;
epena 1:c0429edee15b 445 break;
epena 1:c0429edee15b 446 case AD77681_MCLK_DIV_4:
epena 1:c0429edee15b 447 mclk_div = 4;
epena 1:c0429edee15b 448 break;
epena 1:c0429edee15b 449 case AD77681_MCLK_DIV_2:
epena 1:c0429edee15b 450 mclk_div = 2;
epena 1:c0429edee15b 451 break;
epena 1:c0429edee15b 452 default:
epena 1:c0429edee15b 453 return FAILURE;
epena 1:c0429edee15b 454 break;
epena 1:c0429edee15b 455 }
epena 1:c0429edee15b 456
epena 1:c0429edee15b 457 /* Finding out decimation ratio */
epena 1:c0429edee15b 458 switch (dev->filter) {
epena 1:c0429edee15b 459 case (AD77681_SINC5 | AD77681_FIR):
epena 1:c0429edee15b 460 /* Decimation ratio of FIR or SINC5 (x32 to x1024) */
epena 1:c0429edee15b 461 switch (dev->decimate) {
epena 1:c0429edee15b 462 case AD77681_SINC5_FIR_DECx32:
epena 1:c0429edee15b 463 osr = 32;
epena 1:c0429edee15b 464 break;
epena 1:c0429edee15b 465 case AD77681_SINC5_FIR_DECx64:
epena 1:c0429edee15b 466 osr = 64;
epena 1:c0429edee15b 467 break;
epena 1:c0429edee15b 468 case AD77681_SINC5_FIR_DECx128:
epena 1:c0429edee15b 469 osr = 128;
epena 1:c0429edee15b 470 break;
epena 1:c0429edee15b 471 case AD77681_SINC5_FIR_DECx256:
epena 1:c0429edee15b 472 osr = 256;
epena 1:c0429edee15b 473 break;
epena 1:c0429edee15b 474 case AD77681_SINC5_FIR_DECx512:
epena 1:c0429edee15b 475 osr = 512;
epena 1:c0429edee15b 476 break;
epena 1:c0429edee15b 477 case AD77681_SINC5_FIR_DECx1024:
epena 1:c0429edee15b 478 osr = 1024;
epena 1:c0429edee15b 479 break;
epena 1:c0429edee15b 480 default:
epena 1:c0429edee15b 481 return FAILURE;
epena 1:c0429edee15b 482 break;
epena 1:c0429edee15b 483 }
epena 1:c0429edee15b 484 break;
epena 1:c0429edee15b 485 /* Decimation ratio of SINC5 x8 */
epena 1:c0429edee15b 486 case AD77681_SINC5_DECx8:
epena 1:c0429edee15b 487 osr = 8;
epena 1:c0429edee15b 488 break;
epena 1:c0429edee15b 489 /* Decimation ratio of SINC5 x16 */
epena 1:c0429edee15b 490 case AD77681_SINC5_DECx16:
epena 1:c0429edee15b 491 osr = 16;
epena 1:c0429edee15b 492 break;
epena 1:c0429edee15b 493 /* Decimation ratio of SINC3 */
epena 1:c0429edee15b 494 case AD77681_SINC3:
epena 1:c0429edee15b 495 osr = (dev->sinc3_osr + 1) * 32;
epena 1:c0429edee15b 496 break;
epena 1:c0429edee15b 497 default:
epena 1:c0429edee15b 498 return FAILURE;
epena 1:c0429edee15b 499 break;
epena 1:c0429edee15b 500 }
epena 1:c0429edee15b 501
epena 1:c0429edee15b 502 /* Sample rate to Hz */
epena 1:c0429edee15b 503 dev->sample_rate = (dev->mclk / (osr*mclk_div)) * 1000;
epena 1:c0429edee15b 504
epena 1:c0429edee15b 505 return SUCCESS;
epena 1:c0429edee15b 506 }
epena 1:c0429edee15b 507
epena 1:c0429edee15b 508 /**
epena 1:c0429edee15b 509 * Get SINC3 filter oversampling ratio register value based on user's inserted
epena 1:c0429edee15b 510 * output data rate ODR
epena 1:c0429edee15b 511 * @param dev - The device structure.
epena 1:c0429edee15b 512 * @param sinc3_dec_reg - Returned closest value of SINC3 register
epena 1:c0429edee15b 513 * @param sinc3_odr - Desired output data rage
epena 1:c0429edee15b 514 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 515 */
epena 1:c0429edee15b 516 int32_t ad77681_SINC3_ODR(struct ad77681_dev *dev,
epena 1:c0429edee15b 517 uint16_t *sinc3_dec_reg,
epena 1:c0429edee15b 518 float sinc3_odr)
epena 1:c0429edee15b 519 {
epena 1:c0429edee15b 520 uint8_t mclk_div;
epena 1:c0429edee15b 521 float odr;
epena 1:c0429edee15b 522
epena 1:c0429edee15b 523 if (sinc3_odr < 0)
epena 1:c0429edee15b 524 return FAILURE;
epena 1:c0429edee15b 525
epena 1:c0429edee15b 526 switch (dev->mclk_div) {
epena 1:c0429edee15b 527 case AD77681_MCLK_DIV_16:
epena 1:c0429edee15b 528 mclk_div = 16;
epena 1:c0429edee15b 529 break;
epena 1:c0429edee15b 530 case AD77681_MCLK_DIV_8:
epena 1:c0429edee15b 531 mclk_div = 8;
epena 1:c0429edee15b 532 break;
epena 1:c0429edee15b 533 case AD77681_MCLK_DIV_4:
epena 1:c0429edee15b 534 mclk_div = 4;
epena 1:c0429edee15b 535 break;
epena 1:c0429edee15b 536 case AD77681_MCLK_DIV_2:
epena 1:c0429edee15b 537 mclk_div = 2;
epena 1:c0429edee15b 538 break;
epena 1:c0429edee15b 539 default:
epena 1:c0429edee15b 540 return FAILURE;
epena 1:c0429edee15b 541 break;
epena 1:c0429edee15b 542 }
epena 1:c0429edee15b 543
epena 1:c0429edee15b 544 odr = ((float)(dev->mclk * 1000.0) / (sinc3_odr * (float)(32 * mclk_div))) - 1;
epena 1:c0429edee15b 545
epena 1:c0429edee15b 546 /* Sinc3 oversamplig register has 13 bits, biggest value = 8192 */
epena 1:c0429edee15b 547 if (odr < 8193)
epena 1:c0429edee15b 548 *sinc3_dec_reg = (uint16_t)(odr);
epena 1:c0429edee15b 549 else
epena 1:c0429edee15b 550 return FAILURE;
epena 1:c0429edee15b 551
epena 1:c0429edee15b 552 return SUCCESS;
epena 1:c0429edee15b 553 }
epena 1:c0429edee15b 554
epena 1:c0429edee15b 555 /**
epena 1:c0429edee15b 556 * Set the power consumption mode of the ADC core.
epena 1:c0429edee15b 557 * @param dev - The device structure.
epena 1:c0429edee15b 558 * @param mode - The power mode.
epena 1:c0429edee15b 559 * Accepted values: AD77681_ECO
epena 1:c0429edee15b 560 * AD77681_MEDIAN
epena 1:c0429edee15b 561 * AD77681_FAST
epena 1:c0429edee15b 562 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 563 */
epena 1:c0429edee15b 564 int32_t ad77681_set_power_mode(struct ad77681_dev *dev,
epena 1:c0429edee15b 565 enum ad77681_power_mode mode)
epena 1:c0429edee15b 566 {
epena 1:c0429edee15b 567 int32_t ret;
epena 1:c0429edee15b 568
epena 1:c0429edee15b 569 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 570 AD77681_REG_POWER_CLOCK,
epena 1:c0429edee15b 571 AD77681_POWER_CLK_PWRMODE_MSK,
epena 1:c0429edee15b 572 AD77681_POWER_CLK_PWRMODE(mode));
epena 1:c0429edee15b 573
epena 1:c0429edee15b 574 if (ret == SUCCESS)
epena 1:c0429edee15b 575 dev->power_mode = mode;
epena 1:c0429edee15b 576
epena 1:c0429edee15b 577 return ret;
epena 1:c0429edee15b 578 }
epena 1:c0429edee15b 579
epena 1:c0429edee15b 580 /**
epena 1:c0429edee15b 581 * Set the MCLK divider.
epena 1:c0429edee15b 582 * @param dev - The device structure.
epena 1:c0429edee15b 583 * @param clk_div - The MCLK divider.
epena 1:c0429edee15b 584 * Accepted values: AD77681_MCLK_DIV_16
epena 1:c0429edee15b 585 * AD77681_MCLK_DIV_8
epena 1:c0429edee15b 586 * AD77681_MCLK_DIV_4
epena 1:c0429edee15b 587 * AD77681_MCLK_DIV_2
epena 1:c0429edee15b 588 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 589 */
epena 1:c0429edee15b 590 int32_t ad77681_set_mclk_div(struct ad77681_dev *dev,
epena 1:c0429edee15b 591 enum ad77681_mclk_div clk_div)
epena 1:c0429edee15b 592 {
epena 1:c0429edee15b 593 int32_t ret;
epena 1:c0429edee15b 594
epena 1:c0429edee15b 595 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 596 AD77681_REG_POWER_CLOCK,
epena 1:c0429edee15b 597 AD77681_POWER_CLK_MCLK_DIV_MSK,
epena 1:c0429edee15b 598 AD77681_POWER_CLK_MCLK_DIV(clk_div));
epena 1:c0429edee15b 599
epena 1:c0429edee15b 600 if (ret == SUCCESS)
epena 1:c0429edee15b 601 dev->mclk_div = clk_div;
epena 1:c0429edee15b 602
epena 1:c0429edee15b 603 return ret;
epena 1:c0429edee15b 604 }
epena 1:c0429edee15b 605
epena 1:c0429edee15b 606 /**
epena 1:c0429edee15b 607 * Set the VCM output.
epena 1:c0429edee15b 608 * @param dev - The device structure.
epena 1:c0429edee15b 609 * @param VCM_out - The VCM output voltage.
epena 1:c0429edee15b 610 * Accepted values: AD77681_VCM_HALF_VCC
epena 1:c0429edee15b 611 * AD77681_VCM_2_5V
epena 1:c0429edee15b 612 * AD77681_VCM_2_05V
epena 1:c0429edee15b 613 * AD77681_VCM_1_9V
epena 1:c0429edee15b 614 * AD77681_VCM_1_65V
epena 1:c0429edee15b 615 * AD77681_VCM_1_1V
epena 1:c0429edee15b 616 * AD77681_VCM_0_9V
epena 1:c0429edee15b 617 * AD77681_VCM_OFF
epena 1:c0429edee15b 618 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 619 */
epena 1:c0429edee15b 620 int32_t ad77681_set_VCM_output(struct ad77681_dev *dev,
epena 1:c0429edee15b 621 enum ad77681_VCM_out VCM_out)
epena 1:c0429edee15b 622 {
epena 1:c0429edee15b 623 int32_t ret;
epena 1:c0429edee15b 624
epena 1:c0429edee15b 625 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 626 AD77681_REG_ANALOG2,
epena 1:c0429edee15b 627 AD77681_ANALOG2_VCM_MSK,
epena 1:c0429edee15b 628 AD77681_ANALOG2_VCM(VCM_out));
epena 1:c0429edee15b 629
epena 1:c0429edee15b 630 if (ret == SUCCESS)
epena 1:c0429edee15b 631 dev->VCM_out = VCM_out;
epena 1:c0429edee15b 632
epena 1:c0429edee15b 633 return ret;
epena 1:c0429edee15b 634 }
epena 1:c0429edee15b 635
epena 1:c0429edee15b 636 /**
epena 1:c0429edee15b 637 * Set the AIN- precharge buffer.
epena 1:c0429edee15b 638 * @param dev - The device structure.
epena 1:c0429edee15b 639 * @param AINn - The negative analog input precharge buffer selector
epena 1:c0429edee15b 640 * Accepted values: AD77681_AINn_ENABLED
epena 1:c0429edee15b 641 * AD77681_AINn_DISABLED
epena 1:c0429edee15b 642 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 643 */
epena 1:c0429edee15b 644 int32_t ad77681_set_AINn_buffer(struct ad77681_dev *dev,
epena 1:c0429edee15b 645 enum ad77681_AINn_precharge AINn)
epena 1:c0429edee15b 646 {
epena 1:c0429edee15b 647 int32_t ret;
epena 1:c0429edee15b 648
epena 1:c0429edee15b 649 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 650 AD77681_REG_ANALOG,
epena 1:c0429edee15b 651 AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK,
epena 1:c0429edee15b 652 AD77681_ANALOG_AIN_BUF_NEG_OFF(AINn));
epena 1:c0429edee15b 653
epena 1:c0429edee15b 654 if (ret == SUCCESS)
epena 1:c0429edee15b 655 dev->AINn = AINn;
epena 1:c0429edee15b 656
epena 1:c0429edee15b 657 return ret;
epena 1:c0429edee15b 658 }
epena 1:c0429edee15b 659
epena 1:c0429edee15b 660 /**
epena 1:c0429edee15b 661 * Set the AIN+ precharge buffer.
epena 1:c0429edee15b 662 * @param dev - The device structure.
epena 1:c0429edee15b 663 * @param AINp - The positive analog input precharge buffer selector
epena 1:c0429edee15b 664 * Accepted values: AD77681_AINp_ENABLED
epena 1:c0429edee15b 665 * AD77681_AINp_DISABLED
epena 1:c0429edee15b 666 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 667 */
epena 1:c0429edee15b 668 int32_t ad77681_set_AINp_buffer(struct ad77681_dev *dev,
epena 1:c0429edee15b 669 enum ad77681_AINp_precharge AINp)
epena 1:c0429edee15b 670 {
epena 1:c0429edee15b 671 int32_t ret;
epena 1:c0429edee15b 672
epena 1:c0429edee15b 673 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 674 AD77681_REG_ANALOG,
epena 1:c0429edee15b 675 AD77681_ANALOG_AIN_BUF_POS_OFF_MSK,
epena 1:c0429edee15b 676 AD77681_ANALOG_AIN_BUF_POS_OFF(AINp));
epena 1:c0429edee15b 677
epena 1:c0429edee15b 678 if (ret == SUCCESS)
epena 1:c0429edee15b 679 dev->AINp = AINp;
epena 1:c0429edee15b 680
epena 1:c0429edee15b 681 return ret;
epena 1:c0429edee15b 682 }
epena 1:c0429edee15b 683
epena 1:c0429edee15b 684 /**
epena 1:c0429edee15b 685 * Set the REF- reference buffer
epena 1:c0429edee15b 686 * @param dev - The device structure.
epena 1:c0429edee15b 687 * @param REFn - The negative reference buffer selector
epena 1:c0429edee15b 688 * Accepted values: AD77681_BUFn_DISABLED
epena 1:c0429edee15b 689 * AD77681_BUFn_ENABLED
epena 1:c0429edee15b 690 * AD77681_BUFn_FULL_BUFFER_ON
epena 1:c0429edee15b 691 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 692 */
epena 1:c0429edee15b 693 int32_t ad77681_set_REFn_buffer(struct ad77681_dev *dev,
epena 1:c0429edee15b 694 enum ad77681_REFn_buffer REFn)
epena 1:c0429edee15b 695 {
epena 1:c0429edee15b 696 int32_t ret;
epena 1:c0429edee15b 697
epena 1:c0429edee15b 698 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 699 AD77681_REG_ANALOG,
epena 1:c0429edee15b 700 AD77681_ANALOG_REF_BUF_NEG_MSK,
epena 1:c0429edee15b 701 AD77681_ANALOG_REF_BUF_NEG(REFn));
epena 1:c0429edee15b 702
epena 1:c0429edee15b 703 if (ret == SUCCESS)
epena 1:c0429edee15b 704 dev->REFn = REFn;
epena 1:c0429edee15b 705
epena 1:c0429edee15b 706 return ret;
epena 1:c0429edee15b 707 }
epena 1:c0429edee15b 708
epena 1:c0429edee15b 709 /**
epena 1:c0429edee15b 710 * Set the REF+ reference buffer
epena 1:c0429edee15b 711 * @param dev - The device structure.
epena 1:c0429edee15b 712 * @param REFp - The positive reference buffer selector
epena 1:c0429edee15b 713 * Accepted values: AD77681_BUFp_DISABLED
epena 1:c0429edee15b 714 * AD77681_BUFp_ENABLED
epena 1:c0429edee15b 715 * AD77681_BUFp_FULL_BUFFER_ON
epena 1:c0429edee15b 716 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 717 */
epena 1:c0429edee15b 718 int32_t ad77681_set_REFp_buffer(struct ad77681_dev *dev,
epena 1:c0429edee15b 719 enum ad77681_REFp_buffer REFp)
epena 1:c0429edee15b 720 {
epena 1:c0429edee15b 721 int32_t ret;
epena 1:c0429edee15b 722
epena 1:c0429edee15b 723 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 724 AD77681_REG_ANALOG,
epena 1:c0429edee15b 725 AD77681_ANALOG_REF_BUF_POS_MSK,
epena 1:c0429edee15b 726 AD77681_ANALOG_REF_BUF_POS(REFp));
epena 1:c0429edee15b 727
epena 1:c0429edee15b 728 if (ret == SUCCESS)
epena 1:c0429edee15b 729 dev->REFp = REFp;
epena 1:c0429edee15b 730 else
epena 1:c0429edee15b 731 return FAILURE;
epena 1:c0429edee15b 732
epena 1:c0429edee15b 733 return ret;
epena 1:c0429edee15b 734 }
epena 1:c0429edee15b 735
epena 1:c0429edee15b 736 /**
epena 1:c0429edee15b 737 * Set filter type and decimation ratio
epena 1:c0429edee15b 738 * @param dev - The device structure.
epena 1:c0429edee15b 739 * @param decimate - Decimation ratio of filter
epena 1:c0429edee15b 740 * Accepted values: AD77681_SINC5_FIR_DECx32
epena 1:c0429edee15b 741 * AD77681_SINC5_FIR_DECx64
epena 1:c0429edee15b 742 * AD77681_SINC5_FIR_DECx128
epena 1:c0429edee15b 743 * AD77681_SINC5_FIR_DECx256
epena 1:c0429edee15b 744 * AD77681_SINC5_FIR_DECx512
epena 1:c0429edee15b 745 * AD77681_SINC5_FIR_DECx1024
epena 1:c0429edee15b 746 * @param filter - Select filter type
epena 1:c0429edee15b 747 * Accepted values: AD77681_SINC5
epena 1:c0429edee15b 748 * AD77681_SINC5_DECx8
epena 1:c0429edee15b 749 * AD77681_SINC5_DECx16
epena 1:c0429edee15b 750 * AD77681_SINC3
epena 1:c0429edee15b 751 * AD77681_FIR
epena 1:c0429edee15b 752 * @param sinc3_osr - Select decimation ratio for SINC3 filter separately as
epena 1:c0429edee15b 753 * integer from 0 to 8192.
epena 1:c0429edee15b 754 * See the AD7768-1 datasheet for more info
epena 1:c0429edee15b 755 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 756 */
epena 1:c0429edee15b 757 int32_t ad77681_set_filter_type(struct ad77681_dev *dev,
epena 1:c0429edee15b 758 enum ad77681_sinc5_fir_decimate decimate,
epena 1:c0429edee15b 759 enum ad77681_filter_type filter,
epena 1:c0429edee15b 760 uint16_t sinc3_osr)
epena 1:c0429edee15b 761 {
epena 1:c0429edee15b 762 int32_t ret;
epena 1:c0429edee15b 763
epena 1:c0429edee15b 764 ret = ad77681_spi_reg_write(dev, AD77681_REG_DIGITAL_FILTER, 0x00);
epena 1:c0429edee15b 765
epena 1:c0429edee15b 766 /* SINC5 for OSR 8x and 16x*/
epena 1:c0429edee15b 767 if ((filter == AD77681_SINC5_DECx8) || (filter == AD77681_SINC5_DECx16)) {
epena 1:c0429edee15b 768 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 769 AD77681_REG_DIGITAL_FILTER,
epena 1:c0429edee15b 770 AD77681_DIGI_FILTER_FILTER_MSK,
epena 1:c0429edee15b 771 AD77681_DIGI_FILTER_FILTER(filter));
epena 1:c0429edee15b 772 /* SINC5 and FIR for osr 32x to 1024x */
epena 1:c0429edee15b 773 } else if ((filter == AD77681_SINC5) || (filter == AD77681_FIR)) {
epena 1:c0429edee15b 774 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 775 AD77681_REG_DIGITAL_FILTER,
epena 1:c0429edee15b 776 AD77681_DIGI_FILTER_FILTER_MSK,
epena 1:c0429edee15b 777 AD77681_DIGI_FILTER_FILTER(filter));
epena 1:c0429edee15b 778
epena 1:c0429edee15b 779 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 780 AD77681_REG_DIGITAL_FILTER,
epena 1:c0429edee15b 781 AD77681_DIGI_FILTER_DEC_RATE_MSK,
epena 1:c0429edee15b 782 AD77681_DIGI_FILTER_DEC_RATE(decimate));
epena 1:c0429edee15b 783 /* SINC3*/
epena 1:c0429edee15b 784 } else {
epena 1:c0429edee15b 785 uint8_t sinc3_LSB = 0, sinc3_MSB = 0;
epena 1:c0429edee15b 786
epena 1:c0429edee15b 787 sinc3_MSB = sinc3_osr >> 8;
epena 1:c0429edee15b 788 sinc3_LSB = sinc3_osr & 0x00FF;
epena 1:c0429edee15b 789
epena 1:c0429edee15b 790 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 791 AD77681_REG_DIGITAL_FILTER,
epena 1:c0429edee15b 792 AD77681_DIGI_FILTER_FILTER_MSK,
epena 1:c0429edee15b 793 AD77681_DIGI_FILTER_FILTER(filter));
epena 1:c0429edee15b 794
epena 1:c0429edee15b 795 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 796 AD77681_REG_SINC3_DEC_RATE_MSB,
epena 1:c0429edee15b 797 AD77681_SINC3_DEC_RATE_MSB_MSK,
epena 1:c0429edee15b 798 AD77681_SINC3_DEC_RATE_MSB(sinc3_MSB));
epena 1:c0429edee15b 799
epena 1:c0429edee15b 800 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 801 AD77681_REG_SINC3_DEC_RATE_LSB,
epena 1:c0429edee15b 802 AD77681_SINC3_DEC_RATE_LSB_MSK,
epena 1:c0429edee15b 803 AD77681_SINC3_DEC_RATE_LSB(sinc3_LSB));
epena 1:c0429edee15b 804 }
epena 1:c0429edee15b 805
epena 1:c0429edee15b 806 if ( ret == SUCCESS) {
epena 1:c0429edee15b 807 dev->decimate = decimate;
epena 1:c0429edee15b 808 dev->filter = filter;
epena 1:c0429edee15b 809 /* Sync pulse after each filter change */
epena 1:c0429edee15b 810 ret |= ad77681_initiate_sync(dev);
epena 1:c0429edee15b 811 }
epena 1:c0429edee15b 812
epena 1:c0429edee15b 813 return ret;
epena 1:c0429edee15b 814 }
epena 1:c0429edee15b 815
epena 1:c0429edee15b 816 /**
epena 1:c0429edee15b 817 * Enable 50/60 Hz rejection
epena 1:c0429edee15b 818 * @param dev - The device structure.
epena 1:c0429edee15b 819 * @param enable - The positive reference buffer selector
epena 1:c0429edee15b 820 * Accepted values: true
epena 1:c0429edee15b 821 * false
epena 1:c0429edee15b 822 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 823 */
epena 1:c0429edee15b 824 int32_t ad77681_set_50HZ_rejection(struct ad77681_dev *dev,
epena 1:c0429edee15b 825 uint8_t enable)
epena 1:c0429edee15b 826 {
epena 1:c0429edee15b 827 int32_t ret;
epena 1:c0429edee15b 828
epena 1:c0429edee15b 829 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 830 AD77681_REG_DIGITAL_FILTER,
epena 1:c0429edee15b 831 AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK,
epena 1:c0429edee15b 832 AD77681_DIGI_FILTER_60HZ_REJ_EN(enable));
epena 1:c0429edee15b 833
epena 1:c0429edee15b 834 return ret;
epena 1:c0429edee15b 835 }
epena 1:c0429edee15b 836
epena 1:c0429edee15b 837 /**
epena 1:c0429edee15b 838 * Set the REF- reference buffer
epena 1:c0429edee15b 839 * @param dev - The device structure.
epena 1:c0429edee15b 840 * @param continuous_enable - Continous read enable
epena 1:c0429edee15b 841 * Accepted values: AD77681_CONTINUOUS_READ_ENABLE
epena 1:c0429edee15b 842 * AD77681_CONTINUOUS_READ_DISABLE
epena 1:c0429edee15b 843 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 844 */
epena 1:c0429edee15b 845 int32_t ad77681_set_continuos_read(struct ad77681_dev *dev,
epena 1:c0429edee15b 846 enum ad77681_continuous_read continuous_enable)
epena 1:c0429edee15b 847 {
epena 1:c0429edee15b 848 int32_t ret;
epena 1:c0429edee15b 849
epena 1:c0429edee15b 850 if (continuous_enable) {
epena 1:c0429edee15b 851 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 852 AD77681_REG_INTERFACE_FORMAT,
epena 1:c0429edee15b 853 AD77681_INTERFACE_CONT_READ_MSK,
epena 1:c0429edee15b 854 AD77681_INTERFACE_CONT_READ_EN(continuous_enable));
epena 1:c0429edee15b 855 } else {
epena 1:c0429edee15b 856 /* To exit the continuous read mode, a key 0x6C must be
epena 1:c0429edee15b 857 written into the device over the SPI*/
epena 1:c0429edee15b 858 uint8_t end_key = EXIT_CONT_READ;
epena 1:c0429edee15b 859 ret = spi_write_and_read(dev->spi_desc, &end_key, 1);
epena 1:c0429edee15b 860 }
epena 1:c0429edee15b 861
epena 1:c0429edee15b 862 return ret;
epena 1:c0429edee15b 863 }
epena 1:c0429edee15b 864
epena 1:c0429edee15b 865 /**
epena 1:c0429edee15b 866 * Power down / power up the device
epena 1:c0429edee15b 867 * @param dev - The device structure.
epena 1:c0429edee15b 868 * @param sleep_wake - Power down, or power up the ADC
epena 1:c0429edee15b 869 * Accepted values: AD77681_SLEEP
epena 1:c0429edee15b 870 * AD77681_WAKE
epena 1:c0429edee15b 871 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 872 */
epena 1:c0429edee15b 873 int32_t ad77681_power_down(struct ad77681_dev *dev,
epena 1:c0429edee15b 874 enum ad77681_sleep_wake sleep_wake)
epena 1:c0429edee15b 875 {
epena 1:c0429edee15b 876 int32_t ret;
epena 1:c0429edee15b 877
epena 1:c0429edee15b 878 if (sleep_wake == AD77681_SLEEP) {
epena 1:c0429edee15b 879 ret = ad77681_spi_reg_write(dev, AD77681_REG_POWER_CLOCK,
epena 1:c0429edee15b 880 AD77681_POWER_CLK_POWER_DOWN);
epena 1:c0429edee15b 881 } else {
epena 1:c0429edee15b 882 /* Wake up the ADC over SPI, by sending a wake-up sequence:
epena 1:c0429edee15b 883 1 followed by 63 zeroes and CS hold low*/
epena 1:c0429edee15b 884 uint8_t wake_sequence[8] = { 0 };
epena 1:c0429edee15b 885 /* Insert '1' to the beginning of the wake_sequence*/
epena 1:c0429edee15b 886 wake_sequence[0] = 0x80;
epena 1:c0429edee15b 887 ret = spi_write_and_read(dev->spi_desc, wake_sequence,
epena 1:c0429edee15b 888 ARRAY_SIZE(wake_sequence));
epena 1:c0429edee15b 889 }
epena 1:c0429edee15b 890
epena 1:c0429edee15b 891 return ret;
epena 1:c0429edee15b 892 }
epena 1:c0429edee15b 893
epena 1:c0429edee15b 894 /**
epena 1:c0429edee15b 895 * Conversion mode and source select
epena 1:c0429edee15b 896 * @param dev - The device structure.
epena 1:c0429edee15b 897 * @param conv_mode - Sets the conversion mode of the ADC
epena 1:c0429edee15b 898 * Accepted values: AD77681_CONV_CONTINUOUS
epena 1:c0429edee15b 899 * AD77681_CONV_ONE_SHOT
epena 1:c0429edee15b 900 * AD77681_CONV_SINGLE
epena 1:c0429edee15b 901 * AD77681_CONV_PERIODIC
epena 1:c0429edee15b 902 * @param diag_mux_sel - Selects which signal to route through diagnostic mux
epena 1:c0429edee15b 903 * Accepted values: AD77681_TEMP_SENSOR
epena 1:c0429edee15b 904 * AD77681_AIN_SHORT
epena 1:c0429edee15b 905 * AD77681_POSITIVE_FS
epena 1:c0429edee15b 906 * AD77681_NEGATIVE_FS
epena 1:c0429edee15b 907 * @param conv_diag_sel - Select the input for conversion as AIN or diagnostic mux
epena 1:c0429edee15b 908 * Accepted values: true
epena 1:c0429edee15b 909 * false
epena 1:c0429edee15b 910 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 911 */
epena 1:c0429edee15b 912 int32_t ad77681_set_conv_mode(struct ad77681_dev *dev,
epena 1:c0429edee15b 913 enum ad77681_conv_mode conv_mode,
epena 1:c0429edee15b 914 enum ad77681_conv_diag_mux diag_mux_sel,
epena 1:c0429edee15b 915 bool conv_diag_sel)
epena 1:c0429edee15b 916 {
epena 1:c0429edee15b 917 int32_t ret;
epena 1:c0429edee15b 918
epena 1:c0429edee15b 919 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 920 AD77681_REG_CONVERSION,
epena 1:c0429edee15b 921 AD77681_CONVERSION_MODE_MSK,
epena 1:c0429edee15b 922 AD77681_CONVERSION_MODE(conv_mode));
epena 1:c0429edee15b 923
epena 1:c0429edee15b 924 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 925 AD77681_REG_CONVERSION,
epena 1:c0429edee15b 926 AD77681_CONVERSION_DIAG_MUX_MSK,
epena 1:c0429edee15b 927 AD77681_CONVERSION_DIAG_MUX_SEL(diag_mux_sel));
epena 1:c0429edee15b 928
epena 1:c0429edee15b 929 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 930 AD77681_REG_CONVERSION,
epena 1:c0429edee15b 931 AD77681_CONVERSION_DIAG_SEL_MSK,
epena 1:c0429edee15b 932 AD77681_CONVERSION_DIAG_SEL(conv_diag_sel));
epena 1:c0429edee15b 933
epena 1:c0429edee15b 934 if (ret == SUCCESS) {
epena 1:c0429edee15b 935 dev->conv_mode = conv_mode;
epena 1:c0429edee15b 936 dev->diag_mux_sel = diag_mux_sel;
epena 1:c0429edee15b 937 dev->conv_diag_sel = conv_diag_sel;
epena 1:c0429edee15b 938 }
epena 1:c0429edee15b 939
epena 1:c0429edee15b 940 return ret;
epena 1:c0429edee15b 941 }
epena 1:c0429edee15b 942
epena 1:c0429edee15b 943 /**
epena 1:c0429edee15b 944 * Set the Conversion Result Output Length.
epena 1:c0429edee15b 945 * @param dev - The device structure.
epena 1:c0429edee15b 946 * @param conv_len - The MCLK divider.
epena 1:c0429edee15b 947 * Accepted values: AD77681_CONV_24BIT
epena 1:c0429edee15b 948 * AD77681_CONV_16BIT
epena 1:c0429edee15b 949 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 950 */
epena 1:c0429edee15b 951 int32_t ad77681_set_convlen(struct ad77681_dev *dev,
epena 1:c0429edee15b 952 enum ad77681_conv_len conv_len)
epena 1:c0429edee15b 953 {
epena 1:c0429edee15b 954 int32_t ret;
epena 1:c0429edee15b 955
epena 1:c0429edee15b 956 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 957 AD77681_REG_INTERFACE_FORMAT,
epena 1:c0429edee15b 958 AD77681_INTERFACE_CONVLEN_MSK,
epena 1:c0429edee15b 959 AD77681_INTERFACE_CONVLEN(conv_len));
epena 1:c0429edee15b 960
epena 1:c0429edee15b 961 if (ret == SUCCESS) {
epena 1:c0429edee15b 962 dev->conv_len = conv_len;
epena 1:c0429edee15b 963 ad77681_get_frame_byte(dev);
epena 1:c0429edee15b 964 }
epena 1:c0429edee15b 965
epena 1:c0429edee15b 966 return ret;
epena 1:c0429edee15b 967 }
epena 1:c0429edee15b 968
epena 1:c0429edee15b 969 /**
epena 1:c0429edee15b 970 * Activates CRC on all SPI transactions and
epena 1:c0429edee15b 971 * Selects CRC method as XOR or 8-bit polynomial
epena 1:c0429edee15b 972 * @param dev - The device structure.
epena 1:c0429edee15b 973 * @param crc_sel - The CRC type.
epena 1:c0429edee15b 974 * Accepted values: AD77681_CRC
epena 1:c0429edee15b 975 * AD77681_XOR
epena 1:c0429edee15b 976 * AD77681_NO_CRC
epena 1:c0429edee15b 977 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 978 */
epena 1:c0429edee15b 979 int32_t ad77681_set_crc_sel(struct ad77681_dev *dev,
epena 1:c0429edee15b 980 enum ad77681_crc_sel crc_sel)
epena 1:c0429edee15b 981 {
epena 1:c0429edee15b 982 int32_t ret;
epena 1:c0429edee15b 983
epena 1:c0429edee15b 984 if (crc_sel == AD77681_NO_CRC) {
epena 1:c0429edee15b 985 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 986 AD77681_REG_INTERFACE_FORMAT,
epena 1:c0429edee15b 987 AD77681_INTERFACE_CRC_EN_MSK,
epena 1:c0429edee15b 988 AD77681_INTERFACE_CRC_EN(0));
epena 1:c0429edee15b 989 } else {
epena 1:c0429edee15b 990 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 991 AD77681_REG_INTERFACE_FORMAT,
epena 1:c0429edee15b 992 AD77681_INTERFACE_CRC_EN_MSK,
epena 1:c0429edee15b 993 AD77681_INTERFACE_CRC_EN(1));
epena 1:c0429edee15b 994
epena 1:c0429edee15b 995 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 996 AD77681_REG_INTERFACE_FORMAT,
epena 1:c0429edee15b 997 AD77681_INTERFACE_CRC_TYPE_MSK,
epena 1:c0429edee15b 998 AD77681_INTERFACE_CRC_TYPE(crc_sel));
epena 1:c0429edee15b 999 }
epena 1:c0429edee15b 1000
epena 1:c0429edee15b 1001 if (ret == SUCCESS) {
epena 1:c0429edee15b 1002 dev->crc_sel = crc_sel;
epena 1:c0429edee15b 1003 ad77681_get_frame_byte(dev);
epena 1:c0429edee15b 1004 }
epena 1:c0429edee15b 1005
epena 1:c0429edee15b 1006 return ret;
epena 1:c0429edee15b 1007 }
epena 1:c0429edee15b 1008
epena 1:c0429edee15b 1009 /**
epena 1:c0429edee15b 1010 * Enables Status bits output
epena 1:c0429edee15b 1011 * @param dev - The device structure.
epena 1:c0429edee15b 1012 * @param status_bit - enable or disable status bit
epena 1:c0429edee15b 1013 * Accepted values: true
epena 1:c0429edee15b 1014 * false
epena 1:c0429edee15b 1015 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1016 */
epena 1:c0429edee15b 1017 int32_t ad77681_set_status_bit(struct ad77681_dev *dev,
epena 1:c0429edee15b 1018 bool status_bit)
epena 1:c0429edee15b 1019 {
epena 1:c0429edee15b 1020 int32_t ret;
epena 1:c0429edee15b 1021
epena 1:c0429edee15b 1022 // Set status bit
epena 1:c0429edee15b 1023 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1024 AD77681_REG_INTERFACE_FORMAT,
epena 1:c0429edee15b 1025 AD77681_INTERFACE_STATUS_EN_MSK,
epena 1:c0429edee15b 1026 AD77681_INTERFACE_STATUS_EN(status_bit));
epena 1:c0429edee15b 1027
epena 1:c0429edee15b 1028 if (ret == SUCCESS) {
epena 1:c0429edee15b 1029 dev->status_bit = status_bit;
epena 1:c0429edee15b 1030 ad77681_get_frame_byte(dev);
epena 1:c0429edee15b 1031 }
epena 1:c0429edee15b 1032
epena 1:c0429edee15b 1033 return ret;
epena 1:c0429edee15b 1034 }
epena 1:c0429edee15b 1035
epena 1:c0429edee15b 1036 /**
epena 1:c0429edee15b 1037 * Device reset over SPI.
epena 1:c0429edee15b 1038 * @param dev - The device structure.
epena 1:c0429edee15b 1039 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1040 */
epena 1:c0429edee15b 1041 int32_t ad77681_soft_reset(struct ad77681_dev *dev)
epena 1:c0429edee15b 1042 {
epena 1:c0429edee15b 1043 int32_t ret = 0;
epena 1:c0429edee15b 1044
epena 1:c0429edee15b 1045 // Two writes are required to initialize the reset
epena 1:c0429edee15b 1046 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1047 AD77681_REG_SYNC_RESET,
epena 1:c0429edee15b 1048 AD77681_SYNC_RST_SPI_RESET_MSK,
epena 1:c0429edee15b 1049 AD77681_SYNC_RST_SPI_RESET(0x3));
epena 1:c0429edee15b 1050
epena 1:c0429edee15b 1051 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1052 AD77681_REG_SYNC_RESET,
epena 1:c0429edee15b 1053 AD77681_SYNC_RST_SPI_RESET_MSK,
epena 1:c0429edee15b 1054 AD77681_SYNC_RST_SPI_RESET(0x2));
epena 1:c0429edee15b 1055
epena 1:c0429edee15b 1056 return ret;
epena 1:c0429edee15b 1057 }
epena 1:c0429edee15b 1058
epena 1:c0429edee15b 1059 /**
epena 1:c0429edee15b 1060 * Initiate a SYNC_OUT pulse over spi
epena 1:c0429edee15b 1061 * @param dev - The device structure.
epena 1:c0429edee15b 1062 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1063 */
epena 1:c0429edee15b 1064 int32_t ad77681_initiate_sync(struct ad77681_dev *dev)
epena 1:c0429edee15b 1065 {
epena 1:c0429edee15b 1066 return ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1067 AD77681_REG_SYNC_RESET,
epena 1:c0429edee15b 1068 AD77681_SYNC_RST_SPI_STARTB_MSK,
epena 1:c0429edee15b 1069 AD77681_SYNC_RST_SPI_STARTB(0));
epena 1:c0429edee15b 1070 }
epena 1:c0429edee15b 1071
epena 1:c0429edee15b 1072 /**
epena 1:c0429edee15b 1073 * Write to offset registers
epena 1:c0429edee15b 1074 * @param dev The device structure.
epena 1:c0429edee15b 1075 * @param value The desired value of the whole 24-bit offset register
epena 1:c0429edee15b 1076 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1077 */
epena 1:c0429edee15b 1078 int32_t ad77681_apply_offset(struct ad77681_dev *dev,
epena 1:c0429edee15b 1079 uint32_t value)
epena 1:c0429edee15b 1080 {
epena 1:c0429edee15b 1081 int32_t ret;
epena 1:c0429edee15b 1082 uint8_t offset_HI = 0, offset_MID = 0, offset_LO = 0;
epena 1:c0429edee15b 1083
epena 1:c0429edee15b 1084 offset_HI = (value & 0x00FF0000) >> 16;
epena 1:c0429edee15b 1085 offset_MID = (value & 0x0000FF00) >> 8;
epena 1:c0429edee15b 1086 offset_LO = (value & 0x000000FF);
epena 1:c0429edee15b 1087
epena 1:c0429edee15b 1088 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1089 AD77681_REG_OFFSET_HI,
epena 1:c0429edee15b 1090 AD77681_OFFSET_HI_MSK,
epena 1:c0429edee15b 1091 AD77681_OFFSET_HI(offset_HI));
epena 1:c0429edee15b 1092
epena 1:c0429edee15b 1093 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1094 AD77681_REG_OFFSET_MID,
epena 1:c0429edee15b 1095 AD77681_OFFSET_MID_MSK,
epena 1:c0429edee15b 1096 AD77681_OFFSET_MID(offset_MID));
epena 1:c0429edee15b 1097
epena 1:c0429edee15b 1098 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1099 AD77681_REG_OFFSET_LO,
epena 1:c0429edee15b 1100 AD77681_OFFSET_LO_MSK,
epena 1:c0429edee15b 1101 AD77681_OFFSET_LO(offset_LO));
epena 1:c0429edee15b 1102
epena 1:c0429edee15b 1103 return ret;
epena 1:c0429edee15b 1104 }
epena 1:c0429edee15b 1105
epena 1:c0429edee15b 1106 /**
epena 1:c0429edee15b 1107 * Write to gain registers
epena 1:c0429edee15b 1108 * @param dev - The device structure.
epena 1:c0429edee15b 1109 * @param value - The desired value of the whole 24-bit gain register
epena 1:c0429edee15b 1110 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1111 */
epena 1:c0429edee15b 1112 int32_t ad77681_apply_gain(struct ad77681_dev *dev,
epena 1:c0429edee15b 1113 uint32_t value)
epena 1:c0429edee15b 1114 {
epena 1:c0429edee15b 1115 int32_t ret;
epena 1:c0429edee15b 1116 uint8_t gain_HI = 0, gain_MID = 0, gain_LO = 0;
epena 1:c0429edee15b 1117
epena 1:c0429edee15b 1118 gain_HI = (value & 0x00FF0000) >> 16;
epena 1:c0429edee15b 1119 gain_MID = (value & 0x0000FF00) >> 8;
epena 1:c0429edee15b 1120 gain_LO = (value & 0x000000FF);
epena 1:c0429edee15b 1121
epena 1:c0429edee15b 1122 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1123 AD77681_REG_GAIN_HI,
epena 1:c0429edee15b 1124 AD77681_GAIN_HI_MSK,
epena 1:c0429edee15b 1125 AD77681_GAIN_HI(gain_HI));
epena 1:c0429edee15b 1126
epena 1:c0429edee15b 1127 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1128 AD77681_REG_GAIN_MID,
epena 1:c0429edee15b 1129 AD77681_GAIN_MID_MSK,
epena 1:c0429edee15b 1130 AD77681_GAIN_MID(gain_MID));
epena 1:c0429edee15b 1131
epena 1:c0429edee15b 1132 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1133 AD77681_REG_GAIN_LO,
epena 1:c0429edee15b 1134 AD77681_GAIN_LOW_MSK,
epena 1:c0429edee15b 1135 AD77681_GAIN_LOW(gain_LO));
epena 1:c0429edee15b 1136
epena 1:c0429edee15b 1137 return ret;
epena 1:c0429edee15b 1138 }
epena 1:c0429edee15b 1139
epena 1:c0429edee15b 1140 /**
epena 1:c0429edee15b 1141 * Upload sequence for Programmamble FIR filter
epena 1:c0429edee15b 1142 * @param dev - The device structure.
epena 1:c0429edee15b 1143 * @param coeffs - Pointer to the desired filter coefficients array to be written
epena 1:c0429edee15b 1144 * @param num_coeffs - Count of active filter coeffs
epena 1:c0429edee15b 1145 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1146 */
epena 1:c0429edee15b 1147 int32_t ad77681_programmable_filter(struct ad77681_dev *dev,
epena 1:c0429edee15b 1148 const float *coeffs,
epena 1:c0429edee15b 1149 uint8_t num_coeffs)
epena 1:c0429edee15b 1150 {
epena 1:c0429edee15b 1151 uint8_t coeffs_buf[4], coeffs_index, check_back = 0, i, address;
epena 1:c0429edee15b 1152 uint32_t twait;
epena 1:c0429edee15b 1153 int32_t twos_complement, ret;
epena 1:c0429edee15b 1154 const uint8_t coeff_reg_length = 56;
epena 1:c0429edee15b 1155
epena 1:c0429edee15b 1156 /* Specific keys in the upload sequence */
epena 1:c0429edee15b 1157 const uint8_t key1 = 0xAC, key2 = 0x45, key3 = 0x55;
epena 1:c0429edee15b 1158 /* Scaling factor for all coefficients 2^22 */
epena 1:c0429edee15b 1159 const float coeff_scale_factor = (1 << 22);
epena 1:c0429edee15b 1160 /* Wait time in uS necessary to access the COEFF_CONTROL and */
epena 1:c0429edee15b 1161 /* COEFF_DATA registers. Twait = 512/MCLK */
epena 1:c0429edee15b 1162 twait = (uint32_t)(((512.0) / ((float)(dev->mclk))) * 1000.0) + 1;
epena 1:c0429edee15b 1163
epena 1:c0429edee15b 1164 /* Set Filter to FIR */
epena 1:c0429edee15b 1165 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1166 AD77681_REG_DIGITAL_FILTER,
epena 1:c0429edee15b 1167 AD77681_DIGI_FILTER_FILTER_MSK,
epena 1:c0429edee15b 1168 AD77681_DIGI_FILTER_FILTER(AD77681_FIR));
epena 1:c0429edee15b 1169
epena 1:c0429edee15b 1170 /* Check return value before proceeding */
epena 1:c0429edee15b 1171 if (ret < 0)
epena 1:c0429edee15b 1172 return ret;
epena 1:c0429edee15b 1173
epena 1:c0429edee15b 1174 /* Write the first access key to the ACCESS_KEY register */
epena 1:c0429edee15b 1175 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1176 AD77681_REG_ACCESS_KEY,
epena 1:c0429edee15b 1177 AD77681_ACCESS_KEY_MSK,
epena 1:c0429edee15b 1178 AD77681_ACCESS_KEY(key1));
epena 1:c0429edee15b 1179
epena 1:c0429edee15b 1180 /* Check return value before proceeding */
epena 1:c0429edee15b 1181 if (ret < 0)
epena 1:c0429edee15b 1182 return ret;
epena 1:c0429edee15b 1183
epena 1:c0429edee15b 1184 /* Write the second access key to the ACCESS_KEY register */
epena 1:c0429edee15b 1185 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1186 AD77681_REG_ACCESS_KEY,
epena 1:c0429edee15b 1187 AD77681_ACCESS_KEY_MSK,
epena 1:c0429edee15b 1188 AD77681_ACCESS_KEY(key2));
epena 1:c0429edee15b 1189
epena 1:c0429edee15b 1190 /* Check return value before proceeding */
epena 1:c0429edee15b 1191 if (ret < 0)
epena 1:c0429edee15b 1192 return ret;
epena 1:c0429edee15b 1193
epena 1:c0429edee15b 1194 /* Read the the ACCESS_KEY register bit 0, the key bit */
epena 1:c0429edee15b 1195 ret = ad77681_spi_read_mask(dev,
epena 1:c0429edee15b 1196 AD77681_REG_ACCESS_KEY,
epena 1:c0429edee15b 1197 AD77681_ACCESS_KEY_CHECK_MSK,
epena 1:c0429edee15b 1198 &check_back);
epena 1:c0429edee15b 1199
epena 1:c0429edee15b 1200 /* Checks ret and key bit, return FAILURE in case key bit not equal to 1 */
epena 1:c0429edee15b 1201 if ((ret < 0) || (check_back != 1))
epena 1:c0429edee15b 1202 return FAILURE;
epena 1:c0429edee15b 1203
epena 1:c0429edee15b 1204 /* Set the initial adress to 0 and enable the write and coefficient access bits */
epena 1:c0429edee15b 1205 address = AD77681_COEF_CONTROL_COEFFACCESSEN_MSK
epena 1:c0429edee15b 1206 | AD77681_COEF_CONTROL_COEFFWRITEEN_MSK;
epena 1:c0429edee15b 1207
epena 1:c0429edee15b 1208 /* The COEFF_DATA register has to be filled with 56 coeffs.*/
epena 1:c0429edee15b 1209 /* In case the number of active filter coefficient is less */
epena 1:c0429edee15b 1210 /* than 56, zeros will be padded before the desired coeff. */
epena 1:c0429edee15b 1211 for (i = 0; i < coeff_reg_length; i++) {
epena 1:c0429edee15b 1212 /* Set the coeff address */
epena 1:c0429edee15b 1213 ret = ad77681_spi_reg_write(dev,
epena 1:c0429edee15b 1214 AD77681_REG_COEFF_CONTROL,
epena 1:c0429edee15b 1215 address);
epena 1:c0429edee15b 1216
epena 1:c0429edee15b 1217 /* Check return value before proceeding */
epena 1:c0429edee15b 1218 if (ret < 0)
epena 1:c0429edee15b 1219 return ret;
epena 1:c0429edee15b 1220
epena 1:c0429edee15b 1221 /* Wait for Twait uSeconds*/
epena 1:c0429edee15b 1222 udelay(twait);
epena 1:c0429edee15b 1223
epena 1:c0429edee15b 1224 /* Padding of zeros before the desired coef in case the coef count in less than 56 */
epena 1:c0429edee15b 1225 if((num_coeffs + i) < coeff_reg_length) {
epena 1:c0429edee15b 1226 /* wirte zeroes to COEFF_DATA, in case of less coeffs than 56*/
epena 1:c0429edee15b 1227 coeffs_buf[0] = AD77681_REG_WRITE(AD77681_REG_COEFF_DATA);
epena 1:c0429edee15b 1228 coeffs_buf[1] = 0;
epena 1:c0429edee15b 1229 coeffs_buf[2] = 0;
epena 1:c0429edee15b 1230 coeffs_buf[3] = 0;
epena 1:c0429edee15b 1231 } else {/* Writting of desired filter coefficients */
epena 1:c0429edee15b 1232 /* Computes the index of coefficients to be uploaded */
epena 1:c0429edee15b 1233 coeffs_index = (num_coeffs + i) - coeff_reg_length;
epena 1:c0429edee15b 1234 /* Scaling the coefficient value and converting it to 2's complement */
epena 1:c0429edee15b 1235 twos_complement = (int32_t)(coeffs[coeffs_index] * coeff_scale_factor);
epena 1:c0429edee15b 1236
epena 1:c0429edee15b 1237 /* Write coefficients to COEFF_DATA */
epena 1:c0429edee15b 1238 coeffs_buf[0] = AD77681_REG_WRITE(AD77681_REG_COEFF_DATA);
epena 1:c0429edee15b 1239 coeffs_buf[1] = (twos_complement & 0xFF0000) >> 16;
epena 1:c0429edee15b 1240 coeffs_buf[2] = (twos_complement & 0x00FF00) >> 8;
epena 1:c0429edee15b 1241 coeffs_buf[3] = (twos_complement & 0x0000FF);
epena 1:c0429edee15b 1242 }
epena 1:c0429edee15b 1243
epena 1:c0429edee15b 1244 ret = spi_write_and_read(dev->spi_desc, coeffs_buf, 4);
epena 1:c0429edee15b 1245
epena 1:c0429edee15b 1246 /* Check return value before proceeding */
epena 1:c0429edee15b 1247 if (ret < 0)
epena 1:c0429edee15b 1248 return ret;
epena 1:c0429edee15b 1249
epena 1:c0429edee15b 1250 /* Increment the address*/
epena 1:c0429edee15b 1251 address++;
epena 1:c0429edee15b 1252 /* Wait for Twait uSeconds*/
epena 1:c0429edee15b 1253 udelay(twait);
epena 1:c0429edee15b 1254 }
epena 1:c0429edee15b 1255
epena 1:c0429edee15b 1256 /* Disable coefficient write */
epena 1:c0429edee15b 1257 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1258 AD77681_REG_COEFF_CONTROL,
epena 1:c0429edee15b 1259 AD77681_COEF_CONTROL_COEFFWRITEEN_MSK,
epena 1:c0429edee15b 1260 AD77681_COEF_CONTROL_COEFFWRITEEN(0x00));
epena 1:c0429edee15b 1261
epena 1:c0429edee15b 1262 /* Check return value before proceeding */
epena 1:c0429edee15b 1263 if (ret < 0)
epena 1:c0429edee15b 1264 return ret;
epena 1:c0429edee15b 1265
epena 1:c0429edee15b 1266 udelay(twait);
epena 1:c0429edee15b 1267
epena 1:c0429edee15b 1268 /* Disable coefficient access */
epena 1:c0429edee15b 1269 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1270 AD77681_REG_COEFF_CONTROL,
epena 1:c0429edee15b 1271 AD77681_COEF_CONTROL_COEFFACCESSEN_MSK,
epena 1:c0429edee15b 1272 AD77681_COEF_CONTROL_COEFFACCESSEN(0x00));
epena 1:c0429edee15b 1273
epena 1:c0429edee15b 1274 /* Check return value before proceeding */
epena 1:c0429edee15b 1275 if (ret < 0)
epena 1:c0429edee15b 1276 return ret;
epena 1:c0429edee15b 1277
epena 1:c0429edee15b 1278 /* Toggle the synchronization pulse and to begin reading data */
epena 1:c0429edee15b 1279 /* Write 0x800000 to COEFF_DATA */
epena 1:c0429edee15b 1280 coeffs_buf[0] = AD77681_REG_WRITE(AD77681_REG_COEFF_DATA);
epena 1:c0429edee15b 1281 coeffs_buf[1] = 0x80;
epena 1:c0429edee15b 1282 coeffs_buf[2] = 0x00;
epena 1:c0429edee15b 1283 coeffs_buf[3] = 0x00;
epena 1:c0429edee15b 1284
epena 1:c0429edee15b 1285 ret = spi_write_and_read(dev->spi_desc, coeffs_buf, 4);
epena 1:c0429edee15b 1286
epena 1:c0429edee15b 1287 /* Check return value before proceeding */
epena 1:c0429edee15b 1288 if (ret < 0)
epena 1:c0429edee15b 1289 return ret;
epena 1:c0429edee15b 1290
epena 1:c0429edee15b 1291 /* Exit filter upload by wirting specific access key 0x55*/
epena 1:c0429edee15b 1292 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1293 AD77681_REG_ACCESS_KEY,
epena 1:c0429edee15b 1294 AD77681_ACCESS_KEY_MSK,
epena 1:c0429edee15b 1295 AD77681_ACCESS_KEY(key3));
epena 1:c0429edee15b 1296
epena 1:c0429edee15b 1297 /* Check return value before proceeding */
epena 1:c0429edee15b 1298 if (ret < 0)
epena 1:c0429edee15b 1299 return ret;
epena 1:c0429edee15b 1300
epena 1:c0429edee15b 1301 /* Send synchronization pulse */
epena 1:c0429edee15b 1302 ad77681_initiate_sync(dev);
epena 1:c0429edee15b 1303
epena 1:c0429edee15b 1304 return ret;
epena 1:c0429edee15b 1305 }
epena 1:c0429edee15b 1306
epena 1:c0429edee15b 1307 /**
epena 1:c0429edee15b 1308 * Read value from GPIOs present in AD7768-1 separately, or all GPIOS at once.
epena 1:c0429edee15b 1309 * @param dev - The device structure.
epena 1:c0429edee15b 1310 * @param value - Readed value.
epena 1:c0429edee15b 1311 * @param gpio_number - Number of GPIO, the value will be written into
epena 1:c0429edee15b 1312 * Accepted values: AD77681_GPIO0
epena 1:c0429edee15b 1313 * AD77681_GPIO1
epena 1:c0429edee15b 1314 * AD77681_GPIO2
epena 1:c0429edee15b 1315 * AD77681_GPIO3
epena 1:c0429edee15b 1316 * AD77681_ALL_GPIOS
epena 1:c0429edee15b 1317 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1318 */
epena 1:c0429edee15b 1319 int32_t ad77681_gpio_read(struct ad77681_dev *dev,
epena 1:c0429edee15b 1320 uint8_t *value,
epena 1:c0429edee15b 1321 enum ad77681_gpios gpio_number)
epena 1:c0429edee15b 1322 {
epena 1:c0429edee15b 1323 int32_t ret;
epena 1:c0429edee15b 1324
epena 1:c0429edee15b 1325 switch (gpio_number) {
epena 1:c0429edee15b 1326 case AD77681_GPIO0: /* Read to GPIO0 */
epena 1:c0429edee15b 1327 ret = ad77681_spi_read_mask(dev,
epena 1:c0429edee15b 1328 AD77681_REG_GPIO_READ,
epena 1:c0429edee15b 1329 AD77681_GPIO_READ_0_MSK,
epena 1:c0429edee15b 1330 value);
epena 1:c0429edee15b 1331 break;
epena 1:c0429edee15b 1332 case AD77681_GPIO1: /* Read to GPIO1 */
epena 1:c0429edee15b 1333 ret = ad77681_spi_read_mask(dev,
epena 1:c0429edee15b 1334 AD77681_REG_GPIO_READ,
epena 1:c0429edee15b 1335 AD77681_GPIO_READ_1_MSK,
epena 1:c0429edee15b 1336 value);
epena 1:c0429edee15b 1337 break;
epena 1:c0429edee15b 1338 case AD77681_GPIO2: /* Read to GPIO2 */
epena 1:c0429edee15b 1339 ret = ad77681_spi_read_mask(dev,
epena 1:c0429edee15b 1340 AD77681_REG_GPIO_READ,
epena 1:c0429edee15b 1341 AD77681_GPIO_READ_2_MSK,
epena 1:c0429edee15b 1342 value);
epena 1:c0429edee15b 1343 break;
epena 1:c0429edee15b 1344 case AD77681_GPIO3: /* Read to GPIO3 */
epena 1:c0429edee15b 1345 ret = ad77681_spi_read_mask(dev,
epena 1:c0429edee15b 1346 AD77681_REG_GPIO_READ,
epena 1:c0429edee15b 1347 AD77681_GPIO_READ_3_MSK,
epena 1:c0429edee15b 1348 value);
epena 1:c0429edee15b 1349 break;
epena 1:c0429edee15b 1350 case AD77681_ALL_GPIOS: /* Read to all GPIOs */
epena 1:c0429edee15b 1351 ret = ad77681_spi_read_mask(dev,
epena 1:c0429edee15b 1352 AD77681_REG_GPIO_READ,
epena 1:c0429edee15b 1353 AD77681_GPIO_READ_ALL_MSK,
epena 1:c0429edee15b 1354 value);
epena 1:c0429edee15b 1355 break;
epena 1:c0429edee15b 1356 default:
epena 1:c0429edee15b 1357 return FAILURE;
epena 1:c0429edee15b 1358 break;
epena 1:c0429edee15b 1359 }
epena 1:c0429edee15b 1360
epena 1:c0429edee15b 1361 return ret;
epena 1:c0429edee15b 1362 }
epena 1:c0429edee15b 1363
epena 1:c0429edee15b 1364 /**
epena 1:c0429edee15b 1365 * Write value to GPIOs present in AD7768-1 separately, or all GPIOS at once.
epena 1:c0429edee15b 1366 * @param dev - The device structure.
epena 1:c0429edee15b 1367 * @param value - Value to be written into GPIO
epena 1:c0429edee15b 1368 * Accepted values: GPIO_HIGH
epena 1:c0429edee15b 1369 * GPIO_LOW
epena 1:c0429edee15b 1370 * 4-bit value for all gpios
epena 1:c0429edee15b 1371 * @param gpio_number - Number of GPIO, the value will be written into
epena 1:c0429edee15b 1372 * Accepted values: AD77681_GPIO0
epena 1:c0429edee15b 1373 * AD77681_GPIO1
epena 1:c0429edee15b 1374 * AD77681_GPIO2
epena 1:c0429edee15b 1375 * AD77681_GPIO3
epena 1:c0429edee15b 1376 * AD77681_ALL_GPIOS
epena 1:c0429edee15b 1377 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1378 */
epena 1:c0429edee15b 1379 int32_t ad77681_gpio_write(struct ad77681_dev *dev,
epena 1:c0429edee15b 1380 uint8_t value,
epena 1:c0429edee15b 1381 enum ad77681_gpios gpio_number)
epena 1:c0429edee15b 1382 {
epena 1:c0429edee15b 1383 int32_t ret;
epena 1:c0429edee15b 1384
epena 1:c0429edee15b 1385 switch (gpio_number) {
epena 1:c0429edee15b 1386 case AD77681_GPIO0: /* Write to GPIO0 */
epena 1:c0429edee15b 1387 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1388 AD77681_REG_GPIO_WRITE,
epena 1:c0429edee15b 1389 AD77681_GPIO_WRITE_0_MSK,
epena 1:c0429edee15b 1390 AD77681_GPIO_WRITE_0(value));
epena 1:c0429edee15b 1391 break;
epena 1:c0429edee15b 1392 case AD77681_GPIO1: /* Write to GPIO1 */
epena 1:c0429edee15b 1393 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1394 AD77681_REG_GPIO_WRITE,
epena 1:c0429edee15b 1395 AD77681_GPIO_WRITE_1_MSK,
epena 1:c0429edee15b 1396 AD77681_GPIO_WRITE_1(value));
epena 1:c0429edee15b 1397 break;
epena 1:c0429edee15b 1398 case AD77681_GPIO2: /* Write to GPIO2 */
epena 1:c0429edee15b 1399 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1400 AD77681_REG_GPIO_WRITE,
epena 1:c0429edee15b 1401 AD77681_GPIO_WRITE_2_MSK,
epena 1:c0429edee15b 1402 AD77681_GPIO_WRITE_2(value));
epena 1:c0429edee15b 1403 break;
epena 1:c0429edee15b 1404 case AD77681_GPIO3: /* Write to GPIO3 */
epena 1:c0429edee15b 1405 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1406 AD77681_REG_GPIO_WRITE,
epena 1:c0429edee15b 1407 AD77681_GPIO_WRITE_3_MSK,
epena 1:c0429edee15b 1408 AD77681_GPIO_WRITE_3(value));
epena 1:c0429edee15b 1409 break;
epena 1:c0429edee15b 1410 case AD77681_ALL_GPIOS: /* Write to all GPIOs */
epena 1:c0429edee15b 1411 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1412 AD77681_REG_GPIO_WRITE,
epena 1:c0429edee15b 1413 AD77681_GPIO_WRITE_ALL_MSK,
epena 1:c0429edee15b 1414 AD77681_GPIO_WRITE_ALL(value));
epena 1:c0429edee15b 1415 break;
epena 1:c0429edee15b 1416 default:
epena 1:c0429edee15b 1417 return FAILURE;
epena 1:c0429edee15b 1418 break;
epena 1:c0429edee15b 1419 }
epena 1:c0429edee15b 1420
epena 1:c0429edee15b 1421 return ret;
epena 1:c0429edee15b 1422 }
epena 1:c0429edee15b 1423
epena 1:c0429edee15b 1424 /**
epena 1:c0429edee15b 1425 * Set AD7768-1s GPIO as input or output.
epena 1:c0429edee15b 1426 * @param dev - The device structure.
epena 1:c0429edee15b 1427 * @param direction - Direction of the GPIO
epena 1:c0429edee15b 1428 * Accepted values: GPIO_INPUT
epena 1:c0429edee15b 1429 * GPIO_OUTPUT
epena 1:c0429edee15b 1430 * 4-bit value for all gpios
epena 1:c0429edee15b 1431 * @param gpio_number - Number of GPIO, which will be affected
epena 1:c0429edee15b 1432 * Accepted values: AD77681_GPIO0
epena 1:c0429edee15b 1433 * AD77681_GPIO1
epena 1:c0429edee15b 1434 * AD77681_GPIO2
epena 1:c0429edee15b 1435 * AD77681_GPIO3
epena 1:c0429edee15b 1436 * AD77681_ALL_GPIOS
epena 1:c0429edee15b 1437 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1438 */
epena 1:c0429edee15b 1439 int32_t ad77681_gpio_inout(struct ad77681_dev *dev,
epena 1:c0429edee15b 1440 uint8_t direction,
epena 1:c0429edee15b 1441 enum ad77681_gpios gpio_number)
epena 1:c0429edee15b 1442 {
epena 1:c0429edee15b 1443 int32_t ret;
epena 1:c0429edee15b 1444
epena 1:c0429edee15b 1445 switch (gpio_number) {
epena 1:c0429edee15b 1446 case AD77681_GPIO0: /* Set direction of GPIO0 */
epena 1:c0429edee15b 1447 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1448 AD77681_REG_GPIO_CONTROL,
epena 1:c0429edee15b 1449 AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK,
epena 1:c0429edee15b 1450 AD77681_GPIO_CNTRL_GPIO0_OP_EN(direction));
epena 1:c0429edee15b 1451 break;
epena 1:c0429edee15b 1452 case AD77681_GPIO1: /* Set direction of GPIO1 */
epena 1:c0429edee15b 1453 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1454 AD77681_REG_GPIO_CONTROL,
epena 1:c0429edee15b 1455 AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK,
epena 1:c0429edee15b 1456 AD77681_GPIO_CNTRL_GPIO1_OP_EN(direction));
epena 1:c0429edee15b 1457 break;
epena 1:c0429edee15b 1458 case AD77681_GPIO2: /* Set direction of GPIO2 */
epena 1:c0429edee15b 1459 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1460 AD77681_REG_GPIO_CONTROL,
epena 1:c0429edee15b 1461 AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK,
epena 1:c0429edee15b 1462 AD77681_GPIO_CNTRL_GPIO2_OP_EN(direction));
epena 1:c0429edee15b 1463 break;
epena 1:c0429edee15b 1464 case AD77681_GPIO3: /* Set direction of GPIO3 */
epena 1:c0429edee15b 1465 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1466 AD77681_REG_GPIO_CONTROL,
epena 1:c0429edee15b 1467 AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK,
epena 1:c0429edee15b 1468 AD77681_GPIO_CNTRL_GPIO3_OP_EN(direction));
epena 1:c0429edee15b 1469 break;
epena 1:c0429edee15b 1470 case AD77681_ALL_GPIOS: /* Set direction of all GPIOs */
epena 1:c0429edee15b 1471 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1472 AD77681_REG_GPIO_CONTROL,
epena 1:c0429edee15b 1473 AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK,
epena 1:c0429edee15b 1474 AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN(direction));
epena 1:c0429edee15b 1475 break;
epena 1:c0429edee15b 1476 default:
epena 1:c0429edee15b 1477 return FAILURE;
epena 1:c0429edee15b 1478 break;
epena 1:c0429edee15b 1479 }
epena 1:c0429edee15b 1480
epena 1:c0429edee15b 1481 return ret;
epena 1:c0429edee15b 1482 }
epena 1:c0429edee15b 1483
epena 1:c0429edee15b 1484 /**
epena 1:c0429edee15b 1485 * Enable global GPIO bit.
epena 1:c0429edee15b 1486 * This bit must be set high to change GPIO settings.
epena 1:c0429edee15b 1487 * @param dev - The device structure.
epena 1:c0429edee15b 1488 * @param gpio_enable - Enable or diable the global GPIO pin
epena 1:c0429edee15b 1489 * Accepted values: AD77681_GLOBAL_GPIO_ENABLE
epena 1:c0429edee15b 1490 * AD77681_GLOBAL_GPIO_DISABLE
epena 1:c0429edee15b 1491 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1492 */
epena 1:c0429edee15b 1493 int32_t ad77681_global_gpio(struct ad77681_dev *dev,
epena 1:c0429edee15b 1494 enum ad77681_gobal_gpio_enable gpio_enable)
epena 1:c0429edee15b 1495 {
epena 1:c0429edee15b 1496 return ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1497 AD77681_REG_GPIO_CONTROL,
epena 1:c0429edee15b 1498 AD77681_GPIO_CNTRL_UGPIO_EN_MSK,
epena 1:c0429edee15b 1499 AD77681_GPIO_CNTRL_UGPIO_EN(gpio_enable));
epena 1:c0429edee15b 1500 }
epena 1:c0429edee15b 1501
epena 1:c0429edee15b 1502 /**
epena 1:c0429edee15b 1503 * Read and write from ADC scratchpad register to check SPI Communication in
epena 1:c0429edee15b 1504 * the very beginning, during inicialization.
epena 1:c0429edee15b 1505 * @param dev - The device structure.
epena 1:c0429edee15b 1506 * @param sequence - The sequence which will be written into scratchpad and the
epena 1:c0429edee15b 1507 * readed sequence will be returned
epena 1:c0429edee15b 1508 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1509 */
epena 1:c0429edee15b 1510 int32_t ad77681_scratchpad(struct ad77681_dev *dev,
epena 1:c0429edee15b 1511 uint8_t *sequence)
epena 1:c0429edee15b 1512 {
epena 1:c0429edee15b 1513 int32_t ret;
epena 1:c0429edee15b 1514 const uint8_t check = *sequence;/* Save the original sequence */
epena 1:c0429edee15b 1515 uint8_t ret_sequence = 0;/* Return sequence */
epena 1:c0429edee15b 1516
epena 1:c0429edee15b 1517 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1518 AD77681_REG_SCRATCH_PAD,
epena 1:c0429edee15b 1519 AD77681_SCRATCHPAD_MSK,
epena 1:c0429edee15b 1520 AD77681_SCRATCHPAD(check));
epena 1:c0429edee15b 1521
epena 1:c0429edee15b 1522 ret |= ad77681_spi_read_mask(dev,
epena 1:c0429edee15b 1523 AD77681_REG_SCRATCH_PAD,
epena 1:c0429edee15b 1524 AD77681_SCRATCHPAD_MSK,
epena 1:c0429edee15b 1525 &ret_sequence);
epena 1:c0429edee15b 1526
epena 1:c0429edee15b 1527 if (check != ret_sequence)/* Compare original an returned sequence */
epena 1:c0429edee15b 1528 return FAILURE;
epena 1:c0429edee15b 1529
epena 1:c0429edee15b 1530 return ret;
epena 1:c0429edee15b 1531 }
epena 1:c0429edee15b 1532
epena 1:c0429edee15b 1533 /**
epena 1:c0429edee15b 1534 * Set AD7768-1s GPIO output type between strong driver and open drain.
epena 1:c0429edee15b 1535 * GPIO3 can not be accessed!
epena 1:c0429edee15b 1536 * @param dev - The device structure.
epena 1:c0429edee15b 1537 * @param gpio_number - AD7768-1s GPIO to be affected (Only GPIO0, GPIO1 and GPIO2)
epena 1:c0429edee15b 1538 * Accepted values: AD77681_GPIO0
epena 1:c0429edee15b 1539 * AD77681_GPIO1
epena 1:c0429edee15b 1540 * AD77681_GPIO2
epena 1:c0429edee15b 1541 * AD77681_ALL_GPIOS
epena 1:c0429edee15b 1542 *
epena 1:c0429edee15b 1543 * @param output_type - Output type of the GPIO
epena 1:c0429edee15b 1544 * Accepted values: AD77681_GPIO_STRONG_DRIVER
epena 1:c0429edee15b 1545 * AD77681_GPIO_OPEN_DRAIN
epena 1:c0429edee15b 1546 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1547 */
epena 1:c0429edee15b 1548 int32_t ad77681_gpio_open_drain(struct ad77681_dev *dev,
epena 1:c0429edee15b 1549 enum ad77681_gpios gpio_number,
epena 1:c0429edee15b 1550 enum ad77681_gpio_output_type output_type)
epena 1:c0429edee15b 1551 {
epena 1:c0429edee15b 1552 int32_t ret;
epena 1:c0429edee15b 1553
epena 1:c0429edee15b 1554 switch (gpio_number) {
epena 1:c0429edee15b 1555 case AD77681_GPIO0: /* Set ouptut type of GPIO0 */
epena 1:c0429edee15b 1556 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1557 AD77681_REG_GPIO_CONTROL,
epena 1:c0429edee15b 1558 AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK,
epena 1:c0429edee15b 1559 AD77681_GPIO_CNTRL_GPIO0_OD_EN(output_type));
epena 1:c0429edee15b 1560 break;
epena 1:c0429edee15b 1561 case AD77681_GPIO1: /* Set ouptut type of GPIO1 */
epena 1:c0429edee15b 1562 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1563 AD77681_REG_GPIO_CONTROL,
epena 1:c0429edee15b 1564 AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK,
epena 1:c0429edee15b 1565 AD77681_GPIO_CNTRL_GPIO1_OD_EN(output_type));
epena 1:c0429edee15b 1566 break;
epena 1:c0429edee15b 1567 case AD77681_GPIO2: /* Set ouptut type of GPIO2 */
epena 1:c0429edee15b 1568 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1569 AD77681_REG_GPIO_CONTROL,
epena 1:c0429edee15b 1570 AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK,
epena 1:c0429edee15b 1571 AD77681_GPIO_CNTRL_GPIO2_OD_EN(output_type));
epena 1:c0429edee15b 1572 break;
epena 1:c0429edee15b 1573 case AD77681_ALL_GPIOS: /* Set ouptut type of all GPIOs */
epena 1:c0429edee15b 1574 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1575 AD77681_REG_GPIO_CONTROL,
epena 1:c0429edee15b 1576 AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK,
epena 1:c0429edee15b 1577 AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN(output_type));
epena 1:c0429edee15b 1578 break;
epena 1:c0429edee15b 1579 default:
epena 1:c0429edee15b 1580 return FAILURE;
epena 1:c0429edee15b 1581 break;
epena 1:c0429edee15b 1582 }
epena 1:c0429edee15b 1583
epena 1:c0429edee15b 1584 return ret;
epena 1:c0429edee15b 1585 }
epena 1:c0429edee15b 1586
epena 1:c0429edee15b 1587 /**
epena 1:c0429edee15b 1588 * Clear all error flags at once
epena 1:c0429edee15b 1589 * @param dev - The device structure.
epena 1:c0429edee15b 1590 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1591 */
epena 1:c0429edee15b 1592 int32_t ad77681_clear_error_flags(struct ad77681_dev *dev)
epena 1:c0429edee15b 1593 {
epena 1:c0429edee15b 1594 int32_t ret;
epena 1:c0429edee15b 1595
epena 1:c0429edee15b 1596 /* SPI ignore error CLEAR */
epena 1:c0429edee15b 1597 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1598 AD77681_REG_SPI_DIAG_STATUS,
epena 1:c0429edee15b 1599 AD77681_SPI_IGNORE_ERROR_MSK,
epena 1:c0429edee15b 1600 AD77681_SPI_IGNORE_ERROR_CLR(ENABLE));
epena 1:c0429edee15b 1601 /* SPI read error CLEAR */
epena 1:c0429edee15b 1602 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1603 AD77681_REG_SPI_DIAG_STATUS,
epena 1:c0429edee15b 1604 AD77681_SPI_READ_ERROR_MSK,
epena 1:c0429edee15b 1605 AD77681_SPI_READ_ERROR_CLR(ENABLE));
epena 1:c0429edee15b 1606 /* SPI write error CLEAR */
epena 1:c0429edee15b 1607 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1608 AD77681_REG_SPI_DIAG_STATUS,
epena 1:c0429edee15b 1609 AD77681_SPI_WRITE_ERROR_MSK,
epena 1:c0429edee15b 1610 AD77681_SPI_WRITE_ERROR_CLR(ENABLE));
epena 1:c0429edee15b 1611 /* SPI CRC error CLEAR */
epena 1:c0429edee15b 1612 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1613 AD77681_REG_SPI_DIAG_STATUS,
epena 1:c0429edee15b 1614 AD77681_SPI_CRC_ERROR_MSK,
epena 1:c0429edee15b 1615 AD77681_SPI_CRC_ERROR_CLR(ENABLE));
epena 1:c0429edee15b 1616
epena 1:c0429edee15b 1617 return ret;
epena 1:c0429edee15b 1618 }
epena 1:c0429edee15b 1619
epena 1:c0429edee15b 1620 /**
epena 1:c0429edee15b 1621 * Enabling error flags. All error flags enabled by default
epena 1:c0429edee15b 1622 * @param dev - The device structure.
epena 1:c0429edee15b 1623 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1624 */
epena 1:c0429edee15b 1625 int32_t ad77681_error_flags_enabe(struct ad77681_dev *dev)
epena 1:c0429edee15b 1626 {
epena 1:c0429edee15b 1627 int32_t ret;
epena 1:c0429edee15b 1628
epena 1:c0429edee15b 1629 /* SPI ERRORS ENABLE */
epena 1:c0429edee15b 1630 /* SPI ignore error enable */
epena 1:c0429edee15b 1631 ret = ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1632 AD77681_REG_SPI_DIAG_ENABLE,
epena 1:c0429edee15b 1633 AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK,
epena 1:c0429edee15b 1634 AD77681_SPI_DIAG_ERR_SPI_IGNORE(ENABLE));
epena 1:c0429edee15b 1635 /* SPI Clock count error enable */
epena 1:c0429edee15b 1636 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1637 AD77681_REG_SPI_DIAG_ENABLE,
epena 1:c0429edee15b 1638 AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK,
epena 1:c0429edee15b 1639 AD77681_SPI_DIAG_ERR_SPI_CLK_CNT(ENABLE));
epena 1:c0429edee15b 1640 /* SPI Read error enable */
epena 1:c0429edee15b 1641 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1642 AD77681_REG_SPI_DIAG_ENABLE,
epena 1:c0429edee15b 1643 AD77681_SPI_DIAG_ERR_SPI_RD_MSK,
epena 1:c0429edee15b 1644 AD77681_SPI_DIAG_ERR_SPI_RD(ENABLE));
epena 1:c0429edee15b 1645 /* SPI Write error enable */
epena 1:c0429edee15b 1646 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1647 AD77681_REG_SPI_DIAG_ENABLE,
epena 1:c0429edee15b 1648 AD77681_SPI_DIAG_ERR_SPI_WR_MSK,
epena 1:c0429edee15b 1649 AD77681_SPI_DIAG_ERR_SPI_WR(ENABLE));
epena 1:c0429edee15b 1650
epena 1:c0429edee15b 1651 /* ADC DIAG ERRORS ENABLE */
epena 1:c0429edee15b 1652 /* DLDO PSM error enable */
epena 1:c0429edee15b 1653 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1654 AD77681_REG_ADC_DIAG_ENABLE,
epena 1:c0429edee15b 1655 AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK,
epena 1:c0429edee15b 1656 AD77681_ADC_DIAG_ERR_DLDO_PSM(ENABLE));
epena 1:c0429edee15b 1657 /* ALDO PSM error enable */
epena 1:c0429edee15b 1658 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1659 AD77681_REG_ADC_DIAG_ENABLE,
epena 1:c0429edee15b 1660 AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK,
epena 1:c0429edee15b 1661 AD77681_ADC_DIAG_ERR_ALDO_PSM(ENABLE));
epena 1:c0429edee15b 1662 /* Filter saturated error enable */
epena 1:c0429edee15b 1663 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1664 AD77681_REG_ADC_DIAG_ENABLE,
epena 1:c0429edee15b 1665 AD77681_ADC_DIAG_ERR_FILT_SAT_MSK,
epena 1:c0429edee15b 1666 AD77681_ADC_DIAG_ERR_FILT_SAT(ENABLE));
epena 1:c0429edee15b 1667 /* Filter not settled error enable */
epena 1:c0429edee15b 1668 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1669 AD77681_REG_ADC_DIAG_ENABLE,
epena 1:c0429edee15b 1670 AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK,
epena 1:c0429edee15b 1671 AD77681_ADC_DIAG_ERR_FILT_NOT_SET(ENABLE));
epena 1:c0429edee15b 1672 /* External clock check error enable */
epena 1:c0429edee15b 1673 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1674 AD77681_REG_ADC_DIAG_ENABLE,
epena 1:c0429edee15b 1675 AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK,
epena 1:c0429edee15b 1676 AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL(ENABLE));
epena 1:c0429edee15b 1677
epena 1:c0429edee15b 1678 /* DIG DIAG ENABLE */
epena 1:c0429edee15b 1679 /* Memory map CRC error enabled */
epena 1:c0429edee15b 1680 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1681 AD77681_REG_DIG_DIAG_ENABLE,
epena 1:c0429edee15b 1682 AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK,
epena 1:c0429edee15b 1683 AD77681_DIG_DIAG_ERR_MEMMAP_CRC(ENABLE));
epena 1:c0429edee15b 1684 /* RAM CRC error enabled */
epena 1:c0429edee15b 1685 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1686 AD77681_REG_DIG_DIAG_ENABLE,
epena 1:c0429edee15b 1687 AD77681_DIG_DIAG_ERR_RAM_CRC_MSK,
epena 1:c0429edee15b 1688 AD77681_DIG_DIAG_ERR_RAM_CRC(ENABLE));
epena 1:c0429edee15b 1689 /* FUSE CRC error enabled */
epena 1:c0429edee15b 1690 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1691 AD77681_REG_DIG_DIAG_ENABLE,
epena 1:c0429edee15b 1692 AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK,
epena 1:c0429edee15b 1693 AD77681_DIG_DIAG_ERR_FUSE_CRC(ENABLE));
epena 1:c0429edee15b 1694 /* Enable MCLK Counter */
epena 1:c0429edee15b 1695 ret |= ad77681_spi_write_mask(dev,
epena 1:c0429edee15b 1696 AD77681_REG_DIG_DIAG_ENABLE,
epena 1:c0429edee15b 1697 AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK,
epena 1:c0429edee15b 1698 AD77681_DIG_DIAG_FREQ_COUNT_EN(ENABLE));
epena 1:c0429edee15b 1699
epena 1:c0429edee15b 1700 return ret;
epena 1:c0429edee15b 1701 }
epena 1:c0429edee15b 1702
epena 1:c0429edee15b 1703 /**
epena 1:c0429edee15b 1704 * Read from all ADC status registers
epena 1:c0429edee15b 1705 * @param dev - The device structure.
epena 1:c0429edee15b 1706 * @param status - Structure with all satuts bits
epena 1:c0429edee15b 1707 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1708 */
epena 1:c0429edee15b 1709 int32_t ad77681_status(struct ad77681_dev *dev,
epena 1:c0429edee15b 1710 struct ad77681_status_registers *status)
epena 1:c0429edee15b 1711 {
epena 1:c0429edee15b 1712 int32_t ret;
epena 1:c0429edee15b 1713 uint8_t buf[3];
epena 1:c0429edee15b 1714
epena 1:c0429edee15b 1715 /* Master status register */
epena 1:c0429edee15b 1716 ret = ad77681_spi_reg_read(dev, AD77681_REG_MASTER_STATUS,buf);
epena 1:c0429edee15b 1717 status->master_error = buf[1] & AD77681_MASTER_ERROR_MSK;
epena 1:c0429edee15b 1718 status->adc_error = buf[1] & AD77681_MASTER_ADC_ERROR_MSK;
epena 1:c0429edee15b 1719 status->dig_error = buf[1] & AD77681_MASTER_DIG_ERROR_MSK;
epena 1:c0429edee15b 1720 status->adc_err_ext_clk_qual = buf[1] & AD77681_MASTER_DIG_ERR_EXT_CLK_MSK;
epena 1:c0429edee15b 1721 status->adc_filt_saturated = buf[1] & AD77681_MASTER_FILT_SAT_MSK;
epena 1:c0429edee15b 1722 status->adc_filt_not_settled = buf[1] & AD77681_MASTER_FILT_NOT_SET_MSK;
epena 1:c0429edee15b 1723 status->spi_error = buf[1] & AD77681_MASTER_SPI_ERROR_MSK;
epena 1:c0429edee15b 1724 status->por_flag = buf[1] & AD77681_MASTER_POR_FLAG_MSK;
epena 1:c0429edee15b 1725 /* SPI diag status register */
epena 1:c0429edee15b 1726 ret |= ad77681_spi_reg_read(dev, AD77681_REG_SPI_DIAG_STATUS, buf);
epena 1:c0429edee15b 1727 status->spi_ignore = buf[1] & AD77681_SPI_IGNORE_ERROR_MSK;
epena 1:c0429edee15b 1728 status->spi_clock_count = buf[1] & AD77681_SPI_CLK_CNT_ERROR_MSK;
epena 1:c0429edee15b 1729 status->spi_read_error = buf[1] & AD77681_SPI_READ_ERROR_MSK;
epena 1:c0429edee15b 1730 status->spi_write_error = buf[1] & AD77681_SPI_WRITE_ERROR_MSK;
epena 1:c0429edee15b 1731 status->spi_crc_error = buf[1] & AD77681_SPI_CRC_ERROR_MSK;
epena 1:c0429edee15b 1732 /* ADC diag status register */
epena 1:c0429edee15b 1733 ret |= ad77681_spi_reg_read(dev, AD77681_REG_ADC_DIAG_STATUS,buf);
epena 1:c0429edee15b 1734 status->dldo_psm_error = buf[1] & AD77681_ADC_DLDO_PSM_ERROR_MSK;
epena 1:c0429edee15b 1735 status->aldo_psm_error = buf[1] & AD77681_ADC_ALDO_PSM_ERROR_MSK;
epena 1:c0429edee15b 1736 status->ref_det_error = buf[1] & AD77681_ADC_REF_DET_ERROR_MSK;
epena 1:c0429edee15b 1737 status->filt_sat_error = buf[1] & AD77681_ADC_FILT_SAT_MSK;
epena 1:c0429edee15b 1738 status->filt_not_set_error = buf[1] & AD77681_ADC_FILT_NOT_SET_MSK;
epena 1:c0429edee15b 1739 status->ext_clk_qual_error = buf[1] & AD77681_ADC_DIG_ERR_EXT_CLK_MSK;
epena 1:c0429edee15b 1740 /* DIG diag status register */
epena 1:c0429edee15b 1741 ret |= ad77681_spi_reg_read(dev, AD77681_REG_DIG_DIAG_STATUS,buf);
epena 1:c0429edee15b 1742 status->memoy_map_crc_error = buf[1] & AD77681_DIG_MEMMAP_CRC_ERROR_MSK;
epena 1:c0429edee15b 1743 status->ram_crc_error = buf[1] & AD77681_DIG_RAM_CRC_ERROR_MSK;
epena 1:c0429edee15b 1744 status->fuse_crc_error = buf[1] & AD77681_DIG_FUS_CRC_ERROR_MSK;
epena 1:c0429edee15b 1745
epena 1:c0429edee15b 1746 return ret;
epena 1:c0429edee15b 1747 }
epena 1:c0429edee15b 1748
epena 1:c0429edee15b 1749 /**
epena 1:c0429edee15b 1750 * Initialize the device.
epena 1:c0429edee15b 1751 * @param device - The device structure.
epena 1:c0429edee15b 1752 * @param init_param - The structure that contains the device initial
epena 1:c0429edee15b 1753 * parameters.
epena 1:c0429edee15b 1754 * @param status - The structure that will contains the ADC status
epena 1:c0429edee15b 1755 * @return 0 in case of success, negative error code otherwise.
epena 1:c0429edee15b 1756 */
epena 1:c0429edee15b 1757 int32_t ad77681_setup(struct ad77681_dev **device,
epena 1:c0429edee15b 1758 struct ad77681_init_param init_param,
epena 1:c0429edee15b 1759 struct ad77681_status_registers **status)
epena 1:c0429edee15b 1760 {
epena 1:c0429edee15b 1761 struct ad77681_dev *dev;
epena 1:c0429edee15b 1762 struct ad77681_status_registers *stat;
epena 1:c0429edee15b 1763 int32_t ret;
epena 1:c0429edee15b 1764 uint8_t scratchpad_check = 0xAD;
epena 1:c0429edee15b 1765
epena 1:c0429edee15b 1766 dev = (struct ad77681_dev *)malloc(sizeof(*dev));
epena 1:c0429edee15b 1767 if (!dev) {
epena 1:c0429edee15b 1768 return -1;
epena 1:c0429edee15b 1769 }
epena 1:c0429edee15b 1770
epena 1:c0429edee15b 1771 stat = (struct ad77681_status_registers *)malloc(sizeof(*stat));
epena 1:c0429edee15b 1772 if (!stat) {
epena 1:c0429edee15b 1773 free(dev);
epena 1:c0429edee15b 1774 return -1;
epena 1:c0429edee15b 1775 }
epena 1:c0429edee15b 1776
epena 1:c0429edee15b 1777 dev->power_mode = init_param.power_mode;
epena 1:c0429edee15b 1778 dev->mclk_div = init_param.mclk_div;
epena 1:c0429edee15b 1779 dev->conv_diag_sel = init_param.conv_diag_sel;
epena 1:c0429edee15b 1780 dev->conv_mode = init_param.conv_mode;
epena 1:c0429edee15b 1781 dev->diag_mux_sel = init_param.diag_mux_sel;
epena 1:c0429edee15b 1782 dev->conv_len = init_param.conv_len;
epena 1:c0429edee15b 1783 dev->crc_sel = AD77681_NO_CRC;
epena 1:c0429edee15b 1784 dev->status_bit = init_param.status_bit;
epena 1:c0429edee15b 1785 dev->VCM_out = init_param.VCM_out;
epena 1:c0429edee15b 1786 dev->AINn = init_param.AINn;
epena 1:c0429edee15b 1787 dev->AINp = init_param.AINp;
epena 1:c0429edee15b 1788 dev->REFn = init_param.REFn;
epena 1:c0429edee15b 1789 dev->REFp = init_param.REFp;
epena 1:c0429edee15b 1790 dev->filter = init_param.filter;
epena 1:c0429edee15b 1791 dev->decimate = init_param.decimate;
epena 1:c0429edee15b 1792 dev->sinc3_osr = init_param.sinc3_osr;
epena 1:c0429edee15b 1793 dev->vref = init_param.vref;
epena 1:c0429edee15b 1794 dev->mclk = init_param.mclk;
epena 1:c0429edee15b 1795 dev->sample_rate = init_param.sample_rate;
epena 1:c0429edee15b 1796 dev->data_frame_byte = init_param.data_frame_byte;
epena 1:c0429edee15b 1797
epena 1:c0429edee15b 1798 ret = spi_init(&dev->spi_desc, &init_param.spi_eng_dev_init);
epena 1:c0429edee15b 1799 if (ret < 0) {
epena 1:c0429edee15b 1800 free(dev);
epena 1:c0429edee15b 1801 free(stat);
epena 1:c0429edee15b 1802 return ret;
epena 1:c0429edee15b 1803 }
epena 1:c0429edee15b 1804
epena 1:c0429edee15b 1805 ret |= ad77681_soft_reset(dev);
epena 1:c0429edee15b 1806
epena 1:c0429edee15b 1807 udelay(200);
epena 1:c0429edee15b 1808
epena 1:c0429edee15b 1809 /* Check physical connection using scratchpad*/
epena 1:c0429edee15b 1810 if (ad77681_scratchpad(dev, &scratchpad_check) == FAILURE) {
epena 1:c0429edee15b 1811 scratchpad_check = 0xAD;/* If failure, second try */
epena 1:c0429edee15b 1812 ret |= (ad77681_scratchpad(dev, &scratchpad_check));
epena 1:c0429edee15b 1813 if(ret == FAILURE) {
epena 1:c0429edee15b 1814 free(dev);
epena 1:c0429edee15b 1815 free(stat);
epena 1:c0429edee15b 1816 return ret;
epena 1:c0429edee15b 1817 }
epena 1:c0429edee15b 1818 }
epena 1:c0429edee15b 1819 ret |= ad77681_set_power_mode(dev, dev->power_mode);
epena 1:c0429edee15b 1820 ret |= ad77681_set_mclk_div(dev, dev->mclk_div);
epena 1:c0429edee15b 1821 ret |= ad77681_set_conv_mode(dev,
epena 1:c0429edee15b 1822 dev->conv_mode,
epena 1:c0429edee15b 1823 dev->diag_mux_sel,
epena 1:c0429edee15b 1824 dev->conv_diag_sel);
epena 1:c0429edee15b 1825 ret |= ad77681_set_convlen(dev, dev->conv_len);
epena 1:c0429edee15b 1826 ret |= ad77681_set_status_bit(dev, dev->status_bit);
epena 1:c0429edee15b 1827 ret |= ad77681_set_crc_sel(dev, init_param.crc_sel);
epena 1:c0429edee15b 1828 ret |= ad77681_set_VCM_output(dev, dev->VCM_out);
epena 1:c0429edee15b 1829 ret |= ad77681_set_AINn_buffer(dev, dev->AINn);
epena 1:c0429edee15b 1830 ret |= ad77681_set_AINp_buffer(dev, dev->AINp);
epena 1:c0429edee15b 1831 ret |= ad77681_set_REFn_buffer(dev, dev->REFn);
epena 1:c0429edee15b 1832 ret |= ad77681_set_REFp_buffer(dev, dev->REFp);
epena 1:c0429edee15b 1833 ret |= ad77681_set_filter_type(dev, dev->decimate, dev->filter, dev->sinc3_osr);
epena 1:c0429edee15b 1834 ret |= ad77681_error_flags_enabe(dev);
epena 1:c0429edee15b 1835 ret |= ad77681_clear_error_flags(dev);
epena 1:c0429edee15b 1836 ret |= ad77681_status(dev, stat);
epena 1:c0429edee15b 1837 ad77681_get_frame_byte(dev);
epena 1:c0429edee15b 1838 ad77681_update_sample_rate(dev);
epena 1:c0429edee15b 1839 *status = stat;
epena 1:c0429edee15b 1840 *device = dev;
epena 1:c0429edee15b 1841
epena 1:c0429edee15b 1842 if (!ret)
epena 1:c0429edee15b 1843 printf("ad77681 successfully initialized\n");
epena 1:c0429edee15b 1844
epena 1:c0429edee15b 1845 return ret;
epena 1:c0429edee15b 1846 }
epena 1:c0429edee15b 1847