Habibur Rahman / NRF24L01P

stable library for the Nordic NRF24L01+ radio transciever

nrf24l01p.h@0:795de307e97f, 2016-11-21 (annotated)

Committer:
emoninet2
Date:
Mon Nov 21 19:39:46 2016 +0000
Revision:
0:795de307e97f
ported NRF24L01P library for the mbed after converting to c++ class

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emoninet2 0:795de307e97f 1 /*
emoninet2 0:795de307e97f 2 * nrf24l01p.h
emoninet2 0:795de307e97f 3 *
emoninet2 0:795de307e97f 4 * Created: 29-Mar-16 10:57:14 PM
emoninet2 0:795de307e97f 5 * Author: emon1
emoninet2 0:795de307e97f 6 */
emoninet2 0:795de307e97f 7
emoninet2 0:795de307e97f 8
emoninet2 0:795de307e97f 9 #ifndef __NRF24L01P_H__
emoninet2 0:795de307e97f 10 #define __NRF24L01P_H__
emoninet2 0:795de307e97f 11
emoninet2 0:795de307e97f 12 #include "mbed.h"
emoninet2 0:795de307e97f 13 //#include "nrf24l01p_arch_driver.h"
emoninet2 0:795de307e97f 14
emoninet2 0:795de307e97f 15
emoninet2 0:795de307e97f 16
emoninet2 0:795de307e97f 17 #define _nrf24l01p_delay_us wait_us
emoninet2 0:795de307e97f 18 #define _nrf24l01p_delay_ms wait_ms
emoninet2 0:795de307e97f 19
emoninet2 0:795de307e97f 20
emoninet2 0:795de307e97f 21 #define set_bit(reg,bit) reg|= (1<<bit)
emoninet2 0:795de307e97f 22 #define clr_bit(reg,bit) reg&= ~(1<<bit)
emoninet2 0:795de307e97f 23 #define tgl_bit(reg,bit) reg^= (1<<bit)
emoninet2 0:795de307e97f 24
emoninet2 0:795de307e97f 25
emoninet2 0:795de307e97f 26 #define _NRF24L01P_TX_FIFO_COUNT 3
emoninet2 0:795de307e97f 27 #define _NRF24L01P_RX_FIFO_COUNT 3
emoninet2 0:795de307e97f 28
emoninet2 0:795de307e97f 29 #define _NRF24L01P_TX_FIFO_SIZE 32
emoninet2 0:795de307e97f 30 #define _NRF24L01P_RX_FIFO_SIZE 32
emoninet2 0:795de307e97f 31
emoninet2 0:795de307e97f 32 #define _NRF24L01P_SPI_MAX_DATA_RATE 10000000
emoninet2 0:795de307e97f 33
emoninet2 0:795de307e97f 34
emoninet2 0:795de307e97f 35
emoninet2 0:795de307e97f 36 #define _NRF24L01P_EN_AA_NONE 0
emoninet2 0:795de307e97f 37 #define _NRF24L01P_EN_RXADDR_NONE 0
emoninet2 0:795de307e97f 38 #define _NRF24L01P_SETUP_AW_AW_MASK (0x3<<0)
emoninet2 0:795de307e97f 39
emoninet2 0:795de307e97f 40 #define _NRF24L01P_MIN_RF_FREQUENCY 2400
emoninet2 0:795de307e97f 41 #define _NRF24L01P_MAX_RF_FREQUENCY 2525
emoninet2 0:795de307e97f 42 #define _NRF24L01P_DUMMYBYTE 0x65
emoninet2 0:795de307e97f 43
emoninet2 0:795de307e97f 44
emoninet2 0:795de307e97f 45 /** @name NRF24L01+ commands
emoninet2 0:795de307e97f 46 * These are the commands
emoninet2 0:795de307e97f 47 */
emoninet2 0:795de307e97f 48 /**@{*/
emoninet2 0:795de307e97f 49 #define _NRF24L01P_SPI_CMD_RD_REG 0x00
emoninet2 0:795de307e97f 50 #define _NRF24L01P_SPI_CMD_WR_REG 0x20
emoninet2 0:795de307e97f 51 #define _NRF24L01P_SPI_CMD_RD_RX_PAYLOAD 0x61
emoninet2 0:795de307e97f 52 #define _NRF24L01P_SPI_CMD_WR_TX_PAYLOAD 0xa0
emoninet2 0:795de307e97f 53 #define _NRF24L01P_SPI_CMD_FLUSH_TX 0xe1
emoninet2 0:795de307e97f 54 #define _NRF24L01P_SPI_CMD_FLUSH_RX 0xe2
emoninet2 0:795de307e97f 55 #define _NRF24L01P_SPI_CMD_REUSE_TX_PL 0xe3
emoninet2 0:795de307e97f 56 #define _NRF24L01P_SPI_CMD_R_RX_PL_WID 0x60
emoninet2 0:795de307e97f 57 #define _NRF24L01P_SPI_CMD_W_ACK_PAYLOAD 0xa8
emoninet2 0:795de307e97f 58 #define _NRF24L01P_SPI_CMD_W_TX_PYLD_NO_ACK 0xb0
emoninet2 0:795de307e97f 59 #define _NRF24L01P_SPI_CMD_NOP 0xff
emoninet2 0:795de307e97f 60 /**@}*/
emoninet2 0:795de307e97f 61
emoninet2 0:795de307e97f 62 /** @name NRF24L01+ register address
emoninet2 0:795de307e97f 63 * These are the registers
emoninet2 0:795de307e97f 64 */
emoninet2 0:795de307e97f 65 /**@{*/
emoninet2 0:795de307e97f 66 #define _NRF24L01P_REG_CONFIG 0x00
emoninet2 0:795de307e97f 67 #define _NRF24L01P_REG_EN_AA 0x01
emoninet2 0:795de307e97f 68 #define _NRF24L01P_REG_EN_RXADDR 0x02
emoninet2 0:795de307e97f 69 #define _NRF24L01P_REG_SETUP_AW 0x03
emoninet2 0:795de307e97f 70 #define _NRF24L01P_REG_SETUP_RETR 0x04
emoninet2 0:795de307e97f 71 #define _NRF24L01P_REG_RF_CH 0x05
emoninet2 0:795de307e97f 72 #define _NRF24L01P_REG_RF_SETUP 0x06
emoninet2 0:795de307e97f 73 #define _NRF24L01P_REG_STATUS 0x07
emoninet2 0:795de307e97f 74 #define _NRF24L01P_REG_OBSERVE_TX 0x08
emoninet2 0:795de307e97f 75 #define _NRF24L01P_REG_RPD 0x09
emoninet2 0:795de307e97f 76 #define _NRF24L01P_REG_RX_ADDR_P0 0x0a
emoninet2 0:795de307e97f 77 #define _NRF24L01P_REG_RX_ADDR_P1 0x0b
emoninet2 0:795de307e97f 78 #define _NRF24L01P_REG_RX_ADDR_P2 0x0c
emoninet2 0:795de307e97f 79 #define _NRF24L01P_REG_RX_ADDR_P3 0x0d
emoninet2 0:795de307e97f 80 #define _NRF24L01P_REG_RX_ADDR_P4 0x0e
emoninet2 0:795de307e97f 81 #define _NRF24L01P_REG_RX_ADDR_P5 0x0f
emoninet2 0:795de307e97f 82 #define _NRF24L01P_REG_TX_ADDR 0x10
emoninet2 0:795de307e97f 83 #define _NRF24L01P_REG_RX_PW_P0 0x11
emoninet2 0:795de307e97f 84 #define _NRF24L01P_REG_RX_PW_P1 0x12
emoninet2 0:795de307e97f 85 #define _NRF24L01P_REG_RX_PW_P2 0x13
emoninet2 0:795de307e97f 86 #define _NRF24L01P_REG_RX_PW_P3 0x14
emoninet2 0:795de307e97f 87 #define _NRF24L01P_REG_RX_PW_P4 0x15
emoninet2 0:795de307e97f 88 #define _NRF24L01P_REG_RX_PW_P5 0x16
emoninet2 0:795de307e97f 89 #define _NRF24L01P_REG_FIFO_STATUS 0x17
emoninet2 0:795de307e97f 90 #define _NRF24L01P_REG_DYNPD 0x1c
emoninet2 0:795de307e97f 91 #define _NRF24L01P_REG_FEATURE 0x1d
emoninet2 0:795de307e97f 92 #define _NRF24L01P_REG_ADDRESS_MASK 0x1f
emoninet2 0:795de307e97f 93 /**@}*/
emoninet2 0:795de307e97f 94
emoninet2 0:795de307e97f 95
emoninet2 0:795de307e97f 96
emoninet2 0:795de307e97f 97 /** @name NRF24L01+ config address
emoninet2 0:795de307e97f 98 * These are the congig registers
emoninet2 0:795de307e97f 99 */
emoninet2 0:795de307e97f 100 /**@{*/
emoninet2 0:795de307e97f 101 #define _NRF24L01P_CONFIG_PRIM_RX (1<<0)
emoninet2 0:795de307e97f 102 #define _NRF24L01P_CONFIG_PWR_UP (1<<1)
emoninet2 0:795de307e97f 103 #define _NRF24L01P_CONFIG_CRC0 (1<<2)
emoninet2 0:795de307e97f 104 #define _NRF24L01P_CONFIG_EN_CRC (1<<3)
emoninet2 0:795de307e97f 105 #define _NRF24L01P_CONFIG_MASK_MAX_RT (1<<4)
emoninet2 0:795de307e97f 106 #define _NRF24L01P_CONFIG_MASK_TX_DS (1<<5)
emoninet2 0:795de307e97f 107 #define _NRF24L01P_CONFIG_MASK_RX_DR (1<<6)
emoninet2 0:795de307e97f 108 #define _NRF24L01P_CONFIG_CRC_MASK (_NRF24L01P_CONFIG_EN_CRC|_NRF24L01P_CONFIG_CRC0)
emoninet2 0:795de307e97f 109 /**@}*/
emoninet2 0:795de307e97f 110
emoninet2 0:795de307e97f 111
emoninet2 0:795de307e97f 112 /** @name NRF24L01+ setup register
emoninet2 0:795de307e97f 113 * These are bits of the setup register
emoninet2 0:795de307e97f 114 */
emoninet2 0:795de307e97f 115 /**@{*/
emoninet2 0:795de307e97f 116 #define _NRF24L01P_RF_SETUP_RF_PWR_MASK (0x3<<1)
emoninet2 0:795de307e97f 117 #define _NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT (1 << 3)
emoninet2 0:795de307e97f 118 #define _NRF24L01P_RF_SETUP_RF_DR_LOW_BIT (1 << 5)
emoninet2 0:795de307e97f 119 #define _NRF24L01P_RF_SETUP_RF_DR_MASK (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT|_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT)
emoninet2 0:795de307e97f 120 /**@}*/
emoninet2 0:795de307e97f 121
emoninet2 0:795de307e97f 122
emoninet2 0:795de307e97f 123
emoninet2 0:795de307e97f 124
emoninet2 0:795de307e97f 125 /** @name NRF24L01+ status register
emoninet2 0:795de307e97f 126 * These are bits of the status register
emoninet2 0:795de307e97f 127 */
emoninet2 0:795de307e97f 128 /**@{*/
emoninet2 0:795de307e97f 129 #define _NRF24L01P_STATUS_TX_FULL (1<<0)
emoninet2 0:795de307e97f 130 #define _NRF24L01P_STATUS_RX_P_NO (0x7<<1)
emoninet2 0:795de307e97f 131 #define _NRF24L01P_STATUS_MAX_RT (1<<4)
emoninet2 0:795de307e97f 132 #define _NRF24L01P_STATUS_TX_DS (1<<5)
emoninet2 0:795de307e97f 133 #define _NRF24L01P_STATUS_RX_DR (1<<6)
emoninet2 0:795de307e97f 134 /**@}*/
emoninet2 0:795de307e97f 135
emoninet2 0:795de307e97f 136 /** @name NRF24L01+ observe register
emoninet2 0:795de307e97f 137 * These are bits of the observe register
emoninet2 0:795de307e97f 138 */
emoninet2 0:795de307e97f 139 /**@{*/
emoninet2 0:795de307e97f 140 #define _NRF24L01P_OBSERVE_TX_ARC_CNT_BP 0
emoninet2 0:795de307e97f 141 #define _NRF24L01P_OBSERVE_TX_ARC_CNT_MASK 0x0F
emoninet2 0:795de307e97f 142 #define _NRF24L01P_OBSERVE_TX_PLOS_CNT_BP 4
emoninet2 0:795de307e97f 143 #define _NRF24L01P_OBSERVE_TX_PLOS_CNT_MASK 0xF0
emoninet2 0:795de307e97f 144 /**@}*/
emoninet2 0:795de307e97f 145
emoninet2 0:795de307e97f 146
emoninet2 0:795de307e97f 147 /** @name NRF24L01+ fifo status register
emoninet2 0:795de307e97f 148 * These are bits of the fifo status register
emoninet2 0:795de307e97f 149 */
emoninet2 0:795de307e97f 150 /**@{*/
emoninet2 0:795de307e97f 151 #define _NRF24L01P_FIFO_STATUS_RX_EMPTY (1<<0)
emoninet2 0:795de307e97f 152 #define _NRF24L01P_FIFO_STATUS_RX_FULL (1<<1)
emoninet2 0:795de307e97f 153 #define _NRF24L01P_FIFO_STATUS_TX_EMPTY (1<<4)
emoninet2 0:795de307e97f 154 #define _NRF24L01P_FIFO_STATUS_TX_FULL (1<<5)
emoninet2 0:795de307e97f 155 #define _NRF24L01P_FIFO_STATUS_RX_REUSE (1<<6)
emoninet2 0:795de307e97f 156 /**@}*/
emoninet2 0:795de307e97f 157
emoninet2 0:795de307e97f 158
emoninet2 0:795de307e97f 159 /** @name NRF24L01+ feature register
emoninet2 0:795de307e97f 160 * These are bits of the feature register
emoninet2 0:795de307e97f 161 */
emoninet2 0:795de307e97f 162 /**@{*/
emoninet2 0:795de307e97f 163 #define _NRF24L01_FEATURE_EN_DPL (1<<2)
emoninet2 0:795de307e97f 164 #define _NRF24L01_FEATURE_EN_ACK_PAY (1<<1)
emoninet2 0:795de307e97f 165 #define _NRF24L01_FEATURE_EN_DYN_ACK (1<<0)
emoninet2 0:795de307e97f 166 /**@}*/
emoninet2 0:795de307e97f 167
emoninet2 0:795de307e97f 168
emoninet2 0:795de307e97f 169
emoninet2 0:795de307e97f 170 #define _NRF24L01P_RX_PW_Px_MASK 0x3F
emoninet2 0:795de307e97f 171
emoninet2 0:795de307e97f 172
emoninet2 0:795de307e97f 173 /** @name NRF24L01+ config register
emoninet2 0:795de307e97f 174 * These are bits of the config register
emoninet2 0:795de307e97f 175 */
emoninet2 0:795de307e97f 176 /**@{*/
emoninet2 0:795de307e97f 177 #define _NRF24L01P_TIMING_PowerOnReset_ms 100 // 100mS
emoninet2 0:795de307e97f 178 #define _NRF24L01P_TIMING_Tundef2pd_us 100000 // 100mS
emoninet2 0:795de307e97f 179 #define _NRF24L01P_TIMING_Tstby2a_us 130 // 130uS
emoninet2 0:795de307e97f 180 #define _NRF24L01P_TIMING_Thce_us 10 // 10uS
emoninet2 0:795de307e97f 181 #define _NRF24L01P_TIMING_Tpd2stby_us 4500 // 4.5mS worst case
emoninet2 0:795de307e97f 182 #define _NRF24L01P_TIMING_Tpece2csn_us 4 // 4uS
emoninet2 0:795de307e97f 183 /**@}*/
emoninet2 0:795de307e97f 184
emoninet2 0:795de307e97f 185
emoninet2 0:795de307e97f 186 /** @name NRF24L01+ default values
emoninet2 0:795de307e97f 187 * These are bits of the default values
emoninet2 0:795de307e97f 188 */
emoninet2 0:795de307e97f 189 /**@{*/
emoninet2 0:795de307e97f 190 #define DEFAULT_NRF24L01P_ADDRESS ((unsigned long long) 0xE7E7E7E7E7 )
emoninet2 0:795de307e97f 191 #define DEFAULT_NRF24L01P_ADDRESS_WIDTH 5
emoninet2 0:795de307e97f 192 #define DEFAULT_NRF24L01P_CRC NRF24L01P_CRC_8_BIT
emoninet2 0:795de307e97f 193 #define DEFAULT_NRF24L01P_RF_FREQUENCY (NRF24L01P_MIN_RF_FREQUENCY + 2)
emoninet2 0:795de307e97f 194 #define DEFAULT_NRF24L01P_DATARATE NRF24L01P_DATARATE_1_MBPS
emoninet2 0:795de307e97f 195 #define DEFAULT_NRF24L01P_TX_PWR NRF24L01P_TX_PWR_ZERO_DB
emoninet2 0:795de307e97f 196 #define DEFAULT_NRF24L01P_TRANSFER_SIZE 4
emoninet2 0:795de307e97f 197 /**@}*/
emoninet2 0:795de307e97f 198
emoninet2 0:795de307e97f 199
emoninet2 0:795de307e97f 200 /**
emoninet2 0:795de307e97f 201 * @brief pipe address datatype
emoninet2 0:795de307e97f 202 * data type for the pipe address
emoninet2 0:795de307e97f 203 */
emoninet2 0:795de307e97f 204 #define pipeAddrType_t uint64_t
emoninet2 0:795de307e97f 205
emoninet2 0:795de307e97f 206 /**
emoninet2 0:795de307e97f 207 * @brief CRC options
emoninet2 0:795de307e97f 208 * camn be 8 bit or 16 bit CRC
emoninet2 0:795de307e97f 209 */
emoninet2 0:795de307e97f 210 typedef enum _nrf24l01p_crc_enum{
emoninet2 0:795de307e97f 211 _NRF24L01P_CONFIG_CRC_NONE = (0),
emoninet2 0:795de307e97f 212 _NRF24L01P_CONFIG_CRC_8BIT = (_NRF24L01P_CONFIG_EN_CRC),
emoninet2 0:795de307e97f 213 _NRF24L01P_CONFIG_CRC_16BIT = (_NRF24L01P_CONFIG_EN_CRC|_NRF24L01P_CONFIG_CRC0),
emoninet2 0:795de307e97f 214 }_nrf24l01p_crc_t;
emoninet2 0:795de307e97f 215
emoninet2 0:795de307e97f 216 /**
emoninet2 0:795de307e97f 217 * @brief address width options
emoninet2 0:795de307e97f 218 * address width can be 3 , 4 or 5 bytes
emoninet2 0:795de307e97f 219 */
emoninet2 0:795de307e97f 220 typedef enum _nrf24l01p_aw_enum{
emoninet2 0:795de307e97f 221 _NRF24L01P_SETUP_AW_AW_3BYTE = (0x1<<0),/**< 3 bytes address width */
emoninet2 0:795de307e97f 222 _NRF24L01P_SETUP_AW_AW_4BYTE = (0x2<<0),/**< 4 bytes address width */
emoninet2 0:795de307e97f 223 _NRF24L01P_SETUP_AW_AW_5BYTE = (0x3<<0),/**< 5 bytes address width */
emoninet2 0:795de307e97f 224 }_nrf24l01p_aw_t;
emoninet2 0:795de307e97f 225
emoninet2 0:795de307e97f 226 /**
emoninet2 0:795de307e97f 227 * @brief rf power enumeration
emoninet2 0:795de307e97f 228 * antenna power options
emoninet2 0:795de307e97f 229 */
emoninet2 0:795de307e97f 230 typedef enum _nrf24l01p_RF_power_enum{
emoninet2 0:795de307e97f 231 _NRF24L01P_RF_SETUP_RF_PWR_0DBM = (0x3<<1),
emoninet2 0:795de307e97f 232 _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM = (0x2<<1),
emoninet2 0:795de307e97f 233 _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM = (0x1<<1),
emoninet2 0:795de307e97f 234 _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM = (0x0<<1),
emoninet2 0:795de307e97f 235 }_nrf24l01p_RFpower_t;
emoninet2 0:795de307e97f 236
emoninet2 0:795de307e97f 237 /**
emoninet2 0:795de307e97f 238 * @brief data rate enumeration
emoninet2 0:795de307e97f 239 * choose data rate between 250kbps, 1mbps or 2mbps
emoninet2 0:795de307e97f 240 */
emoninet2 0:795de307e97f 241 typedef enum _nrf24l01p_datarate_enum{
emoninet2 0:795de307e97f 242 _NRF24L01P_RF_SETUP_RF_DR_250KBPS = (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT),
emoninet2 0:795de307e97f 243 _NRF24L01P_RF_SETUP_RF_DR_1MBPS = (0),
emoninet2 0:795de307e97f 244 _NRF24L01P_RF_SETUP_RF_DR_2MBPS = (_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT),
emoninet2 0:795de307e97f 245 }_nrf24l01p_datarate_t;
emoninet2 0:795de307e97f 246
emoninet2 0:795de307e97f 247 /**
emoninet2 0:795de307e97f 248 * @brief pipe numbers enumeration
emoninet2 0:795de307e97f 249 * these are the available pipe numbers
emoninet2 0:795de307e97f 250 */
emoninet2 0:795de307e97f 251 typedef enum _nrf24l01p_pipe_enum{
emoninet2 0:795de307e97f 252 _NRF24L01P_PIPE_P0 = 0,/**< Pipe 0 */
emoninet2 0:795de307e97f 253 _NRF24L01P_PIPE_P1 = 1,/**< Pipe 1 */
emoninet2 0:795de307e97f 254 _NRF24L01P_PIPE_P2 = 2,/**< Pipe 2 */
emoninet2 0:795de307e97f 255 _NRF24L01P_PIPE_P3 = 3,/**< Pipe 3 */
emoninet2 0:795de307e97f 256 _NRF24L01P_PIPE_P4 = 4,/**< Pipe 4 */
emoninet2 0:795de307e97f 257 _NRF24L01P_PIPE_P5 = 5,/**< Pipe 5 */
emoninet2 0:795de307e97f 258 }_nrf24l01p_pipe_t;
emoninet2 0:795de307e97f 259
emoninet2 0:795de307e97f 260
emoninet2 0:795de307e97f 261 /**
emoninet2 0:795de307e97f 262 * @brief this is brief enum.
emoninet2 0:795de307e97f 263 * brief enum continued.
emoninet2 0:795de307e97f 264 *
emoninet2 0:795de307e97f 265 * expect detailed enum here.
emoninet2 0:795de307e97f 266 * @note can also have note.wow
emoninet2 0:795de307e97f 267 */
emoninet2 0:795de307e97f 268 typedef enum {
emoninet2 0:795de307e97f 269 _NRF24L01P_MODE_UNKNOWN,/**< NRF24L01+ unknown mode */
emoninet2 0:795de307e97f 270 _NRF24L01P_MODE_POWER_DOWN,/**< NRF24L01+ Power Down mode */
emoninet2 0:795de307e97f 271 _NRF24L01P_MODE_STANDBY,/**< NRF24L01+ Standby mode */
emoninet2 0:795de307e97f 272 _NRF24L01P_MODE_RX,/**< NRF24L01+ RX mode */
emoninet2 0:795de307e97f 273 _NRF24L01P_MODE_TX,/**< NRF24L01+ TX mode */
emoninet2 0:795de307e97f 274 } nRF24L01P_Mode_Type;
emoninet2 0:795de307e97f 275
emoninet2 0:795de307e97f 276
emoninet2 0:795de307e97f 277 class nrf24l01p
emoninet2 0:795de307e97f 278 {
emoninet2 0:795de307e97f 279 //variables
emoninet2 0:795de307e97f 280 public:
emoninet2 0:795de307e97f 281 protected:
emoninet2 0:795de307e97f 282 private:
emoninet2 0:795de307e97f 283 SPI spi_;
emoninet2 0:795de307e97f 284 DigitalOut nCS_;
emoninet2 0:795de307e97f 285 DigitalOut ce_;
emoninet2 0:795de307e97f 286 InterruptIn nIRQ_;
emoninet2 0:795de307e97f 287
emoninet2 0:795de307e97f 288 nRF24L01P_Mode_Type _nrf24l01p_mode;/**< state of the radio */
emoninet2 0:795de307e97f 289 //functions
emoninet2 0:795de307e97f 290 public:
emoninet2 0:795de307e97f 291 nrf24l01p();
emoninet2 0:795de307e97f 292
emoninet2 0:795de307e97f 293 nrf24l01p(PinName mosi, PinName miso, PinName sck, PinName csn, PinName ce, PinName irq = NC);
emoninet2 0:795de307e97f 294 void arch_nrf24l01p_ce_pin(bool state);
emoninet2 0:795de307e97f 295 void arch_nrf24l01p_csn_pin(bool state);
emoninet2 0:795de307e97f 296 void arch_nrf24l01p_initialize();
emoninet2 0:795de307e97f 297 void arch_spi_master_transcieve(uint8_t *data, int len);
emoninet2 0:795de307e97f 298
emoninet2 0:795de307e97f 299
emoninet2 0:795de307e97f 300 /**
emoninet2 0:795de307e97f 301 * @brief CE Pin
emoninet2 0:795de307e97f 302 * this function handles the CE pin value_com
emoninet2 0:795de307e97f 303 * @param state logic high or low
emoninet2 0:795de307e97f 304 */
emoninet2 0:795de307e97f 305 void ce_pin(bool state);
emoninet2 0:795de307e97f 306 /**
emoninet2 0:795de307e97f 307 * @brief CSN Pin
emoninet2 0:795de307e97f 308 * this function handles the CE pin value_com
emoninet2 0:795de307e97f 309 * @param state logic high or low
emoninet2 0:795de307e97f 310 */
emoninet2 0:795de307e97f 311 void csn_pin(bool state);
emoninet2 0:795de307e97f 312 /**
emoninet2 0:795de307e97f 313 * @brief Read Registers
emoninet2 0:795de307e97f 314 * this function reads the registers
emoninet2 0:795de307e97f 315 * @param address address of the register to read
emoninet2 0:795de307e97f 316 * @param dataout address of array to read into
emoninet2 0:795de307e97f 317 * @param len number of bytes to read
emoninet2 0:795de307e97f 318 * @return none.
emoninet2 0:795de307e97f 319 */
emoninet2 0:795de307e97f 320 void read_register(uint8_t address, uint8_t *dataout, int len);
emoninet2 0:795de307e97f 321 /**
emoninet2 0:795de307e97f 322 * @brief Write Registers
emoninet2 0:795de307e97f 323 * this function writes into the registers
emoninet2 0:795de307e97f 324 * @param address address of the register to write into
emoninet2 0:795de307e97f 325 * @param dataout address of array which holds data to write
emoninet2 0:795de307e97f 326 * @param len number of bytes to write
emoninet2 0:795de307e97f 327 * @return none.
emoninet2 0:795de307e97f 328 */
emoninet2 0:795de307e97f 329 void write_register(uint8_t address, uint8_t *datain, int len);
emoninet2 0:795de307e97f 330 /**
emoninet2 0:795de307e97f 331 * @brief Read RX payload
emoninet2 0:795de307e97f 332 * this function reads the payload from the RX FIFO
emoninet2 0:795de307e97f 333 * @param dataout address of array to read payload data into
emoninet2 0:795de307e97f 334 * @param paylen number of bytes to read from the payload
emoninet2 0:795de307e97f 335 * @return none.
emoninet2 0:795de307e97f 336 */
emoninet2 0:795de307e97f 337 void read_rx_payload(uint8_t *dataout, int pay_len);
emoninet2 0:795de307e97f 338 /**
emoninet2 0:795de307e97f 339 * @brief Write RX payload
emoninet2 0:795de307e97f 340 * this function writes the payload into TX FIFO
emoninet2 0:795de307e97f 341 * @param datain address of array containing the data to write
emoninet2 0:795de307e97f 342 * @param paylen number of bytes to write into the payload
emoninet2 0:795de307e97f 343 * @return none.
emoninet2 0:795de307e97f 344 */
emoninet2 0:795de307e97f 345 void write_tx_payload(uint8_t *datain, int pay_len);
emoninet2 0:795de307e97f 346 /**
emoninet2 0:795de307e97f 347 * @brief Flush TX
emoninet2 0:795de307e97f 348 * this function flushes the TX FIFO buffer
emoninet2 0:795de307e97f 349 */
emoninet2 0:795de307e97f 350 void flush_tx();
emoninet2 0:795de307e97f 351 /**
emoninet2 0:795de307e97f 352 * @brief Flush RX
emoninet2 0:795de307e97f 353 * this function flushes the TX FIFO buffer
emoninet2 0:795de307e97f 354 */
emoninet2 0:795de307e97f 355 void flush_rx();
emoninet2 0:795de307e97f 356 /**
emoninet2 0:795de307e97f 357 * @brief Reuse TX
emoninet2 0:795de307e97f 358 * this function reuses the last data in the TX FIFO
emoninet2 0:795de307e97f 359 *
emoninet2 0:795de307e97f 360 * if the FIFO buffer is not flushed, this command resends the payload
emoninet2 0:795de307e97f 361 * can be used by software when failed to recieve ACK from receiver
emoninet2 0:795de307e97f 362 * saves CPU time since the payload need not be written all over again
emoninet2 0:795de307e97f 363 */
emoninet2 0:795de307e97f 364 void reuse_tx_payload();
emoninet2 0:795de307e97f 365 /**
emoninet2 0:795de307e97f 366 * @brief Read payload width
emoninet2 0:795de307e97f 367 * reads the number of byte in the last FIFO payload
emoninet2 0:795de307e97f 368 *
emoninet2 0:795de307e97f 369 * can only be used if dynamic payload is enabled in FEATURE register
emoninet2 0:795de307e97f 370 * @see _nrf24l01p_enable_dynamic_payload()
emoninet2 0:795de307e97f 371 */
emoninet2 0:795de307e97f 372 int read_rx_payload_width();
emoninet2 0:795de307e97f 373 /**
emoninet2 0:795de307e97f 374 * @brief write ACK payload
emoninet2 0:795de307e97f 375 * payload data to send along with ack
emoninet2 0:795de307e97f 376 *
emoninet2 0:795de307e97f 377 * this is done prior to recieving data on a pipe.
emoninet2 0:795de307e97f 378 * when an ack payload is written for a specific pipe
emoninet2 0:795de307e97f 379 * and that pipe is enabled and auto ack is enableds as well
emoninet2 0:795de307e97f 380 * on receiving a data on that pipe, it will send this data
emoninet2 0:795de307e97f 381 * on the payload along with an ack. If nothing is written on
emoninet2 0:795de307e97f 382 * this payload, then it will send 0 bytes along with the ack
emoninet2 0:795de307e97f 383 * @param pipe pipe number agains which the ack payload is written
emoninet2 0:795de307e97f 384 * @param datain address of array containing the data to write
emoninet2 0:795de307e97f 385 * @param paylen number of bytes to write into the payload
emoninet2 0:795de307e97f 386 */
emoninet2 0:795de307e97f 387 void write_ack_payload(_nrf24l01p_pipe_t pipe, uint8_t *datain, int pay_len);
emoninet2 0:795de307e97f 388 /**
emoninet2 0:795de307e97f 389 * @brief write ACK no payload
emoninet2 0:795de307e97f 390 * payload data to send without an ACK
emoninet2 0:795de307e97f 391 *
emoninet2 0:795de307e97f 392 * @param datain address of array containing the data to write
emoninet2 0:795de307e97f 393 * @param paylen number of bytes to write into the payload
emoninet2 0:795de307e97f 394 */
emoninet2 0:795de307e97f 395 void write_tx_payload_noack(uint8_t *datain, int pay_len);
emoninet2 0:795de307e97f 396 /**
emoninet2 0:795de307e97f 397 * @brief Get Status
emoninet2 0:795de307e97f 398 * reads the status of the NRF24L01+
emoninet2 0:795de307e97f 399 * @return status of the NRF24L01+
emoninet2 0:795de307e97f 400 */
emoninet2 0:795de307e97f 401 int get_status();
emoninet2 0:795de307e97f 402
emoninet2 0:795de307e97f 403
emoninet2 0:795de307e97f 404
emoninet2 0:795de307e97f 405 /**@}*/
emoninet2 0:795de307e97f 406
emoninet2 0:795de307e97f 407
emoninet2 0:795de307e97f 408
emoninet2 0:795de307e97f 409
emoninet2 0:795de307e97f 410
emoninet2 0:795de307e97f 411
emoninet2 0:795de307e97f 412
emoninet2 0:795de307e97f 413
emoninet2 0:795de307e97f 414
emoninet2 0:795de307e97f 415
emoninet2 0:795de307e97f 416 /**
emoninet2 0:795de307e97f 417 * @name NRF24L01+ register control functions
emoninet2 0:795de307e97f 418 */
emoninet2 0:795de307e97f 419 /**@{*/
emoninet2 0:795de307e97f 420 void power_up();
emoninet2 0:795de307e97f 421 void power_down();
emoninet2 0:795de307e97f 422 void rx_mode();
emoninet2 0:795de307e97f 423 void tx_mode();
emoninet2 0:795de307e97f 424 void set_CRC(_nrf24l01p_crc_t opt);
emoninet2 0:795de307e97f 425
emoninet2 0:795de307e97f 426 void enable_auto_ack(_nrf24l01p_pipe_t pipe);
emoninet2 0:795de307e97f 427 void disable_auto_ack(_nrf24l01p_pipe_t pipe);
emoninet2 0:795de307e97f 428 void disable_auto_ack_all_pipes();
emoninet2 0:795de307e97f 429
emoninet2 0:795de307e97f 430 void enable_rx_on_pipe(_nrf24l01p_pipe_t pipe);
emoninet2 0:795de307e97f 431 void disable_rx_on_pipe(_nrf24l01p_pipe_t pipe);
emoninet2 0:795de307e97f 432
emoninet2 0:795de307e97f 433 void set_address_width(_nrf24l01p_aw_t width);
emoninet2 0:795de307e97f 434 _nrf24l01p_aw_t get_address_width();
emoninet2 0:795de307e97f 435
emoninet2 0:795de307e97f 436 void set_auto_retransmission_count(uint8_t count);
emoninet2 0:795de307e97f 437 uint8_t read_auto_retransmission_count();
emoninet2 0:795de307e97f 438 void set_auto_retransmission_delay(uint8_t times250us);
emoninet2 0:795de307e97f 439 uint8_t read_auto_retransmission_delay();
emoninet2 0:795de307e97f 440
emoninet2 0:795de307e97f 441 void set_frequency_offset(uint8_t offset);
emoninet2 0:795de307e97f 442 uint8_t get_frequency_offset();
emoninet2 0:795de307e97f 443
emoninet2 0:795de307e97f 444 void set_DataRate(_nrf24l01p_datarate_t DataRate);
emoninet2 0:795de307e97f 445 _nrf24l01p_datarate_t get_DataRate();
emoninet2 0:795de307e97f 446 void set_RF_Power(_nrf24l01p_RFpower_t RFpower);
emoninet2 0:795de307e97f 447 _nrf24l01p_RFpower_t get_RF_Power();
emoninet2 0:795de307e97f 448
emoninet2 0:795de307e97f 449 bool get_tx_fifo_full_flag();
emoninet2 0:795de307e97f 450 bool get_max_retry_flag();
emoninet2 0:795de307e97f 451 void clear_max_retry_flag();
emoninet2 0:795de307e97f 452 bool get_data_sent_flag();
emoninet2 0:795de307e97f 453 void clear_data_sent_flag();
emoninet2 0:795de307e97f 454 bool get_data_ready_flag();
emoninet2 0:795de307e97f 455 void clear_data_ready_flag();
emoninet2 0:795de307e97f 456 _nrf24l01p_pipe_t get_rx_payload_pipe();
emoninet2 0:795de307e97f 457
emoninet2 0:795de307e97f 458 uint8_t get_arc_count();
emoninet2 0:795de307e97f 459 uint8_t get_plos_count();
emoninet2 0:795de307e97f 460 void clear_plos_count();
emoninet2 0:795de307e97f 461 bool get_rpd();
emoninet2 0:795de307e97f 462
emoninet2 0:795de307e97f 463 void set_RX_pipe_address(_nrf24l01p_pipe_t pipe,pipeAddrType_t address);
emoninet2 0:795de307e97f 464 pipeAddrType_t get_RX_pipe_address(_nrf24l01p_pipe_t pipe);
emoninet2 0:795de307e97f 465 void set_TX_pipe_address(pipeAddrType_t address);
emoninet2 0:795de307e97f 466 pipeAddrType_t get_TX_pipe_address();
emoninet2 0:795de307e97f 467
emoninet2 0:795de307e97f 468 uint8_t get_RX_pipe_width(_nrf24l01p_pipe_t pipe);
emoninet2 0:795de307e97f 469
emoninet2 0:795de307e97f 470
emoninet2 0:795de307e97f 471 bool get_fifo_flag_rx_empty();
emoninet2 0:795de307e97f 472 bool get_fifo_flag_rx_full();
emoninet2 0:795de307e97f 473 bool get_fifo_flag_tx_empty();
emoninet2 0:795de307e97f 474 bool get_fifo_flag_tx_full();
emoninet2 0:795de307e97f 475 bool get_fifo_flag_tx_reuse();
emoninet2 0:795de307e97f 476
emoninet2 0:795de307e97f 477 void enable_dynamic_payload_pipe(_nrf24l01p_pipe_t pipe);
emoninet2 0:795de307e97f 478 void disable_dynamic_payload_pipe(_nrf24l01p_pipe_t pipe);
emoninet2 0:795de307e97f 479 void disable_dynamic_payload_all_pipe();
emoninet2 0:795de307e97f 480 void enable_dynamic_payload();
emoninet2 0:795de307e97f 481 void disable_dynamic_payload();
emoninet2 0:795de307e97f 482 void enable_payload_with_ack();
emoninet2 0:795de307e97f 483 void disable_payload_with_ack();
emoninet2 0:795de307e97f 484 void enable_dynamic_payload_with_ack();
emoninet2 0:795de307e97f 485 void disable_dynamic_payload_with_ack();
emoninet2 0:795de307e97f 486 /**@}*/
emoninet2 0:795de307e97f 487
emoninet2 0:795de307e97f 488
emoninet2 0:795de307e97f 489 /**
emoninet2 0:795de307e97f 490 * @brief Initialize
emoninet2 0:795de307e97f 491 * hardware initialization of the NRF24L01+
emoninet2 0:795de307e97f 492 */
emoninet2 0:795de307e97f 493
emoninet2 0:795de307e97f 494 void init();
emoninet2 0:795de307e97f 495 int startup();
emoninet2 0:795de307e97f 496 int default_config();
emoninet2 0:795de307e97f 497 int stateMode(nRF24L01P_Mode_Type mode);
emoninet2 0:795de307e97f 498
emoninet2 0:795de307e97f 499 bool readable();
emoninet2 0:795de307e97f 500 bool writable();
emoninet2 0:795de307e97f 501
emoninet2 0:795de307e97f 502
emoninet2 0:795de307e97f 503 int send(uint8_t *data, int datalen);
emoninet2 0:795de307e97f 504 int send_to_address(pipeAddrType_t address, uint8_t *data, int datalen);
emoninet2 0:795de307e97f 505 int send_to_address_ack(pipeAddrType_t address, uint8_t *data, int datalen);
emoninet2 0:795de307e97f 506 bool readableOnPipe(_nrf24l01p_pipe_t pipe);
emoninet2 0:795de307e97f 507 int read(_nrf24l01p_pipe_t pipe, uint8_t *data, int datalen);
emoninet2 0:795de307e97f 508 int read_dyn_pld(_nrf24l01p_pipe_t pipe, uint8_t *data);
emoninet2 0:795de307e97f 509 void write_ack(_nrf24l01p_pipe_t pipe, uint8_t *data, int datalen);
emoninet2 0:795de307e97f 510
emoninet2 0:795de307e97f 511 void PTX();
emoninet2 0:795de307e97f 512 void PRX();
emoninet2 0:795de307e97f 513
emoninet2 0:795de307e97f 514 /**@}*/
emoninet2 0:795de307e97f 515
emoninet2 0:795de307e97f 516
emoninet2 0:795de307e97f 517
emoninet2 0:795de307e97f 518
emoninet2 0:795de307e97f 519
emoninet2 0:795de307e97f 520
emoninet2 0:795de307e97f 521
emoninet2 0:795de307e97f 522 ~nrf24l01p();
emoninet2 0:795de307e97f 523 protected:
emoninet2 0:795de307e97f 524
emoninet2 0:795de307e97f 525 private:
emoninet2 0:795de307e97f 526 nrf24l01p( const nrf24l01p &c );
emoninet2 0:795de307e97f 527 nrf24l01p& operator=( const nrf24l01p &c );
emoninet2 0:795de307e97f 528
emoninet2 0:795de307e97f 529
emoninet2 0:795de307e97f 530
emoninet2 0:795de307e97f 531
emoninet2 0:795de307e97f 532
emoninet2 0:795de307e97f 533
emoninet2 0:795de307e97f 534
emoninet2 0:795de307e97f 535 }; //nrf24l01p
emoninet2 0:795de307e97f 536
emoninet2 0:795de307e97f 537 #endif //__NRF24L01P_H__
emoninet2 0:795de307e97f 538