Habibur Rahman / NRF24L01P

stable library for the Nordic NRF24L01+ radio transciever

nrf24l01p.cpp@0:795de307e97f, 2016-11-21 (annotated)

Committer:
emoninet2
Date:
Mon Nov 21 19:39:46 2016 +0000
Revision:
0:795de307e97f
ported NRF24L01P library for the mbed after converting to c++ class

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emoninet2 0:795de307e97f 1 /*
emoninet2 0:795de307e97f 2 * nrf24l01p.cpp
emoninet2 0:795de307e97f 3 *
emoninet2 0:795de307e97f 4 * Created: 29-Mar-16 10:57:13 PM
emoninet2 0:795de307e97f 5 * Author: emon1
emoninet2 0:795de307e97f 6 */
emoninet2 0:795de307e97f 7
emoninet2 0:795de307e97f 8 #include "nrf24l01p.h"
emoninet2 0:795de307e97f 9
emoninet2 0:795de307e97f 10 // default constructor
emoninet2 0:795de307e97f 11 //nrf24l01p::nrf24l01p()
emoninet2 0:795de307e97f 12 //{
emoninet2 0:795de307e97f 13 // init();
emoninet2 0:795de307e97f 14 //} //nrf24l01p
emoninet2 0:795de307e97f 15
emoninet2 0:795de307e97f 16 nrf24l01p::nrf24l01p(PinName mosi,
emoninet2 0:795de307e97f 17 PinName miso,
emoninet2 0:795de307e97f 18 PinName sck,
emoninet2 0:795de307e97f 19 PinName csn,
emoninet2 0:795de307e97f 20 PinName ce,
emoninet2 0:795de307e97f 21 PinName irq)
emoninet2 0:795de307e97f 22 : spi_(mosi, miso, sck), nCS_(csn), ce_(ce), nIRQ_(irq) {
emoninet2 0:795de307e97f 23
emoninet2 0:795de307e97f 24 }
emoninet2 0:795de307e97f 25
emoninet2 0:795de307e97f 26 void nrf24l01p::arch_nrf24l01p_ce_pin(bool state){
emoninet2 0:795de307e97f 27 ce_ = state;
emoninet2 0:795de307e97f 28 }
emoninet2 0:795de307e97f 29 void nrf24l01p::arch_nrf24l01p_csn_pin(bool state){
emoninet2 0:795de307e97f 30 nCS_ = state;
emoninet2 0:795de307e97f 31 }
emoninet2 0:795de307e97f 32 void nrf24l01p::arch_nrf24l01p_initialize(){
emoninet2 0:795de307e97f 33 }
emoninet2 0:795de307e97f 34
emoninet2 0:795de307e97f 35 void nrf24l01p::arch_spi_master_transcieve(uint8_t *data, int len){
emoninet2 0:795de307e97f 36 int i=0;
emoninet2 0:795de307e97f 37 for(i=0;i<len;i++){
emoninet2 0:795de307e97f 38 data[i] = spi_.write(data[i]);
emoninet2 0:795de307e97f 39 }
emoninet2 0:795de307e97f 40
emoninet2 0:795de307e97f 41
emoninet2 0:795de307e97f 42 }
emoninet2 0:795de307e97f 43
emoninet2 0:795de307e97f 44
emoninet2 0:795de307e97f 45
emoninet2 0:795de307e97f 46
emoninet2 0:795de307e97f 47 void nrf24l01p::ce_pin(bool state){
emoninet2 0:795de307e97f 48 arch_nrf24l01p_ce_pin(state);
emoninet2 0:795de307e97f 49 if(state) _nrf24l01p_delay_us(_NRF24L01P_TIMING_Thce_us);
emoninet2 0:795de307e97f 50 //_nrf24l01p_ce_value = state;
emoninet2 0:795de307e97f 51 }
emoninet2 0:795de307e97f 52 void nrf24l01p::csn_pin(bool state){
emoninet2 0:795de307e97f 53
emoninet2 0:795de307e97f 54 arch_nrf24l01p_csn_pin(state);
emoninet2 0:795de307e97f 55 //_nrf24l01p_csn_value = state;
emoninet2 0:795de307e97f 56 }
emoninet2 0:795de307e97f 57
emoninet2 0:795de307e97f 58
emoninet2 0:795de307e97f 59
emoninet2 0:795de307e97f 60
emoninet2 0:795de307e97f 61
emoninet2 0:795de307e97f 62
emoninet2 0:795de307e97f 63 void nrf24l01p::read_register(uint8_t address, uint8_t *data, int len){
emoninet2 0:795de307e97f 64
emoninet2 0:795de307e97f 65 csn_pin(0);
emoninet2 0:795de307e97f 66 uint8_t temp = (address&(_NRF24L01P_REG_ADDRESS_MASK));
emoninet2 0:795de307e97f 67 arch_spi_master_transcieve(&temp,1);
emoninet2 0:795de307e97f 68 arch_spi_master_transcieve(data,len);
emoninet2 0:795de307e97f 69 csn_pin(1);
emoninet2 0:795de307e97f 70 }
emoninet2 0:795de307e97f 71
emoninet2 0:795de307e97f 72 void nrf24l01p::write_register(uint8_t address, uint8_t *data, int len){
emoninet2 0:795de307e97f 73 csn_pin(0);
emoninet2 0:795de307e97f 74 uint8_t temp = (( _NRF24L01P_SPI_CMD_WR_REG | (address&(_NRF24L01P_REG_ADDRESS_MASK))));
emoninet2 0:795de307e97f 75 arch_spi_master_transcieve(&temp,1);
emoninet2 0:795de307e97f 76 arch_spi_master_transcieve(data,len);
emoninet2 0:795de307e97f 77 csn_pin(1);
emoninet2 0:795de307e97f 78 }
emoninet2 0:795de307e97f 79
emoninet2 0:795de307e97f 80
emoninet2 0:795de307e97f 81
emoninet2 0:795de307e97f 82 void nrf24l01p::read_rx_payload(uint8_t *data, int pay_len){
emoninet2 0:795de307e97f 83 csn_pin(0);
emoninet2 0:795de307e97f 84 uint8_t temp = (_NRF24L01P_SPI_CMD_RD_RX_PAYLOAD);
emoninet2 0:795de307e97f 85 arch_spi_master_transcieve(&temp,1);
emoninet2 0:795de307e97f 86 arch_spi_master_transcieve(data,pay_len);
emoninet2 0:795de307e97f 87 csn_pin(1);
emoninet2 0:795de307e97f 88 }
emoninet2 0:795de307e97f 89 void nrf24l01p::write_tx_payload(uint8_t *data, int pay_len){
emoninet2 0:795de307e97f 90 csn_pin(0);
emoninet2 0:795de307e97f 91 uint8_t temp = (_NRF24L01P_SPI_CMD_WR_TX_PAYLOAD);
emoninet2 0:795de307e97f 92 arch_spi_master_transcieve(&temp,1);
emoninet2 0:795de307e97f 93 arch_spi_master_transcieve(data,pay_len);
emoninet2 0:795de307e97f 94 csn_pin(1);
emoninet2 0:795de307e97f 95 }
emoninet2 0:795de307e97f 96
emoninet2 0:795de307e97f 97 void nrf24l01p::flush_tx(){
emoninet2 0:795de307e97f 98 csn_pin(0);
emoninet2 0:795de307e97f 99 uint8_t temp = (_NRF24L01P_SPI_CMD_FLUSH_TX);
emoninet2 0:795de307e97f 100 arch_spi_master_transcieve(&temp,1);
emoninet2 0:795de307e97f 101 csn_pin(1);
emoninet2 0:795de307e97f 102 }
emoninet2 0:795de307e97f 103 void nrf24l01p::flush_rx(){
emoninet2 0:795de307e97f 104 csn_pin(0);
emoninet2 0:795de307e97f 105 uint8_t temp = (_NRF24L01P_SPI_CMD_FLUSH_RX);
emoninet2 0:795de307e97f 106 arch_spi_master_transcieve(&temp,1);
emoninet2 0:795de307e97f 107 csn_pin(1);
emoninet2 0:795de307e97f 108 }
emoninet2 0:795de307e97f 109 void nrf24l01p::reuse_tx_payload(){
emoninet2 0:795de307e97f 110 csn_pin(0);
emoninet2 0:795de307e97f 111 uint8_t temp = (_NRF24L01P_SPI_CMD_REUSE_TX_PL);
emoninet2 0:795de307e97f 112 arch_spi_master_transcieve(&temp,1);
emoninet2 0:795de307e97f 113 csn_pin(1);
emoninet2 0:795de307e97f 114 }
emoninet2 0:795de307e97f 115 int nrf24l01p::read_rx_payload_width(){
emoninet2 0:795de307e97f 116 csn_pin(0);
emoninet2 0:795de307e97f 117 uint8_t temp = (_NRF24L01P_SPI_CMD_R_RX_PL_WID);
emoninet2 0:795de307e97f 118 uint8_t temp2 = 0xff;
emoninet2 0:795de307e97f 119 arch_spi_master_transcieve(&temp,1);
emoninet2 0:795de307e97f 120 arch_spi_master_transcieve(&temp2,1);
emoninet2 0:795de307e97f 121 csn_pin(1);
emoninet2 0:795de307e97f 122 return temp2;
emoninet2 0:795de307e97f 123 }
emoninet2 0:795de307e97f 124
emoninet2 0:795de307e97f 125 void nrf24l01p::write_ack_payload(_nrf24l01p_pipe_t pipe, uint8_t *data, int pay_len){
emoninet2 0:795de307e97f 126 csn_pin(0);
emoninet2 0:795de307e97f 127 uint8_t temp = (_NRF24L01P_SPI_CMD_W_ACK_PAYLOAD | pipe);
emoninet2 0:795de307e97f 128 arch_spi_master_transcieve(&temp,1);
emoninet2 0:795de307e97f 129 arch_spi_master_transcieve(data,pay_len);
emoninet2 0:795de307e97f 130 csn_pin(1);
emoninet2 0:795de307e97f 131 }
emoninet2 0:795de307e97f 132 void nrf24l01p::write_tx_payload_noack(uint8_t *data, int pay_len){
emoninet2 0:795de307e97f 133 csn_pin(0);
emoninet2 0:795de307e97f 134 uint8_t temp = (_NRF24L01P_SPI_CMD_W_TX_PYLD_NO_ACK);
emoninet2 0:795de307e97f 135 arch_spi_master_transcieve(&temp,1);
emoninet2 0:795de307e97f 136 arch_spi_master_transcieve(data,pay_len);
emoninet2 0:795de307e97f 137 csn_pin(1);
emoninet2 0:795de307e97f 138 }
emoninet2 0:795de307e97f 139
emoninet2 0:795de307e97f 140 int nrf24l01p::get_status(){
emoninet2 0:795de307e97f 141 csn_pin(0);
emoninet2 0:795de307e97f 142 uint8_t temp = (_NRF24L01P_SPI_CMD_NOP );
emoninet2 0:795de307e97f 143 arch_spi_master_transcieve(&temp,1);
emoninet2 0:795de307e97f 144 csn_pin(1);
emoninet2 0:795de307e97f 145 return temp;
emoninet2 0:795de307e97f 146 }
emoninet2 0:795de307e97f 147
emoninet2 0:795de307e97f 148
emoninet2 0:795de307e97f 149
emoninet2 0:795de307e97f 150 void nrf24l01p::power_up(){
emoninet2 0:795de307e97f 151 uint8_t temp;
emoninet2 0:795de307e97f 152 read_register(_NRF24L01P_REG_CONFIG,&temp,sizeof(temp));
emoninet2 0:795de307e97f 153 temp |= _NRF24L01P_CONFIG_PWR_UP;
emoninet2 0:795de307e97f 154 write_register(_NRF24L01P_REG_CONFIG,&temp,sizeof(temp));
emoninet2 0:795de307e97f 155
emoninet2 0:795de307e97f 156 }
emoninet2 0:795de307e97f 157 void nrf24l01p::power_down(){
emoninet2 0:795de307e97f 158 uint8_t temp;
emoninet2 0:795de307e97f 159 read_register(_NRF24L01P_REG_CONFIG,&temp,sizeof(temp));
emoninet2 0:795de307e97f 160 temp &= ~_NRF24L01P_CONFIG_PWR_UP;
emoninet2 0:795de307e97f 161 write_register(_NRF24L01P_REG_CONFIG,&temp,sizeof(temp));
emoninet2 0:795de307e97f 162
emoninet2 0:795de307e97f 163 }
emoninet2 0:795de307e97f 164 void nrf24l01p::rx_mode(){
emoninet2 0:795de307e97f 165 uint8_t temp;
emoninet2 0:795de307e97f 166 read_register(_NRF24L01P_REG_CONFIG,&temp,sizeof(temp));
emoninet2 0:795de307e97f 167 temp |= _NRF24L01P_CONFIG_PRIM_RX;
emoninet2 0:795de307e97f 168 write_register(_NRF24L01P_REG_CONFIG,&temp,sizeof(temp));
emoninet2 0:795de307e97f 169
emoninet2 0:795de307e97f 170 }
emoninet2 0:795de307e97f 171 void nrf24l01p::tx_mode(){
emoninet2 0:795de307e97f 172 uint8_t temp;
emoninet2 0:795de307e97f 173 read_register(_NRF24L01P_REG_CONFIG,&temp,sizeof(temp));
emoninet2 0:795de307e97f 174 temp &= ~_NRF24L01P_CONFIG_PRIM_RX;
emoninet2 0:795de307e97f 175 write_register(_NRF24L01P_REG_CONFIG,&temp,sizeof(temp));
emoninet2 0:795de307e97f 176
emoninet2 0:795de307e97f 177 }
emoninet2 0:795de307e97f 178 void nrf24l01p::set_CRC(_nrf24l01p_crc_t opt){
emoninet2 0:795de307e97f 179 uint8_t temp;
emoninet2 0:795de307e97f 180 read_register(_NRF24L01P_REG_CONFIG,&temp,sizeof(temp));
emoninet2 0:795de307e97f 181 temp &= ~(_NRF24L01P_CONFIG_CRC_MASK);
emoninet2 0:795de307e97f 182 temp |= opt;
emoninet2 0:795de307e97f 183 write_register(_NRF24L01P_REG_CONFIG,&temp,sizeof(temp));
emoninet2 0:795de307e97f 184 }
emoninet2 0:795de307e97f 185
emoninet2 0:795de307e97f 186 void nrf24l01p::enable_auto_ack(_nrf24l01p_pipe_t pipe){
emoninet2 0:795de307e97f 187 uint8_t temp;
emoninet2 0:795de307e97f 188 read_register(_NRF24L01P_REG_EN_AA,&temp,sizeof(temp));
emoninet2 0:795de307e97f 189 set_bit(temp,pipe);
emoninet2 0:795de307e97f 190 write_register(_NRF24L01P_REG_EN_AA,&temp,sizeof(temp));
emoninet2 0:795de307e97f 191 }
emoninet2 0:795de307e97f 192 void nrf24l01p::disable_auto_ack(_nrf24l01p_pipe_t pipe){
emoninet2 0:795de307e97f 193 uint8_t temp;
emoninet2 0:795de307e97f 194 read_register(_NRF24L01P_REG_EN_AA,&temp,sizeof(temp));
emoninet2 0:795de307e97f 195 clr_bit(temp,pipe);
emoninet2 0:795de307e97f 196 write_register(_NRF24L01P_REG_EN_AA,&temp,sizeof(temp));
emoninet2 0:795de307e97f 197 }
emoninet2 0:795de307e97f 198 void nrf24l01p::disable_auto_ack_all_pipes(){
emoninet2 0:795de307e97f 199 uint8_t temp = 0;
emoninet2 0:795de307e97f 200 write_register(_NRF24L01P_REG_EN_AA,&temp,sizeof(temp));
emoninet2 0:795de307e97f 201 }
emoninet2 0:795de307e97f 202
emoninet2 0:795de307e97f 203 void nrf24l01p::enable_rx_on_pipe(_nrf24l01p_pipe_t pipe){
emoninet2 0:795de307e97f 204 uint8_t temp;
emoninet2 0:795de307e97f 205 read_register(_NRF24L01P_REG_EN_RXADDR,&temp,sizeof(temp));
emoninet2 0:795de307e97f 206 set_bit(temp,pipe);
emoninet2 0:795de307e97f 207 write_register(_NRF24L01P_REG_EN_RXADDR,&temp,sizeof(temp));
emoninet2 0:795de307e97f 208 }
emoninet2 0:795de307e97f 209 void nrf24l01p::disable_rx_on_pipe(_nrf24l01p_pipe_t pipe){
emoninet2 0:795de307e97f 210 uint8_t temp;
emoninet2 0:795de307e97f 211 read_register(_NRF24L01P_REG_EN_RXADDR,&temp,sizeof(temp));
emoninet2 0:795de307e97f 212 clr_bit(temp,pipe);
emoninet2 0:795de307e97f 213 write_register(_NRF24L01P_REG_EN_RXADDR,&temp,sizeof(temp));
emoninet2 0:795de307e97f 214 }
emoninet2 0:795de307e97f 215
emoninet2 0:795de307e97f 216
emoninet2 0:795de307e97f 217 void nrf24l01p::set_address_width(_nrf24l01p_aw_t width){
emoninet2 0:795de307e97f 218 uint8_t temp = width;
emoninet2 0:795de307e97f 219 write_register(_NRF24L01P_REG_SETUP_AW,&temp,sizeof(temp));
emoninet2 0:795de307e97f 220 }
emoninet2 0:795de307e97f 221
emoninet2 0:795de307e97f 222 _nrf24l01p_aw_t nrf24l01p::get_address_width(){
emoninet2 0:795de307e97f 223 uint8_t temp;
emoninet2 0:795de307e97f 224 read_register(_NRF24L01P_REG_SETUP_AW,&temp,sizeof(temp));
emoninet2 0:795de307e97f 225 return (_nrf24l01p_aw_t) temp;
emoninet2 0:795de307e97f 226 }
emoninet2 0:795de307e97f 227
emoninet2 0:795de307e97f 228 void nrf24l01p::set_auto_retransmission_count(uint8_t count){
emoninet2 0:795de307e97f 229 uint8_t temp;
emoninet2 0:795de307e97f 230 read_register(_NRF24L01P_REG_SETUP_RETR,&temp,sizeof(temp));
emoninet2 0:795de307e97f 231 temp &= ~ 0x0F;
emoninet2 0:795de307e97f 232 temp |= (count<<0);
emoninet2 0:795de307e97f 233 write_register(_NRF24L01P_REG_SETUP_RETR,&temp,sizeof(temp));
emoninet2 0:795de307e97f 234 }
emoninet2 0:795de307e97f 235 uint8_t nrf24l01p::read_auto_retransmission_count(){
emoninet2 0:795de307e97f 236 uint8_t temp;
emoninet2 0:795de307e97f 237 read_register(_NRF24L01P_REG_SETUP_RETR,&temp,sizeof(temp));
emoninet2 0:795de307e97f 238 return temp & 0x0F;
emoninet2 0:795de307e97f 239 }
emoninet2 0:795de307e97f 240 void nrf24l01p::set_auto_retransmission_delay(uint8_t times250us){
emoninet2 0:795de307e97f 241 uint8_t temp;
emoninet2 0:795de307e97f 242 read_register(_NRF24L01P_REG_SETUP_RETR,&temp,sizeof(temp));
emoninet2 0:795de307e97f 243 temp &= ~(0xF0);
emoninet2 0:795de307e97f 244 temp |= (times250us<<4);
emoninet2 0:795de307e97f 245 write_register(_NRF24L01P_REG_SETUP_RETR,&temp,sizeof(temp));
emoninet2 0:795de307e97f 246 }
emoninet2 0:795de307e97f 247 uint8_t nrf24l01p::read_auto_retransmission_delay(){
emoninet2 0:795de307e97f 248 uint8_t temp;
emoninet2 0:795de307e97f 249 read_register(_NRF24L01P_REG_SETUP_RETR,&temp,sizeof(temp));
emoninet2 0:795de307e97f 250 return temp & 0xF0;
emoninet2 0:795de307e97f 251 }
emoninet2 0:795de307e97f 252
emoninet2 0:795de307e97f 253
emoninet2 0:795de307e97f 254
emoninet2 0:795de307e97f 255 void nrf24l01p::set_frequency_offset(uint8_t offset){
emoninet2 0:795de307e97f 256 if( (offset >=0) && ( offset <= 125)){
emoninet2 0:795de307e97f 257 write_register(_NRF24L01P_REG_RF_CH,&offset,sizeof(offset));
emoninet2 0:795de307e97f 258 }
emoninet2 0:795de307e97f 259 }
emoninet2 0:795de307e97f 260 uint8_t nrf24l01p::get_frequency_offset(){
emoninet2 0:795de307e97f 261 uint8_t temp;
emoninet2 0:795de307e97f 262 read_register(_NRF24L01P_REG_RF_CH,&temp,sizeof(temp));
emoninet2 0:795de307e97f 263 return temp;
emoninet2 0:795de307e97f 264 }
emoninet2 0:795de307e97f 265
emoninet2 0:795de307e97f 266 void nrf24l01p::set_DataRate(_nrf24l01p_datarate_t DataRate){
emoninet2 0:795de307e97f 267 uint8_t temp;
emoninet2 0:795de307e97f 268 read_register(_NRF24L01P_REG_RF_SETUP,&temp,sizeof(temp));
emoninet2 0:795de307e97f 269 temp &= ~_NRF24L01P_RF_SETUP_RF_DR_MASK;
emoninet2 0:795de307e97f 270 temp |= DataRate;
emoninet2 0:795de307e97f 271 write_register(_NRF24L01P_REG_RF_SETUP,&temp,sizeof(temp));
emoninet2 0:795de307e97f 272
emoninet2 0:795de307e97f 273 }
emoninet2 0:795de307e97f 274 _nrf24l01p_datarate_t nrf24l01p::get_DataRate(){
emoninet2 0:795de307e97f 275 uint8_t temp;
emoninet2 0:795de307e97f 276 read_register(_NRF24L01P_REG_RF_SETUP,&temp,sizeof(temp));
emoninet2 0:795de307e97f 277 temp &= _NRF24L01P_RF_SETUP_RF_DR_MASK;
emoninet2 0:795de307e97f 278 return (_nrf24l01p_datarate_t) temp;
emoninet2 0:795de307e97f 279 }
emoninet2 0:795de307e97f 280 void nrf24l01p::set_RF_Power(_nrf24l01p_RFpower_t RFpower){
emoninet2 0:795de307e97f 281 uint8_t temp;
emoninet2 0:795de307e97f 282 read_register(_NRF24L01P_REG_RF_SETUP,&temp,sizeof(temp));
emoninet2 0:795de307e97f 283 temp &= ~_NRF24L01P_RF_SETUP_RF_PWR_MASK;
emoninet2 0:795de307e97f 284 temp |= RFpower;
emoninet2 0:795de307e97f 285 write_register(_NRF24L01P_REG_RF_SETUP,&temp,sizeof(temp));
emoninet2 0:795de307e97f 286 }
emoninet2 0:795de307e97f 287 _nrf24l01p_RFpower_t nrf24l01p::get_RF_Power(){
emoninet2 0:795de307e97f 288 uint8_t temp;
emoninet2 0:795de307e97f 289 read_register(_NRF24L01P_REG_RF_SETUP,&temp,sizeof(temp));
emoninet2 0:795de307e97f 290 temp &= _NRF24L01P_RF_SETUP_RF_PWR_MASK;
emoninet2 0:795de307e97f 291 return (_nrf24l01p_RFpower_t) temp;
emoninet2 0:795de307e97f 292 }
emoninet2 0:795de307e97f 293
emoninet2 0:795de307e97f 294
emoninet2 0:795de307e97f 295 bool nrf24l01p::get_tx_fifo_full_flag(){
emoninet2 0:795de307e97f 296 bool flag;
emoninet2 0:795de307e97f 297 //(get_status()&_NRF24L01P_STATUS_TX_FULL)?flag = 1 : flag = 0;
emoninet2 0:795de307e97f 298
emoninet2 0:795de307e97f 299 if(get_status()&_NRF24L01P_STATUS_TX_FULL) flag = 1;
emoninet2 0:795de307e97f 300 else flag = 0;
emoninet2 0:795de307e97f 301
emoninet2 0:795de307e97f 302 return flag;
emoninet2 0:795de307e97f 303 }
emoninet2 0:795de307e97f 304 bool nrf24l01p::get_max_retry_flag(){
emoninet2 0:795de307e97f 305 bool flag;
emoninet2 0:795de307e97f 306 //(get_status()&_NRF24L01P_STATUS_MAX_RT)?flag = 1 : flag = 0;
emoninet2 0:795de307e97f 307 if(get_status()&_NRF24L01P_STATUS_MAX_RT) flag = 1;
emoninet2 0:795de307e97f 308 else flag = 0;
emoninet2 0:795de307e97f 309 return flag;
emoninet2 0:795de307e97f 310 }
emoninet2 0:795de307e97f 311
emoninet2 0:795de307e97f 312
emoninet2 0:795de307e97f 313 void nrf24l01p::clear_max_retry_flag(){
emoninet2 0:795de307e97f 314 uint8_t temp = get_status();
emoninet2 0:795de307e97f 315 temp |= _NRF24L01P_STATUS_MAX_RT;
emoninet2 0:795de307e97f 316 write_register(_NRF24L01P_REG_STATUS,&temp,sizeof(temp));
emoninet2 0:795de307e97f 317 }
emoninet2 0:795de307e97f 318
emoninet2 0:795de307e97f 319 bool nrf24l01p::get_data_sent_flag(){
emoninet2 0:795de307e97f 320 bool flag;
emoninet2 0:795de307e97f 321 //(get_status()&_NRF24L01P_STATUS_TX_DS)?flag = 1 : flag = 0;
emoninet2 0:795de307e97f 322 if(get_status()&_NRF24L01P_STATUS_TX_DS) flag = 1;
emoninet2 0:795de307e97f 323 else flag = 0;
emoninet2 0:795de307e97f 324 return flag;
emoninet2 0:795de307e97f 325 }
emoninet2 0:795de307e97f 326
emoninet2 0:795de307e97f 327 void nrf24l01p::clear_data_sent_flag(){
emoninet2 0:795de307e97f 328 uint8_t temp = get_status();
emoninet2 0:795de307e97f 329 temp |= _NRF24L01P_STATUS_TX_DS;
emoninet2 0:795de307e97f 330 write_register(_NRF24L01P_REG_STATUS,&temp,sizeof(temp));
emoninet2 0:795de307e97f 331 }
emoninet2 0:795de307e97f 332
emoninet2 0:795de307e97f 333 bool nrf24l01p::get_data_ready_flag(){
emoninet2 0:795de307e97f 334 bool flag;
emoninet2 0:795de307e97f 335 if(get_status()&_NRF24L01P_STATUS_RX_DR)flag = 1 ;
emoninet2 0:795de307e97f 336 else flag = 0;
emoninet2 0:795de307e97f 337 return flag;
emoninet2 0:795de307e97f 338 }
emoninet2 0:795de307e97f 339
emoninet2 0:795de307e97f 340 void nrf24l01p::clear_data_ready_flag(){
emoninet2 0:795de307e97f 341 uint8_t temp = get_status();
emoninet2 0:795de307e97f 342 temp |= _NRF24L01P_STATUS_RX_DR;
emoninet2 0:795de307e97f 343 write_register(_NRF24L01P_REG_STATUS,&temp,sizeof(temp));
emoninet2 0:795de307e97f 344 }
emoninet2 0:795de307e97f 345
emoninet2 0:795de307e97f 346 _nrf24l01p_pipe_t nrf24l01p::get_rx_payload_pipe(){
emoninet2 0:795de307e97f 347 _nrf24l01p_pipe_t pipe = (_nrf24l01p_pipe_t) ((get_status()&_NRF24L01P_STATUS_RX_P_NO)>>1);
emoninet2 0:795de307e97f 348 return pipe;
emoninet2 0:795de307e97f 349 }
emoninet2 0:795de307e97f 350
emoninet2 0:795de307e97f 351 uint8_t nrf24l01p::get_arc_count(){
emoninet2 0:795de307e97f 352 uint8_t temp;
emoninet2 0:795de307e97f 353 read_register(_NRF24L01P_REG_OBSERVE_TX,&temp,sizeof(temp));
emoninet2 0:795de307e97f 354 return ((temp>>_NRF24L01P_OBSERVE_TX_ARC_CNT_BP)&_NRF24L01P_OBSERVE_TX_ARC_CNT_MASK);
emoninet2 0:795de307e97f 355
emoninet2 0:795de307e97f 356 }
emoninet2 0:795de307e97f 357 uint8_t nrf24l01p::get_plos_count(){
emoninet2 0:795de307e97f 358 uint8_t temp;
emoninet2 0:795de307e97f 359 read_register(_NRF24L01P_REG_OBSERVE_TX,&temp,sizeof(temp));
emoninet2 0:795de307e97f 360 return ((temp>>_NRF24L01P_OBSERVE_TX_PLOS_CNT_BP)&_NRF24L01P_OBSERVE_TX_PLOS_CNT_MASK);
emoninet2 0:795de307e97f 361 }
emoninet2 0:795de307e97f 362
emoninet2 0:795de307e97f 363 bool nrf24l01p::get_rpd(){
emoninet2 0:795de307e97f 364 uint8_t temp;
emoninet2 0:795de307e97f 365 bool flag;
emoninet2 0:795de307e97f 366 read_register(_NRF24L01P_REG_RPD,&temp,sizeof(temp));
emoninet2 0:795de307e97f 367 if(temp!=0) flag = 1 ;
emoninet2 0:795de307e97f 368 else flag = 0;
emoninet2 0:795de307e97f 369 return flag;
emoninet2 0:795de307e97f 370 }
emoninet2 0:795de307e97f 371
emoninet2 0:795de307e97f 372 void nrf24l01p::set_RX_pipe_address(_nrf24l01p_pipe_t pipe,uint64_t address){
emoninet2 0:795de307e97f 373 int max_pipe_addr_width = 0;
emoninet2 0:795de307e97f 374
emoninet2 0:795de307e97f 375 if((pipe>=0) && (pipe<=1) )
emoninet2 0:795de307e97f 376 {
emoninet2 0:795de307e97f 377 max_pipe_addr_width = 5;
emoninet2 0:795de307e97f 378 }
emoninet2 0:795de307e97f 379 else if ((pipe>=2) && (pipe<=5) ){
emoninet2 0:795de307e97f 380 max_pipe_addr_width = 1;
emoninet2 0:795de307e97f 381 }
emoninet2 0:795de307e97f 382
emoninet2 0:795de307e97f 383
emoninet2 0:795de307e97f 384
emoninet2 0:795de307e97f 385 uint8_t temp[5];
emoninet2 0:795de307e97f 386 int i;
emoninet2 0:795de307e97f 387 for(i=0;i<max_pipe_addr_width;i++){
emoninet2 0:795de307e97f 388 temp[i] = (address>>(8*i))&0xFF;
emoninet2 0:795de307e97f 389 }
emoninet2 0:795de307e97f 390 write_register(_NRF24L01P_REG_RX_ADDR_P0 + pipe,temp,max_pipe_addr_width);
emoninet2 0:795de307e97f 391
emoninet2 0:795de307e97f 392 }
emoninet2 0:795de307e97f 393 uint64_t nrf24l01p::get_RX_pipe_address(_nrf24l01p_pipe_t pipe){
emoninet2 0:795de307e97f 394
emoninet2 0:795de307e97f 395 int max_pipe_addr_width = 0;
emoninet2 0:795de307e97f 396
emoninet2 0:795de307e97f 397 if((pipe>=0) && (pipe<=1) )
emoninet2 0:795de307e97f 398 {
emoninet2 0:795de307e97f 399 max_pipe_addr_width = 5;
emoninet2 0:795de307e97f 400 }
emoninet2 0:795de307e97f 401 else if ((pipe>=2) && (pipe<=5) ){
emoninet2 0:795de307e97f 402 max_pipe_addr_width = 1;
emoninet2 0:795de307e97f 403 }
emoninet2 0:795de307e97f 404
emoninet2 0:795de307e97f 405 uint8_t temp[5];
emoninet2 0:795de307e97f 406 read_register(_NRF24L01P_REG_RX_ADDR_P0 + pipe,temp,max_pipe_addr_width);
emoninet2 0:795de307e97f 407
emoninet2 0:795de307e97f 408 uint64_t temp_addr = 0;
emoninet2 0:795de307e97f 409 uint8_t *temp_addr_ptr = (uint8_t*) &temp_addr;
emoninet2 0:795de307e97f 410 int i;
emoninet2 0:795de307e97f 411 for(i=0;i<max_pipe_addr_width;i++){
emoninet2 0:795de307e97f 412 *(temp_addr_ptr+i)|= (temp[i]);
emoninet2 0:795de307e97f 413 }
emoninet2 0:795de307e97f 414
emoninet2 0:795de307e97f 415 return temp_addr;
emoninet2 0:795de307e97f 416 }
emoninet2 0:795de307e97f 417
emoninet2 0:795de307e97f 418 void nrf24l01p::set_TX_pipe_address(uint64_t address){
emoninet2 0:795de307e97f 419 uint8_t temp[5];
emoninet2 0:795de307e97f 420 int i;
emoninet2 0:795de307e97f 421 for( i=0;i<5;i++){
emoninet2 0:795de307e97f 422 temp[i] = (address>>(8*i))&0xFF;
emoninet2 0:795de307e97f 423 }
emoninet2 0:795de307e97f 424 write_register(_NRF24L01P_REG_TX_ADDR,temp,5);
emoninet2 0:795de307e97f 425 }
emoninet2 0:795de307e97f 426
emoninet2 0:795de307e97f 427 uint64_t nrf24l01p::get_TX_pipe_address(){
emoninet2 0:795de307e97f 428 uint8_t temp[5];
emoninet2 0:795de307e97f 429 read_register(_NRF24L01P_REG_TX_ADDR,temp,5);
emoninet2 0:795de307e97f 430
emoninet2 0:795de307e97f 431 uint64_t temp_addr = 0;
emoninet2 0:795de307e97f 432 uint8_t *temp_addr_ptr = (uint8_t*) &temp_addr;
emoninet2 0:795de307e97f 433 int i;
emoninet2 0:795de307e97f 434 for(i=0;i<5;i++){
emoninet2 0:795de307e97f 435 *(temp_addr_ptr+i)|= (temp[i]);
emoninet2 0:795de307e97f 436 }
emoninet2 0:795de307e97f 437
emoninet2 0:795de307e97f 438 return temp_addr;
emoninet2 0:795de307e97f 439
emoninet2 0:795de307e97f 440 }
emoninet2 0:795de307e97f 441 uint8_t nrf24l01p::get_RX_pipe_width(_nrf24l01p_pipe_t pipe){
emoninet2 0:795de307e97f 442 uint8_t temp;
emoninet2 0:795de307e97f 443 read_register((_NRF24L01P_REG_RX_PW_P0+pipe),&temp,sizeof(temp));
emoninet2 0:795de307e97f 444 return (temp&(0x3F));
emoninet2 0:795de307e97f 445 }
emoninet2 0:795de307e97f 446 bool nrf24l01p::get_fifo_flag_rx_empty(){
emoninet2 0:795de307e97f 447 uint8_t temp;
emoninet2 0:795de307e97f 448 bool flag;
emoninet2 0:795de307e97f 449 read_register(_NRF24L01P_REG_FIFO_STATUS,&temp,sizeof(temp));
emoninet2 0:795de307e97f 450 if(temp&_NRF24L01P_FIFO_STATUS_RX_EMPTY) flag = 1 ;
emoninet2 0:795de307e97f 451 else flag = 0;
emoninet2 0:795de307e97f 452 return flag;
emoninet2 0:795de307e97f 453
emoninet2 0:795de307e97f 454 }
emoninet2 0:795de307e97f 455 bool nrf24l01p::get_fifo_flag_rx_full(){
emoninet2 0:795de307e97f 456 uint8_t temp;
emoninet2 0:795de307e97f 457 bool flag;
emoninet2 0:795de307e97f 458 read_register(_NRF24L01P_REG_FIFO_STATUS,&temp,sizeof(temp));
emoninet2 0:795de307e97f 459 if(temp&_NRF24L01P_FIFO_STATUS_RX_FULL) flag = 1 ;
emoninet2 0:795de307e97f 460 else flag = 0;
emoninet2 0:795de307e97f 461 return flag;
emoninet2 0:795de307e97f 462 }
emoninet2 0:795de307e97f 463 bool nrf24l01p::get_fifo_flag_tx_empty(){
emoninet2 0:795de307e97f 464 uint8_t temp;
emoninet2 0:795de307e97f 465 bool flag;
emoninet2 0:795de307e97f 466 read_register(_NRF24L01P_REG_FIFO_STATUS,&temp,sizeof(temp));
emoninet2 0:795de307e97f 467 if(temp&_NRF24L01P_FIFO_STATUS_TX_EMPTY) flag = 1 ;
emoninet2 0:795de307e97f 468 else flag = 0;
emoninet2 0:795de307e97f 469 return flag;
emoninet2 0:795de307e97f 470 }
emoninet2 0:795de307e97f 471
emoninet2 0:795de307e97f 472 bool nrf24l01p::get_fifo_flag_tx_full(){
emoninet2 0:795de307e97f 473 uint8_t temp;
emoninet2 0:795de307e97f 474 bool flag;
emoninet2 0:795de307e97f 475 read_register(_NRF24L01P_REG_FIFO_STATUS,&temp,sizeof(temp));
emoninet2 0:795de307e97f 476 if(temp&_NRF24L01P_FIFO_STATUS_TX_FULL) flag = 1 ;
emoninet2 0:795de307e97f 477 else flag = 0;
emoninet2 0:795de307e97f 478 return flag;
emoninet2 0:795de307e97f 479 }
emoninet2 0:795de307e97f 480 bool nrf24l01p::get_fifo_flag_tx_reuse(){
emoninet2 0:795de307e97f 481 uint8_t temp;
emoninet2 0:795de307e97f 482 bool flag;
emoninet2 0:795de307e97f 483 read_register(_NRF24L01P_REG_FIFO_STATUS,&temp,sizeof(temp));
emoninet2 0:795de307e97f 484 if(temp&_NRF24L01P_FIFO_STATUS_RX_REUSE) flag = 1 ;
emoninet2 0:795de307e97f 485 else flag = 0;
emoninet2 0:795de307e97f 486 return flag;
emoninet2 0:795de307e97f 487 }
emoninet2 0:795de307e97f 488
emoninet2 0:795de307e97f 489 void nrf24l01p::enable_dynamic_payload_pipe(_nrf24l01p_pipe_t pipe){
emoninet2 0:795de307e97f 490 uint8_t temp;
emoninet2 0:795de307e97f 491 read_register(_NRF24L01P_REG_DYNPD,&temp,sizeof(temp));
emoninet2 0:795de307e97f 492 temp |= (1<<pipe);
emoninet2 0:795de307e97f 493 write_register(_NRF24L01P_REG_DYNPD,&temp,sizeof(temp));
emoninet2 0:795de307e97f 494 }
emoninet2 0:795de307e97f 495 void nrf24l01p::disable_dynamic_payload_pipe(_nrf24l01p_pipe_t pipe){
emoninet2 0:795de307e97f 496 uint8_t temp;
emoninet2 0:795de307e97f 497 read_register(_NRF24L01P_REG_DYNPD,&temp,sizeof(temp));
emoninet2 0:795de307e97f 498 temp &= ~(1<<pipe);
emoninet2 0:795de307e97f 499 write_register(_NRF24L01P_REG_DYNPD,&temp,sizeof(temp));
emoninet2 0:795de307e97f 500 }
emoninet2 0:795de307e97f 501 void nrf24l01p::disable_dynamic_payload_all_pipe(){
emoninet2 0:795de307e97f 502 uint8_t temp = 0x00;
emoninet2 0:795de307e97f 503 write_register(_NRF24L01P_REG_DYNPD,&temp,sizeof(temp));
emoninet2 0:795de307e97f 504 }
emoninet2 0:795de307e97f 505 void nrf24l01p::enable_dynamic_payload(){
emoninet2 0:795de307e97f 506 uint8_t temp;
emoninet2 0:795de307e97f 507 read_register(_NRF24L01P_REG_FEATURE,&temp,sizeof(temp));
emoninet2 0:795de307e97f 508 temp |= _NRF24L01_FEATURE_EN_DPL;
emoninet2 0:795de307e97f 509 write_register(_NRF24L01P_REG_FEATURE,&temp,sizeof(temp));
emoninet2 0:795de307e97f 510 }
emoninet2 0:795de307e97f 511 void nrf24l01p::disable_dynamic_payload(){
emoninet2 0:795de307e97f 512 uint8_t temp;
emoninet2 0:795de307e97f 513 read_register(_NRF24L01P_REG_FEATURE,&temp,sizeof(temp));
emoninet2 0:795de307e97f 514 temp &= ~_NRF24L01_FEATURE_EN_DPL;
emoninet2 0:795de307e97f 515 write_register(_NRF24L01P_REG_FEATURE,&temp,sizeof(temp));
emoninet2 0:795de307e97f 516 }
emoninet2 0:795de307e97f 517 void nrf24l01p::enable_payload_with_ack(){
emoninet2 0:795de307e97f 518 uint8_t temp;
emoninet2 0:795de307e97f 519 read_register(_NRF24L01P_REG_FEATURE,&temp,sizeof(temp));
emoninet2 0:795de307e97f 520 temp |= _NRF24L01_FEATURE_EN_ACK_PAY;
emoninet2 0:795de307e97f 521 write_register(_NRF24L01P_REG_FEATURE,&temp,sizeof(temp));
emoninet2 0:795de307e97f 522 }
emoninet2 0:795de307e97f 523 void nrf24l01p::disable_payload_with_ack(){
emoninet2 0:795de307e97f 524 uint8_t temp;
emoninet2 0:795de307e97f 525 read_register(_NRF24L01P_REG_FEATURE,&temp,sizeof(temp));
emoninet2 0:795de307e97f 526 temp &= ~_NRF24L01_FEATURE_EN_ACK_PAY;
emoninet2 0:795de307e97f 527 write_register(_NRF24L01P_REG_FEATURE,&temp,sizeof(temp));
emoninet2 0:795de307e97f 528 }
emoninet2 0:795de307e97f 529 void nrf24l01p::enable_dynamic_payload_with_ack(){
emoninet2 0:795de307e97f 530 uint8_t temp;
emoninet2 0:795de307e97f 531 read_register(_NRF24L01P_REG_FEATURE,&temp,sizeof(temp));
emoninet2 0:795de307e97f 532 temp |= _NRF24L01_FEATURE_EN_DYN_ACK;
emoninet2 0:795de307e97f 533 write_register(_NRF24L01P_REG_FEATURE,&temp,sizeof(temp));
emoninet2 0:795de307e97f 534 }
emoninet2 0:795de307e97f 535 void nrf24l01p::disable_dynamic_payload_with_ack(){
emoninet2 0:795de307e97f 536 uint8_t temp;
emoninet2 0:795de307e97f 537 read_register(_NRF24L01P_REG_FEATURE,&temp,sizeof(temp));
emoninet2 0:795de307e97f 538 temp &= ~_NRF24L01_FEATURE_EN_DYN_ACK;
emoninet2 0:795de307e97f 539 write_register(_NRF24L01P_REG_FEATURE,&temp,sizeof(temp));
emoninet2 0:795de307e97f 540 }
emoninet2 0:795de307e97f 541
emoninet2 0:795de307e97f 542 void nrf24l01p::init(){
emoninet2 0:795de307e97f 543 arch_nrf24l01p_initialize();
emoninet2 0:795de307e97f 544
emoninet2 0:795de307e97f 545 startup();
emoninet2 0:795de307e97f 546 default_config();
emoninet2 0:795de307e97f 547 }
emoninet2 0:795de307e97f 548
emoninet2 0:795de307e97f 549 int nrf24l01p::startup(){
emoninet2 0:795de307e97f 550 ce_pin(0);
emoninet2 0:795de307e97f 551 csn_pin(0);
emoninet2 0:795de307e97f 552
emoninet2 0:795de307e97f 553 _nrf24l01p_delay_ms(_NRF24L01P_TIMING_PowerOnReset_ms);
emoninet2 0:795de307e97f 554
emoninet2 0:795de307e97f 555 stateMode(_NRF24L01P_MODE_POWER_DOWN);
emoninet2 0:795de307e97f 556 stateMode(_NRF24L01P_MODE_RX);
emoninet2 0:795de307e97f 557
emoninet2 0:795de307e97f 558 clear_data_ready_flag();
emoninet2 0:795de307e97f 559 flush_rx();
emoninet2 0:795de307e97f 560 flush_tx();
emoninet2 0:795de307e97f 561
emoninet2 0:795de307e97f 562 uint8_t status_rst_val = 0x0e;//reset status
emoninet2 0:795de307e97f 563 write_register(_NRF24L01P_REG_STATUS, &status_rst_val,1);
emoninet2 0:795de307e97f 564 uint8_t config_rst_val = 0x0b;//reset config
emoninet2 0:795de307e97f 565 write_register(_NRF24L01P_REG_CONFIG, &config_rst_val,1);
emoninet2 0:795de307e97f 566
emoninet2 0:795de307e97f 567 return 0;
emoninet2 0:795de307e97f 568 }
emoninet2 0:795de307e97f 569
emoninet2 0:795de307e97f 570 int nrf24l01p::default_config(){
emoninet2 0:795de307e97f 571
emoninet2 0:795de307e97f 572 disable_auto_ack_all_pipes();
emoninet2 0:795de307e97f 573 disable_dynamic_payload_all_pipe();/////////ALSO CREEATE FOR DISABLE AUTO ACK FOR ALL PIPE
emoninet2 0:795de307e97f 574 //_nrf24l01p_startup();
emoninet2 0:795de307e97f 575
emoninet2 0:795de307e97f 576
emoninet2 0:795de307e97f 577 enable_dynamic_payload();
emoninet2 0:795de307e97f 578 enable_payload_with_ack();
emoninet2 0:795de307e97f 579
emoninet2 0:795de307e97f 580 enable_auto_ack(_NRF24L01P_PIPE_P0);
emoninet2 0:795de307e97f 581 enable_auto_ack(_NRF24L01P_PIPE_P1);
emoninet2 0:795de307e97f 582 enable_auto_ack(_NRF24L01P_PIPE_P2);
emoninet2 0:795de307e97f 583 enable_auto_ack(_NRF24L01P_PIPE_P3);
emoninet2 0:795de307e97f 584 enable_auto_ack(_NRF24L01P_PIPE_P4);
emoninet2 0:795de307e97f 585 enable_auto_ack(_NRF24L01P_PIPE_P5);
emoninet2 0:795de307e97f 586
emoninet2 0:795de307e97f 587 enable_dynamic_payload_pipe(_NRF24L01P_PIPE_P0);
emoninet2 0:795de307e97f 588 enable_dynamic_payload_pipe(_NRF24L01P_PIPE_P1);
emoninet2 0:795de307e97f 589 enable_dynamic_payload_pipe(_NRF24L01P_PIPE_P2);
emoninet2 0:795de307e97f 590 enable_dynamic_payload_pipe(_NRF24L01P_PIPE_P3);
emoninet2 0:795de307e97f 591 enable_dynamic_payload_pipe(_NRF24L01P_PIPE_P4);
emoninet2 0:795de307e97f 592 enable_dynamic_payload_pipe(_NRF24L01P_PIPE_P5);
emoninet2 0:795de307e97f 593
emoninet2 0:795de307e97f 594 enable_rx_on_pipe(_NRF24L01P_PIPE_P0);
emoninet2 0:795de307e97f 595 enable_rx_on_pipe(_NRF24L01P_PIPE_P1);
emoninet2 0:795de307e97f 596 enable_rx_on_pipe(_NRF24L01P_PIPE_P2);
emoninet2 0:795de307e97f 597 enable_rx_on_pipe(_NRF24L01P_PIPE_P3);
emoninet2 0:795de307e97f 598 enable_rx_on_pipe(_NRF24L01P_PIPE_P4);
emoninet2 0:795de307e97f 599 enable_rx_on_pipe(_NRF24L01P_PIPE_P5);
emoninet2 0:795de307e97f 600
emoninet2 0:795de307e97f 601 set_auto_retransmission_count(15);
emoninet2 0:795de307e97f 602 set_auto_retransmission_delay(15);
emoninet2 0:795de307e97f 603 set_DataRate(_NRF24L01P_RF_SETUP_RF_DR_250KBPS);
emoninet2 0:795de307e97f 604
emoninet2 0:795de307e97f 605 return 0;
emoninet2 0:795de307e97f 606 }
emoninet2 0:795de307e97f 607
emoninet2 0:795de307e97f 608 int nrf24l01p::stateMode(nRF24L01P_Mode_Type mode){
emoninet2 0:795de307e97f 609 switch(mode){
emoninet2 0:795de307e97f 610 case _NRF24L01P_MODE_POWER_DOWN: {
emoninet2 0:795de307e97f 611 power_down();
emoninet2 0:795de307e97f 612 ce_pin(0);
emoninet2 0:795de307e97f 613 _nrf24l01p_mode = _NRF24L01P_MODE_POWER_DOWN;
emoninet2 0:795de307e97f 614 break;
emoninet2 0:795de307e97f 615 }
emoninet2 0:795de307e97f 616 case _NRF24L01P_MODE_STANDBY: {
emoninet2 0:795de307e97f 617 if(_nrf24l01p_mode == _NRF24L01P_MODE_POWER_DOWN){
emoninet2 0:795de307e97f 618 power_up();
emoninet2 0:795de307e97f 619 _nrf24l01p_delay_us(_NRF24L01P_TIMING_Tpd2stby_us);
emoninet2 0:795de307e97f 620 }
emoninet2 0:795de307e97f 621 else{
emoninet2 0:795de307e97f 622 ce_pin(0);
emoninet2 0:795de307e97f 623 }
emoninet2 0:795de307e97f 624 _nrf24l01p_mode = _NRF24L01P_MODE_STANDBY;
emoninet2 0:795de307e97f 625 break;
emoninet2 0:795de307e97f 626 }
emoninet2 0:795de307e97f 627 case _NRF24L01P_MODE_RX: {
emoninet2 0:795de307e97f 628 rx_mode();
emoninet2 0:795de307e97f 629 ce_pin(1);
emoninet2 0:795de307e97f 630 _nrf24l01p_delay_us(_NRF24L01P_TIMING_Tstby2a_us);
emoninet2 0:795de307e97f 631 _nrf24l01p_mode = _NRF24L01P_MODE_RX;
emoninet2 0:795de307e97f 632 break;
emoninet2 0:795de307e97f 633 }
emoninet2 0:795de307e97f 634 case _NRF24L01P_MODE_TX: {
emoninet2 0:795de307e97f 635 tx_mode();
emoninet2 0:795de307e97f 636 ce_pin(1);
emoninet2 0:795de307e97f 637 _nrf24l01p_delay_us(_NRF24L01P_TIMING_Tstby2a_us);
emoninet2 0:795de307e97f 638 mode = _NRF24L01P_MODE_TX;
emoninet2 0:795de307e97f 639 break;
emoninet2 0:795de307e97f 640 }
emoninet2 0:795de307e97f 641 }
emoninet2 0:795de307e97f 642
emoninet2 0:795de307e97f 643 return 0;
emoninet2 0:795de307e97f 644 }
emoninet2 0:795de307e97f 645
emoninet2 0:795de307e97f 646
emoninet2 0:795de307e97f 647 bool nrf24l01p::readable(){
emoninet2 0:795de307e97f 648 bool HasData = 0;
emoninet2 0:795de307e97f 649 HasData = !get_fifo_flag_rx_empty();
emoninet2 0:795de307e97f 650 return HasData;
emoninet2 0:795de307e97f 651 }
emoninet2 0:795de307e97f 652 bool nrf24l01p::writable(){
emoninet2 0:795de307e97f 653 bool HasData = 0;
emoninet2 0:795de307e97f 654 HasData = !get_fifo_flag_tx_empty();
emoninet2 0:795de307e97f 655 return HasData;
emoninet2 0:795de307e97f 656 }
emoninet2 0:795de307e97f 657
emoninet2 0:795de307e97f 658
emoninet2 0:795de307e97f 659
emoninet2 0:795de307e97f 660
emoninet2 0:795de307e97f 661 int nrf24l01p::send(uint8_t *data, int datalen){
emoninet2 0:795de307e97f 662
emoninet2 0:795de307e97f 663 if ( datalen <= 0 ) return 0;
emoninet2 0:795de307e97f 664 if ( datalen > _NRF24L01P_TX_FIFO_SIZE ) datalen = _NRF24L01P_TX_FIFO_SIZE;
emoninet2 0:795de307e97f 665
emoninet2 0:795de307e97f 666 if(get_tx_fifo_full_flag()) return -1;
emoninet2 0:795de307e97f 667 //while(_nrf24l01p_get_tx_fifo_full_flag());
emoninet2 0:795de307e97f 668
emoninet2 0:795de307e97f 669 write_tx_payload(data,datalen);
emoninet2 0:795de307e97f 670
emoninet2 0:795de307e97f 671
emoninet2 0:795de307e97f 672 return 0;
emoninet2 0:795de307e97f 673 }
emoninet2 0:795de307e97f 674
emoninet2 0:795de307e97f 675 int nrf24l01p::send_to_address(uint64_t address, uint8_t *data, int datalen){
emoninet2 0:795de307e97f 676 //_nrf24l01p_disable_payload_with_ack();
emoninet2 0:795de307e97f 677 set_TX_pipe_address(address);
emoninet2 0:795de307e97f 678 return send(data,datalen);
emoninet2 0:795de307e97f 679
emoninet2 0:795de307e97f 680 }
emoninet2 0:795de307e97f 681 int nrf24l01p::send_to_address_ack(uint64_t address, uint8_t *data, int datalen){
emoninet2 0:795de307e97f 682 //_nrf24l01p_enable_payload_with_ack();
emoninet2 0:795de307e97f 683 set_TX_pipe_address(address);
emoninet2 0:795de307e97f 684 set_RX_pipe_address(_NRF24L01P_PIPE_P0, address);
emoninet2 0:795de307e97f 685 return send(data,datalen);
emoninet2 0:795de307e97f 686 }
emoninet2 0:795de307e97f 687
emoninet2 0:795de307e97f 688
emoninet2 0:795de307e97f 689
emoninet2 0:795de307e97f 690
emoninet2 0:795de307e97f 691
emoninet2 0:795de307e97f 692 bool nrf24l01p::readableOnPipe(_nrf24l01p_pipe_t pipe){
emoninet2 0:795de307e97f 693 bool flag = 0;
emoninet2 0:795de307e97f 694 if((pipe >=0) && (pipe <=5)){
emoninet2 0:795de307e97f 695 int status = get_status();
emoninet2 0:795de307e97f 696 if( (status&_NRF24L01P_STATUS_RX_DR) && ((status&_NRF24L01P_STATUS_RX_P_NO)>>1)==pipe){
emoninet2 0:795de307e97f 697 flag = 1;
emoninet2 0:795de307e97f 698 }
emoninet2 0:795de307e97f 699 else{
emoninet2 0:795de307e97f 700 flag = 0;
emoninet2 0:795de307e97f 701 }
emoninet2 0:795de307e97f 702 }
emoninet2 0:795de307e97f 703 return flag;
emoninet2 0:795de307e97f 704 }
emoninet2 0:795de307e97f 705
emoninet2 0:795de307e97f 706
emoninet2 0:795de307e97f 707 int nrf24l01p::read(_nrf24l01p_pipe_t pipe, uint8_t *data, int datalen){
emoninet2 0:795de307e97f 708
emoninet2 0:795de307e97f 709 int rxPayloadWidth;
emoninet2 0:795de307e97f 710
emoninet2 0:795de307e97f 711 if ( ( pipe < 0 ) || ( pipe > 5 ) ) {
emoninet2 0:795de307e97f 712 return -1;
emoninet2 0:795de307e97f 713 }
emoninet2 0:795de307e97f 714
emoninet2 0:795de307e97f 715 if (readableOnPipe(pipe) ) {
emoninet2 0:795de307e97f 716 asm("nop");
emoninet2 0:795de307e97f 717 rxPayloadWidth = _NRF24L01P_TX_FIFO_SIZE;
emoninet2 0:795de307e97f 718
emoninet2 0:795de307e97f 719 if ( ( rxPayloadWidth < 0 ) || ( rxPayloadWidth > _NRF24L01P_RX_FIFO_SIZE ) ) {
emoninet2 0:795de307e97f 720 flush_rx();
emoninet2 0:795de307e97f 721 }
emoninet2 0:795de307e97f 722 else{
emoninet2 0:795de307e97f 723 read_rx_payload(data,rxPayloadWidth);
emoninet2 0:795de307e97f 724
emoninet2 0:795de307e97f 725 if(get_fifo_flag_rx_empty()) {
emoninet2 0:795de307e97f 726 clear_data_ready_flag();
emoninet2 0:795de307e97f 727 }
emoninet2 0:795de307e97f 728 }
emoninet2 0:795de307e97f 729
emoninet2 0:795de307e97f 730 return rxPayloadWidth;
emoninet2 0:795de307e97f 731 }
emoninet2 0:795de307e97f 732
emoninet2 0:795de307e97f 733 //if RX FIFO is full even after reading data, then flush RX FIFO
emoninet2 0:795de307e97f 734 if(get_fifo_flag_rx_full()){
emoninet2 0:795de307e97f 735 clear_data_ready_flag();
emoninet2 0:795de307e97f 736 flush_rx();
emoninet2 0:795de307e97f 737 }
emoninet2 0:795de307e97f 738 return 0;
emoninet2 0:795de307e97f 739 }
emoninet2 0:795de307e97f 740
emoninet2 0:795de307e97f 741 int nrf24l01p::read_dyn_pld(_nrf24l01p_pipe_t pipe, uint8_t *data){
emoninet2 0:795de307e97f 742
emoninet2 0:795de307e97f 743 int rxPayloadWidth;
emoninet2 0:795de307e97f 744
emoninet2 0:795de307e97f 745 if ( ( pipe < 0 ) || ( pipe > 5 ) ) {
emoninet2 0:795de307e97f 746 return -1;
emoninet2 0:795de307e97f 747 }
emoninet2 0:795de307e97f 748
emoninet2 0:795de307e97f 749 if (readableOnPipe(pipe) ) {
emoninet2 0:795de307e97f 750 asm("nop");
emoninet2 0:795de307e97f 751 rxPayloadWidth = read_rx_payload_width();
emoninet2 0:795de307e97f 752
emoninet2 0:795de307e97f 753 if ( ( rxPayloadWidth < 0 ) || ( rxPayloadWidth > _NRF24L01P_RX_FIFO_SIZE ) ) {
emoninet2 0:795de307e97f 754 flush_rx();
emoninet2 0:795de307e97f 755 }
emoninet2 0:795de307e97f 756 else{
emoninet2 0:795de307e97f 757 read_rx_payload(data,rxPayloadWidth);
emoninet2 0:795de307e97f 758
emoninet2 0:795de307e97f 759 if(get_fifo_flag_rx_empty()) {
emoninet2 0:795de307e97f 760 clear_data_ready_flag();
emoninet2 0:795de307e97f 761 }
emoninet2 0:795de307e97f 762 }
emoninet2 0:795de307e97f 763
emoninet2 0:795de307e97f 764 return rxPayloadWidth;
emoninet2 0:795de307e97f 765 }
emoninet2 0:795de307e97f 766 else {//if pipe not readable
emoninet2 0:795de307e97f 767 return 0;
emoninet2 0:795de307e97f 768 }
emoninet2 0:795de307e97f 769 return 0;
emoninet2 0:795de307e97f 770 }
emoninet2 0:795de307e97f 771
emoninet2 0:795de307e97f 772
emoninet2 0:795de307e97f 773
emoninet2 0:795de307e97f 774
emoninet2 0:795de307e97f 775 void nrf24l01p::PTX(){
emoninet2 0:795de307e97f 776
emoninet2 0:795de307e97f 777
emoninet2 0:795de307e97f 778 //backup original machine state
emoninet2 0:795de307e97f 779 nRF24L01P_Mode_Type originalMode = _nrf24l01p_mode;
emoninet2 0:795de307e97f 780
emoninet2 0:795de307e97f 781 //switching to STANDBY to avoid data reception during state check (ATOMIC state check)
emoninet2 0:795de307e97f 782 stateMode(_NRF24L01P_MODE_STANDBY);
emoninet2 0:795de307e97f 783
emoninet2 0:795de307e97f 784 //has data to write and no data to read. Do not enter PTX with data in PRX payload.
emoninet2 0:795de307e97f 785 //This is because, if the PRX is full, then sending a data and will forever wait for ACK
emoninet2 0:795de307e97f 786 //and it will never get the ACK because the PRX fifo is full
emoninet2 0:795de307e97f 787 if(writable() && !readable()){
emoninet2 0:795de307e97f 788
emoninet2 0:795de307e97f 789 //blocked until data sent
emoninet2 0:795de307e97f 790 while(1){
emoninet2 0:795de307e97f 791 //clear data sent flag before the next packet is sent
emoninet2 0:795de307e97f 792 clear_data_sent_flag();
emoninet2 0:795de307e97f 793
emoninet2 0:795de307e97f 794 //strobe CE for single transmission
emoninet2 0:795de307e97f 795 stateMode(_NRF24L01P_MODE_TX);
emoninet2 0:795de307e97f 796 _nrf24l01p_delay_us(_NRF24L01P_TIMING_Tstby2a_us);
emoninet2 0:795de307e97f 797 stateMode(_NRF24L01P_MODE_STANDBY);
emoninet2 0:795de307e97f 798
emoninet2 0:795de307e97f 799 //break when DS flag is set and a single payload is sent or all data on RX FIFO sent
emoninet2 0:795de307e97f 800 if(get_data_sent_flag() || !writable() ) break;
emoninet2 0:795de307e97f 801
emoninet2 0:795de307e97f 802 //if max retry flag is set
emoninet2 0:795de307e97f 803 if(get_max_retry_flag() ) {
emoninet2 0:795de307e97f 804 break;
emoninet2 0:795de307e97f 805 }
emoninet2 0:795de307e97f 806
emoninet2 0:795de307e97f 807
emoninet2 0:795de307e97f 808 }
emoninet2 0:795de307e97f 809 //clear data sent flag
emoninet2 0:795de307e97f 810 clear_data_sent_flag();
emoninet2 0:795de307e97f 811
emoninet2 0:795de307e97f 812 //if got ack packet, just flush it
emoninet2 0:795de307e97f 813 if(get_data_ready_flag()){
emoninet2 0:795de307e97f 814 //do what needs to be done with the ACK payload here
emoninet2 0:795de307e97f 815 flush_rx();
emoninet2 0:795de307e97f 816 }
emoninet2 0:795de307e97f 817 }
emoninet2 0:795de307e97f 818 //restore original machine state
emoninet2 0:795de307e97f 819 stateMode(originalMode);
emoninet2 0:795de307e97f 820
emoninet2 0:795de307e97f 821 }
emoninet2 0:795de307e97f 822
emoninet2 0:795de307e97f 823
emoninet2 0:795de307e97f 824 void nrf24l01p::PRX(){
emoninet2 0:795de307e97f 825
emoninet2 0:795de307e97f 826 //backup original machine state
emoninet2 0:795de307e97f 827 nRF24L01P_Mode_Type originalMode = _nrf24l01p_mode;
emoninet2 0:795de307e97f 828
emoninet2 0:795de307e97f 829 //switching to STANDBY to avoid data reception during state check (ATOMIC state check)
emoninet2 0:795de307e97f 830 stateMode(_NRF24L01P_MODE_STANDBY);
emoninet2 0:795de307e97f 831
emoninet2 0:795de307e97f 832 //if readable (if RX payload data in RX FIFO)
emoninet2 0:795de307e97f 833 if(readable()){
emoninet2 0:795de307e97f 834
emoninet2 0:795de307e97f 835 while(1){
emoninet2 0:795de307e97f 836
emoninet2 0:795de307e97f 837 char rxData[32];
emoninet2 0:795de307e97f 838 _nrf24l01p_pipe_t pipe = get_rx_payload_pipe();
emoninet2 0:795de307e97f 839 int width = read_dyn_pld(pipe, (uint8_t*)rxData);
emoninet2 0:795de307e97f 840 rxData[width] = '\0';
emoninet2 0:795de307e97f 841
emoninet2 0:795de307e97f 842 //what needs to be done with the data read
emoninet2 0:795de307e97f 843 printf("MESG: %s\n", rxData);
emoninet2 0:795de307e97f 844
emoninet2 0:795de307e97f 845 if(!readable()) break;
emoninet2 0:795de307e97f 846
emoninet2 0:795de307e97f 847
emoninet2 0:795de307e97f 848 }
emoninet2 0:795de307e97f 849 }
emoninet2 0:795de307e97f 850 //restore original machine state
emoninet2 0:795de307e97f 851 stateMode(originalMode);
emoninet2 0:795de307e97f 852
emoninet2 0:795de307e97f 853
emoninet2 0:795de307e97f 854 }
emoninet2 0:795de307e97f 855 // default destructor
emoninet2 0:795de307e97f 856 nrf24l01p::~nrf24l01p()
emoninet2 0:795de307e97f 857 {
emoninet2 0:795de307e97f 858 } //~nrf24l01p
emoninet2 0:795de307e97f 859