Emilio Monti / mbed-KL25Z

mbed libraries for KL25Z

Dependents:   FRDM_RGBLED

KL25Z/core_cm0plus.h@9:663789d7729f, 2013-02-18 (annotated)

Committer:
emilmont
Date:
Mon Feb 18 09:41:56 2013 +0000
Revision:
9:663789d7729f
Parent:
2:e9a661555b58 
Update mbed-KL25Z to latest build

Who changed what in which revision?

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emilmont 2:e9a661555b58 1 /**************************************************************************//**
emilmont 2:e9a661555b58 2 * @file core_cm0plus.h
emilmont 2:e9a661555b58 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
emilmont 9:663789d7729f 4 * @version V3.02
emilmont 9:663789d7729f 5 * @date 05. November 2012
emilmont 2:e9a661555b58 6 *
emilmont 2:e9a661555b58 7 * @note
emilmont 2:e9a661555b58 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 2:e9a661555b58 9 *
emilmont 2:e9a661555b58 10 * @par
emilmont 2:e9a661555b58 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 2:e9a661555b58 12 * processor based microcontrollers. This file can be freely distributed
emilmont 2:e9a661555b58 13 * within development tools that are supporting such ARM based processors.
emilmont 2:e9a661555b58 14 *
emilmont 2:e9a661555b58 15 * @par
emilmont 2:e9a661555b58 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 2:e9a661555b58 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 2:e9a661555b58 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 2:e9a661555b58 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 2:e9a661555b58 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 2:e9a661555b58 21 *
emilmont 2:e9a661555b58 22 ******************************************************************************/
emilmont 2:e9a661555b58 23 #if defined ( __ICCARM__ )
emilmont 2:e9a661555b58 24 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 2:e9a661555b58 25 #endif
emilmont 2:e9a661555b58 26
emilmont 2:e9a661555b58 27 #ifdef __cplusplus
emilmont 2:e9a661555b58 28 extern "C" {
emilmont 2:e9a661555b58 29 #endif
emilmont 2:e9a661555b58 30
emilmont 2:e9a661555b58 31 #ifndef __CORE_CM0PLUS_H_GENERIC
emilmont 2:e9a661555b58 32 #define __CORE_CM0PLUS_H_GENERIC
emilmont 2:e9a661555b58 33
emilmont 2:e9a661555b58 34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 2:e9a661555b58 35 CMSIS violates the following MISRA-C:2004 rules:
emilmont 2:e9a661555b58 36
emilmont 2:e9a661555b58 37 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 2:e9a661555b58 38 Function definitions in header files are used to allow 'inlining'.
emilmont 2:e9a661555b58 39
emilmont 2:e9a661555b58 40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 2:e9a661555b58 41 Unions are used for effective representation of core registers.
emilmont 2:e9a661555b58 42
emilmont 2:e9a661555b58 43 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 2:e9a661555b58 44 Function-like macros are used to allow more efficient code.
emilmont 2:e9a661555b58 45 */
emilmont 2:e9a661555b58 46
emilmont 2:e9a661555b58 47
emilmont 2:e9a661555b58 48 /*******************************************************************************
emilmont 2:e9a661555b58 49 * CMSIS definitions
emilmont 2:e9a661555b58 50 ******************************************************************************/
emilmont 2:e9a661555b58 51 /** \ingroup Cortex-M0+
emilmont 2:e9a661555b58 52 @{
emilmont 2:e9a661555b58 53 */
emilmont 2:e9a661555b58 54
emilmont 2:e9a661555b58 55 /* CMSIS CM0P definitions */
emilmont 2:e9a661555b58 56 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
emilmont 2:e9a661555b58 57 #define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
emilmont 2:e9a661555b58 58 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
emilmont 2:e9a661555b58 59 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
emilmont 2:e9a661555b58 60
emilmont 2:e9a661555b58 61 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
emilmont 2:e9a661555b58 62
emilmont 2:e9a661555b58 63
emilmont 2:e9a661555b58 64 #if defined ( __CC_ARM )
emilmont 2:e9a661555b58 65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 2:e9a661555b58 66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 2:e9a661555b58 67 #define __STATIC_INLINE static __inline
emilmont 2:e9a661555b58 68
emilmont 2:e9a661555b58 69 #elif defined ( __ICCARM__ )
emilmont 2:e9a661555b58 70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 2:e9a661555b58 71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 2:e9a661555b58 72 #define __STATIC_INLINE static inline
emilmont 2:e9a661555b58 73
emilmont 2:e9a661555b58 74 #elif defined ( __GNUC__ )
emilmont 2:e9a661555b58 75 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 2:e9a661555b58 76 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 2:e9a661555b58 77 #define __STATIC_INLINE static inline
emilmont 2:e9a661555b58 78
emilmont 2:e9a661555b58 79 #elif defined ( __TASKING__ )
emilmont 2:e9a661555b58 80 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 2:e9a661555b58 81 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 2:e9a661555b58 82 #define __STATIC_INLINE static inline
emilmont 2:e9a661555b58 83
emilmont 2:e9a661555b58 84 #endif
emilmont 2:e9a661555b58 85
emilmont 2:e9a661555b58 86 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
emilmont 2:e9a661555b58 87 */
emilmont 2:e9a661555b58 88 #define __FPU_USED 0
emilmont 2:e9a661555b58 89
emilmont 2:e9a661555b58 90 #if defined ( __CC_ARM )
emilmont 2:e9a661555b58 91 #if defined __TARGET_FPU_VFP
emilmont 2:e9a661555b58 92 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 2:e9a661555b58 93 #endif
emilmont 2:e9a661555b58 94
emilmont 2:e9a661555b58 95 #elif defined ( __ICCARM__ )
emilmont 2:e9a661555b58 96 #if defined __ARMVFP__
emilmont 2:e9a661555b58 97 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 2:e9a661555b58 98 #endif
emilmont 2:e9a661555b58 99
emilmont 2:e9a661555b58 100 #elif defined ( __GNUC__ )
emilmont 2:e9a661555b58 101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
emilmont 2:e9a661555b58 102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 2:e9a661555b58 103 #endif
emilmont 2:e9a661555b58 104
emilmont 2:e9a661555b58 105 #elif defined ( __TASKING__ )
emilmont 2:e9a661555b58 106 #if defined __FPU_VFP__
emilmont 2:e9a661555b58 107 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 2:e9a661555b58 108 #endif
emilmont 2:e9a661555b58 109 #endif
emilmont 2:e9a661555b58 110
emilmont 2:e9a661555b58 111 #include <stdint.h> /* standard types definitions */
emilmont 2:e9a661555b58 112 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 2:e9a661555b58 113 #include <core_cmFunc.h> /* Core Function Access */
emilmont 2:e9a661555b58 114
emilmont 2:e9a661555b58 115 #endif /* __CORE_CM0PLUS_H_GENERIC */
emilmont 2:e9a661555b58 116
emilmont 2:e9a661555b58 117 #ifndef __CMSIS_GENERIC
emilmont 2:e9a661555b58 118
emilmont 2:e9a661555b58 119 #ifndef __CORE_CM0PLUS_H_DEPENDANT
emilmont 2:e9a661555b58 120 #define __CORE_CM0PLUS_H_DEPENDANT
emilmont 2:e9a661555b58 121
emilmont 2:e9a661555b58 122 /* check device defines and use defaults */
emilmont 2:e9a661555b58 123 #if defined __CHECK_DEVICE_DEFINES
emilmont 2:e9a661555b58 124 #ifndef __CM0PLUS_REV
emilmont 2:e9a661555b58 125 #define __CM0PLUS_REV 0x0000
emilmont 2:e9a661555b58 126 #warning "__CM0PLUS_REV not defined in device header file; using default!"
emilmont 2:e9a661555b58 127 #endif
emilmont 2:e9a661555b58 128
emilmont 2:e9a661555b58 129 #ifndef __MPU_PRESENT
emilmont 2:e9a661555b58 130 #define __MPU_PRESENT 0
emilmont 2:e9a661555b58 131 #warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont 2:e9a661555b58 132 #endif
emilmont 2:e9a661555b58 133
emilmont 2:e9a661555b58 134 #ifndef __VTOR_PRESENT
emilmont 2:e9a661555b58 135 #define __VTOR_PRESENT 0
emilmont 2:e9a661555b58 136 #warning "__VTOR_PRESENT not defined in device header file; using default!"
emilmont 2:e9a661555b58 137 #endif
emilmont 2:e9a661555b58 138
emilmont 2:e9a661555b58 139 #ifndef __NVIC_PRIO_BITS
emilmont 2:e9a661555b58 140 #define __NVIC_PRIO_BITS 2
emilmont 2:e9a661555b58 141 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 2:e9a661555b58 142 #endif
emilmont 2:e9a661555b58 143
emilmont 2:e9a661555b58 144 #ifndef __Vendor_SysTickConfig
emilmont 2:e9a661555b58 145 #define __Vendor_SysTickConfig 0
emilmont 2:e9a661555b58 146 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 2:e9a661555b58 147 #endif
emilmont 2:e9a661555b58 148 #endif
emilmont 2:e9a661555b58 149
emilmont 2:e9a661555b58 150 /* IO definitions (access restrictions to peripheral registers) */
emilmont 2:e9a661555b58 151 /**
emilmont 2:e9a661555b58 152 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 2:e9a661555b58 153
emilmont 2:e9a661555b58 154 <strong>IO Type Qualifiers</strong> are used
emilmont 2:e9a661555b58 155 \li to specify the access to peripheral variables.
emilmont 2:e9a661555b58 156 \li for automatic generation of peripheral register debug information.
emilmont 2:e9a661555b58 157 */
emilmont 2:e9a661555b58 158 #ifdef __cplusplus
emilmont 2:e9a661555b58 159 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 2:e9a661555b58 160 #else
emilmont 2:e9a661555b58 161 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 2:e9a661555b58 162 #endif
emilmont 2:e9a661555b58 163 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 2:e9a661555b58 164 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 2:e9a661555b58 165
emilmont 2:e9a661555b58 166 /*@} end of group Cortex-M0+ */
emilmont 2:e9a661555b58 167
emilmont 2:e9a661555b58 168
emilmont 2:e9a661555b58 169
emilmont 2:e9a661555b58 170 /*******************************************************************************
emilmont 2:e9a661555b58 171 * Register Abstraction
emilmont 2:e9a661555b58 172 Core Register contain:
emilmont 2:e9a661555b58 173 - Core Register
emilmont 2:e9a661555b58 174 - Core NVIC Register
emilmont 2:e9a661555b58 175 - Core SCB Register
emilmont 2:e9a661555b58 176 - Core SysTick Register
emilmont 2:e9a661555b58 177 - Core MPU Register
emilmont 2:e9a661555b58 178 ******************************************************************************/
emilmont 2:e9a661555b58 179 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 2:e9a661555b58 180 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 2:e9a661555b58 181 */
emilmont 2:e9a661555b58 182
emilmont 2:e9a661555b58 183 /** \ingroup CMSIS_core_register
emilmont 2:e9a661555b58 184 \defgroup CMSIS_CORE Status and Control Registers
emilmont 2:e9a661555b58 185 \brief Core Register type definitions.
emilmont 2:e9a661555b58 186 @{
emilmont 2:e9a661555b58 187 */
emilmont 2:e9a661555b58 188
emilmont 2:e9a661555b58 189 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 2:e9a661555b58 190 */
emilmont 2:e9a661555b58 191 typedef union
emilmont 2:e9a661555b58 192 {
emilmont 2:e9a661555b58 193 struct
emilmont 2:e9a661555b58 194 {
emilmont 2:e9a661555b58 195 #if (__CORTEX_M != 0x04)
emilmont 2:e9a661555b58 196 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
emilmont 2:e9a661555b58 197 #else
emilmont 2:e9a661555b58 198 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
emilmont 2:e9a661555b58 199 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 2:e9a661555b58 200 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
emilmont 2:e9a661555b58 201 #endif
emilmont 2:e9a661555b58 202 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 2:e9a661555b58 203 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 2:e9a661555b58 204 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 2:e9a661555b58 205 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 2:e9a661555b58 206 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 2:e9a661555b58 207 } b; /*!< Structure used for bit access */
emilmont 2:e9a661555b58 208 uint32_t w; /*!< Type used for word access */
emilmont 2:e9a661555b58 209 } APSR_Type;
emilmont 2:e9a661555b58 210
emilmont 2:e9a661555b58 211
emilmont 2:e9a661555b58 212 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 2:e9a661555b58 213 */
emilmont 2:e9a661555b58 214 typedef union
emilmont 2:e9a661555b58 215 {
emilmont 2:e9a661555b58 216 struct
emilmont 2:e9a661555b58 217 {
emilmont 2:e9a661555b58 218 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 2:e9a661555b58 219 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 2:e9a661555b58 220 } b; /*!< Structure used for bit access */
emilmont 2:e9a661555b58 221 uint32_t w; /*!< Type used for word access */
emilmont 2:e9a661555b58 222 } IPSR_Type;
emilmont 2:e9a661555b58 223
emilmont 2:e9a661555b58 224
emilmont 2:e9a661555b58 225 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 2:e9a661555b58 226 */
emilmont 2:e9a661555b58 227 typedef union
emilmont 2:e9a661555b58 228 {
emilmont 2:e9a661555b58 229 struct
emilmont 2:e9a661555b58 230 {
emilmont 2:e9a661555b58 231 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 2:e9a661555b58 232 #if (__CORTEX_M != 0x04)
emilmont 2:e9a661555b58 233 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 2:e9a661555b58 234 #else
emilmont 2:e9a661555b58 235 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
emilmont 2:e9a661555b58 236 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 2:e9a661555b58 237 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
emilmont 2:e9a661555b58 238 #endif
emilmont 2:e9a661555b58 239 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emilmont 2:e9a661555b58 240 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emilmont 2:e9a661555b58 241 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 2:e9a661555b58 242 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 2:e9a661555b58 243 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 2:e9a661555b58 244 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 2:e9a661555b58 245 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 2:e9a661555b58 246 } b; /*!< Structure used for bit access */
emilmont 2:e9a661555b58 247 uint32_t w; /*!< Type used for word access */
emilmont 2:e9a661555b58 248 } xPSR_Type;
emilmont 2:e9a661555b58 249
emilmont 2:e9a661555b58 250
emilmont 2:e9a661555b58 251 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 2:e9a661555b58 252 */
emilmont 2:e9a661555b58 253 typedef union
emilmont 2:e9a661555b58 254 {
emilmont 2:e9a661555b58 255 struct
emilmont 2:e9a661555b58 256 {
emilmont 2:e9a661555b58 257 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 2:e9a661555b58 258 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
emilmont 2:e9a661555b58 259 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
emilmont 2:e9a661555b58 260 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
emilmont 2:e9a661555b58 261 } b; /*!< Structure used for bit access */
emilmont 2:e9a661555b58 262 uint32_t w; /*!< Type used for word access */
emilmont 2:e9a661555b58 263 } CONTROL_Type;
emilmont 2:e9a661555b58 264
emilmont 2:e9a661555b58 265 /*@} end of group CMSIS_CORE */
emilmont 2:e9a661555b58 266
emilmont 2:e9a661555b58 267
emilmont 2:e9a661555b58 268 /** \ingroup CMSIS_core_register
emilmont 2:e9a661555b58 269 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 2:e9a661555b58 270 \brief Type definitions for the NVIC Registers
emilmont 2:e9a661555b58 271 @{
emilmont 2:e9a661555b58 272 */
emilmont 2:e9a661555b58 273
emilmont 2:e9a661555b58 274 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 2:e9a661555b58 275 */
emilmont 2:e9a661555b58 276 typedef struct
emilmont 2:e9a661555b58 277 {
emilmont 2:e9a661555b58 278 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 2:e9a661555b58 279 uint32_t RESERVED0[31];
emilmont 2:e9a661555b58 280 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 2:e9a661555b58 281 uint32_t RSERVED1[31];
emilmont 2:e9a661555b58 282 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 2:e9a661555b58 283 uint32_t RESERVED2[31];
emilmont 2:e9a661555b58 284 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 2:e9a661555b58 285 uint32_t RESERVED3[31];
emilmont 2:e9a661555b58 286 uint32_t RESERVED4[64];
emilmont 2:e9a661555b58 287 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
emilmont 2:e9a661555b58 288 } NVIC_Type;
emilmont 2:e9a661555b58 289
emilmont 2:e9a661555b58 290 /*@} end of group CMSIS_NVIC */
emilmont 2:e9a661555b58 291
emilmont 2:e9a661555b58 292
emilmont 2:e9a661555b58 293 /** \ingroup CMSIS_core_register
emilmont 2:e9a661555b58 294 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 2:e9a661555b58 295 \brief Type definitions for the System Control Block Registers
emilmont 2:e9a661555b58 296 @{
emilmont 2:e9a661555b58 297 */
emilmont 2:e9a661555b58 298
emilmont 2:e9a661555b58 299 /** \brief Structure type to access the System Control Block (SCB).
emilmont 2:e9a661555b58 300 */
emilmont 2:e9a661555b58 301 typedef struct
emilmont 2:e9a661555b58 302 {
emilmont 2:e9a661555b58 303 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 2:e9a661555b58 304 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 2:e9a661555b58 305 #if (__VTOR_PRESENT == 1)
emilmont 2:e9a661555b58 306 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
emilmont 2:e9a661555b58 307 #else
emilmont 2:e9a661555b58 308 uint32_t RESERVED0;
emilmont 2:e9a661555b58 309 #endif
emilmont 2:e9a661555b58 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 2:e9a661555b58 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 2:e9a661555b58 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 2:e9a661555b58 313 uint32_t RESERVED1;
emilmont 2:e9a661555b58 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emilmont 2:e9a661555b58 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 2:e9a661555b58 316 } SCB_Type;
emilmont 2:e9a661555b58 317
emilmont 2:e9a661555b58 318 /* SCB CPUID Register Definitions */
emilmont 2:e9a661555b58 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 2:e9a661555b58 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 2:e9a661555b58 321
emilmont 2:e9a661555b58 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 2:e9a661555b58 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 2:e9a661555b58 324
emilmont 2:e9a661555b58 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 2:e9a661555b58 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 2:e9a661555b58 327
emilmont 2:e9a661555b58 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 2:e9a661555b58 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 2:e9a661555b58 330
emilmont 2:e9a661555b58 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
emilmont 2:e9a661555b58 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
emilmont 2:e9a661555b58 333
emilmont 2:e9a661555b58 334 /* SCB Interrupt Control State Register Definitions */
emilmont 2:e9a661555b58 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 2:e9a661555b58 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 2:e9a661555b58 337
emilmont 2:e9a661555b58 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 2:e9a661555b58 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 2:e9a661555b58 340
emilmont 2:e9a661555b58 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 2:e9a661555b58 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 2:e9a661555b58 343
emilmont 2:e9a661555b58 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 2:e9a661555b58 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 2:e9a661555b58 346
emilmont 2:e9a661555b58 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 2:e9a661555b58 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 2:e9a661555b58 349
emilmont 2:e9a661555b58 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 2:e9a661555b58 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 2:e9a661555b58 352
emilmont 2:e9a661555b58 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 2:e9a661555b58 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 2:e9a661555b58 355
emilmont 2:e9a661555b58 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 2:e9a661555b58 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 2:e9a661555b58 358
emilmont 2:e9a661555b58 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
emilmont 2:e9a661555b58 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 2:e9a661555b58 361
emilmont 2:e9a661555b58 362 #if (__VTOR_PRESENT == 1)
emilmont 2:e9a661555b58 363 /* SCB Interrupt Control State Register Definitions */
emilmont 2:e9a661555b58 364 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
emilmont 2:e9a661555b58 365 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
emilmont 2:e9a661555b58 366 #endif
emilmont 2:e9a661555b58 367
emilmont 2:e9a661555b58 368 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 2:e9a661555b58 369 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 2:e9a661555b58 370 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 2:e9a661555b58 371
emilmont 2:e9a661555b58 372 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 2:e9a661555b58 373 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 2:e9a661555b58 374
emilmont 2:e9a661555b58 375 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 2:e9a661555b58 376 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 2:e9a661555b58 377
emilmont 2:e9a661555b58 378 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 2:e9a661555b58 379 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 2:e9a661555b58 380
emilmont 2:e9a661555b58 381 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 2:e9a661555b58 382 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 2:e9a661555b58 383
emilmont 2:e9a661555b58 384 /* SCB System Control Register Definitions */
emilmont 2:e9a661555b58 385 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 2:e9a661555b58 386 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 2:e9a661555b58 387
emilmont 2:e9a661555b58 388 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 2:e9a661555b58 389 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 2:e9a661555b58 390
emilmont 2:e9a661555b58 391 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 2:e9a661555b58 392 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 2:e9a661555b58 393
emilmont 2:e9a661555b58 394 /* SCB Configuration Control Register Definitions */
emilmont 2:e9a661555b58 395 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 2:e9a661555b58 396 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 2:e9a661555b58 397
emilmont 2:e9a661555b58 398 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 2:e9a661555b58 399 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 2:e9a661555b58 400
emilmont 2:e9a661555b58 401 /* SCB System Handler Control and State Register Definitions */
emilmont 2:e9a661555b58 402 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 2:e9a661555b58 403 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 2:e9a661555b58 404
emilmont 2:e9a661555b58 405 /*@} end of group CMSIS_SCB */
emilmont 2:e9a661555b58 406
emilmont 2:e9a661555b58 407
emilmont 2:e9a661555b58 408 /** \ingroup CMSIS_core_register
emilmont 2:e9a661555b58 409 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 2:e9a661555b58 410 \brief Type definitions for the System Timer Registers.
emilmont 2:e9a661555b58 411 @{
emilmont 2:e9a661555b58 412 */
emilmont 2:e9a661555b58 413
emilmont 2:e9a661555b58 414 /** \brief Structure type to access the System Timer (SysTick).
emilmont 2:e9a661555b58 415 */
emilmont 2:e9a661555b58 416 typedef struct
emilmont 2:e9a661555b58 417 {
emilmont 2:e9a661555b58 418 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 2:e9a661555b58 419 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 2:e9a661555b58 420 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 2:e9a661555b58 421 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 2:e9a661555b58 422 } SysTick_Type;
emilmont 2:e9a661555b58 423
emilmont 2:e9a661555b58 424 /* SysTick Control / Status Register Definitions */
emilmont 2:e9a661555b58 425 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 2:e9a661555b58 426 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 2:e9a661555b58 427
emilmont 2:e9a661555b58 428 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 2:e9a661555b58 429 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 2:e9a661555b58 430
emilmont 2:e9a661555b58 431 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 2:e9a661555b58 432 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 2:e9a661555b58 433
emilmont 2:e9a661555b58 434 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
emilmont 2:e9a661555b58 435 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
emilmont 2:e9a661555b58 436
emilmont 2:e9a661555b58 437 /* SysTick Reload Register Definitions */
emilmont 2:e9a661555b58 438 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
emilmont 2:e9a661555b58 439 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
emilmont 2:e9a661555b58 440
emilmont 2:e9a661555b58 441 /* SysTick Current Register Definitions */
emilmont 2:e9a661555b58 442 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
emilmont 2:e9a661555b58 443 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
emilmont 2:e9a661555b58 444
emilmont 2:e9a661555b58 445 /* SysTick Calibration Register Definitions */
emilmont 2:e9a661555b58 446 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 2:e9a661555b58 447 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 2:e9a661555b58 448
emilmont 2:e9a661555b58 449 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 2:e9a661555b58 450 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 2:e9a661555b58 451
emilmont 2:e9a661555b58 452 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
emilmont 2:e9a661555b58 453 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
emilmont 2:e9a661555b58 454
emilmont 2:e9a661555b58 455 /*@} end of group CMSIS_SysTick */
emilmont 2:e9a661555b58 456
emilmont 2:e9a661555b58 457 #if (__MPU_PRESENT == 1)
emilmont 2:e9a661555b58 458 /** \ingroup CMSIS_core_register
emilmont 2:e9a661555b58 459 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont 2:e9a661555b58 460 \brief Type definitions for the Memory Protection Unit (MPU)
emilmont 2:e9a661555b58 461 @{
emilmont 2:e9a661555b58 462 */
emilmont 2:e9a661555b58 463
emilmont 2:e9a661555b58 464 /** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont 2:e9a661555b58 465 */
emilmont 2:e9a661555b58 466 typedef struct
emilmont 2:e9a661555b58 467 {
emilmont 2:e9a661555b58 468 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
emilmont 2:e9a661555b58 469 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
emilmont 2:e9a661555b58 470 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
emilmont 2:e9a661555b58 471 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
emilmont 2:e9a661555b58 472 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
emilmont 2:e9a661555b58 473 } MPU_Type;
emilmont 2:e9a661555b58 474
emilmont 2:e9a661555b58 475 /* MPU Type Register */
emilmont 2:e9a661555b58 476 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
emilmont 2:e9a661555b58 477 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
emilmont 2:e9a661555b58 478
emilmont 2:e9a661555b58 479 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
emilmont 2:e9a661555b58 480 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
emilmont 2:e9a661555b58 481
emilmont 2:e9a661555b58 482 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
emilmont 2:e9a661555b58 483 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
emilmont 2:e9a661555b58 484
emilmont 2:e9a661555b58 485 /* MPU Control Register */
emilmont 2:e9a661555b58 486 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
emilmont 2:e9a661555b58 487 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
emilmont 2:e9a661555b58 488
emilmont 2:e9a661555b58 489 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
emilmont 2:e9a661555b58 490 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
emilmont 2:e9a661555b58 491
emilmont 2:e9a661555b58 492 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
emilmont 2:e9a661555b58 493 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
emilmont 2:e9a661555b58 494
emilmont 2:e9a661555b58 495 /* MPU Region Number Register */
emilmont 2:e9a661555b58 496 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
emilmont 2:e9a661555b58 497 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
emilmont 2:e9a661555b58 498
emilmont 2:e9a661555b58 499 /* MPU Region Base Address Register */
emilmont 2:e9a661555b58 500 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
emilmont 2:e9a661555b58 501 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
emilmont 2:e9a661555b58 502
emilmont 2:e9a661555b58 503 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
emilmont 2:e9a661555b58 504 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
emilmont 2:e9a661555b58 505
emilmont 2:e9a661555b58 506 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
emilmont 2:e9a661555b58 507 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
emilmont 2:e9a661555b58 508
emilmont 2:e9a661555b58 509 /* MPU Region Attribute and Size Register */
emilmont 2:e9a661555b58 510 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
emilmont 2:e9a661555b58 511 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
emilmont 2:e9a661555b58 512
emilmont 2:e9a661555b58 513 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
emilmont 2:e9a661555b58 514 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
emilmont 2:e9a661555b58 515
emilmont 2:e9a661555b58 516 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
emilmont 2:e9a661555b58 517 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
emilmont 2:e9a661555b58 518
emilmont 2:e9a661555b58 519 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
emilmont 2:e9a661555b58 520 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
emilmont 2:e9a661555b58 521
emilmont 2:e9a661555b58 522 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
emilmont 2:e9a661555b58 523 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
emilmont 2:e9a661555b58 524
emilmont 2:e9a661555b58 525 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
emilmont 2:e9a661555b58 526 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
emilmont 2:e9a661555b58 527
emilmont 2:e9a661555b58 528 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
emilmont 2:e9a661555b58 529 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
emilmont 2:e9a661555b58 530
emilmont 2:e9a661555b58 531 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
emilmont 2:e9a661555b58 532 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
emilmont 2:e9a661555b58 533
emilmont 2:e9a661555b58 534 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
emilmont 2:e9a661555b58 535 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
emilmont 2:e9a661555b58 536
emilmont 2:e9a661555b58 537 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
emilmont 2:e9a661555b58 538 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
emilmont 2:e9a661555b58 539
emilmont 2:e9a661555b58 540 /*@} end of group CMSIS_MPU */
emilmont 2:e9a661555b58 541 #endif
emilmont 2:e9a661555b58 542
emilmont 2:e9a661555b58 543
emilmont 2:e9a661555b58 544 /** \ingroup CMSIS_core_register
emilmont 2:e9a661555b58 545 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 2:e9a661555b58 546 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
emilmont 2:e9a661555b58 547 are only accessible over DAP and not via processor. Therefore
emilmont 2:e9a661555b58 548 they are not covered by the Cortex-M0 header file.
emilmont 2:e9a661555b58 549 @{
emilmont 2:e9a661555b58 550 */
emilmont 2:e9a661555b58 551 /*@} end of group CMSIS_CoreDebug */
emilmont 2:e9a661555b58 552
emilmont 2:e9a661555b58 553
emilmont 2:e9a661555b58 554 /** \ingroup CMSIS_core_register
emilmont 2:e9a661555b58 555 \defgroup CMSIS_core_base Core Definitions
emilmont 2:e9a661555b58 556 \brief Definitions for base addresses, unions, and structures.
emilmont 2:e9a661555b58 557 @{
emilmont 2:e9a661555b58 558 */
emilmont 2:e9a661555b58 559
emilmont 2:e9a661555b58 560 /* Memory mapping of Cortex-M0+ Hardware */
emilmont 2:e9a661555b58 561 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 2:e9a661555b58 562 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 2:e9a661555b58 563 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 2:e9a661555b58 564 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 2:e9a661555b58 565
emilmont 2:e9a661555b58 566 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 2:e9a661555b58 567 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 2:e9a661555b58 568 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 2:e9a661555b58 569
emilmont 2:e9a661555b58 570 #if (__MPU_PRESENT == 1)
emilmont 2:e9a661555b58 571 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
emilmont 2:e9a661555b58 572 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
emilmont 2:e9a661555b58 573 #endif
emilmont 2:e9a661555b58 574
emilmont 2:e9a661555b58 575 /*@} */
emilmont 2:e9a661555b58 576
emilmont 2:e9a661555b58 577
emilmont 2:e9a661555b58 578
emilmont 2:e9a661555b58 579 /*******************************************************************************
emilmont 2:e9a661555b58 580 * Hardware Abstraction Layer
emilmont 2:e9a661555b58 581 Core Function Interface contains:
emilmont 2:e9a661555b58 582 - Core NVIC Functions
emilmont 2:e9a661555b58 583 - Core SysTick Functions
emilmont 2:e9a661555b58 584 - Core Register Access Functions
emilmont 2:e9a661555b58 585 ******************************************************************************/
emilmont 2:e9a661555b58 586 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 2:e9a661555b58 587 */
emilmont 2:e9a661555b58 588
emilmont 2:e9a661555b58 589
emilmont 2:e9a661555b58 590
emilmont 2:e9a661555b58 591 /* ########################## NVIC functions #################################### */
emilmont 2:e9a661555b58 592 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 2:e9a661555b58 593 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 2:e9a661555b58 594 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 2:e9a661555b58 595 @{
emilmont 2:e9a661555b58 596 */
emilmont 2:e9a661555b58 597
emilmont 2:e9a661555b58 598 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emilmont 2:e9a661555b58 599 /* The following MACROS handle generation of the register offset and byte masks */
emilmont 2:e9a661555b58 600 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
emilmont 2:e9a661555b58 601 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
emilmont 2:e9a661555b58 602 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
emilmont 2:e9a661555b58 603
emilmont 2:e9a661555b58 604
emilmont 2:e9a661555b58 605 /** \brief Enable External Interrupt
emilmont 2:e9a661555b58 606
emilmont 2:e9a661555b58 607 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 2:e9a661555b58 608
emilmont 2:e9a661555b58 609 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 2:e9a661555b58 610 */
emilmont 2:e9a661555b58 611 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 2:e9a661555b58 612 {
emilmont 2:e9a661555b58 613 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 2:e9a661555b58 614 }
emilmont 2:e9a661555b58 615
emilmont 2:e9a661555b58 616
emilmont 2:e9a661555b58 617 /** \brief Disable External Interrupt
emilmont 2:e9a661555b58 618
emilmont 2:e9a661555b58 619 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 2:e9a661555b58 620
emilmont 2:e9a661555b58 621 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 2:e9a661555b58 622 */
emilmont 2:e9a661555b58 623 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 2:e9a661555b58 624 {
emilmont 2:e9a661555b58 625 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 2:e9a661555b58 626 }
emilmont 2:e9a661555b58 627
emilmont 2:e9a661555b58 628
emilmont 2:e9a661555b58 629 /** \brief Get Pending Interrupt
emilmont 2:e9a661555b58 630
emilmont 2:e9a661555b58 631 The function reads the pending register in the NVIC and returns the pending bit
emilmont 2:e9a661555b58 632 for the specified interrupt.
emilmont 2:e9a661555b58 633
emilmont 2:e9a661555b58 634 \param [in] IRQn Interrupt number.
emilmont 2:e9a661555b58 635
emilmont 2:e9a661555b58 636 \return 0 Interrupt status is not pending.
emilmont 2:e9a661555b58 637 \return 1 Interrupt status is pending.
emilmont 2:e9a661555b58 638 */
emilmont 2:e9a661555b58 639 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 2:e9a661555b58 640 {
emilmont 2:e9a661555b58 641 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
emilmont 2:e9a661555b58 642 }
emilmont 2:e9a661555b58 643
emilmont 2:e9a661555b58 644
emilmont 2:e9a661555b58 645 /** \brief Set Pending Interrupt
emilmont 2:e9a661555b58 646
emilmont 2:e9a661555b58 647 The function sets the pending bit of an external interrupt.
emilmont 2:e9a661555b58 648
emilmont 2:e9a661555b58 649 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 2:e9a661555b58 650 */
emilmont 2:e9a661555b58 651 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 2:e9a661555b58 652 {
emilmont 2:e9a661555b58 653 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 2:e9a661555b58 654 }
emilmont 2:e9a661555b58 655
emilmont 2:e9a661555b58 656
emilmont 2:e9a661555b58 657 /** \brief Clear Pending Interrupt
emilmont 2:e9a661555b58 658
emilmont 2:e9a661555b58 659 The function clears the pending bit of an external interrupt.
emilmont 2:e9a661555b58 660
emilmont 2:e9a661555b58 661 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 2:e9a661555b58 662 */
emilmont 2:e9a661555b58 663 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 2:e9a661555b58 664 {
emilmont 2:e9a661555b58 665 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont 2:e9a661555b58 666 }
emilmont 2:e9a661555b58 667
emilmont 2:e9a661555b58 668
emilmont 2:e9a661555b58 669 /** \brief Set Interrupt Priority
emilmont 2:e9a661555b58 670
emilmont 2:e9a661555b58 671 The function sets the priority of an interrupt.
emilmont 2:e9a661555b58 672
emilmont 2:e9a661555b58 673 \note The priority cannot be set for every core interrupt.
emilmont 2:e9a661555b58 674
emilmont 2:e9a661555b58 675 \param [in] IRQn Interrupt number.
emilmont 2:e9a661555b58 676 \param [in] priority Priority to set.
emilmont 2:e9a661555b58 677 */
emilmont 2:e9a661555b58 678 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 2:e9a661555b58 679 {
emilmont 2:e9a661555b58 680 if(IRQn < 0) {
emilmont 2:e9a661555b58 681 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 2:e9a661555b58 682 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 2:e9a661555b58 683 else {
emilmont 2:e9a661555b58 684 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 2:e9a661555b58 685 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 2:e9a661555b58 686 }
emilmont 2:e9a661555b58 687
emilmont 2:e9a661555b58 688
emilmont 2:e9a661555b58 689 /** \brief Get Interrupt Priority
emilmont 2:e9a661555b58 690
emilmont 2:e9a661555b58 691 The function reads the priority of an interrupt. The interrupt
emilmont 2:e9a661555b58 692 number can be positive to specify an external (device specific)
emilmont 2:e9a661555b58 693 interrupt, or negative to specify an internal (core) interrupt.
emilmont 2:e9a661555b58 694
emilmont 2:e9a661555b58 695
emilmont 2:e9a661555b58 696 \param [in] IRQn Interrupt number.
emilmont 2:e9a661555b58 697 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 2:e9a661555b58 698 priority bits of the microcontroller.
emilmont 2:e9a661555b58 699 */
emilmont 2:e9a661555b58 700 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 2:e9a661555b58 701 {
emilmont 2:e9a661555b58 702
emilmont 2:e9a661555b58 703 if(IRQn < 0) {
emilmont 9:663789d7729f 704 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
emilmont 2:e9a661555b58 705 else {
emilmont 9:663789d7729f 706 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont 2:e9a661555b58 707 }
emilmont 2:e9a661555b58 708
emilmont 2:e9a661555b58 709
emilmont 2:e9a661555b58 710 /** \brief System Reset
emilmont 2:e9a661555b58 711
emilmont 2:e9a661555b58 712 The function initiates a system reset request to reset the MCU.
emilmont 2:e9a661555b58 713 */
emilmont 2:e9a661555b58 714 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 2:e9a661555b58 715 {
emilmont 2:e9a661555b58 716 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 2:e9a661555b58 717 buffered write are completed before reset */
emilmont 2:e9a661555b58 718 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emilmont 2:e9a661555b58 719 SCB_AIRCR_SYSRESETREQ_Msk);
emilmont 2:e9a661555b58 720 __DSB(); /* Ensure completion of memory access */
emilmont 2:e9a661555b58 721 while(1); /* wait until reset */
emilmont 2:e9a661555b58 722 }
emilmont 2:e9a661555b58 723
emilmont 2:e9a661555b58 724 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 2:e9a661555b58 725
emilmont 2:e9a661555b58 726
emilmont 2:e9a661555b58 727
emilmont 2:e9a661555b58 728 /* ################################## SysTick function ############################################ */
emilmont 2:e9a661555b58 729 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 2:e9a661555b58 730 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 2:e9a661555b58 731 \brief Functions that configure the System.
emilmont 2:e9a661555b58 732 @{
emilmont 2:e9a661555b58 733 */
emilmont 2:e9a661555b58 734
emilmont 2:e9a661555b58 735 #if (__Vendor_SysTickConfig == 0)
emilmont 2:e9a661555b58 736
emilmont 2:e9a661555b58 737 /** \brief System Tick Configuration
emilmont 2:e9a661555b58 738
emilmont 2:e9a661555b58 739 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 2:e9a661555b58 740 Counter is in free running mode to generate periodic interrupts.
emilmont 2:e9a661555b58 741
emilmont 2:e9a661555b58 742 \param [in] ticks Number of ticks between two interrupts.
emilmont 2:e9a661555b58 743
emilmont 2:e9a661555b58 744 \return 0 Function succeeded.
emilmont 2:e9a661555b58 745 \return 1 Function failed.
emilmont 2:e9a661555b58 746
emilmont 2:e9a661555b58 747 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 2:e9a661555b58 748 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 2:e9a661555b58 749 must contain a vendor-specific implementation of this function.
emilmont 2:e9a661555b58 750
emilmont 2:e9a661555b58 751 */
emilmont 2:e9a661555b58 752 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 2:e9a661555b58 753 {
emilmont 9:663789d7729f 754 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont 2:e9a661555b58 755
emilmont 9:663789d7729f 756 SysTick->LOAD = ticks - 1; /* set reload register */
emilmont 2:e9a661555b58 757 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emilmont 2:e9a661555b58 758 SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont 2:e9a661555b58 759 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 2:e9a661555b58 760 SysTick_CTRL_TICKINT_Msk |
emilmont 2:e9a661555b58 761 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont 2:e9a661555b58 762 return (0); /* Function successful */
emilmont 2:e9a661555b58 763 }
emilmont 2:e9a661555b58 764
emilmont 2:e9a661555b58 765 #endif
emilmont 2:e9a661555b58 766
emilmont 2:e9a661555b58 767 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 2:e9a661555b58 768
emilmont 2:e9a661555b58 769
emilmont 2:e9a661555b58 770
emilmont 2:e9a661555b58 771
emilmont 2:e9a661555b58 772 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
emilmont 2:e9a661555b58 773
emilmont 2:e9a661555b58 774 #endif /* __CMSIS_GENERIC */
emilmont 2:e9a661555b58 775
emilmont 2:e9a661555b58 776 #ifdef __cplusplus
emilmont 2:e9a661555b58 777 }
emilmont 2:e9a661555b58 778 #endif