Emil Johnsen / mbed-src-STM32F030K6

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Fork of mbed-src by Ermanno Brusadin

targets/cmsis/TARGET_STM/TARGET_STM32F4XX/stm32f4xx.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f4xx.h
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.1.0
ebrus 0:0a673c671a56 6 * @date 11-January-2013
ebrus 0:0a673c671a56 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
ebrus 0:0a673c671a56 8 * This file contains all the peripheral register's definitions, bits
ebrus 0:0a673c671a56 9 * definitions and memory mapping for STM32F4xx devices.
ebrus 0:0a673c671a56 10 *
ebrus 0:0a673c671a56 11 * The file is the unique include file that the application programmer
ebrus 0:0a673c671a56 12 * is using in the C source code, usually in main.c. This file contains:
ebrus 0:0a673c671a56 13 * - Configuration section that allows to select:
ebrus 0:0a673c671a56 14 * - The device used in the target application
ebrus 0:0a673c671a56 15 * - To use or not the peripheral's drivers in application code(i.e.
ebrus 0:0a673c671a56 16 * code will be based on direct access to peripheral's registers
ebrus 0:0a673c671a56 17 * rather than drivers API), this option is controlled by
ebrus 0:0a673c671a56 18 * "#define USE_STDPERIPH_DRIVER"
ebrus 0:0a673c671a56 19 * - To change few application-specific parameters such as the HSE
ebrus 0:0a673c671a56 20 * crystal frequency
ebrus 0:0a673c671a56 21 * - Data structures and the address mapping for all peripherals
ebrus 0:0a673c671a56 22 * - Peripheral's registers declarations and bits definition
ebrus 0:0a673c671a56 23 * - Macros to access peripheral's registers hardware
ebrus 0:0a673c671a56 24 *
ebrus 0:0a673c671a56 25 ******************************************************************************
ebrus 0:0a673c671a56 26 * @attention
ebrus 0:0a673c671a56 27 *
ebrus 0:0a673c671a56 28 * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 29 *
ebrus 0:0a673c671a56 30 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
ebrus 0:0a673c671a56 31 * You may not use this file except in compliance with the License.
ebrus 0:0a673c671a56 32 * You may obtain a copy of the License at:
ebrus 0:0a673c671a56 33 *
ebrus 0:0a673c671a56 34 * http://www.st.com/software_license_agreement_liberty_v2
ebrus 0:0a673c671a56 35 *
ebrus 0:0a673c671a56 36 * Unless required by applicable law or agreed to in writing, software
ebrus 0:0a673c671a56 37 * distributed under the License is distributed on an "AS IS" BASIS,
ebrus 0:0a673c671a56 38 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ebrus 0:0a673c671a56 39 * See the License for the specific language governing permissions and
ebrus 0:0a673c671a56 40 * limitations under the License.
ebrus 0:0a673c671a56 41 *
ebrus 0:0a673c671a56 42 ******************************************************************************
ebrus 0:0a673c671a56 43 */
ebrus 0:0a673c671a56 44
ebrus 0:0a673c671a56 45 /** @addtogroup CMSIS
ebrus 0:0a673c671a56 46 * @{
ebrus 0:0a673c671a56 47 */
ebrus 0:0a673c671a56 48
ebrus 0:0a673c671a56 49 /** @addtogroup stm32f4xx
ebrus 0:0a673c671a56 50 * @{
ebrus 0:0a673c671a56 51 */
ebrus 0:0a673c671a56 52
ebrus 0:0a673c671a56 53 #ifndef __STM32F4xx_H
ebrus 0:0a673c671a56 54 #define __STM32F4xx_H
ebrus 0:0a673c671a56 55
ebrus 0:0a673c671a56 56 #ifdef __cplusplus
ebrus 0:0a673c671a56 57 extern "C" {
ebrus 0:0a673c671a56 58 #endif /* __cplusplus */
ebrus 0:0a673c671a56 59
ebrus 0:0a673c671a56 60 /** @addtogroup Library_configuration_section
ebrus 0:0a673c671a56 61 * @{
ebrus 0:0a673c671a56 62 */
ebrus 0:0a673c671a56 63
ebrus 0:0a673c671a56 64 /* Uncomment the line below according to the target STM32 device used in your
ebrus 0:0a673c671a56 65 application
ebrus 0:0a673c671a56 66 */
ebrus 0:0a673c671a56 67
ebrus 0:0a673c671a56 68 #if !defined (STM32F4XX) && !defined (STM32F40XX) && !defined (STM32F427X)
ebrus 0:0a673c671a56 69 #define STM32F40XX /*!< STM32F40xx/41xx Devices */
ebrus 0:0a673c671a56 70 /* #define STM32F427X */ /*!< STM32F427x/437x Devices*/
ebrus 0:0a673c671a56 71 #endif
ebrus 0:0a673c671a56 72
ebrus 0:0a673c671a56 73
ebrus 0:0a673c671a56 74 /* Tip: To avoid modifying this file each time you need to switch between these
ebrus 0:0a673c671a56 75 devices, you can define the device in your toolchain compiler preprocessor.
ebrus 0:0a673c671a56 76 */
ebrus 0:0a673c671a56 77
ebrus 0:0a673c671a56 78 #if !defined (STM32F4XX) && !defined (STM32F40XX) && !defined (STM32F427X)
ebrus 0:0a673c671a56 79 #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
ebrus 0:0a673c671a56 80 #endif
ebrus 0:0a673c671a56 81
ebrus 0:0a673c671a56 82 #if !defined (USE_STDPERIPH_DRIVER)
ebrus 0:0a673c671a56 83 /**
ebrus 0:0a673c671a56 84 * @brief Comment the line below if you will not use the peripherals drivers.
ebrus 0:0a673c671a56 85 In this case, these drivers will not be included and the application code will
ebrus 0:0a673c671a56 86 be based on direct access to peripherals registers
ebrus 0:0a673c671a56 87 */
ebrus 0:0a673c671a56 88 /*#define USE_STDPERIPH_DRIVER */
ebrus 0:0a673c671a56 89 #endif /* USE_STDPERIPH_DRIVER */
ebrus 0:0a673c671a56 90
ebrus 0:0a673c671a56 91 /**
ebrus 0:0a673c671a56 92 * @brief In the following line adjust the value of External High Speed oscillator (HSE)
ebrus 0:0a673c671a56 93 used in your application
ebrus 0:0a673c671a56 94
ebrus 0:0a673c671a56 95 Tip: To avoid modifying this file each time you need to use different HSE, you
ebrus 0:0a673c671a56 96 can define the HSE value in your toolchain compiler preprocessor.
ebrus 0:0a673c671a56 97 */
ebrus 0:0a673c671a56 98
ebrus 0:0a673c671a56 99 #if !defined (HSE_VALUE)
ebrus 0:0a673c671a56 100 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
ebrus 0:0a673c671a56 101 #endif /* HSE_VALUE */
ebrus 0:0a673c671a56 102
ebrus 0:0a673c671a56 103 /**
ebrus 0:0a673c671a56 104 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
ebrus 0:0a673c671a56 105 Timeout value
ebrus 0:0a673c671a56 106 */
ebrus 0:0a673c671a56 107 #if !defined (HSE_STARTUP_TIMEOUT)
ebrus 0:0a673c671a56 108 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
ebrus 0:0a673c671a56 109 #endif /* HSE_STARTUP_TIMEOUT */
ebrus 0:0a673c671a56 110
ebrus 0:0a673c671a56 111 #if !defined (HSI_VALUE)
ebrus 0:0a673c671a56 112 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
ebrus 0:0a673c671a56 113 #endif /* HSI_VALUE */
ebrus 0:0a673c671a56 114
ebrus 0:0a673c671a56 115 /**
ebrus 0:0a673c671a56 116 * @brief STM32F4XX Standard Peripherals Library version number V1.1.0
ebrus 0:0a673c671a56 117 */
ebrus 0:0a673c671a56 118 #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
ebrus 0:0a673c671a56 119 #define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
ebrus 0:0a673c671a56 120 #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
ebrus 0:0a673c671a56 121 #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
ebrus 0:0a673c671a56 122 #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
ebrus 0:0a673c671a56 123 |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
ebrus 0:0a673c671a56 124 |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
ebrus 0:0a673c671a56 125 |(__STM32F4XX_STDPERIPH_VERSION_RC))
ebrus 0:0a673c671a56 126
ebrus 0:0a673c671a56 127 /**
ebrus 0:0a673c671a56 128 * @}
ebrus 0:0a673c671a56 129 */
ebrus 0:0a673c671a56 130
ebrus 0:0a673c671a56 131 /** @addtogroup Configuration_section_for_CMSIS
ebrus 0:0a673c671a56 132 * @{
ebrus 0:0a673c671a56 133 */
ebrus 0:0a673c671a56 134
ebrus 0:0a673c671a56 135 /**
ebrus 0:0a673c671a56 136 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
ebrus 0:0a673c671a56 137 */
ebrus 0:0a673c671a56 138 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
ebrus 0:0a673c671a56 139 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
ebrus 0:0a673c671a56 140 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
ebrus 0:0a673c671a56 141 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
ebrus 0:0a673c671a56 142 #define __FPU_PRESENT 1 /*!< FPU present */
ebrus 0:0a673c671a56 143
ebrus 0:0a673c671a56 144 /**
ebrus 0:0a673c671a56 145 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
ebrus 0:0a673c671a56 146 * in @ref Library_configuration_section
ebrus 0:0a673c671a56 147 */
ebrus 0:0a673c671a56 148 typedef enum IRQn
ebrus 0:0a673c671a56 149 {
ebrus 0:0a673c671a56 150 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
ebrus 0:0a673c671a56 151 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
ebrus 0:0a673c671a56 152 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
ebrus 0:0a673c671a56 153 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
ebrus 0:0a673c671a56 154 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
ebrus 0:0a673c671a56 155 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
ebrus 0:0a673c671a56 156 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
ebrus 0:0a673c671a56 157 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
ebrus 0:0a673c671a56 158 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
ebrus 0:0a673c671a56 159 /****** STM32 specific Interrupt Numbers **********************************************************************/
ebrus 0:0a673c671a56 160 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
ebrus 0:0a673c671a56 161 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
ebrus 0:0a673c671a56 162 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
ebrus 0:0a673c671a56 163 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
ebrus 0:0a673c671a56 164 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
ebrus 0:0a673c671a56 165 RCC_IRQn = 5, /*!< RCC global Interrupt */
ebrus 0:0a673c671a56 166 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
ebrus 0:0a673c671a56 167 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
ebrus 0:0a673c671a56 168 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
ebrus 0:0a673c671a56 169 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
ebrus 0:0a673c671a56 170 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
ebrus 0:0a673c671a56 171 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
ebrus 0:0a673c671a56 172 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
ebrus 0:0a673c671a56 173 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
ebrus 0:0a673c671a56 174 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
ebrus 0:0a673c671a56 175 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
ebrus 0:0a673c671a56 176 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
ebrus 0:0a673c671a56 177 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
ebrus 0:0a673c671a56 178 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
ebrus 0:0a673c671a56 179 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
ebrus 0:0a673c671a56 180 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
ebrus 0:0a673c671a56 181 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
ebrus 0:0a673c671a56 182 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
ebrus 0:0a673c671a56 183 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
ebrus 0:0a673c671a56 184 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
ebrus 0:0a673c671a56 185 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
ebrus 0:0a673c671a56 186 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
ebrus 0:0a673c671a56 187 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
ebrus 0:0a673c671a56 188 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
ebrus 0:0a673c671a56 189 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
ebrus 0:0a673c671a56 190 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
ebrus 0:0a673c671a56 191 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
ebrus 0:0a673c671a56 192 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
ebrus 0:0a673c671a56 193 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
ebrus 0:0a673c671a56 194 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
ebrus 0:0a673c671a56 195 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
ebrus 0:0a673c671a56 196 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
ebrus 0:0a673c671a56 197 USART1_IRQn = 37, /*!< USART1 global Interrupt */
ebrus 0:0a673c671a56 198 USART2_IRQn = 38, /*!< USART2 global Interrupt */
ebrus 0:0a673c671a56 199 USART3_IRQn = 39, /*!< USART3 global Interrupt */
ebrus 0:0a673c671a56 200 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
ebrus 0:0a673c671a56 201 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
ebrus 0:0a673c671a56 202 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
ebrus 0:0a673c671a56 203 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
ebrus 0:0a673c671a56 204 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
ebrus 0:0a673c671a56 205 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
ebrus 0:0a673c671a56 206 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
ebrus 0:0a673c671a56 207 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
ebrus 0:0a673c671a56 208 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
ebrus 0:0a673c671a56 209 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
ebrus 0:0a673c671a56 210 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
ebrus 0:0a673c671a56 211 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
ebrus 0:0a673c671a56 212 UART4_IRQn = 52, /*!< UART4 global Interrupt */
ebrus 0:0a673c671a56 213 UART5_IRQn = 53, /*!< UART5 global Interrupt */
ebrus 0:0a673c671a56 214 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
ebrus 0:0a673c671a56 215 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
ebrus 0:0a673c671a56 216 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
ebrus 0:0a673c671a56 217 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
ebrus 0:0a673c671a56 218 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
ebrus 0:0a673c671a56 219 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
ebrus 0:0a673c671a56 220 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
ebrus 0:0a673c671a56 221 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
ebrus 0:0a673c671a56 222 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
ebrus 0:0a673c671a56 223 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
ebrus 0:0a673c671a56 224 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
ebrus 0:0a673c671a56 225 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
ebrus 0:0a673c671a56 226 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
ebrus 0:0a673c671a56 227 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
ebrus 0:0a673c671a56 228 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
ebrus 0:0a673c671a56 229 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
ebrus 0:0a673c671a56 230 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
ebrus 0:0a673c671a56 231 USART6_IRQn = 71, /*!< USART6 global interrupt */
ebrus 0:0a673c671a56 232 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
ebrus 0:0a673c671a56 233 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
ebrus 0:0a673c671a56 234 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
ebrus 0:0a673c671a56 235 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
ebrus 0:0a673c671a56 236 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
ebrus 0:0a673c671a56 237 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
ebrus 0:0a673c671a56 238 DCMI_IRQn = 78, /*!< DCMI global interrupt */
ebrus 0:0a673c671a56 239 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
ebrus 0:0a673c671a56 240 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
ebrus 0:0a673c671a56 241
ebrus 0:0a673c671a56 242 #ifdef STM32F40XX
ebrus 0:0a673c671a56 243 FPU_IRQn = 81 /*!< FPU global interrupt */
ebrus 0:0a673c671a56 244 #endif /* STM32F40XX */
ebrus 0:0a673c671a56 245
ebrus 0:0a673c671a56 246 #ifdef STM32F427X
ebrus 0:0a673c671a56 247 FPU_IRQn = 81, /*!< FPU global interrupt */
ebrus 0:0a673c671a56 248 UART7_IRQn = 82, /*!< UART7 global interrupt */
ebrus 0:0a673c671a56 249 UART8_IRQn = 83, /*!< UART8 global interrupt */
ebrus 0:0a673c671a56 250 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
ebrus 0:0a673c671a56 251 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
ebrus 0:0a673c671a56 252 SPI6_IRQn = 86 /*!< SPI6 global Interrupt */
ebrus 0:0a673c671a56 253 #endif /* STM32F427X */
ebrus 0:0a673c671a56 254
ebrus 0:0a673c671a56 255 } IRQn_Type;
ebrus 0:0a673c671a56 256
ebrus 0:0a673c671a56 257 /**
ebrus 0:0a673c671a56 258 * @}
ebrus 0:0a673c671a56 259 */
ebrus 0:0a673c671a56 260
ebrus 0:0a673c671a56 261 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
ebrus 0:0a673c671a56 262 #include "system_stm32f4xx.h"
ebrus 0:0a673c671a56 263 #include <stdint.h>
ebrus 0:0a673c671a56 264
ebrus 0:0a673c671a56 265 /** @addtogroup Exported_types
ebrus 0:0a673c671a56 266 * @{
ebrus 0:0a673c671a56 267 */
ebrus 0:0a673c671a56 268 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
ebrus 0:0a673c671a56 269 typedef int32_t s32;
ebrus 0:0a673c671a56 270 typedef int16_t s16;
ebrus 0:0a673c671a56 271 typedef int8_t s8;
ebrus 0:0a673c671a56 272
ebrus 0:0a673c671a56 273 typedef const int32_t sc32; /*!< Read Only */
ebrus 0:0a673c671a56 274 typedef const int16_t sc16; /*!< Read Only */
ebrus 0:0a673c671a56 275 typedef const int8_t sc8; /*!< Read Only */
ebrus 0:0a673c671a56 276
ebrus 0:0a673c671a56 277 typedef __IO int32_t vs32;
ebrus 0:0a673c671a56 278 typedef __IO int16_t vs16;
ebrus 0:0a673c671a56 279 typedef __IO int8_t vs8;
ebrus 0:0a673c671a56 280
ebrus 0:0a673c671a56 281 typedef __I int32_t vsc32; /*!< Read Only */
ebrus 0:0a673c671a56 282 typedef __I int16_t vsc16; /*!< Read Only */
ebrus 0:0a673c671a56 283 typedef __I int8_t vsc8; /*!< Read Only */
ebrus 0:0a673c671a56 284
ebrus 0:0a673c671a56 285 typedef uint32_t u32;
ebrus 0:0a673c671a56 286 typedef uint16_t u16;
ebrus 0:0a673c671a56 287 typedef uint8_t u8;
ebrus 0:0a673c671a56 288
ebrus 0:0a673c671a56 289 typedef const uint32_t uc32; /*!< Read Only */
ebrus 0:0a673c671a56 290 typedef const uint16_t uc16; /*!< Read Only */
ebrus 0:0a673c671a56 291 typedef const uint8_t uc8; /*!< Read Only */
ebrus 0:0a673c671a56 292
ebrus 0:0a673c671a56 293 typedef __IO uint32_t vu32;
ebrus 0:0a673c671a56 294 typedef __IO uint16_t vu16;
ebrus 0:0a673c671a56 295 typedef __IO uint8_t vu8;
ebrus 0:0a673c671a56 296
ebrus 0:0a673c671a56 297 typedef __I uint32_t vuc32; /*!< Read Only */
ebrus 0:0a673c671a56 298 typedef __I uint16_t vuc16; /*!< Read Only */
ebrus 0:0a673c671a56 299 typedef __I uint8_t vuc8; /*!< Read Only */
ebrus 0:0a673c671a56 300
ebrus 0:0a673c671a56 301 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
ebrus 0:0a673c671a56 302
ebrus 0:0a673c671a56 303 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
ebrus 0:0a673c671a56 304 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
ebrus 0:0a673c671a56 305
ebrus 0:0a673c671a56 306 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
ebrus 0:0a673c671a56 307
ebrus 0:0a673c671a56 308 /**
ebrus 0:0a673c671a56 309 * @}
ebrus 0:0a673c671a56 310 */
ebrus 0:0a673c671a56 311
ebrus 0:0a673c671a56 312 /** @addtogroup Peripheral_registers_structures
ebrus 0:0a673c671a56 313 * @{
ebrus 0:0a673c671a56 314 */
ebrus 0:0a673c671a56 315
ebrus 0:0a673c671a56 316 /**
ebrus 0:0a673c671a56 317 * @brief Analog to Digital Converter
ebrus 0:0a673c671a56 318 */
ebrus 0:0a673c671a56 319
ebrus 0:0a673c671a56 320 typedef struct
ebrus 0:0a673c671a56 321 {
ebrus 0:0a673c671a56 322 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
ebrus 0:0a673c671a56 323 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
ebrus 0:0a673c671a56 324 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
ebrus 0:0a673c671a56 325 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
ebrus 0:0a673c671a56 326 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
ebrus 0:0a673c671a56 327 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
ebrus 0:0a673c671a56 328 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
ebrus 0:0a673c671a56 329 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
ebrus 0:0a673c671a56 330 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
ebrus 0:0a673c671a56 331 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
ebrus 0:0a673c671a56 332 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
ebrus 0:0a673c671a56 333 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
ebrus 0:0a673c671a56 334 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
ebrus 0:0a673c671a56 335 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
ebrus 0:0a673c671a56 336 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
ebrus 0:0a673c671a56 337 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
ebrus 0:0a673c671a56 338 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
ebrus 0:0a673c671a56 339 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
ebrus 0:0a673c671a56 340 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
ebrus 0:0a673c671a56 341 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
ebrus 0:0a673c671a56 342 } ADC_TypeDef;
ebrus 0:0a673c671a56 343
ebrus 0:0a673c671a56 344 typedef struct
ebrus 0:0a673c671a56 345 {
ebrus 0:0a673c671a56 346 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
ebrus 0:0a673c671a56 347 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
ebrus 0:0a673c671a56 348 __IO uint32_t CDR; /*!< ADC common regular data register for dual
ebrus 0:0a673c671a56 349 AND triple modes, Address offset: ADC1 base address + 0x308 */
ebrus 0:0a673c671a56 350 } ADC_Common_TypeDef;
ebrus 0:0a673c671a56 351
ebrus 0:0a673c671a56 352
ebrus 0:0a673c671a56 353 /**
ebrus 0:0a673c671a56 354 * @brief Controller Area Network TxMailBox
ebrus 0:0a673c671a56 355 */
ebrus 0:0a673c671a56 356
ebrus 0:0a673c671a56 357 typedef struct
ebrus 0:0a673c671a56 358 {
ebrus 0:0a673c671a56 359 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
ebrus 0:0a673c671a56 360 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
ebrus 0:0a673c671a56 361 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
ebrus 0:0a673c671a56 362 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
ebrus 0:0a673c671a56 363 } CAN_TxMailBox_TypeDef;
ebrus 0:0a673c671a56 364
ebrus 0:0a673c671a56 365 /**
ebrus 0:0a673c671a56 366 * @brief Controller Area Network FIFOMailBox
ebrus 0:0a673c671a56 367 */
ebrus 0:0a673c671a56 368
ebrus 0:0a673c671a56 369 typedef struct
ebrus 0:0a673c671a56 370 {
ebrus 0:0a673c671a56 371 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
ebrus 0:0a673c671a56 372 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
ebrus 0:0a673c671a56 373 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
ebrus 0:0a673c671a56 374 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
ebrus 0:0a673c671a56 375 } CAN_FIFOMailBox_TypeDef;
ebrus 0:0a673c671a56 376
ebrus 0:0a673c671a56 377 /**
ebrus 0:0a673c671a56 378 * @brief Controller Area Network FilterRegister
ebrus 0:0a673c671a56 379 */
ebrus 0:0a673c671a56 380
ebrus 0:0a673c671a56 381 typedef struct
ebrus 0:0a673c671a56 382 {
ebrus 0:0a673c671a56 383 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
ebrus 0:0a673c671a56 384 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
ebrus 0:0a673c671a56 385 } CAN_FilterRegister_TypeDef;
ebrus 0:0a673c671a56 386
ebrus 0:0a673c671a56 387 /**
ebrus 0:0a673c671a56 388 * @brief Controller Area Network
ebrus 0:0a673c671a56 389 */
ebrus 0:0a673c671a56 390
ebrus 0:0a673c671a56 391 typedef struct
ebrus 0:0a673c671a56 392 {
ebrus 0:0a673c671a56 393 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
ebrus 0:0a673c671a56 394 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
ebrus 0:0a673c671a56 395 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
ebrus 0:0a673c671a56 396 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
ebrus 0:0a673c671a56 397 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
ebrus 0:0a673c671a56 398 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
ebrus 0:0a673c671a56 399 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
ebrus 0:0a673c671a56 400 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
ebrus 0:0a673c671a56 401 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
ebrus 0:0a673c671a56 402 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
ebrus 0:0a673c671a56 403 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
ebrus 0:0a673c671a56 404 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
ebrus 0:0a673c671a56 405 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
ebrus 0:0a673c671a56 406 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
ebrus 0:0a673c671a56 407 uint32_t RESERVED2; /*!< Reserved, 0x208 */
ebrus 0:0a673c671a56 408 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
ebrus 0:0a673c671a56 409 uint32_t RESERVED3; /*!< Reserved, 0x210 */
ebrus 0:0a673c671a56 410 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
ebrus 0:0a673c671a56 411 uint32_t RESERVED4; /*!< Reserved, 0x218 */
ebrus 0:0a673c671a56 412 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
ebrus 0:0a673c671a56 413 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
ebrus 0:0a673c671a56 414 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
ebrus 0:0a673c671a56 415 } CAN_TypeDef;
ebrus 0:0a673c671a56 416
ebrus 0:0a673c671a56 417 /**
ebrus 0:0a673c671a56 418 * @brief CRC calculation unit
ebrus 0:0a673c671a56 419 */
ebrus 0:0a673c671a56 420
ebrus 0:0a673c671a56 421 typedef struct
ebrus 0:0a673c671a56 422 {
ebrus 0:0a673c671a56 423 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
ebrus 0:0a673c671a56 424 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
ebrus 0:0a673c671a56 425 uint8_t RESERVED0; /*!< Reserved, 0x05 */
ebrus 0:0a673c671a56 426 uint16_t RESERVED1; /*!< Reserved, 0x06 */
ebrus 0:0a673c671a56 427 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
ebrus 0:0a673c671a56 428 } CRC_TypeDef;
ebrus 0:0a673c671a56 429
ebrus 0:0a673c671a56 430 /**
ebrus 0:0a673c671a56 431 * @brief Digital to Analog Converter
ebrus 0:0a673c671a56 432 */
ebrus 0:0a673c671a56 433
ebrus 0:0a673c671a56 434 typedef struct
ebrus 0:0a673c671a56 435 {
ebrus 0:0a673c671a56 436 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
ebrus 0:0a673c671a56 437 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
ebrus 0:0a673c671a56 438 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
ebrus 0:0a673c671a56 439 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
ebrus 0:0a673c671a56 440 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
ebrus 0:0a673c671a56 441 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
ebrus 0:0a673c671a56 442 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
ebrus 0:0a673c671a56 443 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
ebrus 0:0a673c671a56 444 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
ebrus 0:0a673c671a56 445 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
ebrus 0:0a673c671a56 446 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
ebrus 0:0a673c671a56 447 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
ebrus 0:0a673c671a56 448 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
ebrus 0:0a673c671a56 449 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
ebrus 0:0a673c671a56 450 } DAC_TypeDef;
ebrus 0:0a673c671a56 451
ebrus 0:0a673c671a56 452 /**
ebrus 0:0a673c671a56 453 * @brief Debug MCU
ebrus 0:0a673c671a56 454 */
ebrus 0:0a673c671a56 455
ebrus 0:0a673c671a56 456 typedef struct
ebrus 0:0a673c671a56 457 {
ebrus 0:0a673c671a56 458 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
ebrus 0:0a673c671a56 459 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
ebrus 0:0a673c671a56 460 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
ebrus 0:0a673c671a56 461 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
ebrus 0:0a673c671a56 462 }DBGMCU_TypeDef;
ebrus 0:0a673c671a56 463
ebrus 0:0a673c671a56 464 /**
ebrus 0:0a673c671a56 465 * @brief DCMI
ebrus 0:0a673c671a56 466 */
ebrus 0:0a673c671a56 467
ebrus 0:0a673c671a56 468 typedef struct
ebrus 0:0a673c671a56 469 {
ebrus 0:0a673c671a56 470 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
ebrus 0:0a673c671a56 471 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
ebrus 0:0a673c671a56 472 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
ebrus 0:0a673c671a56 473 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
ebrus 0:0a673c671a56 474 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
ebrus 0:0a673c671a56 475 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
ebrus 0:0a673c671a56 476 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
ebrus 0:0a673c671a56 477 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
ebrus 0:0a673c671a56 478 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
ebrus 0:0a673c671a56 479 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
ebrus 0:0a673c671a56 480 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
ebrus 0:0a673c671a56 481 } DCMI_TypeDef;
ebrus 0:0a673c671a56 482
ebrus 0:0a673c671a56 483 /**
ebrus 0:0a673c671a56 484 * @brief DMA Controller
ebrus 0:0a673c671a56 485 */
ebrus 0:0a673c671a56 486
ebrus 0:0a673c671a56 487 typedef struct
ebrus 0:0a673c671a56 488 {
ebrus 0:0a673c671a56 489 __IO uint32_t CR; /*!< DMA stream x configuration register */
ebrus 0:0a673c671a56 490 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
ebrus 0:0a673c671a56 491 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
ebrus 0:0a673c671a56 492 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
ebrus 0:0a673c671a56 493 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
ebrus 0:0a673c671a56 494 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
ebrus 0:0a673c671a56 495 } DMA_Stream_TypeDef;
ebrus 0:0a673c671a56 496
ebrus 0:0a673c671a56 497 typedef struct
ebrus 0:0a673c671a56 498 {
ebrus 0:0a673c671a56 499 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
ebrus 0:0a673c671a56 500 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
ebrus 0:0a673c671a56 501 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
ebrus 0:0a673c671a56 502 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
ebrus 0:0a673c671a56 503 } DMA_TypeDef;
ebrus 0:0a673c671a56 504
ebrus 0:0a673c671a56 505 /**
ebrus 0:0a673c671a56 506 * @brief Ethernet MAC
ebrus 0:0a673c671a56 507 */
ebrus 0:0a673c671a56 508
ebrus 0:0a673c671a56 509 typedef struct
ebrus 0:0a673c671a56 510 {
ebrus 0:0a673c671a56 511 __IO uint32_t MACCR;
ebrus 0:0a673c671a56 512 __IO uint32_t MACFFR;
ebrus 0:0a673c671a56 513 __IO uint32_t MACHTHR;
ebrus 0:0a673c671a56 514 __IO uint32_t MACHTLR;
ebrus 0:0a673c671a56 515 __IO uint32_t MACMIIAR;
ebrus 0:0a673c671a56 516 __IO uint32_t MACMIIDR;
ebrus 0:0a673c671a56 517 __IO uint32_t MACFCR;
ebrus 0:0a673c671a56 518 __IO uint32_t MACVLANTR; /* 8 */
ebrus 0:0a673c671a56 519 uint32_t RESERVED0[2];
ebrus 0:0a673c671a56 520 __IO uint32_t MACRWUFFR; /* 11 */
ebrus 0:0a673c671a56 521 __IO uint32_t MACPMTCSR;
ebrus 0:0a673c671a56 522 uint32_t RESERVED1[2];
ebrus 0:0a673c671a56 523 __IO uint32_t MACSR; /* 15 */
ebrus 0:0a673c671a56 524 __IO uint32_t MACIMR;
ebrus 0:0a673c671a56 525 __IO uint32_t MACA0HR;
ebrus 0:0a673c671a56 526 __IO uint32_t MACA0LR;
ebrus 0:0a673c671a56 527 __IO uint32_t MACA1HR;
ebrus 0:0a673c671a56 528 __IO uint32_t MACA1LR;
ebrus 0:0a673c671a56 529 __IO uint32_t MACA2HR;
ebrus 0:0a673c671a56 530 __IO uint32_t MACA2LR;
ebrus 0:0a673c671a56 531 __IO uint32_t MACA3HR;
ebrus 0:0a673c671a56 532 __IO uint32_t MACA3LR; /* 24 */
ebrus 0:0a673c671a56 533 uint32_t RESERVED2[40];
ebrus 0:0a673c671a56 534 __IO uint32_t MMCCR; /* 65 */
ebrus 0:0a673c671a56 535 __IO uint32_t MMCRIR;
ebrus 0:0a673c671a56 536 __IO uint32_t MMCTIR;
ebrus 0:0a673c671a56 537 __IO uint32_t MMCRIMR;
ebrus 0:0a673c671a56 538 __IO uint32_t MMCTIMR; /* 69 */
ebrus 0:0a673c671a56 539 uint32_t RESERVED3[14];
ebrus 0:0a673c671a56 540 __IO uint32_t MMCTGFSCCR; /* 84 */
ebrus 0:0a673c671a56 541 __IO uint32_t MMCTGFMSCCR;
ebrus 0:0a673c671a56 542 uint32_t RESERVED4[5];
ebrus 0:0a673c671a56 543 __IO uint32_t MMCTGFCR;
ebrus 0:0a673c671a56 544 uint32_t RESERVED5[10];
ebrus 0:0a673c671a56 545 __IO uint32_t MMCRFCECR;
ebrus 0:0a673c671a56 546 __IO uint32_t MMCRFAECR;
ebrus 0:0a673c671a56 547 uint32_t RESERVED6[10];
ebrus 0:0a673c671a56 548 __IO uint32_t MMCRGUFCR;
ebrus 0:0a673c671a56 549 uint32_t RESERVED7[334];
ebrus 0:0a673c671a56 550 __IO uint32_t PTPTSCR;
ebrus 0:0a673c671a56 551 __IO uint32_t PTPSSIR;
ebrus 0:0a673c671a56 552 __IO uint32_t PTPTSHR;
ebrus 0:0a673c671a56 553 __IO uint32_t PTPTSLR;
ebrus 0:0a673c671a56 554 __IO uint32_t PTPTSHUR;
ebrus 0:0a673c671a56 555 __IO uint32_t PTPTSLUR;
ebrus 0:0a673c671a56 556 __IO uint32_t PTPTSAR;
ebrus 0:0a673c671a56 557 __IO uint32_t PTPTTHR;
ebrus 0:0a673c671a56 558 __IO uint32_t PTPTTLR;
ebrus 0:0a673c671a56 559 __IO uint32_t RESERVED8;
ebrus 0:0a673c671a56 560 __IO uint32_t PTPTSSR;
ebrus 0:0a673c671a56 561 uint32_t RESERVED9[565];
ebrus 0:0a673c671a56 562 __IO uint32_t DMABMR;
ebrus 0:0a673c671a56 563 __IO uint32_t DMATPDR;
ebrus 0:0a673c671a56 564 __IO uint32_t DMARPDR;
ebrus 0:0a673c671a56 565 __IO uint32_t DMARDLAR;
ebrus 0:0a673c671a56 566 __IO uint32_t DMATDLAR;
ebrus 0:0a673c671a56 567 __IO uint32_t DMASR;
ebrus 0:0a673c671a56 568 __IO uint32_t DMAOMR;
ebrus 0:0a673c671a56 569 __IO uint32_t DMAIER;
ebrus 0:0a673c671a56 570 __IO uint32_t DMAMFBOCR;
ebrus 0:0a673c671a56 571 __IO uint32_t DMARSWTR;
ebrus 0:0a673c671a56 572 uint32_t RESERVED10[8];
ebrus 0:0a673c671a56 573 __IO uint32_t DMACHTDR;
ebrus 0:0a673c671a56 574 __IO uint32_t DMACHRDR;
ebrus 0:0a673c671a56 575 __IO uint32_t DMACHTBAR;
ebrus 0:0a673c671a56 576 __IO uint32_t DMACHRBAR;
ebrus 0:0a673c671a56 577 } ETH_TypeDef;
ebrus 0:0a673c671a56 578
ebrus 0:0a673c671a56 579 /**
ebrus 0:0a673c671a56 580 * @brief External Interrupt/Event Controller
ebrus 0:0a673c671a56 581 */
ebrus 0:0a673c671a56 582
ebrus 0:0a673c671a56 583 typedef struct
ebrus 0:0a673c671a56 584 {
ebrus 0:0a673c671a56 585 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
ebrus 0:0a673c671a56 586 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
ebrus 0:0a673c671a56 587 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
ebrus 0:0a673c671a56 588 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
ebrus 0:0a673c671a56 589 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
ebrus 0:0a673c671a56 590 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
ebrus 0:0a673c671a56 591 } EXTI_TypeDef;
ebrus 0:0a673c671a56 592
ebrus 0:0a673c671a56 593 /**
ebrus 0:0a673c671a56 594 * @brief FLASH Registers
ebrus 0:0a673c671a56 595 */
ebrus 0:0a673c671a56 596
ebrus 0:0a673c671a56 597 typedef struct
ebrus 0:0a673c671a56 598 {
ebrus 0:0a673c671a56 599 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
ebrus 0:0a673c671a56 600 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
ebrus 0:0a673c671a56 601 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
ebrus 0:0a673c671a56 602 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
ebrus 0:0a673c671a56 603 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
ebrus 0:0a673c671a56 604 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
ebrus 0:0a673c671a56 605 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
ebrus 0:0a673c671a56 606 } FLASH_TypeDef;
ebrus 0:0a673c671a56 607
ebrus 0:0a673c671a56 608 /**
ebrus 0:0a673c671a56 609 * @brief Flexible Static Memory Controller
ebrus 0:0a673c671a56 610 */
ebrus 0:0a673c671a56 611
ebrus 0:0a673c671a56 612 typedef struct
ebrus 0:0a673c671a56 613 {
ebrus 0:0a673c671a56 614 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
ebrus 0:0a673c671a56 615 } FSMC_Bank1_TypeDef;
ebrus 0:0a673c671a56 616
ebrus 0:0a673c671a56 617 /**
ebrus 0:0a673c671a56 618 * @brief Flexible Static Memory Controller Bank1E
ebrus 0:0a673c671a56 619 */
ebrus 0:0a673c671a56 620
ebrus 0:0a673c671a56 621 typedef struct
ebrus 0:0a673c671a56 622 {
ebrus 0:0a673c671a56 623 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
ebrus 0:0a673c671a56 624 } FSMC_Bank1E_TypeDef;
ebrus 0:0a673c671a56 625
ebrus 0:0a673c671a56 626 /**
ebrus 0:0a673c671a56 627 * @brief Flexible Static Memory Controller Bank2
ebrus 0:0a673c671a56 628 */
ebrus 0:0a673c671a56 629
ebrus 0:0a673c671a56 630 typedef struct
ebrus 0:0a673c671a56 631 {
ebrus 0:0a673c671a56 632 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
ebrus 0:0a673c671a56 633 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
ebrus 0:0a673c671a56 634 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
ebrus 0:0a673c671a56 635 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
ebrus 0:0a673c671a56 636 uint32_t RESERVED0; /*!< Reserved, 0x70 */
ebrus 0:0a673c671a56 637 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
ebrus 0:0a673c671a56 638 } FSMC_Bank2_TypeDef;
ebrus 0:0a673c671a56 639
ebrus 0:0a673c671a56 640 /**
ebrus 0:0a673c671a56 641 * @brief Flexible Static Memory Controller Bank3
ebrus 0:0a673c671a56 642 */
ebrus 0:0a673c671a56 643
ebrus 0:0a673c671a56 644 typedef struct
ebrus 0:0a673c671a56 645 {
ebrus 0:0a673c671a56 646 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
ebrus 0:0a673c671a56 647 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
ebrus 0:0a673c671a56 648 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
ebrus 0:0a673c671a56 649 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
ebrus 0:0a673c671a56 650 uint32_t RESERVED0; /*!< Reserved, 0x90 */
ebrus 0:0a673c671a56 651 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
ebrus 0:0a673c671a56 652 } FSMC_Bank3_TypeDef;
ebrus 0:0a673c671a56 653
ebrus 0:0a673c671a56 654 /**
ebrus 0:0a673c671a56 655 * @brief Flexible Static Memory Controller Bank4
ebrus 0:0a673c671a56 656 */
ebrus 0:0a673c671a56 657
ebrus 0:0a673c671a56 658 typedef struct
ebrus 0:0a673c671a56 659 {
ebrus 0:0a673c671a56 660 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
ebrus 0:0a673c671a56 661 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
ebrus 0:0a673c671a56 662 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
ebrus 0:0a673c671a56 663 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
ebrus 0:0a673c671a56 664 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
ebrus 0:0a673c671a56 665 } FSMC_Bank4_TypeDef;
ebrus 0:0a673c671a56 666
ebrus 0:0a673c671a56 667 /**
ebrus 0:0a673c671a56 668 * @brief General Purpose I/O
ebrus 0:0a673c671a56 669 */
ebrus 0:0a673c671a56 670
ebrus 0:0a673c671a56 671 typedef struct
ebrus 0:0a673c671a56 672 {
ebrus 0:0a673c671a56 673 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
ebrus 0:0a673c671a56 674 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
ebrus 0:0a673c671a56 675 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
ebrus 0:0a673c671a56 676 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
ebrus 0:0a673c671a56 677 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
ebrus 0:0a673c671a56 678 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
ebrus 0:0a673c671a56 679 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
ebrus 0:0a673c671a56 680 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
ebrus 0:0a673c671a56 681 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
ebrus 0:0a673c671a56 682 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
ebrus 0:0a673c671a56 683 } GPIO_TypeDef;
ebrus 0:0a673c671a56 684
ebrus 0:0a673c671a56 685 /**
ebrus 0:0a673c671a56 686 * @brief System configuration controller
ebrus 0:0a673c671a56 687 */
ebrus 0:0a673c671a56 688
ebrus 0:0a673c671a56 689 typedef struct
ebrus 0:0a673c671a56 690 {
ebrus 0:0a673c671a56 691 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
ebrus 0:0a673c671a56 692 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
ebrus 0:0a673c671a56 693 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
ebrus 0:0a673c671a56 694 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
ebrus 0:0a673c671a56 695 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
ebrus 0:0a673c671a56 696 } SYSCFG_TypeDef;
ebrus 0:0a673c671a56 697
ebrus 0:0a673c671a56 698 /**
ebrus 0:0a673c671a56 699 * @brief Inter-integrated Circuit Interface
ebrus 0:0a673c671a56 700 */
ebrus 0:0a673c671a56 701
ebrus 0:0a673c671a56 702 typedef struct
ebrus 0:0a673c671a56 703 {
ebrus 0:0a673c671a56 704 __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
ebrus 0:0a673c671a56 705 uint16_t RESERVED0; /*!< Reserved, 0x02 */
ebrus 0:0a673c671a56 706 __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
ebrus 0:0a673c671a56 707 uint16_t RESERVED1; /*!< Reserved, 0x06 */
ebrus 0:0a673c671a56 708 __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
ebrus 0:0a673c671a56 709 uint16_t RESERVED2; /*!< Reserved, 0x0A */
ebrus 0:0a673c671a56 710 __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
ebrus 0:0a673c671a56 711 uint16_t RESERVED3; /*!< Reserved, 0x0E */
ebrus 0:0a673c671a56 712 __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
ebrus 0:0a673c671a56 713 uint16_t RESERVED4; /*!< Reserved, 0x12 */
ebrus 0:0a673c671a56 714 __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
ebrus 0:0a673c671a56 715 uint16_t RESERVED5; /*!< Reserved, 0x16 */
ebrus 0:0a673c671a56 716 __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
ebrus 0:0a673c671a56 717 uint16_t RESERVED6; /*!< Reserved, 0x1A */
ebrus 0:0a673c671a56 718 __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
ebrus 0:0a673c671a56 719 uint16_t RESERVED7; /*!< Reserved, 0x1E */
ebrus 0:0a673c671a56 720 __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
ebrus 0:0a673c671a56 721 uint16_t RESERVED8; /*!< Reserved, 0x22 */
ebrus 0:0a673c671a56 722 __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
ebrus 0:0a673c671a56 723 uint16_t RESERVED9; /*!< Reserved, 0x26 */
ebrus 0:0a673c671a56 724 } I2C_TypeDef;
ebrus 0:0a673c671a56 725
ebrus 0:0a673c671a56 726 /**
ebrus 0:0a673c671a56 727 * @brief Independent WATCHDOG
ebrus 0:0a673c671a56 728 */
ebrus 0:0a673c671a56 729
ebrus 0:0a673c671a56 730 typedef struct
ebrus 0:0a673c671a56 731 {
ebrus 0:0a673c671a56 732 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
ebrus 0:0a673c671a56 733 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
ebrus 0:0a673c671a56 734 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
ebrus 0:0a673c671a56 735 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
ebrus 0:0a673c671a56 736 } IWDG_TypeDef;
ebrus 0:0a673c671a56 737
ebrus 0:0a673c671a56 738 /**
ebrus 0:0a673c671a56 739 * @brief Power Control
ebrus 0:0a673c671a56 740 */
ebrus 0:0a673c671a56 741
ebrus 0:0a673c671a56 742 typedef struct
ebrus 0:0a673c671a56 743 {
ebrus 0:0a673c671a56 744 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
ebrus 0:0a673c671a56 745 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
ebrus 0:0a673c671a56 746 } PWR_TypeDef;
ebrus 0:0a673c671a56 747
ebrus 0:0a673c671a56 748 /**
ebrus 0:0a673c671a56 749 * @brief Reset and Clock Control
ebrus 0:0a673c671a56 750 */
ebrus 0:0a673c671a56 751
ebrus 0:0a673c671a56 752 typedef struct
ebrus 0:0a673c671a56 753 {
ebrus 0:0a673c671a56 754 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
ebrus 0:0a673c671a56 755 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
ebrus 0:0a673c671a56 756 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
ebrus 0:0a673c671a56 757 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
ebrus 0:0a673c671a56 758 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
ebrus 0:0a673c671a56 759 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
ebrus 0:0a673c671a56 760 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
ebrus 0:0a673c671a56 761 uint32_t RESERVED0; /*!< Reserved, 0x1C */
ebrus 0:0a673c671a56 762 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
ebrus 0:0a673c671a56 763 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
ebrus 0:0a673c671a56 764 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
ebrus 0:0a673c671a56 765 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
ebrus 0:0a673c671a56 766 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
ebrus 0:0a673c671a56 767 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
ebrus 0:0a673c671a56 768 uint32_t RESERVED2; /*!< Reserved, 0x3C */
ebrus 0:0a673c671a56 769 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
ebrus 0:0a673c671a56 770 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
ebrus 0:0a673c671a56 771 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
ebrus 0:0a673c671a56 772 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
ebrus 0:0a673c671a56 773 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
ebrus 0:0a673c671a56 774 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
ebrus 0:0a673c671a56 775 uint32_t RESERVED4; /*!< Reserved, 0x5C */
ebrus 0:0a673c671a56 776 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
ebrus 0:0a673c671a56 777 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
ebrus 0:0a673c671a56 778 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
ebrus 0:0a673c671a56 779 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
ebrus 0:0a673c671a56 780 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
ebrus 0:0a673c671a56 781 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
ebrus 0:0a673c671a56 782 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
ebrus 0:0a673c671a56 783 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
ebrus 0:0a673c671a56 784
ebrus 0:0a673c671a56 785 #ifdef STM32F427X
ebrus 0:0a673c671a56 786 uint32_t RESERVED7; /*!< Reserved, 0x88 */
ebrus 0:0a673c671a56 787 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
ebrus 0:0a673c671a56 788 #endif /* STM32F427X */
ebrus 0:0a673c671a56 789
ebrus 0:0a673c671a56 790 } RCC_TypeDef;
ebrus 0:0a673c671a56 791
ebrus 0:0a673c671a56 792 /**
ebrus 0:0a673c671a56 793 * @brief Real-Time Clock
ebrus 0:0a673c671a56 794 */
ebrus 0:0a673c671a56 795
ebrus 0:0a673c671a56 796 typedef struct
ebrus 0:0a673c671a56 797 {
ebrus 0:0a673c671a56 798 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
ebrus 0:0a673c671a56 799 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
ebrus 0:0a673c671a56 800 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
ebrus 0:0a673c671a56 801 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
ebrus 0:0a673c671a56 802 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
ebrus 0:0a673c671a56 803 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
ebrus 0:0a673c671a56 804 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
ebrus 0:0a673c671a56 805 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
ebrus 0:0a673c671a56 806 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
ebrus 0:0a673c671a56 807 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
ebrus 0:0a673c671a56 808 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
ebrus 0:0a673c671a56 809 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
ebrus 0:0a673c671a56 810 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
ebrus 0:0a673c671a56 811 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
ebrus 0:0a673c671a56 812 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
ebrus 0:0a673c671a56 813 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
ebrus 0:0a673c671a56 814 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
ebrus 0:0a673c671a56 815 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
ebrus 0:0a673c671a56 816 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
ebrus 0:0a673c671a56 817 uint32_t RESERVED7; /*!< Reserved, 0x4C */
ebrus 0:0a673c671a56 818 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
ebrus 0:0a673c671a56 819 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
ebrus 0:0a673c671a56 820 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
ebrus 0:0a673c671a56 821 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
ebrus 0:0a673c671a56 822 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
ebrus 0:0a673c671a56 823 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
ebrus 0:0a673c671a56 824 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
ebrus 0:0a673c671a56 825 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
ebrus 0:0a673c671a56 826 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
ebrus 0:0a673c671a56 827 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
ebrus 0:0a673c671a56 828 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
ebrus 0:0a673c671a56 829 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
ebrus 0:0a673c671a56 830 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
ebrus 0:0a673c671a56 831 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
ebrus 0:0a673c671a56 832 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
ebrus 0:0a673c671a56 833 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
ebrus 0:0a673c671a56 834 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
ebrus 0:0a673c671a56 835 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
ebrus 0:0a673c671a56 836 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
ebrus 0:0a673c671a56 837 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
ebrus 0:0a673c671a56 838 } RTC_TypeDef;
ebrus 0:0a673c671a56 839
ebrus 0:0a673c671a56 840 /**
ebrus 0:0a673c671a56 841 * @brief SD host Interface
ebrus 0:0a673c671a56 842 */
ebrus 0:0a673c671a56 843
ebrus 0:0a673c671a56 844 typedef struct
ebrus 0:0a673c671a56 845 {
ebrus 0:0a673c671a56 846 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
ebrus 0:0a673c671a56 847 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
ebrus 0:0a673c671a56 848 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
ebrus 0:0a673c671a56 849 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
ebrus 0:0a673c671a56 850 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
ebrus 0:0a673c671a56 851 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
ebrus 0:0a673c671a56 852 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
ebrus 0:0a673c671a56 853 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
ebrus 0:0a673c671a56 854 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
ebrus 0:0a673c671a56 855 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
ebrus 0:0a673c671a56 856 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
ebrus 0:0a673c671a56 857 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
ebrus 0:0a673c671a56 858 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
ebrus 0:0a673c671a56 859 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
ebrus 0:0a673c671a56 860 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
ebrus 0:0a673c671a56 861 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
ebrus 0:0a673c671a56 862 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
ebrus 0:0a673c671a56 863 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
ebrus 0:0a673c671a56 864 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
ebrus 0:0a673c671a56 865 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
ebrus 0:0a673c671a56 866 } SDIO_TypeDef;
ebrus 0:0a673c671a56 867
ebrus 0:0a673c671a56 868 /**
ebrus 0:0a673c671a56 869 * @brief Serial Peripheral Interface
ebrus 0:0a673c671a56 870 */
ebrus 0:0a673c671a56 871
ebrus 0:0a673c671a56 872 typedef struct
ebrus 0:0a673c671a56 873 {
ebrus 0:0a673c671a56 874 __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
ebrus 0:0a673c671a56 875 uint16_t RESERVED0; /*!< Reserved, 0x02 */
ebrus 0:0a673c671a56 876 __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
ebrus 0:0a673c671a56 877 uint16_t RESERVED1; /*!< Reserved, 0x06 */
ebrus 0:0a673c671a56 878 __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
ebrus 0:0a673c671a56 879 uint16_t RESERVED2; /*!< Reserved, 0x0A */
ebrus 0:0a673c671a56 880 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
ebrus 0:0a673c671a56 881 uint16_t RESERVED3; /*!< Reserved, 0x0E */
ebrus 0:0a673c671a56 882 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
ebrus 0:0a673c671a56 883 uint16_t RESERVED4; /*!< Reserved, 0x12 */
ebrus 0:0a673c671a56 884 __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
ebrus 0:0a673c671a56 885 uint16_t RESERVED5; /*!< Reserved, 0x16 */
ebrus 0:0a673c671a56 886 __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
ebrus 0:0a673c671a56 887 uint16_t RESERVED6; /*!< Reserved, 0x1A */
ebrus 0:0a673c671a56 888 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
ebrus 0:0a673c671a56 889 uint16_t RESERVED7; /*!< Reserved, 0x1E */
ebrus 0:0a673c671a56 890 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
ebrus 0:0a673c671a56 891 uint16_t RESERVED8; /*!< Reserved, 0x22 */
ebrus 0:0a673c671a56 892 } SPI_TypeDef;
ebrus 0:0a673c671a56 893
ebrus 0:0a673c671a56 894 /**
ebrus 0:0a673c671a56 895 * @brief TIM
ebrus 0:0a673c671a56 896 */
ebrus 0:0a673c671a56 897
ebrus 0:0a673c671a56 898 typedef struct
ebrus 0:0a673c671a56 899 {
ebrus 0:0a673c671a56 900 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
ebrus 0:0a673c671a56 901 uint16_t RESERVED0; /*!< Reserved, 0x02 */
ebrus 0:0a673c671a56 902 __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
ebrus 0:0a673c671a56 903 uint16_t RESERVED1; /*!< Reserved, 0x06 */
ebrus 0:0a673c671a56 904 __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
ebrus 0:0a673c671a56 905 uint16_t RESERVED2; /*!< Reserved, 0x0A */
ebrus 0:0a673c671a56 906 __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
ebrus 0:0a673c671a56 907 uint16_t RESERVED3; /*!< Reserved, 0x0E */
ebrus 0:0a673c671a56 908 __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
ebrus 0:0a673c671a56 909 uint16_t RESERVED4; /*!< Reserved, 0x12 */
ebrus 0:0a673c671a56 910 __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
ebrus 0:0a673c671a56 911 uint16_t RESERVED5; /*!< Reserved, 0x16 */
ebrus 0:0a673c671a56 912 __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
ebrus 0:0a673c671a56 913 uint16_t RESERVED6; /*!< Reserved, 0x1A */
ebrus 0:0a673c671a56 914 __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
ebrus 0:0a673c671a56 915 uint16_t RESERVED7; /*!< Reserved, 0x1E */
ebrus 0:0a673c671a56 916 __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
ebrus 0:0a673c671a56 917 uint16_t RESERVED8; /*!< Reserved, 0x22 */
ebrus 0:0a673c671a56 918 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
ebrus 0:0a673c671a56 919 __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
ebrus 0:0a673c671a56 920 uint16_t RESERVED9; /*!< Reserved, 0x2A */
ebrus 0:0a673c671a56 921 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
ebrus 0:0a673c671a56 922 __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
ebrus 0:0a673c671a56 923 uint16_t RESERVED10; /*!< Reserved, 0x32 */
ebrus 0:0a673c671a56 924 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
ebrus 0:0a673c671a56 925 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
ebrus 0:0a673c671a56 926 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
ebrus 0:0a673c671a56 927 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
ebrus 0:0a673c671a56 928 __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
ebrus 0:0a673c671a56 929 uint16_t RESERVED11; /*!< Reserved, 0x46 */
ebrus 0:0a673c671a56 930 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
ebrus 0:0a673c671a56 931 uint16_t RESERVED12; /*!< Reserved, 0x4A */
ebrus 0:0a673c671a56 932 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
ebrus 0:0a673c671a56 933 uint16_t RESERVED13; /*!< Reserved, 0x4E */
ebrus 0:0a673c671a56 934 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
ebrus 0:0a673c671a56 935 uint16_t RESERVED14; /*!< Reserved, 0x52 */
ebrus 0:0a673c671a56 936 } TIM_TypeDef;
ebrus 0:0a673c671a56 937
ebrus 0:0a673c671a56 938 /**
ebrus 0:0a673c671a56 939 * @brief Universal Synchronous Asynchronous Receiver Transmitter
ebrus 0:0a673c671a56 940 */
ebrus 0:0a673c671a56 941
ebrus 0:0a673c671a56 942 typedef struct
ebrus 0:0a673c671a56 943 {
ebrus 0:0a673c671a56 944 __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
ebrus 0:0a673c671a56 945 uint16_t RESERVED0; /*!< Reserved, 0x02 */
ebrus 0:0a673c671a56 946 __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
ebrus 0:0a673c671a56 947 uint16_t RESERVED1; /*!< Reserved, 0x06 */
ebrus 0:0a673c671a56 948 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
ebrus 0:0a673c671a56 949 uint16_t RESERVED2; /*!< Reserved, 0x0A */
ebrus 0:0a673c671a56 950 __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
ebrus 0:0a673c671a56 951 uint16_t RESERVED3; /*!< Reserved, 0x0E */
ebrus 0:0a673c671a56 952 __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
ebrus 0:0a673c671a56 953 uint16_t RESERVED4; /*!< Reserved, 0x12 */
ebrus 0:0a673c671a56 954 __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
ebrus 0:0a673c671a56 955 uint16_t RESERVED5; /*!< Reserved, 0x16 */
ebrus 0:0a673c671a56 956 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
ebrus 0:0a673c671a56 957 uint16_t RESERVED6; /*!< Reserved, 0x1A */
ebrus 0:0a673c671a56 958 } USART_TypeDef;
ebrus 0:0a673c671a56 959
ebrus 0:0a673c671a56 960 /**
ebrus 0:0a673c671a56 961 * @brief Window WATCHDOG
ebrus 0:0a673c671a56 962 */
ebrus 0:0a673c671a56 963
ebrus 0:0a673c671a56 964 typedef struct
ebrus 0:0a673c671a56 965 {
ebrus 0:0a673c671a56 966 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
ebrus 0:0a673c671a56 967 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
ebrus 0:0a673c671a56 968 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
ebrus 0:0a673c671a56 969 } WWDG_TypeDef;
ebrus 0:0a673c671a56 970
ebrus 0:0a673c671a56 971 /**
ebrus 0:0a673c671a56 972 * @brief Crypto Processor
ebrus 0:0a673c671a56 973 */
ebrus 0:0a673c671a56 974
ebrus 0:0a673c671a56 975 typedef struct
ebrus 0:0a673c671a56 976 {
ebrus 0:0a673c671a56 977 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
ebrus 0:0a673c671a56 978 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
ebrus 0:0a673c671a56 979 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
ebrus 0:0a673c671a56 980 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
ebrus 0:0a673c671a56 981 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
ebrus 0:0a673c671a56 982 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
ebrus 0:0a673c671a56 983 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
ebrus 0:0a673c671a56 984 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
ebrus 0:0a673c671a56 985 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
ebrus 0:0a673c671a56 986 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
ebrus 0:0a673c671a56 987 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
ebrus 0:0a673c671a56 988 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
ebrus 0:0a673c671a56 989 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
ebrus 0:0a673c671a56 990 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
ebrus 0:0a673c671a56 991 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
ebrus 0:0a673c671a56 992 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
ebrus 0:0a673c671a56 993 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
ebrus 0:0a673c671a56 994 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
ebrus 0:0a673c671a56 995 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
ebrus 0:0a673c671a56 996 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
ebrus 0:0a673c671a56 997 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
ebrus 0:0a673c671a56 998 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
ebrus 0:0a673c671a56 999 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
ebrus 0:0a673c671a56 1000 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
ebrus 0:0a673c671a56 1001 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
ebrus 0:0a673c671a56 1002 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
ebrus 0:0a673c671a56 1003 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
ebrus 0:0a673c671a56 1004 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
ebrus 0:0a673c671a56 1005 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
ebrus 0:0a673c671a56 1006 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
ebrus 0:0a673c671a56 1007 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
ebrus 0:0a673c671a56 1008 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
ebrus 0:0a673c671a56 1009 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
ebrus 0:0a673c671a56 1010 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
ebrus 0:0a673c671a56 1011 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
ebrus 0:0a673c671a56 1012 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
ebrus 0:0a673c671a56 1013 } CRYP_TypeDef;
ebrus 0:0a673c671a56 1014
ebrus 0:0a673c671a56 1015 /**
ebrus 0:0a673c671a56 1016 * @brief HASH
ebrus 0:0a673c671a56 1017 */
ebrus 0:0a673c671a56 1018
ebrus 0:0a673c671a56 1019 typedef struct
ebrus 0:0a673c671a56 1020 {
ebrus 0:0a673c671a56 1021 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
ebrus 0:0a673c671a56 1022 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
ebrus 0:0a673c671a56 1023 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
ebrus 0:0a673c671a56 1024 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
ebrus 0:0a673c671a56 1025 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
ebrus 0:0a673c671a56 1026 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
ebrus 0:0a673c671a56 1027 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
ebrus 0:0a673c671a56 1028 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
ebrus 0:0a673c671a56 1029 } HASH_TypeDef;
ebrus 0:0a673c671a56 1030
ebrus 0:0a673c671a56 1031 /**
ebrus 0:0a673c671a56 1032 * @brief HASH_DIGEST
ebrus 0:0a673c671a56 1033 */
ebrus 0:0a673c671a56 1034
ebrus 0:0a673c671a56 1035 typedef struct
ebrus 0:0a673c671a56 1036 {
ebrus 0:0a673c671a56 1037 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
ebrus 0:0a673c671a56 1038 } HASH_DIGEST_TypeDef;
ebrus 0:0a673c671a56 1039
ebrus 0:0a673c671a56 1040 /**
ebrus 0:0a673c671a56 1041 * @brief RNG
ebrus 0:0a673c671a56 1042 */
ebrus 0:0a673c671a56 1043
ebrus 0:0a673c671a56 1044 typedef struct
ebrus 0:0a673c671a56 1045 {
ebrus 0:0a673c671a56 1046 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
ebrus 0:0a673c671a56 1047 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
ebrus 0:0a673c671a56 1048 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
ebrus 0:0a673c671a56 1049 } RNG_TypeDef;
ebrus 0:0a673c671a56 1050
ebrus 0:0a673c671a56 1051 /**
ebrus 0:0a673c671a56 1052 * @}
ebrus 0:0a673c671a56 1053 */
ebrus 0:0a673c671a56 1054
ebrus 0:0a673c671a56 1055 /** @addtogroup Peripheral_memory_map
ebrus 0:0a673c671a56 1056 * @{
ebrus 0:0a673c671a56 1057 */
ebrus 0:0a673c671a56 1058 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
ebrus 0:0a673c671a56 1059 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
ebrus 0:0a673c671a56 1060 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
ebrus 0:0a673c671a56 1061 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
ebrus 0:0a673c671a56 1062 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
ebrus 0:0a673c671a56 1063 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
ebrus 0:0a673c671a56 1064 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
ebrus 0:0a673c671a56 1065 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
ebrus 0:0a673c671a56 1066
ebrus 0:0a673c671a56 1067 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
ebrus 0:0a673c671a56 1068 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
ebrus 0:0a673c671a56 1069 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
ebrus 0:0a673c671a56 1070 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
ebrus 0:0a673c671a56 1071 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
ebrus 0:0a673c671a56 1072 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
ebrus 0:0a673c671a56 1073
ebrus 0:0a673c671a56 1074 /* Legacy defines */
ebrus 0:0a673c671a56 1075 #define SRAM_BASE SRAM1_BASE
ebrus 0:0a673c671a56 1076 #define SRAM_BB_BASE SRAM1_BB_BASE
ebrus 0:0a673c671a56 1077
ebrus 0:0a673c671a56 1078 /*!< Peripheral memory map */
ebrus 0:0a673c671a56 1079 #define APB1PERIPH_BASE PERIPH_BASE
ebrus 0:0a673c671a56 1080 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
ebrus 0:0a673c671a56 1081 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
ebrus 0:0a673c671a56 1082 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
ebrus 0:0a673c671a56 1083
ebrus 0:0a673c671a56 1084 /*!< APB1 peripherals */
ebrus 0:0a673c671a56 1085 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
ebrus 0:0a673c671a56 1086 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
ebrus 0:0a673c671a56 1087 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
ebrus 0:0a673c671a56 1088 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
ebrus 0:0a673c671a56 1089 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
ebrus 0:0a673c671a56 1090 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
ebrus 0:0a673c671a56 1091 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
ebrus 0:0a673c671a56 1092 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
ebrus 0:0a673c671a56 1093 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
ebrus 0:0a673c671a56 1094 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
ebrus 0:0a673c671a56 1095 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
ebrus 0:0a673c671a56 1096 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
ebrus 0:0a673c671a56 1097 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
ebrus 0:0a673c671a56 1098 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
ebrus 0:0a673c671a56 1099 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
ebrus 0:0a673c671a56 1100 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
ebrus 0:0a673c671a56 1101 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
ebrus 0:0a673c671a56 1102 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
ebrus 0:0a673c671a56 1103 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
ebrus 0:0a673c671a56 1104 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
ebrus 0:0a673c671a56 1105 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
ebrus 0:0a673c671a56 1106 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
ebrus 0:0a673c671a56 1107 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
ebrus 0:0a673c671a56 1108 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
ebrus 0:0a673c671a56 1109 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
ebrus 0:0a673c671a56 1110 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
ebrus 0:0a673c671a56 1111 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
ebrus 0:0a673c671a56 1112 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
ebrus 0:0a673c671a56 1113 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
ebrus 0:0a673c671a56 1114
ebrus 0:0a673c671a56 1115 /*!< APB2 peripherals */
ebrus 0:0a673c671a56 1116 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
ebrus 0:0a673c671a56 1117 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
ebrus 0:0a673c671a56 1118 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
ebrus 0:0a673c671a56 1119 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
ebrus 0:0a673c671a56 1120 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
ebrus 0:0a673c671a56 1121 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
ebrus 0:0a673c671a56 1122 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
ebrus 0:0a673c671a56 1123 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
ebrus 0:0a673c671a56 1124 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
ebrus 0:0a673c671a56 1125 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
ebrus 0:0a673c671a56 1126 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
ebrus 0:0a673c671a56 1127 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
ebrus 0:0a673c671a56 1128 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
ebrus 0:0a673c671a56 1129 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
ebrus 0:0a673c671a56 1130 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
ebrus 0:0a673c671a56 1131 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
ebrus 0:0a673c671a56 1132 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
ebrus 0:0a673c671a56 1133 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
ebrus 0:0a673c671a56 1134
ebrus 0:0a673c671a56 1135 /*!< AHB1 peripherals */
ebrus 0:0a673c671a56 1136 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
ebrus 0:0a673c671a56 1137 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
ebrus 0:0a673c671a56 1138 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
ebrus 0:0a673c671a56 1139 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
ebrus 0:0a673c671a56 1140 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
ebrus 0:0a673c671a56 1141 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
ebrus 0:0a673c671a56 1142 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
ebrus 0:0a673c671a56 1143 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
ebrus 0:0a673c671a56 1144 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
ebrus 0:0a673c671a56 1145
ebrus 0:0a673c671a56 1146 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
ebrus 0:0a673c671a56 1147 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
ebrus 0:0a673c671a56 1148 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
ebrus 0:0a673c671a56 1149 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
ebrus 0:0a673c671a56 1150 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
ebrus 0:0a673c671a56 1151 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
ebrus 0:0a673c671a56 1152 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
ebrus 0:0a673c671a56 1153 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
ebrus 0:0a673c671a56 1154 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
ebrus 0:0a673c671a56 1155 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
ebrus 0:0a673c671a56 1156 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
ebrus 0:0a673c671a56 1157 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
ebrus 0:0a673c671a56 1158 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
ebrus 0:0a673c671a56 1159 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
ebrus 0:0a673c671a56 1160 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
ebrus 0:0a673c671a56 1161 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
ebrus 0:0a673c671a56 1162 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
ebrus 0:0a673c671a56 1163 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
ebrus 0:0a673c671a56 1164 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
ebrus 0:0a673c671a56 1165 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
ebrus 0:0a673c671a56 1166 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
ebrus 0:0a673c671a56 1167 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
ebrus 0:0a673c671a56 1168 #define ETH_MAC_BASE (ETH_BASE)
ebrus 0:0a673c671a56 1169 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
ebrus 0:0a673c671a56 1170 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
ebrus 0:0a673c671a56 1171 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
ebrus 0:0a673c671a56 1172
ebrus 0:0a673c671a56 1173 /*!< AHB2 peripherals */
ebrus 0:0a673c671a56 1174 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
ebrus 0:0a673c671a56 1175 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
ebrus 0:0a673c671a56 1176 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
ebrus 0:0a673c671a56 1177 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
ebrus 0:0a673c671a56 1178 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
ebrus 0:0a673c671a56 1179
ebrus 0:0a673c671a56 1180 /*!< FSMC Bankx registers base address */
ebrus 0:0a673c671a56 1181 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
ebrus 0:0a673c671a56 1182 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
ebrus 0:0a673c671a56 1183 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
ebrus 0:0a673c671a56 1184 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
ebrus 0:0a673c671a56 1185 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
ebrus 0:0a673c671a56 1186
ebrus 0:0a673c671a56 1187 /* Debug MCU registers base address */
ebrus 0:0a673c671a56 1188 #define DBGMCU_BASE ((uint32_t )0xE0042000)
ebrus 0:0a673c671a56 1189
ebrus 0:0a673c671a56 1190 /**
ebrus 0:0a673c671a56 1191 * @}
ebrus 0:0a673c671a56 1192 */
ebrus 0:0a673c671a56 1193
ebrus 0:0a673c671a56 1194 /** @addtogroup Peripheral_declaration
ebrus 0:0a673c671a56 1195 * @{
ebrus 0:0a673c671a56 1196 */
ebrus 0:0a673c671a56 1197 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
ebrus 0:0a673c671a56 1198 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
ebrus 0:0a673c671a56 1199 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
ebrus 0:0a673c671a56 1200 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
ebrus 0:0a673c671a56 1201 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
ebrus 0:0a673c671a56 1202 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
ebrus 0:0a673c671a56 1203 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
ebrus 0:0a673c671a56 1204 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
ebrus 0:0a673c671a56 1205 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
ebrus 0:0a673c671a56 1206 #define RTC ((RTC_TypeDef *) RTC_BASE)
ebrus 0:0a673c671a56 1207 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
ebrus 0:0a673c671a56 1208 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
ebrus 0:0a673c671a56 1209 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
ebrus 0:0a673c671a56 1210 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
ebrus 0:0a673c671a56 1211 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
ebrus 0:0a673c671a56 1212 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
ebrus 0:0a673c671a56 1213 #define USART2 ((USART_TypeDef *) USART2_BASE)
ebrus 0:0a673c671a56 1214 #define USART3 ((USART_TypeDef *) USART3_BASE)
ebrus 0:0a673c671a56 1215 #define UART4 ((USART_TypeDef *) UART4_BASE)
ebrus 0:0a673c671a56 1216 #define UART5 ((USART_TypeDef *) UART5_BASE)
ebrus 0:0a673c671a56 1217 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
ebrus 0:0a673c671a56 1218 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
ebrus 0:0a673c671a56 1219 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
ebrus 0:0a673c671a56 1220 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
ebrus 0:0a673c671a56 1221 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
ebrus 0:0a673c671a56 1222 #define PWR ((PWR_TypeDef *) PWR_BASE)
ebrus 0:0a673c671a56 1223 #define DAC ((DAC_TypeDef *) DAC_BASE)
ebrus 0:0a673c671a56 1224 #define UART7 ((USART_TypeDef *) UART7_BASE)
ebrus 0:0a673c671a56 1225 #define UART8 ((USART_TypeDef *) UART8_BASE)
ebrus 0:0a673c671a56 1226 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
ebrus 0:0a673c671a56 1227 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
ebrus 0:0a673c671a56 1228 #define USART1 ((USART_TypeDef *) USART1_BASE)
ebrus 0:0a673c671a56 1229 #define USART6 ((USART_TypeDef *) USART6_BASE)
ebrus 0:0a673c671a56 1230 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
ebrus 0:0a673c671a56 1231 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
ebrus 0:0a673c671a56 1232 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
ebrus 0:0a673c671a56 1233 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
ebrus 0:0a673c671a56 1234 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
ebrus 0:0a673c671a56 1235 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
ebrus 0:0a673c671a56 1236 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
ebrus 0:0a673c671a56 1237 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
ebrus 0:0a673c671a56 1238 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
ebrus 0:0a673c671a56 1239 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
ebrus 0:0a673c671a56 1240 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
ebrus 0:0a673c671a56 1241 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
ebrus 0:0a673c671a56 1242 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
ebrus 0:0a673c671a56 1243 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
ebrus 0:0a673c671a56 1244
ebrus 0:0a673c671a56 1245 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
ebrus 0:0a673c671a56 1246 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
ebrus 0:0a673c671a56 1247 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
ebrus 0:0a673c671a56 1248 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
ebrus 0:0a673c671a56 1249 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
ebrus 0:0a673c671a56 1250 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
ebrus 0:0a673c671a56 1251 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
ebrus 0:0a673c671a56 1252 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
ebrus 0:0a673c671a56 1253 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
ebrus 0:0a673c671a56 1254
ebrus 0:0a673c671a56 1255 #define CRC ((CRC_TypeDef *) CRC_BASE)
ebrus 0:0a673c671a56 1256 #define RCC ((RCC_TypeDef *) RCC_BASE)
ebrus 0:0a673c671a56 1257 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
ebrus 0:0a673c671a56 1258 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
ebrus 0:0a673c671a56 1259 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
ebrus 0:0a673c671a56 1260 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
ebrus 0:0a673c671a56 1261 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
ebrus 0:0a673c671a56 1262 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
ebrus 0:0a673c671a56 1263 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
ebrus 0:0a673c671a56 1264 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
ebrus 0:0a673c671a56 1265 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
ebrus 0:0a673c671a56 1266 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
ebrus 0:0a673c671a56 1267 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
ebrus 0:0a673c671a56 1268 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
ebrus 0:0a673c671a56 1269 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
ebrus 0:0a673c671a56 1270 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
ebrus 0:0a673c671a56 1271 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
ebrus 0:0a673c671a56 1272 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
ebrus 0:0a673c671a56 1273 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
ebrus 0:0a673c671a56 1274 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
ebrus 0:0a673c671a56 1275 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
ebrus 0:0a673c671a56 1276 #define ETH ((ETH_TypeDef *) ETH_BASE)
ebrus 0:0a673c671a56 1277 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
ebrus 0:0a673c671a56 1278 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
ebrus 0:0a673c671a56 1279 #define HASH ((HASH_TypeDef *) HASH_BASE)
ebrus 0:0a673c671a56 1280 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
ebrus 0:0a673c671a56 1281 #define RNG ((RNG_TypeDef *) RNG_BASE)
ebrus 0:0a673c671a56 1282 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
ebrus 0:0a673c671a56 1283 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
ebrus 0:0a673c671a56 1284 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
ebrus 0:0a673c671a56 1285 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
ebrus 0:0a673c671a56 1286 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
ebrus 0:0a673c671a56 1287 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
ebrus 0:0a673c671a56 1288
ebrus 0:0a673c671a56 1289 /**
ebrus 0:0a673c671a56 1290 * @}
ebrus 0:0a673c671a56 1291 */
ebrus 0:0a673c671a56 1292
ebrus 0:0a673c671a56 1293 /** @addtogroup Exported_constants
ebrus 0:0a673c671a56 1294 * @{
ebrus 0:0a673c671a56 1295 */
ebrus 0:0a673c671a56 1296
ebrus 0:0a673c671a56 1297 /** @addtogroup Peripheral_Registers_Bits_Definition
ebrus 0:0a673c671a56 1298 * @{
ebrus 0:0a673c671a56 1299 */
ebrus 0:0a673c671a56 1300
ebrus 0:0a673c671a56 1301 /******************************************************************************/
ebrus 0:0a673c671a56 1302 /* Peripheral Registers_Bits_Definition */
ebrus 0:0a673c671a56 1303 /******************************************************************************/
ebrus 0:0a673c671a56 1304
ebrus 0:0a673c671a56 1305 /******************************************************************************/
ebrus 0:0a673c671a56 1306 /* */
ebrus 0:0a673c671a56 1307 /* Analog to Digital Converter */
ebrus 0:0a673c671a56 1308 /* */
ebrus 0:0a673c671a56 1309 /******************************************************************************/
ebrus 0:0a673c671a56 1310 /******************** Bit definition for ADC_SR register ********************/
ebrus 0:0a673c671a56 1311 #define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
ebrus 0:0a673c671a56 1312 #define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
ebrus 0:0a673c671a56 1313 #define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
ebrus 0:0a673c671a56 1314 #define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
ebrus 0:0a673c671a56 1315 #define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
ebrus 0:0a673c671a56 1316 #define ADC_SR_OVR ((uint8_t)0x20) /*!<Overrun flag */
ebrus 0:0a673c671a56 1317
ebrus 0:0a673c671a56 1318 /******************* Bit definition for ADC_CR1 register ********************/
ebrus 0:0a673c671a56 1319 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
ebrus 0:0a673c671a56 1320 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 1321 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 1322 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 1323 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 1324 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 1325 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
ebrus 0:0a673c671a56 1326 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
ebrus 0:0a673c671a56 1327 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
ebrus 0:0a673c671a56 1328 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
ebrus 0:0a673c671a56 1329 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
ebrus 0:0a673c671a56 1330 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
ebrus 0:0a673c671a56 1331 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
ebrus 0:0a673c671a56 1332 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
ebrus 0:0a673c671a56 1333 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
ebrus 0:0a673c671a56 1334 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1335 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1336 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1337 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
ebrus 0:0a673c671a56 1338 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
ebrus 0:0a673c671a56 1339 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
ebrus 0:0a673c671a56 1340 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1341 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1342 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
ebrus 0:0a673c671a56 1343
ebrus 0:0a673c671a56 1344 /******************* Bit definition for ADC_CR2 register ********************/
ebrus 0:0a673c671a56 1345 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
ebrus 0:0a673c671a56 1346 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
ebrus 0:0a673c671a56 1347 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
ebrus 0:0a673c671a56 1348 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
ebrus 0:0a673c671a56 1349 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
ebrus 0:0a673c671a56 1350 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
ebrus 0:0a673c671a56 1351 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
ebrus 0:0a673c671a56 1352 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1353 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1354 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1355 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1356 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
ebrus 0:0a673c671a56 1357 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1358 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1359 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
ebrus 0:0a673c671a56 1360 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
ebrus 0:0a673c671a56 1361 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1362 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1363 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1364 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1365 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
ebrus 0:0a673c671a56 1366 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1367 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1368 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
ebrus 0:0a673c671a56 1369
ebrus 0:0a673c671a56 1370 /****************** Bit definition for ADC_SMPR1 register *******************/
ebrus 0:0a673c671a56 1371 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
ebrus 0:0a673c671a56 1372 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 1373 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 1374 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 1375 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
ebrus 0:0a673c671a56 1376 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
ebrus 0:0a673c671a56 1377 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
ebrus 0:0a673c671a56 1378 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
ebrus 0:0a673c671a56 1379 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
ebrus 0:0a673c671a56 1380 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
ebrus 0:0a673c671a56 1381 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
ebrus 0:0a673c671a56 1382 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
ebrus 0:0a673c671a56 1383 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
ebrus 0:0a673c671a56 1384 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
ebrus 0:0a673c671a56 1385 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
ebrus 0:0a673c671a56 1386 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
ebrus 0:0a673c671a56 1387 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
ebrus 0:0a673c671a56 1388 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1389 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1390 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1391 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
ebrus 0:0a673c671a56 1392 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1393 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1394 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1395 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
ebrus 0:0a673c671a56 1396 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1397 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1398 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1399 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
ebrus 0:0a673c671a56 1400 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1401 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1402 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1403 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
ebrus 0:0a673c671a56 1404 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1405 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1406 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1407
ebrus 0:0a673c671a56 1408 /****************** Bit definition for ADC_SMPR2 register *******************/
ebrus 0:0a673c671a56 1409 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
ebrus 0:0a673c671a56 1410 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 1411 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 1412 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 1413 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
ebrus 0:0a673c671a56 1414 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
ebrus 0:0a673c671a56 1415 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
ebrus 0:0a673c671a56 1416 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
ebrus 0:0a673c671a56 1417 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
ebrus 0:0a673c671a56 1418 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
ebrus 0:0a673c671a56 1419 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
ebrus 0:0a673c671a56 1420 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
ebrus 0:0a673c671a56 1421 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
ebrus 0:0a673c671a56 1422 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
ebrus 0:0a673c671a56 1423 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
ebrus 0:0a673c671a56 1424 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
ebrus 0:0a673c671a56 1425 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
ebrus 0:0a673c671a56 1426 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1427 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1428 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1429 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
ebrus 0:0a673c671a56 1430 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1431 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1432 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1433 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
ebrus 0:0a673c671a56 1434 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1435 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1436 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1437 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
ebrus 0:0a673c671a56 1438 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1439 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1440 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1441 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
ebrus 0:0a673c671a56 1442 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1443 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1444 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1445 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
ebrus 0:0a673c671a56 1446 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1447 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1448 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1449
ebrus 0:0a673c671a56 1450 /****************** Bit definition for ADC_JOFR1 register *******************/
ebrus 0:0a673c671a56 1451 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
ebrus 0:0a673c671a56 1452
ebrus 0:0a673c671a56 1453 /****************** Bit definition for ADC_JOFR2 register *******************/
ebrus 0:0a673c671a56 1454 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
ebrus 0:0a673c671a56 1455
ebrus 0:0a673c671a56 1456 /****************** Bit definition for ADC_JOFR3 register *******************/
ebrus 0:0a673c671a56 1457 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
ebrus 0:0a673c671a56 1458
ebrus 0:0a673c671a56 1459 /****************** Bit definition for ADC_JOFR4 register *******************/
ebrus 0:0a673c671a56 1460 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
ebrus 0:0a673c671a56 1461
ebrus 0:0a673c671a56 1462 /******************* Bit definition for ADC_HTR register ********************/
ebrus 0:0a673c671a56 1463 #define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
ebrus 0:0a673c671a56 1464
ebrus 0:0a673c671a56 1465 /******************* Bit definition for ADC_LTR register ********************/
ebrus 0:0a673c671a56 1466 #define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
ebrus 0:0a673c671a56 1467
ebrus 0:0a673c671a56 1468 /******************* Bit definition for ADC_SQR1 register *******************/
ebrus 0:0a673c671a56 1469 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
ebrus 0:0a673c671a56 1470 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 1471 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 1472 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 1473 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 1474 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 1475 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
ebrus 0:0a673c671a56 1476 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
ebrus 0:0a673c671a56 1477 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
ebrus 0:0a673c671a56 1478 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
ebrus 0:0a673c671a56 1479 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
ebrus 0:0a673c671a56 1480 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
ebrus 0:0a673c671a56 1481 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
ebrus 0:0a673c671a56 1482 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
ebrus 0:0a673c671a56 1483 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
ebrus 0:0a673c671a56 1484 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1485 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1486 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
ebrus 0:0a673c671a56 1487 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
ebrus 0:0a673c671a56 1488 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1489 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1490 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1491 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1492 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
ebrus 0:0a673c671a56 1493 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
ebrus 0:0a673c671a56 1494 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1495 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1496 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1497 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1498
ebrus 0:0a673c671a56 1499 /******************* Bit definition for ADC_SQR2 register *******************/
ebrus 0:0a673c671a56 1500 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
ebrus 0:0a673c671a56 1501 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 1502 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 1503 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 1504 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 1505 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 1506 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
ebrus 0:0a673c671a56 1507 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
ebrus 0:0a673c671a56 1508 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
ebrus 0:0a673c671a56 1509 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
ebrus 0:0a673c671a56 1510 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
ebrus 0:0a673c671a56 1511 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
ebrus 0:0a673c671a56 1512 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
ebrus 0:0a673c671a56 1513 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
ebrus 0:0a673c671a56 1514 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
ebrus 0:0a673c671a56 1515 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1516 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1517 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
ebrus 0:0a673c671a56 1518 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
ebrus 0:0a673c671a56 1519 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1520 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1521 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1522 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1523 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
ebrus 0:0a673c671a56 1524 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
ebrus 0:0a673c671a56 1525 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1526 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1527 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1528 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1529 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
ebrus 0:0a673c671a56 1530 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
ebrus 0:0a673c671a56 1531 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1532 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1533 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1534 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1535 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
ebrus 0:0a673c671a56 1536
ebrus 0:0a673c671a56 1537 /******************* Bit definition for ADC_SQR3 register *******************/
ebrus 0:0a673c671a56 1538 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
ebrus 0:0a673c671a56 1539 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 1540 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 1541 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 1542 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 1543 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 1544 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
ebrus 0:0a673c671a56 1545 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
ebrus 0:0a673c671a56 1546 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
ebrus 0:0a673c671a56 1547 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
ebrus 0:0a673c671a56 1548 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
ebrus 0:0a673c671a56 1549 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
ebrus 0:0a673c671a56 1550 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
ebrus 0:0a673c671a56 1551 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
ebrus 0:0a673c671a56 1552 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
ebrus 0:0a673c671a56 1553 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1554 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1555 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
ebrus 0:0a673c671a56 1556 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
ebrus 0:0a673c671a56 1557 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1558 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1559 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1560 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1561 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
ebrus 0:0a673c671a56 1562 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
ebrus 0:0a673c671a56 1563 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1564 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1565 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1566 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1567 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
ebrus 0:0a673c671a56 1568 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
ebrus 0:0a673c671a56 1569 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1570 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1571 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1572 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1573 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
ebrus 0:0a673c671a56 1574
ebrus 0:0a673c671a56 1575 /******************* Bit definition for ADC_JSQR register *******************/
ebrus 0:0a673c671a56 1576 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
ebrus 0:0a673c671a56 1577 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 1578 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 1579 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 1580 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 1581 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 1582 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
ebrus 0:0a673c671a56 1583 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
ebrus 0:0a673c671a56 1584 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
ebrus 0:0a673c671a56 1585 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
ebrus 0:0a673c671a56 1586 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
ebrus 0:0a673c671a56 1587 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
ebrus 0:0a673c671a56 1588 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
ebrus 0:0a673c671a56 1589 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
ebrus 0:0a673c671a56 1590 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
ebrus 0:0a673c671a56 1591 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1592 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1593 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
ebrus 0:0a673c671a56 1594 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
ebrus 0:0a673c671a56 1595 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1596 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1597 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
ebrus 0:0a673c671a56 1598 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
ebrus 0:0a673c671a56 1599 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
ebrus 0:0a673c671a56 1600 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
ebrus 0:0a673c671a56 1601 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1602 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1603
ebrus 0:0a673c671a56 1604 /******************* Bit definition for ADC_JDR1 register *******************/
ebrus 0:0a673c671a56 1605 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
ebrus 0:0a673c671a56 1606
ebrus 0:0a673c671a56 1607 /******************* Bit definition for ADC_JDR2 register *******************/
ebrus 0:0a673c671a56 1608 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
ebrus 0:0a673c671a56 1609
ebrus 0:0a673c671a56 1610 /******************* Bit definition for ADC_JDR3 register *******************/
ebrus 0:0a673c671a56 1611 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
ebrus 0:0a673c671a56 1612
ebrus 0:0a673c671a56 1613 /******************* Bit definition for ADC_JDR4 register *******************/
ebrus 0:0a673c671a56 1614 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
ebrus 0:0a673c671a56 1615
ebrus 0:0a673c671a56 1616 /******************** Bit definition for ADC_DR register ********************/
ebrus 0:0a673c671a56 1617 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
ebrus 0:0a673c671a56 1618 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
ebrus 0:0a673c671a56 1619
ebrus 0:0a673c671a56 1620 /******************* Bit definition for ADC_CSR register ********************/
ebrus 0:0a673c671a56 1621 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
ebrus 0:0a673c671a56 1622 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
ebrus 0:0a673c671a56 1623 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
ebrus 0:0a673c671a56 1624 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
ebrus 0:0a673c671a56 1625 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
ebrus 0:0a673c671a56 1626 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
ebrus 0:0a673c671a56 1627 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
ebrus 0:0a673c671a56 1628 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
ebrus 0:0a673c671a56 1629 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
ebrus 0:0a673c671a56 1630 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
ebrus 0:0a673c671a56 1631 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
ebrus 0:0a673c671a56 1632 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
ebrus 0:0a673c671a56 1633 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
ebrus 0:0a673c671a56 1634 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
ebrus 0:0a673c671a56 1635 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
ebrus 0:0a673c671a56 1636 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
ebrus 0:0a673c671a56 1637 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
ebrus 0:0a673c671a56 1638 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
ebrus 0:0a673c671a56 1639
ebrus 0:0a673c671a56 1640 /******************* Bit definition for ADC_CCR register ********************/
ebrus 0:0a673c671a56 1641 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
ebrus 0:0a673c671a56 1642 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 1643 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 1644 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 1645 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 1646 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 1647 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
ebrus 0:0a673c671a56 1648 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 1649 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 1650 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 1651 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 1652 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
ebrus 0:0a673c671a56 1653 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
ebrus 0:0a673c671a56 1654 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1655 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1656 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
ebrus 0:0a673c671a56 1657 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 1658 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 1659 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
ebrus 0:0a673c671a56 1660 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
ebrus 0:0a673c671a56 1661
ebrus 0:0a673c671a56 1662 /******************* Bit definition for ADC_CDR register ********************/
ebrus 0:0a673c671a56 1663 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
ebrus 0:0a673c671a56 1664 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
ebrus 0:0a673c671a56 1665
ebrus 0:0a673c671a56 1666 /******************************************************************************/
ebrus 0:0a673c671a56 1667 /* */
ebrus 0:0a673c671a56 1668 /* Controller Area Network */
ebrus 0:0a673c671a56 1669 /* */
ebrus 0:0a673c671a56 1670 /******************************************************************************/
ebrus 0:0a673c671a56 1671 /*!<CAN control and status registers */
ebrus 0:0a673c671a56 1672 /******************* Bit definition for CAN_MCR register ********************/
ebrus 0:0a673c671a56 1673 #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
ebrus 0:0a673c671a56 1674 #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
ebrus 0:0a673c671a56 1675 #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
ebrus 0:0a673c671a56 1676 #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
ebrus 0:0a673c671a56 1677 #define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
ebrus 0:0a673c671a56 1678 #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
ebrus 0:0a673c671a56 1679 #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
ebrus 0:0a673c671a56 1680 #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
ebrus 0:0a673c671a56 1681 #define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
ebrus 0:0a673c671a56 1682
ebrus 0:0a673c671a56 1683 /******************* Bit definition for CAN_MSR register ********************/
ebrus 0:0a673c671a56 1684 #define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
ebrus 0:0a673c671a56 1685 #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
ebrus 0:0a673c671a56 1686 #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
ebrus 0:0a673c671a56 1687 #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
ebrus 0:0a673c671a56 1688 #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
ebrus 0:0a673c671a56 1689 #define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
ebrus 0:0a673c671a56 1690 #define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
ebrus 0:0a673c671a56 1691 #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
ebrus 0:0a673c671a56 1692 #define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
ebrus 0:0a673c671a56 1693
ebrus 0:0a673c671a56 1694 /******************* Bit definition for CAN_TSR register ********************/
ebrus 0:0a673c671a56 1695 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
ebrus 0:0a673c671a56 1696 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
ebrus 0:0a673c671a56 1697 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
ebrus 0:0a673c671a56 1698 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
ebrus 0:0a673c671a56 1699 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
ebrus 0:0a673c671a56 1700 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
ebrus 0:0a673c671a56 1701 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
ebrus 0:0a673c671a56 1702 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
ebrus 0:0a673c671a56 1703 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
ebrus 0:0a673c671a56 1704 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
ebrus 0:0a673c671a56 1705 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
ebrus 0:0a673c671a56 1706 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
ebrus 0:0a673c671a56 1707 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
ebrus 0:0a673c671a56 1708 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
ebrus 0:0a673c671a56 1709 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
ebrus 0:0a673c671a56 1710 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
ebrus 0:0a673c671a56 1711
ebrus 0:0a673c671a56 1712 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
ebrus 0:0a673c671a56 1713 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
ebrus 0:0a673c671a56 1714 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
ebrus 0:0a673c671a56 1715 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
ebrus 0:0a673c671a56 1716
ebrus 0:0a673c671a56 1717 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
ebrus 0:0a673c671a56 1718 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
ebrus 0:0a673c671a56 1719 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
ebrus 0:0a673c671a56 1720 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
ebrus 0:0a673c671a56 1721
ebrus 0:0a673c671a56 1722 /******************* Bit definition for CAN_RF0R register *******************/
ebrus 0:0a673c671a56 1723 #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
ebrus 0:0a673c671a56 1724 #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
ebrus 0:0a673c671a56 1725 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
ebrus 0:0a673c671a56 1726 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
ebrus 0:0a673c671a56 1727
ebrus 0:0a673c671a56 1728 /******************* Bit definition for CAN_RF1R register *******************/
ebrus 0:0a673c671a56 1729 #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
ebrus 0:0a673c671a56 1730 #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
ebrus 0:0a673c671a56 1731 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
ebrus 0:0a673c671a56 1732 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
ebrus 0:0a673c671a56 1733
ebrus 0:0a673c671a56 1734 /******************** Bit definition for CAN_IER register *******************/
ebrus 0:0a673c671a56 1735 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
ebrus 0:0a673c671a56 1736 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
ebrus 0:0a673c671a56 1737 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
ebrus 0:0a673c671a56 1738 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
ebrus 0:0a673c671a56 1739 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
ebrus 0:0a673c671a56 1740 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
ebrus 0:0a673c671a56 1741 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
ebrus 0:0a673c671a56 1742 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
ebrus 0:0a673c671a56 1743 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
ebrus 0:0a673c671a56 1744 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
ebrus 0:0a673c671a56 1745 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
ebrus 0:0a673c671a56 1746 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
ebrus 0:0a673c671a56 1747 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
ebrus 0:0a673c671a56 1748 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
ebrus 0:0a673c671a56 1749
ebrus 0:0a673c671a56 1750 /******************** Bit definition for CAN_ESR register *******************/
ebrus 0:0a673c671a56 1751 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
ebrus 0:0a673c671a56 1752 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
ebrus 0:0a673c671a56 1753 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
ebrus 0:0a673c671a56 1754
ebrus 0:0a673c671a56 1755 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
ebrus 0:0a673c671a56 1756 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 1757 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 1758 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:0a673c671a56 1759
ebrus 0:0a673c671a56 1760 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
ebrus 0:0a673c671a56 1761 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
ebrus 0:0a673c671a56 1762
ebrus 0:0a673c671a56 1763 /******************* Bit definition for CAN_BTR register ********************/
ebrus 0:0a673c671a56 1764 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
ebrus 0:0a673c671a56 1765 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
ebrus 0:0a673c671a56 1766 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
ebrus 0:0a673c671a56 1767 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
ebrus 0:0a673c671a56 1768 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
ebrus 0:0a673c671a56 1769 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
ebrus 0:0a673c671a56 1770
ebrus 0:0a673c671a56 1771 /*!<Mailbox registers */
ebrus 0:0a673c671a56 1772 /****************** Bit definition for CAN_TI0R register ********************/
ebrus 0:0a673c671a56 1773 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
ebrus 0:0a673c671a56 1774 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
ebrus 0:0a673c671a56 1775 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
ebrus 0:0a673c671a56 1776 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
ebrus 0:0a673c671a56 1777 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
ebrus 0:0a673c671a56 1778
ebrus 0:0a673c671a56 1779 /****************** Bit definition for CAN_TDT0R register *******************/
ebrus 0:0a673c671a56 1780 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
ebrus 0:0a673c671a56 1781 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
ebrus 0:0a673c671a56 1782 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
ebrus 0:0a673c671a56 1783
ebrus 0:0a673c671a56 1784 /****************** Bit definition for CAN_TDL0R register *******************/
ebrus 0:0a673c671a56 1785 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
ebrus 0:0a673c671a56 1786 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
ebrus 0:0a673c671a56 1787 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
ebrus 0:0a673c671a56 1788 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
ebrus 0:0a673c671a56 1789
ebrus 0:0a673c671a56 1790 /****************** Bit definition for CAN_TDH0R register *******************/
ebrus 0:0a673c671a56 1791 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
ebrus 0:0a673c671a56 1792 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
ebrus 0:0a673c671a56 1793 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
ebrus 0:0a673c671a56 1794 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
ebrus 0:0a673c671a56 1795
ebrus 0:0a673c671a56 1796 /******************* Bit definition for CAN_TI1R register *******************/
ebrus 0:0a673c671a56 1797 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
ebrus 0:0a673c671a56 1798 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
ebrus 0:0a673c671a56 1799 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
ebrus 0:0a673c671a56 1800 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
ebrus 0:0a673c671a56 1801 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
ebrus 0:0a673c671a56 1802
ebrus 0:0a673c671a56 1803 /******************* Bit definition for CAN_TDT1R register ******************/
ebrus 0:0a673c671a56 1804 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
ebrus 0:0a673c671a56 1805 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
ebrus 0:0a673c671a56 1806 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
ebrus 0:0a673c671a56 1807
ebrus 0:0a673c671a56 1808 /******************* Bit definition for CAN_TDL1R register ******************/
ebrus 0:0a673c671a56 1809 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
ebrus 0:0a673c671a56 1810 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
ebrus 0:0a673c671a56 1811 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
ebrus 0:0a673c671a56 1812 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
ebrus 0:0a673c671a56 1813
ebrus 0:0a673c671a56 1814 /******************* Bit definition for CAN_TDH1R register ******************/
ebrus 0:0a673c671a56 1815 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
ebrus 0:0a673c671a56 1816 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
ebrus 0:0a673c671a56 1817 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
ebrus 0:0a673c671a56 1818 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
ebrus 0:0a673c671a56 1819
ebrus 0:0a673c671a56 1820 /******************* Bit definition for CAN_TI2R register *******************/
ebrus 0:0a673c671a56 1821 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
ebrus 0:0a673c671a56 1822 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
ebrus 0:0a673c671a56 1823 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
ebrus 0:0a673c671a56 1824 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
ebrus 0:0a673c671a56 1825 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
ebrus 0:0a673c671a56 1826
ebrus 0:0a673c671a56 1827 /******************* Bit definition for CAN_TDT2R register ******************/
ebrus 0:0a673c671a56 1828 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
ebrus 0:0a673c671a56 1829 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
ebrus 0:0a673c671a56 1830 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
ebrus 0:0a673c671a56 1831
ebrus 0:0a673c671a56 1832 /******************* Bit definition for CAN_TDL2R register ******************/
ebrus 0:0a673c671a56 1833 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
ebrus 0:0a673c671a56 1834 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
ebrus 0:0a673c671a56 1835 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
ebrus 0:0a673c671a56 1836 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
ebrus 0:0a673c671a56 1837
ebrus 0:0a673c671a56 1838 /******************* Bit definition for CAN_TDH2R register ******************/
ebrus 0:0a673c671a56 1839 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
ebrus 0:0a673c671a56 1840 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
ebrus 0:0a673c671a56 1841 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
ebrus 0:0a673c671a56 1842 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
ebrus 0:0a673c671a56 1843
ebrus 0:0a673c671a56 1844 /******************* Bit definition for CAN_RI0R register *******************/
ebrus 0:0a673c671a56 1845 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
ebrus 0:0a673c671a56 1846 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
ebrus 0:0a673c671a56 1847 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
ebrus 0:0a673c671a56 1848 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
ebrus 0:0a673c671a56 1849
ebrus 0:0a673c671a56 1850 /******************* Bit definition for CAN_RDT0R register ******************/
ebrus 0:0a673c671a56 1851 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
ebrus 0:0a673c671a56 1852 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
ebrus 0:0a673c671a56 1853 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
ebrus 0:0a673c671a56 1854
ebrus 0:0a673c671a56 1855 /******************* Bit definition for CAN_RDL0R register ******************/
ebrus 0:0a673c671a56 1856 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
ebrus 0:0a673c671a56 1857 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
ebrus 0:0a673c671a56 1858 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
ebrus 0:0a673c671a56 1859 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
ebrus 0:0a673c671a56 1860
ebrus 0:0a673c671a56 1861 /******************* Bit definition for CAN_RDH0R register ******************/
ebrus 0:0a673c671a56 1862 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
ebrus 0:0a673c671a56 1863 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
ebrus 0:0a673c671a56 1864 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
ebrus 0:0a673c671a56 1865 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
ebrus 0:0a673c671a56 1866
ebrus 0:0a673c671a56 1867 /******************* Bit definition for CAN_RI1R register *******************/
ebrus 0:0a673c671a56 1868 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
ebrus 0:0a673c671a56 1869 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
ebrus 0:0a673c671a56 1870 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
ebrus 0:0a673c671a56 1871 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
ebrus 0:0a673c671a56 1872
ebrus 0:0a673c671a56 1873 /******************* Bit definition for CAN_RDT1R register ******************/
ebrus 0:0a673c671a56 1874 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
ebrus 0:0a673c671a56 1875 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
ebrus 0:0a673c671a56 1876 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
ebrus 0:0a673c671a56 1877
ebrus 0:0a673c671a56 1878 /******************* Bit definition for CAN_RDL1R register ******************/
ebrus 0:0a673c671a56 1879 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
ebrus 0:0a673c671a56 1880 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
ebrus 0:0a673c671a56 1881 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
ebrus 0:0a673c671a56 1882 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
ebrus 0:0a673c671a56 1883
ebrus 0:0a673c671a56 1884 /******************* Bit definition for CAN_RDH1R register ******************/
ebrus 0:0a673c671a56 1885 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
ebrus 0:0a673c671a56 1886 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
ebrus 0:0a673c671a56 1887 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
ebrus 0:0a673c671a56 1888 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
ebrus 0:0a673c671a56 1889
ebrus 0:0a673c671a56 1890 /*!<CAN filter registers */
ebrus 0:0a673c671a56 1891 /******************* Bit definition for CAN_FMR register ********************/
ebrus 0:0a673c671a56 1892 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
ebrus 0:0a673c671a56 1893
ebrus 0:0a673c671a56 1894 /******************* Bit definition for CAN_FM1R register *******************/
ebrus 0:0a673c671a56 1895 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
ebrus 0:0a673c671a56 1896 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
ebrus 0:0a673c671a56 1897 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
ebrus 0:0a673c671a56 1898 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
ebrus 0:0a673c671a56 1899 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
ebrus 0:0a673c671a56 1900 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
ebrus 0:0a673c671a56 1901 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
ebrus 0:0a673c671a56 1902 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
ebrus 0:0a673c671a56 1903 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
ebrus 0:0a673c671a56 1904 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
ebrus 0:0a673c671a56 1905 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
ebrus 0:0a673c671a56 1906 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
ebrus 0:0a673c671a56 1907 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
ebrus 0:0a673c671a56 1908 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
ebrus 0:0a673c671a56 1909 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
ebrus 0:0a673c671a56 1910
ebrus 0:0a673c671a56 1911 /******************* Bit definition for CAN_FS1R register *******************/
ebrus 0:0a673c671a56 1912 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
ebrus 0:0a673c671a56 1913 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
ebrus 0:0a673c671a56 1914 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
ebrus 0:0a673c671a56 1915 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
ebrus 0:0a673c671a56 1916 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
ebrus 0:0a673c671a56 1917 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
ebrus 0:0a673c671a56 1918 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
ebrus 0:0a673c671a56 1919 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
ebrus 0:0a673c671a56 1920 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
ebrus 0:0a673c671a56 1921 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
ebrus 0:0a673c671a56 1922 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
ebrus 0:0a673c671a56 1923 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
ebrus 0:0a673c671a56 1924 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
ebrus 0:0a673c671a56 1925 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
ebrus 0:0a673c671a56 1926 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
ebrus 0:0a673c671a56 1927
ebrus 0:0a673c671a56 1928 /****************** Bit definition for CAN_FFA1R register *******************/
ebrus 0:0a673c671a56 1929 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
ebrus 0:0a673c671a56 1930 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
ebrus 0:0a673c671a56 1931 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
ebrus 0:0a673c671a56 1932 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
ebrus 0:0a673c671a56 1933 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
ebrus 0:0a673c671a56 1934 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
ebrus 0:0a673c671a56 1935 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
ebrus 0:0a673c671a56 1936 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
ebrus 0:0a673c671a56 1937 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
ebrus 0:0a673c671a56 1938 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
ebrus 0:0a673c671a56 1939 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
ebrus 0:0a673c671a56 1940 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
ebrus 0:0a673c671a56 1941 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
ebrus 0:0a673c671a56 1942 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
ebrus 0:0a673c671a56 1943 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
ebrus 0:0a673c671a56 1944
ebrus 0:0a673c671a56 1945 /******************* Bit definition for CAN_FA1R register *******************/
ebrus 0:0a673c671a56 1946 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
ebrus 0:0a673c671a56 1947 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
ebrus 0:0a673c671a56 1948 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
ebrus 0:0a673c671a56 1949 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
ebrus 0:0a673c671a56 1950 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
ebrus 0:0a673c671a56 1951 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
ebrus 0:0a673c671a56 1952 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
ebrus 0:0a673c671a56 1953 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
ebrus 0:0a673c671a56 1954 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
ebrus 0:0a673c671a56 1955 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
ebrus 0:0a673c671a56 1956 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
ebrus 0:0a673c671a56 1957 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
ebrus 0:0a673c671a56 1958 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
ebrus 0:0a673c671a56 1959 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
ebrus 0:0a673c671a56 1960 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
ebrus 0:0a673c671a56 1961
ebrus 0:0a673c671a56 1962 /******************* Bit definition for CAN_F0R1 register *******************/
ebrus 0:0a673c671a56 1963 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 1964 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 1965 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 1966 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 1967 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 1968 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 1969 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 1970 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 1971 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 1972 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 1973 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 1974 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 1975 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 1976 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 1977 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 1978 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 1979 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 1980 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 1981 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 1982 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 1983 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 1984 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 1985 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 1986 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 1987 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 1988 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 1989 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 1990 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 1991 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 1992 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 1993 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 1994 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 1995
ebrus 0:0a673c671a56 1996 /******************* Bit definition for CAN_F1R1 register *******************/
ebrus 0:0a673c671a56 1997 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 1998 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 1999 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2000 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2001 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2002 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2003 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2004 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2005 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2006 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2007 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2008 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2009 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2010 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2011 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2012 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2013 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2014 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2015 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2016 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2017 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2018 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2019 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2020 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2021 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2022 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2023 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2024 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2025 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2026 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2027 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2028 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2029
ebrus 0:0a673c671a56 2030 /******************* Bit definition for CAN_F2R1 register *******************/
ebrus 0:0a673c671a56 2031 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2032 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2033 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2034 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2035 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2036 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2037 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2038 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2039 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2040 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2041 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2042 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2043 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2044 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2045 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2046 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2047 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2048 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2049 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2050 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2051 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2052 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2053 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2054 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2055 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2056 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2057 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2058 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2059 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2060 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2061 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2062 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2063
ebrus 0:0a673c671a56 2064 /******************* Bit definition for CAN_F3R1 register *******************/
ebrus 0:0a673c671a56 2065 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2066 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2067 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2068 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2069 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2070 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2071 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2072 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2073 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2074 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2075 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2076 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2077 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2078 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2079 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2080 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2081 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2082 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2083 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2084 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2085 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2086 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2087 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2088 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2089 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2090 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2091 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2092 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2093 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2094 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2095 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2096 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2097
ebrus 0:0a673c671a56 2098 /******************* Bit definition for CAN_F4R1 register *******************/
ebrus 0:0a673c671a56 2099 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2100 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2101 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2102 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2103 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2104 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2105 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2106 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2107 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2108 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2109 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2110 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2111 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2112 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2113 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2114 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2115 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2116 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2117 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2118 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2119 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2120 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2121 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2122 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2123 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2124 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2125 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2126 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2127 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2128 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2129 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2130 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2131
ebrus 0:0a673c671a56 2132 /******************* Bit definition for CAN_F5R1 register *******************/
ebrus 0:0a673c671a56 2133 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2134 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2135 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2136 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2137 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2138 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2139 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2140 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2141 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2142 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2143 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2144 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2145 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2146 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2147 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2148 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2149 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2150 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2151 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2152 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2153 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2154 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2155 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2156 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2157 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2158 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2159 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2160 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2161 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2162 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2163 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2164 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2165
ebrus 0:0a673c671a56 2166 /******************* Bit definition for CAN_F6R1 register *******************/
ebrus 0:0a673c671a56 2167 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2168 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2169 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2170 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2171 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2172 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2173 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2174 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2175 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2176 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2177 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2178 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2179 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2180 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2181 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2182 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2183 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2184 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2185 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2186 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2187 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2188 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2189 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2190 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2191 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2192 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2193 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2194 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2195 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2196 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2197 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2198 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2199
ebrus 0:0a673c671a56 2200 /******************* Bit definition for CAN_F7R1 register *******************/
ebrus 0:0a673c671a56 2201 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2202 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2203 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2204 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2205 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2206 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2207 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2208 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2209 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2210 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2211 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2212 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2213 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2214 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2215 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2216 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2217 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2218 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2219 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2220 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2221 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2222 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2223 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2224 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2225 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2226 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2227 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2228 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2229 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2230 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2231 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2232 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2233
ebrus 0:0a673c671a56 2234 /******************* Bit definition for CAN_F8R1 register *******************/
ebrus 0:0a673c671a56 2235 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2236 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2237 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2238 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2239 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2240 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2241 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2242 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2243 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2244 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2245 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2246 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2247 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2248 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2249 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2250 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2251 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2252 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2253 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2254 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2255 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2256 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2257 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2258 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2259 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2260 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2261 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2262 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2263 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2264 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2265 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2266 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2267
ebrus 0:0a673c671a56 2268 /******************* Bit definition for CAN_F9R1 register *******************/
ebrus 0:0a673c671a56 2269 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2270 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2271 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2272 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2273 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2274 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2275 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2276 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2277 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2278 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2279 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2280 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2281 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2282 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2283 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2284 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2285 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2286 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2287 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2288 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2289 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2290 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2291 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2292 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2293 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2294 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2295 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2296 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2297 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2298 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2299 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2300 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2301
ebrus 0:0a673c671a56 2302 /******************* Bit definition for CAN_F10R1 register ******************/
ebrus 0:0a673c671a56 2303 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2304 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2305 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2306 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2307 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2308 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2309 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2310 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2311 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2312 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2313 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2314 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2315 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2316 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2317 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2318 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2319 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2320 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2321 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2322 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2323 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2324 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2325 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2326 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2327 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2328 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2329 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2330 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2331 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2332 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2333 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2334 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2335
ebrus 0:0a673c671a56 2336 /******************* Bit definition for CAN_F11R1 register ******************/
ebrus 0:0a673c671a56 2337 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2338 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2339 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2340 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2341 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2342 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2343 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2344 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2345 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2346 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2347 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2348 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2349 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2350 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2351 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2352 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2353 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2354 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2355 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2356 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2357 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2358 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2359 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2360 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2361 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2362 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2363 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2364 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2365 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2366 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2367 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2368 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2369
ebrus 0:0a673c671a56 2370 /******************* Bit definition for CAN_F12R1 register ******************/
ebrus 0:0a673c671a56 2371 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2372 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2373 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2374 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2375 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2376 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2377 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2378 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2379 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2380 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2381 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2382 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2383 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2384 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2385 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2386 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2387 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2388 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2389 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2390 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2391 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2392 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2393 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2394 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2395 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2396 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2397 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2398 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2399 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2400 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2401 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2402 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2403
ebrus 0:0a673c671a56 2404 /******************* Bit definition for CAN_F13R1 register ******************/
ebrus 0:0a673c671a56 2405 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2406 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2407 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2408 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2409 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2410 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2411 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2412 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2413 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2414 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2415 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2416 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2417 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2418 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2419 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2420 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2421 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2422 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2423 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2424 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2425 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2426 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2427 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2428 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2429 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2430 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2431 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2432 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2433 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2434 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2435 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2436 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2437
ebrus 0:0a673c671a56 2438 /******************* Bit definition for CAN_F0R2 register *******************/
ebrus 0:0a673c671a56 2439 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2440 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2441 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2442 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2443 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2444 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2445 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2446 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2447 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2448 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2449 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2450 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2451 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2452 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2453 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2454 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2455 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2456 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2457 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2458 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2459 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2460 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2461 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2462 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2463 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2464 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2465 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2466 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2467 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2468 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2469 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2470 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2471
ebrus 0:0a673c671a56 2472 /******************* Bit definition for CAN_F1R2 register *******************/
ebrus 0:0a673c671a56 2473 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2474 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2475 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2476 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2477 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2478 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2479 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2480 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2481 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2482 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2483 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2484 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2485 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2486 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2487 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2488 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2489 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2490 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2491 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2492 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2493 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2494 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2495 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2496 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2497 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2498 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2499 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2500 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2501 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2502 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2503 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2504 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2505
ebrus 0:0a673c671a56 2506 /******************* Bit definition for CAN_F2R2 register *******************/
ebrus 0:0a673c671a56 2507 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2508 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2509 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2510 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2511 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2512 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2513 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2514 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2515 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2516 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2517 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2518 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2519 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2520 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2521 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2522 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2523 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2524 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2525 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2526 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2527 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2528 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2529 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2530 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2531 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2532 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2533 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2534 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2535 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2536 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2537 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2538 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2539
ebrus 0:0a673c671a56 2540 /******************* Bit definition for CAN_F3R2 register *******************/
ebrus 0:0a673c671a56 2541 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2542 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2543 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2544 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2545 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2546 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2547 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2548 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2549 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2550 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2551 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2552 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2553 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2554 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2555 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2556 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2557 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2558 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2559 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2560 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2561 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2562 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2563 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2564 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2565 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2566 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2567 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2568 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2569 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2570 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2571 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2572 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2573
ebrus 0:0a673c671a56 2574 /******************* Bit definition for CAN_F4R2 register *******************/
ebrus 0:0a673c671a56 2575 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2576 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2577 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2578 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2579 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2580 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2581 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2582 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2583 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2584 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2585 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2586 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2587 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2588 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2589 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2590 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2591 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2592 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2593 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2594 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2595 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2596 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2597 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2598 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2599 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2600 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2601 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2602 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2603 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2604 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2605 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2606 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2607
ebrus 0:0a673c671a56 2608 /******************* Bit definition for CAN_F5R2 register *******************/
ebrus 0:0a673c671a56 2609 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2610 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2611 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2612 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2613 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2614 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2615 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2616 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2617 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2618 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2619 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2620 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2621 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2622 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2623 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2624 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2625 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2626 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2627 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2628 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2629 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2630 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2631 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2632 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2633 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2634 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2635 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2636 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2637 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2638 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2639 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2640 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2641
ebrus 0:0a673c671a56 2642 /******************* Bit definition for CAN_F6R2 register *******************/
ebrus 0:0a673c671a56 2643 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2644 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2645 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2646 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2647 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2648 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2649 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2650 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2651 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2652 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2653 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2654 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2655 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2656 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2657 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2658 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2659 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2660 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2661 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2662 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2663 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2664 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2665 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2666 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2667 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2668 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2669 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2670 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2671 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2672 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2673 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2674 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2675
ebrus 0:0a673c671a56 2676 /******************* Bit definition for CAN_F7R2 register *******************/
ebrus 0:0a673c671a56 2677 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2678 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2679 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2680 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2681 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2682 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2683 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2684 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2685 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2686 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2687 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2688 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2689 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2690 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2691 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2692 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2693 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2694 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2695 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2696 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2697 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2698 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2699 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2700 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2701 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2702 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2703 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2704 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2705 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2706 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2707 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2708 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2709
ebrus 0:0a673c671a56 2710 /******************* Bit definition for CAN_F8R2 register *******************/
ebrus 0:0a673c671a56 2711 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2712 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2713 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2714 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2715 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2716 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2717 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2718 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2719 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2720 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2721 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2722 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2723 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2724 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2725 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2726 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2727 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2728 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2729 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2730 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2731 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2732 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2733 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2734 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2735 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2736 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2737 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2738 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2739 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2740 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2741 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2742 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2743
ebrus 0:0a673c671a56 2744 /******************* Bit definition for CAN_F9R2 register *******************/
ebrus 0:0a673c671a56 2745 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2746 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2747 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2748 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2749 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2750 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2751 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2752 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2753 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2754 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2755 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2756 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2757 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2758 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2759 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2760 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2761 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2762 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2763 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2764 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2765 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2766 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2767 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2768 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2769 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2770 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2771 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2772 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2773 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2774 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2775 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2776 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2777
ebrus 0:0a673c671a56 2778 /******************* Bit definition for CAN_F10R2 register ******************/
ebrus 0:0a673c671a56 2779 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2780 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2781 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2782 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2783 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2784 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2785 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2786 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2787 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2788 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2789 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2790 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2791 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2792 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2793 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2794 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2795 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2796 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2797 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2798 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2799 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2800 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2801 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2802 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2803 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2804 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2805 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2806 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2807 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2808 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2809 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2810 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2811
ebrus 0:0a673c671a56 2812 /******************* Bit definition for CAN_F11R2 register ******************/
ebrus 0:0a673c671a56 2813 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2814 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2815 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2816 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2817 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2818 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2819 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2820 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2821 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2822 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2823 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2824 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2825 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2826 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2827 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2828 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2829 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2830 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2831 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2832 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2833 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2834 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2835 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2836 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2837 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2838 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2839 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2840 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2841 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2842 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2843 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2844 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2845
ebrus 0:0a673c671a56 2846 /******************* Bit definition for CAN_F12R2 register ******************/
ebrus 0:0a673c671a56 2847 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2848 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2849 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2850 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2851 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2852 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2853 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2854 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2855 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2856 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2857 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2858 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2859 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2860 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2861 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2862 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2863 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2864 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2865 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2866 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2867 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2868 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2869 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2870 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2871 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2872 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2873 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2874 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2875 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2876 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2877 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2878 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2879
ebrus 0:0a673c671a56 2880 /******************* Bit definition for CAN_F13R2 register ******************/
ebrus 0:0a673c671a56 2881 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:0a673c671a56 2882 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:0a673c671a56 2883 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:0a673c671a56 2884 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:0a673c671a56 2885 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:0a673c671a56 2886 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:0a673c671a56 2887 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:0a673c671a56 2888 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:0a673c671a56 2889 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:0a673c671a56 2890 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:0a673c671a56 2891 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:0a673c671a56 2892 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:0a673c671a56 2893 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:0a673c671a56 2894 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:0a673c671a56 2895 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:0a673c671a56 2896 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:0a673c671a56 2897 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:0a673c671a56 2898 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:0a673c671a56 2899 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:0a673c671a56 2900 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:0a673c671a56 2901 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:0a673c671a56 2902 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:0a673c671a56 2903 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:0a673c671a56 2904 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:0a673c671a56 2905 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:0a673c671a56 2906 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:0a673c671a56 2907 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:0a673c671a56 2908 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:0a673c671a56 2909 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:0a673c671a56 2910 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:0a673c671a56 2911 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:0a673c671a56 2912 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:0a673c671a56 2913
ebrus 0:0a673c671a56 2914 /******************************************************************************/
ebrus 0:0a673c671a56 2915 /* */
ebrus 0:0a673c671a56 2916 /* CRC calculation unit */
ebrus 0:0a673c671a56 2917 /* */
ebrus 0:0a673c671a56 2918 /******************************************************************************/
ebrus 0:0a673c671a56 2919 /******************* Bit definition for CRC_DR register *********************/
ebrus 0:0a673c671a56 2920 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
ebrus 0:0a673c671a56 2921
ebrus 0:0a673c671a56 2922
ebrus 0:0a673c671a56 2923 /******************* Bit definition for CRC_IDR register ********************/
ebrus 0:0a673c671a56 2924 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
ebrus 0:0a673c671a56 2925
ebrus 0:0a673c671a56 2926
ebrus 0:0a673c671a56 2927 /******************** Bit definition for CRC_CR register ********************/
ebrus 0:0a673c671a56 2928 #define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
ebrus 0:0a673c671a56 2929
ebrus 0:0a673c671a56 2930 /******************************************************************************/
ebrus 0:0a673c671a56 2931 /* */
ebrus 0:0a673c671a56 2932 /* Crypto Processor */
ebrus 0:0a673c671a56 2933 /* */
ebrus 0:0a673c671a56 2934 /******************************************************************************/
ebrus 0:0a673c671a56 2935 /******************* Bits definition for CRYP_CR register ********************/
ebrus 0:0a673c671a56 2936 #define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 2937
ebrus 0:0a673c671a56 2938 #define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)
ebrus 0:0a673c671a56 2939 #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 2940 #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 2941 #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 2942 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 2943 #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 2944 #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 2945 #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
ebrus 0:0a673c671a56 2946 #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 2947 #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
ebrus 0:0a673c671a56 2948 #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
ebrus 0:0a673c671a56 2949 #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
ebrus 0:0a673c671a56 2950
ebrus 0:0a673c671a56 2951 #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
ebrus 0:0a673c671a56 2952 #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 2953 #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 2954 #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
ebrus 0:0a673c671a56 2955 #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 2956 #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 2957 #define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 2958 #define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 2959
ebrus 0:0a673c671a56 2960 #define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)
ebrus 0:0a673c671a56 2961 #define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 2962 #define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 2963 #define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 2964
ebrus 0:0a673c671a56 2965 /****************** Bits definition for CRYP_SR register *********************/
ebrus 0:0a673c671a56 2966 #define CRYP_SR_IFEM ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 2967 #define CRYP_SR_IFNF ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 2968 #define CRYP_SR_OFNE ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 2969 #define CRYP_SR_OFFU ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 2970 #define CRYP_SR_BUSY ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 2971 /****************** Bits definition for CRYP_DMACR register ******************/
ebrus 0:0a673c671a56 2972 #define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 2973 #define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 2974 /***************** Bits definition for CRYP_IMSCR register ******************/
ebrus 0:0a673c671a56 2975 #define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 2976 #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 2977 /****************** Bits definition for CRYP_RISR register *******************/
ebrus 0:0a673c671a56 2978 #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 2979 #define CRYP_RISR_INRIS ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 2980 /****************** Bits definition for CRYP_MISR register *******************/
ebrus 0:0a673c671a56 2981 #define CRYP_MISR_INMIS ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 2982 #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 2983
ebrus 0:0a673c671a56 2984 /******************************************************************************/
ebrus 0:0a673c671a56 2985 /* */
ebrus 0:0a673c671a56 2986 /* Digital to Analog Converter */
ebrus 0:0a673c671a56 2987 /* */
ebrus 0:0a673c671a56 2988 /******************************************************************************/
ebrus 0:0a673c671a56 2989 /******************** Bit definition for DAC_CR register ********************/
ebrus 0:0a673c671a56 2990 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
ebrus 0:0a673c671a56 2991 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
ebrus 0:0a673c671a56 2992 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
ebrus 0:0a673c671a56 2993
ebrus 0:0a673c671a56 2994 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
ebrus 0:0a673c671a56 2995 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
ebrus 0:0a673c671a56 2996 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
ebrus 0:0a673c671a56 2997 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
ebrus 0:0a673c671a56 2998
ebrus 0:0a673c671a56 2999 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
ebrus 0:0a673c671a56 3000 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
ebrus 0:0a673c671a56 3001 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
ebrus 0:0a673c671a56 3002
ebrus 0:0a673c671a56 3003 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
ebrus 0:0a673c671a56 3004 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 3005 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 3006 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 3007 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 3008
ebrus 0:0a673c671a56 3009 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
ebrus 0:0a673c671a56 3010 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
ebrus 0:0a673c671a56 3011 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
ebrus 0:0a673c671a56 3012 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
ebrus 0:0a673c671a56 3013
ebrus 0:0a673c671a56 3014 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
ebrus 0:0a673c671a56 3015 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3016 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3017 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3018
ebrus 0:0a673c671a56 3019 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
ebrus 0:0a673c671a56 3020 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3021 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3022
ebrus 0:0a673c671a56 3023 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
ebrus 0:0a673c671a56 3024 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3025 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3026 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3027 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3028
ebrus 0:0a673c671a56 3029 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
ebrus 0:0a673c671a56 3030
ebrus 0:0a673c671a56 3031 /***************** Bit definition for DAC_SWTRIGR register ******************/
ebrus 0:0a673c671a56 3032 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
ebrus 0:0a673c671a56 3033 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
ebrus 0:0a673c671a56 3034
ebrus 0:0a673c671a56 3035 /***************** Bit definition for DAC_DHR12R1 register ******************/
ebrus 0:0a673c671a56 3036 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
ebrus 0:0a673c671a56 3037
ebrus 0:0a673c671a56 3038 /***************** Bit definition for DAC_DHR12L1 register ******************/
ebrus 0:0a673c671a56 3039 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
ebrus 0:0a673c671a56 3040
ebrus 0:0a673c671a56 3041 /****************** Bit definition for DAC_DHR8R1 register ******************/
ebrus 0:0a673c671a56 3042 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
ebrus 0:0a673c671a56 3043
ebrus 0:0a673c671a56 3044 /***************** Bit definition for DAC_DHR12R2 register ******************/
ebrus 0:0a673c671a56 3045 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
ebrus 0:0a673c671a56 3046
ebrus 0:0a673c671a56 3047 /***************** Bit definition for DAC_DHR12L2 register ******************/
ebrus 0:0a673c671a56 3048 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
ebrus 0:0a673c671a56 3049
ebrus 0:0a673c671a56 3050 /****************** Bit definition for DAC_DHR8R2 register ******************/
ebrus 0:0a673c671a56 3051 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
ebrus 0:0a673c671a56 3052
ebrus 0:0a673c671a56 3053 /***************** Bit definition for DAC_DHR12RD register ******************/
ebrus 0:0a673c671a56 3054 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
ebrus 0:0a673c671a56 3055 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
ebrus 0:0a673c671a56 3056
ebrus 0:0a673c671a56 3057 /***************** Bit definition for DAC_DHR12LD register ******************/
ebrus 0:0a673c671a56 3058 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
ebrus 0:0a673c671a56 3059 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
ebrus 0:0a673c671a56 3060
ebrus 0:0a673c671a56 3061 /****************** Bit definition for DAC_DHR8RD register ******************/
ebrus 0:0a673c671a56 3062 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
ebrus 0:0a673c671a56 3063 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
ebrus 0:0a673c671a56 3064
ebrus 0:0a673c671a56 3065 /******************* Bit definition for DAC_DOR1 register *******************/
ebrus 0:0a673c671a56 3066 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
ebrus 0:0a673c671a56 3067
ebrus 0:0a673c671a56 3068 /******************* Bit definition for DAC_DOR2 register *******************/
ebrus 0:0a673c671a56 3069 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
ebrus 0:0a673c671a56 3070
ebrus 0:0a673c671a56 3071 /******************** Bit definition for DAC_SR register ********************/
ebrus 0:0a673c671a56 3072 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
ebrus 0:0a673c671a56 3073 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
ebrus 0:0a673c671a56 3074
ebrus 0:0a673c671a56 3075 /******************************************************************************/
ebrus 0:0a673c671a56 3076 /* */
ebrus 0:0a673c671a56 3077 /* Debug MCU */
ebrus 0:0a673c671a56 3078 /* */
ebrus 0:0a673c671a56 3079 /******************************************************************************/
ebrus 0:0a673c671a56 3080
ebrus 0:0a673c671a56 3081 /******************************************************************************/
ebrus 0:0a673c671a56 3082 /* */
ebrus 0:0a673c671a56 3083 /* DCMI */
ebrus 0:0a673c671a56 3084 /* */
ebrus 0:0a673c671a56 3085 /******************************************************************************/
ebrus 0:0a673c671a56 3086 /******************** Bits definition for DCMI_CR register ******************/
ebrus 0:0a673c671a56 3087 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3088 #define DCMI_CR_CM ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3089 #define DCMI_CR_CROP ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3090 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3091 #define DCMI_CR_ESS ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3092 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 3093 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 3094 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 3095 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 3096 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 3097 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 3098 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 3099 #define DCMI_CR_CRE ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 3100 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 3101
ebrus 0:0a673c671a56 3102 /******************** Bits definition for DCMI_SR register ******************/
ebrus 0:0a673c671a56 3103 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3104 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3105 #define DCMI_SR_FNE ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3106
ebrus 0:0a673c671a56 3107 /******************** Bits definition for DCMI_RISR register ****************/
ebrus 0:0a673c671a56 3108 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3109 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3110 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3111 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3112 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3113
ebrus 0:0a673c671a56 3114 /******************** Bits definition for DCMI_IER register *****************/
ebrus 0:0a673c671a56 3115 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3116 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3117 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3118 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3119 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3120
ebrus 0:0a673c671a56 3121 /******************** Bits definition for DCMI_MISR register ****************/
ebrus 0:0a673c671a56 3122 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3123 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3124 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3125 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3126 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3127
ebrus 0:0a673c671a56 3128 /******************** Bits definition for DCMI_ICR register *****************/
ebrus 0:0a673c671a56 3129 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3130 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3131 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3132 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3133 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3134
ebrus 0:0a673c671a56 3135 /******************************************************************************/
ebrus 0:0a673c671a56 3136 /* */
ebrus 0:0a673c671a56 3137 /* DMA Controller */
ebrus 0:0a673c671a56 3138 /* */
ebrus 0:0a673c671a56 3139 /******************************************************************************/
ebrus 0:0a673c671a56 3140 /******************** Bits definition for DMA_SxCR register *****************/
ebrus 0:0a673c671a56 3141 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
ebrus 0:0a673c671a56 3142 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 3143 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 3144 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 3145 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
ebrus 0:0a673c671a56 3146 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 3147 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 3148 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
ebrus 0:0a673c671a56 3149 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 3150 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 3151 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 3152 #define DMA_SxCR_CT ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 3153 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 3154 #define DMA_SxCR_PL ((uint32_t)0x00030000)
ebrus 0:0a673c671a56 3155 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 3156 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 3157 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 3158 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
ebrus 0:0a673c671a56 3159 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 3160 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 3161 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
ebrus 0:0a673c671a56 3162 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 3163 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 3164 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 3165 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 3166 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 3167 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
ebrus 0:0a673c671a56 3168 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 3169 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 3170 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 3171 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3172 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3173 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3174 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3175 #define DMA_SxCR_EN ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3176
ebrus 0:0a673c671a56 3177 /******************** Bits definition for DMA_SxCNDTR register **************/
ebrus 0:0a673c671a56 3178 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
ebrus 0:0a673c671a56 3179 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3180 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3181 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3182 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3183 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3184 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 3185 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 3186 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 3187 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 3188 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 3189 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 3190 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 3191 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 3192 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 3193 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 3194 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 3195
ebrus 0:0a673c671a56 3196 /******************** Bits definition for DMA_SxFCR register ****************/
ebrus 0:0a673c671a56 3197 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 3198 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
ebrus 0:0a673c671a56 3199 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3200 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3201 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 3202 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3203 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
ebrus 0:0a673c671a56 3204 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3205 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3206
ebrus 0:0a673c671a56 3207 /******************** Bits definition for DMA_LISR register *****************/
ebrus 0:0a673c671a56 3208 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 3209 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 3210 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 3211 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 3212 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 3213 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 3214 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 3215 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 3216 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 3217 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 3218 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 3219 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 3220 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 3221 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 3222 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 3223 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 3224 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3225 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3226 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3227 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3228
ebrus 0:0a673c671a56 3229 /******************** Bits definition for DMA_HISR register *****************/
ebrus 0:0a673c671a56 3230 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 3231 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 3232 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 3233 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 3234 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 3235 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 3236 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 3237 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 3238 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 3239 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 3240 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 3241 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 3242 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 3243 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 3244 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 3245 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 3246 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3247 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3248 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3249 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3250
ebrus 0:0a673c671a56 3251 /******************** Bits definition for DMA_LIFCR register ****************/
ebrus 0:0a673c671a56 3252 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 3253 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 3254 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 3255 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 3256 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 3257 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 3258 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 3259 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 3260 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 3261 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 3262 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 3263 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 3264 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 3265 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 3266 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 3267 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 3268 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3269 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3270 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3271 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3272
ebrus 0:0a673c671a56 3273 /******************** Bits definition for DMA_HIFCR register ****************/
ebrus 0:0a673c671a56 3274 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 3275 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 3276 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 3277 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 3278 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 3279 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 3280 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 3281 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 3282 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 3283 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 3284 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 3285 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 3286 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 3287 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 3288 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 3289 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 3290 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3291 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3292 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3293 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3294
ebrus 0:0a673c671a56 3295
ebrus 0:0a673c671a56 3296 /******************************************************************************/
ebrus 0:0a673c671a56 3297 /* */
ebrus 0:0a673c671a56 3298 /* External Interrupt/Event Controller */
ebrus 0:0a673c671a56 3299 /* */
ebrus 0:0a673c671a56 3300 /******************************************************************************/
ebrus 0:0a673c671a56 3301 /******************* Bit definition for EXTI_IMR register *******************/
ebrus 0:0a673c671a56 3302 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
ebrus 0:0a673c671a56 3303 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
ebrus 0:0a673c671a56 3304 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
ebrus 0:0a673c671a56 3305 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
ebrus 0:0a673c671a56 3306 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
ebrus 0:0a673c671a56 3307 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
ebrus 0:0a673c671a56 3308 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
ebrus 0:0a673c671a56 3309 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
ebrus 0:0a673c671a56 3310 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
ebrus 0:0a673c671a56 3311 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
ebrus 0:0a673c671a56 3312 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
ebrus 0:0a673c671a56 3313 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
ebrus 0:0a673c671a56 3314 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
ebrus 0:0a673c671a56 3315 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
ebrus 0:0a673c671a56 3316 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
ebrus 0:0a673c671a56 3317 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
ebrus 0:0a673c671a56 3318 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
ebrus 0:0a673c671a56 3319 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
ebrus 0:0a673c671a56 3320 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
ebrus 0:0a673c671a56 3321 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
ebrus 0:0a673c671a56 3322
ebrus 0:0a673c671a56 3323 /******************* Bit definition for EXTI_EMR register *******************/
ebrus 0:0a673c671a56 3324 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
ebrus 0:0a673c671a56 3325 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
ebrus 0:0a673c671a56 3326 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
ebrus 0:0a673c671a56 3327 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
ebrus 0:0a673c671a56 3328 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
ebrus 0:0a673c671a56 3329 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
ebrus 0:0a673c671a56 3330 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
ebrus 0:0a673c671a56 3331 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
ebrus 0:0a673c671a56 3332 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
ebrus 0:0a673c671a56 3333 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
ebrus 0:0a673c671a56 3334 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
ebrus 0:0a673c671a56 3335 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
ebrus 0:0a673c671a56 3336 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
ebrus 0:0a673c671a56 3337 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
ebrus 0:0a673c671a56 3338 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
ebrus 0:0a673c671a56 3339 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
ebrus 0:0a673c671a56 3340 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
ebrus 0:0a673c671a56 3341 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
ebrus 0:0a673c671a56 3342 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
ebrus 0:0a673c671a56 3343 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
ebrus 0:0a673c671a56 3344
ebrus 0:0a673c671a56 3345 /****************** Bit definition for EXTI_RTSR register *******************/
ebrus 0:0a673c671a56 3346 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
ebrus 0:0a673c671a56 3347 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
ebrus 0:0a673c671a56 3348 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
ebrus 0:0a673c671a56 3349 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
ebrus 0:0a673c671a56 3350 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
ebrus 0:0a673c671a56 3351 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
ebrus 0:0a673c671a56 3352 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
ebrus 0:0a673c671a56 3353 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
ebrus 0:0a673c671a56 3354 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
ebrus 0:0a673c671a56 3355 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
ebrus 0:0a673c671a56 3356 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
ebrus 0:0a673c671a56 3357 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
ebrus 0:0a673c671a56 3358 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
ebrus 0:0a673c671a56 3359 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
ebrus 0:0a673c671a56 3360 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
ebrus 0:0a673c671a56 3361 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
ebrus 0:0a673c671a56 3362 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
ebrus 0:0a673c671a56 3363 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
ebrus 0:0a673c671a56 3364 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
ebrus 0:0a673c671a56 3365 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
ebrus 0:0a673c671a56 3366
ebrus 0:0a673c671a56 3367 /****************** Bit definition for EXTI_FTSR register *******************/
ebrus 0:0a673c671a56 3368 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
ebrus 0:0a673c671a56 3369 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
ebrus 0:0a673c671a56 3370 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
ebrus 0:0a673c671a56 3371 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
ebrus 0:0a673c671a56 3372 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
ebrus 0:0a673c671a56 3373 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
ebrus 0:0a673c671a56 3374 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
ebrus 0:0a673c671a56 3375 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
ebrus 0:0a673c671a56 3376 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
ebrus 0:0a673c671a56 3377 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
ebrus 0:0a673c671a56 3378 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
ebrus 0:0a673c671a56 3379 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
ebrus 0:0a673c671a56 3380 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
ebrus 0:0a673c671a56 3381 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
ebrus 0:0a673c671a56 3382 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
ebrus 0:0a673c671a56 3383 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
ebrus 0:0a673c671a56 3384 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
ebrus 0:0a673c671a56 3385 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
ebrus 0:0a673c671a56 3386 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
ebrus 0:0a673c671a56 3387 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
ebrus 0:0a673c671a56 3388
ebrus 0:0a673c671a56 3389 /****************** Bit definition for EXTI_SWIER register ******************/
ebrus 0:0a673c671a56 3390 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
ebrus 0:0a673c671a56 3391 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
ebrus 0:0a673c671a56 3392 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
ebrus 0:0a673c671a56 3393 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
ebrus 0:0a673c671a56 3394 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
ebrus 0:0a673c671a56 3395 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
ebrus 0:0a673c671a56 3396 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
ebrus 0:0a673c671a56 3397 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
ebrus 0:0a673c671a56 3398 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
ebrus 0:0a673c671a56 3399 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
ebrus 0:0a673c671a56 3400 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
ebrus 0:0a673c671a56 3401 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
ebrus 0:0a673c671a56 3402 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
ebrus 0:0a673c671a56 3403 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
ebrus 0:0a673c671a56 3404 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
ebrus 0:0a673c671a56 3405 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
ebrus 0:0a673c671a56 3406 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
ebrus 0:0a673c671a56 3407 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
ebrus 0:0a673c671a56 3408 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
ebrus 0:0a673c671a56 3409 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
ebrus 0:0a673c671a56 3410
ebrus 0:0a673c671a56 3411 /******************* Bit definition for EXTI_PR register ********************/
ebrus 0:0a673c671a56 3412 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
ebrus 0:0a673c671a56 3413 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
ebrus 0:0a673c671a56 3414 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
ebrus 0:0a673c671a56 3415 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
ebrus 0:0a673c671a56 3416 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
ebrus 0:0a673c671a56 3417 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
ebrus 0:0a673c671a56 3418 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
ebrus 0:0a673c671a56 3419 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
ebrus 0:0a673c671a56 3420 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
ebrus 0:0a673c671a56 3421 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
ebrus 0:0a673c671a56 3422 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
ebrus 0:0a673c671a56 3423 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
ebrus 0:0a673c671a56 3424 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
ebrus 0:0a673c671a56 3425 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
ebrus 0:0a673c671a56 3426 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
ebrus 0:0a673c671a56 3427 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
ebrus 0:0a673c671a56 3428 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
ebrus 0:0a673c671a56 3429 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
ebrus 0:0a673c671a56 3430 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
ebrus 0:0a673c671a56 3431 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
ebrus 0:0a673c671a56 3432
ebrus 0:0a673c671a56 3433 /******************************************************************************/
ebrus 0:0a673c671a56 3434 /* */
ebrus 0:0a673c671a56 3435 /* FLASH */
ebrus 0:0a673c671a56 3436 /* */
ebrus 0:0a673c671a56 3437 /******************************************************************************/
ebrus 0:0a673c671a56 3438 /******************* Bits definition for FLASH_ACR register *****************/
ebrus 0:0a673c671a56 3439 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
ebrus 0:0a673c671a56 3440 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 3441 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3442 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3443 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
ebrus 0:0a673c671a56 3444 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3445 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
ebrus 0:0a673c671a56 3446 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
ebrus 0:0a673c671a56 3447 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
ebrus 0:0a673c671a56 3448
ebrus 0:0a673c671a56 3449 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 3450 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 3451 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 3452 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 3453 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 3454 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
ebrus 0:0a673c671a56 3455 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
ebrus 0:0a673c671a56 3456
ebrus 0:0a673c671a56 3457 /******************* Bits definition for FLASH_SR register ******************/
ebrus 0:0a673c671a56 3458 #define FLASH_SR_EOP ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3459 #define FLASH_SR_SOP ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3460 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3461 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 3462 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 3463 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 3464 #define FLASH_SR_BSY ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 3465
ebrus 0:0a673c671a56 3466 /******************* Bits definition for FLASH_CR register ******************/
ebrus 0:0a673c671a56 3467 #define FLASH_CR_PG ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3468 #define FLASH_CR_SER ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3469 #define FLASH_CR_MER ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3470 #define FLASH_CR_MER1 FLASH_CR_MER
ebrus 0:0a673c671a56 3471 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
ebrus 0:0a673c671a56 3472 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3473 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 3474 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 3475 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 3476 #define FLASH_CR_SNB_4 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 3477 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
ebrus 0:0a673c671a56 3478 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 3479 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 3480 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 3481 #define FLASH_CR_STRT ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 3482 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 3483 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 3484
ebrus 0:0a673c671a56 3485 /******************* Bits definition for FLASH_OPTCR register ***************/
ebrus 0:0a673c671a56 3486 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 3487 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 3488 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 3489 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 3490 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
ebrus 0:0a673c671a56 3491 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 3492 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 3493 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 3494 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
ebrus 0:0a673c671a56 3495 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 3496 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 3497 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 3498 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 3499 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 3500 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 3501 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 3502 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 3503 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
ebrus 0:0a673c671a56 3504 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 3505 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 3506 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 3507 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 3508 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 3509 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 3510 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 3511 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 3512 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 3513 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 3514 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 3515 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 3516
ebrus 0:0a673c671a56 3517 /****************** Bits definition for FLASH_OPTCR1 register ***************/
ebrus 0:0a673c671a56 3518 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
ebrus 0:0a673c671a56 3519 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 3520 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 3521 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 3522 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 3523 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 3524 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 3525 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 3526 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 3527 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 3528 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 3529 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 3530 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 3531
ebrus 0:0a673c671a56 3532
ebrus 0:0a673c671a56 3533 /******************************************************************************/
ebrus 0:0a673c671a56 3534 /* */
ebrus 0:0a673c671a56 3535 /* Flexible Static Memory Controller */
ebrus 0:0a673c671a56 3536 /* */
ebrus 0:0a673c671a56 3537 /******************************************************************************/
ebrus 0:0a673c671a56 3538 /****************** Bit definition for FSMC_BCR1 register *******************/
ebrus 0:0a673c671a56 3539 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
ebrus 0:0a673c671a56 3540 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
ebrus 0:0a673c671a56 3541
ebrus 0:0a673c671a56 3542 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
ebrus 0:0a673c671a56 3543 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
ebrus 0:0a673c671a56 3544 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
ebrus 0:0a673c671a56 3545
ebrus 0:0a673c671a56 3546 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
ebrus 0:0a673c671a56 3547 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3548 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3549
ebrus 0:0a673c671a56 3550 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
ebrus 0:0a673c671a56 3551 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
ebrus 0:0a673c671a56 3552 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
ebrus 0:0a673c671a56 3553 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
ebrus 0:0a673c671a56 3554 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
ebrus 0:0a673c671a56 3555 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
ebrus 0:0a673c671a56 3556 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
ebrus 0:0a673c671a56 3557 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
ebrus 0:0a673c671a56 3558 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
ebrus 0:0a673c671a56 3559 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
ebrus 0:0a673c671a56 3560
ebrus 0:0a673c671a56 3561 /****************** Bit definition for FSMC_BCR2 register *******************/
ebrus 0:0a673c671a56 3562 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
ebrus 0:0a673c671a56 3563 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
ebrus 0:0a673c671a56 3564
ebrus 0:0a673c671a56 3565 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
ebrus 0:0a673c671a56 3566 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
ebrus 0:0a673c671a56 3567 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
ebrus 0:0a673c671a56 3568
ebrus 0:0a673c671a56 3569 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
ebrus 0:0a673c671a56 3570 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3571 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3572
ebrus 0:0a673c671a56 3573 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
ebrus 0:0a673c671a56 3574 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
ebrus 0:0a673c671a56 3575 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
ebrus 0:0a673c671a56 3576 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
ebrus 0:0a673c671a56 3577 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
ebrus 0:0a673c671a56 3578 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
ebrus 0:0a673c671a56 3579 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
ebrus 0:0a673c671a56 3580 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
ebrus 0:0a673c671a56 3581 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
ebrus 0:0a673c671a56 3582 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
ebrus 0:0a673c671a56 3583
ebrus 0:0a673c671a56 3584 /****************** Bit definition for FSMC_BCR3 register *******************/
ebrus 0:0a673c671a56 3585 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
ebrus 0:0a673c671a56 3586 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
ebrus 0:0a673c671a56 3587
ebrus 0:0a673c671a56 3588 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
ebrus 0:0a673c671a56 3589 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
ebrus 0:0a673c671a56 3590 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
ebrus 0:0a673c671a56 3591
ebrus 0:0a673c671a56 3592 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
ebrus 0:0a673c671a56 3593 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3594 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3595
ebrus 0:0a673c671a56 3596 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
ebrus 0:0a673c671a56 3597 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
ebrus 0:0a673c671a56 3598 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
ebrus 0:0a673c671a56 3599 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
ebrus 0:0a673c671a56 3600 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
ebrus 0:0a673c671a56 3601 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
ebrus 0:0a673c671a56 3602 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
ebrus 0:0a673c671a56 3603 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
ebrus 0:0a673c671a56 3604 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
ebrus 0:0a673c671a56 3605 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
ebrus 0:0a673c671a56 3606
ebrus 0:0a673c671a56 3607 /****************** Bit definition for FSMC_BCR4 register *******************/
ebrus 0:0a673c671a56 3608 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
ebrus 0:0a673c671a56 3609 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
ebrus 0:0a673c671a56 3610
ebrus 0:0a673c671a56 3611 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
ebrus 0:0a673c671a56 3612 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
ebrus 0:0a673c671a56 3613 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
ebrus 0:0a673c671a56 3614
ebrus 0:0a673c671a56 3615 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
ebrus 0:0a673c671a56 3616 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3617 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3618
ebrus 0:0a673c671a56 3619 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
ebrus 0:0a673c671a56 3620 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
ebrus 0:0a673c671a56 3621 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
ebrus 0:0a673c671a56 3622 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
ebrus 0:0a673c671a56 3623 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
ebrus 0:0a673c671a56 3624 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
ebrus 0:0a673c671a56 3625 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
ebrus 0:0a673c671a56 3626 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
ebrus 0:0a673c671a56 3627 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
ebrus 0:0a673c671a56 3628 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
ebrus 0:0a673c671a56 3629
ebrus 0:0a673c671a56 3630 /****************** Bit definition for FSMC_BTR1 register ******************/
ebrus 0:0a673c671a56 3631 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:0a673c671a56 3632 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 3633 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 3634 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 3635 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 3636
ebrus 0:0a673c671a56 3637 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:0a673c671a56 3638 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3639 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3640 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:0a673c671a56 3641 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:0a673c671a56 3642
ebrus 0:0a673c671a56 3643 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:0a673c671a56 3644 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 3645 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 3646 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 3647 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 3648
ebrus 0:0a673c671a56 3649 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
ebrus 0:0a673c671a56 3650 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3651 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3652 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3653 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3654
ebrus 0:0a673c671a56 3655 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:0a673c671a56 3656 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3657 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3658 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3659 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3660
ebrus 0:0a673c671a56 3661 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:0a673c671a56 3662 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3663 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3664 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3665 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3666
ebrus 0:0a673c671a56 3667 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:0a673c671a56 3668 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3669 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3670
ebrus 0:0a673c671a56 3671 /****************** Bit definition for FSMC_BTR2 register *******************/
ebrus 0:0a673c671a56 3672 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:0a673c671a56 3673 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 3674 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 3675 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 3676 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 3677
ebrus 0:0a673c671a56 3678 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:0a673c671a56 3679 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3680 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3681 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:0a673c671a56 3682 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:0a673c671a56 3683
ebrus 0:0a673c671a56 3684 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:0a673c671a56 3685 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 3686 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 3687 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 3688 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 3689
ebrus 0:0a673c671a56 3690 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
ebrus 0:0a673c671a56 3691 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3692 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3693 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3694 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3695
ebrus 0:0a673c671a56 3696 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:0a673c671a56 3697 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3698 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3699 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3700 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3701
ebrus 0:0a673c671a56 3702 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:0a673c671a56 3703 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3704 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3705 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3706 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3707
ebrus 0:0a673c671a56 3708 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:0a673c671a56 3709 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3710 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3711
ebrus 0:0a673c671a56 3712 /******************* Bit definition for FSMC_BTR3 register *******************/
ebrus 0:0a673c671a56 3713 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:0a673c671a56 3714 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 3715 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 3716 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 3717 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 3718
ebrus 0:0a673c671a56 3719 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:0a673c671a56 3720 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3721 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3722 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:0a673c671a56 3723 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:0a673c671a56 3724
ebrus 0:0a673c671a56 3725 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:0a673c671a56 3726 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 3727 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 3728 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 3729 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 3730
ebrus 0:0a673c671a56 3731 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
ebrus 0:0a673c671a56 3732 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3733 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3734 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3735 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3736
ebrus 0:0a673c671a56 3737 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:0a673c671a56 3738 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3739 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3740 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3741 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3742
ebrus 0:0a673c671a56 3743 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:0a673c671a56 3744 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3745 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3746 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3747 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3748
ebrus 0:0a673c671a56 3749 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:0a673c671a56 3750 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3751 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3752
ebrus 0:0a673c671a56 3753 /****************** Bit definition for FSMC_BTR4 register *******************/
ebrus 0:0a673c671a56 3754 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:0a673c671a56 3755 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 3756 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 3757 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 3758 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 3759
ebrus 0:0a673c671a56 3760 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:0a673c671a56 3761 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3762 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3763 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:0a673c671a56 3764 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:0a673c671a56 3765
ebrus 0:0a673c671a56 3766 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:0a673c671a56 3767 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 3768 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 3769 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 3770 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 3771
ebrus 0:0a673c671a56 3772 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
ebrus 0:0a673c671a56 3773 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3774 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3775 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3776 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3777
ebrus 0:0a673c671a56 3778 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:0a673c671a56 3779 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3780 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3781 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3782 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3783
ebrus 0:0a673c671a56 3784 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:0a673c671a56 3785 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3786 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3787 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3788 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3789
ebrus 0:0a673c671a56 3790 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:0a673c671a56 3791 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3792 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3793
ebrus 0:0a673c671a56 3794 /****************** Bit definition for FSMC_BWTR1 register ******************/
ebrus 0:0a673c671a56 3795 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:0a673c671a56 3796 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 3797 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 3798 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 3799 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 3800
ebrus 0:0a673c671a56 3801 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:0a673c671a56 3802 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3803 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3804 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:0a673c671a56 3805 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:0a673c671a56 3806
ebrus 0:0a673c671a56 3807 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:0a673c671a56 3808 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 3809 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 3810 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 3811 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 3812
ebrus 0:0a673c671a56 3813 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:0a673c671a56 3814 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3815 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3816 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3817 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3818
ebrus 0:0a673c671a56 3819 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:0a673c671a56 3820 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3821 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3822 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3823 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3824
ebrus 0:0a673c671a56 3825 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:0a673c671a56 3826 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3827 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3828
ebrus 0:0a673c671a56 3829 /****************** Bit definition for FSMC_BWTR2 register ******************/
ebrus 0:0a673c671a56 3830 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:0a673c671a56 3831 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 3832 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 3833 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 3834 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 3835
ebrus 0:0a673c671a56 3836 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:0a673c671a56 3837 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3838 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3839 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:0a673c671a56 3840 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:0a673c671a56 3841
ebrus 0:0a673c671a56 3842 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:0a673c671a56 3843 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 3844 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 3845 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 3846 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 3847
ebrus 0:0a673c671a56 3848 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:0a673c671a56 3849 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3850 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
ebrus 0:0a673c671a56 3851 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3852 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3853
ebrus 0:0a673c671a56 3854 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:0a673c671a56 3855 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3856 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3857 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3858 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3859
ebrus 0:0a673c671a56 3860 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:0a673c671a56 3861 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3862 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3863
ebrus 0:0a673c671a56 3864 /****************** Bit definition for FSMC_BWTR3 register ******************/
ebrus 0:0a673c671a56 3865 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:0a673c671a56 3866 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 3867 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 3868 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 3869 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 3870
ebrus 0:0a673c671a56 3871 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:0a673c671a56 3872 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3873 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3874 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:0a673c671a56 3875 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:0a673c671a56 3876
ebrus 0:0a673c671a56 3877 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:0a673c671a56 3878 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 3879 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 3880 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 3881 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 3882
ebrus 0:0a673c671a56 3883 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:0a673c671a56 3884 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3885 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3886 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3887 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3888
ebrus 0:0a673c671a56 3889 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:0a673c671a56 3890 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3891 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3892 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3893 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3894
ebrus 0:0a673c671a56 3895 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:0a673c671a56 3896 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3897 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3898
ebrus 0:0a673c671a56 3899 /****************** Bit definition for FSMC_BWTR4 register ******************/
ebrus 0:0a673c671a56 3900 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:0a673c671a56 3901 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 3902 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 3903 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 3904 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 3905
ebrus 0:0a673c671a56 3906 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:0a673c671a56 3907 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3908 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3909 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:0a673c671a56 3910 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:0a673c671a56 3911
ebrus 0:0a673c671a56 3912 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:0a673c671a56 3913 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 3914 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 3915 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 3916 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 3917
ebrus 0:0a673c671a56 3918 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:0a673c671a56 3919 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3920 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3921 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3922 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3923
ebrus 0:0a673c671a56 3924 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:0a673c671a56 3925 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3926 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3927 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3928 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3929
ebrus 0:0a673c671a56 3930 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:0a673c671a56 3931 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3932 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3933
ebrus 0:0a673c671a56 3934 /****************** Bit definition for FSMC_PCR2 register *******************/
ebrus 0:0a673c671a56 3935 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
ebrus 0:0a673c671a56 3936 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
ebrus 0:0a673c671a56 3937 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
ebrus 0:0a673c671a56 3938
ebrus 0:0a673c671a56 3939 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
ebrus 0:0a673c671a56 3940 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3941 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3942
ebrus 0:0a673c671a56 3943 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
ebrus 0:0a673c671a56 3944
ebrus 0:0a673c671a56 3945 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
ebrus 0:0a673c671a56 3946 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
ebrus 0:0a673c671a56 3947 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
ebrus 0:0a673c671a56 3948 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
ebrus 0:0a673c671a56 3949 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3950
ebrus 0:0a673c671a56 3951 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
ebrus 0:0a673c671a56 3952 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3953 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3954 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3955 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3956
ebrus 0:0a673c671a56 3957 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
ebrus 0:0a673c671a56 3958 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3959 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3960 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3961
ebrus 0:0a673c671a56 3962 /****************** Bit definition for FSMC_PCR3 register *******************/
ebrus 0:0a673c671a56 3963 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
ebrus 0:0a673c671a56 3964 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
ebrus 0:0a673c671a56 3965 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
ebrus 0:0a673c671a56 3966
ebrus 0:0a673c671a56 3967 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
ebrus 0:0a673c671a56 3968 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3969 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3970
ebrus 0:0a673c671a56 3971 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
ebrus 0:0a673c671a56 3972
ebrus 0:0a673c671a56 3973 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
ebrus 0:0a673c671a56 3974 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
ebrus 0:0a673c671a56 3975 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
ebrus 0:0a673c671a56 3976 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
ebrus 0:0a673c671a56 3977 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3978
ebrus 0:0a673c671a56 3979 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
ebrus 0:0a673c671a56 3980 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3981 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3982 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3983 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
ebrus 0:0a673c671a56 3984
ebrus 0:0a673c671a56 3985 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
ebrus 0:0a673c671a56 3986 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
ebrus 0:0a673c671a56 3987 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
ebrus 0:0a673c671a56 3988 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
ebrus 0:0a673c671a56 3989
ebrus 0:0a673c671a56 3990 /****************** Bit definition for FSMC_PCR4 register *******************/
ebrus 0:0a673c671a56 3991 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
ebrus 0:0a673c671a56 3992 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
ebrus 0:0a673c671a56 3993 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
ebrus 0:0a673c671a56 3994
ebrus 0:0a673c671a56 3995 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
ebrus 0:0a673c671a56 3996 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:0a673c671a56 3997 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:0a673c671a56 3998
ebrus 0:0a673c671a56 3999 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
ebrus 0:0a673c671a56 4000
ebrus 0:0a673c671a56 4001 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
ebrus 0:0a673c671a56 4002 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
ebrus 0:0a673c671a56 4003 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
ebrus 0:0a673c671a56 4004 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
ebrus 0:0a673c671a56 4005 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4006
ebrus 0:0a673c671a56 4007 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
ebrus 0:0a673c671a56 4008 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4009 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4010 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4011 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4012
ebrus 0:0a673c671a56 4013 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
ebrus 0:0a673c671a56 4014 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4015 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4016 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4017
ebrus 0:0a673c671a56 4018 /******************* Bit definition for FSMC_SR2 register *******************/
ebrus 0:0a673c671a56 4019 #define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
ebrus 0:0a673c671a56 4020 #define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
ebrus 0:0a673c671a56 4021 #define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
ebrus 0:0a673c671a56 4022 #define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
ebrus 0:0a673c671a56 4023 #define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
ebrus 0:0a673c671a56 4024 #define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
ebrus 0:0a673c671a56 4025 #define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
ebrus 0:0a673c671a56 4026
ebrus 0:0a673c671a56 4027 /******************* Bit definition for FSMC_SR3 register *******************/
ebrus 0:0a673c671a56 4028 #define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
ebrus 0:0a673c671a56 4029 #define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
ebrus 0:0a673c671a56 4030 #define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
ebrus 0:0a673c671a56 4031 #define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
ebrus 0:0a673c671a56 4032 #define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
ebrus 0:0a673c671a56 4033 #define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
ebrus 0:0a673c671a56 4034 #define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
ebrus 0:0a673c671a56 4035
ebrus 0:0a673c671a56 4036 /******************* Bit definition for FSMC_SR4 register *******************/
ebrus 0:0a673c671a56 4037 #define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
ebrus 0:0a673c671a56 4038 #define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
ebrus 0:0a673c671a56 4039 #define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
ebrus 0:0a673c671a56 4040 #define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
ebrus 0:0a673c671a56 4041 #define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
ebrus 0:0a673c671a56 4042 #define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
ebrus 0:0a673c671a56 4043 #define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
ebrus 0:0a673c671a56 4044
ebrus 0:0a673c671a56 4045 /****************** Bit definition for FSMC_PMEM2 register ******************/
ebrus 0:0a673c671a56 4046 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
ebrus 0:0a673c671a56 4047 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 4048 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 4049 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 4050 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 4051 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 4052 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:0a673c671a56 4053 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:0a673c671a56 4054 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:0a673c671a56 4055
ebrus 0:0a673c671a56 4056 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
ebrus 0:0a673c671a56 4057 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 4058 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 4059 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 4060 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 4061 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4062 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4063 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4064 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4065
ebrus 0:0a673c671a56 4066 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
ebrus 0:0a673c671a56 4067 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4068 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4069 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4070 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4071 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4072 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4073 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4074 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4075
ebrus 0:0a673c671a56 4076 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
ebrus 0:0a673c671a56 4077 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4078 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4079 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4080 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4081 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4082 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4083 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4084 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4085
ebrus 0:0a673c671a56 4086 /****************** Bit definition for FSMC_PMEM3 register ******************/
ebrus 0:0a673c671a56 4087 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
ebrus 0:0a673c671a56 4088 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 4089 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 4090 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 4091 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 4092 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 4093 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:0a673c671a56 4094 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:0a673c671a56 4095 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:0a673c671a56 4096
ebrus 0:0a673c671a56 4097 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
ebrus 0:0a673c671a56 4098 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 4099 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 4100 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 4101 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 4102 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4103 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4104 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4105 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4106
ebrus 0:0a673c671a56 4107 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
ebrus 0:0a673c671a56 4108 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4109 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4110 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4111 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4112 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4113 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4114 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4115 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4116
ebrus 0:0a673c671a56 4117 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
ebrus 0:0a673c671a56 4118 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4119 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4120 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4121 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4122 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4123 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4124 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4125 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4126
ebrus 0:0a673c671a56 4127 /****************** Bit definition for FSMC_PMEM4 register ******************/
ebrus 0:0a673c671a56 4128 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
ebrus 0:0a673c671a56 4129 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 4130 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 4131 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 4132 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 4133 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 4134 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:0a673c671a56 4135 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:0a673c671a56 4136 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:0a673c671a56 4137
ebrus 0:0a673c671a56 4138 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
ebrus 0:0a673c671a56 4139 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 4140 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 4141 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 4142 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 4143 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4144 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4145 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4146 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4147
ebrus 0:0a673c671a56 4148 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
ebrus 0:0a673c671a56 4149 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4150 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4151 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4152 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4153 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4154 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4155 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4156 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4157
ebrus 0:0a673c671a56 4158 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
ebrus 0:0a673c671a56 4159 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4160 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4161 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4162 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4163 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4164 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4165 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4166 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4167
ebrus 0:0a673c671a56 4168 /****************** Bit definition for FSMC_PATT2 register ******************/
ebrus 0:0a673c671a56 4169 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
ebrus 0:0a673c671a56 4170 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 4171 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 4172 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 4173 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 4174 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 4175 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:0a673c671a56 4176 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:0a673c671a56 4177 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:0a673c671a56 4178
ebrus 0:0a673c671a56 4179 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
ebrus 0:0a673c671a56 4180 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 4181 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 4182 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 4183 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 4184 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4185 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4186 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4187 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4188
ebrus 0:0a673c671a56 4189 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
ebrus 0:0a673c671a56 4190 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4191 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4192 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4193 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4194 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4195 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4196 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4197 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4198
ebrus 0:0a673c671a56 4199 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
ebrus 0:0a673c671a56 4200 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4201 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4202 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4203 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4204 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4205 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4206 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4207 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4208
ebrus 0:0a673c671a56 4209 /****************** Bit definition for FSMC_PATT3 register ******************/
ebrus 0:0a673c671a56 4210 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
ebrus 0:0a673c671a56 4211 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 4212 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 4213 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 4214 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 4215 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 4216 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:0a673c671a56 4217 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:0a673c671a56 4218 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:0a673c671a56 4219
ebrus 0:0a673c671a56 4220 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
ebrus 0:0a673c671a56 4221 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 4222 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 4223 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 4224 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 4225 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4226 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4227 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4228 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4229
ebrus 0:0a673c671a56 4230 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
ebrus 0:0a673c671a56 4231 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4232 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4233 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4234 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4235 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4236 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4237 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4238 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4239
ebrus 0:0a673c671a56 4240 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
ebrus 0:0a673c671a56 4241 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4242 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4243 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4244 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4245 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4246 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4247 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4248 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4249
ebrus 0:0a673c671a56 4250 /****************** Bit definition for FSMC_PATT4 register ******************/
ebrus 0:0a673c671a56 4251 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
ebrus 0:0a673c671a56 4252 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 4253 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 4254 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 4255 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 4256 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 4257 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:0a673c671a56 4258 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:0a673c671a56 4259 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:0a673c671a56 4260
ebrus 0:0a673c671a56 4261 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
ebrus 0:0a673c671a56 4262 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 4263 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 4264 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 4265 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 4266 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4267 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4268 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4269 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4270
ebrus 0:0a673c671a56 4271 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
ebrus 0:0a673c671a56 4272 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4273 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4274 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4275 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4276 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4277 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4278 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4279 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4280
ebrus 0:0a673c671a56 4281 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
ebrus 0:0a673c671a56 4282 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4283 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4284 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4285 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4286 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4287 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4288 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4289 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4290
ebrus 0:0a673c671a56 4291 /****************** Bit definition for FSMC_PIO4 register *******************/
ebrus 0:0a673c671a56 4292 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
ebrus 0:0a673c671a56 4293 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:0a673c671a56 4294 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:0a673c671a56 4295 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:0a673c671a56 4296 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:0a673c671a56 4297 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:0a673c671a56 4298 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:0a673c671a56 4299 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:0a673c671a56 4300 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:0a673c671a56 4301
ebrus 0:0a673c671a56 4302 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
ebrus 0:0a673c671a56 4303 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:0a673c671a56 4304 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:0a673c671a56 4305 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:0a673c671a56 4306 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:0a673c671a56 4307 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4308 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4309 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4310 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4311
ebrus 0:0a673c671a56 4312 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
ebrus 0:0a673c671a56 4313 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4314 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4315 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4316 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4317 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4318 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4319 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4320 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4321
ebrus 0:0a673c671a56 4322 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
ebrus 0:0a673c671a56 4323 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:0a673c671a56 4324 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:0a673c671a56 4325 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:0a673c671a56 4326 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:0a673c671a56 4327 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:0a673c671a56 4328 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:0a673c671a56 4329 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:0a673c671a56 4330 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:0a673c671a56 4331
ebrus 0:0a673c671a56 4332 /****************** Bit definition for FSMC_ECCR2 register ******************/
ebrus 0:0a673c671a56 4333 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
ebrus 0:0a673c671a56 4334
ebrus 0:0a673c671a56 4335 /****************** Bit definition for FSMC_ECCR3 register ******************/
ebrus 0:0a673c671a56 4336 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
ebrus 0:0a673c671a56 4337
ebrus 0:0a673c671a56 4338
ebrus 0:0a673c671a56 4339 /******************************************************************************/
ebrus 0:0a673c671a56 4340 /* */
ebrus 0:0a673c671a56 4341 /* General Purpose I/O */
ebrus 0:0a673c671a56 4342 /* */
ebrus 0:0a673c671a56 4343 /******************************************************************************/
ebrus 0:0a673c671a56 4344 /****************** Bits definition for GPIO_MODER register *****************/
ebrus 0:0a673c671a56 4345 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
ebrus 0:0a673c671a56 4346 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 4347 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 4348
ebrus 0:0a673c671a56 4349 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
ebrus 0:0a673c671a56 4350 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 4351 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 4352
ebrus 0:0a673c671a56 4353 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
ebrus 0:0a673c671a56 4354 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 4355 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 4356
ebrus 0:0a673c671a56 4357 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
ebrus 0:0a673c671a56 4358 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 4359 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 4360
ebrus 0:0a673c671a56 4361 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
ebrus 0:0a673c671a56 4362 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 4363 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 4364
ebrus 0:0a673c671a56 4365 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
ebrus 0:0a673c671a56 4366 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 4367 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 4368
ebrus 0:0a673c671a56 4369 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
ebrus 0:0a673c671a56 4370 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 4371 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 4372
ebrus 0:0a673c671a56 4373 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
ebrus 0:0a673c671a56 4374 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 4375 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 4376
ebrus 0:0a673c671a56 4377 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
ebrus 0:0a673c671a56 4378 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 4379 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 4380
ebrus 0:0a673c671a56 4381 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
ebrus 0:0a673c671a56 4382 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 4383 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 4384
ebrus 0:0a673c671a56 4385 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
ebrus 0:0a673c671a56 4386 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 4387 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 4388
ebrus 0:0a673c671a56 4389 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
ebrus 0:0a673c671a56 4390 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 4391 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 4392
ebrus 0:0a673c671a56 4393 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
ebrus 0:0a673c671a56 4394 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 4395 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 4396
ebrus 0:0a673c671a56 4397 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
ebrus 0:0a673c671a56 4398 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 4399 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 4400
ebrus 0:0a673c671a56 4401 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
ebrus 0:0a673c671a56 4402 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 4403 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 4404
ebrus 0:0a673c671a56 4405 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
ebrus 0:0a673c671a56 4406 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 4407 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 4408
ebrus 0:0a673c671a56 4409 /****************** Bits definition for GPIO_OTYPER register ****************/
ebrus 0:0a673c671a56 4410 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 4411 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 4412 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 4413 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 4414 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 4415 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 4416 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 4417 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 4418 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 4419 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 4420 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 4421 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 4422 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 4423 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 4424 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 4425 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 4426
ebrus 0:0a673c671a56 4427 /****************** Bits definition for GPIO_OSPEEDR register ***************/
ebrus 0:0a673c671a56 4428 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
ebrus 0:0a673c671a56 4429 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 4430 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 4431
ebrus 0:0a673c671a56 4432 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
ebrus 0:0a673c671a56 4433 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 4434 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 4435
ebrus 0:0a673c671a56 4436 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
ebrus 0:0a673c671a56 4437 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 4438 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 4439
ebrus 0:0a673c671a56 4440 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
ebrus 0:0a673c671a56 4441 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 4442 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 4443
ebrus 0:0a673c671a56 4444 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
ebrus 0:0a673c671a56 4445 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 4446 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 4447
ebrus 0:0a673c671a56 4448 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
ebrus 0:0a673c671a56 4449 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 4450 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 4451
ebrus 0:0a673c671a56 4452 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
ebrus 0:0a673c671a56 4453 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 4454 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 4455
ebrus 0:0a673c671a56 4456 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
ebrus 0:0a673c671a56 4457 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 4458 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 4459
ebrus 0:0a673c671a56 4460 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
ebrus 0:0a673c671a56 4461 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 4462 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 4463
ebrus 0:0a673c671a56 4464 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
ebrus 0:0a673c671a56 4465 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 4466 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 4467
ebrus 0:0a673c671a56 4468 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
ebrus 0:0a673c671a56 4469 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 4470 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 4471
ebrus 0:0a673c671a56 4472 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
ebrus 0:0a673c671a56 4473 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 4474 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 4475
ebrus 0:0a673c671a56 4476 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
ebrus 0:0a673c671a56 4477 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 4478 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 4479
ebrus 0:0a673c671a56 4480 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
ebrus 0:0a673c671a56 4481 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 4482 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 4483
ebrus 0:0a673c671a56 4484 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
ebrus 0:0a673c671a56 4485 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 4486 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 4487
ebrus 0:0a673c671a56 4488 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
ebrus 0:0a673c671a56 4489 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 4490 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 4491
ebrus 0:0a673c671a56 4492 /****************** Bits definition for GPIO_PUPDR register *****************/
ebrus 0:0a673c671a56 4493 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
ebrus 0:0a673c671a56 4494 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 4495 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 4496
ebrus 0:0a673c671a56 4497 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
ebrus 0:0a673c671a56 4498 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 4499 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 4500
ebrus 0:0a673c671a56 4501 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
ebrus 0:0a673c671a56 4502 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 4503 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 4504
ebrus 0:0a673c671a56 4505 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
ebrus 0:0a673c671a56 4506 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 4507 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 4508
ebrus 0:0a673c671a56 4509 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
ebrus 0:0a673c671a56 4510 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 4511 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 4512
ebrus 0:0a673c671a56 4513 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
ebrus 0:0a673c671a56 4514 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 4515 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 4516
ebrus 0:0a673c671a56 4517 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
ebrus 0:0a673c671a56 4518 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 4519 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 4520
ebrus 0:0a673c671a56 4521 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
ebrus 0:0a673c671a56 4522 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 4523 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 4524
ebrus 0:0a673c671a56 4525 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
ebrus 0:0a673c671a56 4526 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 4527 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 4528
ebrus 0:0a673c671a56 4529 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
ebrus 0:0a673c671a56 4530 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 4531 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 4532
ebrus 0:0a673c671a56 4533 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
ebrus 0:0a673c671a56 4534 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 4535 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 4536
ebrus 0:0a673c671a56 4537 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
ebrus 0:0a673c671a56 4538 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 4539 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 4540
ebrus 0:0a673c671a56 4541 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
ebrus 0:0a673c671a56 4542 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 4543 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 4544
ebrus 0:0a673c671a56 4545 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
ebrus 0:0a673c671a56 4546 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 4547 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 4548
ebrus 0:0a673c671a56 4549 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
ebrus 0:0a673c671a56 4550 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 4551 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 4552
ebrus 0:0a673c671a56 4553 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
ebrus 0:0a673c671a56 4554 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 4555 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 4556
ebrus 0:0a673c671a56 4557 /****************** Bits definition for GPIO_IDR register *******************/
ebrus 0:0a673c671a56 4558 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 4559 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 4560 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 4561 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 4562 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 4563 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 4564 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 4565 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 4566 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 4567 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 4568 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 4569 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 4570 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 4571 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 4572 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 4573 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 4574 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
ebrus 0:0a673c671a56 4575 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
ebrus 0:0a673c671a56 4576 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
ebrus 0:0a673c671a56 4577 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
ebrus 0:0a673c671a56 4578 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
ebrus 0:0a673c671a56 4579 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
ebrus 0:0a673c671a56 4580 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
ebrus 0:0a673c671a56 4581 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
ebrus 0:0a673c671a56 4582 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
ebrus 0:0a673c671a56 4583 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
ebrus 0:0a673c671a56 4584 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
ebrus 0:0a673c671a56 4585 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
ebrus 0:0a673c671a56 4586 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
ebrus 0:0a673c671a56 4587 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
ebrus 0:0a673c671a56 4588 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
ebrus 0:0a673c671a56 4589 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
ebrus 0:0a673c671a56 4590 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
ebrus 0:0a673c671a56 4591
ebrus 0:0a673c671a56 4592 /****************** Bits definition for GPIO_ODR register *******************/
ebrus 0:0a673c671a56 4593 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 4594 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 4595 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 4596 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 4597 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 4598 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 4599 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 4600 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 4601 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 4602 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 4603 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 4604 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 4605 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 4606 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 4607 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 4608 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 4609 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
ebrus 0:0a673c671a56 4610 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
ebrus 0:0a673c671a56 4611 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
ebrus 0:0a673c671a56 4612 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
ebrus 0:0a673c671a56 4613 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
ebrus 0:0a673c671a56 4614 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
ebrus 0:0a673c671a56 4615 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
ebrus 0:0a673c671a56 4616 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
ebrus 0:0a673c671a56 4617 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
ebrus 0:0a673c671a56 4618 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
ebrus 0:0a673c671a56 4619 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
ebrus 0:0a673c671a56 4620 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
ebrus 0:0a673c671a56 4621 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
ebrus 0:0a673c671a56 4622 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
ebrus 0:0a673c671a56 4623 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
ebrus 0:0a673c671a56 4624 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
ebrus 0:0a673c671a56 4625 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
ebrus 0:0a673c671a56 4626
ebrus 0:0a673c671a56 4627 /****************** Bits definition for GPIO_BSRR register ******************/
ebrus 0:0a673c671a56 4628 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 4629 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 4630 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 4631 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 4632 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 4633 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 4634 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 4635 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 4636 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 4637 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 4638 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 4639 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 4640 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 4641 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 4642 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 4643 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 4644 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 4645 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 4646 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 4647 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 4648 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 4649 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 4650 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 4651 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 4652 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 4653 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 4654 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 4655 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 4656 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 4657 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 4658 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 4659 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 4660
ebrus 0:0a673c671a56 4661 /******************************************************************************/
ebrus 0:0a673c671a56 4662 /* */
ebrus 0:0a673c671a56 4663 /* HASH */
ebrus 0:0a673c671a56 4664 /* */
ebrus 0:0a673c671a56 4665 /******************************************************************************/
ebrus 0:0a673c671a56 4666 /****************** Bits definition for HASH_CR register ********************/
ebrus 0:0a673c671a56 4667 #define HASH_CR_INIT ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 4668 #define HASH_CR_DMAE ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 4669 #define HASH_CR_DATATYPE ((uint32_t)0x00000030)
ebrus 0:0a673c671a56 4670 #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 4671 #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 4672 #define HASH_CR_MODE ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 4673 #define HASH_CR_ALGO ((uint32_t)0x00040080)
ebrus 0:0a673c671a56 4674 #define HASH_CR_ALGO_0 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 4675 #define HASH_CR_ALGO_1 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 4676 #define HASH_CR_NBW ((uint32_t)0x00000F00)
ebrus 0:0a673c671a56 4677 #define HASH_CR_NBW_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 4678 #define HASH_CR_NBW_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 4679 #define HASH_CR_NBW_2 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 4680 #define HASH_CR_NBW_3 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 4681 #define HASH_CR_DINNE ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 4682 #define HASH_CR_MDMAT ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 4683 #define HASH_CR_LKEY ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 4684
ebrus 0:0a673c671a56 4685 /****************** Bits definition for HASH_STR register *******************/
ebrus 0:0a673c671a56 4686 #define HASH_STR_NBW ((uint32_t)0x0000001F)
ebrus 0:0a673c671a56 4687 #define HASH_STR_NBW_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 4688 #define HASH_STR_NBW_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 4689 #define HASH_STR_NBW_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 4690 #define HASH_STR_NBW_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 4691 #define HASH_STR_NBW_4 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 4692 #define HASH_STR_DCAL ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 4693
ebrus 0:0a673c671a56 4694 /****************** Bits definition for HASH_IMR register *******************/
ebrus 0:0a673c671a56 4695 #define HASH_IMR_DINIM ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 4696 #define HASH_IMR_DCIM ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 4697
ebrus 0:0a673c671a56 4698 /****************** Bits definition for HASH_SR register ********************/
ebrus 0:0a673c671a56 4699 #define HASH_SR_DINIS ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 4700 #define HASH_SR_DCIS ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 4701 #define HASH_SR_DMAS ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 4702 #define HASH_SR_BUSY ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 4703
ebrus 0:0a673c671a56 4704 /******************************************************************************/
ebrus 0:0a673c671a56 4705 /* */
ebrus 0:0a673c671a56 4706 /* Inter-integrated Circuit Interface */
ebrus 0:0a673c671a56 4707 /* */
ebrus 0:0a673c671a56 4708 /******************************************************************************/
ebrus 0:0a673c671a56 4709 /******************* Bit definition for I2C_CR1 register ********************/
ebrus 0:0a673c671a56 4710 #define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
ebrus 0:0a673c671a56 4711 #define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
ebrus 0:0a673c671a56 4712 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
ebrus 0:0a673c671a56 4713 #define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
ebrus 0:0a673c671a56 4714 #define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
ebrus 0:0a673c671a56 4715 #define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
ebrus 0:0a673c671a56 4716 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
ebrus 0:0a673c671a56 4717 #define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
ebrus 0:0a673c671a56 4718 #define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
ebrus 0:0a673c671a56 4719 #define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
ebrus 0:0a673c671a56 4720 #define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
ebrus 0:0a673c671a56 4721 #define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
ebrus 0:0a673c671a56 4722 #define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
ebrus 0:0a673c671a56 4723 #define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
ebrus 0:0a673c671a56 4724
ebrus 0:0a673c671a56 4725 /******************* Bit definition for I2C_CR2 register ********************/
ebrus 0:0a673c671a56 4726 #define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
ebrus 0:0a673c671a56 4727 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
ebrus 0:0a673c671a56 4728 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
ebrus 0:0a673c671a56 4729 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
ebrus 0:0a673c671a56 4730 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
ebrus 0:0a673c671a56 4731 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
ebrus 0:0a673c671a56 4732 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
ebrus 0:0a673c671a56 4733
ebrus 0:0a673c671a56 4734 #define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
ebrus 0:0a673c671a56 4735 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
ebrus 0:0a673c671a56 4736 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
ebrus 0:0a673c671a56 4737 #define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
ebrus 0:0a673c671a56 4738 #define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
ebrus 0:0a673c671a56 4739
ebrus 0:0a673c671a56 4740 /******************* Bit definition for I2C_OAR1 register *******************/
ebrus 0:0a673c671a56 4741 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
ebrus 0:0a673c671a56 4742 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
ebrus 0:0a673c671a56 4743
ebrus 0:0a673c671a56 4744 #define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
ebrus 0:0a673c671a56 4745 #define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
ebrus 0:0a673c671a56 4746 #define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
ebrus 0:0a673c671a56 4747 #define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
ebrus 0:0a673c671a56 4748 #define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
ebrus 0:0a673c671a56 4749 #define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
ebrus 0:0a673c671a56 4750 #define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
ebrus 0:0a673c671a56 4751 #define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
ebrus 0:0a673c671a56 4752 #define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
ebrus 0:0a673c671a56 4753 #define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
ebrus 0:0a673c671a56 4754
ebrus 0:0a673c671a56 4755 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
ebrus 0:0a673c671a56 4756
ebrus 0:0a673c671a56 4757 /******************* Bit definition for I2C_OAR2 register *******************/
ebrus 0:0a673c671a56 4758 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
ebrus 0:0a673c671a56 4759 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
ebrus 0:0a673c671a56 4760
ebrus 0:0a673c671a56 4761 /******************** Bit definition for I2C_DR register ********************/
ebrus 0:0a673c671a56 4762 #define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
ebrus 0:0a673c671a56 4763
ebrus 0:0a673c671a56 4764 /******************* Bit definition for I2C_SR1 register ********************/
ebrus 0:0a673c671a56 4765 #define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
ebrus 0:0a673c671a56 4766 #define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
ebrus 0:0a673c671a56 4767 #define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
ebrus 0:0a673c671a56 4768 #define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
ebrus 0:0a673c671a56 4769 #define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
ebrus 0:0a673c671a56 4770 #define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
ebrus 0:0a673c671a56 4771 #define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
ebrus 0:0a673c671a56 4772 #define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
ebrus 0:0a673c671a56 4773 #define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
ebrus 0:0a673c671a56 4774 #define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
ebrus 0:0a673c671a56 4775 #define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
ebrus 0:0a673c671a56 4776 #define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
ebrus 0:0a673c671a56 4777 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
ebrus 0:0a673c671a56 4778 #define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
ebrus 0:0a673c671a56 4779
ebrus 0:0a673c671a56 4780 /******************* Bit definition for I2C_SR2 register ********************/
ebrus 0:0a673c671a56 4781 #define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
ebrus 0:0a673c671a56 4782 #define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
ebrus 0:0a673c671a56 4783 #define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
ebrus 0:0a673c671a56 4784 #define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
ebrus 0:0a673c671a56 4785 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
ebrus 0:0a673c671a56 4786 #define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
ebrus 0:0a673c671a56 4787 #define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
ebrus 0:0a673c671a56 4788 #define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
ebrus 0:0a673c671a56 4789
ebrus 0:0a673c671a56 4790 /******************* Bit definition for I2C_CCR register ********************/
ebrus 0:0a673c671a56 4791 #define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
ebrus 0:0a673c671a56 4792 #define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
ebrus 0:0a673c671a56 4793 #define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
ebrus 0:0a673c671a56 4794
ebrus 0:0a673c671a56 4795 /****************** Bit definition for I2C_TRISE register *******************/
ebrus 0:0a673c671a56 4796 #define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
ebrus 0:0a673c671a56 4797
ebrus 0:0a673c671a56 4798 /****************** Bit definition for I2C_FLTR register *******************/
ebrus 0:0a673c671a56 4799 #define I2C_FLTR_DNF ((uint8_t)0x0F) /*!<Digital Noise Filter */
ebrus 0:0a673c671a56 4800 #define I2C_FLTR_ANOFF ((uint8_t)0x10) /*!<Analog Noise Filter OFF */
ebrus 0:0a673c671a56 4801
ebrus 0:0a673c671a56 4802 /******************************************************************************/
ebrus 0:0a673c671a56 4803 /* */
ebrus 0:0a673c671a56 4804 /* Independent WATCHDOG */
ebrus 0:0a673c671a56 4805 /* */
ebrus 0:0a673c671a56 4806 /******************************************************************************/
ebrus 0:0a673c671a56 4807 /******************* Bit definition for IWDG_KR register ********************/
ebrus 0:0a673c671a56 4808 #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
ebrus 0:0a673c671a56 4809
ebrus 0:0a673c671a56 4810 /******************* Bit definition for IWDG_PR register ********************/
ebrus 0:0a673c671a56 4811 #define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
ebrus 0:0a673c671a56 4812 #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
ebrus 0:0a673c671a56 4813 #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
ebrus 0:0a673c671a56 4814 #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
ebrus 0:0a673c671a56 4815
ebrus 0:0a673c671a56 4816 /******************* Bit definition for IWDG_RLR register *******************/
ebrus 0:0a673c671a56 4817 #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
ebrus 0:0a673c671a56 4818
ebrus 0:0a673c671a56 4819 /******************* Bit definition for IWDG_SR register ********************/
ebrus 0:0a673c671a56 4820 #define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
ebrus 0:0a673c671a56 4821 #define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
ebrus 0:0a673c671a56 4822
ebrus 0:0a673c671a56 4823
ebrus 0:0a673c671a56 4824 /******************************************************************************/
ebrus 0:0a673c671a56 4825 /* */
ebrus 0:0a673c671a56 4826 /* Power Control */
ebrus 0:0a673c671a56 4827 /* */
ebrus 0:0a673c671a56 4828 /******************************************************************************/
ebrus 0:0a673c671a56 4829 /******************** Bit definition for PWR_CR register ********************/
ebrus 0:0a673c671a56 4830 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
ebrus 0:0a673c671a56 4831 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
ebrus 0:0a673c671a56 4832 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
ebrus 0:0a673c671a56 4833 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
ebrus 0:0a673c671a56 4834 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
ebrus 0:0a673c671a56 4835
ebrus 0:0a673c671a56 4836 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
ebrus 0:0a673c671a56 4837 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
ebrus 0:0a673c671a56 4838 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
ebrus 0:0a673c671a56 4839 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
ebrus 0:0a673c671a56 4840
ebrus 0:0a673c671a56 4841 /*!< PVD level configuration */
ebrus 0:0a673c671a56 4842 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
ebrus 0:0a673c671a56 4843 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
ebrus 0:0a673c671a56 4844 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
ebrus 0:0a673c671a56 4845 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
ebrus 0:0a673c671a56 4846 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
ebrus 0:0a673c671a56 4847 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
ebrus 0:0a673c671a56 4848 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
ebrus 0:0a673c671a56 4849 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
ebrus 0:0a673c671a56 4850
ebrus 0:0a673c671a56 4851 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
ebrus 0:0a673c671a56 4852 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
ebrus 0:0a673c671a56 4853 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
ebrus 0:0a673c671a56 4854 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
ebrus 0:0a673c671a56 4855
ebrus 0:0a673c671a56 4856 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
ebrus 0:0a673c671a56 4857 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
ebrus 0:0a673c671a56 4858 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
ebrus 0:0a673c671a56 4859
ebrus 0:0a673c671a56 4860 /* Legacy define */
ebrus 0:0a673c671a56 4861 #define PWR_CR_PMODE PWR_CR_VOS
ebrus 0:0a673c671a56 4862
ebrus 0:0a673c671a56 4863 /******************* Bit definition for PWR_CSR register ********************/
ebrus 0:0a673c671a56 4864 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
ebrus 0:0a673c671a56 4865 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
ebrus 0:0a673c671a56 4866 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
ebrus 0:0a673c671a56 4867 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
ebrus 0:0a673c671a56 4868 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
ebrus 0:0a673c671a56 4869 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
ebrus 0:0a673c671a56 4870 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
ebrus 0:0a673c671a56 4871
ebrus 0:0a673c671a56 4872 /* Legacy define */
ebrus 0:0a673c671a56 4873 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
ebrus 0:0a673c671a56 4874
ebrus 0:0a673c671a56 4875 /******************************************************************************/
ebrus 0:0a673c671a56 4876 /* */
ebrus 0:0a673c671a56 4877 /* Reset and Clock Control */
ebrus 0:0a673c671a56 4878 /* */
ebrus 0:0a673c671a56 4879 /******************************************************************************/
ebrus 0:0a673c671a56 4880 /******************** Bit definition for RCC_CR register ********************/
ebrus 0:0a673c671a56 4881 #define RCC_CR_HSION ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 4882 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 4883
ebrus 0:0a673c671a56 4884 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
ebrus 0:0a673c671a56 4885 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
ebrus 0:0a673c671a56 4886 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
ebrus 0:0a673c671a56 4887 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
ebrus 0:0a673c671a56 4888 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
ebrus 0:0a673c671a56 4889 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
ebrus 0:0a673c671a56 4890
ebrus 0:0a673c671a56 4891 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
ebrus 0:0a673c671a56 4892 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
ebrus 0:0a673c671a56 4893 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
ebrus 0:0a673c671a56 4894 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
ebrus 0:0a673c671a56 4895 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
ebrus 0:0a673c671a56 4896 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
ebrus 0:0a673c671a56 4897 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
ebrus 0:0a673c671a56 4898 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
ebrus 0:0a673c671a56 4899 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
ebrus 0:0a673c671a56 4900
ebrus 0:0a673c671a56 4901 #define RCC_CR_HSEON ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 4902 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 4903 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 4904 #define RCC_CR_CSSON ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 4905 #define RCC_CR_PLLON ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 4906 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 4907 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 4908 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 4909
ebrus 0:0a673c671a56 4910
ebrus 0:0a673c671a56 4911 /******************** Bit definition for RCC_PLLCFGR register ***************/
ebrus 0:0a673c671a56 4912 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
ebrus 0:0a673c671a56 4913 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 4914 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 4915 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 4916 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 4917 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 4918 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 4919
ebrus 0:0a673c671a56 4920 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
ebrus 0:0a673c671a56 4921 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 4922 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 4923 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 4924 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 4925 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 4926 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 4927 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 4928 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 4929 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 4930
ebrus 0:0a673c671a56 4931 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
ebrus 0:0a673c671a56 4932 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 4933 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 4934
ebrus 0:0a673c671a56 4935 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 4936 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 4937 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 4938
ebrus 0:0a673c671a56 4939 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
ebrus 0:0a673c671a56 4940 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 4941 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 4942 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 4943 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 4944
ebrus 0:0a673c671a56 4945 /******************** Bit definition for RCC_CFGR register ******************/
ebrus 0:0a673c671a56 4946 /*!< SW configuration */
ebrus 0:0a673c671a56 4947 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
ebrus 0:0a673c671a56 4948 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
ebrus 0:0a673c671a56 4949 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
ebrus 0:0a673c671a56 4950
ebrus 0:0a673c671a56 4951 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
ebrus 0:0a673c671a56 4952 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
ebrus 0:0a673c671a56 4953 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
ebrus 0:0a673c671a56 4954
ebrus 0:0a673c671a56 4955 /*!< SWS configuration */
ebrus 0:0a673c671a56 4956 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
ebrus 0:0a673c671a56 4957 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
ebrus 0:0a673c671a56 4958 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
ebrus 0:0a673c671a56 4959
ebrus 0:0a673c671a56 4960 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
ebrus 0:0a673c671a56 4961 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
ebrus 0:0a673c671a56 4962 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
ebrus 0:0a673c671a56 4963
ebrus 0:0a673c671a56 4964 /*!< HPRE configuration */
ebrus 0:0a673c671a56 4965 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
ebrus 0:0a673c671a56 4966 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
ebrus 0:0a673c671a56 4967 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
ebrus 0:0a673c671a56 4968 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
ebrus 0:0a673c671a56 4969 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
ebrus 0:0a673c671a56 4970
ebrus 0:0a673c671a56 4971 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
ebrus 0:0a673c671a56 4972 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
ebrus 0:0a673c671a56 4973 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
ebrus 0:0a673c671a56 4974 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
ebrus 0:0a673c671a56 4975 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
ebrus 0:0a673c671a56 4976 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
ebrus 0:0a673c671a56 4977 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
ebrus 0:0a673c671a56 4978 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
ebrus 0:0a673c671a56 4979 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
ebrus 0:0a673c671a56 4980
ebrus 0:0a673c671a56 4981 /*!< PPRE1 configuration */
ebrus 0:0a673c671a56 4982 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
ebrus 0:0a673c671a56 4983 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
ebrus 0:0a673c671a56 4984 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
ebrus 0:0a673c671a56 4985 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
ebrus 0:0a673c671a56 4986
ebrus 0:0a673c671a56 4987 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
ebrus 0:0a673c671a56 4988 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
ebrus 0:0a673c671a56 4989 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
ebrus 0:0a673c671a56 4990 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
ebrus 0:0a673c671a56 4991 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
ebrus 0:0a673c671a56 4992
ebrus 0:0a673c671a56 4993 /*!< PPRE2 configuration */
ebrus 0:0a673c671a56 4994 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
ebrus 0:0a673c671a56 4995 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
ebrus 0:0a673c671a56 4996 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
ebrus 0:0a673c671a56 4997 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
ebrus 0:0a673c671a56 4998
ebrus 0:0a673c671a56 4999 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
ebrus 0:0a673c671a56 5000 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
ebrus 0:0a673c671a56 5001 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
ebrus 0:0a673c671a56 5002 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
ebrus 0:0a673c671a56 5003 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
ebrus 0:0a673c671a56 5004
ebrus 0:0a673c671a56 5005 /*!< RTCPRE configuration */
ebrus 0:0a673c671a56 5006 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
ebrus 0:0a673c671a56 5007 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5008 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5009 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5010 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 5011 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5012
ebrus 0:0a673c671a56 5013 /*!< MCO1 configuration */
ebrus 0:0a673c671a56 5014 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
ebrus 0:0a673c671a56 5015 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5016 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5017
ebrus 0:0a673c671a56 5018 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 5019
ebrus 0:0a673c671a56 5020 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
ebrus 0:0a673c671a56 5021 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 5022 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 5023 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 5024
ebrus 0:0a673c671a56 5025 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
ebrus 0:0a673c671a56 5026 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 5027 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 5028 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 5029
ebrus 0:0a673c671a56 5030 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
ebrus 0:0a673c671a56 5031 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 5032 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 5033
ebrus 0:0a673c671a56 5034 /******************** Bit definition for RCC_CIR register *******************/
ebrus 0:0a673c671a56 5035 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5036 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5037 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5038 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5039 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5040 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5041 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5042 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5043 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5044 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 5045 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5046 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5047 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5048 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5049 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5050 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5051 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 5052 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5053 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5054 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 5055
ebrus 0:0a673c671a56 5056 /******************** Bit definition for RCC_AHB1RSTR register **************/
ebrus 0:0a673c671a56 5057 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5058 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5059 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5060 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5061 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5062 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5063 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5064 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5065 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5066 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5067 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5068 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5069 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 5070 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 5071
ebrus 0:0a673c671a56 5072 /******************** Bit definition for RCC_AHB2RSTR register **************/
ebrus 0:0a673c671a56 5073 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5074 #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5075 #define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5076 /* maintained for legacy purpose */
ebrus 0:0a673c671a56 5077 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
ebrus 0:0a673c671a56 5078 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5079 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5080
ebrus 0:0a673c671a56 5081 /******************** Bit definition for RCC_AHB3RSTR register **************/
ebrus 0:0a673c671a56 5082 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5083
ebrus 0:0a673c671a56 5084 /******************** Bit definition for RCC_APB1RSTR register **************/
ebrus 0:0a673c671a56 5085 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5086 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5087 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5088 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5089 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5090 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5091 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5092 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5093 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5094 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5095 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5096 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 5097 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5098 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5099 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 5100 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5101 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5102 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5103 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 5104 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 5105 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 5106 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 5107 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 5108 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 5109 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 5110
ebrus 0:0a673c671a56 5111 /******************** Bit definition for RCC_APB2RSTR register **************/
ebrus 0:0a673c671a56 5112 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5113 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5114 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5115 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5116 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5117 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5118 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5119 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5120 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5121 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5122 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5123 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5124 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5125 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5126
ebrus 0:0a673c671a56 5127 /* Old SPI1RST bit definition, maintained for legacy purpose */
ebrus 0:0a673c671a56 5128 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
ebrus 0:0a673c671a56 5129
ebrus 0:0a673c671a56 5130 /******************** Bit definition for RCC_AHB1ENR register ***************/
ebrus 0:0a673c671a56 5131 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5132 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5133 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5134 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5135 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5136 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5137 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5138 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5139 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5140 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5141 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5142 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5143 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5144 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5145 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 5146 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 5147 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 5148 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 5149 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 5150 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 5151
ebrus 0:0a673c671a56 5152 /******************** Bit definition for RCC_AHB2ENR register ***************/
ebrus 0:0a673c671a56 5153 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5154 #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5155 #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5156 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5157 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5158
ebrus 0:0a673c671a56 5159 /******************** Bit definition for RCC_AHB3ENR register ***************/
ebrus 0:0a673c671a56 5160 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5161
ebrus 0:0a673c671a56 5162 /******************** Bit definition for RCC_APB1ENR register ***************/
ebrus 0:0a673c671a56 5163 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5164 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5165 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5166 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5167 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5168 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5169 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5170 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5171 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5172 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5173 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5174 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 5175 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5176 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5177 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 5178 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5179 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5180 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5181 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 5182 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 5183 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 5184 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 5185 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 5186 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 5187 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 5188
ebrus 0:0a673c671a56 5189 /******************** Bit definition for RCC_APB2ENR register ***************/
ebrus 0:0a673c671a56 5190 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5191 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5192 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5193 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5194 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5195 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5196 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 5197 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5198 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5199 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5200 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5201 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5202 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5203 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5204 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5205 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5206
ebrus 0:0a673c671a56 5207 /******************** Bit definition for RCC_AHB1LPENR register *************/
ebrus 0:0a673c671a56 5208 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5209 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5210 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5211 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5212 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5213 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5214 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5215 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5216 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5217 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5218 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 5219 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5220 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5221 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5222 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 5223 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5224 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5225 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 5226 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 5227 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 5228 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 5229 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 5230 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 5231
ebrus 0:0a673c671a56 5232 /******************** Bit definition for RCC_AHB2LPENR register *************/
ebrus 0:0a673c671a56 5233 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5234 #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5235 #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5236 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5237 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5238
ebrus 0:0a673c671a56 5239 /******************** Bit definition for RCC_AHB3LPENR register *************/
ebrus 0:0a673c671a56 5240 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5241
ebrus 0:0a673c671a56 5242 /******************** Bit definition for RCC_APB1LPENR register *************/
ebrus 0:0a673c671a56 5243 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5244 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5245 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5246 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5247 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5248 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5249 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5250 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5251 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5252 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5253 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5254 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 5255 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5256 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5257 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 5258 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5259 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5260 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5261 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 5262 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 5263 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 5264 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 5265 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 5266 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 5267 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 5268
ebrus 0:0a673c671a56 5269 /******************** Bit definition for RCC_APB2LPENR register *************/
ebrus 0:0a673c671a56 5270 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5271 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5272 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5273 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5274 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5275 #define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5276 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 5277 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5278 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5279 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5280 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5281 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5282 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5283 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5284 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5285 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5286
ebrus 0:0a673c671a56 5287 /******************** Bit definition for RCC_BDCR register ******************/
ebrus 0:0a673c671a56 5288 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5289 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5290 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5291
ebrus 0:0a673c671a56 5292 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
ebrus 0:0a673c671a56 5293 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5294 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5295
ebrus 0:0a673c671a56 5296 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 5297 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5298
ebrus 0:0a673c671a56 5299 /******************** Bit definition for RCC_CSR register *******************/
ebrus 0:0a673c671a56 5300 #define RCC_CSR_LSION ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5301 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5302 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 5303 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 5304 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 5305 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 5306 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 5307 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 5308 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 5309 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 5310
ebrus 0:0a673c671a56 5311 /******************** Bit definition for RCC_SSCGR register *****************/
ebrus 0:0a673c671a56 5312 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
ebrus 0:0a673c671a56 5313 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
ebrus 0:0a673c671a56 5314 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 5315 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 5316
ebrus 0:0a673c671a56 5317 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
ebrus 0:0a673c671a56 5318 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
ebrus 0:0a673c671a56 5319 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
ebrus 0:0a673c671a56 5320
ebrus 0:0a673c671a56 5321 /******************** Bit definition for RCC_DCKCFGR register ***************/
ebrus 0:0a673c671a56 5322 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 5323
ebrus 0:0a673c671a56 5324
ebrus 0:0a673c671a56 5325 /******************************************************************************/
ebrus 0:0a673c671a56 5326 /* */
ebrus 0:0a673c671a56 5327 /* RNG */
ebrus 0:0a673c671a56 5328 /* */
ebrus 0:0a673c671a56 5329 /******************************************************************************/
ebrus 0:0a673c671a56 5330 /******************** Bits definition for RNG_CR register *******************/
ebrus 0:0a673c671a56 5331 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5332 #define RNG_CR_IE ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5333
ebrus 0:0a673c671a56 5334 /******************** Bits definition for RNG_SR register *******************/
ebrus 0:0a673c671a56 5335 #define RNG_SR_DRDY ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5336 #define RNG_SR_CECS ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5337 #define RNG_SR_SECS ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5338 #define RNG_SR_CEIS ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5339 #define RNG_SR_SEIS ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5340
ebrus 0:0a673c671a56 5341 /******************************************************************************/
ebrus 0:0a673c671a56 5342 /* */
ebrus 0:0a673c671a56 5343 /* Real-Time Clock (RTC) */
ebrus 0:0a673c671a56 5344 /* */
ebrus 0:0a673c671a56 5345 /******************************************************************************/
ebrus 0:0a673c671a56 5346 /******************** Bits definition for RTC_TR register *******************/
ebrus 0:0a673c671a56 5347 #define RTC_TR_PM ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5348 #define RTC_TR_HT ((uint32_t)0x00300000)
ebrus 0:0a673c671a56 5349 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5350 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5351 #define RTC_TR_HU ((uint32_t)0x000F0000)
ebrus 0:0a673c671a56 5352 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5353 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5354 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5355 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 5356 #define RTC_TR_MNT ((uint32_t)0x00007000)
ebrus 0:0a673c671a56 5357 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5358 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5359 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5360 #define RTC_TR_MNU ((uint32_t)0x00000F00)
ebrus 0:0a673c671a56 5361 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5362 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5363 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 5364 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5365 #define RTC_TR_ST ((uint32_t)0x00000070)
ebrus 0:0a673c671a56 5366 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5367 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5368 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5369 #define RTC_TR_SU ((uint32_t)0x0000000F)
ebrus 0:0a673c671a56 5370 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5371 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5372 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5373 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5374
ebrus 0:0a673c671a56 5375 /******************** Bits definition for RTC_DR register *******************/
ebrus 0:0a673c671a56 5376 #define RTC_DR_YT ((uint32_t)0x00F00000)
ebrus 0:0a673c671a56 5377 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5378 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5379 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5380 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 5381 #define RTC_DR_YU ((uint32_t)0x000F0000)
ebrus 0:0a673c671a56 5382 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5383 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5384 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5385 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 5386 #define RTC_DR_WDU ((uint32_t)0x0000E000)
ebrus 0:0a673c671a56 5387 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5388 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5389 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 5390 #define RTC_DR_MT ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5391 #define RTC_DR_MU ((uint32_t)0x00000F00)
ebrus 0:0a673c671a56 5392 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5393 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5394 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 5395 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5396 #define RTC_DR_DT ((uint32_t)0x00000030)
ebrus 0:0a673c671a56 5397 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5398 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5399 #define RTC_DR_DU ((uint32_t)0x0000000F)
ebrus 0:0a673c671a56 5400 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5401 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5402 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5403 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5404
ebrus 0:0a673c671a56 5405 /******************** Bits definition for RTC_CR register *******************/
ebrus 0:0a673c671a56 5406 #define RTC_CR_COE ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 5407 #define RTC_CR_OSEL ((uint32_t)0x00600000)
ebrus 0:0a673c671a56 5408 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5409 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5410 #define RTC_CR_POL ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5411 #define RTC_CR_COSEL ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 5412 #define RTC_CR_BCK ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5413 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5414 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5415 #define RTC_CR_TSIE ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 5416 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5417 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5418 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5419 #define RTC_CR_TSE ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5420 #define RTC_CR_WUTE ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 5421 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5422 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5423 #define RTC_CR_DCE ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5424 #define RTC_CR_FMT ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5425 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5426 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5427 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5428 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
ebrus 0:0a673c671a56 5429 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5430 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5431 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5432
ebrus 0:0a673c671a56 5433 /******************** Bits definition for RTC_ISR register ******************/
ebrus 0:0a673c671a56 5434 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5435 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5436 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5437 #define RTC_ISR_TSF ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5438 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 5439 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5440 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5441 #define RTC_ISR_INIT ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5442 #define RTC_ISR_INITF ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5443 #define RTC_ISR_RSF ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5444 #define RTC_ISR_INITS ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5445 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5446 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5447 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5448 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5449
ebrus 0:0a673c671a56 5450 /******************** Bits definition for RTC_PRER register *****************/
ebrus 0:0a673c671a56 5451 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
ebrus 0:0a673c671a56 5452 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
ebrus 0:0a673c671a56 5453
ebrus 0:0a673c671a56 5454 /******************** Bits definition for RTC_WUTR register *****************/
ebrus 0:0a673c671a56 5455 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
ebrus 0:0a673c671a56 5456
ebrus 0:0a673c671a56 5457 /******************** Bits definition for RTC_CALIBR register ***************/
ebrus 0:0a673c671a56 5458 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5459 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
ebrus 0:0a673c671a56 5460
ebrus 0:0a673c671a56 5461 /******************** Bits definition for RTC_ALRMAR register ***************/
ebrus 0:0a673c671a56 5462 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 5463 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 5464 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
ebrus 0:0a673c671a56 5465 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 5466 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 5467 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
ebrus 0:0a673c671a56 5468 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 5469 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 5470 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 5471 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 5472 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 5473 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5474 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
ebrus 0:0a673c671a56 5475 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5476 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5477 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
ebrus 0:0a673c671a56 5478 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5479 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5480 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5481 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 5482 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 5483 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
ebrus 0:0a673c671a56 5484 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5485 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5486 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5487 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
ebrus 0:0a673c671a56 5488 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5489 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5490 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 5491 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5492 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5493 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
ebrus 0:0a673c671a56 5494 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5495 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5496 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5497 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
ebrus 0:0a673c671a56 5498 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5499 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5500 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5501 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5502
ebrus 0:0a673c671a56 5503 /******************** Bits definition for RTC_ALRMBR register ***************/
ebrus 0:0a673c671a56 5504 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 5505 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
ebrus 0:0a673c671a56 5506 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
ebrus 0:0a673c671a56 5507 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
ebrus 0:0a673c671a56 5508 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 5509 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
ebrus 0:0a673c671a56 5510 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 5511 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 5512 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 5513 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 5514 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 5515 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5516 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
ebrus 0:0a673c671a56 5517 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5518 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5519 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
ebrus 0:0a673c671a56 5520 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5521 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5522 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5523 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 5524 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 5525 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
ebrus 0:0a673c671a56 5526 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5527 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5528 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5529 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
ebrus 0:0a673c671a56 5530 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5531 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5532 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 5533 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5534 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5535 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
ebrus 0:0a673c671a56 5536 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5537 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5538 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5539 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
ebrus 0:0a673c671a56 5540 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5541 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5542 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5543 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5544
ebrus 0:0a673c671a56 5545 /******************** Bits definition for RTC_WPR register ******************/
ebrus 0:0a673c671a56 5546 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
ebrus 0:0a673c671a56 5547
ebrus 0:0a673c671a56 5548 /******************** Bits definition for RTC_SSR register ******************/
ebrus 0:0a673c671a56 5549 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
ebrus 0:0a673c671a56 5550
ebrus 0:0a673c671a56 5551 /******************** Bits definition for RTC_SHIFTR register ***************/
ebrus 0:0a673c671a56 5552 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
ebrus 0:0a673c671a56 5553 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
ebrus 0:0a673c671a56 5554
ebrus 0:0a673c671a56 5555 /******************** Bits definition for RTC_TSTR register *****************/
ebrus 0:0a673c671a56 5556 #define RTC_TSTR_PM ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 5557 #define RTC_TSTR_HT ((uint32_t)0x00300000)
ebrus 0:0a673c671a56 5558 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 5559 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 5560 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
ebrus 0:0a673c671a56 5561 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5562 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5563 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5564 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 5565 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
ebrus 0:0a673c671a56 5566 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5567 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5568 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5569 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
ebrus 0:0a673c671a56 5570 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5571 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5572 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 5573 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5574 #define RTC_TSTR_ST ((uint32_t)0x00000070)
ebrus 0:0a673c671a56 5575 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5576 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5577 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5578 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
ebrus 0:0a673c671a56 5579 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5580 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5581 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5582 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5583
ebrus 0:0a673c671a56 5584 /******************** Bits definition for RTC_TSDR register *****************/
ebrus 0:0a673c671a56 5585 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
ebrus 0:0a673c671a56 5586 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5587 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5588 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 5589 #define RTC_TSDR_MT ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5590 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
ebrus 0:0a673c671a56 5591 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5592 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5593 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 5594 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5595 #define RTC_TSDR_DT ((uint32_t)0x00000030)
ebrus 0:0a673c671a56 5596 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5597 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5598 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
ebrus 0:0a673c671a56 5599 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5600 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5601 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5602 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5603
ebrus 0:0a673c671a56 5604 /******************** Bits definition for RTC_TSSSR register ****************/
ebrus 0:0a673c671a56 5605 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
ebrus 0:0a673c671a56 5606
ebrus 0:0a673c671a56 5607 /******************** Bits definition for RTC_CAL register *****************/
ebrus 0:0a673c671a56 5608 #define RTC_CALR_CALP ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 5609 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5610 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5611 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
ebrus 0:0a673c671a56 5612 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5613 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5614 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5615 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 5616 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 5617 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 5618 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 5619 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5620 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5621
ebrus 0:0a673c671a56 5622 /******************** Bits definition for RTC_TAFCR register ****************/
ebrus 0:0a673c671a56 5623 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 5624 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 5625 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 5626 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 5627 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
ebrus 0:0a673c671a56 5628 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 5629 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 5630 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
ebrus 0:0a673c671a56 5631 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 5632 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 5633 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
ebrus 0:0a673c671a56 5634 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 5635 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 5636 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 5637 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 5638 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5639 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5640 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5641
ebrus 0:0a673c671a56 5642 /******************** Bits definition for RTC_ALRMASSR register *************/
ebrus 0:0a673c671a56 5643 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
ebrus 0:0a673c671a56 5644 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 5645 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 5646 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 5647 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 5648 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
ebrus 0:0a673c671a56 5649
ebrus 0:0a673c671a56 5650 /******************** Bits definition for RTC_ALRMBSSR register *************/
ebrus 0:0a673c671a56 5651 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
ebrus 0:0a673c671a56 5652 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 5653 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 5654 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 5655 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 5656 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
ebrus 0:0a673c671a56 5657
ebrus 0:0a673c671a56 5658 /******************** Bits definition for RTC_BKP0R register ****************/
ebrus 0:0a673c671a56 5659 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5660
ebrus 0:0a673c671a56 5661 /******************** Bits definition for RTC_BKP1R register ****************/
ebrus 0:0a673c671a56 5662 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5663
ebrus 0:0a673c671a56 5664 /******************** Bits definition for RTC_BKP2R register ****************/
ebrus 0:0a673c671a56 5665 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5666
ebrus 0:0a673c671a56 5667 /******************** Bits definition for RTC_BKP3R register ****************/
ebrus 0:0a673c671a56 5668 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5669
ebrus 0:0a673c671a56 5670 /******************** Bits definition for RTC_BKP4R register ****************/
ebrus 0:0a673c671a56 5671 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5672
ebrus 0:0a673c671a56 5673 /******************** Bits definition for RTC_BKP5R register ****************/
ebrus 0:0a673c671a56 5674 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5675
ebrus 0:0a673c671a56 5676 /******************** Bits definition for RTC_BKP6R register ****************/
ebrus 0:0a673c671a56 5677 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5678
ebrus 0:0a673c671a56 5679 /******************** Bits definition for RTC_BKP7R register ****************/
ebrus 0:0a673c671a56 5680 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5681
ebrus 0:0a673c671a56 5682 /******************** Bits definition for RTC_BKP8R register ****************/
ebrus 0:0a673c671a56 5683 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5684
ebrus 0:0a673c671a56 5685 /******************** Bits definition for RTC_BKP9R register ****************/
ebrus 0:0a673c671a56 5686 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5687
ebrus 0:0a673c671a56 5688 /******************** Bits definition for RTC_BKP10R register ***************/
ebrus 0:0a673c671a56 5689 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5690
ebrus 0:0a673c671a56 5691 /******************** Bits definition for RTC_BKP11R register ***************/
ebrus 0:0a673c671a56 5692 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5693
ebrus 0:0a673c671a56 5694 /******************** Bits definition for RTC_BKP12R register ***************/
ebrus 0:0a673c671a56 5695 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5696
ebrus 0:0a673c671a56 5697 /******************** Bits definition for RTC_BKP13R register ***************/
ebrus 0:0a673c671a56 5698 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5699
ebrus 0:0a673c671a56 5700 /******************** Bits definition for RTC_BKP14R register ***************/
ebrus 0:0a673c671a56 5701 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5702
ebrus 0:0a673c671a56 5703 /******************** Bits definition for RTC_BKP15R register ***************/
ebrus 0:0a673c671a56 5704 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5705
ebrus 0:0a673c671a56 5706 /******************** Bits definition for RTC_BKP16R register ***************/
ebrus 0:0a673c671a56 5707 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5708
ebrus 0:0a673c671a56 5709 /******************** Bits definition for RTC_BKP17R register ***************/
ebrus 0:0a673c671a56 5710 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5711
ebrus 0:0a673c671a56 5712 /******************** Bits definition for RTC_BKP18R register ***************/
ebrus 0:0a673c671a56 5713 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5714
ebrus 0:0a673c671a56 5715 /******************** Bits definition for RTC_BKP19R register ***************/
ebrus 0:0a673c671a56 5716 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
ebrus 0:0a673c671a56 5717
ebrus 0:0a673c671a56 5718
ebrus 0:0a673c671a56 5719 /******************************************************************************/
ebrus 0:0a673c671a56 5720 /* */
ebrus 0:0a673c671a56 5721 /* SD host Interface */
ebrus 0:0a673c671a56 5722 /* */
ebrus 0:0a673c671a56 5723 /******************************************************************************/
ebrus 0:0a673c671a56 5724 /****************** Bit definition for SDIO_POWER register ******************/
ebrus 0:0a673c671a56 5725 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
ebrus 0:0a673c671a56 5726 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
ebrus 0:0a673c671a56 5727 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
ebrus 0:0a673c671a56 5728
ebrus 0:0a673c671a56 5729 /****************** Bit definition for SDIO_CLKCR register ******************/
ebrus 0:0a673c671a56 5730 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
ebrus 0:0a673c671a56 5731 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
ebrus 0:0a673c671a56 5732 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
ebrus 0:0a673c671a56 5733 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
ebrus 0:0a673c671a56 5734
ebrus 0:0a673c671a56 5735 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
ebrus 0:0a673c671a56 5736 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
ebrus 0:0a673c671a56 5737 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
ebrus 0:0a673c671a56 5738
ebrus 0:0a673c671a56 5739 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
ebrus 0:0a673c671a56 5740 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
ebrus 0:0a673c671a56 5741
ebrus 0:0a673c671a56 5742 /******************* Bit definition for SDIO_ARG register *******************/
ebrus 0:0a673c671a56 5743 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
ebrus 0:0a673c671a56 5744
ebrus 0:0a673c671a56 5745 /******************* Bit definition for SDIO_CMD register *******************/
ebrus 0:0a673c671a56 5746 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
ebrus 0:0a673c671a56 5747
ebrus 0:0a673c671a56 5748 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
ebrus 0:0a673c671a56 5749 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
ebrus 0:0a673c671a56 5750 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
ebrus 0:0a673c671a56 5751
ebrus 0:0a673c671a56 5752 #define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
ebrus 0:0a673c671a56 5753 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
ebrus 0:0a673c671a56 5754 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
ebrus 0:0a673c671a56 5755 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
ebrus 0:0a673c671a56 5756 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
ebrus 0:0a673c671a56 5757 #define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
ebrus 0:0a673c671a56 5758 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
ebrus 0:0a673c671a56 5759
ebrus 0:0a673c671a56 5760 /***************** Bit definition for SDIO_RESPCMD register *****************/
ebrus 0:0a673c671a56 5761 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
ebrus 0:0a673c671a56 5762
ebrus 0:0a673c671a56 5763 /****************** Bit definition for SDIO_RESP0 register ******************/
ebrus 0:0a673c671a56 5764 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
ebrus 0:0a673c671a56 5765
ebrus 0:0a673c671a56 5766 /****************** Bit definition for SDIO_RESP1 register ******************/
ebrus 0:0a673c671a56 5767 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
ebrus 0:0a673c671a56 5768
ebrus 0:0a673c671a56 5769 /****************** Bit definition for SDIO_RESP2 register ******************/
ebrus 0:0a673c671a56 5770 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
ebrus 0:0a673c671a56 5771
ebrus 0:0a673c671a56 5772 /****************** Bit definition for SDIO_RESP3 register ******************/
ebrus 0:0a673c671a56 5773 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
ebrus 0:0a673c671a56 5774
ebrus 0:0a673c671a56 5775 /****************** Bit definition for SDIO_RESP4 register ******************/
ebrus 0:0a673c671a56 5776 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
ebrus 0:0a673c671a56 5777
ebrus 0:0a673c671a56 5778 /****************** Bit definition for SDIO_DTIMER register *****************/
ebrus 0:0a673c671a56 5779 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
ebrus 0:0a673c671a56 5780
ebrus 0:0a673c671a56 5781 /****************** Bit definition for SDIO_DLEN register *******************/
ebrus 0:0a673c671a56 5782 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
ebrus 0:0a673c671a56 5783
ebrus 0:0a673c671a56 5784 /****************** Bit definition for SDIO_DCTRL register ******************/
ebrus 0:0a673c671a56 5785 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
ebrus 0:0a673c671a56 5786 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
ebrus 0:0a673c671a56 5787 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
ebrus 0:0a673c671a56 5788 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
ebrus 0:0a673c671a56 5789
ebrus 0:0a673c671a56 5790 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
ebrus 0:0a673c671a56 5791 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
ebrus 0:0a673c671a56 5792 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
ebrus 0:0a673c671a56 5793 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
ebrus 0:0a673c671a56 5794 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
ebrus 0:0a673c671a56 5795
ebrus 0:0a673c671a56 5796 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
ebrus 0:0a673c671a56 5797 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
ebrus 0:0a673c671a56 5798 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
ebrus 0:0a673c671a56 5799 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
ebrus 0:0a673c671a56 5800
ebrus 0:0a673c671a56 5801 /****************** Bit definition for SDIO_DCOUNT register *****************/
ebrus 0:0a673c671a56 5802 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
ebrus 0:0a673c671a56 5803
ebrus 0:0a673c671a56 5804 /****************** Bit definition for SDIO_STA register ********************/
ebrus 0:0a673c671a56 5805 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
ebrus 0:0a673c671a56 5806 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
ebrus 0:0a673c671a56 5807 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
ebrus 0:0a673c671a56 5808 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
ebrus 0:0a673c671a56 5809 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
ebrus 0:0a673c671a56 5810 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
ebrus 0:0a673c671a56 5811 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
ebrus 0:0a673c671a56 5812 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
ebrus 0:0a673c671a56 5813 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
ebrus 0:0a673c671a56 5814 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
ebrus 0:0a673c671a56 5815 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
ebrus 0:0a673c671a56 5816 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
ebrus 0:0a673c671a56 5817 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
ebrus 0:0a673c671a56 5818 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
ebrus 0:0a673c671a56 5819 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
ebrus 0:0a673c671a56 5820 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
ebrus 0:0a673c671a56 5821 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
ebrus 0:0a673c671a56 5822 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
ebrus 0:0a673c671a56 5823 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
ebrus 0:0a673c671a56 5824 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
ebrus 0:0a673c671a56 5825 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
ebrus 0:0a673c671a56 5826 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
ebrus 0:0a673c671a56 5827 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
ebrus 0:0a673c671a56 5828 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
ebrus 0:0a673c671a56 5829
ebrus 0:0a673c671a56 5830 /******************* Bit definition for SDIO_ICR register *******************/
ebrus 0:0a673c671a56 5831 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
ebrus 0:0a673c671a56 5832 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
ebrus 0:0a673c671a56 5833 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
ebrus 0:0a673c671a56 5834 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
ebrus 0:0a673c671a56 5835 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
ebrus 0:0a673c671a56 5836 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
ebrus 0:0a673c671a56 5837 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
ebrus 0:0a673c671a56 5838 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
ebrus 0:0a673c671a56 5839 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
ebrus 0:0a673c671a56 5840 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
ebrus 0:0a673c671a56 5841 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
ebrus 0:0a673c671a56 5842 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
ebrus 0:0a673c671a56 5843 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
ebrus 0:0a673c671a56 5844
ebrus 0:0a673c671a56 5845 /****************** Bit definition for SDIO_MASK register *******************/
ebrus 0:0a673c671a56 5846 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
ebrus 0:0a673c671a56 5847 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
ebrus 0:0a673c671a56 5848 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
ebrus 0:0a673c671a56 5849 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
ebrus 0:0a673c671a56 5850 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
ebrus 0:0a673c671a56 5851 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
ebrus 0:0a673c671a56 5852 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
ebrus 0:0a673c671a56 5853 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
ebrus 0:0a673c671a56 5854 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
ebrus 0:0a673c671a56 5855 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
ebrus 0:0a673c671a56 5856 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
ebrus 0:0a673c671a56 5857 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
ebrus 0:0a673c671a56 5858 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
ebrus 0:0a673c671a56 5859 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
ebrus 0:0a673c671a56 5860 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
ebrus 0:0a673c671a56 5861 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
ebrus 0:0a673c671a56 5862 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
ebrus 0:0a673c671a56 5863 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
ebrus 0:0a673c671a56 5864 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
ebrus 0:0a673c671a56 5865 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
ebrus 0:0a673c671a56 5866 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
ebrus 0:0a673c671a56 5867 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
ebrus 0:0a673c671a56 5868 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
ebrus 0:0a673c671a56 5869 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
ebrus 0:0a673c671a56 5870
ebrus 0:0a673c671a56 5871 /***************** Bit definition for SDIO_FIFOCNT register *****************/
ebrus 0:0a673c671a56 5872 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
ebrus 0:0a673c671a56 5873
ebrus 0:0a673c671a56 5874 /****************** Bit definition for SDIO_FIFO register *******************/
ebrus 0:0a673c671a56 5875 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
ebrus 0:0a673c671a56 5876
ebrus 0:0a673c671a56 5877 /******************************************************************************/
ebrus 0:0a673c671a56 5878 /* */
ebrus 0:0a673c671a56 5879 /* Serial Peripheral Interface */
ebrus 0:0a673c671a56 5880 /* */
ebrus 0:0a673c671a56 5881 /******************************************************************************/
ebrus 0:0a673c671a56 5882 /******************* Bit definition for SPI_CR1 register ********************/
ebrus 0:0a673c671a56 5883 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
ebrus 0:0a673c671a56 5884 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
ebrus 0:0a673c671a56 5885 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
ebrus 0:0a673c671a56 5886
ebrus 0:0a673c671a56 5887 #define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
ebrus 0:0a673c671a56 5888 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
ebrus 0:0a673c671a56 5889 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
ebrus 0:0a673c671a56 5890 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
ebrus 0:0a673c671a56 5891
ebrus 0:0a673c671a56 5892 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
ebrus 0:0a673c671a56 5893 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
ebrus 0:0a673c671a56 5894 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
ebrus 0:0a673c671a56 5895 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
ebrus 0:0a673c671a56 5896 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
ebrus 0:0a673c671a56 5897 #define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
ebrus 0:0a673c671a56 5898 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
ebrus 0:0a673c671a56 5899 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
ebrus 0:0a673c671a56 5900 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
ebrus 0:0a673c671a56 5901 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
ebrus 0:0a673c671a56 5902
ebrus 0:0a673c671a56 5903 /******************* Bit definition for SPI_CR2 register ********************/
ebrus 0:0a673c671a56 5904 #define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
ebrus 0:0a673c671a56 5905 #define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
ebrus 0:0a673c671a56 5906 #define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
ebrus 0:0a673c671a56 5907 #define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
ebrus 0:0a673c671a56 5908 #define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
ebrus 0:0a673c671a56 5909 #define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
ebrus 0:0a673c671a56 5910
ebrus 0:0a673c671a56 5911 /******************** Bit definition for SPI_SR register ********************/
ebrus 0:0a673c671a56 5912 #define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
ebrus 0:0a673c671a56 5913 #define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
ebrus 0:0a673c671a56 5914 #define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
ebrus 0:0a673c671a56 5915 #define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
ebrus 0:0a673c671a56 5916 #define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
ebrus 0:0a673c671a56 5917 #define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
ebrus 0:0a673c671a56 5918 #define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
ebrus 0:0a673c671a56 5919 #define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
ebrus 0:0a673c671a56 5920
ebrus 0:0a673c671a56 5921 /******************** Bit definition for SPI_DR register ********************/
ebrus 0:0a673c671a56 5922 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
ebrus 0:0a673c671a56 5923
ebrus 0:0a673c671a56 5924 /******************* Bit definition for SPI_CRCPR register ******************/
ebrus 0:0a673c671a56 5925 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
ebrus 0:0a673c671a56 5926
ebrus 0:0a673c671a56 5927 /****************** Bit definition for SPI_RXCRCR register ******************/
ebrus 0:0a673c671a56 5928 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
ebrus 0:0a673c671a56 5929
ebrus 0:0a673c671a56 5930 /****************** Bit definition for SPI_TXCRCR register ******************/
ebrus 0:0a673c671a56 5931 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
ebrus 0:0a673c671a56 5932
ebrus 0:0a673c671a56 5933 /****************** Bit definition for SPI_I2SCFGR register *****************/
ebrus 0:0a673c671a56 5934 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
ebrus 0:0a673c671a56 5935
ebrus 0:0a673c671a56 5936 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
ebrus 0:0a673c671a56 5937 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
ebrus 0:0a673c671a56 5938 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
ebrus 0:0a673c671a56 5939
ebrus 0:0a673c671a56 5940 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
ebrus 0:0a673c671a56 5941
ebrus 0:0a673c671a56 5942 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
ebrus 0:0a673c671a56 5943 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
ebrus 0:0a673c671a56 5944 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
ebrus 0:0a673c671a56 5945
ebrus 0:0a673c671a56 5946 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
ebrus 0:0a673c671a56 5947
ebrus 0:0a673c671a56 5948 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
ebrus 0:0a673c671a56 5949 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
ebrus 0:0a673c671a56 5950 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
ebrus 0:0a673c671a56 5951
ebrus 0:0a673c671a56 5952 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
ebrus 0:0a673c671a56 5953 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
ebrus 0:0a673c671a56 5954
ebrus 0:0a673c671a56 5955 /****************** Bit definition for SPI_I2SPR register *******************/
ebrus 0:0a673c671a56 5956 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
ebrus 0:0a673c671a56 5957 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
ebrus 0:0a673c671a56 5958 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
ebrus 0:0a673c671a56 5959
ebrus 0:0a673c671a56 5960 /******************************************************************************/
ebrus 0:0a673c671a56 5961 /* */
ebrus 0:0a673c671a56 5962 /* SYSCFG */
ebrus 0:0a673c671a56 5963 /* */
ebrus 0:0a673c671a56 5964 /******************************************************************************/
ebrus 0:0a673c671a56 5965 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
ebrus 0:0a673c671a56 5966 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
ebrus 0:0a673c671a56 5967 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 5968 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 5969 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 5970
ebrus 0:0a673c671a56 5971 #define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
ebrus 0:0a673c671a56 5972
ebrus 0:0a673c671a56 5973 /****************** Bit definition for SYSCFG_PMC register ******************/
ebrus 0:0a673c671a56 5974 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
ebrus 0:0a673c671a56 5975 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
ebrus 0:0a673c671a56 5976 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
ebrus 0:0a673c671a56 5977
ebrus 0:0a673c671a56 5978 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
ebrus 0:0a673c671a56 5979 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */
ebrus 0:0a673c671a56 5980 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
ebrus 0:0a673c671a56 5981 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
ebrus 0:0a673c671a56 5982 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!<EXTI 3 configuration */
ebrus 0:0a673c671a56 5983 /**
ebrus 0:0a673c671a56 5984 * @brief EXTI0 configuration
ebrus 0:0a673c671a56 5985 */
ebrus 0:0a673c671a56 5986 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */
ebrus 0:0a673c671a56 5987 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */
ebrus 0:0a673c671a56 5988 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */
ebrus 0:0a673c671a56 5989 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */
ebrus 0:0a673c671a56 5990 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */
ebrus 0:0a673c671a56 5991 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */
ebrus 0:0a673c671a56 5992 #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */
ebrus 0:0a673c671a56 5993 #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */
ebrus 0:0a673c671a56 5994 #define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */
ebrus 0:0a673c671a56 5995
ebrus 0:0a673c671a56 5996 /**
ebrus 0:0a673c671a56 5997 * @brief EXTI1 configuration
ebrus 0:0a673c671a56 5998 */
ebrus 0:0a673c671a56 5999 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */
ebrus 0:0a673c671a56 6000 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */
ebrus 0:0a673c671a56 6001 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */
ebrus 0:0a673c671a56 6002 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */
ebrus 0:0a673c671a56 6003 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */
ebrus 0:0a673c671a56 6004 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */
ebrus 0:0a673c671a56 6005 #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */
ebrus 0:0a673c671a56 6006 #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */
ebrus 0:0a673c671a56 6007 #define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */
ebrus 0:0a673c671a56 6008
ebrus 0:0a673c671a56 6009 /**
ebrus 0:0a673c671a56 6010 * @brief EXTI2 configuration
ebrus 0:0a673c671a56 6011 */
ebrus 0:0a673c671a56 6012 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */
ebrus 0:0a673c671a56 6013 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */
ebrus 0:0a673c671a56 6014 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */
ebrus 0:0a673c671a56 6015 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */
ebrus 0:0a673c671a56 6016 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */
ebrus 0:0a673c671a56 6017 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */
ebrus 0:0a673c671a56 6018 #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */
ebrus 0:0a673c671a56 6019 #define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */
ebrus 0:0a673c671a56 6020 #define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */
ebrus 0:0a673c671a56 6021
ebrus 0:0a673c671a56 6022 /**
ebrus 0:0a673c671a56 6023 * @brief EXTI3 configuration
ebrus 0:0a673c671a56 6024 */
ebrus 0:0a673c671a56 6025 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */
ebrus 0:0a673c671a56 6026 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */
ebrus 0:0a673c671a56 6027 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */
ebrus 0:0a673c671a56 6028 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */
ebrus 0:0a673c671a56 6029 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */
ebrus 0:0a673c671a56 6030 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */
ebrus 0:0a673c671a56 6031 #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */
ebrus 0:0a673c671a56 6032 #define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */
ebrus 0:0a673c671a56 6033 #define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */
ebrus 0:0a673c671a56 6034
ebrus 0:0a673c671a56 6035 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
ebrus 0:0a673c671a56 6036 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!<EXTI 4 configuration */
ebrus 0:0a673c671a56 6037 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
ebrus 0:0a673c671a56 6038 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
ebrus 0:0a673c671a56 6039 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!<EXTI 7 configuration */
ebrus 0:0a673c671a56 6040 /**
ebrus 0:0a673c671a56 6041 * @brief EXTI4 configuration
ebrus 0:0a673c671a56 6042 */
ebrus 0:0a673c671a56 6043 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */
ebrus 0:0a673c671a56 6044 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */
ebrus 0:0a673c671a56 6045 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */
ebrus 0:0a673c671a56 6046 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */
ebrus 0:0a673c671a56 6047 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */
ebrus 0:0a673c671a56 6048 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */
ebrus 0:0a673c671a56 6049 #define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */
ebrus 0:0a673c671a56 6050 #define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */
ebrus 0:0a673c671a56 6051 #define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */
ebrus 0:0a673c671a56 6052
ebrus 0:0a673c671a56 6053 /**
ebrus 0:0a673c671a56 6054 * @brief EXTI5 configuration
ebrus 0:0a673c671a56 6055 */
ebrus 0:0a673c671a56 6056 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */
ebrus 0:0a673c671a56 6057 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */
ebrus 0:0a673c671a56 6058 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */
ebrus 0:0a673c671a56 6059 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */
ebrus 0:0a673c671a56 6060 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */
ebrus 0:0a673c671a56 6061 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */
ebrus 0:0a673c671a56 6062 #define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */
ebrus 0:0a673c671a56 6063 #define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */
ebrus 0:0a673c671a56 6064 #define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */
ebrus 0:0a673c671a56 6065
ebrus 0:0a673c671a56 6066 /**
ebrus 0:0a673c671a56 6067 * @brief EXTI6 configuration
ebrus 0:0a673c671a56 6068 */
ebrus 0:0a673c671a56 6069 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */
ebrus 0:0a673c671a56 6070 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */
ebrus 0:0a673c671a56 6071 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */
ebrus 0:0a673c671a56 6072 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */
ebrus 0:0a673c671a56 6073 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */
ebrus 0:0a673c671a56 6074 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */
ebrus 0:0a673c671a56 6075 #define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */
ebrus 0:0a673c671a56 6076 #define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */
ebrus 0:0a673c671a56 6077 #define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */
ebrus 0:0a673c671a56 6078
ebrus 0:0a673c671a56 6079 /**
ebrus 0:0a673c671a56 6080 * @brief EXTI7 configuration
ebrus 0:0a673c671a56 6081 */
ebrus 0:0a673c671a56 6082 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */
ebrus 0:0a673c671a56 6083 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */
ebrus 0:0a673c671a56 6084 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */
ebrus 0:0a673c671a56 6085 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */
ebrus 0:0a673c671a56 6086 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */
ebrus 0:0a673c671a56 6087 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */
ebrus 0:0a673c671a56 6088 #define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */
ebrus 0:0a673c671a56 6089 #define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */
ebrus 0:0a673c671a56 6090 #define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */
ebrus 0:0a673c671a56 6091
ebrus 0:0a673c671a56 6092 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
ebrus 0:0a673c671a56 6093 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!<EXTI 8 configuration */
ebrus 0:0a673c671a56 6094 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
ebrus 0:0a673c671a56 6095 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
ebrus 0:0a673c671a56 6096 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!<EXTI 11 configuration */
ebrus 0:0a673c671a56 6097
ebrus 0:0a673c671a56 6098 /**
ebrus 0:0a673c671a56 6099 * @brief EXTI8 configuration
ebrus 0:0a673c671a56 6100 */
ebrus 0:0a673c671a56 6101 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */
ebrus 0:0a673c671a56 6102 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */
ebrus 0:0a673c671a56 6103 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */
ebrus 0:0a673c671a56 6104 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */
ebrus 0:0a673c671a56 6105 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */
ebrus 0:0a673c671a56 6106 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */
ebrus 0:0a673c671a56 6107 #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */
ebrus 0:0a673c671a56 6108 #define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */
ebrus 0:0a673c671a56 6109 #define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */
ebrus 0:0a673c671a56 6110
ebrus 0:0a673c671a56 6111 /**
ebrus 0:0a673c671a56 6112 * @brief EXTI9 configuration
ebrus 0:0a673c671a56 6113 */
ebrus 0:0a673c671a56 6114 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */
ebrus 0:0a673c671a56 6115 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */
ebrus 0:0a673c671a56 6116 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */
ebrus 0:0a673c671a56 6117 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */
ebrus 0:0a673c671a56 6118 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */
ebrus 0:0a673c671a56 6119 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */
ebrus 0:0a673c671a56 6120 #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */
ebrus 0:0a673c671a56 6121 #define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */
ebrus 0:0a673c671a56 6122 #define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */
ebrus 0:0a673c671a56 6123
ebrus 0:0a673c671a56 6124 /**
ebrus 0:0a673c671a56 6125 * @brief EXTI10 configuration
ebrus 0:0a673c671a56 6126 */
ebrus 0:0a673c671a56 6127 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */
ebrus 0:0a673c671a56 6128 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */
ebrus 0:0a673c671a56 6129 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */
ebrus 0:0a673c671a56 6130 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */
ebrus 0:0a673c671a56 6131 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */
ebrus 0:0a673c671a56 6132 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */
ebrus 0:0a673c671a56 6133 #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */
ebrus 0:0a673c671a56 6134 #define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */
ebrus 0:0a673c671a56 6135 #define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */
ebrus 0:0a673c671a56 6136
ebrus 0:0a673c671a56 6137 /**
ebrus 0:0a673c671a56 6138 * @brief EXTI11 configuration
ebrus 0:0a673c671a56 6139 */
ebrus 0:0a673c671a56 6140 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */
ebrus 0:0a673c671a56 6141 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */
ebrus 0:0a673c671a56 6142 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */
ebrus 0:0a673c671a56 6143 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */
ebrus 0:0a673c671a56 6144 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */
ebrus 0:0a673c671a56 6145 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */
ebrus 0:0a673c671a56 6146 #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */
ebrus 0:0a673c671a56 6147 #define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */
ebrus 0:0a673c671a56 6148 #define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */
ebrus 0:0a673c671a56 6149
ebrus 0:0a673c671a56 6150 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
ebrus 0:0a673c671a56 6151 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!<EXTI 12 configuration */
ebrus 0:0a673c671a56 6152 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
ebrus 0:0a673c671a56 6153 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
ebrus 0:0a673c671a56 6154 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!<EXTI 15 configuration */
ebrus 0:0a673c671a56 6155 /**
ebrus 0:0a673c671a56 6156 * @brief EXTI12 configuration
ebrus 0:0a673c671a56 6157 */
ebrus 0:0a673c671a56 6158 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */
ebrus 0:0a673c671a56 6159 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */
ebrus 0:0a673c671a56 6160 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */
ebrus 0:0a673c671a56 6161 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */
ebrus 0:0a673c671a56 6162 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */
ebrus 0:0a673c671a56 6163 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */
ebrus 0:0a673c671a56 6164 #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */
ebrus 0:0a673c671a56 6165 #define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */
ebrus 0:0a673c671a56 6166
ebrus 0:0a673c671a56 6167 /**
ebrus 0:0a673c671a56 6168 * @brief EXTI13 configuration
ebrus 0:0a673c671a56 6169 */
ebrus 0:0a673c671a56 6170 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */
ebrus 0:0a673c671a56 6171 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */
ebrus 0:0a673c671a56 6172 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */
ebrus 0:0a673c671a56 6173 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */
ebrus 0:0a673c671a56 6174 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */
ebrus 0:0a673c671a56 6175 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */
ebrus 0:0a673c671a56 6176 #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */
ebrus 0:0a673c671a56 6177 #define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */
ebrus 0:0a673c671a56 6178
ebrus 0:0a673c671a56 6179 /**
ebrus 0:0a673c671a56 6180 * @brief EXTI14 configuration
ebrus 0:0a673c671a56 6181 */
ebrus 0:0a673c671a56 6182 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */
ebrus 0:0a673c671a56 6183 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */
ebrus 0:0a673c671a56 6184 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */
ebrus 0:0a673c671a56 6185 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */
ebrus 0:0a673c671a56 6186 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */
ebrus 0:0a673c671a56 6187 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */
ebrus 0:0a673c671a56 6188 #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */
ebrus 0:0a673c671a56 6189 #define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */
ebrus 0:0a673c671a56 6190
ebrus 0:0a673c671a56 6191 /**
ebrus 0:0a673c671a56 6192 * @brief EXTI15 configuration
ebrus 0:0a673c671a56 6193 */
ebrus 0:0a673c671a56 6194 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */
ebrus 0:0a673c671a56 6195 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */
ebrus 0:0a673c671a56 6196 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */
ebrus 0:0a673c671a56 6197 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */
ebrus 0:0a673c671a56 6198 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */
ebrus 0:0a673c671a56 6199 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */
ebrus 0:0a673c671a56 6200 #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */
ebrus 0:0a673c671a56 6201 #define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */
ebrus 0:0a673c671a56 6202
ebrus 0:0a673c671a56 6203 /****************** Bit definition for SYSCFG_CMPCR register ****************/
ebrus 0:0a673c671a56 6204 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
ebrus 0:0a673c671a56 6205 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
ebrus 0:0a673c671a56 6206
ebrus 0:0a673c671a56 6207 /******************************************************************************/
ebrus 0:0a673c671a56 6208 /* */
ebrus 0:0a673c671a56 6209 /* TIM */
ebrus 0:0a673c671a56 6210 /* */
ebrus 0:0a673c671a56 6211 /******************************************************************************/
ebrus 0:0a673c671a56 6212 /******************* Bit definition for TIM_CR1 register ********************/
ebrus 0:0a673c671a56 6213 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
ebrus 0:0a673c671a56 6214 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
ebrus 0:0a673c671a56 6215 #define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
ebrus 0:0a673c671a56 6216 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
ebrus 0:0a673c671a56 6217 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
ebrus 0:0a673c671a56 6218
ebrus 0:0a673c671a56 6219 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
ebrus 0:0a673c671a56 6220 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
ebrus 0:0a673c671a56 6221 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
ebrus 0:0a673c671a56 6222
ebrus 0:0a673c671a56 6223 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
ebrus 0:0a673c671a56 6224
ebrus 0:0a673c671a56 6225 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
ebrus 0:0a673c671a56 6226 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
ebrus 0:0a673c671a56 6227 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
ebrus 0:0a673c671a56 6228
ebrus 0:0a673c671a56 6229 /******************* Bit definition for TIM_CR2 register ********************/
ebrus 0:0a673c671a56 6230 #define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
ebrus 0:0a673c671a56 6231 #define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
ebrus 0:0a673c671a56 6232 #define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
ebrus 0:0a673c671a56 6233
ebrus 0:0a673c671a56 6234 #define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
ebrus 0:0a673c671a56 6235 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
ebrus 0:0a673c671a56 6236 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
ebrus 0:0a673c671a56 6237 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
ebrus 0:0a673c671a56 6238
ebrus 0:0a673c671a56 6239 #define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
ebrus 0:0a673c671a56 6240 #define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
ebrus 0:0a673c671a56 6241 #define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
ebrus 0:0a673c671a56 6242 #define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
ebrus 0:0a673c671a56 6243 #define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
ebrus 0:0a673c671a56 6244 #define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
ebrus 0:0a673c671a56 6245 #define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
ebrus 0:0a673c671a56 6246 #define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
ebrus 0:0a673c671a56 6247
ebrus 0:0a673c671a56 6248 /******************* Bit definition for TIM_SMCR register *******************/
ebrus 0:0a673c671a56 6249 #define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
ebrus 0:0a673c671a56 6250 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
ebrus 0:0a673c671a56 6251 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
ebrus 0:0a673c671a56 6252 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
ebrus 0:0a673c671a56 6253
ebrus 0:0a673c671a56 6254 #define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
ebrus 0:0a673c671a56 6255 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
ebrus 0:0a673c671a56 6256 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
ebrus 0:0a673c671a56 6257 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
ebrus 0:0a673c671a56 6258
ebrus 0:0a673c671a56 6259 #define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
ebrus 0:0a673c671a56 6260
ebrus 0:0a673c671a56 6261 #define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
ebrus 0:0a673c671a56 6262 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
ebrus 0:0a673c671a56 6263 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
ebrus 0:0a673c671a56 6264 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
ebrus 0:0a673c671a56 6265 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
ebrus 0:0a673c671a56 6266
ebrus 0:0a673c671a56 6267 #define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
ebrus 0:0a673c671a56 6268 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
ebrus 0:0a673c671a56 6269 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
ebrus 0:0a673c671a56 6270
ebrus 0:0a673c671a56 6271 #define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
ebrus 0:0a673c671a56 6272 #define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
ebrus 0:0a673c671a56 6273
ebrus 0:0a673c671a56 6274 /******************* Bit definition for TIM_DIER register *******************/
ebrus 0:0a673c671a56 6275 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
ebrus 0:0a673c671a56 6276 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
ebrus 0:0a673c671a56 6277 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
ebrus 0:0a673c671a56 6278 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
ebrus 0:0a673c671a56 6279 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
ebrus 0:0a673c671a56 6280 #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
ebrus 0:0a673c671a56 6281 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
ebrus 0:0a673c671a56 6282 #define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
ebrus 0:0a673c671a56 6283 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
ebrus 0:0a673c671a56 6284 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
ebrus 0:0a673c671a56 6285 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
ebrus 0:0a673c671a56 6286 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
ebrus 0:0a673c671a56 6287 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
ebrus 0:0a673c671a56 6288 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
ebrus 0:0a673c671a56 6289 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
ebrus 0:0a673c671a56 6290
ebrus 0:0a673c671a56 6291 /******************** Bit definition for TIM_SR register ********************/
ebrus 0:0a673c671a56 6292 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
ebrus 0:0a673c671a56 6293 #define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
ebrus 0:0a673c671a56 6294 #define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
ebrus 0:0a673c671a56 6295 #define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
ebrus 0:0a673c671a56 6296 #define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
ebrus 0:0a673c671a56 6297 #define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
ebrus 0:0a673c671a56 6298 #define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
ebrus 0:0a673c671a56 6299 #define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
ebrus 0:0a673c671a56 6300 #define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
ebrus 0:0a673c671a56 6301 #define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
ebrus 0:0a673c671a56 6302 #define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
ebrus 0:0a673c671a56 6303 #define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
ebrus 0:0a673c671a56 6304
ebrus 0:0a673c671a56 6305 /******************* Bit definition for TIM_EGR register ********************/
ebrus 0:0a673c671a56 6306 #define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
ebrus 0:0a673c671a56 6307 #define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
ebrus 0:0a673c671a56 6308 #define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
ebrus 0:0a673c671a56 6309 #define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
ebrus 0:0a673c671a56 6310 #define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
ebrus 0:0a673c671a56 6311 #define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
ebrus 0:0a673c671a56 6312 #define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
ebrus 0:0a673c671a56 6313 #define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
ebrus 0:0a673c671a56 6314
ebrus 0:0a673c671a56 6315 /****************** Bit definition for TIM_CCMR1 register *******************/
ebrus 0:0a673c671a56 6316 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
ebrus 0:0a673c671a56 6317 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
ebrus 0:0a673c671a56 6318 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
ebrus 0:0a673c671a56 6319
ebrus 0:0a673c671a56 6320 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
ebrus 0:0a673c671a56 6321 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
ebrus 0:0a673c671a56 6322
ebrus 0:0a673c671a56 6323 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
ebrus 0:0a673c671a56 6324 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
ebrus 0:0a673c671a56 6325 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
ebrus 0:0a673c671a56 6326 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
ebrus 0:0a673c671a56 6327
ebrus 0:0a673c671a56 6328 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
ebrus 0:0a673c671a56 6329
ebrus 0:0a673c671a56 6330 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
ebrus 0:0a673c671a56 6331 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
ebrus 0:0a673c671a56 6332 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
ebrus 0:0a673c671a56 6333
ebrus 0:0a673c671a56 6334 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
ebrus 0:0a673c671a56 6335 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
ebrus 0:0a673c671a56 6336
ebrus 0:0a673c671a56 6337 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
ebrus 0:0a673c671a56 6338 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
ebrus 0:0a673c671a56 6339 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
ebrus 0:0a673c671a56 6340 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
ebrus 0:0a673c671a56 6341
ebrus 0:0a673c671a56 6342 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
ebrus 0:0a673c671a56 6343
ebrus 0:0a673c671a56 6344 /*----------------------------------------------------------------------------*/
ebrus 0:0a673c671a56 6345
ebrus 0:0a673c671a56 6346 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
ebrus 0:0a673c671a56 6347 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
ebrus 0:0a673c671a56 6348 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
ebrus 0:0a673c671a56 6349
ebrus 0:0a673c671a56 6350 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
ebrus 0:0a673c671a56 6351 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
ebrus 0:0a673c671a56 6352 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
ebrus 0:0a673c671a56 6353 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
ebrus 0:0a673c671a56 6354 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
ebrus 0:0a673c671a56 6355
ebrus 0:0a673c671a56 6356 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
ebrus 0:0a673c671a56 6357 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
ebrus 0:0a673c671a56 6358 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
ebrus 0:0a673c671a56 6359
ebrus 0:0a673c671a56 6360 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
ebrus 0:0a673c671a56 6361 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
ebrus 0:0a673c671a56 6362 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
ebrus 0:0a673c671a56 6363 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
ebrus 0:0a673c671a56 6364 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
ebrus 0:0a673c671a56 6365
ebrus 0:0a673c671a56 6366 /****************** Bit definition for TIM_CCMR2 register *******************/
ebrus 0:0a673c671a56 6367 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
ebrus 0:0a673c671a56 6368 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
ebrus 0:0a673c671a56 6369 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
ebrus 0:0a673c671a56 6370
ebrus 0:0a673c671a56 6371 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
ebrus 0:0a673c671a56 6372 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
ebrus 0:0a673c671a56 6373
ebrus 0:0a673c671a56 6374 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
ebrus 0:0a673c671a56 6375 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
ebrus 0:0a673c671a56 6376 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
ebrus 0:0a673c671a56 6377 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
ebrus 0:0a673c671a56 6378
ebrus 0:0a673c671a56 6379 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
ebrus 0:0a673c671a56 6380
ebrus 0:0a673c671a56 6381 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
ebrus 0:0a673c671a56 6382 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
ebrus 0:0a673c671a56 6383 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
ebrus 0:0a673c671a56 6384
ebrus 0:0a673c671a56 6385 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
ebrus 0:0a673c671a56 6386 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
ebrus 0:0a673c671a56 6387
ebrus 0:0a673c671a56 6388 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
ebrus 0:0a673c671a56 6389 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
ebrus 0:0a673c671a56 6390 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
ebrus 0:0a673c671a56 6391 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
ebrus 0:0a673c671a56 6392
ebrus 0:0a673c671a56 6393 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
ebrus 0:0a673c671a56 6394
ebrus 0:0a673c671a56 6395 /*----------------------------------------------------------------------------*/
ebrus 0:0a673c671a56 6396
ebrus 0:0a673c671a56 6397 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
ebrus 0:0a673c671a56 6398 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
ebrus 0:0a673c671a56 6399 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
ebrus 0:0a673c671a56 6400
ebrus 0:0a673c671a56 6401 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
ebrus 0:0a673c671a56 6402 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
ebrus 0:0a673c671a56 6403 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
ebrus 0:0a673c671a56 6404 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
ebrus 0:0a673c671a56 6405 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
ebrus 0:0a673c671a56 6406
ebrus 0:0a673c671a56 6407 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
ebrus 0:0a673c671a56 6408 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
ebrus 0:0a673c671a56 6409 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
ebrus 0:0a673c671a56 6410
ebrus 0:0a673c671a56 6411 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
ebrus 0:0a673c671a56 6412 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
ebrus 0:0a673c671a56 6413 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
ebrus 0:0a673c671a56 6414 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
ebrus 0:0a673c671a56 6415 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
ebrus 0:0a673c671a56 6416
ebrus 0:0a673c671a56 6417 /******************* Bit definition for TIM_CCER register *******************/
ebrus 0:0a673c671a56 6418 #define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
ebrus 0:0a673c671a56 6419 #define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
ebrus 0:0a673c671a56 6420 #define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
ebrus 0:0a673c671a56 6421 #define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
ebrus 0:0a673c671a56 6422 #define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
ebrus 0:0a673c671a56 6423 #define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
ebrus 0:0a673c671a56 6424 #define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
ebrus 0:0a673c671a56 6425 #define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
ebrus 0:0a673c671a56 6426 #define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
ebrus 0:0a673c671a56 6427 #define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
ebrus 0:0a673c671a56 6428 #define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
ebrus 0:0a673c671a56 6429 #define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
ebrus 0:0a673c671a56 6430 #define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
ebrus 0:0a673c671a56 6431 #define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
ebrus 0:0a673c671a56 6432 #define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
ebrus 0:0a673c671a56 6433
ebrus 0:0a673c671a56 6434 /******************* Bit definition for TIM_CNT register ********************/
ebrus 0:0a673c671a56 6435 #define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
ebrus 0:0a673c671a56 6436
ebrus 0:0a673c671a56 6437 /******************* Bit definition for TIM_PSC register ********************/
ebrus 0:0a673c671a56 6438 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
ebrus 0:0a673c671a56 6439
ebrus 0:0a673c671a56 6440 /******************* Bit definition for TIM_ARR register ********************/
ebrus 0:0a673c671a56 6441 #define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
ebrus 0:0a673c671a56 6442
ebrus 0:0a673c671a56 6443 /******************* Bit definition for TIM_RCR register ********************/
ebrus 0:0a673c671a56 6444 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
ebrus 0:0a673c671a56 6445
ebrus 0:0a673c671a56 6446 /******************* Bit definition for TIM_CCR1 register *******************/
ebrus 0:0a673c671a56 6447 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
ebrus 0:0a673c671a56 6448
ebrus 0:0a673c671a56 6449 /******************* Bit definition for TIM_CCR2 register *******************/
ebrus 0:0a673c671a56 6450 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
ebrus 0:0a673c671a56 6451
ebrus 0:0a673c671a56 6452 /******************* Bit definition for TIM_CCR3 register *******************/
ebrus 0:0a673c671a56 6453 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
ebrus 0:0a673c671a56 6454
ebrus 0:0a673c671a56 6455 /******************* Bit definition for TIM_CCR4 register *******************/
ebrus 0:0a673c671a56 6456 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
ebrus 0:0a673c671a56 6457
ebrus 0:0a673c671a56 6458 /******************* Bit definition for TIM_BDTR register *******************/
ebrus 0:0a673c671a56 6459 #define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
ebrus 0:0a673c671a56 6460 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
ebrus 0:0a673c671a56 6461 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
ebrus 0:0a673c671a56 6462 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
ebrus 0:0a673c671a56 6463 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
ebrus 0:0a673c671a56 6464 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
ebrus 0:0a673c671a56 6465 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
ebrus 0:0a673c671a56 6466 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
ebrus 0:0a673c671a56 6467 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
ebrus 0:0a673c671a56 6468
ebrus 0:0a673c671a56 6469 #define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
ebrus 0:0a673c671a56 6470 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
ebrus 0:0a673c671a56 6471 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
ebrus 0:0a673c671a56 6472
ebrus 0:0a673c671a56 6473 #define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
ebrus 0:0a673c671a56 6474 #define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
ebrus 0:0a673c671a56 6475 #define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
ebrus 0:0a673c671a56 6476 #define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
ebrus 0:0a673c671a56 6477 #define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
ebrus 0:0a673c671a56 6478 #define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
ebrus 0:0a673c671a56 6479
ebrus 0:0a673c671a56 6480 /******************* Bit definition for TIM_DCR register ********************/
ebrus 0:0a673c671a56 6481 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
ebrus 0:0a673c671a56 6482 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
ebrus 0:0a673c671a56 6483 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
ebrus 0:0a673c671a56 6484 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
ebrus 0:0a673c671a56 6485 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
ebrus 0:0a673c671a56 6486 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
ebrus 0:0a673c671a56 6487
ebrus 0:0a673c671a56 6488 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
ebrus 0:0a673c671a56 6489 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
ebrus 0:0a673c671a56 6490 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
ebrus 0:0a673c671a56 6491 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
ebrus 0:0a673c671a56 6492 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
ebrus 0:0a673c671a56 6493 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
ebrus 0:0a673c671a56 6494
ebrus 0:0a673c671a56 6495 /******************* Bit definition for TIM_DMAR register *******************/
ebrus 0:0a673c671a56 6496 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
ebrus 0:0a673c671a56 6497
ebrus 0:0a673c671a56 6498 /******************* Bit definition for TIM_OR register *********************/
ebrus 0:0a673c671a56 6499 #define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
ebrus 0:0a673c671a56 6500 #define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
ebrus 0:0a673c671a56 6501 #define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
ebrus 0:0a673c671a56 6502 #define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
ebrus 0:0a673c671a56 6503 #define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*!<Bit 0 */
ebrus 0:0a673c671a56 6504 #define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*!<Bit 1 */
ebrus 0:0a673c671a56 6505
ebrus 0:0a673c671a56 6506
ebrus 0:0a673c671a56 6507 /******************************************************************************/
ebrus 0:0a673c671a56 6508 /* */
ebrus 0:0a673c671a56 6509 /* Universal Synchronous Asynchronous Receiver Transmitter */
ebrus 0:0a673c671a56 6510 /* */
ebrus 0:0a673c671a56 6511 /******************************************************************************/
ebrus 0:0a673c671a56 6512 /******************* Bit definition for USART_SR register *******************/
ebrus 0:0a673c671a56 6513 #define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
ebrus 0:0a673c671a56 6514 #define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
ebrus 0:0a673c671a56 6515 #define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
ebrus 0:0a673c671a56 6516 #define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
ebrus 0:0a673c671a56 6517 #define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
ebrus 0:0a673c671a56 6518 #define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
ebrus 0:0a673c671a56 6519 #define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
ebrus 0:0a673c671a56 6520 #define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
ebrus 0:0a673c671a56 6521 #define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
ebrus 0:0a673c671a56 6522 #define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
ebrus 0:0a673c671a56 6523
ebrus 0:0a673c671a56 6524 /******************* Bit definition for USART_DR register *******************/
ebrus 0:0a673c671a56 6525 #define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
ebrus 0:0a673c671a56 6526
ebrus 0:0a673c671a56 6527 /****************** Bit definition for USART_BRR register *******************/
ebrus 0:0a673c671a56 6528 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
ebrus 0:0a673c671a56 6529 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
ebrus 0:0a673c671a56 6530
ebrus 0:0a673c671a56 6531 /****************** Bit definition for USART_CR1 register *******************/
ebrus 0:0a673c671a56 6532 #define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
ebrus 0:0a673c671a56 6533 #define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
ebrus 0:0a673c671a56 6534 #define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
ebrus 0:0a673c671a56 6535 #define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
ebrus 0:0a673c671a56 6536 #define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
ebrus 0:0a673c671a56 6537 #define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
ebrus 0:0a673c671a56 6538 #define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
ebrus 0:0a673c671a56 6539 #define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
ebrus 0:0a673c671a56 6540 #define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
ebrus 0:0a673c671a56 6541 #define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
ebrus 0:0a673c671a56 6542 #define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
ebrus 0:0a673c671a56 6543 #define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
ebrus 0:0a673c671a56 6544 #define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
ebrus 0:0a673c671a56 6545 #define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
ebrus 0:0a673c671a56 6546 #define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversampling by 8 enable */
ebrus 0:0a673c671a56 6547
ebrus 0:0a673c671a56 6548 /****************** Bit definition for USART_CR2 register *******************/
ebrus 0:0a673c671a56 6549 #define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
ebrus 0:0a673c671a56 6550 #define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
ebrus 0:0a673c671a56 6551 #define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
ebrus 0:0a673c671a56 6552 #define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
ebrus 0:0a673c671a56 6553 #define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
ebrus 0:0a673c671a56 6554 #define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
ebrus 0:0a673c671a56 6555 #define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
ebrus 0:0a673c671a56 6556
ebrus 0:0a673c671a56 6557 #define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
ebrus 0:0a673c671a56 6558 #define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
ebrus 0:0a673c671a56 6559 #define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
ebrus 0:0a673c671a56 6560
ebrus 0:0a673c671a56 6561 #define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
ebrus 0:0a673c671a56 6562
ebrus 0:0a673c671a56 6563 /****************** Bit definition for USART_CR3 register *******************/
ebrus 0:0a673c671a56 6564 #define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
ebrus 0:0a673c671a56 6565 #define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
ebrus 0:0a673c671a56 6566 #define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
ebrus 0:0a673c671a56 6567 #define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
ebrus 0:0a673c671a56 6568 #define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
ebrus 0:0a673c671a56 6569 #define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
ebrus 0:0a673c671a56 6570 #define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
ebrus 0:0a673c671a56 6571 #define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
ebrus 0:0a673c671a56 6572 #define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
ebrus 0:0a673c671a56 6573 #define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
ebrus 0:0a673c671a56 6574 #define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
ebrus 0:0a673c671a56 6575 #define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<USART One bit method enable */
ebrus 0:0a673c671a56 6576
ebrus 0:0a673c671a56 6577 /****************** Bit definition for USART_GTPR register ******************/
ebrus 0:0a673c671a56 6578 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
ebrus 0:0a673c671a56 6579 #define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
ebrus 0:0a673c671a56 6580 #define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
ebrus 0:0a673c671a56 6581 #define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
ebrus 0:0a673c671a56 6582 #define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
ebrus 0:0a673c671a56 6583 #define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
ebrus 0:0a673c671a56 6584 #define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
ebrus 0:0a673c671a56 6585 #define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
ebrus 0:0a673c671a56 6586 #define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
ebrus 0:0a673c671a56 6587
ebrus 0:0a673c671a56 6588 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
ebrus 0:0a673c671a56 6589
ebrus 0:0a673c671a56 6590 /******************************************************************************/
ebrus 0:0a673c671a56 6591 /* */
ebrus 0:0a673c671a56 6592 /* Window WATCHDOG */
ebrus 0:0a673c671a56 6593 /* */
ebrus 0:0a673c671a56 6594 /******************************************************************************/
ebrus 0:0a673c671a56 6595 /******************* Bit definition for WWDG_CR register ********************/
ebrus 0:0a673c671a56 6596 #define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
ebrus 0:0a673c671a56 6597 #define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
ebrus 0:0a673c671a56 6598 #define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
ebrus 0:0a673c671a56 6599 #define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
ebrus 0:0a673c671a56 6600 #define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
ebrus 0:0a673c671a56 6601 #define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
ebrus 0:0a673c671a56 6602 #define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
ebrus 0:0a673c671a56 6603 #define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
ebrus 0:0a673c671a56 6604
ebrus 0:0a673c671a56 6605 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
ebrus 0:0a673c671a56 6606
ebrus 0:0a673c671a56 6607 /******************* Bit definition for WWDG_CFR register *******************/
ebrus 0:0a673c671a56 6608 #define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
ebrus 0:0a673c671a56 6609 #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
ebrus 0:0a673c671a56 6610 #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
ebrus 0:0a673c671a56 6611 #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
ebrus 0:0a673c671a56 6612 #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
ebrus 0:0a673c671a56 6613 #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
ebrus 0:0a673c671a56 6614 #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
ebrus 0:0a673c671a56 6615 #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
ebrus 0:0a673c671a56 6616
ebrus 0:0a673c671a56 6617 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
ebrus 0:0a673c671a56 6618 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
ebrus 0:0a673c671a56 6619 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
ebrus 0:0a673c671a56 6620
ebrus 0:0a673c671a56 6621 #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
ebrus 0:0a673c671a56 6622
ebrus 0:0a673c671a56 6623 /******************* Bit definition for WWDG_SR register ********************/
ebrus 0:0a673c671a56 6624 #define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
ebrus 0:0a673c671a56 6625
ebrus 0:0a673c671a56 6626
ebrus 0:0a673c671a56 6627 /******************************************************************************/
ebrus 0:0a673c671a56 6628 /* */
ebrus 0:0a673c671a56 6629 /* DBG */
ebrus 0:0a673c671a56 6630 /* */
ebrus 0:0a673c671a56 6631 /******************************************************************************/
ebrus 0:0a673c671a56 6632 /******************** Bit definition for DBGMCU_IDCODE register *************/
ebrus 0:0a673c671a56 6633 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
ebrus 0:0a673c671a56 6634 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
ebrus 0:0a673c671a56 6635
ebrus 0:0a673c671a56 6636 /******************** Bit definition for DBGMCU_CR register *****************/
ebrus 0:0a673c671a56 6637 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 6638 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 6639 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 6640 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 6641
ebrus 0:0a673c671a56 6642 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
ebrus 0:0a673c671a56 6643 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
ebrus 0:0a673c671a56 6644 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
ebrus 0:0a673c671a56 6645
ebrus 0:0a673c671a56 6646 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
ebrus 0:0a673c671a56 6647 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 6648 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 6649 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 6650 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 6651 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 6652 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 6653 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 6654 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 6655 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 6656 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 6657 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 6658 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 6659 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 6660 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 6661 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 6662 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 6663 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 6664 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
ebrus 0:0a673c671a56 6665 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
ebrus 0:0a673c671a56 6666
ebrus 0:0a673c671a56 6667 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
ebrus 0:0a673c671a56 6668 #define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 6669 #define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 6670 #define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 6671 #define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 6672 #define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 6673
ebrus 0:0a673c671a56 6674 /******************************************************************************/
ebrus 0:0a673c671a56 6675 /* */
ebrus 0:0a673c671a56 6676 /* Ethernet MAC Registers bits definitions */
ebrus 0:0a673c671a56 6677 /* */
ebrus 0:0a673c671a56 6678 /******************************************************************************/
ebrus 0:0a673c671a56 6679 /* Bit definition for Ethernet MAC Control Register register */
ebrus 0:0a673c671a56 6680 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
ebrus 0:0a673c671a56 6681 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
ebrus 0:0a673c671a56 6682 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
ebrus 0:0a673c671a56 6683 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
ebrus 0:0a673c671a56 6684 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
ebrus 0:0a673c671a56 6685 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
ebrus 0:0a673c671a56 6686 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
ebrus 0:0a673c671a56 6687 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
ebrus 0:0a673c671a56 6688 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
ebrus 0:0a673c671a56 6689 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
ebrus 0:0a673c671a56 6690 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
ebrus 0:0a673c671a56 6691 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
ebrus 0:0a673c671a56 6692 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
ebrus 0:0a673c671a56 6693 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
ebrus 0:0a673c671a56 6694 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
ebrus 0:0a673c671a56 6695 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
ebrus 0:0a673c671a56 6696 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
ebrus 0:0a673c671a56 6697 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
ebrus 0:0a673c671a56 6698 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
ebrus 0:0a673c671a56 6699 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
ebrus 0:0a673c671a56 6700 a transmission attempt during retries after a collision: 0 =< r <2^k */
ebrus 0:0a673c671a56 6701 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
ebrus 0:0a673c671a56 6702 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
ebrus 0:0a673c671a56 6703 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
ebrus 0:0a673c671a56 6704 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
ebrus 0:0a673c671a56 6705 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
ebrus 0:0a673c671a56 6706 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
ebrus 0:0a673c671a56 6707 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
ebrus 0:0a673c671a56 6708
ebrus 0:0a673c671a56 6709 /* Bit definition for Ethernet MAC Frame Filter Register */
ebrus 0:0a673c671a56 6710 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
ebrus 0:0a673c671a56 6711 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
ebrus 0:0a673c671a56 6712 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
ebrus 0:0a673c671a56 6713 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
ebrus 0:0a673c671a56 6714 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
ebrus 0:0a673c671a56 6715 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
ebrus 0:0a673c671a56 6716 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
ebrus 0:0a673c671a56 6717 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
ebrus 0:0a673c671a56 6718 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
ebrus 0:0a673c671a56 6719 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
ebrus 0:0a673c671a56 6720 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
ebrus 0:0a673c671a56 6721 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
ebrus 0:0a673c671a56 6722 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
ebrus 0:0a673c671a56 6723 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
ebrus 0:0a673c671a56 6724
ebrus 0:0a673c671a56 6725 /* Bit definition for Ethernet MAC Hash Table High Register */
ebrus 0:0a673c671a56 6726 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
ebrus 0:0a673c671a56 6727
ebrus 0:0a673c671a56 6728 /* Bit definition for Ethernet MAC Hash Table Low Register */
ebrus 0:0a673c671a56 6729 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
ebrus 0:0a673c671a56 6730
ebrus 0:0a673c671a56 6731 /* Bit definition for Ethernet MAC MII Address Register */
ebrus 0:0a673c671a56 6732 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
ebrus 0:0a673c671a56 6733 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
ebrus 0:0a673c671a56 6734 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
ebrus 0:0a673c671a56 6735 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
ebrus 0:0a673c671a56 6736 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
ebrus 0:0a673c671a56 6737 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
ebrus 0:0a673c671a56 6738 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
ebrus 0:0a673c671a56 6739 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
ebrus 0:0a673c671a56 6740 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
ebrus 0:0a673c671a56 6741 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
ebrus 0:0a673c671a56 6742
ebrus 0:0a673c671a56 6743 /* Bit definition for Ethernet MAC MII Data Register */
ebrus 0:0a673c671a56 6744 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
ebrus 0:0a673c671a56 6745
ebrus 0:0a673c671a56 6746 /* Bit definition for Ethernet MAC Flow Control Register */
ebrus 0:0a673c671a56 6747 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
ebrus 0:0a673c671a56 6748 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
ebrus 0:0a673c671a56 6749 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
ebrus 0:0a673c671a56 6750 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
ebrus 0:0a673c671a56 6751 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
ebrus 0:0a673c671a56 6752 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
ebrus 0:0a673c671a56 6753 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
ebrus 0:0a673c671a56 6754 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
ebrus 0:0a673c671a56 6755 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
ebrus 0:0a673c671a56 6756 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
ebrus 0:0a673c671a56 6757 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
ebrus 0:0a673c671a56 6758
ebrus 0:0a673c671a56 6759 /* Bit definition for Ethernet MAC VLAN Tag Register */
ebrus 0:0a673c671a56 6760 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
ebrus 0:0a673c671a56 6761 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
ebrus 0:0a673c671a56 6762
ebrus 0:0a673c671a56 6763 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
ebrus 0:0a673c671a56 6764 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
ebrus 0:0a673c671a56 6765 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
ebrus 0:0a673c671a56 6766 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
ebrus 0:0a673c671a56 6767 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
ebrus 0:0a673c671a56 6768 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
ebrus 0:0a673c671a56 6769 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
ebrus 0:0a673c671a56 6770 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
ebrus 0:0a673c671a56 6771 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
ebrus 0:0a673c671a56 6772 RSVD - Filter1 Command - RSVD - Filter0 Command
ebrus 0:0a673c671a56 6773 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
ebrus 0:0a673c671a56 6774 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
ebrus 0:0a673c671a56 6775 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
ebrus 0:0a673c671a56 6776
ebrus 0:0a673c671a56 6777 /* Bit definition for Ethernet MAC PMT Control and Status Register */
ebrus 0:0a673c671a56 6778 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
ebrus 0:0a673c671a56 6779 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
ebrus 0:0a673c671a56 6780 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
ebrus 0:0a673c671a56 6781 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
ebrus 0:0a673c671a56 6782 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
ebrus 0:0a673c671a56 6783 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
ebrus 0:0a673c671a56 6784 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
ebrus 0:0a673c671a56 6785
ebrus 0:0a673c671a56 6786 /* Bit definition for Ethernet MAC Status Register */
ebrus 0:0a673c671a56 6787 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
ebrus 0:0a673c671a56 6788 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
ebrus 0:0a673c671a56 6789 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
ebrus 0:0a673c671a56 6790 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
ebrus 0:0a673c671a56 6791 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
ebrus 0:0a673c671a56 6792
ebrus 0:0a673c671a56 6793 /* Bit definition for Ethernet MAC Interrupt Mask Register */
ebrus 0:0a673c671a56 6794 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
ebrus 0:0a673c671a56 6795 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
ebrus 0:0a673c671a56 6796
ebrus 0:0a673c671a56 6797 /* Bit definition for Ethernet MAC Address0 High Register */
ebrus 0:0a673c671a56 6798 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
ebrus 0:0a673c671a56 6799
ebrus 0:0a673c671a56 6800 /* Bit definition for Ethernet MAC Address0 Low Register */
ebrus 0:0a673c671a56 6801 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
ebrus 0:0a673c671a56 6802
ebrus 0:0a673c671a56 6803 /* Bit definition for Ethernet MAC Address1 High Register */
ebrus 0:0a673c671a56 6804 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
ebrus 0:0a673c671a56 6805 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
ebrus 0:0a673c671a56 6806 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
ebrus 0:0a673c671a56 6807 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
ebrus 0:0a673c671a56 6808 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
ebrus 0:0a673c671a56 6809 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
ebrus 0:0a673c671a56 6810 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
ebrus 0:0a673c671a56 6811 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
ebrus 0:0a673c671a56 6812 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
ebrus 0:0a673c671a56 6813 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
ebrus 0:0a673c671a56 6814
ebrus 0:0a673c671a56 6815 /* Bit definition for Ethernet MAC Address1 Low Register */
ebrus 0:0a673c671a56 6816 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
ebrus 0:0a673c671a56 6817
ebrus 0:0a673c671a56 6818 /* Bit definition for Ethernet MAC Address2 High Register */
ebrus 0:0a673c671a56 6819 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
ebrus 0:0a673c671a56 6820 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
ebrus 0:0a673c671a56 6821 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
ebrus 0:0a673c671a56 6822 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
ebrus 0:0a673c671a56 6823 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
ebrus 0:0a673c671a56 6824 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
ebrus 0:0a673c671a56 6825 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
ebrus 0:0a673c671a56 6826 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
ebrus 0:0a673c671a56 6827 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
ebrus 0:0a673c671a56 6828 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
ebrus 0:0a673c671a56 6829
ebrus 0:0a673c671a56 6830 /* Bit definition for Ethernet MAC Address2 Low Register */
ebrus 0:0a673c671a56 6831 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
ebrus 0:0a673c671a56 6832
ebrus 0:0a673c671a56 6833 /* Bit definition for Ethernet MAC Address3 High Register */
ebrus 0:0a673c671a56 6834 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
ebrus 0:0a673c671a56 6835 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
ebrus 0:0a673c671a56 6836 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
ebrus 0:0a673c671a56 6837 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
ebrus 0:0a673c671a56 6838 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
ebrus 0:0a673c671a56 6839 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
ebrus 0:0a673c671a56 6840 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
ebrus 0:0a673c671a56 6841 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
ebrus 0:0a673c671a56 6842 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
ebrus 0:0a673c671a56 6843 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
ebrus 0:0a673c671a56 6844
ebrus 0:0a673c671a56 6845 /* Bit definition for Ethernet MAC Address3 Low Register */
ebrus 0:0a673c671a56 6846 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
ebrus 0:0a673c671a56 6847
ebrus 0:0a673c671a56 6848 /******************************************************************************/
ebrus 0:0a673c671a56 6849 /* Ethernet MMC Registers bits definition */
ebrus 0:0a673c671a56 6850 /******************************************************************************/
ebrus 0:0a673c671a56 6851
ebrus 0:0a673c671a56 6852 /* Bit definition for Ethernet MMC Contol Register */
ebrus 0:0a673c671a56 6853 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
ebrus 0:0a673c671a56 6854 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
ebrus 0:0a673c671a56 6855 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
ebrus 0:0a673c671a56 6856 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
ebrus 0:0a673c671a56 6857 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
ebrus 0:0a673c671a56 6858 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
ebrus 0:0a673c671a56 6859
ebrus 0:0a673c671a56 6860 /* Bit definition for Ethernet MMC Receive Interrupt Register */
ebrus 0:0a673c671a56 6861 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
ebrus 0:0a673c671a56 6862 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
ebrus 0:0a673c671a56 6863 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
ebrus 0:0a673c671a56 6864
ebrus 0:0a673c671a56 6865 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
ebrus 0:0a673c671a56 6866 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
ebrus 0:0a673c671a56 6867 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
ebrus 0:0a673c671a56 6868 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
ebrus 0:0a673c671a56 6869
ebrus 0:0a673c671a56 6870 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
ebrus 0:0a673c671a56 6871 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
ebrus 0:0a673c671a56 6872 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
ebrus 0:0a673c671a56 6873 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
ebrus 0:0a673c671a56 6874
ebrus 0:0a673c671a56 6875 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
ebrus 0:0a673c671a56 6876 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
ebrus 0:0a673c671a56 6877 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
ebrus 0:0a673c671a56 6878 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
ebrus 0:0a673c671a56 6879
ebrus 0:0a673c671a56 6880 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
ebrus 0:0a673c671a56 6881 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
ebrus 0:0a673c671a56 6882
ebrus 0:0a673c671a56 6883 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
ebrus 0:0a673c671a56 6884 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
ebrus 0:0a673c671a56 6885
ebrus 0:0a673c671a56 6886 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
ebrus 0:0a673c671a56 6887 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
ebrus 0:0a673c671a56 6888
ebrus 0:0a673c671a56 6889 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
ebrus 0:0a673c671a56 6890 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
ebrus 0:0a673c671a56 6891
ebrus 0:0a673c671a56 6892 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
ebrus 0:0a673c671a56 6893 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
ebrus 0:0a673c671a56 6894
ebrus 0:0a673c671a56 6895 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
ebrus 0:0a673c671a56 6896 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
ebrus 0:0a673c671a56 6897
ebrus 0:0a673c671a56 6898 /******************************************************************************/
ebrus 0:0a673c671a56 6899 /* Ethernet PTP Registers bits definition */
ebrus 0:0a673c671a56 6900 /******************************************************************************/
ebrus 0:0a673c671a56 6901
ebrus 0:0a673c671a56 6902 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
ebrus 0:0a673c671a56 6903 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
ebrus 0:0a673c671a56 6904 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
ebrus 0:0a673c671a56 6905 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
ebrus 0:0a673c671a56 6906 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
ebrus 0:0a673c671a56 6907 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
ebrus 0:0a673c671a56 6908 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
ebrus 0:0a673c671a56 6909 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
ebrus 0:0a673c671a56 6910 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
ebrus 0:0a673c671a56 6911 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
ebrus 0:0a673c671a56 6912
ebrus 0:0a673c671a56 6913 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
ebrus 0:0a673c671a56 6914 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
ebrus 0:0a673c671a56 6915 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
ebrus 0:0a673c671a56 6916 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
ebrus 0:0a673c671a56 6917 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
ebrus 0:0a673c671a56 6918 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
ebrus 0:0a673c671a56 6919
ebrus 0:0a673c671a56 6920 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
ebrus 0:0a673c671a56 6921 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
ebrus 0:0a673c671a56 6922
ebrus 0:0a673c671a56 6923 /* Bit definition for Ethernet PTP Time Stamp High Register */
ebrus 0:0a673c671a56 6924 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
ebrus 0:0a673c671a56 6925
ebrus 0:0a673c671a56 6926 /* Bit definition for Ethernet PTP Time Stamp Low Register */
ebrus 0:0a673c671a56 6927 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
ebrus 0:0a673c671a56 6928 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
ebrus 0:0a673c671a56 6929
ebrus 0:0a673c671a56 6930 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
ebrus 0:0a673c671a56 6931 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
ebrus 0:0a673c671a56 6932
ebrus 0:0a673c671a56 6933 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
ebrus 0:0a673c671a56 6934 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
ebrus 0:0a673c671a56 6935 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
ebrus 0:0a673c671a56 6936
ebrus 0:0a673c671a56 6937 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
ebrus 0:0a673c671a56 6938 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
ebrus 0:0a673c671a56 6939
ebrus 0:0a673c671a56 6940 /* Bit definition for Ethernet PTP Target Time High Register */
ebrus 0:0a673c671a56 6941 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
ebrus 0:0a673c671a56 6942
ebrus 0:0a673c671a56 6943 /* Bit definition for Ethernet PTP Target Time Low Register */
ebrus 0:0a673c671a56 6944 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
ebrus 0:0a673c671a56 6945
ebrus 0:0a673c671a56 6946 /* Bit definition for Ethernet PTP Time Stamp Status Register */
ebrus 0:0a673c671a56 6947 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
ebrus 0:0a673c671a56 6948 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
ebrus 0:0a673c671a56 6949
ebrus 0:0a673c671a56 6950 /******************************************************************************/
ebrus 0:0a673c671a56 6951 /* Ethernet DMA Registers bits definition */
ebrus 0:0a673c671a56 6952 /******************************************************************************/
ebrus 0:0a673c671a56 6953
ebrus 0:0a673c671a56 6954 /* Bit definition for Ethernet DMA Bus Mode Register */
ebrus 0:0a673c671a56 6955 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
ebrus 0:0a673c671a56 6956 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
ebrus 0:0a673c671a56 6957 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
ebrus 0:0a673c671a56 6958 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
ebrus 0:0a673c671a56 6959 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
ebrus 0:0a673c671a56 6960 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
ebrus 0:0a673c671a56 6961 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
ebrus 0:0a673c671a56 6962 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
ebrus 0:0a673c671a56 6963 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
ebrus 0:0a673c671a56 6964 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
ebrus 0:0a673c671a56 6965 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
ebrus 0:0a673c671a56 6966 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
ebrus 0:0a673c671a56 6967 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
ebrus 0:0a673c671a56 6968 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
ebrus 0:0a673c671a56 6969 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
ebrus 0:0a673c671a56 6970 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
ebrus 0:0a673c671a56 6971 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
ebrus 0:0a673c671a56 6972 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
ebrus 0:0a673c671a56 6973 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
ebrus 0:0a673c671a56 6974 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
ebrus 0:0a673c671a56 6975 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
ebrus 0:0a673c671a56 6976 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
ebrus 0:0a673c671a56 6977 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
ebrus 0:0a673c671a56 6978 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
ebrus 0:0a673c671a56 6979 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
ebrus 0:0a673c671a56 6980 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
ebrus 0:0a673c671a56 6981 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
ebrus 0:0a673c671a56 6982 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
ebrus 0:0a673c671a56 6983 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
ebrus 0:0a673c671a56 6984 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
ebrus 0:0a673c671a56 6985 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
ebrus 0:0a673c671a56 6986 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
ebrus 0:0a673c671a56 6987 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
ebrus 0:0a673c671a56 6988 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
ebrus 0:0a673c671a56 6989 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
ebrus 0:0a673c671a56 6990 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
ebrus 0:0a673c671a56 6991 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
ebrus 0:0a673c671a56 6992 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
ebrus 0:0a673c671a56 6993 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
ebrus 0:0a673c671a56 6994
ebrus 0:0a673c671a56 6995 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
ebrus 0:0a673c671a56 6996 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
ebrus 0:0a673c671a56 6997
ebrus 0:0a673c671a56 6998 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
ebrus 0:0a673c671a56 6999 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
ebrus 0:0a673c671a56 7000
ebrus 0:0a673c671a56 7001 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
ebrus 0:0a673c671a56 7002 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
ebrus 0:0a673c671a56 7003
ebrus 0:0a673c671a56 7004 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
ebrus 0:0a673c671a56 7005 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
ebrus 0:0a673c671a56 7006
ebrus 0:0a673c671a56 7007 /* Bit definition for Ethernet DMA Status Register */
ebrus 0:0a673c671a56 7008 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
ebrus 0:0a673c671a56 7009 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
ebrus 0:0a673c671a56 7010 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
ebrus 0:0a673c671a56 7011 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
ebrus 0:0a673c671a56 7012 /* combination with EBS[2:0] for GetFlagStatus function */
ebrus 0:0a673c671a56 7013 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
ebrus 0:0a673c671a56 7014 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
ebrus 0:0a673c671a56 7015 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
ebrus 0:0a673c671a56 7016 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
ebrus 0:0a673c671a56 7017 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
ebrus 0:0a673c671a56 7018 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
ebrus 0:0a673c671a56 7019 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
ebrus 0:0a673c671a56 7020 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
ebrus 0:0a673c671a56 7021 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
ebrus 0:0a673c671a56 7022 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
ebrus 0:0a673c671a56 7023 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
ebrus 0:0a673c671a56 7024 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
ebrus 0:0a673c671a56 7025 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
ebrus 0:0a673c671a56 7026 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
ebrus 0:0a673c671a56 7027 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
ebrus 0:0a673c671a56 7028 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
ebrus 0:0a673c671a56 7029 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
ebrus 0:0a673c671a56 7030 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
ebrus 0:0a673c671a56 7031 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
ebrus 0:0a673c671a56 7032 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
ebrus 0:0a673c671a56 7033 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
ebrus 0:0a673c671a56 7034 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
ebrus 0:0a673c671a56 7035 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
ebrus 0:0a673c671a56 7036 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
ebrus 0:0a673c671a56 7037 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
ebrus 0:0a673c671a56 7038 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
ebrus 0:0a673c671a56 7039 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
ebrus 0:0a673c671a56 7040 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
ebrus 0:0a673c671a56 7041 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
ebrus 0:0a673c671a56 7042 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
ebrus 0:0a673c671a56 7043 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
ebrus 0:0a673c671a56 7044 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
ebrus 0:0a673c671a56 7045
ebrus 0:0a673c671a56 7046 /* Bit definition for Ethernet DMA Operation Mode Register */
ebrus 0:0a673c671a56 7047 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
ebrus 0:0a673c671a56 7048 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
ebrus 0:0a673c671a56 7049 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
ebrus 0:0a673c671a56 7050 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
ebrus 0:0a673c671a56 7051 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
ebrus 0:0a673c671a56 7052 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
ebrus 0:0a673c671a56 7053 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
ebrus 0:0a673c671a56 7054 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
ebrus 0:0a673c671a56 7055 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
ebrus 0:0a673c671a56 7056 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
ebrus 0:0a673c671a56 7057 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
ebrus 0:0a673c671a56 7058 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
ebrus 0:0a673c671a56 7059 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
ebrus 0:0a673c671a56 7060 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
ebrus 0:0a673c671a56 7061 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
ebrus 0:0a673c671a56 7062 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
ebrus 0:0a673c671a56 7063 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
ebrus 0:0a673c671a56 7064 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
ebrus 0:0a673c671a56 7065 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
ebrus 0:0a673c671a56 7066 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
ebrus 0:0a673c671a56 7067 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
ebrus 0:0a673c671a56 7068 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
ebrus 0:0a673c671a56 7069 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
ebrus 0:0a673c671a56 7070 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
ebrus 0:0a673c671a56 7071
ebrus 0:0a673c671a56 7072 /* Bit definition for Ethernet DMA Interrupt Enable Register */
ebrus 0:0a673c671a56 7073 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
ebrus 0:0a673c671a56 7074 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
ebrus 0:0a673c671a56 7075 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
ebrus 0:0a673c671a56 7076 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
ebrus 0:0a673c671a56 7077 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
ebrus 0:0a673c671a56 7078 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
ebrus 0:0a673c671a56 7079 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
ebrus 0:0a673c671a56 7080 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
ebrus 0:0a673c671a56 7081 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
ebrus 0:0a673c671a56 7082 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
ebrus 0:0a673c671a56 7083 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
ebrus 0:0a673c671a56 7084 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
ebrus 0:0a673c671a56 7085 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
ebrus 0:0a673c671a56 7086 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
ebrus 0:0a673c671a56 7087 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
ebrus 0:0a673c671a56 7088
ebrus 0:0a673c671a56 7089 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
ebrus 0:0a673c671a56 7090 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
ebrus 0:0a673c671a56 7091 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
ebrus 0:0a673c671a56 7092 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
ebrus 0:0a673c671a56 7093 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
ebrus 0:0a673c671a56 7094
ebrus 0:0a673c671a56 7095 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
ebrus 0:0a673c671a56 7096 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
ebrus 0:0a673c671a56 7097
ebrus 0:0a673c671a56 7098 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
ebrus 0:0a673c671a56 7099 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
ebrus 0:0a673c671a56 7100
ebrus 0:0a673c671a56 7101 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
ebrus 0:0a673c671a56 7102 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
ebrus 0:0a673c671a56 7103
ebrus 0:0a673c671a56 7104 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
ebrus 0:0a673c671a56 7105 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
ebrus 0:0a673c671a56 7106
ebrus 0:0a673c671a56 7107 /**
ebrus 0:0a673c671a56 7108 *
ebrus 0:0a673c671a56 7109 */
ebrus 0:0a673c671a56 7110
ebrus 0:0a673c671a56 7111 /**
ebrus 0:0a673c671a56 7112 * @}
ebrus 0:0a673c671a56 7113 */
ebrus 0:0a673c671a56 7114
ebrus 0:0a673c671a56 7115 #ifdef USE_STDPERIPH_DRIVER
ebrus 0:0a673c671a56 7116 #include "stm32f4xx_conf.h"
ebrus 0:0a673c671a56 7117 #endif /* USE_STDPERIPH_DRIVER */
ebrus 0:0a673c671a56 7118
ebrus 0:0a673c671a56 7119 /** @addtogroup Exported_macro
ebrus 0:0a673c671a56 7120 * @{
ebrus 0:0a673c671a56 7121 */
ebrus 0:0a673c671a56 7122
ebrus 0:0a673c671a56 7123 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
ebrus 0:0a673c671a56 7124
ebrus 0:0a673c671a56 7125 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
ebrus 0:0a673c671a56 7126
ebrus 0:0a673c671a56 7127 #define READ_BIT(REG, BIT) ((REG) & (BIT))
ebrus 0:0a673c671a56 7128
ebrus 0:0a673c671a56 7129 #define CLEAR_REG(REG) ((REG) = (0x0))
ebrus 0:0a673c671a56 7130
ebrus 0:0a673c671a56 7131 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
ebrus 0:0a673c671a56 7132
ebrus 0:0a673c671a56 7133 #define READ_REG(REG) ((REG))
ebrus 0:0a673c671a56 7134
ebrus 0:0a673c671a56 7135 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
ebrus 0:0a673c671a56 7136
ebrus 0:0a673c671a56 7137 /**
ebrus 0:0a673c671a56 7138 * @}
ebrus 0:0a673c671a56 7139 */
ebrus 0:0a673c671a56 7140
ebrus 0:0a673c671a56 7141 #ifdef __cplusplus
ebrus 0:0a673c671a56 7142 }
ebrus 0:0a673c671a56 7143 #endif /* __cplusplus */
ebrus 0:0a673c671a56 7144
ebrus 0:0a673c671a56 7145 #endif /* __STM32F4xx_H */
ebrus 0:0a673c671a56 7146
ebrus 0:0a673c671a56 7147 /**
ebrus 0:0a673c671a56 7148 * @}
ebrus 0:0a673c671a56 7149 */
ebrus 0:0a673c671a56 7150
ebrus 0:0a673c671a56 7151 /**
ebrus 0:0a673c671a56 7152 * @}
ebrus 0:0a673c671a56 7153 */
ebrus 0:0a673c671a56 7154
ebrus 0:0a673c671a56 7155 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/