Eli Hughes / CMSIS_DSP_401

V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.

Dependents:   MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more

core_cm4_simd.h@0:3d9c67d97d6f, 2014-07-28 (annotated)

Committer:
emh203
Date:
Mon Jul 28 15:03:15 2014 +0000
Revision:
0:3d9c67d97d6f
1st working commit.   Had to remove arm_bitreversal2.s     arm_cfft_f32.c and arm_rfft_fast_f32.c.    The .s will not assemble.      For now I removed these functions so we could at least have a library for the other functions.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emh203 0:3d9c67d97d6f 1 /**************************************************************************//**
emh203 0:3d9c67d97d6f 2 * @file core_cm4_simd.h
emh203 0:3d9c67d97d6f 3 * @brief CMSIS Cortex-M4 SIMD Header File
emh203 0:3d9c67d97d6f 4 * @version V3.30
emh203 0:3d9c67d97d6f 5 * @date 17. February 2014
emh203 0:3d9c67d97d6f 6 *
emh203 0:3d9c67d97d6f 7 * @note
emh203 0:3d9c67d97d6f 8 *
emh203 0:3d9c67d97d6f 9 ******************************************************************************/
emh203 0:3d9c67d97d6f 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
emh203 0:3d9c67d97d6f 11
emh203 0:3d9c67d97d6f 12 All rights reserved.
emh203 0:3d9c67d97d6f 13 Redistribution and use in source and binary forms, with or without
emh203 0:3d9c67d97d6f 14 modification, are permitted provided that the following conditions are met:
emh203 0:3d9c67d97d6f 15 - Redistributions of source code must retain the above copyright
emh203 0:3d9c67d97d6f 16 notice, this list of conditions and the following disclaimer.
emh203 0:3d9c67d97d6f 17 - Redistributions in binary form must reproduce the above copyright
emh203 0:3d9c67d97d6f 18 notice, this list of conditions and the following disclaimer in the
emh203 0:3d9c67d97d6f 19 documentation and/or other materials provided with the distribution.
emh203 0:3d9c67d97d6f 20 - Neither the name of ARM nor the names of its contributors may be used
emh203 0:3d9c67d97d6f 21 to endorse or promote products derived from this software without
emh203 0:3d9c67d97d6f 22 specific prior written permission.
emh203 0:3d9c67d97d6f 23 *
emh203 0:3d9c67d97d6f 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emh203 0:3d9c67d97d6f 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emh203 0:3d9c67d97d6f 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emh203 0:3d9c67d97d6f 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emh203 0:3d9c67d97d6f 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emh203 0:3d9c67d97d6f 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emh203 0:3d9c67d97d6f 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emh203 0:3d9c67d97d6f 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emh203 0:3d9c67d97d6f 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emh203 0:3d9c67d97d6f 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emh203 0:3d9c67d97d6f 34 POSSIBILITY OF SUCH DAMAGE.
emh203 0:3d9c67d97d6f 35 ---------------------------------------------------------------------------*/
emh203 0:3d9c67d97d6f 36
emh203 0:3d9c67d97d6f 37
emh203 0:3d9c67d97d6f 38 #if defined ( __ICCARM__ )
emh203 0:3d9c67d97d6f 39 #pragma system_include /* treat file as system include file for MISRA check */
emh203 0:3d9c67d97d6f 40 #endif
emh203 0:3d9c67d97d6f 41
emh203 0:3d9c67d97d6f 42 #ifndef __CORE_CM4_SIMD_H
emh203 0:3d9c67d97d6f 43 #define __CORE_CM4_SIMD_H
emh203 0:3d9c67d97d6f 44
emh203 0:3d9c67d97d6f 45 #ifdef __cplusplus
emh203 0:3d9c67d97d6f 46 extern "C" {
emh203 0:3d9c67d97d6f 47 #endif
emh203 0:3d9c67d97d6f 48
emh203 0:3d9c67d97d6f 49
emh203 0:3d9c67d97d6f 50 /*******************************************************************************
emh203 0:3d9c67d97d6f 51 * Hardware Abstraction Layer
emh203 0:3d9c67d97d6f 52 ******************************************************************************/
emh203 0:3d9c67d97d6f 53
emh203 0:3d9c67d97d6f 54
emh203 0:3d9c67d97d6f 55 /* ################### Compiler specific Intrinsics ########################### */
emh203 0:3d9c67d97d6f 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
emh203 0:3d9c67d97d6f 57 Access to dedicated SIMD instructions
emh203 0:3d9c67d97d6f 58 @{
emh203 0:3d9c67d97d6f 59 */
emh203 0:3d9c67d97d6f 60
emh203 0:3d9c67d97d6f 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emh203 0:3d9c67d97d6f 62 /* ARM armcc specific functions */
emh203 0:3d9c67d97d6f 63 #define __SADD8 __sadd8
emh203 0:3d9c67d97d6f 64 #define __QADD8 __qadd8
emh203 0:3d9c67d97d6f 65 #define __SHADD8 __shadd8
emh203 0:3d9c67d97d6f 66 #define __UADD8 __uadd8
emh203 0:3d9c67d97d6f 67 #define __UQADD8 __uqadd8
emh203 0:3d9c67d97d6f 68 #define __UHADD8 __uhadd8
emh203 0:3d9c67d97d6f 69 #define __SSUB8 __ssub8
emh203 0:3d9c67d97d6f 70 #define __QSUB8 __qsub8
emh203 0:3d9c67d97d6f 71 #define __SHSUB8 __shsub8
emh203 0:3d9c67d97d6f 72 #define __USUB8 __usub8
emh203 0:3d9c67d97d6f 73 #define __UQSUB8 __uqsub8
emh203 0:3d9c67d97d6f 74 #define __UHSUB8 __uhsub8
emh203 0:3d9c67d97d6f 75 #define __SADD16 __sadd16
emh203 0:3d9c67d97d6f 76 #define __QADD16 __qadd16
emh203 0:3d9c67d97d6f 77 #define __SHADD16 __shadd16
emh203 0:3d9c67d97d6f 78 #define __UADD16 __uadd16
emh203 0:3d9c67d97d6f 79 #define __UQADD16 __uqadd16
emh203 0:3d9c67d97d6f 80 #define __UHADD16 __uhadd16
emh203 0:3d9c67d97d6f 81 #define __SSUB16 __ssub16
emh203 0:3d9c67d97d6f 82 #define __QSUB16 __qsub16
emh203 0:3d9c67d97d6f 83 #define __SHSUB16 __shsub16
emh203 0:3d9c67d97d6f 84 #define __USUB16 __usub16
emh203 0:3d9c67d97d6f 85 #define __UQSUB16 __uqsub16
emh203 0:3d9c67d97d6f 86 #define __UHSUB16 __uhsub16
emh203 0:3d9c67d97d6f 87 #define __SASX __sasx
emh203 0:3d9c67d97d6f 88 #define __QASX __qasx
emh203 0:3d9c67d97d6f 89 #define __SHASX __shasx
emh203 0:3d9c67d97d6f 90 #define __UASX __uasx
emh203 0:3d9c67d97d6f 91 #define __UQASX __uqasx
emh203 0:3d9c67d97d6f 92 #define __UHASX __uhasx
emh203 0:3d9c67d97d6f 93 #define __SSAX __ssax
emh203 0:3d9c67d97d6f 94 #define __QSAX __qsax
emh203 0:3d9c67d97d6f 95 #define __SHSAX __shsax
emh203 0:3d9c67d97d6f 96 #define __USAX __usax
emh203 0:3d9c67d97d6f 97 #define __UQSAX __uqsax
emh203 0:3d9c67d97d6f 98 #define __UHSAX __uhsax
emh203 0:3d9c67d97d6f 99 #define __USAD8 __usad8
emh203 0:3d9c67d97d6f 100 #define __USADA8 __usada8
emh203 0:3d9c67d97d6f 101 #define __SSAT16 __ssat16
emh203 0:3d9c67d97d6f 102 #define __USAT16 __usat16
emh203 0:3d9c67d97d6f 103 #define __UXTB16 __uxtb16
emh203 0:3d9c67d97d6f 104 #define __UXTAB16 __uxtab16
emh203 0:3d9c67d97d6f 105 #define __SXTB16 __sxtb16
emh203 0:3d9c67d97d6f 106 #define __SXTAB16 __sxtab16
emh203 0:3d9c67d97d6f 107 #define __SMUAD __smuad
emh203 0:3d9c67d97d6f 108 #define __SMUADX __smuadx
emh203 0:3d9c67d97d6f 109 #define __SMLAD __smlad
emh203 0:3d9c67d97d6f 110 #define __SMLADX __smladx
emh203 0:3d9c67d97d6f 111 #define __SMLALD __smlald
emh203 0:3d9c67d97d6f 112 #define __SMLALDX __smlaldx
emh203 0:3d9c67d97d6f 113 #define __SMUSD __smusd
emh203 0:3d9c67d97d6f 114 #define __SMUSDX __smusdx
emh203 0:3d9c67d97d6f 115 #define __SMLSD __smlsd
emh203 0:3d9c67d97d6f 116 #define __SMLSDX __smlsdx
emh203 0:3d9c67d97d6f 117 #define __SMLSLD __smlsld
emh203 0:3d9c67d97d6f 118 #define __SMLSLDX __smlsldx
emh203 0:3d9c67d97d6f 119 #define __SEL __sel
emh203 0:3d9c67d97d6f 120 #define __QADD __qadd
emh203 0:3d9c67d97d6f 121 #define __QSUB __qsub
emh203 0:3d9c67d97d6f 122
emh203 0:3d9c67d97d6f 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
emh203 0:3d9c67d97d6f 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
emh203 0:3d9c67d97d6f 125
emh203 0:3d9c67d97d6f 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
emh203 0:3d9c67d97d6f 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
emh203 0:3d9c67d97d6f 128
emh203 0:3d9c67d97d6f 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
emh203 0:3d9c67d97d6f 130 ((int64_t)(ARG3) << 32) ) >> 32))
emh203 0:3d9c67d97d6f 131
emh203 0:3d9c67d97d6f 132
emh203 0:3d9c67d97d6f 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emh203 0:3d9c67d97d6f 134 /* GNU gcc specific functions */
emh203 0:3d9c67d97d6f 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 136 {
emh203 0:3d9c67d97d6f 137 uint32_t result;
emh203 0:3d9c67d97d6f 138
emh203 0:3d9c67d97d6f 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 140 return(result);
emh203 0:3d9c67d97d6f 141 }
emh203 0:3d9c67d97d6f 142
emh203 0:3d9c67d97d6f 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 144 {
emh203 0:3d9c67d97d6f 145 uint32_t result;
emh203 0:3d9c67d97d6f 146
emh203 0:3d9c67d97d6f 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 148 return(result);
emh203 0:3d9c67d97d6f 149 }
emh203 0:3d9c67d97d6f 150
emh203 0:3d9c67d97d6f 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 152 {
emh203 0:3d9c67d97d6f 153 uint32_t result;
emh203 0:3d9c67d97d6f 154
emh203 0:3d9c67d97d6f 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 156 return(result);
emh203 0:3d9c67d97d6f 157 }
emh203 0:3d9c67d97d6f 158
emh203 0:3d9c67d97d6f 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 160 {
emh203 0:3d9c67d97d6f 161 uint32_t result;
emh203 0:3d9c67d97d6f 162
emh203 0:3d9c67d97d6f 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 164 return(result);
emh203 0:3d9c67d97d6f 165 }
emh203 0:3d9c67d97d6f 166
emh203 0:3d9c67d97d6f 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 168 {
emh203 0:3d9c67d97d6f 169 uint32_t result;
emh203 0:3d9c67d97d6f 170
emh203 0:3d9c67d97d6f 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 172 return(result);
emh203 0:3d9c67d97d6f 173 }
emh203 0:3d9c67d97d6f 174
emh203 0:3d9c67d97d6f 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 176 {
emh203 0:3d9c67d97d6f 177 uint32_t result;
emh203 0:3d9c67d97d6f 178
emh203 0:3d9c67d97d6f 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 180 return(result);
emh203 0:3d9c67d97d6f 181 }
emh203 0:3d9c67d97d6f 182
emh203 0:3d9c67d97d6f 183
emh203 0:3d9c67d97d6f 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 185 {
emh203 0:3d9c67d97d6f 186 uint32_t result;
emh203 0:3d9c67d97d6f 187
emh203 0:3d9c67d97d6f 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 189 return(result);
emh203 0:3d9c67d97d6f 190 }
emh203 0:3d9c67d97d6f 191
emh203 0:3d9c67d97d6f 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 193 {
emh203 0:3d9c67d97d6f 194 uint32_t result;
emh203 0:3d9c67d97d6f 195
emh203 0:3d9c67d97d6f 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 197 return(result);
emh203 0:3d9c67d97d6f 198 }
emh203 0:3d9c67d97d6f 199
emh203 0:3d9c67d97d6f 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 201 {
emh203 0:3d9c67d97d6f 202 uint32_t result;
emh203 0:3d9c67d97d6f 203
emh203 0:3d9c67d97d6f 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 205 return(result);
emh203 0:3d9c67d97d6f 206 }
emh203 0:3d9c67d97d6f 207
emh203 0:3d9c67d97d6f 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 209 {
emh203 0:3d9c67d97d6f 210 uint32_t result;
emh203 0:3d9c67d97d6f 211
emh203 0:3d9c67d97d6f 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 213 return(result);
emh203 0:3d9c67d97d6f 214 }
emh203 0:3d9c67d97d6f 215
emh203 0:3d9c67d97d6f 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 217 {
emh203 0:3d9c67d97d6f 218 uint32_t result;
emh203 0:3d9c67d97d6f 219
emh203 0:3d9c67d97d6f 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 221 return(result);
emh203 0:3d9c67d97d6f 222 }
emh203 0:3d9c67d97d6f 223
emh203 0:3d9c67d97d6f 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 225 {
emh203 0:3d9c67d97d6f 226 uint32_t result;
emh203 0:3d9c67d97d6f 227
emh203 0:3d9c67d97d6f 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 229 return(result);
emh203 0:3d9c67d97d6f 230 }
emh203 0:3d9c67d97d6f 231
emh203 0:3d9c67d97d6f 232
emh203 0:3d9c67d97d6f 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 234 {
emh203 0:3d9c67d97d6f 235 uint32_t result;
emh203 0:3d9c67d97d6f 236
emh203 0:3d9c67d97d6f 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 238 return(result);
emh203 0:3d9c67d97d6f 239 }
emh203 0:3d9c67d97d6f 240
emh203 0:3d9c67d97d6f 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 242 {
emh203 0:3d9c67d97d6f 243 uint32_t result;
emh203 0:3d9c67d97d6f 244
emh203 0:3d9c67d97d6f 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 246 return(result);
emh203 0:3d9c67d97d6f 247 }
emh203 0:3d9c67d97d6f 248
emh203 0:3d9c67d97d6f 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 250 {
emh203 0:3d9c67d97d6f 251 uint32_t result;
emh203 0:3d9c67d97d6f 252
emh203 0:3d9c67d97d6f 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 254 return(result);
emh203 0:3d9c67d97d6f 255 }
emh203 0:3d9c67d97d6f 256
emh203 0:3d9c67d97d6f 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 258 {
emh203 0:3d9c67d97d6f 259 uint32_t result;
emh203 0:3d9c67d97d6f 260
emh203 0:3d9c67d97d6f 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 262 return(result);
emh203 0:3d9c67d97d6f 263 }
emh203 0:3d9c67d97d6f 264
emh203 0:3d9c67d97d6f 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 266 {
emh203 0:3d9c67d97d6f 267 uint32_t result;
emh203 0:3d9c67d97d6f 268
emh203 0:3d9c67d97d6f 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 270 return(result);
emh203 0:3d9c67d97d6f 271 }
emh203 0:3d9c67d97d6f 272
emh203 0:3d9c67d97d6f 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 274 {
emh203 0:3d9c67d97d6f 275 uint32_t result;
emh203 0:3d9c67d97d6f 276
emh203 0:3d9c67d97d6f 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 278 return(result);
emh203 0:3d9c67d97d6f 279 }
emh203 0:3d9c67d97d6f 280
emh203 0:3d9c67d97d6f 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 282 {
emh203 0:3d9c67d97d6f 283 uint32_t result;
emh203 0:3d9c67d97d6f 284
emh203 0:3d9c67d97d6f 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 286 return(result);
emh203 0:3d9c67d97d6f 287 }
emh203 0:3d9c67d97d6f 288
emh203 0:3d9c67d97d6f 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 290 {
emh203 0:3d9c67d97d6f 291 uint32_t result;
emh203 0:3d9c67d97d6f 292
emh203 0:3d9c67d97d6f 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 294 return(result);
emh203 0:3d9c67d97d6f 295 }
emh203 0:3d9c67d97d6f 296
emh203 0:3d9c67d97d6f 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 298 {
emh203 0:3d9c67d97d6f 299 uint32_t result;
emh203 0:3d9c67d97d6f 300
emh203 0:3d9c67d97d6f 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 302 return(result);
emh203 0:3d9c67d97d6f 303 }
emh203 0:3d9c67d97d6f 304
emh203 0:3d9c67d97d6f 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 306 {
emh203 0:3d9c67d97d6f 307 uint32_t result;
emh203 0:3d9c67d97d6f 308
emh203 0:3d9c67d97d6f 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 310 return(result);
emh203 0:3d9c67d97d6f 311 }
emh203 0:3d9c67d97d6f 312
emh203 0:3d9c67d97d6f 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 314 {
emh203 0:3d9c67d97d6f 315 uint32_t result;
emh203 0:3d9c67d97d6f 316
emh203 0:3d9c67d97d6f 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 318 return(result);
emh203 0:3d9c67d97d6f 319 }
emh203 0:3d9c67d97d6f 320
emh203 0:3d9c67d97d6f 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 322 {
emh203 0:3d9c67d97d6f 323 uint32_t result;
emh203 0:3d9c67d97d6f 324
emh203 0:3d9c67d97d6f 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 326 return(result);
emh203 0:3d9c67d97d6f 327 }
emh203 0:3d9c67d97d6f 328
emh203 0:3d9c67d97d6f 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 330 {
emh203 0:3d9c67d97d6f 331 uint32_t result;
emh203 0:3d9c67d97d6f 332
emh203 0:3d9c67d97d6f 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 334 return(result);
emh203 0:3d9c67d97d6f 335 }
emh203 0:3d9c67d97d6f 336
emh203 0:3d9c67d97d6f 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 338 {
emh203 0:3d9c67d97d6f 339 uint32_t result;
emh203 0:3d9c67d97d6f 340
emh203 0:3d9c67d97d6f 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 342 return(result);
emh203 0:3d9c67d97d6f 343 }
emh203 0:3d9c67d97d6f 344
emh203 0:3d9c67d97d6f 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 346 {
emh203 0:3d9c67d97d6f 347 uint32_t result;
emh203 0:3d9c67d97d6f 348
emh203 0:3d9c67d97d6f 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 350 return(result);
emh203 0:3d9c67d97d6f 351 }
emh203 0:3d9c67d97d6f 352
emh203 0:3d9c67d97d6f 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 354 {
emh203 0:3d9c67d97d6f 355 uint32_t result;
emh203 0:3d9c67d97d6f 356
emh203 0:3d9c67d97d6f 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 358 return(result);
emh203 0:3d9c67d97d6f 359 }
emh203 0:3d9c67d97d6f 360
emh203 0:3d9c67d97d6f 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 362 {
emh203 0:3d9c67d97d6f 363 uint32_t result;
emh203 0:3d9c67d97d6f 364
emh203 0:3d9c67d97d6f 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 366 return(result);
emh203 0:3d9c67d97d6f 367 }
emh203 0:3d9c67d97d6f 368
emh203 0:3d9c67d97d6f 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 370 {
emh203 0:3d9c67d97d6f 371 uint32_t result;
emh203 0:3d9c67d97d6f 372
emh203 0:3d9c67d97d6f 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 374 return(result);
emh203 0:3d9c67d97d6f 375 }
emh203 0:3d9c67d97d6f 376
emh203 0:3d9c67d97d6f 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 378 {
emh203 0:3d9c67d97d6f 379 uint32_t result;
emh203 0:3d9c67d97d6f 380
emh203 0:3d9c67d97d6f 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 382 return(result);
emh203 0:3d9c67d97d6f 383 }
emh203 0:3d9c67d97d6f 384
emh203 0:3d9c67d97d6f 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 386 {
emh203 0:3d9c67d97d6f 387 uint32_t result;
emh203 0:3d9c67d97d6f 388
emh203 0:3d9c67d97d6f 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 390 return(result);
emh203 0:3d9c67d97d6f 391 }
emh203 0:3d9c67d97d6f 392
emh203 0:3d9c67d97d6f 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 394 {
emh203 0:3d9c67d97d6f 395 uint32_t result;
emh203 0:3d9c67d97d6f 396
emh203 0:3d9c67d97d6f 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 398 return(result);
emh203 0:3d9c67d97d6f 399 }
emh203 0:3d9c67d97d6f 400
emh203 0:3d9c67d97d6f 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 402 {
emh203 0:3d9c67d97d6f 403 uint32_t result;
emh203 0:3d9c67d97d6f 404
emh203 0:3d9c67d97d6f 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 406 return(result);
emh203 0:3d9c67d97d6f 407 }
emh203 0:3d9c67d97d6f 408
emh203 0:3d9c67d97d6f 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 410 {
emh203 0:3d9c67d97d6f 411 uint32_t result;
emh203 0:3d9c67d97d6f 412
emh203 0:3d9c67d97d6f 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 414 return(result);
emh203 0:3d9c67d97d6f 415 }
emh203 0:3d9c67d97d6f 416
emh203 0:3d9c67d97d6f 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 418 {
emh203 0:3d9c67d97d6f 419 uint32_t result;
emh203 0:3d9c67d97d6f 420
emh203 0:3d9c67d97d6f 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 422 return(result);
emh203 0:3d9c67d97d6f 423 }
emh203 0:3d9c67d97d6f 424
emh203 0:3d9c67d97d6f 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 426 {
emh203 0:3d9c67d97d6f 427 uint32_t result;
emh203 0:3d9c67d97d6f 428
emh203 0:3d9c67d97d6f 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 430 return(result);
emh203 0:3d9c67d97d6f 431 }
emh203 0:3d9c67d97d6f 432
emh203 0:3d9c67d97d6f 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
emh203 0:3d9c67d97d6f 434 {
emh203 0:3d9c67d97d6f 435 uint32_t result;
emh203 0:3d9c67d97d6f 436
emh203 0:3d9c67d97d6f 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emh203 0:3d9c67d97d6f 438 return(result);
emh203 0:3d9c67d97d6f 439 }
emh203 0:3d9c67d97d6f 440
emh203 0:3d9c67d97d6f 441 #define __SSAT16(ARG1,ARG2) \
emh203 0:3d9c67d97d6f 442 ({ \
emh203 0:3d9c67d97d6f 443 uint32_t __RES, __ARG1 = (ARG1); \
emh203 0:3d9c67d97d6f 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emh203 0:3d9c67d97d6f 445 __RES; \
emh203 0:3d9c67d97d6f 446 })
emh203 0:3d9c67d97d6f 447
emh203 0:3d9c67d97d6f 448 #define __USAT16(ARG1,ARG2) \
emh203 0:3d9c67d97d6f 449 ({ \
emh203 0:3d9c67d97d6f 450 uint32_t __RES, __ARG1 = (ARG1); \
emh203 0:3d9c67d97d6f 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emh203 0:3d9c67d97d6f 452 __RES; \
emh203 0:3d9c67d97d6f 453 })
emh203 0:3d9c67d97d6f 454
emh203 0:3d9c67d97d6f 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
emh203 0:3d9c67d97d6f 456 {
emh203 0:3d9c67d97d6f 457 uint32_t result;
emh203 0:3d9c67d97d6f 458
emh203 0:3d9c67d97d6f 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
emh203 0:3d9c67d97d6f 460 return(result);
emh203 0:3d9c67d97d6f 461 }
emh203 0:3d9c67d97d6f 462
emh203 0:3d9c67d97d6f 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 464 {
emh203 0:3d9c67d97d6f 465 uint32_t result;
emh203 0:3d9c67d97d6f 466
emh203 0:3d9c67d97d6f 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 468 return(result);
emh203 0:3d9c67d97d6f 469 }
emh203 0:3d9c67d97d6f 470
emh203 0:3d9c67d97d6f 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
emh203 0:3d9c67d97d6f 472 {
emh203 0:3d9c67d97d6f 473 uint32_t result;
emh203 0:3d9c67d97d6f 474
emh203 0:3d9c67d97d6f 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
emh203 0:3d9c67d97d6f 476 return(result);
emh203 0:3d9c67d97d6f 477 }
emh203 0:3d9c67d97d6f 478
emh203 0:3d9c67d97d6f 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 480 {
emh203 0:3d9c67d97d6f 481 uint32_t result;
emh203 0:3d9c67d97d6f 482
emh203 0:3d9c67d97d6f 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 484 return(result);
emh203 0:3d9c67d97d6f 485 }
emh203 0:3d9c67d97d6f 486
emh203 0:3d9c67d97d6f 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 488 {
emh203 0:3d9c67d97d6f 489 uint32_t result;
emh203 0:3d9c67d97d6f 490
emh203 0:3d9c67d97d6f 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 492 return(result);
emh203 0:3d9c67d97d6f 493 }
emh203 0:3d9c67d97d6f 494
emh203 0:3d9c67d97d6f 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 496 {
emh203 0:3d9c67d97d6f 497 uint32_t result;
emh203 0:3d9c67d97d6f 498
emh203 0:3d9c67d97d6f 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 500 return(result);
emh203 0:3d9c67d97d6f 501 }
emh203 0:3d9c67d97d6f 502
emh203 0:3d9c67d97d6f 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
emh203 0:3d9c67d97d6f 504 {
emh203 0:3d9c67d97d6f 505 uint32_t result;
emh203 0:3d9c67d97d6f 506
emh203 0:3d9c67d97d6f 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emh203 0:3d9c67d97d6f 508 return(result);
emh203 0:3d9c67d97d6f 509 }
emh203 0:3d9c67d97d6f 510
emh203 0:3d9c67d97d6f 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
emh203 0:3d9c67d97d6f 512 {
emh203 0:3d9c67d97d6f 513 uint32_t result;
emh203 0:3d9c67d97d6f 514
emh203 0:3d9c67d97d6f 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emh203 0:3d9c67d97d6f 516 return(result);
emh203 0:3d9c67d97d6f 517 }
emh203 0:3d9c67d97d6f 518
emh203 0:3d9c67d97d6f 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
emh203 0:3d9c67d97d6f 520 {
emh203 0:3d9c67d97d6f 521 union llreg_u{
emh203 0:3d9c67d97d6f 522 uint32_t w32[2];
emh203 0:3d9c67d97d6f 523 uint64_t w64;
emh203 0:3d9c67d97d6f 524 } llr;
emh203 0:3d9c67d97d6f 525 llr.w64 = acc;
emh203 0:3d9c67d97d6f 526
emh203 0:3d9c67d97d6f 527 #ifndef __ARMEB__ // Little endian
emh203 0:3d9c67d97d6f 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
emh203 0:3d9c67d97d6f 529 #else // Big endian
emh203 0:3d9c67d97d6f 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
emh203 0:3d9c67d97d6f 531 #endif
emh203 0:3d9c67d97d6f 532
emh203 0:3d9c67d97d6f 533 return(llr.w64);
emh203 0:3d9c67d97d6f 534 }
emh203 0:3d9c67d97d6f 535
emh203 0:3d9c67d97d6f 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
emh203 0:3d9c67d97d6f 537 {
emh203 0:3d9c67d97d6f 538 union llreg_u{
emh203 0:3d9c67d97d6f 539 uint32_t w32[2];
emh203 0:3d9c67d97d6f 540 uint64_t w64;
emh203 0:3d9c67d97d6f 541 } llr;
emh203 0:3d9c67d97d6f 542 llr.w64 = acc;
emh203 0:3d9c67d97d6f 543
emh203 0:3d9c67d97d6f 544 #ifndef __ARMEB__ // Little endian
emh203 0:3d9c67d97d6f 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
emh203 0:3d9c67d97d6f 546 #else // Big endian
emh203 0:3d9c67d97d6f 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
emh203 0:3d9c67d97d6f 548 #endif
emh203 0:3d9c67d97d6f 549
emh203 0:3d9c67d97d6f 550 return(llr.w64);
emh203 0:3d9c67d97d6f 551 }
emh203 0:3d9c67d97d6f 552
emh203 0:3d9c67d97d6f 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 554 {
emh203 0:3d9c67d97d6f 555 uint32_t result;
emh203 0:3d9c67d97d6f 556
emh203 0:3d9c67d97d6f 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 558 return(result);
emh203 0:3d9c67d97d6f 559 }
emh203 0:3d9c67d97d6f 560
emh203 0:3d9c67d97d6f 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 562 {
emh203 0:3d9c67d97d6f 563 uint32_t result;
emh203 0:3d9c67d97d6f 564
emh203 0:3d9c67d97d6f 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 566 return(result);
emh203 0:3d9c67d97d6f 567 }
emh203 0:3d9c67d97d6f 568
emh203 0:3d9c67d97d6f 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
emh203 0:3d9c67d97d6f 570 {
emh203 0:3d9c67d97d6f 571 uint32_t result;
emh203 0:3d9c67d97d6f 572
emh203 0:3d9c67d97d6f 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emh203 0:3d9c67d97d6f 574 return(result);
emh203 0:3d9c67d97d6f 575 }
emh203 0:3d9c67d97d6f 576
emh203 0:3d9c67d97d6f 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
emh203 0:3d9c67d97d6f 578 {
emh203 0:3d9c67d97d6f 579 uint32_t result;
emh203 0:3d9c67d97d6f 580
emh203 0:3d9c67d97d6f 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
emh203 0:3d9c67d97d6f 582 return(result);
emh203 0:3d9c67d97d6f 583 }
emh203 0:3d9c67d97d6f 584
emh203 0:3d9c67d97d6f 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
emh203 0:3d9c67d97d6f 586 {
emh203 0:3d9c67d97d6f 587 union llreg_u{
emh203 0:3d9c67d97d6f 588 uint32_t w32[2];
emh203 0:3d9c67d97d6f 589 uint64_t w64;
emh203 0:3d9c67d97d6f 590 } llr;
emh203 0:3d9c67d97d6f 591 llr.w64 = acc;
emh203 0:3d9c67d97d6f 592
emh203 0:3d9c67d97d6f 593 #ifndef __ARMEB__ // Little endian
emh203 0:3d9c67d97d6f 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
emh203 0:3d9c67d97d6f 595 #else // Big endian
emh203 0:3d9c67d97d6f 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
emh203 0:3d9c67d97d6f 597 #endif
emh203 0:3d9c67d97d6f 598
emh203 0:3d9c67d97d6f 599 return(llr.w64);
emh203 0:3d9c67d97d6f 600 }
emh203 0:3d9c67d97d6f 601
emh203 0:3d9c67d97d6f 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
emh203 0:3d9c67d97d6f 603 {
emh203 0:3d9c67d97d6f 604 union llreg_u{
emh203 0:3d9c67d97d6f 605 uint32_t w32[2];
emh203 0:3d9c67d97d6f 606 uint64_t w64;
emh203 0:3d9c67d97d6f 607 } llr;
emh203 0:3d9c67d97d6f 608 llr.w64 = acc;
emh203 0:3d9c67d97d6f 609
emh203 0:3d9c67d97d6f 610 #ifndef __ARMEB__ // Little endian
emh203 0:3d9c67d97d6f 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
emh203 0:3d9c67d97d6f 612 #else // Big endian
emh203 0:3d9c67d97d6f 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
emh203 0:3d9c67d97d6f 614 #endif
emh203 0:3d9c67d97d6f 615
emh203 0:3d9c67d97d6f 616 return(llr.w64);
emh203 0:3d9c67d97d6f 617 }
emh203 0:3d9c67d97d6f 618
emh203 0:3d9c67d97d6f 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 620 {
emh203 0:3d9c67d97d6f 621 uint32_t result;
emh203 0:3d9c67d97d6f 622
emh203 0:3d9c67d97d6f 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 624 return(result);
emh203 0:3d9c67d97d6f 625 }
emh203 0:3d9c67d97d6f 626
emh203 0:3d9c67d97d6f 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 628 {
emh203 0:3d9c67d97d6f 629 uint32_t result;
emh203 0:3d9c67d97d6f 630
emh203 0:3d9c67d97d6f 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 632 return(result);
emh203 0:3d9c67d97d6f 633 }
emh203 0:3d9c67d97d6f 634
emh203 0:3d9c67d97d6f 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
emh203 0:3d9c67d97d6f 636 {
emh203 0:3d9c67d97d6f 637 uint32_t result;
emh203 0:3d9c67d97d6f 638
emh203 0:3d9c67d97d6f 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
emh203 0:3d9c67d97d6f 640 return(result);
emh203 0:3d9c67d97d6f 641 }
emh203 0:3d9c67d97d6f 642
emh203 0:3d9c67d97d6f 643 #define __PKHBT(ARG1,ARG2,ARG3) \
emh203 0:3d9c67d97d6f 644 ({ \
emh203 0:3d9c67d97d6f 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
emh203 0:3d9c67d97d6f 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
emh203 0:3d9c67d97d6f 647 __RES; \
emh203 0:3d9c67d97d6f 648 })
emh203 0:3d9c67d97d6f 649
emh203 0:3d9c67d97d6f 650 #define __PKHTB(ARG1,ARG2,ARG3) \
emh203 0:3d9c67d97d6f 651 ({ \
emh203 0:3d9c67d97d6f 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
emh203 0:3d9c67d97d6f 653 if (ARG3 == 0) \
emh203 0:3d9c67d97d6f 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
emh203 0:3d9c67d97d6f 655 else \
emh203 0:3d9c67d97d6f 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
emh203 0:3d9c67d97d6f 657 __RES; \
emh203 0:3d9c67d97d6f 658 })
emh203 0:3d9c67d97d6f 659
emh203 0:3d9c67d97d6f 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
emh203 0:3d9c67d97d6f 661 {
emh203 0:3d9c67d97d6f 662 int32_t result;
emh203 0:3d9c67d97d6f 663
emh203 0:3d9c67d97d6f 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
emh203 0:3d9c67d97d6f 665 return(result);
emh203 0:3d9c67d97d6f 666 }
emh203 0:3d9c67d97d6f 667
emh203 0:3d9c67d97d6f 668
emh203 0:3d9c67d97d6f 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emh203 0:3d9c67d97d6f 670 /* IAR iccarm specific functions */
emh203 0:3d9c67d97d6f 671 #include <cmsis_iar.h>
emh203 0:3d9c67d97d6f 672
emh203 0:3d9c67d97d6f 673
emh203 0:3d9c67d97d6f 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emh203 0:3d9c67d97d6f 675 /* TI CCS specific functions */
emh203 0:3d9c67d97d6f 676 #include <cmsis_ccs.h>
emh203 0:3d9c67d97d6f 677
emh203 0:3d9c67d97d6f 678
emh203 0:3d9c67d97d6f 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emh203 0:3d9c67d97d6f 680 /* TASKING carm specific functions */
emh203 0:3d9c67d97d6f 681 /* not yet supported */
emh203 0:3d9c67d97d6f 682
emh203 0:3d9c67d97d6f 683
emh203 0:3d9c67d97d6f 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
emh203 0:3d9c67d97d6f 685 /* Cosmic specific functions */
emh203 0:3d9c67d97d6f 686 #include <cmsis_csm.h>
emh203 0:3d9c67d97d6f 687
emh203 0:3d9c67d97d6f 688 #endif
emh203 0:3d9c67d97d6f 689
emh203 0:3d9c67d97d6f 690 /*@} end of group CMSIS_SIMD_intrinsics */
emh203 0:3d9c67d97d6f 691
emh203 0:3d9c67d97d6f 692
emh203 0:3d9c67d97d6f 693 #ifdef __cplusplus
emh203 0:3d9c67d97d6f 694 }
emh203 0:3d9c67d97d6f 695 #endif
emh203 0:3d9c67d97d6f 696
emh203 0:3d9c67d97d6f 697 #endif /* __CORE_CM4_SIMD_H */