V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.
Dependents: MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more
FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
- Committer:
- emh203
- Date:
- 2014-07-28
- Revision:
- 0:3d9c67d97d6f
File content as of revision 0:3d9c67d97d6f:
/* ---------------------------------------------------------------------- * Copyright (C) 2010-2014 ARM Limited. All rights reserved. * * $Date: 12. March 2014 * $Revision: V1.4.3 * * Project: CMSIS DSP Library * Title: arm_biquad_cascade_df1_32x64_init_q31.c * * Description: High precision Q31 Biquad cascade filter initialization function. * * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * - Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * - Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * - Neither the name of ARM LIMITED nor the names of its contributors * may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * -------------------------------------------------------------------- */ #include "arm_math.h" /** * @ingroup groupFilters */ /** * @addtogroup BiquadCascadeDF1_32x64 * @{ */ /** * @details * * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format. * @return none * * <b>Coefficient and State Ordering:</b> * * \par * The coefficients are stored in the array <code>pCoeffs</code> in the following order: * <pre> * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...} * </pre> * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage, * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage, * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values. * * \par * The <code>pState</code> points to state variables array and size of each state variable is 1.63 format. * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>. * The state variables are arranged in the state array as: * <pre> * {x[n-1], x[n-2], y[n-1], y[n-2]} * </pre> * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. * The state array has a total length of <code>4*numStages</code> values. * The state variables are updated after each block of data is processed; the coefficients are untouched. */ void arm_biquad_cas_df1_32x64_init_q31( arm_biquad_cas_df1_32x64_ins_q31 * S, uint8_t numStages, q31_t * pCoeffs, q63_t * pState, uint8_t postShift) { /* Assign filter stages */ S->numStages = numStages; /* Assign postShift to be applied to the output */ S->postShift = postShift; /* Assign coefficient pointer */ S->pCoeffs = pCoeffs; /* Clear state buffer and size is always 4 * numStages */ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t)); /* Assign state pointer */ S->pState = pState; } /** * @} end of BiquadCascadeDF1_32x64 group */