V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.
Dependents: MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more
core_sc300.h@0:3d9c67d97d6f, 2014-07-28 (annotated)
- Committer:
- emh203
- Date:
- Mon Jul 28 15:03:15 2014 +0000
- Revision:
- 0:3d9c67d97d6f
1st working commit. Had to remove arm_bitreversal2.s arm_cfft_f32.c and arm_rfft_fast_f32.c. The .s will not assemble. For now I removed these functions so we could at least have a library for the other functions.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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emh203 | 0:3d9c67d97d6f | 1 | /**************************************************************************//** |
emh203 | 0:3d9c67d97d6f | 2 | * @file core_sc300.h |
emh203 | 0:3d9c67d97d6f | 3 | * @brief CMSIS SC300 Core Peripheral Access Layer Header File |
emh203 | 0:3d9c67d97d6f | 4 | * @version V3.30 |
emh203 | 0:3d9c67d97d6f | 5 | * @date 06. May 2014 |
emh203 | 0:3d9c67d97d6f | 6 | * |
emh203 | 0:3d9c67d97d6f | 7 | * @note |
emh203 | 0:3d9c67d97d6f | 8 | * |
emh203 | 0:3d9c67d97d6f | 9 | ******************************************************************************/ |
emh203 | 0:3d9c67d97d6f | 10 | /* Copyright (c) 2009 - 2014 ARM LIMITED |
emh203 | 0:3d9c67d97d6f | 11 | |
emh203 | 0:3d9c67d97d6f | 12 | All rights reserved. |
emh203 | 0:3d9c67d97d6f | 13 | Redistribution and use in source and binary forms, with or without |
emh203 | 0:3d9c67d97d6f | 14 | modification, are permitted provided that the following conditions are met: |
emh203 | 0:3d9c67d97d6f | 15 | - Redistributions of source code must retain the above copyright |
emh203 | 0:3d9c67d97d6f | 16 | notice, this list of conditions and the following disclaimer. |
emh203 | 0:3d9c67d97d6f | 17 | - Redistributions in binary form must reproduce the above copyright |
emh203 | 0:3d9c67d97d6f | 18 | notice, this list of conditions and the following disclaimer in the |
emh203 | 0:3d9c67d97d6f | 19 | documentation and/or other materials provided with the distribution. |
emh203 | 0:3d9c67d97d6f | 20 | - Neither the name of ARM nor the names of its contributors may be used |
emh203 | 0:3d9c67d97d6f | 21 | to endorse or promote products derived from this software without |
emh203 | 0:3d9c67d97d6f | 22 | specific prior written permission. |
emh203 | 0:3d9c67d97d6f | 23 | * |
emh203 | 0:3d9c67d97d6f | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
emh203 | 0:3d9c67d97d6f | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
emh203 | 0:3d9c67d97d6f | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
emh203 | 0:3d9c67d97d6f | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
emh203 | 0:3d9c67d97d6f | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
emh203 | 0:3d9c67d97d6f | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
emh203 | 0:3d9c67d97d6f | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
emh203 | 0:3d9c67d97d6f | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
emh203 | 0:3d9c67d97d6f | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
emh203 | 0:3d9c67d97d6f | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
emh203 | 0:3d9c67d97d6f | 34 | POSSIBILITY OF SUCH DAMAGE. |
emh203 | 0:3d9c67d97d6f | 35 | ---------------------------------------------------------------------------*/ |
emh203 | 0:3d9c67d97d6f | 36 | |
emh203 | 0:3d9c67d97d6f | 37 | |
emh203 | 0:3d9c67d97d6f | 38 | #if defined ( __ICCARM__ ) |
emh203 | 0:3d9c67d97d6f | 39 | #pragma system_include /* treat file as system include file for MISRA check */ |
emh203 | 0:3d9c67d97d6f | 40 | #endif |
emh203 | 0:3d9c67d97d6f | 41 | |
emh203 | 0:3d9c67d97d6f | 42 | #ifndef __CORE_SC300_H_GENERIC |
emh203 | 0:3d9c67d97d6f | 43 | #define __CORE_SC300_H_GENERIC |
emh203 | 0:3d9c67d97d6f | 44 | |
emh203 | 0:3d9c67d97d6f | 45 | #ifdef __cplusplus |
emh203 | 0:3d9c67d97d6f | 46 | extern "C" { |
emh203 | 0:3d9c67d97d6f | 47 | #endif |
emh203 | 0:3d9c67d97d6f | 48 | |
emh203 | 0:3d9c67d97d6f | 49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
emh203 | 0:3d9c67d97d6f | 50 | CMSIS violates the following MISRA-C:2004 rules: |
emh203 | 0:3d9c67d97d6f | 51 | |
emh203 | 0:3d9c67d97d6f | 52 | \li Required Rule 8.5, object/function definition in header file.<br> |
emh203 | 0:3d9c67d97d6f | 53 | Function definitions in header files are used to allow 'inlining'. |
emh203 | 0:3d9c67d97d6f | 54 | |
emh203 | 0:3d9c67d97d6f | 55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
emh203 | 0:3d9c67d97d6f | 56 | Unions are used for effective representation of core registers. |
emh203 | 0:3d9c67d97d6f | 57 | |
emh203 | 0:3d9c67d97d6f | 58 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
emh203 | 0:3d9c67d97d6f | 59 | Function-like macros are used to allow more efficient code. |
emh203 | 0:3d9c67d97d6f | 60 | */ |
emh203 | 0:3d9c67d97d6f | 61 | |
emh203 | 0:3d9c67d97d6f | 62 | |
emh203 | 0:3d9c67d97d6f | 63 | /******************************************************************************* |
emh203 | 0:3d9c67d97d6f | 64 | * CMSIS definitions |
emh203 | 0:3d9c67d97d6f | 65 | ******************************************************************************/ |
emh203 | 0:3d9c67d97d6f | 66 | /** \ingroup SC3000 |
emh203 | 0:3d9c67d97d6f | 67 | @{ |
emh203 | 0:3d9c67d97d6f | 68 | */ |
emh203 | 0:3d9c67d97d6f | 69 | |
emh203 | 0:3d9c67d97d6f | 70 | /* CMSIS SC300 definitions */ |
emh203 | 0:3d9c67d97d6f | 71 | #define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ |
emh203 | 0:3d9c67d97d6f | 72 | #define __SC300_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ |
emh203 | 0:3d9c67d97d6f | 73 | #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ |
emh203 | 0:3d9c67d97d6f | 74 | __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
emh203 | 0:3d9c67d97d6f | 75 | |
emh203 | 0:3d9c67d97d6f | 76 | #define __CORTEX_SC (300) /*!< Cortex secure core */ |
emh203 | 0:3d9c67d97d6f | 77 | |
emh203 | 0:3d9c67d97d6f | 78 | |
emh203 | 0:3d9c67d97d6f | 79 | #if defined ( __CC_ARM ) |
emh203 | 0:3d9c67d97d6f | 80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
emh203 | 0:3d9c67d97d6f | 81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
emh203 | 0:3d9c67d97d6f | 82 | #define __STATIC_INLINE static __inline |
emh203 | 0:3d9c67d97d6f | 83 | |
emh203 | 0:3d9c67d97d6f | 84 | #elif defined ( __GNUC__ ) |
emh203 | 0:3d9c67d97d6f | 85 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
emh203 | 0:3d9c67d97d6f | 86 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
emh203 | 0:3d9c67d97d6f | 87 | #define __STATIC_INLINE static inline |
emh203 | 0:3d9c67d97d6f | 88 | |
emh203 | 0:3d9c67d97d6f | 89 | #elif defined ( __ICCARM__ ) |
emh203 | 0:3d9c67d97d6f | 90 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
emh203 | 0:3d9c67d97d6f | 91 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
emh203 | 0:3d9c67d97d6f | 92 | #define __STATIC_INLINE static inline |
emh203 | 0:3d9c67d97d6f | 93 | |
emh203 | 0:3d9c67d97d6f | 94 | #elif defined ( __TMS470__ ) |
emh203 | 0:3d9c67d97d6f | 95 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
emh203 | 0:3d9c67d97d6f | 96 | #define __STATIC_INLINE static inline |
emh203 | 0:3d9c67d97d6f | 97 | |
emh203 | 0:3d9c67d97d6f | 98 | #elif defined ( __TASKING__ ) |
emh203 | 0:3d9c67d97d6f | 99 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
emh203 | 0:3d9c67d97d6f | 100 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
emh203 | 0:3d9c67d97d6f | 101 | #define __STATIC_INLINE static inline |
emh203 | 0:3d9c67d97d6f | 102 | |
emh203 | 0:3d9c67d97d6f | 103 | #elif defined ( __CSMC__ ) /* Cosmic */ |
emh203 | 0:3d9c67d97d6f | 104 | #define __packed |
emh203 | 0:3d9c67d97d6f | 105 | #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
emh203 | 0:3d9c67d97d6f | 106 | #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ |
emh203 | 0:3d9c67d97d6f | 107 | #define __STATIC_INLINE static inline |
emh203 | 0:3d9c67d97d6f | 108 | |
emh203 | 0:3d9c67d97d6f | 109 | #endif |
emh203 | 0:3d9c67d97d6f | 110 | |
emh203 | 0:3d9c67d97d6f | 111 | /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all |
emh203 | 0:3d9c67d97d6f | 112 | */ |
emh203 | 0:3d9c67d97d6f | 113 | #define __FPU_USED 0 |
emh203 | 0:3d9c67d97d6f | 114 | |
emh203 | 0:3d9c67d97d6f | 115 | #if defined ( __CC_ARM ) |
emh203 | 0:3d9c67d97d6f | 116 | #if defined __TARGET_FPU_VFP |
emh203 | 0:3d9c67d97d6f | 117 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emh203 | 0:3d9c67d97d6f | 118 | #endif |
emh203 | 0:3d9c67d97d6f | 119 | |
emh203 | 0:3d9c67d97d6f | 120 | #elif defined ( __GNUC__ ) |
emh203 | 0:3d9c67d97d6f | 121 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
emh203 | 0:3d9c67d97d6f | 122 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emh203 | 0:3d9c67d97d6f | 123 | #endif |
emh203 | 0:3d9c67d97d6f | 124 | |
emh203 | 0:3d9c67d97d6f | 125 | #elif defined ( __ICCARM__ ) |
emh203 | 0:3d9c67d97d6f | 126 | #if defined __ARMVFP__ |
emh203 | 0:3d9c67d97d6f | 127 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emh203 | 0:3d9c67d97d6f | 128 | #endif |
emh203 | 0:3d9c67d97d6f | 129 | |
emh203 | 0:3d9c67d97d6f | 130 | #elif defined ( __TMS470__ ) |
emh203 | 0:3d9c67d97d6f | 131 | #if defined __TI__VFP_SUPPORT____ |
emh203 | 0:3d9c67d97d6f | 132 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emh203 | 0:3d9c67d97d6f | 133 | #endif |
emh203 | 0:3d9c67d97d6f | 134 | |
emh203 | 0:3d9c67d97d6f | 135 | #elif defined ( __TASKING__ ) |
emh203 | 0:3d9c67d97d6f | 136 | #if defined __FPU_VFP__ |
emh203 | 0:3d9c67d97d6f | 137 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emh203 | 0:3d9c67d97d6f | 138 | #endif |
emh203 | 0:3d9c67d97d6f | 139 | |
emh203 | 0:3d9c67d97d6f | 140 | #elif defined ( __CSMC__ ) /* Cosmic */ |
emh203 | 0:3d9c67d97d6f | 141 | #if ( __CSMC__ & 0x400) // FPU present for parser |
emh203 | 0:3d9c67d97d6f | 142 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emh203 | 0:3d9c67d97d6f | 143 | #endif |
emh203 | 0:3d9c67d97d6f | 144 | #endif |
emh203 | 0:3d9c67d97d6f | 145 | |
emh203 | 0:3d9c67d97d6f | 146 | #include <stdint.h> /* standard types definitions */ |
emh203 | 0:3d9c67d97d6f | 147 | #include <core_cmInstr.h> /* Core Instruction Access */ |
emh203 | 0:3d9c67d97d6f | 148 | #include <core_cmFunc.h> /* Core Function Access */ |
emh203 | 0:3d9c67d97d6f | 149 | |
emh203 | 0:3d9c67d97d6f | 150 | #endif /* __CORE_SC300_H_GENERIC */ |
emh203 | 0:3d9c67d97d6f | 151 | |
emh203 | 0:3d9c67d97d6f | 152 | #ifndef __CMSIS_GENERIC |
emh203 | 0:3d9c67d97d6f | 153 | |
emh203 | 0:3d9c67d97d6f | 154 | #ifndef __CORE_SC300_H_DEPENDANT |
emh203 | 0:3d9c67d97d6f | 155 | #define __CORE_SC300_H_DEPENDANT |
emh203 | 0:3d9c67d97d6f | 156 | |
emh203 | 0:3d9c67d97d6f | 157 | /* check device defines and use defaults */ |
emh203 | 0:3d9c67d97d6f | 158 | #if defined __CHECK_DEVICE_DEFINES |
emh203 | 0:3d9c67d97d6f | 159 | #ifndef __SC300_REV |
emh203 | 0:3d9c67d97d6f | 160 | #define __SC300_REV 0x0000 |
emh203 | 0:3d9c67d97d6f | 161 | #warning "__SC300_REV not defined in device header file; using default!" |
emh203 | 0:3d9c67d97d6f | 162 | #endif |
emh203 | 0:3d9c67d97d6f | 163 | |
emh203 | 0:3d9c67d97d6f | 164 | #ifndef __MPU_PRESENT |
emh203 | 0:3d9c67d97d6f | 165 | #define __MPU_PRESENT 0 |
emh203 | 0:3d9c67d97d6f | 166 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
emh203 | 0:3d9c67d97d6f | 167 | #endif |
emh203 | 0:3d9c67d97d6f | 168 | |
emh203 | 0:3d9c67d97d6f | 169 | #ifndef __NVIC_PRIO_BITS |
emh203 | 0:3d9c67d97d6f | 170 | #define __NVIC_PRIO_BITS 4 |
emh203 | 0:3d9c67d97d6f | 171 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
emh203 | 0:3d9c67d97d6f | 172 | #endif |
emh203 | 0:3d9c67d97d6f | 173 | |
emh203 | 0:3d9c67d97d6f | 174 | #ifndef __Vendor_SysTickConfig |
emh203 | 0:3d9c67d97d6f | 175 | #define __Vendor_SysTickConfig 0 |
emh203 | 0:3d9c67d97d6f | 176 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
emh203 | 0:3d9c67d97d6f | 177 | #endif |
emh203 | 0:3d9c67d97d6f | 178 | #endif |
emh203 | 0:3d9c67d97d6f | 179 | |
emh203 | 0:3d9c67d97d6f | 180 | /* IO definitions (access restrictions to peripheral registers) */ |
emh203 | 0:3d9c67d97d6f | 181 | /** |
emh203 | 0:3d9c67d97d6f | 182 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
emh203 | 0:3d9c67d97d6f | 183 | |
emh203 | 0:3d9c67d97d6f | 184 | <strong>IO Type Qualifiers</strong> are used |
emh203 | 0:3d9c67d97d6f | 185 | \li to specify the access to peripheral variables. |
emh203 | 0:3d9c67d97d6f | 186 | \li for automatic generation of peripheral register debug information. |
emh203 | 0:3d9c67d97d6f | 187 | */ |
emh203 | 0:3d9c67d97d6f | 188 | #ifdef __cplusplus |
emh203 | 0:3d9c67d97d6f | 189 | #define __I volatile /*!< Defines 'read only' permissions */ |
emh203 | 0:3d9c67d97d6f | 190 | #else |
emh203 | 0:3d9c67d97d6f | 191 | #define __I volatile const /*!< Defines 'read only' permissions */ |
emh203 | 0:3d9c67d97d6f | 192 | #endif |
emh203 | 0:3d9c67d97d6f | 193 | #define __O volatile /*!< Defines 'write only' permissions */ |
emh203 | 0:3d9c67d97d6f | 194 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
emh203 | 0:3d9c67d97d6f | 195 | |
emh203 | 0:3d9c67d97d6f | 196 | /*@} end of group SC300 */ |
emh203 | 0:3d9c67d97d6f | 197 | |
emh203 | 0:3d9c67d97d6f | 198 | |
emh203 | 0:3d9c67d97d6f | 199 | |
emh203 | 0:3d9c67d97d6f | 200 | /******************************************************************************* |
emh203 | 0:3d9c67d97d6f | 201 | * Register Abstraction |
emh203 | 0:3d9c67d97d6f | 202 | Core Register contain: |
emh203 | 0:3d9c67d97d6f | 203 | - Core Register |
emh203 | 0:3d9c67d97d6f | 204 | - Core NVIC Register |
emh203 | 0:3d9c67d97d6f | 205 | - Core SCB Register |
emh203 | 0:3d9c67d97d6f | 206 | - Core SysTick Register |
emh203 | 0:3d9c67d97d6f | 207 | - Core Debug Register |
emh203 | 0:3d9c67d97d6f | 208 | - Core MPU Register |
emh203 | 0:3d9c67d97d6f | 209 | ******************************************************************************/ |
emh203 | 0:3d9c67d97d6f | 210 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
emh203 | 0:3d9c67d97d6f | 211 | \brief Type definitions and defines for Cortex-M processor based devices. |
emh203 | 0:3d9c67d97d6f | 212 | */ |
emh203 | 0:3d9c67d97d6f | 213 | |
emh203 | 0:3d9c67d97d6f | 214 | /** \ingroup CMSIS_core_register |
emh203 | 0:3d9c67d97d6f | 215 | \defgroup CMSIS_CORE Status and Control Registers |
emh203 | 0:3d9c67d97d6f | 216 | \brief Core Register type definitions. |
emh203 | 0:3d9c67d97d6f | 217 | @{ |
emh203 | 0:3d9c67d97d6f | 218 | */ |
emh203 | 0:3d9c67d97d6f | 219 | |
emh203 | 0:3d9c67d97d6f | 220 | /** \brief Union type to access the Application Program Status Register (APSR). |
emh203 | 0:3d9c67d97d6f | 221 | */ |
emh203 | 0:3d9c67d97d6f | 222 | typedef union |
emh203 | 0:3d9c67d97d6f | 223 | { |
emh203 | 0:3d9c67d97d6f | 224 | struct |
emh203 | 0:3d9c67d97d6f | 225 | { |
emh203 | 0:3d9c67d97d6f | 226 | #if (__CORTEX_M != 0x04) |
emh203 | 0:3d9c67d97d6f | 227 | uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ |
emh203 | 0:3d9c67d97d6f | 228 | #else |
emh203 | 0:3d9c67d97d6f | 229 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ |
emh203 | 0:3d9c67d97d6f | 230 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
emh203 | 0:3d9c67d97d6f | 231 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ |
emh203 | 0:3d9c67d97d6f | 232 | #endif |
emh203 | 0:3d9c67d97d6f | 233 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
emh203 | 0:3d9c67d97d6f | 234 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
emh203 | 0:3d9c67d97d6f | 235 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
emh203 | 0:3d9c67d97d6f | 236 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
emh203 | 0:3d9c67d97d6f | 237 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
emh203 | 0:3d9c67d97d6f | 238 | } b; /*!< Structure used for bit access */ |
emh203 | 0:3d9c67d97d6f | 239 | uint32_t w; /*!< Type used for word access */ |
emh203 | 0:3d9c67d97d6f | 240 | } APSR_Type; |
emh203 | 0:3d9c67d97d6f | 241 | |
emh203 | 0:3d9c67d97d6f | 242 | |
emh203 | 0:3d9c67d97d6f | 243 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
emh203 | 0:3d9c67d97d6f | 244 | */ |
emh203 | 0:3d9c67d97d6f | 245 | typedef union |
emh203 | 0:3d9c67d97d6f | 246 | { |
emh203 | 0:3d9c67d97d6f | 247 | struct |
emh203 | 0:3d9c67d97d6f | 248 | { |
emh203 | 0:3d9c67d97d6f | 249 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
emh203 | 0:3d9c67d97d6f | 250 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
emh203 | 0:3d9c67d97d6f | 251 | } b; /*!< Structure used for bit access */ |
emh203 | 0:3d9c67d97d6f | 252 | uint32_t w; /*!< Type used for word access */ |
emh203 | 0:3d9c67d97d6f | 253 | } IPSR_Type; |
emh203 | 0:3d9c67d97d6f | 254 | |
emh203 | 0:3d9c67d97d6f | 255 | |
emh203 | 0:3d9c67d97d6f | 256 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
emh203 | 0:3d9c67d97d6f | 257 | */ |
emh203 | 0:3d9c67d97d6f | 258 | typedef union |
emh203 | 0:3d9c67d97d6f | 259 | { |
emh203 | 0:3d9c67d97d6f | 260 | struct |
emh203 | 0:3d9c67d97d6f | 261 | { |
emh203 | 0:3d9c67d97d6f | 262 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
emh203 | 0:3d9c67d97d6f | 263 | #if (__CORTEX_M != 0x04) |
emh203 | 0:3d9c67d97d6f | 264 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
emh203 | 0:3d9c67d97d6f | 265 | #else |
emh203 | 0:3d9c67d97d6f | 266 | uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ |
emh203 | 0:3d9c67d97d6f | 267 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
emh203 | 0:3d9c67d97d6f | 268 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ |
emh203 | 0:3d9c67d97d6f | 269 | #endif |
emh203 | 0:3d9c67d97d6f | 270 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
emh203 | 0:3d9c67d97d6f | 271 | uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ |
emh203 | 0:3d9c67d97d6f | 272 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
emh203 | 0:3d9c67d97d6f | 273 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
emh203 | 0:3d9c67d97d6f | 274 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
emh203 | 0:3d9c67d97d6f | 275 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
emh203 | 0:3d9c67d97d6f | 276 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
emh203 | 0:3d9c67d97d6f | 277 | } b; /*!< Structure used for bit access */ |
emh203 | 0:3d9c67d97d6f | 278 | uint32_t w; /*!< Type used for word access */ |
emh203 | 0:3d9c67d97d6f | 279 | } xPSR_Type; |
emh203 | 0:3d9c67d97d6f | 280 | |
emh203 | 0:3d9c67d97d6f | 281 | |
emh203 | 0:3d9c67d97d6f | 282 | /** \brief Union type to access the Control Registers (CONTROL). |
emh203 | 0:3d9c67d97d6f | 283 | */ |
emh203 | 0:3d9c67d97d6f | 284 | typedef union |
emh203 | 0:3d9c67d97d6f | 285 | { |
emh203 | 0:3d9c67d97d6f | 286 | struct |
emh203 | 0:3d9c67d97d6f | 287 | { |
emh203 | 0:3d9c67d97d6f | 288 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
emh203 | 0:3d9c67d97d6f | 289 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
emh203 | 0:3d9c67d97d6f | 290 | uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ |
emh203 | 0:3d9c67d97d6f | 291 | uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ |
emh203 | 0:3d9c67d97d6f | 292 | } b; /*!< Structure used for bit access */ |
emh203 | 0:3d9c67d97d6f | 293 | uint32_t w; /*!< Type used for word access */ |
emh203 | 0:3d9c67d97d6f | 294 | } CONTROL_Type; |
emh203 | 0:3d9c67d97d6f | 295 | |
emh203 | 0:3d9c67d97d6f | 296 | /*@} end of group CMSIS_CORE */ |
emh203 | 0:3d9c67d97d6f | 297 | |
emh203 | 0:3d9c67d97d6f | 298 | |
emh203 | 0:3d9c67d97d6f | 299 | /** \ingroup CMSIS_core_register |
emh203 | 0:3d9c67d97d6f | 300 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
emh203 | 0:3d9c67d97d6f | 301 | \brief Type definitions for the NVIC Registers |
emh203 | 0:3d9c67d97d6f | 302 | @{ |
emh203 | 0:3d9c67d97d6f | 303 | */ |
emh203 | 0:3d9c67d97d6f | 304 | |
emh203 | 0:3d9c67d97d6f | 305 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
emh203 | 0:3d9c67d97d6f | 306 | */ |
emh203 | 0:3d9c67d97d6f | 307 | typedef struct |
emh203 | 0:3d9c67d97d6f | 308 | { |
emh203 | 0:3d9c67d97d6f | 309 | __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
emh203 | 0:3d9c67d97d6f | 310 | uint32_t RESERVED0[24]; |
emh203 | 0:3d9c67d97d6f | 311 | __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
emh203 | 0:3d9c67d97d6f | 312 | uint32_t RSERVED1[24]; |
emh203 | 0:3d9c67d97d6f | 313 | __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
emh203 | 0:3d9c67d97d6f | 314 | uint32_t RESERVED2[24]; |
emh203 | 0:3d9c67d97d6f | 315 | __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
emh203 | 0:3d9c67d97d6f | 316 | uint32_t RESERVED3[24]; |
emh203 | 0:3d9c67d97d6f | 317 | __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ |
emh203 | 0:3d9c67d97d6f | 318 | uint32_t RESERVED4[56]; |
emh203 | 0:3d9c67d97d6f | 319 | __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ |
emh203 | 0:3d9c67d97d6f | 320 | uint32_t RESERVED5[644]; |
emh203 | 0:3d9c67d97d6f | 321 | __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ |
emh203 | 0:3d9c67d97d6f | 322 | } NVIC_Type; |
emh203 | 0:3d9c67d97d6f | 323 | |
emh203 | 0:3d9c67d97d6f | 324 | /* Software Triggered Interrupt Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 325 | #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ |
emh203 | 0:3d9c67d97d6f | 326 | #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ |
emh203 | 0:3d9c67d97d6f | 327 | |
emh203 | 0:3d9c67d97d6f | 328 | /*@} end of group CMSIS_NVIC */ |
emh203 | 0:3d9c67d97d6f | 329 | |
emh203 | 0:3d9c67d97d6f | 330 | |
emh203 | 0:3d9c67d97d6f | 331 | /** \ingroup CMSIS_core_register |
emh203 | 0:3d9c67d97d6f | 332 | \defgroup CMSIS_SCB System Control Block (SCB) |
emh203 | 0:3d9c67d97d6f | 333 | \brief Type definitions for the System Control Block Registers |
emh203 | 0:3d9c67d97d6f | 334 | @{ |
emh203 | 0:3d9c67d97d6f | 335 | */ |
emh203 | 0:3d9c67d97d6f | 336 | |
emh203 | 0:3d9c67d97d6f | 337 | /** \brief Structure type to access the System Control Block (SCB). |
emh203 | 0:3d9c67d97d6f | 338 | */ |
emh203 | 0:3d9c67d97d6f | 339 | typedef struct |
emh203 | 0:3d9c67d97d6f | 340 | { |
emh203 | 0:3d9c67d97d6f | 341 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
emh203 | 0:3d9c67d97d6f | 342 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
emh203 | 0:3d9c67d97d6f | 343 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
emh203 | 0:3d9c67d97d6f | 344 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
emh203 | 0:3d9c67d97d6f | 345 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
emh203 | 0:3d9c67d97d6f | 346 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
emh203 | 0:3d9c67d97d6f | 347 | __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
emh203 | 0:3d9c67d97d6f | 348 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
emh203 | 0:3d9c67d97d6f | 349 | __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ |
emh203 | 0:3d9c67d97d6f | 350 | __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ |
emh203 | 0:3d9c67d97d6f | 351 | __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ |
emh203 | 0:3d9c67d97d6f | 352 | __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ |
emh203 | 0:3d9c67d97d6f | 353 | __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ |
emh203 | 0:3d9c67d97d6f | 354 | __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ |
emh203 | 0:3d9c67d97d6f | 355 | __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ |
emh203 | 0:3d9c67d97d6f | 356 | __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ |
emh203 | 0:3d9c67d97d6f | 357 | __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ |
emh203 | 0:3d9c67d97d6f | 358 | __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ |
emh203 | 0:3d9c67d97d6f | 359 | __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ |
emh203 | 0:3d9c67d97d6f | 360 | uint32_t RESERVED0[5]; |
emh203 | 0:3d9c67d97d6f | 361 | __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ |
emh203 | 0:3d9c67d97d6f | 362 | } SCB_Type; |
emh203 | 0:3d9c67d97d6f | 363 | |
emh203 | 0:3d9c67d97d6f | 364 | /* SCB CPUID Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 365 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
emh203 | 0:3d9c67d97d6f | 366 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
emh203 | 0:3d9c67d97d6f | 367 | |
emh203 | 0:3d9c67d97d6f | 368 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
emh203 | 0:3d9c67d97d6f | 369 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
emh203 | 0:3d9c67d97d6f | 370 | |
emh203 | 0:3d9c67d97d6f | 371 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
emh203 | 0:3d9c67d97d6f | 372 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
emh203 | 0:3d9c67d97d6f | 373 | |
emh203 | 0:3d9c67d97d6f | 374 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
emh203 | 0:3d9c67d97d6f | 375 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
emh203 | 0:3d9c67d97d6f | 376 | |
emh203 | 0:3d9c67d97d6f | 377 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
emh203 | 0:3d9c67d97d6f | 378 | #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ |
emh203 | 0:3d9c67d97d6f | 379 | |
emh203 | 0:3d9c67d97d6f | 380 | /* SCB Interrupt Control State Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 381 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
emh203 | 0:3d9c67d97d6f | 382 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
emh203 | 0:3d9c67d97d6f | 383 | |
emh203 | 0:3d9c67d97d6f | 384 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
emh203 | 0:3d9c67d97d6f | 385 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
emh203 | 0:3d9c67d97d6f | 386 | |
emh203 | 0:3d9c67d97d6f | 387 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
emh203 | 0:3d9c67d97d6f | 388 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
emh203 | 0:3d9c67d97d6f | 389 | |
emh203 | 0:3d9c67d97d6f | 390 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
emh203 | 0:3d9c67d97d6f | 391 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
emh203 | 0:3d9c67d97d6f | 392 | |
emh203 | 0:3d9c67d97d6f | 393 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
emh203 | 0:3d9c67d97d6f | 394 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
emh203 | 0:3d9c67d97d6f | 395 | |
emh203 | 0:3d9c67d97d6f | 396 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
emh203 | 0:3d9c67d97d6f | 397 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
emh203 | 0:3d9c67d97d6f | 398 | |
emh203 | 0:3d9c67d97d6f | 399 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
emh203 | 0:3d9c67d97d6f | 400 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
emh203 | 0:3d9c67d97d6f | 401 | |
emh203 | 0:3d9c67d97d6f | 402 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
emh203 | 0:3d9c67d97d6f | 403 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
emh203 | 0:3d9c67d97d6f | 404 | |
emh203 | 0:3d9c67d97d6f | 405 | #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ |
emh203 | 0:3d9c67d97d6f | 406 | #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
emh203 | 0:3d9c67d97d6f | 407 | |
emh203 | 0:3d9c67d97d6f | 408 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
emh203 | 0:3d9c67d97d6f | 409 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ |
emh203 | 0:3d9c67d97d6f | 410 | |
emh203 | 0:3d9c67d97d6f | 411 | /* SCB Vector Table Offset Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 412 | #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ |
emh203 | 0:3d9c67d97d6f | 413 | #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ |
emh203 | 0:3d9c67d97d6f | 414 | |
emh203 | 0:3d9c67d97d6f | 415 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
emh203 | 0:3d9c67d97d6f | 416 | #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
emh203 | 0:3d9c67d97d6f | 417 | |
emh203 | 0:3d9c67d97d6f | 418 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 419 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
emh203 | 0:3d9c67d97d6f | 420 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
emh203 | 0:3d9c67d97d6f | 421 | |
emh203 | 0:3d9c67d97d6f | 422 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
emh203 | 0:3d9c67d97d6f | 423 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
emh203 | 0:3d9c67d97d6f | 424 | |
emh203 | 0:3d9c67d97d6f | 425 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
emh203 | 0:3d9c67d97d6f | 426 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
emh203 | 0:3d9c67d97d6f | 427 | |
emh203 | 0:3d9c67d97d6f | 428 | #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ |
emh203 | 0:3d9c67d97d6f | 429 | #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ |
emh203 | 0:3d9c67d97d6f | 430 | |
emh203 | 0:3d9c67d97d6f | 431 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
emh203 | 0:3d9c67d97d6f | 432 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
emh203 | 0:3d9c67d97d6f | 433 | |
emh203 | 0:3d9c67d97d6f | 434 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
emh203 | 0:3d9c67d97d6f | 435 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
emh203 | 0:3d9c67d97d6f | 436 | |
emh203 | 0:3d9c67d97d6f | 437 | #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ |
emh203 | 0:3d9c67d97d6f | 438 | #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ |
emh203 | 0:3d9c67d97d6f | 439 | |
emh203 | 0:3d9c67d97d6f | 440 | /* SCB System Control Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 441 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
emh203 | 0:3d9c67d97d6f | 442 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
emh203 | 0:3d9c67d97d6f | 443 | |
emh203 | 0:3d9c67d97d6f | 444 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
emh203 | 0:3d9c67d97d6f | 445 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
emh203 | 0:3d9c67d97d6f | 446 | |
emh203 | 0:3d9c67d97d6f | 447 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
emh203 | 0:3d9c67d97d6f | 448 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
emh203 | 0:3d9c67d97d6f | 449 | |
emh203 | 0:3d9c67d97d6f | 450 | /* SCB Configuration Control Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 451 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
emh203 | 0:3d9c67d97d6f | 452 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
emh203 | 0:3d9c67d97d6f | 453 | |
emh203 | 0:3d9c67d97d6f | 454 | #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ |
emh203 | 0:3d9c67d97d6f | 455 | #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
emh203 | 0:3d9c67d97d6f | 456 | |
emh203 | 0:3d9c67d97d6f | 457 | #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ |
emh203 | 0:3d9c67d97d6f | 458 | #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
emh203 | 0:3d9c67d97d6f | 459 | |
emh203 | 0:3d9c67d97d6f | 460 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
emh203 | 0:3d9c67d97d6f | 461 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
emh203 | 0:3d9c67d97d6f | 462 | |
emh203 | 0:3d9c67d97d6f | 463 | #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ |
emh203 | 0:3d9c67d97d6f | 464 | #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
emh203 | 0:3d9c67d97d6f | 465 | |
emh203 | 0:3d9c67d97d6f | 466 | #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ |
emh203 | 0:3d9c67d97d6f | 467 | #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ |
emh203 | 0:3d9c67d97d6f | 468 | |
emh203 | 0:3d9c67d97d6f | 469 | /* SCB System Handler Control and State Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 470 | #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ |
emh203 | 0:3d9c67d97d6f | 471 | #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ |
emh203 | 0:3d9c67d97d6f | 472 | |
emh203 | 0:3d9c67d97d6f | 473 | #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ |
emh203 | 0:3d9c67d97d6f | 474 | #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ |
emh203 | 0:3d9c67d97d6f | 475 | |
emh203 | 0:3d9c67d97d6f | 476 | #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ |
emh203 | 0:3d9c67d97d6f | 477 | #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ |
emh203 | 0:3d9c67d97d6f | 478 | |
emh203 | 0:3d9c67d97d6f | 479 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
emh203 | 0:3d9c67d97d6f | 480 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
emh203 | 0:3d9c67d97d6f | 481 | |
emh203 | 0:3d9c67d97d6f | 482 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ |
emh203 | 0:3d9c67d97d6f | 483 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ |
emh203 | 0:3d9c67d97d6f | 484 | |
emh203 | 0:3d9c67d97d6f | 485 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ |
emh203 | 0:3d9c67d97d6f | 486 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ |
emh203 | 0:3d9c67d97d6f | 487 | |
emh203 | 0:3d9c67d97d6f | 488 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ |
emh203 | 0:3d9c67d97d6f | 489 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ |
emh203 | 0:3d9c67d97d6f | 490 | |
emh203 | 0:3d9c67d97d6f | 491 | #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ |
emh203 | 0:3d9c67d97d6f | 492 | #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
emh203 | 0:3d9c67d97d6f | 493 | |
emh203 | 0:3d9c67d97d6f | 494 | #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ |
emh203 | 0:3d9c67d97d6f | 495 | #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
emh203 | 0:3d9c67d97d6f | 496 | |
emh203 | 0:3d9c67d97d6f | 497 | #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ |
emh203 | 0:3d9c67d97d6f | 498 | #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ |
emh203 | 0:3d9c67d97d6f | 499 | |
emh203 | 0:3d9c67d97d6f | 500 | #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ |
emh203 | 0:3d9c67d97d6f | 501 | #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
emh203 | 0:3d9c67d97d6f | 502 | |
emh203 | 0:3d9c67d97d6f | 503 | #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ |
emh203 | 0:3d9c67d97d6f | 504 | #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ |
emh203 | 0:3d9c67d97d6f | 505 | |
emh203 | 0:3d9c67d97d6f | 506 | #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ |
emh203 | 0:3d9c67d97d6f | 507 | #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ |
emh203 | 0:3d9c67d97d6f | 508 | |
emh203 | 0:3d9c67d97d6f | 509 | #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ |
emh203 | 0:3d9c67d97d6f | 510 | #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ |
emh203 | 0:3d9c67d97d6f | 511 | |
emh203 | 0:3d9c67d97d6f | 512 | /* SCB Configurable Fault Status Registers Definitions */ |
emh203 | 0:3d9c67d97d6f | 513 | #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ |
emh203 | 0:3d9c67d97d6f | 514 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ |
emh203 | 0:3d9c67d97d6f | 515 | |
emh203 | 0:3d9c67d97d6f | 516 | #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ |
emh203 | 0:3d9c67d97d6f | 517 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ |
emh203 | 0:3d9c67d97d6f | 518 | |
emh203 | 0:3d9c67d97d6f | 519 | #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ |
emh203 | 0:3d9c67d97d6f | 520 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ |
emh203 | 0:3d9c67d97d6f | 521 | |
emh203 | 0:3d9c67d97d6f | 522 | /* SCB Hard Fault Status Registers Definitions */ |
emh203 | 0:3d9c67d97d6f | 523 | #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ |
emh203 | 0:3d9c67d97d6f | 524 | #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ |
emh203 | 0:3d9c67d97d6f | 525 | |
emh203 | 0:3d9c67d97d6f | 526 | #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ |
emh203 | 0:3d9c67d97d6f | 527 | #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ |
emh203 | 0:3d9c67d97d6f | 528 | |
emh203 | 0:3d9c67d97d6f | 529 | #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ |
emh203 | 0:3d9c67d97d6f | 530 | #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ |
emh203 | 0:3d9c67d97d6f | 531 | |
emh203 | 0:3d9c67d97d6f | 532 | /* SCB Debug Fault Status Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 533 | #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ |
emh203 | 0:3d9c67d97d6f | 534 | #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ |
emh203 | 0:3d9c67d97d6f | 535 | |
emh203 | 0:3d9c67d97d6f | 536 | #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ |
emh203 | 0:3d9c67d97d6f | 537 | #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ |
emh203 | 0:3d9c67d97d6f | 538 | |
emh203 | 0:3d9c67d97d6f | 539 | #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ |
emh203 | 0:3d9c67d97d6f | 540 | #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ |
emh203 | 0:3d9c67d97d6f | 541 | |
emh203 | 0:3d9c67d97d6f | 542 | #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ |
emh203 | 0:3d9c67d97d6f | 543 | #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ |
emh203 | 0:3d9c67d97d6f | 544 | |
emh203 | 0:3d9c67d97d6f | 545 | #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ |
emh203 | 0:3d9c67d97d6f | 546 | #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ |
emh203 | 0:3d9c67d97d6f | 547 | |
emh203 | 0:3d9c67d97d6f | 548 | /*@} end of group CMSIS_SCB */ |
emh203 | 0:3d9c67d97d6f | 549 | |
emh203 | 0:3d9c67d97d6f | 550 | |
emh203 | 0:3d9c67d97d6f | 551 | /** \ingroup CMSIS_core_register |
emh203 | 0:3d9c67d97d6f | 552 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
emh203 | 0:3d9c67d97d6f | 553 | \brief Type definitions for the System Control and ID Register not in the SCB |
emh203 | 0:3d9c67d97d6f | 554 | @{ |
emh203 | 0:3d9c67d97d6f | 555 | */ |
emh203 | 0:3d9c67d97d6f | 556 | |
emh203 | 0:3d9c67d97d6f | 557 | /** \brief Structure type to access the System Control and ID Register not in the SCB. |
emh203 | 0:3d9c67d97d6f | 558 | */ |
emh203 | 0:3d9c67d97d6f | 559 | typedef struct |
emh203 | 0:3d9c67d97d6f | 560 | { |
emh203 | 0:3d9c67d97d6f | 561 | uint32_t RESERVED0[1]; |
emh203 | 0:3d9c67d97d6f | 562 | __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ |
emh203 | 0:3d9c67d97d6f | 563 | uint32_t RESERVED1[1]; |
emh203 | 0:3d9c67d97d6f | 564 | } SCnSCB_Type; |
emh203 | 0:3d9c67d97d6f | 565 | |
emh203 | 0:3d9c67d97d6f | 566 | /* Interrupt Controller Type Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 567 | #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ |
emh203 | 0:3d9c67d97d6f | 568 | #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ |
emh203 | 0:3d9c67d97d6f | 569 | |
emh203 | 0:3d9c67d97d6f | 570 | /*@} end of group CMSIS_SCnotSCB */ |
emh203 | 0:3d9c67d97d6f | 571 | |
emh203 | 0:3d9c67d97d6f | 572 | |
emh203 | 0:3d9c67d97d6f | 573 | /** \ingroup CMSIS_core_register |
emh203 | 0:3d9c67d97d6f | 574 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
emh203 | 0:3d9c67d97d6f | 575 | \brief Type definitions for the System Timer Registers. |
emh203 | 0:3d9c67d97d6f | 576 | @{ |
emh203 | 0:3d9c67d97d6f | 577 | */ |
emh203 | 0:3d9c67d97d6f | 578 | |
emh203 | 0:3d9c67d97d6f | 579 | /** \brief Structure type to access the System Timer (SysTick). |
emh203 | 0:3d9c67d97d6f | 580 | */ |
emh203 | 0:3d9c67d97d6f | 581 | typedef struct |
emh203 | 0:3d9c67d97d6f | 582 | { |
emh203 | 0:3d9c67d97d6f | 583 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
emh203 | 0:3d9c67d97d6f | 584 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
emh203 | 0:3d9c67d97d6f | 585 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
emh203 | 0:3d9c67d97d6f | 586 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
emh203 | 0:3d9c67d97d6f | 587 | } SysTick_Type; |
emh203 | 0:3d9c67d97d6f | 588 | |
emh203 | 0:3d9c67d97d6f | 589 | /* SysTick Control / Status Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 590 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
emh203 | 0:3d9c67d97d6f | 591 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
emh203 | 0:3d9c67d97d6f | 592 | |
emh203 | 0:3d9c67d97d6f | 593 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
emh203 | 0:3d9c67d97d6f | 594 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
emh203 | 0:3d9c67d97d6f | 595 | |
emh203 | 0:3d9c67d97d6f | 596 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
emh203 | 0:3d9c67d97d6f | 597 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
emh203 | 0:3d9c67d97d6f | 598 | |
emh203 | 0:3d9c67d97d6f | 599 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
emh203 | 0:3d9c67d97d6f | 600 | #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ |
emh203 | 0:3d9c67d97d6f | 601 | |
emh203 | 0:3d9c67d97d6f | 602 | /* SysTick Reload Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 603 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
emh203 | 0:3d9c67d97d6f | 604 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ |
emh203 | 0:3d9c67d97d6f | 605 | |
emh203 | 0:3d9c67d97d6f | 606 | /* SysTick Current Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 607 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
emh203 | 0:3d9c67d97d6f | 608 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ |
emh203 | 0:3d9c67d97d6f | 609 | |
emh203 | 0:3d9c67d97d6f | 610 | /* SysTick Calibration Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 611 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
emh203 | 0:3d9c67d97d6f | 612 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
emh203 | 0:3d9c67d97d6f | 613 | |
emh203 | 0:3d9c67d97d6f | 614 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
emh203 | 0:3d9c67d97d6f | 615 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
emh203 | 0:3d9c67d97d6f | 616 | |
emh203 | 0:3d9c67d97d6f | 617 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
emh203 | 0:3d9c67d97d6f | 618 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ |
emh203 | 0:3d9c67d97d6f | 619 | |
emh203 | 0:3d9c67d97d6f | 620 | /*@} end of group CMSIS_SysTick */ |
emh203 | 0:3d9c67d97d6f | 621 | |
emh203 | 0:3d9c67d97d6f | 622 | |
emh203 | 0:3d9c67d97d6f | 623 | /** \ingroup CMSIS_core_register |
emh203 | 0:3d9c67d97d6f | 624 | \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) |
emh203 | 0:3d9c67d97d6f | 625 | \brief Type definitions for the Instrumentation Trace Macrocell (ITM) |
emh203 | 0:3d9c67d97d6f | 626 | @{ |
emh203 | 0:3d9c67d97d6f | 627 | */ |
emh203 | 0:3d9c67d97d6f | 628 | |
emh203 | 0:3d9c67d97d6f | 629 | /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). |
emh203 | 0:3d9c67d97d6f | 630 | */ |
emh203 | 0:3d9c67d97d6f | 631 | typedef struct |
emh203 | 0:3d9c67d97d6f | 632 | { |
emh203 | 0:3d9c67d97d6f | 633 | __O union |
emh203 | 0:3d9c67d97d6f | 634 | { |
emh203 | 0:3d9c67d97d6f | 635 | __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ |
emh203 | 0:3d9c67d97d6f | 636 | __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ |
emh203 | 0:3d9c67d97d6f | 637 | __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ |
emh203 | 0:3d9c67d97d6f | 638 | } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ |
emh203 | 0:3d9c67d97d6f | 639 | uint32_t RESERVED0[864]; |
emh203 | 0:3d9c67d97d6f | 640 | __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ |
emh203 | 0:3d9c67d97d6f | 641 | uint32_t RESERVED1[15]; |
emh203 | 0:3d9c67d97d6f | 642 | __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ |
emh203 | 0:3d9c67d97d6f | 643 | uint32_t RESERVED2[15]; |
emh203 | 0:3d9c67d97d6f | 644 | __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ |
emh203 | 0:3d9c67d97d6f | 645 | uint32_t RESERVED3[29]; |
emh203 | 0:3d9c67d97d6f | 646 | __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ |
emh203 | 0:3d9c67d97d6f | 647 | __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ |
emh203 | 0:3d9c67d97d6f | 648 | __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ |
emh203 | 0:3d9c67d97d6f | 649 | uint32_t RESERVED4[43]; |
emh203 | 0:3d9c67d97d6f | 650 | __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ |
emh203 | 0:3d9c67d97d6f | 651 | __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ |
emh203 | 0:3d9c67d97d6f | 652 | uint32_t RESERVED5[6]; |
emh203 | 0:3d9c67d97d6f | 653 | __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ |
emh203 | 0:3d9c67d97d6f | 654 | __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ |
emh203 | 0:3d9c67d97d6f | 655 | __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ |
emh203 | 0:3d9c67d97d6f | 656 | __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ |
emh203 | 0:3d9c67d97d6f | 657 | __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ |
emh203 | 0:3d9c67d97d6f | 658 | __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ |
emh203 | 0:3d9c67d97d6f | 659 | __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ |
emh203 | 0:3d9c67d97d6f | 660 | __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ |
emh203 | 0:3d9c67d97d6f | 661 | __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ |
emh203 | 0:3d9c67d97d6f | 662 | __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ |
emh203 | 0:3d9c67d97d6f | 663 | __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ |
emh203 | 0:3d9c67d97d6f | 664 | __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ |
emh203 | 0:3d9c67d97d6f | 665 | } ITM_Type; |
emh203 | 0:3d9c67d97d6f | 666 | |
emh203 | 0:3d9c67d97d6f | 667 | /* ITM Trace Privilege Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 668 | #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ |
emh203 | 0:3d9c67d97d6f | 669 | #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ |
emh203 | 0:3d9c67d97d6f | 670 | |
emh203 | 0:3d9c67d97d6f | 671 | /* ITM Trace Control Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 672 | #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ |
emh203 | 0:3d9c67d97d6f | 673 | #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ |
emh203 | 0:3d9c67d97d6f | 674 | |
emh203 | 0:3d9c67d97d6f | 675 | #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ |
emh203 | 0:3d9c67d97d6f | 676 | #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ |
emh203 | 0:3d9c67d97d6f | 677 | |
emh203 | 0:3d9c67d97d6f | 678 | #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ |
emh203 | 0:3d9c67d97d6f | 679 | #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ |
emh203 | 0:3d9c67d97d6f | 680 | |
emh203 | 0:3d9c67d97d6f | 681 | #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ |
emh203 | 0:3d9c67d97d6f | 682 | #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ |
emh203 | 0:3d9c67d97d6f | 683 | |
emh203 | 0:3d9c67d97d6f | 684 | #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ |
emh203 | 0:3d9c67d97d6f | 685 | #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ |
emh203 | 0:3d9c67d97d6f | 686 | |
emh203 | 0:3d9c67d97d6f | 687 | #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ |
emh203 | 0:3d9c67d97d6f | 688 | #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ |
emh203 | 0:3d9c67d97d6f | 689 | |
emh203 | 0:3d9c67d97d6f | 690 | #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ |
emh203 | 0:3d9c67d97d6f | 691 | #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ |
emh203 | 0:3d9c67d97d6f | 692 | |
emh203 | 0:3d9c67d97d6f | 693 | #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ |
emh203 | 0:3d9c67d97d6f | 694 | #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ |
emh203 | 0:3d9c67d97d6f | 695 | |
emh203 | 0:3d9c67d97d6f | 696 | #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ |
emh203 | 0:3d9c67d97d6f | 697 | #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ |
emh203 | 0:3d9c67d97d6f | 698 | |
emh203 | 0:3d9c67d97d6f | 699 | /* ITM Integration Write Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 700 | #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ |
emh203 | 0:3d9c67d97d6f | 701 | #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ |
emh203 | 0:3d9c67d97d6f | 702 | |
emh203 | 0:3d9c67d97d6f | 703 | /* ITM Integration Read Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 704 | #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ |
emh203 | 0:3d9c67d97d6f | 705 | #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ |
emh203 | 0:3d9c67d97d6f | 706 | |
emh203 | 0:3d9c67d97d6f | 707 | /* ITM Integration Mode Control Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 708 | #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ |
emh203 | 0:3d9c67d97d6f | 709 | #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ |
emh203 | 0:3d9c67d97d6f | 710 | |
emh203 | 0:3d9c67d97d6f | 711 | /* ITM Lock Status Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 712 | #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ |
emh203 | 0:3d9c67d97d6f | 713 | #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ |
emh203 | 0:3d9c67d97d6f | 714 | |
emh203 | 0:3d9c67d97d6f | 715 | #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ |
emh203 | 0:3d9c67d97d6f | 716 | #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ |
emh203 | 0:3d9c67d97d6f | 717 | |
emh203 | 0:3d9c67d97d6f | 718 | #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ |
emh203 | 0:3d9c67d97d6f | 719 | #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ |
emh203 | 0:3d9c67d97d6f | 720 | |
emh203 | 0:3d9c67d97d6f | 721 | /*@}*/ /* end of group CMSIS_ITM */ |
emh203 | 0:3d9c67d97d6f | 722 | |
emh203 | 0:3d9c67d97d6f | 723 | |
emh203 | 0:3d9c67d97d6f | 724 | /** \ingroup CMSIS_core_register |
emh203 | 0:3d9c67d97d6f | 725 | \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) |
emh203 | 0:3d9c67d97d6f | 726 | \brief Type definitions for the Data Watchpoint and Trace (DWT) |
emh203 | 0:3d9c67d97d6f | 727 | @{ |
emh203 | 0:3d9c67d97d6f | 728 | */ |
emh203 | 0:3d9c67d97d6f | 729 | |
emh203 | 0:3d9c67d97d6f | 730 | /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). |
emh203 | 0:3d9c67d97d6f | 731 | */ |
emh203 | 0:3d9c67d97d6f | 732 | typedef struct |
emh203 | 0:3d9c67d97d6f | 733 | { |
emh203 | 0:3d9c67d97d6f | 734 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ |
emh203 | 0:3d9c67d97d6f | 735 | __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ |
emh203 | 0:3d9c67d97d6f | 736 | __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ |
emh203 | 0:3d9c67d97d6f | 737 | __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ |
emh203 | 0:3d9c67d97d6f | 738 | __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ |
emh203 | 0:3d9c67d97d6f | 739 | __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ |
emh203 | 0:3d9c67d97d6f | 740 | __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ |
emh203 | 0:3d9c67d97d6f | 741 | __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ |
emh203 | 0:3d9c67d97d6f | 742 | __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ |
emh203 | 0:3d9c67d97d6f | 743 | __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ |
emh203 | 0:3d9c67d97d6f | 744 | __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ |
emh203 | 0:3d9c67d97d6f | 745 | uint32_t RESERVED0[1]; |
emh203 | 0:3d9c67d97d6f | 746 | __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ |
emh203 | 0:3d9c67d97d6f | 747 | __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ |
emh203 | 0:3d9c67d97d6f | 748 | __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ |
emh203 | 0:3d9c67d97d6f | 749 | uint32_t RESERVED1[1]; |
emh203 | 0:3d9c67d97d6f | 750 | __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ |
emh203 | 0:3d9c67d97d6f | 751 | __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ |
emh203 | 0:3d9c67d97d6f | 752 | __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ |
emh203 | 0:3d9c67d97d6f | 753 | uint32_t RESERVED2[1]; |
emh203 | 0:3d9c67d97d6f | 754 | __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ |
emh203 | 0:3d9c67d97d6f | 755 | __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ |
emh203 | 0:3d9c67d97d6f | 756 | __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ |
emh203 | 0:3d9c67d97d6f | 757 | } DWT_Type; |
emh203 | 0:3d9c67d97d6f | 758 | |
emh203 | 0:3d9c67d97d6f | 759 | /* DWT Control Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 760 | #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ |
emh203 | 0:3d9c67d97d6f | 761 | #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ |
emh203 | 0:3d9c67d97d6f | 762 | |
emh203 | 0:3d9c67d97d6f | 763 | #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ |
emh203 | 0:3d9c67d97d6f | 764 | #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ |
emh203 | 0:3d9c67d97d6f | 765 | |
emh203 | 0:3d9c67d97d6f | 766 | #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ |
emh203 | 0:3d9c67d97d6f | 767 | #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ |
emh203 | 0:3d9c67d97d6f | 768 | |
emh203 | 0:3d9c67d97d6f | 769 | #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ |
emh203 | 0:3d9c67d97d6f | 770 | #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ |
emh203 | 0:3d9c67d97d6f | 771 | |
emh203 | 0:3d9c67d97d6f | 772 | #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ |
emh203 | 0:3d9c67d97d6f | 773 | #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ |
emh203 | 0:3d9c67d97d6f | 774 | |
emh203 | 0:3d9c67d97d6f | 775 | #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ |
emh203 | 0:3d9c67d97d6f | 776 | #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ |
emh203 | 0:3d9c67d97d6f | 777 | |
emh203 | 0:3d9c67d97d6f | 778 | #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ |
emh203 | 0:3d9c67d97d6f | 779 | #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ |
emh203 | 0:3d9c67d97d6f | 780 | |
emh203 | 0:3d9c67d97d6f | 781 | #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ |
emh203 | 0:3d9c67d97d6f | 782 | #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ |
emh203 | 0:3d9c67d97d6f | 783 | |
emh203 | 0:3d9c67d97d6f | 784 | #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ |
emh203 | 0:3d9c67d97d6f | 785 | #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ |
emh203 | 0:3d9c67d97d6f | 786 | |
emh203 | 0:3d9c67d97d6f | 787 | #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ |
emh203 | 0:3d9c67d97d6f | 788 | #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ |
emh203 | 0:3d9c67d97d6f | 789 | |
emh203 | 0:3d9c67d97d6f | 790 | #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ |
emh203 | 0:3d9c67d97d6f | 791 | #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ |
emh203 | 0:3d9c67d97d6f | 792 | |
emh203 | 0:3d9c67d97d6f | 793 | #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ |
emh203 | 0:3d9c67d97d6f | 794 | #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ |
emh203 | 0:3d9c67d97d6f | 795 | |
emh203 | 0:3d9c67d97d6f | 796 | #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ |
emh203 | 0:3d9c67d97d6f | 797 | #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ |
emh203 | 0:3d9c67d97d6f | 798 | |
emh203 | 0:3d9c67d97d6f | 799 | #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ |
emh203 | 0:3d9c67d97d6f | 800 | #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ |
emh203 | 0:3d9c67d97d6f | 801 | |
emh203 | 0:3d9c67d97d6f | 802 | #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ |
emh203 | 0:3d9c67d97d6f | 803 | #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ |
emh203 | 0:3d9c67d97d6f | 804 | |
emh203 | 0:3d9c67d97d6f | 805 | #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ |
emh203 | 0:3d9c67d97d6f | 806 | #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ |
emh203 | 0:3d9c67d97d6f | 807 | |
emh203 | 0:3d9c67d97d6f | 808 | #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ |
emh203 | 0:3d9c67d97d6f | 809 | #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ |
emh203 | 0:3d9c67d97d6f | 810 | |
emh203 | 0:3d9c67d97d6f | 811 | #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ |
emh203 | 0:3d9c67d97d6f | 812 | #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ |
emh203 | 0:3d9c67d97d6f | 813 | |
emh203 | 0:3d9c67d97d6f | 814 | /* DWT CPI Count Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 815 | #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ |
emh203 | 0:3d9c67d97d6f | 816 | #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ |
emh203 | 0:3d9c67d97d6f | 817 | |
emh203 | 0:3d9c67d97d6f | 818 | /* DWT Exception Overhead Count Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 819 | #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ |
emh203 | 0:3d9c67d97d6f | 820 | #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ |
emh203 | 0:3d9c67d97d6f | 821 | |
emh203 | 0:3d9c67d97d6f | 822 | /* DWT Sleep Count Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 823 | #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ |
emh203 | 0:3d9c67d97d6f | 824 | #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ |
emh203 | 0:3d9c67d97d6f | 825 | |
emh203 | 0:3d9c67d97d6f | 826 | /* DWT LSU Count Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 827 | #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ |
emh203 | 0:3d9c67d97d6f | 828 | #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ |
emh203 | 0:3d9c67d97d6f | 829 | |
emh203 | 0:3d9c67d97d6f | 830 | /* DWT Folded-instruction Count Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 831 | #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ |
emh203 | 0:3d9c67d97d6f | 832 | #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ |
emh203 | 0:3d9c67d97d6f | 833 | |
emh203 | 0:3d9c67d97d6f | 834 | /* DWT Comparator Mask Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 835 | #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ |
emh203 | 0:3d9c67d97d6f | 836 | #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ |
emh203 | 0:3d9c67d97d6f | 837 | |
emh203 | 0:3d9c67d97d6f | 838 | /* DWT Comparator Function Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 839 | #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ |
emh203 | 0:3d9c67d97d6f | 840 | #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ |
emh203 | 0:3d9c67d97d6f | 841 | |
emh203 | 0:3d9c67d97d6f | 842 | #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ |
emh203 | 0:3d9c67d97d6f | 843 | #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ |
emh203 | 0:3d9c67d97d6f | 844 | |
emh203 | 0:3d9c67d97d6f | 845 | #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ |
emh203 | 0:3d9c67d97d6f | 846 | #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ |
emh203 | 0:3d9c67d97d6f | 847 | |
emh203 | 0:3d9c67d97d6f | 848 | #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ |
emh203 | 0:3d9c67d97d6f | 849 | #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ |
emh203 | 0:3d9c67d97d6f | 850 | |
emh203 | 0:3d9c67d97d6f | 851 | #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ |
emh203 | 0:3d9c67d97d6f | 852 | #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ |
emh203 | 0:3d9c67d97d6f | 853 | |
emh203 | 0:3d9c67d97d6f | 854 | #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ |
emh203 | 0:3d9c67d97d6f | 855 | #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ |
emh203 | 0:3d9c67d97d6f | 856 | |
emh203 | 0:3d9c67d97d6f | 857 | #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ |
emh203 | 0:3d9c67d97d6f | 858 | #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ |
emh203 | 0:3d9c67d97d6f | 859 | |
emh203 | 0:3d9c67d97d6f | 860 | #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ |
emh203 | 0:3d9c67d97d6f | 861 | #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ |
emh203 | 0:3d9c67d97d6f | 862 | |
emh203 | 0:3d9c67d97d6f | 863 | #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ |
emh203 | 0:3d9c67d97d6f | 864 | #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ |
emh203 | 0:3d9c67d97d6f | 865 | |
emh203 | 0:3d9c67d97d6f | 866 | /*@}*/ /* end of group CMSIS_DWT */ |
emh203 | 0:3d9c67d97d6f | 867 | |
emh203 | 0:3d9c67d97d6f | 868 | |
emh203 | 0:3d9c67d97d6f | 869 | /** \ingroup CMSIS_core_register |
emh203 | 0:3d9c67d97d6f | 870 | \defgroup CMSIS_TPI Trace Port Interface (TPI) |
emh203 | 0:3d9c67d97d6f | 871 | \brief Type definitions for the Trace Port Interface (TPI) |
emh203 | 0:3d9c67d97d6f | 872 | @{ |
emh203 | 0:3d9c67d97d6f | 873 | */ |
emh203 | 0:3d9c67d97d6f | 874 | |
emh203 | 0:3d9c67d97d6f | 875 | /** \brief Structure type to access the Trace Port Interface Register (TPI). |
emh203 | 0:3d9c67d97d6f | 876 | */ |
emh203 | 0:3d9c67d97d6f | 877 | typedef struct |
emh203 | 0:3d9c67d97d6f | 878 | { |
emh203 | 0:3d9c67d97d6f | 879 | __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ |
emh203 | 0:3d9c67d97d6f | 880 | __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ |
emh203 | 0:3d9c67d97d6f | 881 | uint32_t RESERVED0[2]; |
emh203 | 0:3d9c67d97d6f | 882 | __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ |
emh203 | 0:3d9c67d97d6f | 883 | uint32_t RESERVED1[55]; |
emh203 | 0:3d9c67d97d6f | 884 | __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ |
emh203 | 0:3d9c67d97d6f | 885 | uint32_t RESERVED2[131]; |
emh203 | 0:3d9c67d97d6f | 886 | __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ |
emh203 | 0:3d9c67d97d6f | 887 | __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ |
emh203 | 0:3d9c67d97d6f | 888 | __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ |
emh203 | 0:3d9c67d97d6f | 889 | uint32_t RESERVED3[759]; |
emh203 | 0:3d9c67d97d6f | 890 | __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ |
emh203 | 0:3d9c67d97d6f | 891 | __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ |
emh203 | 0:3d9c67d97d6f | 892 | __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ |
emh203 | 0:3d9c67d97d6f | 893 | uint32_t RESERVED4[1]; |
emh203 | 0:3d9c67d97d6f | 894 | __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ |
emh203 | 0:3d9c67d97d6f | 895 | __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ |
emh203 | 0:3d9c67d97d6f | 896 | __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ |
emh203 | 0:3d9c67d97d6f | 897 | uint32_t RESERVED5[39]; |
emh203 | 0:3d9c67d97d6f | 898 | __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ |
emh203 | 0:3d9c67d97d6f | 899 | __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ |
emh203 | 0:3d9c67d97d6f | 900 | uint32_t RESERVED7[8]; |
emh203 | 0:3d9c67d97d6f | 901 | __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ |
emh203 | 0:3d9c67d97d6f | 902 | __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ |
emh203 | 0:3d9c67d97d6f | 903 | } TPI_Type; |
emh203 | 0:3d9c67d97d6f | 904 | |
emh203 | 0:3d9c67d97d6f | 905 | /* TPI Asynchronous Clock Prescaler Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 906 | #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ |
emh203 | 0:3d9c67d97d6f | 907 | #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ |
emh203 | 0:3d9c67d97d6f | 908 | |
emh203 | 0:3d9c67d97d6f | 909 | /* TPI Selected Pin Protocol Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 910 | #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ |
emh203 | 0:3d9c67d97d6f | 911 | #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ |
emh203 | 0:3d9c67d97d6f | 912 | |
emh203 | 0:3d9c67d97d6f | 913 | /* TPI Formatter and Flush Status Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 914 | #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ |
emh203 | 0:3d9c67d97d6f | 915 | #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ |
emh203 | 0:3d9c67d97d6f | 916 | |
emh203 | 0:3d9c67d97d6f | 917 | #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ |
emh203 | 0:3d9c67d97d6f | 918 | #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ |
emh203 | 0:3d9c67d97d6f | 919 | |
emh203 | 0:3d9c67d97d6f | 920 | #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ |
emh203 | 0:3d9c67d97d6f | 921 | #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ |
emh203 | 0:3d9c67d97d6f | 922 | |
emh203 | 0:3d9c67d97d6f | 923 | #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ |
emh203 | 0:3d9c67d97d6f | 924 | #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ |
emh203 | 0:3d9c67d97d6f | 925 | |
emh203 | 0:3d9c67d97d6f | 926 | /* TPI Formatter and Flush Control Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 927 | #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ |
emh203 | 0:3d9c67d97d6f | 928 | #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ |
emh203 | 0:3d9c67d97d6f | 929 | |
emh203 | 0:3d9c67d97d6f | 930 | #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ |
emh203 | 0:3d9c67d97d6f | 931 | #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ |
emh203 | 0:3d9c67d97d6f | 932 | |
emh203 | 0:3d9c67d97d6f | 933 | /* TPI TRIGGER Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 934 | #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ |
emh203 | 0:3d9c67d97d6f | 935 | #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ |
emh203 | 0:3d9c67d97d6f | 936 | |
emh203 | 0:3d9c67d97d6f | 937 | /* TPI Integration ETM Data Register Definitions (FIFO0) */ |
emh203 | 0:3d9c67d97d6f | 938 | #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ |
emh203 | 0:3d9c67d97d6f | 939 | #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ |
emh203 | 0:3d9c67d97d6f | 940 | |
emh203 | 0:3d9c67d97d6f | 941 | #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ |
emh203 | 0:3d9c67d97d6f | 942 | #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ |
emh203 | 0:3d9c67d97d6f | 943 | |
emh203 | 0:3d9c67d97d6f | 944 | #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ |
emh203 | 0:3d9c67d97d6f | 945 | #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ |
emh203 | 0:3d9c67d97d6f | 946 | |
emh203 | 0:3d9c67d97d6f | 947 | #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ |
emh203 | 0:3d9c67d97d6f | 948 | #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ |
emh203 | 0:3d9c67d97d6f | 949 | |
emh203 | 0:3d9c67d97d6f | 950 | #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ |
emh203 | 0:3d9c67d97d6f | 951 | #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ |
emh203 | 0:3d9c67d97d6f | 952 | |
emh203 | 0:3d9c67d97d6f | 953 | #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ |
emh203 | 0:3d9c67d97d6f | 954 | #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ |
emh203 | 0:3d9c67d97d6f | 955 | |
emh203 | 0:3d9c67d97d6f | 956 | #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ |
emh203 | 0:3d9c67d97d6f | 957 | #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ |
emh203 | 0:3d9c67d97d6f | 958 | |
emh203 | 0:3d9c67d97d6f | 959 | /* TPI ITATBCTR2 Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 960 | #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ |
emh203 | 0:3d9c67d97d6f | 961 | #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ |
emh203 | 0:3d9c67d97d6f | 962 | |
emh203 | 0:3d9c67d97d6f | 963 | /* TPI Integration ITM Data Register Definitions (FIFO1) */ |
emh203 | 0:3d9c67d97d6f | 964 | #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ |
emh203 | 0:3d9c67d97d6f | 965 | #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ |
emh203 | 0:3d9c67d97d6f | 966 | |
emh203 | 0:3d9c67d97d6f | 967 | #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ |
emh203 | 0:3d9c67d97d6f | 968 | #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ |
emh203 | 0:3d9c67d97d6f | 969 | |
emh203 | 0:3d9c67d97d6f | 970 | #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ |
emh203 | 0:3d9c67d97d6f | 971 | #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ |
emh203 | 0:3d9c67d97d6f | 972 | |
emh203 | 0:3d9c67d97d6f | 973 | #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ |
emh203 | 0:3d9c67d97d6f | 974 | #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ |
emh203 | 0:3d9c67d97d6f | 975 | |
emh203 | 0:3d9c67d97d6f | 976 | #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ |
emh203 | 0:3d9c67d97d6f | 977 | #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ |
emh203 | 0:3d9c67d97d6f | 978 | |
emh203 | 0:3d9c67d97d6f | 979 | #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ |
emh203 | 0:3d9c67d97d6f | 980 | #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ |
emh203 | 0:3d9c67d97d6f | 981 | |
emh203 | 0:3d9c67d97d6f | 982 | #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ |
emh203 | 0:3d9c67d97d6f | 983 | #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ |
emh203 | 0:3d9c67d97d6f | 984 | |
emh203 | 0:3d9c67d97d6f | 985 | /* TPI ITATBCTR0 Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 986 | #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ |
emh203 | 0:3d9c67d97d6f | 987 | #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ |
emh203 | 0:3d9c67d97d6f | 988 | |
emh203 | 0:3d9c67d97d6f | 989 | /* TPI Integration Mode Control Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 990 | #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ |
emh203 | 0:3d9c67d97d6f | 991 | #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ |
emh203 | 0:3d9c67d97d6f | 992 | |
emh203 | 0:3d9c67d97d6f | 993 | /* TPI DEVID Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 994 | #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ |
emh203 | 0:3d9c67d97d6f | 995 | #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ |
emh203 | 0:3d9c67d97d6f | 996 | |
emh203 | 0:3d9c67d97d6f | 997 | #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ |
emh203 | 0:3d9c67d97d6f | 998 | #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ |
emh203 | 0:3d9c67d97d6f | 999 | |
emh203 | 0:3d9c67d97d6f | 1000 | #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ |
emh203 | 0:3d9c67d97d6f | 1001 | #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ |
emh203 | 0:3d9c67d97d6f | 1002 | |
emh203 | 0:3d9c67d97d6f | 1003 | #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ |
emh203 | 0:3d9c67d97d6f | 1004 | #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ |
emh203 | 0:3d9c67d97d6f | 1005 | |
emh203 | 0:3d9c67d97d6f | 1006 | #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ |
emh203 | 0:3d9c67d97d6f | 1007 | #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ |
emh203 | 0:3d9c67d97d6f | 1008 | |
emh203 | 0:3d9c67d97d6f | 1009 | #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ |
emh203 | 0:3d9c67d97d6f | 1010 | #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ |
emh203 | 0:3d9c67d97d6f | 1011 | |
emh203 | 0:3d9c67d97d6f | 1012 | /* TPI DEVTYPE Register Definitions */ |
emh203 | 0:3d9c67d97d6f | 1013 | #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ |
emh203 | 0:3d9c67d97d6f | 1014 | #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ |
emh203 | 0:3d9c67d97d6f | 1015 | |
emh203 | 0:3d9c67d97d6f | 1016 | #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ |
emh203 | 0:3d9c67d97d6f | 1017 | #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ |
emh203 | 0:3d9c67d97d6f | 1018 | |
emh203 | 0:3d9c67d97d6f | 1019 | /*@}*/ /* end of group CMSIS_TPI */ |
emh203 | 0:3d9c67d97d6f | 1020 | |
emh203 | 0:3d9c67d97d6f | 1021 | |
emh203 | 0:3d9c67d97d6f | 1022 | #if (__MPU_PRESENT == 1) |
emh203 | 0:3d9c67d97d6f | 1023 | /** \ingroup CMSIS_core_register |
emh203 | 0:3d9c67d97d6f | 1024 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
emh203 | 0:3d9c67d97d6f | 1025 | \brief Type definitions for the Memory Protection Unit (MPU) |
emh203 | 0:3d9c67d97d6f | 1026 | @{ |
emh203 | 0:3d9c67d97d6f | 1027 | */ |
emh203 | 0:3d9c67d97d6f | 1028 | |
emh203 | 0:3d9c67d97d6f | 1029 | /** \brief Structure type to access the Memory Protection Unit (MPU). |
emh203 | 0:3d9c67d97d6f | 1030 | */ |
emh203 | 0:3d9c67d97d6f | 1031 | typedef struct |
emh203 | 0:3d9c67d97d6f | 1032 | { |
emh203 | 0:3d9c67d97d6f | 1033 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
emh203 | 0:3d9c67d97d6f | 1034 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
emh203 | 0:3d9c67d97d6f | 1035 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
emh203 | 0:3d9c67d97d6f | 1036 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
emh203 | 0:3d9c67d97d6f | 1037 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
emh203 | 0:3d9c67d97d6f | 1038 | __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ |
emh203 | 0:3d9c67d97d6f | 1039 | __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ |
emh203 | 0:3d9c67d97d6f | 1040 | __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ |
emh203 | 0:3d9c67d97d6f | 1041 | __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ |
emh203 | 0:3d9c67d97d6f | 1042 | __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ |
emh203 | 0:3d9c67d97d6f | 1043 | __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ |
emh203 | 0:3d9c67d97d6f | 1044 | } MPU_Type; |
emh203 | 0:3d9c67d97d6f | 1045 | |
emh203 | 0:3d9c67d97d6f | 1046 | /* MPU Type Register */ |
emh203 | 0:3d9c67d97d6f | 1047 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
emh203 | 0:3d9c67d97d6f | 1048 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
emh203 | 0:3d9c67d97d6f | 1049 | |
emh203 | 0:3d9c67d97d6f | 1050 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
emh203 | 0:3d9c67d97d6f | 1051 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
emh203 | 0:3d9c67d97d6f | 1052 | |
emh203 | 0:3d9c67d97d6f | 1053 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
emh203 | 0:3d9c67d97d6f | 1054 | #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ |
emh203 | 0:3d9c67d97d6f | 1055 | |
emh203 | 0:3d9c67d97d6f | 1056 | /* MPU Control Register */ |
emh203 | 0:3d9c67d97d6f | 1057 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
emh203 | 0:3d9c67d97d6f | 1058 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
emh203 | 0:3d9c67d97d6f | 1059 | |
emh203 | 0:3d9c67d97d6f | 1060 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
emh203 | 0:3d9c67d97d6f | 1061 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
emh203 | 0:3d9c67d97d6f | 1062 | |
emh203 | 0:3d9c67d97d6f | 1063 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
emh203 | 0:3d9c67d97d6f | 1064 | #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ |
emh203 | 0:3d9c67d97d6f | 1065 | |
emh203 | 0:3d9c67d97d6f | 1066 | /* MPU Region Number Register */ |
emh203 | 0:3d9c67d97d6f | 1067 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
emh203 | 0:3d9c67d97d6f | 1068 | #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ |
emh203 | 0:3d9c67d97d6f | 1069 | |
emh203 | 0:3d9c67d97d6f | 1070 | /* MPU Region Base Address Register */ |
emh203 | 0:3d9c67d97d6f | 1071 | #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ |
emh203 | 0:3d9c67d97d6f | 1072 | #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
emh203 | 0:3d9c67d97d6f | 1073 | |
emh203 | 0:3d9c67d97d6f | 1074 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
emh203 | 0:3d9c67d97d6f | 1075 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
emh203 | 0:3d9c67d97d6f | 1076 | |
emh203 | 0:3d9c67d97d6f | 1077 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
emh203 | 0:3d9c67d97d6f | 1078 | #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ |
emh203 | 0:3d9c67d97d6f | 1079 | |
emh203 | 0:3d9c67d97d6f | 1080 | /* MPU Region Attribute and Size Register */ |
emh203 | 0:3d9c67d97d6f | 1081 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ |
emh203 | 0:3d9c67d97d6f | 1082 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
emh203 | 0:3d9c67d97d6f | 1083 | |
emh203 | 0:3d9c67d97d6f | 1084 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ |
emh203 | 0:3d9c67d97d6f | 1085 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
emh203 | 0:3d9c67d97d6f | 1086 | |
emh203 | 0:3d9c67d97d6f | 1087 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ |
emh203 | 0:3d9c67d97d6f | 1088 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
emh203 | 0:3d9c67d97d6f | 1089 | |
emh203 | 0:3d9c67d97d6f | 1090 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ |
emh203 | 0:3d9c67d97d6f | 1091 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
emh203 | 0:3d9c67d97d6f | 1092 | |
emh203 | 0:3d9c67d97d6f | 1093 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ |
emh203 | 0:3d9c67d97d6f | 1094 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
emh203 | 0:3d9c67d97d6f | 1095 | |
emh203 | 0:3d9c67d97d6f | 1096 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ |
emh203 | 0:3d9c67d97d6f | 1097 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
emh203 | 0:3d9c67d97d6f | 1098 | |
emh203 | 0:3d9c67d97d6f | 1099 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ |
emh203 | 0:3d9c67d97d6f | 1100 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
emh203 | 0:3d9c67d97d6f | 1101 | |
emh203 | 0:3d9c67d97d6f | 1102 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
emh203 | 0:3d9c67d97d6f | 1103 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
emh203 | 0:3d9c67d97d6f | 1104 | |
emh203 | 0:3d9c67d97d6f | 1105 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
emh203 | 0:3d9c67d97d6f | 1106 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
emh203 | 0:3d9c67d97d6f | 1107 | |
emh203 | 0:3d9c67d97d6f | 1108 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
emh203 | 0:3d9c67d97d6f | 1109 | #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ |
emh203 | 0:3d9c67d97d6f | 1110 | |
emh203 | 0:3d9c67d97d6f | 1111 | /*@} end of group CMSIS_MPU */ |
emh203 | 0:3d9c67d97d6f | 1112 | #endif |
emh203 | 0:3d9c67d97d6f | 1113 | |
emh203 | 0:3d9c67d97d6f | 1114 | |
emh203 | 0:3d9c67d97d6f | 1115 | /** \ingroup CMSIS_core_register |
emh203 | 0:3d9c67d97d6f | 1116 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
emh203 | 0:3d9c67d97d6f | 1117 | \brief Type definitions for the Core Debug Registers |
emh203 | 0:3d9c67d97d6f | 1118 | @{ |
emh203 | 0:3d9c67d97d6f | 1119 | */ |
emh203 | 0:3d9c67d97d6f | 1120 | |
emh203 | 0:3d9c67d97d6f | 1121 | /** \brief Structure type to access the Core Debug Register (CoreDebug). |
emh203 | 0:3d9c67d97d6f | 1122 | */ |
emh203 | 0:3d9c67d97d6f | 1123 | typedef struct |
emh203 | 0:3d9c67d97d6f | 1124 | { |
emh203 | 0:3d9c67d97d6f | 1125 | __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ |
emh203 | 0:3d9c67d97d6f | 1126 | __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ |
emh203 | 0:3d9c67d97d6f | 1127 | __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ |
emh203 | 0:3d9c67d97d6f | 1128 | __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ |
emh203 | 0:3d9c67d97d6f | 1129 | } CoreDebug_Type; |
emh203 | 0:3d9c67d97d6f | 1130 | |
emh203 | 0:3d9c67d97d6f | 1131 | /* Debug Halting Control and Status Register */ |
emh203 | 0:3d9c67d97d6f | 1132 | #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ |
emh203 | 0:3d9c67d97d6f | 1133 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
emh203 | 0:3d9c67d97d6f | 1134 | |
emh203 | 0:3d9c67d97d6f | 1135 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
emh203 | 0:3d9c67d97d6f | 1136 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
emh203 | 0:3d9c67d97d6f | 1137 | |
emh203 | 0:3d9c67d97d6f | 1138 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
emh203 | 0:3d9c67d97d6f | 1139 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
emh203 | 0:3d9c67d97d6f | 1140 | |
emh203 | 0:3d9c67d97d6f | 1141 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
emh203 | 0:3d9c67d97d6f | 1142 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
emh203 | 0:3d9c67d97d6f | 1143 | |
emh203 | 0:3d9c67d97d6f | 1144 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ |
emh203 | 0:3d9c67d97d6f | 1145 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
emh203 | 0:3d9c67d97d6f | 1146 | |
emh203 | 0:3d9c67d97d6f | 1147 | #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ |
emh203 | 0:3d9c67d97d6f | 1148 | #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
emh203 | 0:3d9c67d97d6f | 1149 | |
emh203 | 0:3d9c67d97d6f | 1150 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ |
emh203 | 0:3d9c67d97d6f | 1151 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
emh203 | 0:3d9c67d97d6f | 1152 | |
emh203 | 0:3d9c67d97d6f | 1153 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ |
emh203 | 0:3d9c67d97d6f | 1154 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ |
emh203 | 0:3d9c67d97d6f | 1155 | |
emh203 | 0:3d9c67d97d6f | 1156 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
emh203 | 0:3d9c67d97d6f | 1157 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
emh203 | 0:3d9c67d97d6f | 1158 | |
emh203 | 0:3d9c67d97d6f | 1159 | #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ |
emh203 | 0:3d9c67d97d6f | 1160 | #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
emh203 | 0:3d9c67d97d6f | 1161 | |
emh203 | 0:3d9c67d97d6f | 1162 | #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ |
emh203 | 0:3d9c67d97d6f | 1163 | #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
emh203 | 0:3d9c67d97d6f | 1164 | |
emh203 | 0:3d9c67d97d6f | 1165 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
emh203 | 0:3d9c67d97d6f | 1166 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
emh203 | 0:3d9c67d97d6f | 1167 | |
emh203 | 0:3d9c67d97d6f | 1168 | /* Debug Core Register Selector Register */ |
emh203 | 0:3d9c67d97d6f | 1169 | #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ |
emh203 | 0:3d9c67d97d6f | 1170 | #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
emh203 | 0:3d9c67d97d6f | 1171 | |
emh203 | 0:3d9c67d97d6f | 1172 | #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ |
emh203 | 0:3d9c67d97d6f | 1173 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ |
emh203 | 0:3d9c67d97d6f | 1174 | |
emh203 | 0:3d9c67d97d6f | 1175 | /* Debug Exception and Monitor Control Register */ |
emh203 | 0:3d9c67d97d6f | 1176 | #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ |
emh203 | 0:3d9c67d97d6f | 1177 | #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ |
emh203 | 0:3d9c67d97d6f | 1178 | |
emh203 | 0:3d9c67d97d6f | 1179 | #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ |
emh203 | 0:3d9c67d97d6f | 1180 | #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ |
emh203 | 0:3d9c67d97d6f | 1181 | |
emh203 | 0:3d9c67d97d6f | 1182 | #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ |
emh203 | 0:3d9c67d97d6f | 1183 | #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ |
emh203 | 0:3d9c67d97d6f | 1184 | |
emh203 | 0:3d9c67d97d6f | 1185 | #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ |
emh203 | 0:3d9c67d97d6f | 1186 | #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ |
emh203 | 0:3d9c67d97d6f | 1187 | |
emh203 | 0:3d9c67d97d6f | 1188 | #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ |
emh203 | 0:3d9c67d97d6f | 1189 | #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ |
emh203 | 0:3d9c67d97d6f | 1190 | |
emh203 | 0:3d9c67d97d6f | 1191 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
emh203 | 0:3d9c67d97d6f | 1192 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
emh203 | 0:3d9c67d97d6f | 1193 | |
emh203 | 0:3d9c67d97d6f | 1194 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ |
emh203 | 0:3d9c67d97d6f | 1195 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ |
emh203 | 0:3d9c67d97d6f | 1196 | |
emh203 | 0:3d9c67d97d6f | 1197 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ |
emh203 | 0:3d9c67d97d6f | 1198 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ |
emh203 | 0:3d9c67d97d6f | 1199 | |
emh203 | 0:3d9c67d97d6f | 1200 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ |
emh203 | 0:3d9c67d97d6f | 1201 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ |
emh203 | 0:3d9c67d97d6f | 1202 | |
emh203 | 0:3d9c67d97d6f | 1203 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ |
emh203 | 0:3d9c67d97d6f | 1204 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ |
emh203 | 0:3d9c67d97d6f | 1205 | |
emh203 | 0:3d9c67d97d6f | 1206 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ |
emh203 | 0:3d9c67d97d6f | 1207 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ |
emh203 | 0:3d9c67d97d6f | 1208 | |
emh203 | 0:3d9c67d97d6f | 1209 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ |
emh203 | 0:3d9c67d97d6f | 1210 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ |
emh203 | 0:3d9c67d97d6f | 1211 | |
emh203 | 0:3d9c67d97d6f | 1212 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
emh203 | 0:3d9c67d97d6f | 1213 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
emh203 | 0:3d9c67d97d6f | 1214 | |
emh203 | 0:3d9c67d97d6f | 1215 | /*@} end of group CMSIS_CoreDebug */ |
emh203 | 0:3d9c67d97d6f | 1216 | |
emh203 | 0:3d9c67d97d6f | 1217 | |
emh203 | 0:3d9c67d97d6f | 1218 | /** \ingroup CMSIS_core_register |
emh203 | 0:3d9c67d97d6f | 1219 | \defgroup CMSIS_core_base Core Definitions |
emh203 | 0:3d9c67d97d6f | 1220 | \brief Definitions for base addresses, unions, and structures. |
emh203 | 0:3d9c67d97d6f | 1221 | @{ |
emh203 | 0:3d9c67d97d6f | 1222 | */ |
emh203 | 0:3d9c67d97d6f | 1223 | |
emh203 | 0:3d9c67d97d6f | 1224 | /* Memory mapping of Cortex-M3 Hardware */ |
emh203 | 0:3d9c67d97d6f | 1225 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
emh203 | 0:3d9c67d97d6f | 1226 | #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ |
emh203 | 0:3d9c67d97d6f | 1227 | #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ |
emh203 | 0:3d9c67d97d6f | 1228 | #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ |
emh203 | 0:3d9c67d97d6f | 1229 | #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ |
emh203 | 0:3d9c67d97d6f | 1230 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
emh203 | 0:3d9c67d97d6f | 1231 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
emh203 | 0:3d9c67d97d6f | 1232 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
emh203 | 0:3d9c67d97d6f | 1233 | |
emh203 | 0:3d9c67d97d6f | 1234 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
emh203 | 0:3d9c67d97d6f | 1235 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
emh203 | 0:3d9c67d97d6f | 1236 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
emh203 | 0:3d9c67d97d6f | 1237 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
emh203 | 0:3d9c67d97d6f | 1238 | #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ |
emh203 | 0:3d9c67d97d6f | 1239 | #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ |
emh203 | 0:3d9c67d97d6f | 1240 | #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ |
emh203 | 0:3d9c67d97d6f | 1241 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ |
emh203 | 0:3d9c67d97d6f | 1242 | |
emh203 | 0:3d9c67d97d6f | 1243 | #if (__MPU_PRESENT == 1) |
emh203 | 0:3d9c67d97d6f | 1244 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
emh203 | 0:3d9c67d97d6f | 1245 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
emh203 | 0:3d9c67d97d6f | 1246 | #endif |
emh203 | 0:3d9c67d97d6f | 1247 | |
emh203 | 0:3d9c67d97d6f | 1248 | /*@} */ |
emh203 | 0:3d9c67d97d6f | 1249 | |
emh203 | 0:3d9c67d97d6f | 1250 | |
emh203 | 0:3d9c67d97d6f | 1251 | |
emh203 | 0:3d9c67d97d6f | 1252 | /******************************************************************************* |
emh203 | 0:3d9c67d97d6f | 1253 | * Hardware Abstraction Layer |
emh203 | 0:3d9c67d97d6f | 1254 | Core Function Interface contains: |
emh203 | 0:3d9c67d97d6f | 1255 | - Core NVIC Functions |
emh203 | 0:3d9c67d97d6f | 1256 | - Core SysTick Functions |
emh203 | 0:3d9c67d97d6f | 1257 | - Core Debug Functions |
emh203 | 0:3d9c67d97d6f | 1258 | - Core Register Access Functions |
emh203 | 0:3d9c67d97d6f | 1259 | ******************************************************************************/ |
emh203 | 0:3d9c67d97d6f | 1260 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
emh203 | 0:3d9c67d97d6f | 1261 | */ |
emh203 | 0:3d9c67d97d6f | 1262 | |
emh203 | 0:3d9c67d97d6f | 1263 | |
emh203 | 0:3d9c67d97d6f | 1264 | |
emh203 | 0:3d9c67d97d6f | 1265 | /* ########################## NVIC functions #################################### */ |
emh203 | 0:3d9c67d97d6f | 1266 | /** \ingroup CMSIS_Core_FunctionInterface |
emh203 | 0:3d9c67d97d6f | 1267 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
emh203 | 0:3d9c67d97d6f | 1268 | \brief Functions that manage interrupts and exceptions via the NVIC. |
emh203 | 0:3d9c67d97d6f | 1269 | @{ |
emh203 | 0:3d9c67d97d6f | 1270 | */ |
emh203 | 0:3d9c67d97d6f | 1271 | |
emh203 | 0:3d9c67d97d6f | 1272 | /** \brief Set Priority Grouping |
emh203 | 0:3d9c67d97d6f | 1273 | |
emh203 | 0:3d9c67d97d6f | 1274 | The function sets the priority grouping field using the required unlock sequence. |
emh203 | 0:3d9c67d97d6f | 1275 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. |
emh203 | 0:3d9c67d97d6f | 1276 | Only values from 0..7 are used. |
emh203 | 0:3d9c67d97d6f | 1277 | In case of a conflict between priority grouping and available |
emh203 | 0:3d9c67d97d6f | 1278 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
emh203 | 0:3d9c67d97d6f | 1279 | |
emh203 | 0:3d9c67d97d6f | 1280 | \param [in] PriorityGroup Priority grouping field. |
emh203 | 0:3d9c67d97d6f | 1281 | */ |
emh203 | 0:3d9c67d97d6f | 1282 | __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
emh203 | 0:3d9c67d97d6f | 1283 | { |
emh203 | 0:3d9c67d97d6f | 1284 | uint32_t reg_value; |
emh203 | 0:3d9c67d97d6f | 1285 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ |
emh203 | 0:3d9c67d97d6f | 1286 | |
emh203 | 0:3d9c67d97d6f | 1287 | reg_value = SCB->AIRCR; /* read old register configuration */ |
emh203 | 0:3d9c67d97d6f | 1288 | reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ |
emh203 | 0:3d9c67d97d6f | 1289 | reg_value = (reg_value | |
emh203 | 0:3d9c67d97d6f | 1290 | ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
emh203 | 0:3d9c67d97d6f | 1291 | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ |
emh203 | 0:3d9c67d97d6f | 1292 | SCB->AIRCR = reg_value; |
emh203 | 0:3d9c67d97d6f | 1293 | } |
emh203 | 0:3d9c67d97d6f | 1294 | |
emh203 | 0:3d9c67d97d6f | 1295 | |
emh203 | 0:3d9c67d97d6f | 1296 | /** \brief Get Priority Grouping |
emh203 | 0:3d9c67d97d6f | 1297 | |
emh203 | 0:3d9c67d97d6f | 1298 | The function reads the priority grouping field from the NVIC Interrupt Controller. |
emh203 | 0:3d9c67d97d6f | 1299 | |
emh203 | 0:3d9c67d97d6f | 1300 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). |
emh203 | 0:3d9c67d97d6f | 1301 | */ |
emh203 | 0:3d9c67d97d6f | 1302 | __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) |
emh203 | 0:3d9c67d97d6f | 1303 | { |
emh203 | 0:3d9c67d97d6f | 1304 | return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ |
emh203 | 0:3d9c67d97d6f | 1305 | } |
emh203 | 0:3d9c67d97d6f | 1306 | |
emh203 | 0:3d9c67d97d6f | 1307 | |
emh203 | 0:3d9c67d97d6f | 1308 | /** \brief Enable External Interrupt |
emh203 | 0:3d9c67d97d6f | 1309 | |
emh203 | 0:3d9c67d97d6f | 1310 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
emh203 | 0:3d9c67d97d6f | 1311 | |
emh203 | 0:3d9c67d97d6f | 1312 | \param [in] IRQn External interrupt number. Value cannot be negative. |
emh203 | 0:3d9c67d97d6f | 1313 | */ |
emh203 | 0:3d9c67d97d6f | 1314 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
emh203 | 0:3d9c67d97d6f | 1315 | { |
emh203 | 0:3d9c67d97d6f | 1316 | NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ |
emh203 | 0:3d9c67d97d6f | 1317 | } |
emh203 | 0:3d9c67d97d6f | 1318 | |
emh203 | 0:3d9c67d97d6f | 1319 | |
emh203 | 0:3d9c67d97d6f | 1320 | /** \brief Disable External Interrupt |
emh203 | 0:3d9c67d97d6f | 1321 | |
emh203 | 0:3d9c67d97d6f | 1322 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
emh203 | 0:3d9c67d97d6f | 1323 | |
emh203 | 0:3d9c67d97d6f | 1324 | \param [in] IRQn External interrupt number. Value cannot be negative. |
emh203 | 0:3d9c67d97d6f | 1325 | */ |
emh203 | 0:3d9c67d97d6f | 1326 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
emh203 | 0:3d9c67d97d6f | 1327 | { |
emh203 | 0:3d9c67d97d6f | 1328 | NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ |
emh203 | 0:3d9c67d97d6f | 1329 | } |
emh203 | 0:3d9c67d97d6f | 1330 | |
emh203 | 0:3d9c67d97d6f | 1331 | |
emh203 | 0:3d9c67d97d6f | 1332 | /** \brief Get Pending Interrupt |
emh203 | 0:3d9c67d97d6f | 1333 | |
emh203 | 0:3d9c67d97d6f | 1334 | The function reads the pending register in the NVIC and returns the pending bit |
emh203 | 0:3d9c67d97d6f | 1335 | for the specified interrupt. |
emh203 | 0:3d9c67d97d6f | 1336 | |
emh203 | 0:3d9c67d97d6f | 1337 | \param [in] IRQn Interrupt number. |
emh203 | 0:3d9c67d97d6f | 1338 | |
emh203 | 0:3d9c67d97d6f | 1339 | \return 0 Interrupt status is not pending. |
emh203 | 0:3d9c67d97d6f | 1340 | \return 1 Interrupt status is pending. |
emh203 | 0:3d9c67d97d6f | 1341 | */ |
emh203 | 0:3d9c67d97d6f | 1342 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
emh203 | 0:3d9c67d97d6f | 1343 | { |
emh203 | 0:3d9c67d97d6f | 1344 | return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ |
emh203 | 0:3d9c67d97d6f | 1345 | } |
emh203 | 0:3d9c67d97d6f | 1346 | |
emh203 | 0:3d9c67d97d6f | 1347 | |
emh203 | 0:3d9c67d97d6f | 1348 | /** \brief Set Pending Interrupt |
emh203 | 0:3d9c67d97d6f | 1349 | |
emh203 | 0:3d9c67d97d6f | 1350 | The function sets the pending bit of an external interrupt. |
emh203 | 0:3d9c67d97d6f | 1351 | |
emh203 | 0:3d9c67d97d6f | 1352 | \param [in] IRQn Interrupt number. Value cannot be negative. |
emh203 | 0:3d9c67d97d6f | 1353 | */ |
emh203 | 0:3d9c67d97d6f | 1354 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
emh203 | 0:3d9c67d97d6f | 1355 | { |
emh203 | 0:3d9c67d97d6f | 1356 | NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ |
emh203 | 0:3d9c67d97d6f | 1357 | } |
emh203 | 0:3d9c67d97d6f | 1358 | |
emh203 | 0:3d9c67d97d6f | 1359 | |
emh203 | 0:3d9c67d97d6f | 1360 | /** \brief Clear Pending Interrupt |
emh203 | 0:3d9c67d97d6f | 1361 | |
emh203 | 0:3d9c67d97d6f | 1362 | The function clears the pending bit of an external interrupt. |
emh203 | 0:3d9c67d97d6f | 1363 | |
emh203 | 0:3d9c67d97d6f | 1364 | \param [in] IRQn External interrupt number. Value cannot be negative. |
emh203 | 0:3d9c67d97d6f | 1365 | */ |
emh203 | 0:3d9c67d97d6f | 1366 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
emh203 | 0:3d9c67d97d6f | 1367 | { |
emh203 | 0:3d9c67d97d6f | 1368 | NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ |
emh203 | 0:3d9c67d97d6f | 1369 | } |
emh203 | 0:3d9c67d97d6f | 1370 | |
emh203 | 0:3d9c67d97d6f | 1371 | |
emh203 | 0:3d9c67d97d6f | 1372 | /** \brief Get Active Interrupt |
emh203 | 0:3d9c67d97d6f | 1373 | |
emh203 | 0:3d9c67d97d6f | 1374 | The function reads the active register in NVIC and returns the active bit. |
emh203 | 0:3d9c67d97d6f | 1375 | |
emh203 | 0:3d9c67d97d6f | 1376 | \param [in] IRQn Interrupt number. |
emh203 | 0:3d9c67d97d6f | 1377 | |
emh203 | 0:3d9c67d97d6f | 1378 | \return 0 Interrupt status is not active. |
emh203 | 0:3d9c67d97d6f | 1379 | \return 1 Interrupt status is active. |
emh203 | 0:3d9c67d97d6f | 1380 | */ |
emh203 | 0:3d9c67d97d6f | 1381 | __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) |
emh203 | 0:3d9c67d97d6f | 1382 | { |
emh203 | 0:3d9c67d97d6f | 1383 | return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ |
emh203 | 0:3d9c67d97d6f | 1384 | } |
emh203 | 0:3d9c67d97d6f | 1385 | |
emh203 | 0:3d9c67d97d6f | 1386 | |
emh203 | 0:3d9c67d97d6f | 1387 | /** \brief Set Interrupt Priority |
emh203 | 0:3d9c67d97d6f | 1388 | |
emh203 | 0:3d9c67d97d6f | 1389 | The function sets the priority of an interrupt. |
emh203 | 0:3d9c67d97d6f | 1390 | |
emh203 | 0:3d9c67d97d6f | 1391 | \note The priority cannot be set for every core interrupt. |
emh203 | 0:3d9c67d97d6f | 1392 | |
emh203 | 0:3d9c67d97d6f | 1393 | \param [in] IRQn Interrupt number. |
emh203 | 0:3d9c67d97d6f | 1394 | \param [in] priority Priority to set. |
emh203 | 0:3d9c67d97d6f | 1395 | */ |
emh203 | 0:3d9c67d97d6f | 1396 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
emh203 | 0:3d9c67d97d6f | 1397 | { |
emh203 | 0:3d9c67d97d6f | 1398 | if(IRQn < 0) { |
emh203 | 0:3d9c67d97d6f | 1399 | SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ |
emh203 | 0:3d9c67d97d6f | 1400 | else { |
emh203 | 0:3d9c67d97d6f | 1401 | NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ |
emh203 | 0:3d9c67d97d6f | 1402 | } |
emh203 | 0:3d9c67d97d6f | 1403 | |
emh203 | 0:3d9c67d97d6f | 1404 | |
emh203 | 0:3d9c67d97d6f | 1405 | /** \brief Get Interrupt Priority |
emh203 | 0:3d9c67d97d6f | 1406 | |
emh203 | 0:3d9c67d97d6f | 1407 | The function reads the priority of an interrupt. The interrupt |
emh203 | 0:3d9c67d97d6f | 1408 | number can be positive to specify an external (device specific) |
emh203 | 0:3d9c67d97d6f | 1409 | interrupt, or negative to specify an internal (core) interrupt. |
emh203 | 0:3d9c67d97d6f | 1410 | |
emh203 | 0:3d9c67d97d6f | 1411 | |
emh203 | 0:3d9c67d97d6f | 1412 | \param [in] IRQn Interrupt number. |
emh203 | 0:3d9c67d97d6f | 1413 | \return Interrupt Priority. Value is aligned automatically to the implemented |
emh203 | 0:3d9c67d97d6f | 1414 | priority bits of the microcontroller. |
emh203 | 0:3d9c67d97d6f | 1415 | */ |
emh203 | 0:3d9c67d97d6f | 1416 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
emh203 | 0:3d9c67d97d6f | 1417 | { |
emh203 | 0:3d9c67d97d6f | 1418 | |
emh203 | 0:3d9c67d97d6f | 1419 | if(IRQn < 0) { |
emh203 | 0:3d9c67d97d6f | 1420 | return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ |
emh203 | 0:3d9c67d97d6f | 1421 | else { |
emh203 | 0:3d9c67d97d6f | 1422 | return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ |
emh203 | 0:3d9c67d97d6f | 1423 | } |
emh203 | 0:3d9c67d97d6f | 1424 | |
emh203 | 0:3d9c67d97d6f | 1425 | |
emh203 | 0:3d9c67d97d6f | 1426 | /** \brief Encode Priority |
emh203 | 0:3d9c67d97d6f | 1427 | |
emh203 | 0:3d9c67d97d6f | 1428 | The function encodes the priority for an interrupt with the given priority group, |
emh203 | 0:3d9c67d97d6f | 1429 | preemptive priority value, and subpriority value. |
emh203 | 0:3d9c67d97d6f | 1430 | In case of a conflict between priority grouping and available |
emh203 | 0:3d9c67d97d6f | 1431 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
emh203 | 0:3d9c67d97d6f | 1432 | |
emh203 | 0:3d9c67d97d6f | 1433 | \param [in] PriorityGroup Used priority group. |
emh203 | 0:3d9c67d97d6f | 1434 | \param [in] PreemptPriority Preemptive priority value (starting from 0). |
emh203 | 0:3d9c67d97d6f | 1435 | \param [in] SubPriority Subpriority value (starting from 0). |
emh203 | 0:3d9c67d97d6f | 1436 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
emh203 | 0:3d9c67d97d6f | 1437 | */ |
emh203 | 0:3d9c67d97d6f | 1438 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
emh203 | 0:3d9c67d97d6f | 1439 | { |
emh203 | 0:3d9c67d97d6f | 1440 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
emh203 | 0:3d9c67d97d6f | 1441 | uint32_t PreemptPriorityBits; |
emh203 | 0:3d9c67d97d6f | 1442 | uint32_t SubPriorityBits; |
emh203 | 0:3d9c67d97d6f | 1443 | |
emh203 | 0:3d9c67d97d6f | 1444 | PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
emh203 | 0:3d9c67d97d6f | 1445 | SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
emh203 | 0:3d9c67d97d6f | 1446 | |
emh203 | 0:3d9c67d97d6f | 1447 | return ( |
emh203 | 0:3d9c67d97d6f | 1448 | ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | |
emh203 | 0:3d9c67d97d6f | 1449 | ((SubPriority & ((1 << (SubPriorityBits )) - 1))) |
emh203 | 0:3d9c67d97d6f | 1450 | ); |
emh203 | 0:3d9c67d97d6f | 1451 | } |
emh203 | 0:3d9c67d97d6f | 1452 | |
emh203 | 0:3d9c67d97d6f | 1453 | |
emh203 | 0:3d9c67d97d6f | 1454 | /** \brief Decode Priority |
emh203 | 0:3d9c67d97d6f | 1455 | |
emh203 | 0:3d9c67d97d6f | 1456 | The function decodes an interrupt priority value with a given priority group to |
emh203 | 0:3d9c67d97d6f | 1457 | preemptive priority value and subpriority value. |
emh203 | 0:3d9c67d97d6f | 1458 | In case of a conflict between priority grouping and available |
emh203 | 0:3d9c67d97d6f | 1459 | priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
emh203 | 0:3d9c67d97d6f | 1460 | |
emh203 | 0:3d9c67d97d6f | 1461 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
emh203 | 0:3d9c67d97d6f | 1462 | \param [in] PriorityGroup Used priority group. |
emh203 | 0:3d9c67d97d6f | 1463 | \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
emh203 | 0:3d9c67d97d6f | 1464 | \param [out] pSubPriority Subpriority value (starting from 0). |
emh203 | 0:3d9c67d97d6f | 1465 | */ |
emh203 | 0:3d9c67d97d6f | 1466 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) |
emh203 | 0:3d9c67d97d6f | 1467 | { |
emh203 | 0:3d9c67d97d6f | 1468 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
emh203 | 0:3d9c67d97d6f | 1469 | uint32_t PreemptPriorityBits; |
emh203 | 0:3d9c67d97d6f | 1470 | uint32_t SubPriorityBits; |
emh203 | 0:3d9c67d97d6f | 1471 | |
emh203 | 0:3d9c67d97d6f | 1472 | PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
emh203 | 0:3d9c67d97d6f | 1473 | SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
emh203 | 0:3d9c67d97d6f | 1474 | |
emh203 | 0:3d9c67d97d6f | 1475 | *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); |
emh203 | 0:3d9c67d97d6f | 1476 | *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); |
emh203 | 0:3d9c67d97d6f | 1477 | } |
emh203 | 0:3d9c67d97d6f | 1478 | |
emh203 | 0:3d9c67d97d6f | 1479 | |
emh203 | 0:3d9c67d97d6f | 1480 | /** \brief System Reset |
emh203 | 0:3d9c67d97d6f | 1481 | |
emh203 | 0:3d9c67d97d6f | 1482 | The function initiates a system reset request to reset the MCU. |
emh203 | 0:3d9c67d97d6f | 1483 | */ |
emh203 | 0:3d9c67d97d6f | 1484 | __STATIC_INLINE void NVIC_SystemReset(void) |
emh203 | 0:3d9c67d97d6f | 1485 | { |
emh203 | 0:3d9c67d97d6f | 1486 | __DSB(); /* Ensure all outstanding memory accesses included |
emh203 | 0:3d9c67d97d6f | 1487 | buffered write are completed before reset */ |
emh203 | 0:3d9c67d97d6f | 1488 | SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
emh203 | 0:3d9c67d97d6f | 1489 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
emh203 | 0:3d9c67d97d6f | 1490 | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ |
emh203 | 0:3d9c67d97d6f | 1491 | __DSB(); /* Ensure completion of memory access */ |
emh203 | 0:3d9c67d97d6f | 1492 | while(1); /* wait until reset */ |
emh203 | 0:3d9c67d97d6f | 1493 | } |
emh203 | 0:3d9c67d97d6f | 1494 | |
emh203 | 0:3d9c67d97d6f | 1495 | /*@} end of CMSIS_Core_NVICFunctions */ |
emh203 | 0:3d9c67d97d6f | 1496 | |
emh203 | 0:3d9c67d97d6f | 1497 | |
emh203 | 0:3d9c67d97d6f | 1498 | |
emh203 | 0:3d9c67d97d6f | 1499 | /* ################################## SysTick function ############################################ */ |
emh203 | 0:3d9c67d97d6f | 1500 | /** \ingroup CMSIS_Core_FunctionInterface |
emh203 | 0:3d9c67d97d6f | 1501 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
emh203 | 0:3d9c67d97d6f | 1502 | \brief Functions that configure the System. |
emh203 | 0:3d9c67d97d6f | 1503 | @{ |
emh203 | 0:3d9c67d97d6f | 1504 | */ |
emh203 | 0:3d9c67d97d6f | 1505 | |
emh203 | 0:3d9c67d97d6f | 1506 | #if (__Vendor_SysTickConfig == 0) |
emh203 | 0:3d9c67d97d6f | 1507 | |
emh203 | 0:3d9c67d97d6f | 1508 | /** \brief System Tick Configuration |
emh203 | 0:3d9c67d97d6f | 1509 | |
emh203 | 0:3d9c67d97d6f | 1510 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
emh203 | 0:3d9c67d97d6f | 1511 | Counter is in free running mode to generate periodic interrupts. |
emh203 | 0:3d9c67d97d6f | 1512 | |
emh203 | 0:3d9c67d97d6f | 1513 | \param [in] ticks Number of ticks between two interrupts. |
emh203 | 0:3d9c67d97d6f | 1514 | |
emh203 | 0:3d9c67d97d6f | 1515 | \return 0 Function succeeded. |
emh203 | 0:3d9c67d97d6f | 1516 | \return 1 Function failed. |
emh203 | 0:3d9c67d97d6f | 1517 | |
emh203 | 0:3d9c67d97d6f | 1518 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
emh203 | 0:3d9c67d97d6f | 1519 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
emh203 | 0:3d9c67d97d6f | 1520 | must contain a vendor-specific implementation of this function. |
emh203 | 0:3d9c67d97d6f | 1521 | |
emh203 | 0:3d9c67d97d6f | 1522 | */ |
emh203 | 0:3d9c67d97d6f | 1523 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
emh203 | 0:3d9c67d97d6f | 1524 | { |
emh203 | 0:3d9c67d97d6f | 1525 | if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ |
emh203 | 0:3d9c67d97d6f | 1526 | |
emh203 | 0:3d9c67d97d6f | 1527 | SysTick->LOAD = ticks - 1; /* set reload register */ |
emh203 | 0:3d9c67d97d6f | 1528 | NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ |
emh203 | 0:3d9c67d97d6f | 1529 | SysTick->VAL = 0; /* Load the SysTick Counter Value */ |
emh203 | 0:3d9c67d97d6f | 1530 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
emh203 | 0:3d9c67d97d6f | 1531 | SysTick_CTRL_TICKINT_Msk | |
emh203 | 0:3d9c67d97d6f | 1532 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
emh203 | 0:3d9c67d97d6f | 1533 | return (0); /* Function successful */ |
emh203 | 0:3d9c67d97d6f | 1534 | } |
emh203 | 0:3d9c67d97d6f | 1535 | |
emh203 | 0:3d9c67d97d6f | 1536 | #endif |
emh203 | 0:3d9c67d97d6f | 1537 | |
emh203 | 0:3d9c67d97d6f | 1538 | /*@} end of CMSIS_Core_SysTickFunctions */ |
emh203 | 0:3d9c67d97d6f | 1539 | |
emh203 | 0:3d9c67d97d6f | 1540 | |
emh203 | 0:3d9c67d97d6f | 1541 | |
emh203 | 0:3d9c67d97d6f | 1542 | /* ##################################### Debug In/Output function ########################################### */ |
emh203 | 0:3d9c67d97d6f | 1543 | /** \ingroup CMSIS_Core_FunctionInterface |
emh203 | 0:3d9c67d97d6f | 1544 | \defgroup CMSIS_core_DebugFunctions ITM Functions |
emh203 | 0:3d9c67d97d6f | 1545 | \brief Functions that access the ITM debug interface. |
emh203 | 0:3d9c67d97d6f | 1546 | @{ |
emh203 | 0:3d9c67d97d6f | 1547 | */ |
emh203 | 0:3d9c67d97d6f | 1548 | |
emh203 | 0:3d9c67d97d6f | 1549 | extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ |
emh203 | 0:3d9c67d97d6f | 1550 | #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ |
emh203 | 0:3d9c67d97d6f | 1551 | |
emh203 | 0:3d9c67d97d6f | 1552 | |
emh203 | 0:3d9c67d97d6f | 1553 | /** \brief ITM Send Character |
emh203 | 0:3d9c67d97d6f | 1554 | |
emh203 | 0:3d9c67d97d6f | 1555 | The function transmits a character via the ITM channel 0, and |
emh203 | 0:3d9c67d97d6f | 1556 | \li Just returns when no debugger is connected that has booked the output. |
emh203 | 0:3d9c67d97d6f | 1557 | \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. |
emh203 | 0:3d9c67d97d6f | 1558 | |
emh203 | 0:3d9c67d97d6f | 1559 | \param [in] ch Character to transmit. |
emh203 | 0:3d9c67d97d6f | 1560 | |
emh203 | 0:3d9c67d97d6f | 1561 | \returns Character to transmit. |
emh203 | 0:3d9c67d97d6f | 1562 | */ |
emh203 | 0:3d9c67d97d6f | 1563 | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) |
emh203 | 0:3d9c67d97d6f | 1564 | { |
emh203 | 0:3d9c67d97d6f | 1565 | if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ |
emh203 | 0:3d9c67d97d6f | 1566 | (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ |
emh203 | 0:3d9c67d97d6f | 1567 | { |
emh203 | 0:3d9c67d97d6f | 1568 | while (ITM->PORT[0].u32 == 0); |
emh203 | 0:3d9c67d97d6f | 1569 | ITM->PORT[0].u8 = (uint8_t) ch; |
emh203 | 0:3d9c67d97d6f | 1570 | } |
emh203 | 0:3d9c67d97d6f | 1571 | return (ch); |
emh203 | 0:3d9c67d97d6f | 1572 | } |
emh203 | 0:3d9c67d97d6f | 1573 | |
emh203 | 0:3d9c67d97d6f | 1574 | |
emh203 | 0:3d9c67d97d6f | 1575 | /** \brief ITM Receive Character |
emh203 | 0:3d9c67d97d6f | 1576 | |
emh203 | 0:3d9c67d97d6f | 1577 | The function inputs a character via the external variable \ref ITM_RxBuffer. |
emh203 | 0:3d9c67d97d6f | 1578 | |
emh203 | 0:3d9c67d97d6f | 1579 | \return Received character. |
emh203 | 0:3d9c67d97d6f | 1580 | \return -1 No character pending. |
emh203 | 0:3d9c67d97d6f | 1581 | */ |
emh203 | 0:3d9c67d97d6f | 1582 | __STATIC_INLINE int32_t ITM_ReceiveChar (void) { |
emh203 | 0:3d9c67d97d6f | 1583 | int32_t ch = -1; /* no character available */ |
emh203 | 0:3d9c67d97d6f | 1584 | |
emh203 | 0:3d9c67d97d6f | 1585 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { |
emh203 | 0:3d9c67d97d6f | 1586 | ch = ITM_RxBuffer; |
emh203 | 0:3d9c67d97d6f | 1587 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ |
emh203 | 0:3d9c67d97d6f | 1588 | } |
emh203 | 0:3d9c67d97d6f | 1589 | |
emh203 | 0:3d9c67d97d6f | 1590 | return (ch); |
emh203 | 0:3d9c67d97d6f | 1591 | } |
emh203 | 0:3d9c67d97d6f | 1592 | |
emh203 | 0:3d9c67d97d6f | 1593 | |
emh203 | 0:3d9c67d97d6f | 1594 | /** \brief ITM Check Character |
emh203 | 0:3d9c67d97d6f | 1595 | |
emh203 | 0:3d9c67d97d6f | 1596 | The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. |
emh203 | 0:3d9c67d97d6f | 1597 | |
emh203 | 0:3d9c67d97d6f | 1598 | \return 0 No character available. |
emh203 | 0:3d9c67d97d6f | 1599 | \return 1 Character available. |
emh203 | 0:3d9c67d97d6f | 1600 | */ |
emh203 | 0:3d9c67d97d6f | 1601 | __STATIC_INLINE int32_t ITM_CheckChar (void) { |
emh203 | 0:3d9c67d97d6f | 1602 | |
emh203 | 0:3d9c67d97d6f | 1603 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { |
emh203 | 0:3d9c67d97d6f | 1604 | return (0); /* no character available */ |
emh203 | 0:3d9c67d97d6f | 1605 | } else { |
emh203 | 0:3d9c67d97d6f | 1606 | return (1); /* character available */ |
emh203 | 0:3d9c67d97d6f | 1607 | } |
emh203 | 0:3d9c67d97d6f | 1608 | } |
emh203 | 0:3d9c67d97d6f | 1609 | |
emh203 | 0:3d9c67d97d6f | 1610 | /*@} end of CMSIS_core_DebugFunctions */ |
emh203 | 0:3d9c67d97d6f | 1611 | |
emh203 | 0:3d9c67d97d6f | 1612 | #endif /* __CORE_SC300_H_DEPENDANT */ |
emh203 | 0:3d9c67d97d6f | 1613 | |
emh203 | 0:3d9c67d97d6f | 1614 | #ifdef __cplusplus |
emh203 | 0:3d9c67d97d6f | 1615 | } |
emh203 | 0:3d9c67d97d6f | 1616 | #endif |
emh203 | 0:3d9c67d97d6f | 1617 | |
emh203 | 0:3d9c67d97d6f | 1618 | #endif /* __CMSIS_GENERIC */ |