Lightweight Mbed Library for STM F4 and F7
hal/spi_api.h@2:0edeaf13dfb2, 2021-02-04 (annotated)
- Committer:
- elijahsj
- Date:
- Thu Feb 04 20:44:34 2021 +0000
- Revision:
- 2:0edeaf13dfb2
- Parent:
- 0:083111ae2a11
modfiied for spine board;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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saloutos | 0:083111ae2a11 | 1 | |
saloutos | 0:083111ae2a11 | 2 | /** \addtogroup hal */ |
saloutos | 0:083111ae2a11 | 3 | /** @{*/ |
saloutos | 0:083111ae2a11 | 4 | /* mbed Microcontroller Library |
saloutos | 0:083111ae2a11 | 5 | * Copyright (c) 2006-2013 ARM Limited |
saloutos | 0:083111ae2a11 | 6 | * |
saloutos | 0:083111ae2a11 | 7 | * Licensed under the Apache License, Version 2.0 (the "License"); |
saloutos | 0:083111ae2a11 | 8 | * you may not use this file except in compliance with the License. |
saloutos | 0:083111ae2a11 | 9 | * You may obtain a copy of the License at |
saloutos | 0:083111ae2a11 | 10 | * |
saloutos | 0:083111ae2a11 | 11 | * http://www.apache.org/licenses/LICENSE-2.0 |
saloutos | 0:083111ae2a11 | 12 | * |
saloutos | 0:083111ae2a11 | 13 | * Unless required by applicable law or agreed to in writing, software |
saloutos | 0:083111ae2a11 | 14 | * distributed under the License is distributed on an "AS IS" BASIS, |
saloutos | 0:083111ae2a11 | 15 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
saloutos | 0:083111ae2a11 | 16 | * See the License for the specific language governing permissions and |
saloutos | 0:083111ae2a11 | 17 | * limitations under the License. |
saloutos | 0:083111ae2a11 | 18 | */ |
saloutos | 0:083111ae2a11 | 19 | #ifndef MBED_SPI_API_H |
saloutos | 0:083111ae2a11 | 20 | #define MBED_SPI_API_H |
saloutos | 0:083111ae2a11 | 21 | |
saloutos | 0:083111ae2a11 | 22 | #include "device.h" |
saloutos | 0:083111ae2a11 | 23 | #include "hal/dma_api.h" |
saloutos | 0:083111ae2a11 | 24 | #include "hal/buffer.h" |
saloutos | 0:083111ae2a11 | 25 | |
saloutos | 0:083111ae2a11 | 26 | #if DEVICE_SPI |
saloutos | 0:083111ae2a11 | 27 | |
saloutos | 0:083111ae2a11 | 28 | #define SPI_EVENT_ERROR (1 << 1) |
saloutos | 0:083111ae2a11 | 29 | #define SPI_EVENT_COMPLETE (1 << 2) |
saloutos | 0:083111ae2a11 | 30 | #define SPI_EVENT_RX_OVERFLOW (1 << 3) |
saloutos | 0:083111ae2a11 | 31 | #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW) |
saloutos | 0:083111ae2a11 | 32 | |
saloutos | 0:083111ae2a11 | 33 | #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred |
saloutos | 0:083111ae2a11 | 34 | |
saloutos | 0:083111ae2a11 | 35 | #define SPI_FILL_WORD (0xFFFF) |
saloutos | 0:083111ae2a11 | 36 | #define SPI_FILL_CHAR (0xFF) |
saloutos | 0:083111ae2a11 | 37 | |
saloutos | 0:083111ae2a11 | 38 | #if DEVICE_SPI_ASYNCH |
saloutos | 0:083111ae2a11 | 39 | /** Asynch SPI HAL structure |
saloutos | 0:083111ae2a11 | 40 | */ |
saloutos | 0:083111ae2a11 | 41 | typedef struct { |
saloutos | 0:083111ae2a11 | 42 | struct spi_s spi; /**< Target specific SPI structure */ |
saloutos | 0:083111ae2a11 | 43 | struct buffer_s tx_buff; /**< Tx buffer */ |
saloutos | 0:083111ae2a11 | 44 | struct buffer_s rx_buff; /**< Rx buffer */ |
saloutos | 0:083111ae2a11 | 45 | } spi_t; |
saloutos | 0:083111ae2a11 | 46 | |
saloutos | 0:083111ae2a11 | 47 | #else |
saloutos | 0:083111ae2a11 | 48 | /** Non-asynch SPI HAL structure |
saloutos | 0:083111ae2a11 | 49 | */ |
saloutos | 0:083111ae2a11 | 50 | typedef struct spi_s spi_t; |
saloutos | 0:083111ae2a11 | 51 | |
saloutos | 0:083111ae2a11 | 52 | #endif |
saloutos | 0:083111ae2a11 | 53 | |
saloutos | 0:083111ae2a11 | 54 | #ifdef __cplusplus |
saloutos | 0:083111ae2a11 | 55 | extern "C" { |
saloutos | 0:083111ae2a11 | 56 | #endif |
saloutos | 0:083111ae2a11 | 57 | |
saloutos | 0:083111ae2a11 | 58 | /** |
saloutos | 0:083111ae2a11 | 59 | * \defgroup hal_GeneralSPI SPI Configuration Functions |
saloutos | 0:083111ae2a11 | 60 | * @{ |
saloutos | 0:083111ae2a11 | 61 | */ |
saloutos | 0:083111ae2a11 | 62 | |
saloutos | 0:083111ae2a11 | 63 | /** Initialize the SPI peripheral |
saloutos | 0:083111ae2a11 | 64 | * |
saloutos | 0:083111ae2a11 | 65 | * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral |
saloutos | 0:083111ae2a11 | 66 | * @param[out] obj The SPI object to initialize |
saloutos | 0:083111ae2a11 | 67 | * @param[in] mosi The pin to use for MOSI |
saloutos | 0:083111ae2a11 | 68 | * @param[in] miso The pin to use for MISO |
saloutos | 0:083111ae2a11 | 69 | * @param[in] sclk The pin to use for SCLK |
saloutos | 0:083111ae2a11 | 70 | * @param[in] ssel The pin to use for SSEL |
saloutos | 0:083111ae2a11 | 71 | */ |
saloutos | 0:083111ae2a11 | 72 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel); |
saloutos | 0:083111ae2a11 | 73 | |
saloutos | 0:083111ae2a11 | 74 | /** Release a SPI object |
saloutos | 0:083111ae2a11 | 75 | * |
saloutos | 0:083111ae2a11 | 76 | * TODO: spi_free is currently unimplemented |
saloutos | 0:083111ae2a11 | 77 | * This will require reference counting at the C++ level to be safe |
saloutos | 0:083111ae2a11 | 78 | * |
saloutos | 0:083111ae2a11 | 79 | * Return the pins owned by the SPI object to their reset state |
saloutos | 0:083111ae2a11 | 80 | * Disable the SPI peripheral |
saloutos | 0:083111ae2a11 | 81 | * Disable the SPI clock |
saloutos | 0:083111ae2a11 | 82 | * @param[in] obj The SPI object to deinitialize |
saloutos | 0:083111ae2a11 | 83 | */ |
saloutos | 0:083111ae2a11 | 84 | void spi_free(spi_t *obj); |
saloutos | 0:083111ae2a11 | 85 | |
saloutos | 0:083111ae2a11 | 86 | /** Configure the SPI format |
saloutos | 0:083111ae2a11 | 87 | * |
saloutos | 0:083111ae2a11 | 88 | * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode. |
saloutos | 0:083111ae2a11 | 89 | * The default bit order is MSB. |
saloutos | 0:083111ae2a11 | 90 | * @param[in,out] obj The SPI object to configure |
saloutos | 0:083111ae2a11 | 91 | * @param[in] bits The number of bits per frame |
saloutos | 0:083111ae2a11 | 92 | * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) |
saloutos | 0:083111ae2a11 | 93 | * @param[in] slave Zero for master mode or non-zero for slave mode |
saloutos | 0:083111ae2a11 | 94 | */ |
saloutos | 0:083111ae2a11 | 95 | void spi_format(spi_t *obj, int bits, int mode, int slave); |
saloutos | 0:083111ae2a11 | 96 | |
saloutos | 0:083111ae2a11 | 97 | /** Set the SPI baud rate |
saloutos | 0:083111ae2a11 | 98 | * |
saloutos | 0:083111ae2a11 | 99 | * Actual frequency may differ from the desired frequency due to available dividers and bus clock |
saloutos | 0:083111ae2a11 | 100 | * Configures the SPI peripheral's baud rate |
saloutos | 0:083111ae2a11 | 101 | * @param[in,out] obj The SPI object to configure |
saloutos | 0:083111ae2a11 | 102 | * @param[in] hz The baud rate in Hz |
saloutos | 0:083111ae2a11 | 103 | */ |
saloutos | 0:083111ae2a11 | 104 | void spi_frequency(spi_t *obj, int hz); |
saloutos | 0:083111ae2a11 | 105 | |
saloutos | 0:083111ae2a11 | 106 | /**@}*/ |
saloutos | 0:083111ae2a11 | 107 | /** |
saloutos | 0:083111ae2a11 | 108 | * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer |
saloutos | 0:083111ae2a11 | 109 | * @{ |
saloutos | 0:083111ae2a11 | 110 | */ |
saloutos | 0:083111ae2a11 | 111 | |
saloutos | 0:083111ae2a11 | 112 | /** Write a byte out in master mode and receive a value |
saloutos | 0:083111ae2a11 | 113 | * |
saloutos | 0:083111ae2a11 | 114 | * @param[in] obj The SPI peripheral to use for sending |
saloutos | 0:083111ae2a11 | 115 | * @param[in] value The value to send |
saloutos | 0:083111ae2a11 | 116 | * @return Returns the value received during send |
saloutos | 0:083111ae2a11 | 117 | */ |
saloutos | 0:083111ae2a11 | 118 | int spi_master_write(spi_t *obj, int value); |
saloutos | 0:083111ae2a11 | 119 | |
saloutos | 0:083111ae2a11 | 120 | /** Write a block out in master mode and receive a value |
saloutos | 0:083111ae2a11 | 121 | * |
saloutos | 0:083111ae2a11 | 122 | * The total number of bytes sent and recieved will be the maximum of |
saloutos | 0:083111ae2a11 | 123 | * tx_length and rx_length. The bytes written will be padded with the |
saloutos | 0:083111ae2a11 | 124 | * value 0xff. |
saloutos | 0:083111ae2a11 | 125 | * |
saloutos | 0:083111ae2a11 | 126 | * @param[in] obj The SPI peripheral to use for sending |
saloutos | 0:083111ae2a11 | 127 | * @param[in] tx_buffer Pointer to the byte-array of data to write to the device |
saloutos | 0:083111ae2a11 | 128 | * @param[in] tx_length Number of bytes to write, may be zero |
saloutos | 0:083111ae2a11 | 129 | * @param[in] rx_buffer Pointer to the byte-array of data to read from the device |
saloutos | 0:083111ae2a11 | 130 | * @param[in] rx_length Number of bytes to read, may be zero |
saloutos | 0:083111ae2a11 | 131 | * @param[in] write_fill Default data transmitted while performing a read |
saloutos | 0:083111ae2a11 | 132 | * @returns |
saloutos | 0:083111ae2a11 | 133 | * The number of bytes written and read from the device. This is |
saloutos | 0:083111ae2a11 | 134 | * maximum of tx_length and rx_length. |
saloutos | 0:083111ae2a11 | 135 | */ |
saloutos | 0:083111ae2a11 | 136 | int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill); |
saloutos | 0:083111ae2a11 | 137 | |
saloutos | 0:083111ae2a11 | 138 | /** Check if a value is available to read |
saloutos | 0:083111ae2a11 | 139 | * |
saloutos | 0:083111ae2a11 | 140 | * @param[in] obj The SPI peripheral to check |
saloutos | 0:083111ae2a11 | 141 | * @return non-zero if a value is available |
saloutos | 0:083111ae2a11 | 142 | */ |
saloutos | 0:083111ae2a11 | 143 | int spi_slave_receive(spi_t *obj); |
saloutos | 0:083111ae2a11 | 144 | |
saloutos | 0:083111ae2a11 | 145 | /** Get a received value out of the SPI receive buffer in slave mode |
saloutos | 0:083111ae2a11 | 146 | * |
saloutos | 0:083111ae2a11 | 147 | * Blocks until a value is available |
saloutos | 0:083111ae2a11 | 148 | * @param[in] obj The SPI peripheral to read |
saloutos | 0:083111ae2a11 | 149 | * @return The value received |
saloutos | 0:083111ae2a11 | 150 | */ |
saloutos | 0:083111ae2a11 | 151 | int spi_slave_read(spi_t *obj); |
saloutos | 0:083111ae2a11 | 152 | |
saloutos | 0:083111ae2a11 | 153 | /** Write a value to the SPI peripheral in slave mode |
saloutos | 0:083111ae2a11 | 154 | * |
saloutos | 0:083111ae2a11 | 155 | * Blocks until the SPI peripheral can be written to |
saloutos | 0:083111ae2a11 | 156 | * @param[in] obj The SPI peripheral to write |
saloutos | 0:083111ae2a11 | 157 | * @param[in] value The value to write |
saloutos | 0:083111ae2a11 | 158 | */ |
saloutos | 0:083111ae2a11 | 159 | void spi_slave_write(spi_t *obj, int value); |
saloutos | 0:083111ae2a11 | 160 | |
saloutos | 0:083111ae2a11 | 161 | /** Checks if the specified SPI peripheral is in use |
saloutos | 0:083111ae2a11 | 162 | * |
saloutos | 0:083111ae2a11 | 163 | * @param[in] obj The SPI peripheral to check |
saloutos | 0:083111ae2a11 | 164 | * @return non-zero if the peripheral is currently transmitting |
saloutos | 0:083111ae2a11 | 165 | */ |
saloutos | 0:083111ae2a11 | 166 | int spi_busy(spi_t *obj); |
saloutos | 0:083111ae2a11 | 167 | |
saloutos | 0:083111ae2a11 | 168 | /** Get the module number |
saloutos | 0:083111ae2a11 | 169 | * |
saloutos | 0:083111ae2a11 | 170 | * @param[in] obj The SPI peripheral to check |
saloutos | 0:083111ae2a11 | 171 | * @return The module number |
saloutos | 0:083111ae2a11 | 172 | */ |
saloutos | 0:083111ae2a11 | 173 | uint8_t spi_get_module(spi_t *obj); |
saloutos | 0:083111ae2a11 | 174 | |
saloutos | 0:083111ae2a11 | 175 | /**@}*/ |
saloutos | 0:083111ae2a11 | 176 | |
saloutos | 0:083111ae2a11 | 177 | #if DEVICE_SPI_ASYNCH |
saloutos | 0:083111ae2a11 | 178 | /** |
saloutos | 0:083111ae2a11 | 179 | * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer |
saloutos | 0:083111ae2a11 | 180 | * @{ |
saloutos | 0:083111ae2a11 | 181 | */ |
saloutos | 0:083111ae2a11 | 182 | |
saloutos | 0:083111ae2a11 | 183 | /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff |
saloutos | 0:083111ae2a11 | 184 | * |
saloutos | 0:083111ae2a11 | 185 | * @param[in] obj The SPI object that holds the transfer information |
saloutos | 0:083111ae2a11 | 186 | * @param[in] tx The transmit buffer |
saloutos | 0:083111ae2a11 | 187 | * @param[in] tx_length The number of bytes to transmit |
saloutos | 0:083111ae2a11 | 188 | * @param[in] rx The receive buffer |
saloutos | 0:083111ae2a11 | 189 | * @param[in] rx_length The number of bytes to receive |
saloutos | 0:083111ae2a11 | 190 | * @param[in] bit_width The bit width of buffer words |
saloutos | 0:083111ae2a11 | 191 | * @param[in] event The logical OR of events to be registered |
saloutos | 0:083111ae2a11 | 192 | * @param[in] handler SPI interrupt handler |
saloutos | 0:083111ae2a11 | 193 | * @param[in] hint A suggestion for how to use DMA with this transfer |
saloutos | 0:083111ae2a11 | 194 | */ |
saloutos | 0:083111ae2a11 | 195 | void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint); |
saloutos | 0:083111ae2a11 | 196 | |
saloutos | 0:083111ae2a11 | 197 | /** The asynchronous IRQ handler |
saloutos | 0:083111ae2a11 | 198 | * |
saloutos | 0:083111ae2a11 | 199 | * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination |
saloutos | 0:083111ae2a11 | 200 | * conditions, such as buffer overflows or transfer complete. |
saloutos | 0:083111ae2a11 | 201 | * @param[in] obj The SPI object that holds the transfer information |
saloutos | 0:083111ae2a11 | 202 | * @return Event flags if a transfer termination condition was met; otherwise 0. |
saloutos | 0:083111ae2a11 | 203 | */ |
saloutos | 0:083111ae2a11 | 204 | uint32_t spi_irq_handler_asynch(spi_t *obj); |
saloutos | 0:083111ae2a11 | 205 | |
saloutos | 0:083111ae2a11 | 206 | /** Attempts to determine if the SPI peripheral is already in use |
saloutos | 0:083111ae2a11 | 207 | * |
saloutos | 0:083111ae2a11 | 208 | * If a temporary DMA channel has been allocated, peripheral is in use. |
saloutos | 0:083111ae2a11 | 209 | * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA |
saloutos | 0:083111ae2a11 | 210 | * channel were allocated. |
saloutos | 0:083111ae2a11 | 211 | * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check |
saloutos | 0:083111ae2a11 | 212 | * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if |
saloutos | 0:083111ae2a11 | 213 | * there are any bytes in the FIFOs. |
saloutos | 0:083111ae2a11 | 214 | * @param[in] obj The SPI object to check for activity |
saloutos | 0:083111ae2a11 | 215 | * @return Non-zero if the SPI port is active or zero if it is not. |
saloutos | 0:083111ae2a11 | 216 | */ |
saloutos | 0:083111ae2a11 | 217 | uint8_t spi_active(spi_t *obj); |
saloutos | 0:083111ae2a11 | 218 | |
saloutos | 0:083111ae2a11 | 219 | /** Abort an SPI transfer |
saloutos | 0:083111ae2a11 | 220 | * |
saloutos | 0:083111ae2a11 | 221 | * @param obj The SPI peripheral to stop |
saloutos | 0:083111ae2a11 | 222 | */ |
saloutos | 0:083111ae2a11 | 223 | void spi_abort_asynch(spi_t *obj); |
saloutos | 0:083111ae2a11 | 224 | |
saloutos | 0:083111ae2a11 | 225 | |
saloutos | 0:083111ae2a11 | 226 | #endif |
saloutos | 0:083111ae2a11 | 227 | |
saloutos | 0:083111ae2a11 | 228 | /**@}*/ |
saloutos | 0:083111ae2a11 | 229 | |
saloutos | 0:083111ae2a11 | 230 | #ifdef __cplusplus |
saloutos | 0:083111ae2a11 | 231 | } |
saloutos | 0:083111ae2a11 | 232 | #endif // __cplusplus |
saloutos | 0:083111ae2a11 | 233 | |
saloutos | 0:083111ae2a11 | 234 | #endif // SPI_DEVICE |
saloutos | 0:083111ae2a11 | 235 | |
saloutos | 0:083111ae2a11 | 236 | #endif // MBED_SPI_API_H |
saloutos | 0:083111ae2a11 | 237 | |
saloutos | 0:083111ae2a11 | 238 | /** @}*/ |