Elijah Stanger-Jones / mbed-dev-f303

test

targets/TARGET_STM/stm_spi_api.c@1:8a094db1347f, 2020-11-09 (annotated)

Committer:
elijahsj
Date:
Mon Nov 09 00:02:47 2020 -0500
Revision:
1:8a094db1347f
test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elijahsj 1:8a094db1347f 1 /* mbed Microcontroller Library
elijahsj 1:8a094db1347f 2 *******************************************************************************
elijahsj 1:8a094db1347f 3 * Copyright (c) 2015, STMicroelectronics
elijahsj 1:8a094db1347f 4 * All rights reserved.
elijahsj 1:8a094db1347f 5 *
elijahsj 1:8a094db1347f 6 * Redistribution and use in source and binary forms, with or without
elijahsj 1:8a094db1347f 7 * modification, are permitted provided that the following conditions are met:
elijahsj 1:8a094db1347f 8 *
elijahsj 1:8a094db1347f 9 * 1. Redistributions of source code must retain the above copyright notice,
elijahsj 1:8a094db1347f 10 * this list of conditions and the following disclaimer.
elijahsj 1:8a094db1347f 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
elijahsj 1:8a094db1347f 12 * this list of conditions and the following disclaimer in the documentation
elijahsj 1:8a094db1347f 13 * and/or other materials provided with the distribution.
elijahsj 1:8a094db1347f 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
elijahsj 1:8a094db1347f 15 * may be used to endorse or promote products derived from this software
elijahsj 1:8a094db1347f 16 * without specific prior written permission.
elijahsj 1:8a094db1347f 17 *
elijahsj 1:8a094db1347f 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elijahsj 1:8a094db1347f 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elijahsj 1:8a094db1347f 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elijahsj 1:8a094db1347f 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elijahsj 1:8a094db1347f 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elijahsj 1:8a094db1347f 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elijahsj 1:8a094db1347f 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elijahsj 1:8a094db1347f 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elijahsj 1:8a094db1347f 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elijahsj 1:8a094db1347f 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elijahsj 1:8a094db1347f 28 *******************************************************************************
elijahsj 1:8a094db1347f 29 */
elijahsj 1:8a094db1347f 30 #include "mbed_assert.h"
elijahsj 1:8a094db1347f 31 #include "mbed_error.h"
elijahsj 1:8a094db1347f 32 #include "spi_api.h"
elijahsj 1:8a094db1347f 33
elijahsj 1:8a094db1347f 34 #if DEVICE_SPI
elijahsj 1:8a094db1347f 35 #include <stdbool.h>
elijahsj 1:8a094db1347f 36 #include <math.h>
elijahsj 1:8a094db1347f 37 #include <string.h>
elijahsj 1:8a094db1347f 38 #include "cmsis.h"
elijahsj 1:8a094db1347f 39 #include "pinmap.h"
elijahsj 1:8a094db1347f 40 #include "PeripheralPins.h"
elijahsj 1:8a094db1347f 41 #include "spi_device.h"
elijahsj 1:8a094db1347f 42
elijahsj 1:8a094db1347f 43 #if DEVICE_SPI_ASYNCH
elijahsj 1:8a094db1347f 44 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi))
elijahsj 1:8a094db1347f 45 #else
elijahsj 1:8a094db1347f 46 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi))
elijahsj 1:8a094db1347f 47 #endif
elijahsj 1:8a094db1347f 48
elijahsj 1:8a094db1347f 49 #if DEVICE_SPI_ASYNCH
elijahsj 1:8a094db1347f 50 #define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
elijahsj 1:8a094db1347f 51 #else
elijahsj 1:8a094db1347f 52 #define SPI_S(obj) (( struct spi_s *)(obj))
elijahsj 1:8a094db1347f 53 #endif
elijahsj 1:8a094db1347f 54
elijahsj 1:8a094db1347f 55 #ifndef DEBUG_STDIO
elijahsj 1:8a094db1347f 56 # define DEBUG_STDIO 0
elijahsj 1:8a094db1347f 57 #endif
elijahsj 1:8a094db1347f 58
elijahsj 1:8a094db1347f 59 #if DEBUG_STDIO
elijahsj 1:8a094db1347f 60 # include <stdio.h>
elijahsj 1:8a094db1347f 61 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
elijahsj 1:8a094db1347f 62 #else
elijahsj 1:8a094db1347f 63 # define DEBUG_PRINTF(...) {}
elijahsj 1:8a094db1347f 64 #endif
elijahsj 1:8a094db1347f 65
elijahsj 1:8a094db1347f 66 /* Consider 10ms as the default timeout for sending/receving 1 byte */
elijahsj 1:8a094db1347f 67 #define TIMEOUT_1_BYTE 10
elijahsj 1:8a094db1347f 68
elijahsj 1:8a094db1347f 69 void init_spi(spi_t *obj)
elijahsj 1:8a094db1347f 70 {
elijahsj 1:8a094db1347f 71 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 72 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 73
elijahsj 1:8a094db1347f 74 __HAL_SPI_DISABLE(handle);
elijahsj 1:8a094db1347f 75
elijahsj 1:8a094db1347f 76 DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
elijahsj 1:8a094db1347f 77 if (HAL_SPI_Init(handle) != HAL_OK) {
elijahsj 1:8a094db1347f 78 error("Cannot initialize SPI");
elijahsj 1:8a094db1347f 79 }
elijahsj 1:8a094db1347f 80
elijahsj 1:8a094db1347f 81 /* In case of standard 4 wires SPI,PI can be kept enabled all time
elijahsj 1:8a094db1347f 82 * and SCK will only be generated during the write operations. But in case
elijahsj 1:8a094db1347f 83 * of 3 wires, it should be only enabled during rd/wr unitary operations,
elijahsj 1:8a094db1347f 84 * which is handled inside STM32 HAL layer.
elijahsj 1:8a094db1347f 85 */
elijahsj 1:8a094db1347f 86 if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
elijahsj 1:8a094db1347f 87 __HAL_SPI_ENABLE(handle);
elijahsj 1:8a094db1347f 88 }
elijahsj 1:8a094db1347f 89 }
elijahsj 1:8a094db1347f 90
elijahsj 1:8a094db1347f 91 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
elijahsj 1:8a094db1347f 92 {
elijahsj 1:8a094db1347f 93 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 94 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 95
elijahsj 1:8a094db1347f 96 // Determine the SPI to use
elijahsj 1:8a094db1347f 97 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
elijahsj 1:8a094db1347f 98 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
elijahsj 1:8a094db1347f 99 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
elijahsj 1:8a094db1347f 100 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
elijahsj 1:8a094db1347f 101
elijahsj 1:8a094db1347f 102 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
elijahsj 1:8a094db1347f 103 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
elijahsj 1:8a094db1347f 104
elijahsj 1:8a094db1347f 105 spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
elijahsj 1:8a094db1347f 106 MBED_ASSERT(spiobj->spi != (SPIName)NC);
elijahsj 1:8a094db1347f 107
elijahsj 1:8a094db1347f 108 #if defined SPI1_BASE
elijahsj 1:8a094db1347f 109 // Enable SPI clock
elijahsj 1:8a094db1347f 110 if (spiobj->spi == SPI_1) {
elijahsj 1:8a094db1347f 111 __HAL_RCC_SPI1_CLK_ENABLE();
elijahsj 1:8a094db1347f 112 spiobj->spiIRQ = SPI1_IRQn;
elijahsj 1:8a094db1347f 113 }
elijahsj 1:8a094db1347f 114 #endif
elijahsj 1:8a094db1347f 115
elijahsj 1:8a094db1347f 116 #if defined SPI2_BASE
elijahsj 1:8a094db1347f 117 if (spiobj->spi == SPI_2) {
elijahsj 1:8a094db1347f 118 __HAL_RCC_SPI2_CLK_ENABLE();
elijahsj 1:8a094db1347f 119 spiobj->spiIRQ = SPI2_IRQn;
elijahsj 1:8a094db1347f 120 }
elijahsj 1:8a094db1347f 121 #endif
elijahsj 1:8a094db1347f 122
elijahsj 1:8a094db1347f 123 #if defined SPI3_BASE
elijahsj 1:8a094db1347f 124 if (spiobj->spi == SPI_3) {
elijahsj 1:8a094db1347f 125 __HAL_RCC_SPI3_CLK_ENABLE();
elijahsj 1:8a094db1347f 126 spiobj->spiIRQ = SPI3_IRQn;
elijahsj 1:8a094db1347f 127 }
elijahsj 1:8a094db1347f 128 #endif
elijahsj 1:8a094db1347f 129
elijahsj 1:8a094db1347f 130 #if defined SPI4_BASE
elijahsj 1:8a094db1347f 131 if (spiobj->spi == SPI_4) {
elijahsj 1:8a094db1347f 132 __HAL_RCC_SPI4_CLK_ENABLE();
elijahsj 1:8a094db1347f 133 spiobj->spiIRQ = SPI4_IRQn;
elijahsj 1:8a094db1347f 134 }
elijahsj 1:8a094db1347f 135 #endif
elijahsj 1:8a094db1347f 136
elijahsj 1:8a094db1347f 137 #if defined SPI5_BASE
elijahsj 1:8a094db1347f 138 if (spiobj->spi == SPI_5) {
elijahsj 1:8a094db1347f 139 __HAL_RCC_SPI5_CLK_ENABLE();
elijahsj 1:8a094db1347f 140 spiobj->spiIRQ = SPI5_IRQn;
elijahsj 1:8a094db1347f 141 }
elijahsj 1:8a094db1347f 142 #endif
elijahsj 1:8a094db1347f 143
elijahsj 1:8a094db1347f 144 #if defined SPI6_BASE
elijahsj 1:8a094db1347f 145 if (spiobj->spi == SPI_6) {
elijahsj 1:8a094db1347f 146 __HAL_RCC_SPI6_CLK_ENABLE();
elijahsj 1:8a094db1347f 147 spiobj->spiIRQ = SPI6_IRQn;
elijahsj 1:8a094db1347f 148 }
elijahsj 1:8a094db1347f 149 #endif
elijahsj 1:8a094db1347f 150
elijahsj 1:8a094db1347f 151 // Configure the SPI pins
elijahsj 1:8a094db1347f 152 pinmap_pinout(mosi, PinMap_SPI_MOSI);
elijahsj 1:8a094db1347f 153 pinmap_pinout(miso, PinMap_SPI_MISO);
elijahsj 1:8a094db1347f 154 pinmap_pinout(sclk, PinMap_SPI_SCLK);
elijahsj 1:8a094db1347f 155 spiobj->pin_miso = miso;
elijahsj 1:8a094db1347f 156 spiobj->pin_mosi = mosi;
elijahsj 1:8a094db1347f 157 spiobj->pin_sclk = sclk;
elijahsj 1:8a094db1347f 158 spiobj->pin_ssel = ssel;
elijahsj 1:8a094db1347f 159 if (ssel != NC) {
elijahsj 1:8a094db1347f 160 pinmap_pinout(ssel, PinMap_SPI_SSEL);
elijahsj 1:8a094db1347f 161 } else {
elijahsj 1:8a094db1347f 162 handle->Init.NSS = SPI_NSS_SOFT;
elijahsj 1:8a094db1347f 163 }
elijahsj 1:8a094db1347f 164
elijahsj 1:8a094db1347f 165 /* Fill default value */
elijahsj 1:8a094db1347f 166 handle->Instance = SPI_INST(obj);
elijahsj 1:8a094db1347f 167 handle->Init.Mode = SPI_MODE_MASTER;
elijahsj 1:8a094db1347f 168 handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
elijahsj 1:8a094db1347f 169
elijahsj 1:8a094db1347f 170 if (miso != NC) {
elijahsj 1:8a094db1347f 171 handle->Init.Direction = SPI_DIRECTION_2LINES;
elijahsj 1:8a094db1347f 172 } else {
elijahsj 1:8a094db1347f 173 handle->Init.Direction = SPI_DIRECTION_1LINE;
elijahsj 1:8a094db1347f 174 }
elijahsj 1:8a094db1347f 175
elijahsj 1:8a094db1347f 176 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
elijahsj 1:8a094db1347f 177 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
elijahsj 1:8a094db1347f 178 handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
elijahsj 1:8a094db1347f 179 handle->Init.CRCPolynomial = 7;
elijahsj 1:8a094db1347f 180 handle->Init.DataSize = SPI_DATASIZE_8BIT;
elijahsj 1:8a094db1347f 181 handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
elijahsj 1:8a094db1347f 182 handle->Init.TIMode = SPI_TIMODE_DISABLE;
elijahsj 1:8a094db1347f 183
elijahsj 1:8a094db1347f 184 init_spi(obj);
elijahsj 1:8a094db1347f 185 }
elijahsj 1:8a094db1347f 186
elijahsj 1:8a094db1347f 187 void spi_free(spi_t *obj)
elijahsj 1:8a094db1347f 188 {
elijahsj 1:8a094db1347f 189 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 190 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 191
elijahsj 1:8a094db1347f 192 DEBUG_PRINTF("spi_free\r\n");
elijahsj 1:8a094db1347f 193
elijahsj 1:8a094db1347f 194 __HAL_SPI_DISABLE(handle);
elijahsj 1:8a094db1347f 195 HAL_SPI_DeInit(handle);
elijahsj 1:8a094db1347f 196
elijahsj 1:8a094db1347f 197 #if defined SPI1_BASE
elijahsj 1:8a094db1347f 198 // Reset SPI and disable clock
elijahsj 1:8a094db1347f 199 if (spiobj->spi == SPI_1) {
elijahsj 1:8a094db1347f 200 __HAL_RCC_SPI1_FORCE_RESET();
elijahsj 1:8a094db1347f 201 __HAL_RCC_SPI1_RELEASE_RESET();
elijahsj 1:8a094db1347f 202 __HAL_RCC_SPI1_CLK_DISABLE();
elijahsj 1:8a094db1347f 203 }
elijahsj 1:8a094db1347f 204 #endif
elijahsj 1:8a094db1347f 205 #if defined SPI2_BASE
elijahsj 1:8a094db1347f 206 if (spiobj->spi == SPI_2) {
elijahsj 1:8a094db1347f 207 __HAL_RCC_SPI2_FORCE_RESET();
elijahsj 1:8a094db1347f 208 __HAL_RCC_SPI2_RELEASE_RESET();
elijahsj 1:8a094db1347f 209 __HAL_RCC_SPI2_CLK_DISABLE();
elijahsj 1:8a094db1347f 210 }
elijahsj 1:8a094db1347f 211 #endif
elijahsj 1:8a094db1347f 212
elijahsj 1:8a094db1347f 213 #if defined SPI3_BASE
elijahsj 1:8a094db1347f 214 if (spiobj->spi == SPI_3) {
elijahsj 1:8a094db1347f 215 __HAL_RCC_SPI3_FORCE_RESET();
elijahsj 1:8a094db1347f 216 __HAL_RCC_SPI3_RELEASE_RESET();
elijahsj 1:8a094db1347f 217 __HAL_RCC_SPI3_CLK_DISABLE();
elijahsj 1:8a094db1347f 218 }
elijahsj 1:8a094db1347f 219 #endif
elijahsj 1:8a094db1347f 220
elijahsj 1:8a094db1347f 221 #if defined SPI4_BASE
elijahsj 1:8a094db1347f 222 if (spiobj->spi == SPI_4) {
elijahsj 1:8a094db1347f 223 __HAL_RCC_SPI4_FORCE_RESET();
elijahsj 1:8a094db1347f 224 __HAL_RCC_SPI4_RELEASE_RESET();
elijahsj 1:8a094db1347f 225 __HAL_RCC_SPI4_CLK_DISABLE();
elijahsj 1:8a094db1347f 226 }
elijahsj 1:8a094db1347f 227 #endif
elijahsj 1:8a094db1347f 228
elijahsj 1:8a094db1347f 229 #if defined SPI5_BASE
elijahsj 1:8a094db1347f 230 if (spiobj->spi == SPI_5) {
elijahsj 1:8a094db1347f 231 __HAL_RCC_SPI5_FORCE_RESET();
elijahsj 1:8a094db1347f 232 __HAL_RCC_SPI5_RELEASE_RESET();
elijahsj 1:8a094db1347f 233 __HAL_RCC_SPI5_CLK_DISABLE();
elijahsj 1:8a094db1347f 234 }
elijahsj 1:8a094db1347f 235 #endif
elijahsj 1:8a094db1347f 236
elijahsj 1:8a094db1347f 237 #if defined SPI6_BASE
elijahsj 1:8a094db1347f 238 if (spiobj->spi == SPI_6) {
elijahsj 1:8a094db1347f 239 __HAL_RCC_SPI6_FORCE_RESET();
elijahsj 1:8a094db1347f 240 __HAL_RCC_SPI6_RELEASE_RESET();
elijahsj 1:8a094db1347f 241 __HAL_RCC_SPI6_CLK_DISABLE();
elijahsj 1:8a094db1347f 242 }
elijahsj 1:8a094db1347f 243 #endif
elijahsj 1:8a094db1347f 244
elijahsj 1:8a094db1347f 245 // Configure GPIOs
elijahsj 1:8a094db1347f 246 pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
elijahsj 1:8a094db1347f 247 pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
elijahsj 1:8a094db1347f 248 pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
elijahsj 1:8a094db1347f 249 if (handle->Init.NSS != SPI_NSS_SOFT) {
elijahsj 1:8a094db1347f 250 pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
elijahsj 1:8a094db1347f 251 }
elijahsj 1:8a094db1347f 252 }
elijahsj 1:8a094db1347f 253
elijahsj 1:8a094db1347f 254 void spi_format(spi_t *obj, int bits, int mode, int slave)
elijahsj 1:8a094db1347f 255 {
elijahsj 1:8a094db1347f 256 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 257 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 258
elijahsj 1:8a094db1347f 259 DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
elijahsj 1:8a094db1347f 260
elijahsj 1:8a094db1347f 261 // Save new values
elijahsj 1:8a094db1347f 262 handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
elijahsj 1:8a094db1347f 263
elijahsj 1:8a094db1347f 264 switch (mode) {
elijahsj 1:8a094db1347f 265 case 0:
elijahsj 1:8a094db1347f 266 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
elijahsj 1:8a094db1347f 267 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
elijahsj 1:8a094db1347f 268 break;
elijahsj 1:8a094db1347f 269 case 1:
elijahsj 1:8a094db1347f 270 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
elijahsj 1:8a094db1347f 271 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
elijahsj 1:8a094db1347f 272 break;
elijahsj 1:8a094db1347f 273 case 2:
elijahsj 1:8a094db1347f 274 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
elijahsj 1:8a094db1347f 275 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
elijahsj 1:8a094db1347f 276 break;
elijahsj 1:8a094db1347f 277 default:
elijahsj 1:8a094db1347f 278 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
elijahsj 1:8a094db1347f 279 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
elijahsj 1:8a094db1347f 280 break;
elijahsj 1:8a094db1347f 281 }
elijahsj 1:8a094db1347f 282
elijahsj 1:8a094db1347f 283 if (handle->Init.NSS != SPI_NSS_SOFT) {
elijahsj 1:8a094db1347f 284 handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
elijahsj 1:8a094db1347f 285 }
elijahsj 1:8a094db1347f 286
elijahsj 1:8a094db1347f 287 handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
elijahsj 1:8a094db1347f 288
elijahsj 1:8a094db1347f 289 init_spi(obj);
elijahsj 1:8a094db1347f 290 }
elijahsj 1:8a094db1347f 291
elijahsj 1:8a094db1347f 292 /*
elijahsj 1:8a094db1347f 293 * Only the IP clock input is family dependant so it computed
elijahsj 1:8a094db1347f 294 * separately in spi_get_clock_freq
elijahsj 1:8a094db1347f 295 */
elijahsj 1:8a094db1347f 296 extern int spi_get_clock_freq(spi_t *obj);
elijahsj 1:8a094db1347f 297
elijahsj 1:8a094db1347f 298 static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2,
elijahsj 1:8a094db1347f 299 SPI_BAUDRATEPRESCALER_4,
elijahsj 1:8a094db1347f 300 SPI_BAUDRATEPRESCALER_8,
elijahsj 1:8a094db1347f 301 SPI_BAUDRATEPRESCALER_16,
elijahsj 1:8a094db1347f 302 SPI_BAUDRATEPRESCALER_32,
elijahsj 1:8a094db1347f 303 SPI_BAUDRATEPRESCALER_64,
elijahsj 1:8a094db1347f 304 SPI_BAUDRATEPRESCALER_128,
elijahsj 1:8a094db1347f 305 SPI_BAUDRATEPRESCALER_256};
elijahsj 1:8a094db1347f 306
elijahsj 1:8a094db1347f 307 void spi_frequency(spi_t *obj, int hz) {
elijahsj 1:8a094db1347f 308 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 309 int spi_hz = 0;
elijahsj 1:8a094db1347f 310 uint8_t prescaler_rank = 0;
elijahsj 1:8a094db1347f 311 uint8_t last_index = (sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) - 1;
elijahsj 1:8a094db1347f 312 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 313
elijahsj 1:8a094db1347f 314 /* Calculate the spi clock for prescaler_rank 0: SPI_BAUDRATEPRESCALER_2 */
elijahsj 1:8a094db1347f 315 spi_hz = spi_get_clock_freq(obj) / 2;
elijahsj 1:8a094db1347f 316
elijahsj 1:8a094db1347f 317 /* Define pre-scaler in order to get highest available frequency below requested frequency */
elijahsj 1:8a094db1347f 318 while ((spi_hz > hz) && (prescaler_rank < last_index)) {
elijahsj 1:8a094db1347f 319 spi_hz = spi_hz / 2;
elijahsj 1:8a094db1347f 320 prescaler_rank++;
elijahsj 1:8a094db1347f 321 }
elijahsj 1:8a094db1347f 322
elijahsj 1:8a094db1347f 323 /* Use the best fit pre-scaler */
elijahsj 1:8a094db1347f 324 handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank];
elijahsj 1:8a094db1347f 325
elijahsj 1:8a094db1347f 326 /* In case maximum pre-scaler still gives too high freq, raise an error */
elijahsj 1:8a094db1347f 327 if (spi_hz > hz) {
elijahsj 1:8a094db1347f 328 DEBUG_PRINTF("WARNING: lowest SPI freq (%d) higher than requested (%d)\r\n", spi_hz, hz);
elijahsj 1:8a094db1347f 329 }
elijahsj 1:8a094db1347f 330
elijahsj 1:8a094db1347f 331 DEBUG_PRINTF("spi_frequency, request:%d, select:%d\r\n", hz, spi_hz);
elijahsj 1:8a094db1347f 332
elijahsj 1:8a094db1347f 333 init_spi(obj);
elijahsj 1:8a094db1347f 334 }
elijahsj 1:8a094db1347f 335
elijahsj 1:8a094db1347f 336 static inline int ssp_readable(spi_t *obj)
elijahsj 1:8a094db1347f 337 {
elijahsj 1:8a094db1347f 338 int status;
elijahsj 1:8a094db1347f 339 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 340 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 341
elijahsj 1:8a094db1347f 342 // Check if data is received
elijahsj 1:8a094db1347f 343 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
elijahsj 1:8a094db1347f 344 return status;
elijahsj 1:8a094db1347f 345 }
elijahsj 1:8a094db1347f 346
elijahsj 1:8a094db1347f 347 static inline int ssp_writeable(spi_t *obj)
elijahsj 1:8a094db1347f 348 {
elijahsj 1:8a094db1347f 349 int status;
elijahsj 1:8a094db1347f 350 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 351 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 352
elijahsj 1:8a094db1347f 353 // Check if data is transmitted
elijahsj 1:8a094db1347f 354 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
elijahsj 1:8a094db1347f 355 return status;
elijahsj 1:8a094db1347f 356 }
elijahsj 1:8a094db1347f 357
elijahsj 1:8a094db1347f 358 static inline int ssp_busy(spi_t *obj)
elijahsj 1:8a094db1347f 359 {
elijahsj 1:8a094db1347f 360 int status;
elijahsj 1:8a094db1347f 361 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 362 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 363 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
elijahsj 1:8a094db1347f 364 return status;
elijahsj 1:8a094db1347f 365 }
elijahsj 1:8a094db1347f 366
elijahsj 1:8a094db1347f 367 int spi_master_write(spi_t *obj, int value)
elijahsj 1:8a094db1347f 368 {
elijahsj 1:8a094db1347f 369 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 370 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 371
elijahsj 1:8a094db1347f 372 if (handle->Init.Direction == SPI_DIRECTION_1LINE) {
elijahsj 1:8a094db1347f 373 return HAL_SPI_Transmit(handle, (uint8_t*)&value, 1, TIMEOUT_1_BYTE);
elijahsj 1:8a094db1347f 374 }
elijahsj 1:8a094db1347f 375
elijahsj 1:8a094db1347f 376 #if defined(LL_SPI_RX_FIFO_TH_HALF)
elijahsj 1:8a094db1347f 377 /* Configure the default data size */
elijahsj 1:8a094db1347f 378 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
elijahsj 1:8a094db1347f 379 LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_HALF);
elijahsj 1:8a094db1347f 380 } else {
elijahsj 1:8a094db1347f 381 LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_QUARTER);
elijahsj 1:8a094db1347f 382 }
elijahsj 1:8a094db1347f 383 #endif
elijahsj 1:8a094db1347f 384
elijahsj 1:8a094db1347f 385 /* Here we're using LL which means direct registers access
elijahsj 1:8a094db1347f 386 * There is no error management, so we may end up looping
elijahsj 1:8a094db1347f 387 * infinitely here in case of faulty device for insatnce,
elijahsj 1:8a094db1347f 388 * but this will increase performances significantly
elijahsj 1:8a094db1347f 389 */
elijahsj 1:8a094db1347f 390
elijahsj 1:8a094db1347f 391 /* Wait TXE flag to transmit data */
elijahsj 1:8a094db1347f 392 while (!LL_SPI_IsActiveFlag_TXE(SPI_INST(obj)));
elijahsj 1:8a094db1347f 393
elijahsj 1:8a094db1347f 394 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
elijahsj 1:8a094db1347f 395 LL_SPI_TransmitData16(SPI_INST(obj), value);
elijahsj 1:8a094db1347f 396 } else {
elijahsj 1:8a094db1347f 397 LL_SPI_TransmitData8(SPI_INST(obj), (uint8_t) value);
elijahsj 1:8a094db1347f 398 }
elijahsj 1:8a094db1347f 399
elijahsj 1:8a094db1347f 400 /* Then wait RXE flag before reading */
elijahsj 1:8a094db1347f 401 while (!LL_SPI_IsActiveFlag_RXNE(SPI_INST(obj)));
elijahsj 1:8a094db1347f 402
elijahsj 1:8a094db1347f 403 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
elijahsj 1:8a094db1347f 404 return LL_SPI_ReceiveData16(SPI_INST(obj));
elijahsj 1:8a094db1347f 405 } else {
elijahsj 1:8a094db1347f 406 return LL_SPI_ReceiveData8(SPI_INST(obj));
elijahsj 1:8a094db1347f 407 }
elijahsj 1:8a094db1347f 408 }
elijahsj 1:8a094db1347f 409
elijahsj 1:8a094db1347f 410 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
elijahsj 1:8a094db1347f 411 char *rx_buffer, int rx_length, char write_fill)
elijahsj 1:8a094db1347f 412 {
elijahsj 1:8a094db1347f 413 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 414 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 415 int total = (tx_length > rx_length) ? tx_length : rx_length;
elijahsj 1:8a094db1347f 416 int i = 0;
elijahsj 1:8a094db1347f 417 if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
elijahsj 1:8a094db1347f 418 for (i = 0; i < total; i++) {
elijahsj 1:8a094db1347f 419 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
elijahsj 1:8a094db1347f 420 char in = spi_master_write(obj, out);
elijahsj 1:8a094db1347f 421 if (i < rx_length) {
elijahsj 1:8a094db1347f 422 rx_buffer[i] = in;
elijahsj 1:8a094db1347f 423 }
elijahsj 1:8a094db1347f 424 }
elijahsj 1:8a094db1347f 425 } else {
elijahsj 1:8a094db1347f 426 /* In case of 1 WIRE only, first handle TX, then Rx */
elijahsj 1:8a094db1347f 427 if (tx_length != 0) {
elijahsj 1:8a094db1347f 428 if (HAL_OK != HAL_SPI_Transmit(handle, (uint8_t*)tx_buffer, tx_length, tx_length*TIMEOUT_1_BYTE)) {
elijahsj 1:8a094db1347f 429 /* report an error */
elijahsj 1:8a094db1347f 430 total = 0;
elijahsj 1:8a094db1347f 431 }
elijahsj 1:8a094db1347f 432 }
elijahsj 1:8a094db1347f 433 if (rx_length != 0) {
elijahsj 1:8a094db1347f 434 if (HAL_OK != HAL_SPI_Receive(handle, (uint8_t*)rx_buffer, rx_length, rx_length*TIMEOUT_1_BYTE)) {
elijahsj 1:8a094db1347f 435 /* report an error */
elijahsj 1:8a094db1347f 436 total = 0;
elijahsj 1:8a094db1347f 437 }
elijahsj 1:8a094db1347f 438 }
elijahsj 1:8a094db1347f 439 }
elijahsj 1:8a094db1347f 440
elijahsj 1:8a094db1347f 441 return total;
elijahsj 1:8a094db1347f 442 }
elijahsj 1:8a094db1347f 443
elijahsj 1:8a094db1347f 444 int spi_slave_receive(spi_t *obj)
elijahsj 1:8a094db1347f 445 {
elijahsj 1:8a094db1347f 446 return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
elijahsj 1:8a094db1347f 447 };
elijahsj 1:8a094db1347f 448
elijahsj 1:8a094db1347f 449 int spi_slave_read(spi_t *obj)
elijahsj 1:8a094db1347f 450 {
elijahsj 1:8a094db1347f 451 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 452 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 453 while (!ssp_readable(obj));
elijahsj 1:8a094db1347f 454 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
elijahsj 1:8a094db1347f 455 return LL_SPI_ReceiveData16(SPI_INST(obj));
elijahsj 1:8a094db1347f 456 } else {
elijahsj 1:8a094db1347f 457 return LL_SPI_ReceiveData8(SPI_INST(obj));
elijahsj 1:8a094db1347f 458 }
elijahsj 1:8a094db1347f 459 }
elijahsj 1:8a094db1347f 460
elijahsj 1:8a094db1347f 461 void spi_slave_write(spi_t *obj, int value)
elijahsj 1:8a094db1347f 462 {
elijahsj 1:8a094db1347f 463 SPI_TypeDef *spi = SPI_INST(obj);
elijahsj 1:8a094db1347f 464 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 465 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 466 while (!ssp_writeable(obj));
elijahsj 1:8a094db1347f 467 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
elijahsj 1:8a094db1347f 468 // Force 8-bit access to the data register
elijahsj 1:8a094db1347f 469 uint8_t *p_spi_dr = 0;
elijahsj 1:8a094db1347f 470 p_spi_dr = (uint8_t *) & (spi->DR);
elijahsj 1:8a094db1347f 471 *p_spi_dr = (uint8_t)value;
elijahsj 1:8a094db1347f 472 } else { // SPI_DATASIZE_16BIT
elijahsj 1:8a094db1347f 473 spi->DR = (uint16_t)value;
elijahsj 1:8a094db1347f 474 }
elijahsj 1:8a094db1347f 475 }
elijahsj 1:8a094db1347f 476
elijahsj 1:8a094db1347f 477 int spi_busy(spi_t *obj)
elijahsj 1:8a094db1347f 478 {
elijahsj 1:8a094db1347f 479 return ssp_busy(obj);
elijahsj 1:8a094db1347f 480 }
elijahsj 1:8a094db1347f 481
elijahsj 1:8a094db1347f 482 #ifdef DEVICE_SPI_ASYNCH
elijahsj 1:8a094db1347f 483 typedef enum {
elijahsj 1:8a094db1347f 484 SPI_TRANSFER_TYPE_NONE = 0,
elijahsj 1:8a094db1347f 485 SPI_TRANSFER_TYPE_TX = 1,
elijahsj 1:8a094db1347f 486 SPI_TRANSFER_TYPE_RX = 2,
elijahsj 1:8a094db1347f 487 SPI_TRANSFER_TYPE_TXRX = 3,
elijahsj 1:8a094db1347f 488 } transfer_type_t;
elijahsj 1:8a094db1347f 489
elijahsj 1:8a094db1347f 490
elijahsj 1:8a094db1347f 491 /// @returns the number of bytes transferred, or `0` if nothing transferred
elijahsj 1:8a094db1347f 492 static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
elijahsj 1:8a094db1347f 493 {
elijahsj 1:8a094db1347f 494 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 495 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 496 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
elijahsj 1:8a094db1347f 497 // the HAL expects number of transfers instead of number of bytes
elijahsj 1:8a094db1347f 498 // so for 16 bit transfer width the count needs to be halved
elijahsj 1:8a094db1347f 499 size_t words;
elijahsj 1:8a094db1347f 500
elijahsj 1:8a094db1347f 501 DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
elijahsj 1:8a094db1347f 502
elijahsj 1:8a094db1347f 503 obj->spi.transfer_type = transfer_type;
elijahsj 1:8a094db1347f 504
elijahsj 1:8a094db1347f 505 if (is16bit) {
elijahsj 1:8a094db1347f 506 words = length / 2;
elijahsj 1:8a094db1347f 507 } else {
elijahsj 1:8a094db1347f 508 words = length;
elijahsj 1:8a094db1347f 509 }
elijahsj 1:8a094db1347f 510
elijahsj 1:8a094db1347f 511 // enable the interrupt
elijahsj 1:8a094db1347f 512 IRQn_Type irq_n = spiobj->spiIRQ;
elijahsj 1:8a094db1347f 513 NVIC_DisableIRQ(irq_n);
elijahsj 1:8a094db1347f 514 NVIC_ClearPendingIRQ(irq_n);
elijahsj 1:8a094db1347f 515 NVIC_SetPriority(irq_n, 1);
elijahsj 1:8a094db1347f 516 NVIC_EnableIRQ(irq_n);
elijahsj 1:8a094db1347f 517
elijahsj 1:8a094db1347f 518 // enable the right hal transfer
elijahsj 1:8a094db1347f 519 int rc = 0;
elijahsj 1:8a094db1347f 520 switch(transfer_type) {
elijahsj 1:8a094db1347f 521 case SPI_TRANSFER_TYPE_TXRX:
elijahsj 1:8a094db1347f 522 rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words);
elijahsj 1:8a094db1347f 523 break;
elijahsj 1:8a094db1347f 524 case SPI_TRANSFER_TYPE_TX:
elijahsj 1:8a094db1347f 525 rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words);
elijahsj 1:8a094db1347f 526 break;
elijahsj 1:8a094db1347f 527 case SPI_TRANSFER_TYPE_RX:
elijahsj 1:8a094db1347f 528 // the receive function also "transmits" the receive buffer so in order
elijahsj 1:8a094db1347f 529 // to guarantee that 0xff is on the line, we explicitly memset it here
elijahsj 1:8a094db1347f 530 memset(rx, SPI_FILL_WORD, length);
elijahsj 1:8a094db1347f 531 rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words);
elijahsj 1:8a094db1347f 532 break;
elijahsj 1:8a094db1347f 533 default:
elijahsj 1:8a094db1347f 534 length = 0;
elijahsj 1:8a094db1347f 535 }
elijahsj 1:8a094db1347f 536
elijahsj 1:8a094db1347f 537 if (rc) {
elijahsj 1:8a094db1347f 538 DEBUG_PRINTF("SPI: RC=%u\n", rc);
elijahsj 1:8a094db1347f 539 length = 0;
elijahsj 1:8a094db1347f 540 }
elijahsj 1:8a094db1347f 541
elijahsj 1:8a094db1347f 542 return length;
elijahsj 1:8a094db1347f 543 }
elijahsj 1:8a094db1347f 544
elijahsj 1:8a094db1347f 545 // asynchronous API
elijahsj 1:8a094db1347f 546 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
elijahsj 1:8a094db1347f 547 {
elijahsj 1:8a094db1347f 548 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 549 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 550
elijahsj 1:8a094db1347f 551 // TODO: DMA usage is currently ignored
elijahsj 1:8a094db1347f 552 (void) hint;
elijahsj 1:8a094db1347f 553
elijahsj 1:8a094db1347f 554 // check which use-case we have
elijahsj 1:8a094db1347f 555 bool use_tx = (tx != NULL && tx_length > 0);
elijahsj 1:8a094db1347f 556 bool use_rx = (rx != NULL && rx_length > 0);
elijahsj 1:8a094db1347f 557 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
elijahsj 1:8a094db1347f 558
elijahsj 1:8a094db1347f 559 // don't do anything, if the buffers aren't valid
elijahsj 1:8a094db1347f 560 if (!use_tx && !use_rx)
elijahsj 1:8a094db1347f 561 return;
elijahsj 1:8a094db1347f 562
elijahsj 1:8a094db1347f 563 // copy the buffers to the SPI object
elijahsj 1:8a094db1347f 564 obj->tx_buff.buffer = (void *) tx;
elijahsj 1:8a094db1347f 565 obj->tx_buff.length = tx_length;
elijahsj 1:8a094db1347f 566 obj->tx_buff.pos = 0;
elijahsj 1:8a094db1347f 567 obj->tx_buff.width = is16bit ? 16 : 8;
elijahsj 1:8a094db1347f 568
elijahsj 1:8a094db1347f 569 obj->rx_buff.buffer = rx;
elijahsj 1:8a094db1347f 570 obj->rx_buff.length = rx_length;
elijahsj 1:8a094db1347f 571 obj->rx_buff.pos = 0;
elijahsj 1:8a094db1347f 572 obj->rx_buff.width = obj->tx_buff.width;
elijahsj 1:8a094db1347f 573
elijahsj 1:8a094db1347f 574 obj->spi.event = event;
elijahsj 1:8a094db1347f 575
elijahsj 1:8a094db1347f 576 DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
elijahsj 1:8a094db1347f 577
elijahsj 1:8a094db1347f 578 // register the thunking handler
elijahsj 1:8a094db1347f 579 IRQn_Type irq_n = spiobj->spiIRQ;
elijahsj 1:8a094db1347f 580 NVIC_SetVector(irq_n, (uint32_t)handler);
elijahsj 1:8a094db1347f 581
elijahsj 1:8a094db1347f 582 // enable the right hal transfer
elijahsj 1:8a094db1347f 583 if (use_tx && use_rx) {
elijahsj 1:8a094db1347f 584 // we cannot manage different rx / tx sizes, let's use smaller one
elijahsj 1:8a094db1347f 585 size_t size = (tx_length < rx_length)? tx_length : rx_length;
elijahsj 1:8a094db1347f 586 if(tx_length != rx_length) {
elijahsj 1:8a094db1347f 587 DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
elijahsj 1:8a094db1347f 588 obj->tx_buff.length = size;
elijahsj 1:8a094db1347f 589 obj->rx_buff.length = size;
elijahsj 1:8a094db1347f 590 }
elijahsj 1:8a094db1347f 591 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
elijahsj 1:8a094db1347f 592 } else if (use_tx) {
elijahsj 1:8a094db1347f 593 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
elijahsj 1:8a094db1347f 594 } else if (use_rx) {
elijahsj 1:8a094db1347f 595 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
elijahsj 1:8a094db1347f 596 }
elijahsj 1:8a094db1347f 597 }
elijahsj 1:8a094db1347f 598
elijahsj 1:8a094db1347f 599 inline uint32_t spi_irq_handler_asynch(spi_t *obj)
elijahsj 1:8a094db1347f 600 {
elijahsj 1:8a094db1347f 601 int event = 0;
elijahsj 1:8a094db1347f 602
elijahsj 1:8a094db1347f 603 // call the CubeF4 handler, this will update the handle
elijahsj 1:8a094db1347f 604 HAL_SPI_IRQHandler(&obj->spi.handle);
elijahsj 1:8a094db1347f 605
elijahsj 1:8a094db1347f 606 if (obj->spi.handle.State == HAL_SPI_STATE_READY) {
elijahsj 1:8a094db1347f 607 // When HAL SPI is back to READY state, check if there was an error
elijahsj 1:8a094db1347f 608 int error = obj->spi.handle.ErrorCode;
elijahsj 1:8a094db1347f 609 if(error != HAL_SPI_ERROR_NONE) {
elijahsj 1:8a094db1347f 610 // something went wrong and the transfer has definitely completed
elijahsj 1:8a094db1347f 611 event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
elijahsj 1:8a094db1347f 612
elijahsj 1:8a094db1347f 613 if (error & HAL_SPI_ERROR_OVR) {
elijahsj 1:8a094db1347f 614 // buffer overrun
elijahsj 1:8a094db1347f 615 event |= SPI_EVENT_RX_OVERFLOW;
elijahsj 1:8a094db1347f 616 }
elijahsj 1:8a094db1347f 617 } else {
elijahsj 1:8a094db1347f 618 // else we're done
elijahsj 1:8a094db1347f 619 event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
elijahsj 1:8a094db1347f 620 }
elijahsj 1:8a094db1347f 621 // enable the interrupt
elijahsj 1:8a094db1347f 622 NVIC_DisableIRQ(obj->spi.spiIRQ);
elijahsj 1:8a094db1347f 623 NVIC_ClearPendingIRQ(obj->spi.spiIRQ);
elijahsj 1:8a094db1347f 624 }
elijahsj 1:8a094db1347f 625
elijahsj 1:8a094db1347f 626
elijahsj 1:8a094db1347f 627 return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
elijahsj 1:8a094db1347f 628 }
elijahsj 1:8a094db1347f 629
elijahsj 1:8a094db1347f 630 uint8_t spi_active(spi_t *obj)
elijahsj 1:8a094db1347f 631 {
elijahsj 1:8a094db1347f 632 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 633 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 634 HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
elijahsj 1:8a094db1347f 635
elijahsj 1:8a094db1347f 636 switch(state) {
elijahsj 1:8a094db1347f 637 case HAL_SPI_STATE_RESET:
elijahsj 1:8a094db1347f 638 case HAL_SPI_STATE_READY:
elijahsj 1:8a094db1347f 639 case HAL_SPI_STATE_ERROR:
elijahsj 1:8a094db1347f 640 return 0;
elijahsj 1:8a094db1347f 641 default:
elijahsj 1:8a094db1347f 642 return 1;
elijahsj 1:8a094db1347f 643 }
elijahsj 1:8a094db1347f 644 }
elijahsj 1:8a094db1347f 645
elijahsj 1:8a094db1347f 646 void spi_abort_asynch(spi_t *obj)
elijahsj 1:8a094db1347f 647 {
elijahsj 1:8a094db1347f 648 struct spi_s *spiobj = SPI_S(obj);
elijahsj 1:8a094db1347f 649 SPI_HandleTypeDef *handle = &(spiobj->handle);
elijahsj 1:8a094db1347f 650
elijahsj 1:8a094db1347f 651 // disable interrupt
elijahsj 1:8a094db1347f 652 IRQn_Type irq_n = spiobj->spiIRQ;
elijahsj 1:8a094db1347f 653 NVIC_ClearPendingIRQ(irq_n);
elijahsj 1:8a094db1347f 654 NVIC_DisableIRQ(irq_n);
elijahsj 1:8a094db1347f 655
elijahsj 1:8a094db1347f 656 // clean-up
elijahsj 1:8a094db1347f 657 __HAL_SPI_DISABLE(handle);
elijahsj 1:8a094db1347f 658 HAL_SPI_DeInit(handle);
elijahsj 1:8a094db1347f 659 HAL_SPI_Init(handle);
elijahsj 1:8a094db1347f 660 __HAL_SPI_ENABLE(handle);
elijahsj 1:8a094db1347f 661 }
elijahsj 1:8a094db1347f 662
elijahsj 1:8a094db1347f 663 #endif //DEVICE_SPI_ASYNCH
elijahsj 1:8a094db1347f 664
elijahsj 1:8a094db1347f 665 #endif