Elijah Stanger-Jones / mbed-dev-f303

test

targets/TARGET_STM/i2c_api.c@1:8a094db1347f, 2020-11-09 (annotated)

Committer:
elijahsj
Date:
Mon Nov 09 00:02:47 2020 -0500
Revision:
1:8a094db1347f
test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elijahsj 1:8a094db1347f 1 /* mbed Microcontroller Library
elijahsj 1:8a094db1347f 2 *******************************************************************************
elijahsj 1:8a094db1347f 3 * Copyright (c) 2015, STMicroelectronics
elijahsj 1:8a094db1347f 4 * All rights reserved.
elijahsj 1:8a094db1347f 5 *
elijahsj 1:8a094db1347f 6 * Redistribution and use in source and binary forms, with or without
elijahsj 1:8a094db1347f 7 * modification, are permitted provided that the following conditions are met:
elijahsj 1:8a094db1347f 8 *
elijahsj 1:8a094db1347f 9 * 1. Redistributions of source code must retain the above copyright notice,
elijahsj 1:8a094db1347f 10 * this list of conditions and the following disclaimer.
elijahsj 1:8a094db1347f 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
elijahsj 1:8a094db1347f 12 * this list of conditions and the following disclaimer in the documentation
elijahsj 1:8a094db1347f 13 * and/or other materials provided with the distribution.
elijahsj 1:8a094db1347f 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
elijahsj 1:8a094db1347f 15 * may be used to endorse or promote products derived from this software
elijahsj 1:8a094db1347f 16 * without specific prior written permission.
elijahsj 1:8a094db1347f 17 *
elijahsj 1:8a094db1347f 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elijahsj 1:8a094db1347f 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elijahsj 1:8a094db1347f 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elijahsj 1:8a094db1347f 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elijahsj 1:8a094db1347f 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elijahsj 1:8a094db1347f 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elijahsj 1:8a094db1347f 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elijahsj 1:8a094db1347f 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elijahsj 1:8a094db1347f 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elijahsj 1:8a094db1347f 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elijahsj 1:8a094db1347f 28 *******************************************************************************
elijahsj 1:8a094db1347f 29 */
elijahsj 1:8a094db1347f 30
elijahsj 1:8a094db1347f 31
elijahsj 1:8a094db1347f 32 #include "mbed_assert.h"
elijahsj 1:8a094db1347f 33 #include "i2c_api.h"
elijahsj 1:8a094db1347f 34 #include "platform/mbed_wait_api.h"
elijahsj 1:8a094db1347f 35
elijahsj 1:8a094db1347f 36 #if DEVICE_I2C
elijahsj 1:8a094db1347f 37
elijahsj 1:8a094db1347f 38 #include "cmsis.h"
elijahsj 1:8a094db1347f 39 #include "pinmap.h"
elijahsj 1:8a094db1347f 40 #include "PeripheralPins.h"
elijahsj 1:8a094db1347f 41 #include "i2c_device.h" // family specific defines
elijahsj 1:8a094db1347f 42
elijahsj 1:8a094db1347f 43 #ifndef DEBUG_STDIO
elijahsj 1:8a094db1347f 44 # define DEBUG_STDIO 0
elijahsj 1:8a094db1347f 45 #endif
elijahsj 1:8a094db1347f 46
elijahsj 1:8a094db1347f 47 #if DEBUG_STDIO
elijahsj 1:8a094db1347f 48 # include <stdio.h>
elijahsj 1:8a094db1347f 49 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
elijahsj 1:8a094db1347f 50 #else
elijahsj 1:8a094db1347f 51 # define DEBUG_PRINTF(...) {}
elijahsj 1:8a094db1347f 52 #endif
elijahsj 1:8a094db1347f 53
elijahsj 1:8a094db1347f 54 #if DEVICE_I2C_ASYNCH
elijahsj 1:8a094db1347f 55 #define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
elijahsj 1:8a094db1347f 56 #else
elijahsj 1:8a094db1347f 57 #define I2C_S(obj) (struct i2c_s *) (obj)
elijahsj 1:8a094db1347f 58 #endif
elijahsj 1:8a094db1347f 59
elijahsj 1:8a094db1347f 60 /* Family specific description for I2C */
elijahsj 1:8a094db1347f 61 #define I2C_NUM (5)
elijahsj 1:8a094db1347f 62 static I2C_HandleTypeDef* i2c_handles[I2C_NUM];
elijahsj 1:8a094db1347f 63
elijahsj 1:8a094db1347f 64 /* Timeout values are based on core clock and I2C clock.
elijahsj 1:8a094db1347f 65 The BYTE_TIMEOUT is computed as twice the number of cycles it would
elijahsj 1:8a094db1347f 66 take to send 10 bits over I2C. Most Flags should take less than that.
elijahsj 1:8a094db1347f 67 This is for immediate FLAG or ACK check.
elijahsj 1:8a094db1347f 68 */
elijahsj 1:8a094db1347f 69 #define BYTE_TIMEOUT ((SystemCoreClock / obj_s->hz) * 2 * 10)
elijahsj 1:8a094db1347f 70 /* Timeout values based on I2C clock.
elijahsj 1:8a094db1347f 71 The BYTE_TIMEOUT_US is computed as 3x the time in us it would
elijahsj 1:8a094db1347f 72 take to send 10 bits over I2C. Most Flags should take less than that.
elijahsj 1:8a094db1347f 73 This is for complete transfers check.
elijahsj 1:8a094db1347f 74 */
elijahsj 1:8a094db1347f 75 #define BYTE_TIMEOUT_US ((SystemCoreClock / obj_s->hz) * 3 * 10)
elijahsj 1:8a094db1347f 76 /* Timeout values for flags and events waiting loops. These timeouts are
elijahsj 1:8a094db1347f 77 not based on accurate values, they just guarantee that the application will
elijahsj 1:8a094db1347f 78 not remain stuck if the I2C communication is corrupted.
elijahsj 1:8a094db1347f 79 */
elijahsj 1:8a094db1347f 80 #define FLAG_TIMEOUT ((int)0x1000)
elijahsj 1:8a094db1347f 81
elijahsj 1:8a094db1347f 82 /* GENERIC INIT and HELPERS FUNCTIONS */
elijahsj 1:8a094db1347f 83
elijahsj 1:8a094db1347f 84 #if defined(I2C1_BASE)
elijahsj 1:8a094db1347f 85 static void i2c1_irq(void)
elijahsj 1:8a094db1347f 86 {
elijahsj 1:8a094db1347f 87 I2C_HandleTypeDef * handle = i2c_handles[0];
elijahsj 1:8a094db1347f 88 HAL_I2C_EV_IRQHandler(handle);
elijahsj 1:8a094db1347f 89 HAL_I2C_ER_IRQHandler(handle);
elijahsj 1:8a094db1347f 90 }
elijahsj 1:8a094db1347f 91 #endif
elijahsj 1:8a094db1347f 92 #if defined(I2C2_BASE)
elijahsj 1:8a094db1347f 93 static void i2c2_irq(void)
elijahsj 1:8a094db1347f 94 {
elijahsj 1:8a094db1347f 95 I2C_HandleTypeDef * handle = i2c_handles[1];
elijahsj 1:8a094db1347f 96 HAL_I2C_EV_IRQHandler(handle);
elijahsj 1:8a094db1347f 97 HAL_I2C_ER_IRQHandler(handle);
elijahsj 1:8a094db1347f 98 }
elijahsj 1:8a094db1347f 99 #endif
elijahsj 1:8a094db1347f 100 #if defined(I2C3_BASE)
elijahsj 1:8a094db1347f 101 static void i2c3_irq(void)
elijahsj 1:8a094db1347f 102 {
elijahsj 1:8a094db1347f 103 I2C_HandleTypeDef * handle = i2c_handles[2];
elijahsj 1:8a094db1347f 104 HAL_I2C_EV_IRQHandler(handle);
elijahsj 1:8a094db1347f 105 HAL_I2C_ER_IRQHandler(handle);
elijahsj 1:8a094db1347f 106 }
elijahsj 1:8a094db1347f 107 #endif
elijahsj 1:8a094db1347f 108 #if defined(I2C4_BASE)
elijahsj 1:8a094db1347f 109 static void i2c4_irq(void)
elijahsj 1:8a094db1347f 110 {
elijahsj 1:8a094db1347f 111 I2C_HandleTypeDef * handle = i2c_handles[3];
elijahsj 1:8a094db1347f 112 HAL_I2C_EV_IRQHandler(handle);
elijahsj 1:8a094db1347f 113 HAL_I2C_ER_IRQHandler(handle);
elijahsj 1:8a094db1347f 114 }
elijahsj 1:8a094db1347f 115 #endif
elijahsj 1:8a094db1347f 116 #if defined(FMPI2C1_BASE)
elijahsj 1:8a094db1347f 117 static void i2c5_irq(void)
elijahsj 1:8a094db1347f 118 {
elijahsj 1:8a094db1347f 119 I2C_HandleTypeDef * handle = i2c_handles[4];
elijahsj 1:8a094db1347f 120 HAL_I2C_EV_IRQHandler(handle);
elijahsj 1:8a094db1347f 121 HAL_I2C_ER_IRQHandler(handle);
elijahsj 1:8a094db1347f 122 }
elijahsj 1:8a094db1347f 123 #endif
elijahsj 1:8a094db1347f 124
elijahsj 1:8a094db1347f 125 void i2c_ev_err_enable(i2c_t *obj, uint32_t handler) {
elijahsj 1:8a094db1347f 126 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 127 IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
elijahsj 1:8a094db1347f 128 IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
elijahsj 1:8a094db1347f 129 /* default prio in master case is set to 2 */
elijahsj 1:8a094db1347f 130 uint32_t prio = 2;
elijahsj 1:8a094db1347f 131
elijahsj 1:8a094db1347f 132 /* Set up ITs using IRQ and handler tables */
elijahsj 1:8a094db1347f 133 NVIC_SetVector(irq_event_n, handler);
elijahsj 1:8a094db1347f 134 NVIC_SetVector(irq_error_n, handler);
elijahsj 1:8a094db1347f 135
elijahsj 1:8a094db1347f 136 #if DEVICE_I2CSLAVE
elijahsj 1:8a094db1347f 137 /* Set higher priority to slave device than master.
elijahsj 1:8a094db1347f 138 * In case a device makes use of both master and slave, the
elijahsj 1:8a094db1347f 139 * slave needs higher responsiveness.
elijahsj 1:8a094db1347f 140 */
elijahsj 1:8a094db1347f 141 if (obj_s->slave) {
elijahsj 1:8a094db1347f 142 prio = 1;
elijahsj 1:8a094db1347f 143 }
elijahsj 1:8a094db1347f 144 #endif
elijahsj 1:8a094db1347f 145
elijahsj 1:8a094db1347f 146 NVIC_SetPriority(irq_event_n, prio);
elijahsj 1:8a094db1347f 147 NVIC_SetPriority(irq_error_n, prio);
elijahsj 1:8a094db1347f 148 NVIC_EnableIRQ(irq_event_n);
elijahsj 1:8a094db1347f 149 NVIC_EnableIRQ(irq_error_n);
elijahsj 1:8a094db1347f 150 }
elijahsj 1:8a094db1347f 151
elijahsj 1:8a094db1347f 152 void i2c_ev_err_disable(i2c_t *obj) {
elijahsj 1:8a094db1347f 153 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 154 IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
elijahsj 1:8a094db1347f 155 IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
elijahsj 1:8a094db1347f 156
elijahsj 1:8a094db1347f 157 HAL_NVIC_DisableIRQ(irq_event_n);
elijahsj 1:8a094db1347f 158 HAL_NVIC_DisableIRQ(irq_error_n);
elijahsj 1:8a094db1347f 159 }
elijahsj 1:8a094db1347f 160
elijahsj 1:8a094db1347f 161 uint32_t i2c_get_irq_handler(i2c_t *obj)
elijahsj 1:8a094db1347f 162 {
elijahsj 1:8a094db1347f 163 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 164 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 165 uint32_t handler = 0;
elijahsj 1:8a094db1347f 166
elijahsj 1:8a094db1347f 167 switch (obj_s->index) {
elijahsj 1:8a094db1347f 168 #if defined(I2C1_BASE)
elijahsj 1:8a094db1347f 169 case 0:
elijahsj 1:8a094db1347f 170 handler = (uint32_t)&i2c1_irq;
elijahsj 1:8a094db1347f 171 break;
elijahsj 1:8a094db1347f 172 #endif
elijahsj 1:8a094db1347f 173 #if defined(I2C2_BASE)
elijahsj 1:8a094db1347f 174 case 1:
elijahsj 1:8a094db1347f 175 handler = (uint32_t)&i2c2_irq;
elijahsj 1:8a094db1347f 176 break;
elijahsj 1:8a094db1347f 177 #endif
elijahsj 1:8a094db1347f 178 #if defined(I2C3_BASE)
elijahsj 1:8a094db1347f 179 case 2:
elijahsj 1:8a094db1347f 180 handler = (uint32_t)&i2c3_irq;
elijahsj 1:8a094db1347f 181 break;
elijahsj 1:8a094db1347f 182 #endif
elijahsj 1:8a094db1347f 183 #if defined(I2C4_BASE)
elijahsj 1:8a094db1347f 184 case 3:
elijahsj 1:8a094db1347f 185 handler = (uint32_t)&i2c4_irq;
elijahsj 1:8a094db1347f 186 break;
elijahsj 1:8a094db1347f 187 #endif
elijahsj 1:8a094db1347f 188 #if defined(FMPI2C1_BASE)
elijahsj 1:8a094db1347f 189 case 4:
elijahsj 1:8a094db1347f 190 handler = (uint32_t)&i2c5_irq;
elijahsj 1:8a094db1347f 191 break;
elijahsj 1:8a094db1347f 192 #endif
elijahsj 1:8a094db1347f 193 }
elijahsj 1:8a094db1347f 194
elijahsj 1:8a094db1347f 195 i2c_handles[obj_s->index] = handle;
elijahsj 1:8a094db1347f 196 return handler;
elijahsj 1:8a094db1347f 197 }
elijahsj 1:8a094db1347f 198
elijahsj 1:8a094db1347f 199 void i2c_hw_reset(i2c_t *obj) {
elijahsj 1:8a094db1347f 200 int timeout;
elijahsj 1:8a094db1347f 201 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 202 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 203
elijahsj 1:8a094db1347f 204 handle->Instance = (I2C_TypeDef *)(obj_s->i2c);
elijahsj 1:8a094db1347f 205
elijahsj 1:8a094db1347f 206 // wait before reset
elijahsj 1:8a094db1347f 207 timeout = BYTE_TIMEOUT;
elijahsj 1:8a094db1347f 208 while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
elijahsj 1:8a094db1347f 209 #if defined I2C1_BASE
elijahsj 1:8a094db1347f 210 if (obj_s->i2c == I2C_1) {
elijahsj 1:8a094db1347f 211 __HAL_RCC_I2C1_FORCE_RESET();
elijahsj 1:8a094db1347f 212 __HAL_RCC_I2C1_RELEASE_RESET();
elijahsj 1:8a094db1347f 213 }
elijahsj 1:8a094db1347f 214 #endif
elijahsj 1:8a094db1347f 215 #if defined I2C2_BASE
elijahsj 1:8a094db1347f 216 if (obj_s->i2c == I2C_2) {
elijahsj 1:8a094db1347f 217 __HAL_RCC_I2C2_FORCE_RESET();
elijahsj 1:8a094db1347f 218 __HAL_RCC_I2C2_RELEASE_RESET();
elijahsj 1:8a094db1347f 219 }
elijahsj 1:8a094db1347f 220 #endif
elijahsj 1:8a094db1347f 221 #if defined I2C3_BASE
elijahsj 1:8a094db1347f 222 if (obj_s->i2c == I2C_3) {
elijahsj 1:8a094db1347f 223 __HAL_RCC_I2C3_FORCE_RESET();
elijahsj 1:8a094db1347f 224 __HAL_RCC_I2C3_RELEASE_RESET();
elijahsj 1:8a094db1347f 225 }
elijahsj 1:8a094db1347f 226 #endif
elijahsj 1:8a094db1347f 227 #if defined I2C4_BASE
elijahsj 1:8a094db1347f 228 if (obj_s->i2c == I2C_4) {
elijahsj 1:8a094db1347f 229 __HAL_RCC_I2C4_FORCE_RESET();
elijahsj 1:8a094db1347f 230 __HAL_RCC_I2C4_RELEASE_RESET();
elijahsj 1:8a094db1347f 231 }
elijahsj 1:8a094db1347f 232 #endif
elijahsj 1:8a094db1347f 233 #if defined FMPI2C1_BASE
elijahsj 1:8a094db1347f 234 if (obj_s->i2c == FMPI2C_1) {
elijahsj 1:8a094db1347f 235 __HAL_RCC_FMPI2C1_FORCE_RESET();
elijahsj 1:8a094db1347f 236 __HAL_RCC_FMPI2C1_RELEASE_RESET();
elijahsj 1:8a094db1347f 237 }
elijahsj 1:8a094db1347f 238 #endif
elijahsj 1:8a094db1347f 239 }
elijahsj 1:8a094db1347f 240
elijahsj 1:8a094db1347f 241 void i2c_sw_reset(i2c_t *obj)
elijahsj 1:8a094db1347f 242 {
elijahsj 1:8a094db1347f 243 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 244 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 245 /* SW reset procedure:
elijahsj 1:8a094db1347f 246 * PE must be kept low during at least 3 APB clock cycles
elijahsj 1:8a094db1347f 247 * in order to perform the software reset.
elijahsj 1:8a094db1347f 248 * This is ensured by writing the following software sequence:
elijahsj 1:8a094db1347f 249 * - Write PE=0
elijahsj 1:8a094db1347f 250 * - Check PE=0
elijahsj 1:8a094db1347f 251 * - Write PE=1.
elijahsj 1:8a094db1347f 252 */
elijahsj 1:8a094db1347f 253 handle->Instance->CR1 &= ~I2C_CR1_PE;
elijahsj 1:8a094db1347f 254 while(handle->Instance->CR1 & I2C_CR1_PE);
elijahsj 1:8a094db1347f 255 handle->Instance->CR1 |= I2C_CR1_PE;
elijahsj 1:8a094db1347f 256 }
elijahsj 1:8a094db1347f 257
elijahsj 1:8a094db1347f 258 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
elijahsj 1:8a094db1347f 259
elijahsj 1:8a094db1347f 260 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 261
elijahsj 1:8a094db1347f 262 // Determine the I2C to use
elijahsj 1:8a094db1347f 263 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
elijahsj 1:8a094db1347f 264 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
elijahsj 1:8a094db1347f 265 obj_s->sda = sda;
elijahsj 1:8a094db1347f 266 obj_s->scl = scl;
elijahsj 1:8a094db1347f 267
elijahsj 1:8a094db1347f 268 obj_s->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
elijahsj 1:8a094db1347f 269 MBED_ASSERT(obj_s->i2c != (I2CName)NC);
elijahsj 1:8a094db1347f 270
elijahsj 1:8a094db1347f 271 #if defined I2C1_BASE
elijahsj 1:8a094db1347f 272 // Enable I2C1 clock and pinout if not done
elijahsj 1:8a094db1347f 273 if (obj_s->i2c == I2C_1) {
elijahsj 1:8a094db1347f 274 obj_s->index = 0;
elijahsj 1:8a094db1347f 275 __HAL_RCC_I2C1_CLK_ENABLE();
elijahsj 1:8a094db1347f 276 // Configure I2C pins
elijahsj 1:8a094db1347f 277 pinmap_pinout(sda, PinMap_I2C_SDA);
elijahsj 1:8a094db1347f 278 pinmap_pinout(scl, PinMap_I2C_SCL);
elijahsj 1:8a094db1347f 279 pin_mode(sda, OpenDrainPullUp);
elijahsj 1:8a094db1347f 280 pin_mode(scl, OpenDrainPullUp);
elijahsj 1:8a094db1347f 281 obj_s->event_i2cIRQ = I2C1_EV_IRQn;
elijahsj 1:8a094db1347f 282 obj_s->error_i2cIRQ = I2C1_ER_IRQn;
elijahsj 1:8a094db1347f 283 }
elijahsj 1:8a094db1347f 284 #endif
elijahsj 1:8a094db1347f 285 #if defined I2C2_BASE
elijahsj 1:8a094db1347f 286 // Enable I2C2 clock and pinout if not done
elijahsj 1:8a094db1347f 287 if (obj_s->i2c == I2C_2) {
elijahsj 1:8a094db1347f 288 obj_s->index = 1;
elijahsj 1:8a094db1347f 289 __HAL_RCC_I2C2_CLK_ENABLE();
elijahsj 1:8a094db1347f 290 // Configure I2C pins
elijahsj 1:8a094db1347f 291 pinmap_pinout(sda, PinMap_I2C_SDA);
elijahsj 1:8a094db1347f 292 pinmap_pinout(scl, PinMap_I2C_SCL);
elijahsj 1:8a094db1347f 293 pin_mode(sda, OpenDrainPullUp);
elijahsj 1:8a094db1347f 294 pin_mode(scl, OpenDrainPullUp);
elijahsj 1:8a094db1347f 295 obj_s->event_i2cIRQ = I2C2_EV_IRQn;
elijahsj 1:8a094db1347f 296 obj_s->error_i2cIRQ = I2C2_ER_IRQn;
elijahsj 1:8a094db1347f 297 }
elijahsj 1:8a094db1347f 298 #endif
elijahsj 1:8a094db1347f 299 #if defined I2C3_BASE
elijahsj 1:8a094db1347f 300 // Enable I2C3 clock and pinout if not done
elijahsj 1:8a094db1347f 301 if (obj_s->i2c == I2C_3) {
elijahsj 1:8a094db1347f 302 obj_s->index = 2;
elijahsj 1:8a094db1347f 303 __HAL_RCC_I2C3_CLK_ENABLE();
elijahsj 1:8a094db1347f 304 // Configure I2C pins
elijahsj 1:8a094db1347f 305 pinmap_pinout(sda, PinMap_I2C_SDA);
elijahsj 1:8a094db1347f 306 pinmap_pinout(scl, PinMap_I2C_SCL);
elijahsj 1:8a094db1347f 307 pin_mode(sda, OpenDrainPullUp);
elijahsj 1:8a094db1347f 308 pin_mode(scl, OpenDrainPullUp);
elijahsj 1:8a094db1347f 309 obj_s->event_i2cIRQ = I2C3_EV_IRQn;
elijahsj 1:8a094db1347f 310 obj_s->error_i2cIRQ = I2C3_ER_IRQn;
elijahsj 1:8a094db1347f 311 }
elijahsj 1:8a094db1347f 312 #endif
elijahsj 1:8a094db1347f 313 #if defined I2C4_BASE
elijahsj 1:8a094db1347f 314 // Enable I2C3 clock and pinout if not done
elijahsj 1:8a094db1347f 315 if (obj_s->i2c == I2C_4) {
elijahsj 1:8a094db1347f 316 obj_s->index = 3;
elijahsj 1:8a094db1347f 317 __HAL_RCC_I2C4_CLK_ENABLE();
elijahsj 1:8a094db1347f 318 // Configure I2C pins
elijahsj 1:8a094db1347f 319 pinmap_pinout(sda, PinMap_I2C_SDA);
elijahsj 1:8a094db1347f 320 pinmap_pinout(scl, PinMap_I2C_SCL);
elijahsj 1:8a094db1347f 321 pin_mode(sda, OpenDrainPullUp);
elijahsj 1:8a094db1347f 322 pin_mode(scl, OpenDrainPullUp);
elijahsj 1:8a094db1347f 323 obj_s->event_i2cIRQ = I2C4_EV_IRQn;
elijahsj 1:8a094db1347f 324 obj_s->error_i2cIRQ = I2C4_ER_IRQn;
elijahsj 1:8a094db1347f 325 }
elijahsj 1:8a094db1347f 326 #endif
elijahsj 1:8a094db1347f 327 #if defined FMPI2C1_BASE
elijahsj 1:8a094db1347f 328 // Enable I2C3 clock and pinout if not done
elijahsj 1:8a094db1347f 329 if (obj_s->i2c == FMPI2C_1) {
elijahsj 1:8a094db1347f 330 obj_s->index = 4;
elijahsj 1:8a094db1347f 331 __HAL_RCC_FMPI2C1_CLK_ENABLE();
elijahsj 1:8a094db1347f 332 // Configure I2C pins
elijahsj 1:8a094db1347f 333 pinmap_pinout(sda, PinMap_I2C_SDA);
elijahsj 1:8a094db1347f 334 pinmap_pinout(scl, PinMap_I2C_SCL);
elijahsj 1:8a094db1347f 335 pin_mode(sda, OpenDrainPullUp);
elijahsj 1:8a094db1347f 336 pin_mode(scl, OpenDrainPullUp);
elijahsj 1:8a094db1347f 337 obj_s->event_i2cIRQ = FMPI2C1_EV_IRQn;
elijahsj 1:8a094db1347f 338 obj_s->error_i2cIRQ = FMPI2C1_ER_IRQn;
elijahsj 1:8a094db1347f 339 }
elijahsj 1:8a094db1347f 340 #endif
elijahsj 1:8a094db1347f 341
elijahsj 1:8a094db1347f 342 // I2C configuration
elijahsj 1:8a094db1347f 343 // Default hz value used for timeout computation
elijahsj 1:8a094db1347f 344 if(!obj_s->hz)
elijahsj 1:8a094db1347f 345 obj_s->hz = 100000; // 100 kHz per default
elijahsj 1:8a094db1347f 346
elijahsj 1:8a094db1347f 347 // Reset to clear pending flags if any
elijahsj 1:8a094db1347f 348 i2c_hw_reset(obj);
elijahsj 1:8a094db1347f 349 i2c_frequency(obj, obj_s->hz );
elijahsj 1:8a094db1347f 350
elijahsj 1:8a094db1347f 351 #if DEVICE_I2CSLAVE
elijahsj 1:8a094db1347f 352 // I2C master by default
elijahsj 1:8a094db1347f 353 obj_s->slave = 0;
elijahsj 1:8a094db1347f 354 obj_s->pending_slave_tx_master_rx = 0;
elijahsj 1:8a094db1347f 355 obj_s->pending_slave_rx_maxter_tx = 0;
elijahsj 1:8a094db1347f 356 #endif
elijahsj 1:8a094db1347f 357
elijahsj 1:8a094db1347f 358 // I2C Xfer operation init
elijahsj 1:8a094db1347f 359 obj_s->event = 0;
elijahsj 1:8a094db1347f 360 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
elijahsj 1:8a094db1347f 361 #ifdef I2C_IP_VERSION_V2
elijahsj 1:8a094db1347f 362 obj_s->pending_start = 0;
elijahsj 1:8a094db1347f 363 #endif
elijahsj 1:8a094db1347f 364 }
elijahsj 1:8a094db1347f 365
elijahsj 1:8a094db1347f 366 void i2c_frequency(i2c_t *obj, int hz)
elijahsj 1:8a094db1347f 367 {
elijahsj 1:8a094db1347f 368 int timeout;
elijahsj 1:8a094db1347f 369 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 370 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 371
elijahsj 1:8a094db1347f 372 // wait before init
elijahsj 1:8a094db1347f 373 timeout = BYTE_TIMEOUT;
elijahsj 1:8a094db1347f 374 while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
elijahsj 1:8a094db1347f 375
elijahsj 1:8a094db1347f 376 #ifdef I2C_IP_VERSION_V1
elijahsj 1:8a094db1347f 377 handle->Init.ClockSpeed = hz;
elijahsj 1:8a094db1347f 378 handle->Init.DutyCycle = I2C_DUTYCYCLE_2;
elijahsj 1:8a094db1347f 379 #endif
elijahsj 1:8a094db1347f 380 #ifdef I2C_IP_VERSION_V2
elijahsj 1:8a094db1347f 381 /* Only predefined timing for below frequencies are supported */
elijahsj 1:8a094db1347f 382 MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
elijahsj 1:8a094db1347f 383 handle->Init.Timing = get_i2c_timing(hz);
elijahsj 1:8a094db1347f 384
elijahsj 1:8a094db1347f 385 // Enable the Fast Mode Plus capability
elijahsj 1:8a094db1347f 386 if (hz == 1000000) {
elijahsj 1:8a094db1347f 387 #if defined(I2C1_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C1)
elijahsj 1:8a094db1347f 388 if (obj_s->i2c == I2C_1) {
elijahsj 1:8a094db1347f 389 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C1);
elijahsj 1:8a094db1347f 390 }
elijahsj 1:8a094db1347f 391 #endif
elijahsj 1:8a094db1347f 392 #if defined(I2C2_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C2)
elijahsj 1:8a094db1347f 393 if (obj_s->i2c == I2C_2) {
elijahsj 1:8a094db1347f 394 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C2);
elijahsj 1:8a094db1347f 395 }
elijahsj 1:8a094db1347f 396 #endif
elijahsj 1:8a094db1347f 397 #if defined(I2C3_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C3)
elijahsj 1:8a094db1347f 398 if (obj_s->i2c == I2C_3) {
elijahsj 1:8a094db1347f 399 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C3);
elijahsj 1:8a094db1347f 400 }
elijahsj 1:8a094db1347f 401 #endif
elijahsj 1:8a094db1347f 402 #if defined(I2C4_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C4)
elijahsj 1:8a094db1347f 403 if (obj_s->i2c == I2C_4) {
elijahsj 1:8a094db1347f 404 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C4);
elijahsj 1:8a094db1347f 405 }
elijahsj 1:8a094db1347f 406 #endif
elijahsj 1:8a094db1347f 407 }
elijahsj 1:8a094db1347f 408 #endif //I2C_IP_VERSION_V2
elijahsj 1:8a094db1347f 409
elijahsj 1:8a094db1347f 410 /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
elijahsj 1:8a094db1347f 411 #if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG)
elijahsj 1:8a094db1347f 412 if (obj_s->i2c == I2C_1) {
elijahsj 1:8a094db1347f 413 __HAL_RCC_I2C1_CONFIG(I2CAPI_I2C1_CLKSRC);
elijahsj 1:8a094db1347f 414 }
elijahsj 1:8a094db1347f 415 #endif
elijahsj 1:8a094db1347f 416 #if defined(I2C2_BASE) && defined(__HAL_RCC_I2C2_CONFIG)
elijahsj 1:8a094db1347f 417 if (obj_s->i2c == I2C_2) {
elijahsj 1:8a094db1347f 418 __HAL_RCC_I2C2_CONFIG(I2CAPI_I2C2_CLKSRC);
elijahsj 1:8a094db1347f 419 }
elijahsj 1:8a094db1347f 420 #endif
elijahsj 1:8a094db1347f 421 #if defined(I2C3_BASE) && defined(__HAL_RCC_I2C3_CONFIG)
elijahsj 1:8a094db1347f 422 if (obj_s->i2c == I2C_3) {
elijahsj 1:8a094db1347f 423 __HAL_RCC_I2C3_CONFIG(I2CAPI_I2C3_CLKSRC);
elijahsj 1:8a094db1347f 424 }
elijahsj 1:8a094db1347f 425 #endif
elijahsj 1:8a094db1347f 426 #if defined(I2C4_BASE) && defined(__HAL_RCC_I2C4_CONFIG)
elijahsj 1:8a094db1347f 427 if (obj_s->i2c == I2C_4) {
elijahsj 1:8a094db1347f 428 __HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC);
elijahsj 1:8a094db1347f 429 }
elijahsj 1:8a094db1347f 430 #endif
elijahsj 1:8a094db1347f 431
elijahsj 1:8a094db1347f 432 #ifdef I2C_ANALOGFILTER_ENABLE
elijahsj 1:8a094db1347f 433 /* Enable the Analog I2C Filter */
elijahsj 1:8a094db1347f 434 HAL_I2CEx_AnalogFilter_Config(handle,I2C_ANALOGFILTER_ENABLE);
elijahsj 1:8a094db1347f 435 #endif
elijahsj 1:8a094db1347f 436
elijahsj 1:8a094db1347f 437 // I2C configuration
elijahsj 1:8a094db1347f 438 handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
elijahsj 1:8a094db1347f 439 handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
elijahsj 1:8a094db1347f 440 handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
elijahsj 1:8a094db1347f 441 handle->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
elijahsj 1:8a094db1347f 442 handle->Init.OwnAddress1 = 0;
elijahsj 1:8a094db1347f 443 handle->Init.OwnAddress2 = 0;
elijahsj 1:8a094db1347f 444 HAL_I2C_Init(handle);
elijahsj 1:8a094db1347f 445
elijahsj 1:8a094db1347f 446 /* store frequency for timeout computation */
elijahsj 1:8a094db1347f 447 obj_s->hz = hz;
elijahsj 1:8a094db1347f 448 }
elijahsj 1:8a094db1347f 449
elijahsj 1:8a094db1347f 450 i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c){
elijahsj 1:8a094db1347f 451 /* Aim of the function is to get i2c_s pointer using hi2c pointer */
elijahsj 1:8a094db1347f 452 /* Highly inspired from magical linux kernel's "container_of" */
elijahsj 1:8a094db1347f 453 /* (which was not directly used since not compatible with IAR toolchain) */
elijahsj 1:8a094db1347f 454 struct i2c_s *obj_s;
elijahsj 1:8a094db1347f 455 i2c_t *obj;
elijahsj 1:8a094db1347f 456
elijahsj 1:8a094db1347f 457 obj_s = (struct i2c_s *)( (char *)hi2c - offsetof(struct i2c_s,handle));
elijahsj 1:8a094db1347f 458 obj = (i2c_t *)( (char *)obj_s - offsetof(i2c_t,i2c));
elijahsj 1:8a094db1347f 459
elijahsj 1:8a094db1347f 460 return (obj);
elijahsj 1:8a094db1347f 461 }
elijahsj 1:8a094db1347f 462
elijahsj 1:8a094db1347f 463 void i2c_reset(i2c_t *obj) {
elijahsj 1:8a094db1347f 464 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 465 /* As recommended in i2c_api.h, mainly send stop */
elijahsj 1:8a094db1347f 466 i2c_stop(obj);
elijahsj 1:8a094db1347f 467 /* then re-init */
elijahsj 1:8a094db1347f 468 i2c_init(obj, obj_s->sda, obj_s->scl);
elijahsj 1:8a094db1347f 469 }
elijahsj 1:8a094db1347f 470
elijahsj 1:8a094db1347f 471 /*
elijahsj 1:8a094db1347f 472 * UNITARY APIS.
elijahsj 1:8a094db1347f 473 * For very basic operations, direct registers access is needed
elijahsj 1:8a094db1347f 474 * There are 2 different IPs version that need to be supported
elijahsj 1:8a094db1347f 475 */
elijahsj 1:8a094db1347f 476 #ifdef I2C_IP_VERSION_V1
elijahsj 1:8a094db1347f 477 int i2c_start(i2c_t *obj) {
elijahsj 1:8a094db1347f 478
elijahsj 1:8a094db1347f 479 int timeout;
elijahsj 1:8a094db1347f 480 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 481 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 482
elijahsj 1:8a094db1347f 483 // Clear Acknowledge failure flag
elijahsj 1:8a094db1347f 484 __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_AF);
elijahsj 1:8a094db1347f 485
elijahsj 1:8a094db1347f 486 // Wait the STOP condition has been previously correctly sent
elijahsj 1:8a094db1347f 487 // This timeout can be avoid in some specific cases by simply clearing the STOP bit
elijahsj 1:8a094db1347f 488 timeout = FLAG_TIMEOUT;
elijahsj 1:8a094db1347f 489 while ((handle->Instance->CR1 & I2C_CR1_STOP) == I2C_CR1_STOP) {
elijahsj 1:8a094db1347f 490 if ((timeout--) == 0) {
elijahsj 1:8a094db1347f 491 return 1;
elijahsj 1:8a094db1347f 492 }
elijahsj 1:8a094db1347f 493 }
elijahsj 1:8a094db1347f 494
elijahsj 1:8a094db1347f 495 // Generate the START condition
elijahsj 1:8a094db1347f 496 handle->Instance->CR1 |= I2C_CR1_START;
elijahsj 1:8a094db1347f 497
elijahsj 1:8a094db1347f 498 // Wait the START condition has been correctly sent
elijahsj 1:8a094db1347f 499 timeout = FLAG_TIMEOUT;
elijahsj 1:8a094db1347f 500 while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_SB) == RESET) {
elijahsj 1:8a094db1347f 501 if ((timeout--) == 0) {
elijahsj 1:8a094db1347f 502 return 1;
elijahsj 1:8a094db1347f 503 }
elijahsj 1:8a094db1347f 504 }
elijahsj 1:8a094db1347f 505
elijahsj 1:8a094db1347f 506 return 0;
elijahsj 1:8a094db1347f 507 }
elijahsj 1:8a094db1347f 508
elijahsj 1:8a094db1347f 509 int i2c_stop(i2c_t *obj) {
elijahsj 1:8a094db1347f 510 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 511 I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c;
elijahsj 1:8a094db1347f 512
elijahsj 1:8a094db1347f 513 // Generate the STOP condition
elijahsj 1:8a094db1347f 514 i2c->CR1 |= I2C_CR1_STOP;
elijahsj 1:8a094db1347f 515
elijahsj 1:8a094db1347f 516 /* In case of mixed usage of the APIs (unitary + SYNC)
elijahsj 1:8a094db1347f 517 * re-init HAL state
elijahsj 1:8a094db1347f 518 */
elijahsj 1:8a094db1347f 519 if(obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME)
elijahsj 1:8a094db1347f 520 i2c_init(obj, obj_s->sda, obj_s->scl);
elijahsj 1:8a094db1347f 521
elijahsj 1:8a094db1347f 522 return 0;
elijahsj 1:8a094db1347f 523 }
elijahsj 1:8a094db1347f 524
elijahsj 1:8a094db1347f 525 int i2c_byte_read(i2c_t *obj, int last) {
elijahsj 1:8a094db1347f 526
elijahsj 1:8a094db1347f 527 int timeout;
elijahsj 1:8a094db1347f 528 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 529 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 530
elijahsj 1:8a094db1347f 531 if (last) {
elijahsj 1:8a094db1347f 532 // Don't acknowledge the last byte
elijahsj 1:8a094db1347f 533 handle->Instance->CR1 &= ~I2C_CR1_ACK;
elijahsj 1:8a094db1347f 534 } else {
elijahsj 1:8a094db1347f 535 // Acknowledge the byte
elijahsj 1:8a094db1347f 536 handle->Instance->CR1 |= I2C_CR1_ACK;
elijahsj 1:8a094db1347f 537 }
elijahsj 1:8a094db1347f 538
elijahsj 1:8a094db1347f 539 // Wait until the byte is received
elijahsj 1:8a094db1347f 540 timeout = FLAG_TIMEOUT;
elijahsj 1:8a094db1347f 541 while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE) == RESET) {
elijahsj 1:8a094db1347f 542 if ((timeout--) == 0) {
elijahsj 1:8a094db1347f 543 return -1;
elijahsj 1:8a094db1347f 544 }
elijahsj 1:8a094db1347f 545 }
elijahsj 1:8a094db1347f 546
elijahsj 1:8a094db1347f 547 return (int)handle->Instance->DR;
elijahsj 1:8a094db1347f 548 }
elijahsj 1:8a094db1347f 549
elijahsj 1:8a094db1347f 550 int i2c_byte_write(i2c_t *obj, int data) {
elijahsj 1:8a094db1347f 551
elijahsj 1:8a094db1347f 552 int timeout;
elijahsj 1:8a094db1347f 553 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 554 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 555
elijahsj 1:8a094db1347f 556 handle->Instance->DR = (uint8_t)data;
elijahsj 1:8a094db1347f 557
elijahsj 1:8a094db1347f 558 // Wait until the byte (might be the address) is transmitted
elijahsj 1:8a094db1347f 559 timeout = FLAG_TIMEOUT;
elijahsj 1:8a094db1347f 560 while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE) == RESET) &&
elijahsj 1:8a094db1347f 561 (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == RESET) &&
elijahsj 1:8a094db1347f 562 (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET)) {
elijahsj 1:8a094db1347f 563 if ((timeout--) == 0) {
elijahsj 1:8a094db1347f 564 return 2;
elijahsj 1:8a094db1347f 565 }
elijahsj 1:8a094db1347f 566 }
elijahsj 1:8a094db1347f 567
elijahsj 1:8a094db1347f 568 if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) != RESET)
elijahsj 1:8a094db1347f 569 {
elijahsj 1:8a094db1347f 570 __HAL_I2C_CLEAR_ADDRFLAG(handle);
elijahsj 1:8a094db1347f 571 }
elijahsj 1:8a094db1347f 572
elijahsj 1:8a094db1347f 573 return 1;
elijahsj 1:8a094db1347f 574 }
elijahsj 1:8a094db1347f 575 #endif //I2C_IP_VERSION_V1
elijahsj 1:8a094db1347f 576 #ifdef I2C_IP_VERSION_V2
elijahsj 1:8a094db1347f 577
elijahsj 1:8a094db1347f 578 int i2c_start(i2c_t *obj) {
elijahsj 1:8a094db1347f 579 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 580 /* This I2C IP doesn't */
elijahsj 1:8a094db1347f 581 obj_s->pending_start = 1;
elijahsj 1:8a094db1347f 582 return 0;
elijahsj 1:8a094db1347f 583 }
elijahsj 1:8a094db1347f 584
elijahsj 1:8a094db1347f 585 int i2c_stop(i2c_t *obj) {
elijahsj 1:8a094db1347f 586 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 587 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 588 int timeout = FLAG_TIMEOUT;
elijahsj 1:8a094db1347f 589 #if DEVICE_I2CSLAVE
elijahsj 1:8a094db1347f 590 if (obj_s->slave) {
elijahsj 1:8a094db1347f 591 /* re-init slave when stop is requested */
elijahsj 1:8a094db1347f 592 i2c_init(obj, obj_s->sda, obj_s->scl);
elijahsj 1:8a094db1347f 593 return 0;
elijahsj 1:8a094db1347f 594 }
elijahsj 1:8a094db1347f 595 #endif
elijahsj 1:8a094db1347f 596 // Disable reload mode
elijahsj 1:8a094db1347f 597 handle->Instance->CR2 &= (uint32_t)~I2C_CR2_RELOAD;
elijahsj 1:8a094db1347f 598 // Generate the STOP condition
elijahsj 1:8a094db1347f 599 handle->Instance->CR2 |= I2C_CR2_STOP;
elijahsj 1:8a094db1347f 600
elijahsj 1:8a094db1347f 601 timeout = FLAG_TIMEOUT;
elijahsj 1:8a094db1347f 602 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_STOPF)) {
elijahsj 1:8a094db1347f 603 if ((timeout--) == 0) {
elijahsj 1:8a094db1347f 604 return I2C_ERROR_BUS_BUSY;
elijahsj 1:8a094db1347f 605 }
elijahsj 1:8a094db1347f 606 }
elijahsj 1:8a094db1347f 607
elijahsj 1:8a094db1347f 608 /* Clear STOP Flag */
elijahsj 1:8a094db1347f 609 __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_STOPF);
elijahsj 1:8a094db1347f 610
elijahsj 1:8a094db1347f 611 /* Erase slave address, this wiil be used as a marker
elijahsj 1:8a094db1347f 612 * to know when we need to prepare next start */
elijahsj 1:8a094db1347f 613 handle->Instance->CR2 &= ~I2C_CR2_SADD;
elijahsj 1:8a094db1347f 614
elijahsj 1:8a094db1347f 615 /*
elijahsj 1:8a094db1347f 616 * V2 IP is meant for automatic STOP, not user STOP
elijahsj 1:8a094db1347f 617 * SW reset the IP state machine before next transaction
elijahsj 1:8a094db1347f 618 */
elijahsj 1:8a094db1347f 619 i2c_sw_reset(obj);
elijahsj 1:8a094db1347f 620
elijahsj 1:8a094db1347f 621 /* In case of mixed usage of the APIs (unitary + SYNC)
elijahsj 1:8a094db1347f 622 * re-init HAL state */
elijahsj 1:8a094db1347f 623 if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) {
elijahsj 1:8a094db1347f 624 i2c_init(obj, obj_s->sda, obj_s->scl);
elijahsj 1:8a094db1347f 625 }
elijahsj 1:8a094db1347f 626
elijahsj 1:8a094db1347f 627 return 0;
elijahsj 1:8a094db1347f 628 }
elijahsj 1:8a094db1347f 629
elijahsj 1:8a094db1347f 630 int i2c_byte_read(i2c_t *obj, int last) {
elijahsj 1:8a094db1347f 631 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 632 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 633 int timeout = FLAG_TIMEOUT;
elijahsj 1:8a094db1347f 634 uint32_t tmpreg = handle->Instance->CR2;
elijahsj 1:8a094db1347f 635 char data;
elijahsj 1:8a094db1347f 636 #if DEVICE_I2CSLAVE
elijahsj 1:8a094db1347f 637 if (obj_s->slave) {
elijahsj 1:8a094db1347f 638 return i2c_slave_read(obj, &data, 1);
elijahsj 1:8a094db1347f 639 }
elijahsj 1:8a094db1347f 640 #endif
elijahsj 1:8a094db1347f 641 /* Then send data when there's room in the TX fifo */
elijahsj 1:8a094db1347f 642 if ((tmpreg & I2C_CR2_RELOAD) != 0) {
elijahsj 1:8a094db1347f 643 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
elijahsj 1:8a094db1347f 644 if ((timeout--) == 0) {
elijahsj 1:8a094db1347f 645 DEBUG_PRINTF("timeout in byte_read\r\n");
elijahsj 1:8a094db1347f 646 return -1;
elijahsj 1:8a094db1347f 647 }
elijahsj 1:8a094db1347f 648 }
elijahsj 1:8a094db1347f 649 }
elijahsj 1:8a094db1347f 650
elijahsj 1:8a094db1347f 651 /* Enable reload mode as we don't know how many bytes will be sent */
elijahsj 1:8a094db1347f 652 /* and set transfer size to 1 */
elijahsj 1:8a094db1347f 653 tmpreg |= I2C_CR2_RELOAD | (I2C_CR2_NBYTES & (1 << 16));
elijahsj 1:8a094db1347f 654 /* Set the prepared configuration */
elijahsj 1:8a094db1347f 655 handle->Instance->CR2 = tmpreg;
elijahsj 1:8a094db1347f 656
elijahsj 1:8a094db1347f 657 timeout = FLAG_TIMEOUT;
elijahsj 1:8a094db1347f 658 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE)) {
elijahsj 1:8a094db1347f 659 if ((timeout--) == 0) {
elijahsj 1:8a094db1347f 660 return -1;
elijahsj 1:8a094db1347f 661 }
elijahsj 1:8a094db1347f 662 }
elijahsj 1:8a094db1347f 663
elijahsj 1:8a094db1347f 664 /* Then Get Byte */
elijahsj 1:8a094db1347f 665 data = handle->Instance->RXDR;
elijahsj 1:8a094db1347f 666
elijahsj 1:8a094db1347f 667 if (last) {
elijahsj 1:8a094db1347f 668 /* Disable Address Acknowledge */
elijahsj 1:8a094db1347f 669 handle->Instance->CR2 |= I2C_CR2_NACK;
elijahsj 1:8a094db1347f 670 }
elijahsj 1:8a094db1347f 671
elijahsj 1:8a094db1347f 672 return data;
elijahsj 1:8a094db1347f 673 }
elijahsj 1:8a094db1347f 674
elijahsj 1:8a094db1347f 675 int i2c_byte_write(i2c_t *obj, int data) {
elijahsj 1:8a094db1347f 676 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 677 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 678 int timeout = FLAG_TIMEOUT;
elijahsj 1:8a094db1347f 679 uint32_t tmpreg = handle->Instance->CR2;
elijahsj 1:8a094db1347f 680 #if DEVICE_I2CSLAVE
elijahsj 1:8a094db1347f 681 if (obj_s->slave) {
elijahsj 1:8a094db1347f 682 return i2c_slave_write(obj, (char *) &data, 1);
elijahsj 1:8a094db1347f 683 }
elijahsj 1:8a094db1347f 684 #endif
elijahsj 1:8a094db1347f 685 if (obj_s->pending_start) {
elijahsj 1:8a094db1347f 686 obj_s->pending_start = 0;
elijahsj 1:8a094db1347f 687 //* First byte after the start is the address */
elijahsj 1:8a094db1347f 688 tmpreg |= (uint32_t)((uint32_t)data & I2C_CR2_SADD);
elijahsj 1:8a094db1347f 689 if (data & 0x01) {
elijahsj 1:8a094db1347f 690 tmpreg |= I2C_CR2_START | I2C_CR2_RD_WRN;
elijahsj 1:8a094db1347f 691 } else {
elijahsj 1:8a094db1347f 692 tmpreg |= I2C_CR2_START;
elijahsj 1:8a094db1347f 693 tmpreg &= ~I2C_CR2_RD_WRN;
elijahsj 1:8a094db1347f 694 }
elijahsj 1:8a094db1347f 695 /* Disable reload first to use it later */
elijahsj 1:8a094db1347f 696 tmpreg &= ~I2C_CR2_RELOAD;
elijahsj 1:8a094db1347f 697 /* Disable Autoend */
elijahsj 1:8a094db1347f 698 tmpreg &= ~I2C_CR2_AUTOEND;
elijahsj 1:8a094db1347f 699 /* Do not set any transfer size for now */
elijahsj 1:8a094db1347f 700 tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
elijahsj 1:8a094db1347f 701 /* Set the prepared configuration */
elijahsj 1:8a094db1347f 702 handle->Instance->CR2 = tmpreg;
elijahsj 1:8a094db1347f 703 } else {
elijahsj 1:8a094db1347f 704 /* Set the prepared configuration */
elijahsj 1:8a094db1347f 705 tmpreg = handle->Instance->CR2;
elijahsj 1:8a094db1347f 706
elijahsj 1:8a094db1347f 707 /* Then send data when there's room in the TX fifo */
elijahsj 1:8a094db1347f 708 if ((tmpreg & I2C_CR2_RELOAD) != 0) {
elijahsj 1:8a094db1347f 709 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
elijahsj 1:8a094db1347f 710 if ((timeout--) == 0) {
elijahsj 1:8a094db1347f 711 DEBUG_PRINTF("timeout in byte_write\r\n");
elijahsj 1:8a094db1347f 712 return 2;
elijahsj 1:8a094db1347f 713 }
elijahsj 1:8a094db1347f 714 }
elijahsj 1:8a094db1347f 715 }
elijahsj 1:8a094db1347f 716 /* Enable reload mode as we don't know how many bytes will eb sent */
elijahsj 1:8a094db1347f 717 tmpreg |= I2C_CR2_RELOAD;
elijahsj 1:8a094db1347f 718 /* Set transfer size to 1 */
elijahsj 1:8a094db1347f 719 tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
elijahsj 1:8a094db1347f 720 /* Set the prepared configuration */
elijahsj 1:8a094db1347f 721 handle->Instance->CR2 = tmpreg;
elijahsj 1:8a094db1347f 722 /* Prepare next write */
elijahsj 1:8a094db1347f 723 timeout = FLAG_TIMEOUT;
elijahsj 1:8a094db1347f 724 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE)) {
elijahsj 1:8a094db1347f 725 if ((timeout--) == 0) {
elijahsj 1:8a094db1347f 726 return 2;
elijahsj 1:8a094db1347f 727 }
elijahsj 1:8a094db1347f 728 }
elijahsj 1:8a094db1347f 729 /* Write byte */
elijahsj 1:8a094db1347f 730 handle->Instance->TXDR = data;
elijahsj 1:8a094db1347f 731 }
elijahsj 1:8a094db1347f 732
elijahsj 1:8a094db1347f 733 return 1;
elijahsj 1:8a094db1347f 734 }
elijahsj 1:8a094db1347f 735 #endif //I2C_IP_VERSION_V2
elijahsj 1:8a094db1347f 736
elijahsj 1:8a094db1347f 737 /*
elijahsj 1:8a094db1347f 738 * SYNC APIS
elijahsj 1:8a094db1347f 739 */
elijahsj 1:8a094db1347f 740 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
elijahsj 1:8a094db1347f 741 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 742 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 743 int count = I2C_ERROR_BUS_BUSY, ret = 0;
elijahsj 1:8a094db1347f 744 uint32_t timeout = 0;
elijahsj 1:8a094db1347f 745
elijahsj 1:8a094db1347f 746 if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
elijahsj 1:8a094db1347f 747 (obj_s->XferOperation == I2C_LAST_FRAME)) {
elijahsj 1:8a094db1347f 748 if (stop)
elijahsj 1:8a094db1347f 749 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
elijahsj 1:8a094db1347f 750 else
elijahsj 1:8a094db1347f 751 obj_s->XferOperation = I2C_FIRST_FRAME;
elijahsj 1:8a094db1347f 752 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
elijahsj 1:8a094db1347f 753 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
elijahsj 1:8a094db1347f 754 if (stop)
elijahsj 1:8a094db1347f 755 obj_s->XferOperation = I2C_LAST_FRAME;
elijahsj 1:8a094db1347f 756 else
elijahsj 1:8a094db1347f 757 obj_s->XferOperation = I2C_NEXT_FRAME;
elijahsj 1:8a094db1347f 758 }
elijahsj 1:8a094db1347f 759
elijahsj 1:8a094db1347f 760 obj_s->event = 0;
elijahsj 1:8a094db1347f 761
elijahsj 1:8a094db1347f 762 /* Activate default IRQ handlers for sync mode
elijahsj 1:8a094db1347f 763 * which would be overwritten in async mode
elijahsj 1:8a094db1347f 764 */
elijahsj 1:8a094db1347f 765 i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
elijahsj 1:8a094db1347f 766
elijahsj 1:8a094db1347f 767 ret = HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
elijahsj 1:8a094db1347f 768
elijahsj 1:8a094db1347f 769 if(ret == HAL_OK) {
elijahsj 1:8a094db1347f 770 timeout = BYTE_TIMEOUT_US * (length + 1);
elijahsj 1:8a094db1347f 771 /* transfer started : wait completion or timeout */
elijahsj 1:8a094db1347f 772 while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
elijahsj 1:8a094db1347f 773 wait_us(1);
elijahsj 1:8a094db1347f 774 }
elijahsj 1:8a094db1347f 775
elijahsj 1:8a094db1347f 776 i2c_ev_err_disable(obj);
elijahsj 1:8a094db1347f 777
elijahsj 1:8a094db1347f 778 if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
elijahsj 1:8a094db1347f 779 DEBUG_PRINTF(" TIMEOUT or error in i2c_read\r\n");
elijahsj 1:8a094db1347f 780 /* re-init IP to try and get back in a working state */
elijahsj 1:8a094db1347f 781 i2c_init(obj, obj_s->sda, obj_s->scl);
elijahsj 1:8a094db1347f 782 } else {
elijahsj 1:8a094db1347f 783 count = length;
elijahsj 1:8a094db1347f 784 }
elijahsj 1:8a094db1347f 785 } else {
elijahsj 1:8a094db1347f 786 DEBUG_PRINTF("ERROR in i2c_read:%d\r\n", ret);
elijahsj 1:8a094db1347f 787 }
elijahsj 1:8a094db1347f 788
elijahsj 1:8a094db1347f 789 return count;
elijahsj 1:8a094db1347f 790 }
elijahsj 1:8a094db1347f 791
elijahsj 1:8a094db1347f 792 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
elijahsj 1:8a094db1347f 793 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 794 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 795 int count = I2C_ERROR_BUS_BUSY, ret = 0;
elijahsj 1:8a094db1347f 796 uint32_t timeout = 0;
elijahsj 1:8a094db1347f 797
elijahsj 1:8a094db1347f 798 if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
elijahsj 1:8a094db1347f 799 (obj_s->XferOperation == I2C_LAST_FRAME)) {
elijahsj 1:8a094db1347f 800 if (stop)
elijahsj 1:8a094db1347f 801 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
elijahsj 1:8a094db1347f 802 else
elijahsj 1:8a094db1347f 803 obj_s->XferOperation = I2C_FIRST_FRAME;
elijahsj 1:8a094db1347f 804 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
elijahsj 1:8a094db1347f 805 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
elijahsj 1:8a094db1347f 806 if (stop)
elijahsj 1:8a094db1347f 807 obj_s->XferOperation = I2C_LAST_FRAME;
elijahsj 1:8a094db1347f 808 else
elijahsj 1:8a094db1347f 809 obj_s->XferOperation = I2C_NEXT_FRAME;
elijahsj 1:8a094db1347f 810 }
elijahsj 1:8a094db1347f 811
elijahsj 1:8a094db1347f 812 obj_s->event = 0;
elijahsj 1:8a094db1347f 813
elijahsj 1:8a094db1347f 814 i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
elijahsj 1:8a094db1347f 815
elijahsj 1:8a094db1347f 816 ret = HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
elijahsj 1:8a094db1347f 817
elijahsj 1:8a094db1347f 818 if(ret == HAL_OK) {
elijahsj 1:8a094db1347f 819 timeout = BYTE_TIMEOUT_US * (length + 1);
elijahsj 1:8a094db1347f 820 /* transfer started : wait completion or timeout */
elijahsj 1:8a094db1347f 821 while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
elijahsj 1:8a094db1347f 822 wait_us(1);
elijahsj 1:8a094db1347f 823 }
elijahsj 1:8a094db1347f 824
elijahsj 1:8a094db1347f 825 i2c_ev_err_disable(obj);
elijahsj 1:8a094db1347f 826
elijahsj 1:8a094db1347f 827 if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
elijahsj 1:8a094db1347f 828 DEBUG_PRINTF(" TIMEOUT or error in i2c_write\r\n");
elijahsj 1:8a094db1347f 829 /* re-init IP to try and get back in a working state */
elijahsj 1:8a094db1347f 830 i2c_init(obj, obj_s->sda, obj_s->scl);
elijahsj 1:8a094db1347f 831 } else {
elijahsj 1:8a094db1347f 832 count = length;
elijahsj 1:8a094db1347f 833 }
elijahsj 1:8a094db1347f 834 } else {
elijahsj 1:8a094db1347f 835 DEBUG_PRINTF("ERROR in i2c_read\r\n");
elijahsj 1:8a094db1347f 836 }
elijahsj 1:8a094db1347f 837
elijahsj 1:8a094db1347f 838 return count;
elijahsj 1:8a094db1347f 839 }
elijahsj 1:8a094db1347f 840
elijahsj 1:8a094db1347f 841 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c){
elijahsj 1:8a094db1347f 842 /* Get object ptr based on handler ptr */
elijahsj 1:8a094db1347f 843 i2c_t *obj = get_i2c_obj(hi2c);
elijahsj 1:8a094db1347f 844 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 845
elijahsj 1:8a094db1347f 846 #if DEVICE_I2C_ASYNCH
elijahsj 1:8a094db1347f 847 /* Handle potential Tx/Rx use case */
elijahsj 1:8a094db1347f 848 if ((obj->tx_buff.length) && (obj->rx_buff.length)) {
elijahsj 1:8a094db1347f 849 if (obj_s->stop) {
elijahsj 1:8a094db1347f 850 obj_s->XferOperation = I2C_LAST_FRAME;
elijahsj 1:8a094db1347f 851 } else {
elijahsj 1:8a094db1347f 852 obj_s->XferOperation = I2C_NEXT_FRAME;
elijahsj 1:8a094db1347f 853 }
elijahsj 1:8a094db1347f 854
elijahsj 1:8a094db1347f 855 HAL_I2C_Master_Sequential_Receive_IT(hi2c, obj_s->address, (uint8_t*)obj->rx_buff.buffer , obj->rx_buff.length, obj_s->XferOperation);
elijahsj 1:8a094db1347f 856 }
elijahsj 1:8a094db1347f 857 else
elijahsj 1:8a094db1347f 858 #endif
elijahsj 1:8a094db1347f 859 {
elijahsj 1:8a094db1347f 860 /* Set event flag */
elijahsj 1:8a094db1347f 861 obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
elijahsj 1:8a094db1347f 862 }
elijahsj 1:8a094db1347f 863 }
elijahsj 1:8a094db1347f 864
elijahsj 1:8a094db1347f 865 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c){
elijahsj 1:8a094db1347f 866 /* Get object ptr based on handler ptr */
elijahsj 1:8a094db1347f 867 i2c_t *obj = get_i2c_obj(hi2c);
elijahsj 1:8a094db1347f 868 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 869
elijahsj 1:8a094db1347f 870 /* Set event flag */
elijahsj 1:8a094db1347f 871 obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
elijahsj 1:8a094db1347f 872 }
elijahsj 1:8a094db1347f 873
elijahsj 1:8a094db1347f 874 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c){
elijahsj 1:8a094db1347f 875 /* Get object ptr based on handler ptr */
elijahsj 1:8a094db1347f 876 i2c_t *obj = get_i2c_obj(hi2c);
elijahsj 1:8a094db1347f 877 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 878 #if DEVICE_I2CSLAVE
elijahsj 1:8a094db1347f 879 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 880 uint32_t address = 0;
elijahsj 1:8a094db1347f 881 /* Store address to handle it after reset */
elijahsj 1:8a094db1347f 882 if(obj_s->slave)
elijahsj 1:8a094db1347f 883 address = handle->Init.OwnAddress1;
elijahsj 1:8a094db1347f 884 #endif
elijahsj 1:8a094db1347f 885
elijahsj 1:8a094db1347f 886 DEBUG_PRINTF("HAL_I2C_ErrorCallback:%d, index=%d\r\n", (int) hi2c->ErrorCode, obj_s->index);
elijahsj 1:8a094db1347f 887
elijahsj 1:8a094db1347f 888 /* re-init IP to try and get back in a working state */
elijahsj 1:8a094db1347f 889 i2c_init(obj, obj_s->sda, obj_s->scl);
elijahsj 1:8a094db1347f 890
elijahsj 1:8a094db1347f 891 #if DEVICE_I2CSLAVE
elijahsj 1:8a094db1347f 892 /* restore slave address */
elijahsj 1:8a094db1347f 893 if (address != 0) {
elijahsj 1:8a094db1347f 894 obj_s->slave = 1;
elijahsj 1:8a094db1347f 895 i2c_slave_address(obj, 0, address, 0);
elijahsj 1:8a094db1347f 896 }
elijahsj 1:8a094db1347f 897 #endif
elijahsj 1:8a094db1347f 898
elijahsj 1:8a094db1347f 899 /* Keep Set event flag */
elijahsj 1:8a094db1347f 900 obj_s->event = I2C_EVENT_ERROR;
elijahsj 1:8a094db1347f 901 }
elijahsj 1:8a094db1347f 902
elijahsj 1:8a094db1347f 903 #if DEVICE_I2CSLAVE
elijahsj 1:8a094db1347f 904 /* SLAVE API FUNCTIONS */
elijahsj 1:8a094db1347f 905 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
elijahsj 1:8a094db1347f 906 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 907 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 908
elijahsj 1:8a094db1347f 909 // I2C configuration
elijahsj 1:8a094db1347f 910 handle->Init.OwnAddress1 = address;
elijahsj 1:8a094db1347f 911 HAL_I2C_Init(handle);
elijahsj 1:8a094db1347f 912
elijahsj 1:8a094db1347f 913 i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
elijahsj 1:8a094db1347f 914
elijahsj 1:8a094db1347f 915 HAL_I2C_EnableListen_IT(handle);
elijahsj 1:8a094db1347f 916 }
elijahsj 1:8a094db1347f 917
elijahsj 1:8a094db1347f 918 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
elijahsj 1:8a094db1347f 919
elijahsj 1:8a094db1347f 920 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 921 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 922
elijahsj 1:8a094db1347f 923 if (enable_slave) {
elijahsj 1:8a094db1347f 924 obj_s->slave = 1;
elijahsj 1:8a094db1347f 925 HAL_I2C_EnableListen_IT(handle);
elijahsj 1:8a094db1347f 926 } else {
elijahsj 1:8a094db1347f 927 obj_s->slave = 0;
elijahsj 1:8a094db1347f 928 HAL_I2C_DisableListen_IT(handle);
elijahsj 1:8a094db1347f 929 }
elijahsj 1:8a094db1347f 930 }
elijahsj 1:8a094db1347f 931
elijahsj 1:8a094db1347f 932 // See I2CSlave.h
elijahsj 1:8a094db1347f 933 #define NoData 0 // the slave has not been addressed
elijahsj 1:8a094db1347f 934 #define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
elijahsj 1:8a094db1347f 935 #define WriteGeneral 2 // the master is writing to all slave
elijahsj 1:8a094db1347f 936 #define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
elijahsj 1:8a094db1347f 937
elijahsj 1:8a094db1347f 938
elijahsj 1:8a094db1347f 939 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) {
elijahsj 1:8a094db1347f 940 /* Get object ptr based on handler ptr */
elijahsj 1:8a094db1347f 941 i2c_t *obj = get_i2c_obj(hi2c);
elijahsj 1:8a094db1347f 942 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 943
elijahsj 1:8a094db1347f 944 /* Transfer direction in HAL is from Master point of view */
elijahsj 1:8a094db1347f 945 if(TransferDirection == I2C_DIRECTION_RECEIVE) {
elijahsj 1:8a094db1347f 946 obj_s->pending_slave_tx_master_rx = 1;
elijahsj 1:8a094db1347f 947 }
elijahsj 1:8a094db1347f 948
elijahsj 1:8a094db1347f 949 if(TransferDirection == I2C_DIRECTION_TRANSMIT) {
elijahsj 1:8a094db1347f 950 obj_s->pending_slave_rx_maxter_tx = 1;
elijahsj 1:8a094db1347f 951 }
elijahsj 1:8a094db1347f 952 }
elijahsj 1:8a094db1347f 953
elijahsj 1:8a094db1347f 954 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle){
elijahsj 1:8a094db1347f 955 /* Get object ptr based on handler ptr */
elijahsj 1:8a094db1347f 956 i2c_t *obj = get_i2c_obj(I2cHandle);
elijahsj 1:8a094db1347f 957 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 958 obj_s->pending_slave_tx_master_rx = 0;
elijahsj 1:8a094db1347f 959 }
elijahsj 1:8a094db1347f 960
elijahsj 1:8a094db1347f 961 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle){
elijahsj 1:8a094db1347f 962 /* Get object ptr based on handler ptr */
elijahsj 1:8a094db1347f 963 i2c_t *obj = get_i2c_obj(I2cHandle);
elijahsj 1:8a094db1347f 964 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 965 obj_s->pending_slave_rx_maxter_tx = 0;
elijahsj 1:8a094db1347f 966 }
elijahsj 1:8a094db1347f 967
elijahsj 1:8a094db1347f 968 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
elijahsj 1:8a094db1347f 969 {
elijahsj 1:8a094db1347f 970 /* restart listening for master requests */
elijahsj 1:8a094db1347f 971 HAL_I2C_EnableListen_IT(hi2c);
elijahsj 1:8a094db1347f 972 }
elijahsj 1:8a094db1347f 973
elijahsj 1:8a094db1347f 974 int i2c_slave_receive(i2c_t *obj) {
elijahsj 1:8a094db1347f 975
elijahsj 1:8a094db1347f 976 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 977 int retValue = NoData;
elijahsj 1:8a094db1347f 978
elijahsj 1:8a094db1347f 979 if(obj_s->pending_slave_rx_maxter_tx) {
elijahsj 1:8a094db1347f 980 retValue = WriteAddressed;
elijahsj 1:8a094db1347f 981 }
elijahsj 1:8a094db1347f 982
elijahsj 1:8a094db1347f 983 if(obj_s->pending_slave_tx_master_rx) {
elijahsj 1:8a094db1347f 984 retValue = ReadAddressed;
elijahsj 1:8a094db1347f 985 }
elijahsj 1:8a094db1347f 986
elijahsj 1:8a094db1347f 987 return (retValue);
elijahsj 1:8a094db1347f 988 }
elijahsj 1:8a094db1347f 989
elijahsj 1:8a094db1347f 990 int i2c_slave_read(i2c_t *obj, char *data, int length) {
elijahsj 1:8a094db1347f 991 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 992 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 993 int count = 0;
elijahsj 1:8a094db1347f 994 int ret = 0;
elijahsj 1:8a094db1347f 995 uint32_t timeout = 0;
elijahsj 1:8a094db1347f 996
elijahsj 1:8a094db1347f 997 /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
elijahsj 1:8a094db1347f 998 ret = HAL_I2C_Slave_Sequential_Receive_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
elijahsj 1:8a094db1347f 999
elijahsj 1:8a094db1347f 1000 if(ret == HAL_OK) {
elijahsj 1:8a094db1347f 1001 timeout = BYTE_TIMEOUT_US * (length + 1);
elijahsj 1:8a094db1347f 1002 while(obj_s->pending_slave_rx_maxter_tx && (--timeout != 0)) {
elijahsj 1:8a094db1347f 1003 wait_us(1);
elijahsj 1:8a094db1347f 1004 }
elijahsj 1:8a094db1347f 1005
elijahsj 1:8a094db1347f 1006 if(timeout != 0) {
elijahsj 1:8a094db1347f 1007 count = length;
elijahsj 1:8a094db1347f 1008 } else {
elijahsj 1:8a094db1347f 1009 DEBUG_PRINTF("TIMEOUT or error in i2c_slave_read\r\n");
elijahsj 1:8a094db1347f 1010 }
elijahsj 1:8a094db1347f 1011 }
elijahsj 1:8a094db1347f 1012 return count;
elijahsj 1:8a094db1347f 1013 }
elijahsj 1:8a094db1347f 1014
elijahsj 1:8a094db1347f 1015 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
elijahsj 1:8a094db1347f 1016 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 1017 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 1018 int count = 0;
elijahsj 1:8a094db1347f 1019 int ret = 0;
elijahsj 1:8a094db1347f 1020 uint32_t timeout = 0;
elijahsj 1:8a094db1347f 1021
elijahsj 1:8a094db1347f 1022 /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
elijahsj 1:8a094db1347f 1023 ret = HAL_I2C_Slave_Sequential_Transmit_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
elijahsj 1:8a094db1347f 1024
elijahsj 1:8a094db1347f 1025 if(ret == HAL_OK) {
elijahsj 1:8a094db1347f 1026 timeout = BYTE_TIMEOUT_US * (length + 1);
elijahsj 1:8a094db1347f 1027 while(obj_s->pending_slave_tx_master_rx && (--timeout != 0)) {
elijahsj 1:8a094db1347f 1028 wait_us(1);
elijahsj 1:8a094db1347f 1029 }
elijahsj 1:8a094db1347f 1030
elijahsj 1:8a094db1347f 1031 if(timeout != 0) {
elijahsj 1:8a094db1347f 1032 count = length;
elijahsj 1:8a094db1347f 1033 } else {
elijahsj 1:8a094db1347f 1034 DEBUG_PRINTF("TIMEOUT or error in i2c_slave_write\r\n");
elijahsj 1:8a094db1347f 1035 }
elijahsj 1:8a094db1347f 1036 }
elijahsj 1:8a094db1347f 1037
elijahsj 1:8a094db1347f 1038 return count;
elijahsj 1:8a094db1347f 1039 }
elijahsj 1:8a094db1347f 1040 #endif // DEVICE_I2CSLAVE
elijahsj 1:8a094db1347f 1041
elijahsj 1:8a094db1347f 1042 #if DEVICE_I2C_ASYNCH
elijahsj 1:8a094db1347f 1043 /* ASYNCH MASTER API FUNCTIONS */
elijahsj 1:8a094db1347f 1044 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c){
elijahsj 1:8a094db1347f 1045 /* Get object ptr based on handler ptr */
elijahsj 1:8a094db1347f 1046 i2c_t *obj = get_i2c_obj(hi2c);
elijahsj 1:8a094db1347f 1047 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 1048 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 1049
elijahsj 1:8a094db1347f 1050 /* Disable IT. Not always done before calling macro */
elijahsj 1:8a094db1347f 1051 __HAL_I2C_DISABLE_IT(handle, I2C_IT_ALL);
elijahsj 1:8a094db1347f 1052 i2c_ev_err_disable(obj);
elijahsj 1:8a094db1347f 1053
elijahsj 1:8a094db1347f 1054 /* Set event flag */
elijahsj 1:8a094db1347f 1055 obj_s->event = I2C_EVENT_ERROR;
elijahsj 1:8a094db1347f 1056 }
elijahsj 1:8a094db1347f 1057
elijahsj 1:8a094db1347f 1058 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) {
elijahsj 1:8a094db1347f 1059
elijahsj 1:8a094db1347f 1060 // TODO: DMA usage is currently ignored by this way
elijahsj 1:8a094db1347f 1061 (void) hint;
elijahsj 1:8a094db1347f 1062
elijahsj 1:8a094db1347f 1063 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 1064 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 1065
elijahsj 1:8a094db1347f 1066 /* Update object */
elijahsj 1:8a094db1347f 1067 obj->tx_buff.buffer = (void *)tx;
elijahsj 1:8a094db1347f 1068 obj->tx_buff.length = tx_length;
elijahsj 1:8a094db1347f 1069 obj->tx_buff.pos = 0;
elijahsj 1:8a094db1347f 1070 obj->tx_buff.width = 8;
elijahsj 1:8a094db1347f 1071
elijahsj 1:8a094db1347f 1072 obj->rx_buff.buffer = (void *)rx;
elijahsj 1:8a094db1347f 1073 obj->rx_buff.length = rx_length;
elijahsj 1:8a094db1347f 1074 obj->rx_buff.pos = SIZE_MAX;
elijahsj 1:8a094db1347f 1075 obj->rx_buff.width = 8;
elijahsj 1:8a094db1347f 1076
elijahsj 1:8a094db1347f 1077 obj_s->available_events = event;
elijahsj 1:8a094db1347f 1078 obj_s->event = 0;
elijahsj 1:8a094db1347f 1079 obj_s->address = address;
elijahsj 1:8a094db1347f 1080 obj_s->stop = stop;
elijahsj 1:8a094db1347f 1081
elijahsj 1:8a094db1347f 1082 i2c_ev_err_enable(obj, handler);
elijahsj 1:8a094db1347f 1083
elijahsj 1:8a094db1347f 1084 /* Set operation step depending if stop sending required or not */
elijahsj 1:8a094db1347f 1085 if ((tx_length && !rx_length) || (!tx_length && rx_length)) {
elijahsj 1:8a094db1347f 1086 if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
elijahsj 1:8a094db1347f 1087 (obj_s->XferOperation == I2C_LAST_FRAME)) {
elijahsj 1:8a094db1347f 1088 if (stop)
elijahsj 1:8a094db1347f 1089 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
elijahsj 1:8a094db1347f 1090 else
elijahsj 1:8a094db1347f 1091 obj_s->XferOperation = I2C_FIRST_FRAME;
elijahsj 1:8a094db1347f 1092 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
elijahsj 1:8a094db1347f 1093 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
elijahsj 1:8a094db1347f 1094 if (stop)
elijahsj 1:8a094db1347f 1095 obj_s->XferOperation = I2C_LAST_FRAME;
elijahsj 1:8a094db1347f 1096 else
elijahsj 1:8a094db1347f 1097 obj_s->XferOperation = I2C_NEXT_FRAME;
elijahsj 1:8a094db1347f 1098 }
elijahsj 1:8a094db1347f 1099
elijahsj 1:8a094db1347f 1100 if (tx_length > 0) {
elijahsj 1:8a094db1347f 1101 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, obj_s->XferOperation);
elijahsj 1:8a094db1347f 1102 }
elijahsj 1:8a094db1347f 1103 if (rx_length > 0) {
elijahsj 1:8a094db1347f 1104 HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t*)rx, rx_length, obj_s->XferOperation);
elijahsj 1:8a094db1347f 1105 }
elijahsj 1:8a094db1347f 1106 }
elijahsj 1:8a094db1347f 1107 else if (tx_length && rx_length) {
elijahsj 1:8a094db1347f 1108 /* Two steps operation, don't modify XferOperation, keep it for next step */
elijahsj 1:8a094db1347f 1109 if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
elijahsj 1:8a094db1347f 1110 (obj_s->XferOperation == I2C_LAST_FRAME)) {
elijahsj 1:8a094db1347f 1111 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_FIRST_FRAME);
elijahsj 1:8a094db1347f 1112 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
elijahsj 1:8a094db1347f 1113 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
elijahsj 1:8a094db1347f 1114 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_NEXT_FRAME);
elijahsj 1:8a094db1347f 1115 }
elijahsj 1:8a094db1347f 1116 }
elijahsj 1:8a094db1347f 1117 }
elijahsj 1:8a094db1347f 1118
elijahsj 1:8a094db1347f 1119
elijahsj 1:8a094db1347f 1120 uint32_t i2c_irq_handler_asynch(i2c_t *obj) {
elijahsj 1:8a094db1347f 1121
elijahsj 1:8a094db1347f 1122 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 1123 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 1124
elijahsj 1:8a094db1347f 1125 HAL_I2C_EV_IRQHandler(handle);
elijahsj 1:8a094db1347f 1126 HAL_I2C_ER_IRQHandler(handle);
elijahsj 1:8a094db1347f 1127
elijahsj 1:8a094db1347f 1128 /* Return I2C event status */
elijahsj 1:8a094db1347f 1129 return (obj_s->event & obj_s->available_events);
elijahsj 1:8a094db1347f 1130 }
elijahsj 1:8a094db1347f 1131
elijahsj 1:8a094db1347f 1132 uint8_t i2c_active(i2c_t *obj) {
elijahsj 1:8a094db1347f 1133
elijahsj 1:8a094db1347f 1134 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 1135 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 1136
elijahsj 1:8a094db1347f 1137 if (handle->State == HAL_I2C_STATE_READY) {
elijahsj 1:8a094db1347f 1138 return 0;
elijahsj 1:8a094db1347f 1139 }
elijahsj 1:8a094db1347f 1140 else {
elijahsj 1:8a094db1347f 1141 return 1;
elijahsj 1:8a094db1347f 1142 }
elijahsj 1:8a094db1347f 1143 }
elijahsj 1:8a094db1347f 1144
elijahsj 1:8a094db1347f 1145 void i2c_abort_asynch(i2c_t *obj) {
elijahsj 1:8a094db1347f 1146
elijahsj 1:8a094db1347f 1147 struct i2c_s *obj_s = I2C_S(obj);
elijahsj 1:8a094db1347f 1148 I2C_HandleTypeDef *handle = &(obj_s->handle);
elijahsj 1:8a094db1347f 1149
elijahsj 1:8a094db1347f 1150 /* Abort HAL requires DevAddress, but is not used. Use Dummy */
elijahsj 1:8a094db1347f 1151 uint16_t Dummy_DevAddress = 0x00;
elijahsj 1:8a094db1347f 1152
elijahsj 1:8a094db1347f 1153 HAL_I2C_Master_Abort_IT(handle, Dummy_DevAddress);
elijahsj 1:8a094db1347f 1154 }
elijahsj 1:8a094db1347f 1155
elijahsj 1:8a094db1347f 1156 #endif // DEVICE_I2C_ASYNCH
elijahsj 1:8a094db1347f 1157
elijahsj 1:8a094db1347f 1158 #endif // DEVICE_I2C