Elijah Stanger-Jones / mbed-dev-f303

test

targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.c@1:8a094db1347f, 2020-11-09 (annotated)

Committer:
elijahsj
Date:
Mon Nov 09 00:02:47 2020 -0500
Revision:
1:8a094db1347f
test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elijahsj 1:8a094db1347f 1 /**
elijahsj 1:8a094db1347f 2 * @file
elijahsj 1:8a094db1347f 3 * @brief Watchdog Timer 2 Function Implementations.
elijahsj 1:8a094db1347f 4 */
elijahsj 1:8a094db1347f 5 /* *****************************************************************************
elijahsj 1:8a094db1347f 6 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
elijahsj 1:8a094db1347f 7 *
elijahsj 1:8a094db1347f 8 * Permission is hereby granted, free of charge, to any person obtaining a
elijahsj 1:8a094db1347f 9 * copy of this software and associated documentation files (the "Software"),
elijahsj 1:8a094db1347f 10 * to deal in the Software without restriction, including without limitation
elijahsj 1:8a094db1347f 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
elijahsj 1:8a094db1347f 12 * and/or sell copies of the Software, and to permit persons to whom the
elijahsj 1:8a094db1347f 13 * Software is furnished to do so, subject to the following conditions:
elijahsj 1:8a094db1347f 14 *
elijahsj 1:8a094db1347f 15 * The above copyright notice and this permission notice shall be included
elijahsj 1:8a094db1347f 16 * in all copies or substantial portions of the Software.
elijahsj 1:8a094db1347f 17 *
elijahsj 1:8a094db1347f 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
elijahsj 1:8a094db1347f 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
elijahsj 1:8a094db1347f 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
elijahsj 1:8a094db1347f 21 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
elijahsj 1:8a094db1347f 22 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
elijahsj 1:8a094db1347f 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
elijahsj 1:8a094db1347f 24 * OTHER DEALINGS IN THE SOFTWARE.
elijahsj 1:8a094db1347f 25 *
elijahsj 1:8a094db1347f 26 * Except as contained in this notice, the name of Maxim Integrated
elijahsj 1:8a094db1347f 27 * Products, Inc. shall not be used except as stated in the Maxim Integrated
elijahsj 1:8a094db1347f 28 * Products, Inc. Branding Policy.
elijahsj 1:8a094db1347f 29 *
elijahsj 1:8a094db1347f 30 * The mere transfer of this software does not imply any licenses
elijahsj 1:8a094db1347f 31 * of trade secrets, proprietary technology, copyrights, patents,
elijahsj 1:8a094db1347f 32 * trademarks, maskwork rights, or any other form of intellectual
elijahsj 1:8a094db1347f 33 * property whatsoever. Maxim Integrated Products, Inc. retains all
elijahsj 1:8a094db1347f 34 * ownership rights.
elijahsj 1:8a094db1347f 35 *
elijahsj 1:8a094db1347f 36 * $Date: 2016-09-08 17:06:34 -0500 (Thu, 08 Sep 2016) $
elijahsj 1:8a094db1347f 37 * $Revision: 24320 $
elijahsj 1:8a094db1347f 38 *
elijahsj 1:8a094db1347f 39 **************************************************************************** */
elijahsj 1:8a094db1347f 40
elijahsj 1:8a094db1347f 41 /* **** Includes **** */
elijahsj 1:8a094db1347f 42 #include <stddef.h>
elijahsj 1:8a094db1347f 43 #include "wdt2.h"
elijahsj 1:8a094db1347f 44 #include "pwrseq_regs.h"
elijahsj 1:8a094db1347f 45
elijahsj 1:8a094db1347f 46 /**
elijahsj 1:8a094db1347f 47 * @ingroup wdt2
elijahsj 1:8a094db1347f 48 * @{
elijahsj 1:8a094db1347f 49 */
elijahsj 1:8a094db1347f 50 static uint32_t interruptEnable = 0; //keeps track to interrupts to enable in start function
elijahsj 1:8a094db1347f 51
elijahsj 1:8a094db1347f 52 /* ************************************************************************* */
elijahsj 1:8a094db1347f 53 int WDT2_Init(uint8_t runInSleep, uint8_t unlock_key)
elijahsj 1:8a094db1347f 54 {
elijahsj 1:8a094db1347f 55 //enable nanoring in run and sleep mode
elijahsj 1:8a094db1347f 56 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_RUN);
elijahsj 1:8a094db1347f 57
elijahsj 1:8a094db1347f 58 //unlock ctrl to be writable
elijahsj 1:8a094db1347f 59 MXC_WDT2->lock_ctrl = unlock_key;
elijahsj 1:8a094db1347f 60
elijahsj 1:8a094db1347f 61 //check to make sure it unlocked
elijahsj 1:8a094db1347f 62 if (MXC_WDT2->lock_ctrl & 0x01)
elijahsj 1:8a094db1347f 63 return E_BAD_STATE;
elijahsj 1:8a094db1347f 64
elijahsj 1:8a094db1347f 65 //disable all interrupts
elijahsj 1:8a094db1347f 66 interruptEnable = 0;
elijahsj 1:8a094db1347f 67 MXC_WDT2->enable = interruptEnable;
elijahsj 1:8a094db1347f 68
elijahsj 1:8a094db1347f 69 //enable the watchdog clock and clear all other settings
elijahsj 1:8a094db1347f 70 MXC_WDT2->ctrl = (MXC_F_WDT2_CTRL_EN_CLOCK);
elijahsj 1:8a094db1347f 71
elijahsj 1:8a094db1347f 72 //clear all interrupt flags
elijahsj 1:8a094db1347f 73 MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL;
elijahsj 1:8a094db1347f 74
elijahsj 1:8a094db1347f 75 if(runInSleep) {
elijahsj 1:8a094db1347f 76 // turn on nanoring during sleep
elijahsj 1:8a094db1347f 77 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_SLP);
elijahsj 1:8a094db1347f 78 //turn on timer during sleep
elijahsj 1:8a094db1347f 79 MXC_WDT2->ctrl |= MXC_F_WDT2_CTRL_EN_TIMER_SLP;
elijahsj 1:8a094db1347f 80 } else {
elijahsj 1:8a094db1347f 81 // turn off nanoring during sleep
elijahsj 1:8a094db1347f 82 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_NREN_SLP);
elijahsj 1:8a094db1347f 83 //turn off timer during sleep
elijahsj 1:8a094db1347f 84 MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_EN_TIMER_SLP);
elijahsj 1:8a094db1347f 85 }
elijahsj 1:8a094db1347f 86
elijahsj 1:8a094db1347f 87 //lock ctrl to read-only
elijahsj 1:8a094db1347f 88 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
elijahsj 1:8a094db1347f 89
elijahsj 1:8a094db1347f 90 return E_NO_ERROR;
elijahsj 1:8a094db1347f 91 }
elijahsj 1:8a094db1347f 92
elijahsj 1:8a094db1347f 93 /* ************************************************************************* */
elijahsj 1:8a094db1347f 94 int WDT2_EnableWakeUp(wdt2_period_t int_period, uint8_t unlock_key)
elijahsj 1:8a094db1347f 95 {
elijahsj 1:8a094db1347f 96 // Make sure interrupt period is valid
elijahsj 1:8a094db1347f 97 if (int_period >= WDT2_PERIOD_MAX)
elijahsj 1:8a094db1347f 98 return E_INVALID;
elijahsj 1:8a094db1347f 99
elijahsj 1:8a094db1347f 100 //unlock ctrl to be writable
elijahsj 1:8a094db1347f 101 MXC_WDT2->lock_ctrl = unlock_key;
elijahsj 1:8a094db1347f 102
elijahsj 1:8a094db1347f 103 //check to make sure it unlocked
elijahsj 1:8a094db1347f 104 if (MXC_WDT2->lock_ctrl & 0x01)
elijahsj 1:8a094db1347f 105 return E_BAD_STATE;
elijahsj 1:8a094db1347f 106
elijahsj 1:8a094db1347f 107 //stop timer and clear interval period
elijahsj 1:8a094db1347f 108 MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_INT_PERIOD | MXC_F_WDT2_CTRL_EN_TIMER);
elijahsj 1:8a094db1347f 109
elijahsj 1:8a094db1347f 110 //set interval period
elijahsj 1:8a094db1347f 111 MXC_WDT2->ctrl |= (int_period << MXC_F_WDT2_CTRL_INT_PERIOD_POS);
elijahsj 1:8a094db1347f 112
elijahsj 1:8a094db1347f 113 //enable timeout wake-up
elijahsj 1:8a094db1347f 114 interruptEnable |= MXC_F_WDT2_ENABLE_TIMEOUT;
elijahsj 1:8a094db1347f 115
elijahsj 1:8a094db1347f 116 //lock ctrl to read-only
elijahsj 1:8a094db1347f 117 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
elijahsj 1:8a094db1347f 118
elijahsj 1:8a094db1347f 119 // Enable wake-up
elijahsj 1:8a094db1347f 120 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG;
elijahsj 1:8a094db1347f 121
elijahsj 1:8a094db1347f 122 return E_NO_ERROR;
elijahsj 1:8a094db1347f 123 }
elijahsj 1:8a094db1347f 124
elijahsj 1:8a094db1347f 125 /* ************************************************************************* */
elijahsj 1:8a094db1347f 126 int WDT2_DisableWakeUp(uint8_t unlock_key)
elijahsj 1:8a094db1347f 127 {
elijahsj 1:8a094db1347f 128 //unlock register to be writable
elijahsj 1:8a094db1347f 129 MXC_WDT2->lock_ctrl = unlock_key;
elijahsj 1:8a094db1347f 130
elijahsj 1:8a094db1347f 131 //check to make sure it unlocked
elijahsj 1:8a094db1347f 132 if (MXC_WDT2->lock_ctrl & 0x01)
elijahsj 1:8a094db1347f 133 return E_BAD_STATE;
elijahsj 1:8a094db1347f 134
elijahsj 1:8a094db1347f 135 //disable timeout wake-up
elijahsj 1:8a094db1347f 136 interruptEnable &= ~MXC_F_WDT2_ENABLE_TIMEOUT;
elijahsj 1:8a094db1347f 137 MXC_WDT2->enable = interruptEnable;
elijahsj 1:8a094db1347f 138
elijahsj 1:8a094db1347f 139 //lock register to read-only
elijahsj 1:8a094db1347f 140 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
elijahsj 1:8a094db1347f 141
elijahsj 1:8a094db1347f 142 // disable wake-up
elijahsj 1:8a094db1347f 143 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG;
elijahsj 1:8a094db1347f 144
elijahsj 1:8a094db1347f 145 return E_NO_ERROR;
elijahsj 1:8a094db1347f 146 }
elijahsj 1:8a094db1347f 147
elijahsj 1:8a094db1347f 148 /* ************************************************************************* */
elijahsj 1:8a094db1347f 149 int WDT2_EnableReset(wdt2_period_t rst_period, uint8_t unlock_key)
elijahsj 1:8a094db1347f 150 {
elijahsj 1:8a094db1347f 151 // Make sure reset period is valid
elijahsj 1:8a094db1347f 152 if (rst_period >= WDT2_PERIOD_MAX)
elijahsj 1:8a094db1347f 153 return E_INVALID;
elijahsj 1:8a094db1347f 154
elijahsj 1:8a094db1347f 155 //unlock ctrl to be writable
elijahsj 1:8a094db1347f 156 MXC_WDT2->lock_ctrl = unlock_key;
elijahsj 1:8a094db1347f 157
elijahsj 1:8a094db1347f 158 //check to make sure it unlocked
elijahsj 1:8a094db1347f 159 if (MXC_WDT2->lock_ctrl & 0x01)
elijahsj 1:8a094db1347f 160 return E_BAD_STATE;
elijahsj 1:8a094db1347f 161
elijahsj 1:8a094db1347f 162 //stop timer and clear reset period
elijahsj 1:8a094db1347f 163 MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_RST_PERIOD | MXC_F_WDT2_CTRL_EN_TIMER);
elijahsj 1:8a094db1347f 164
elijahsj 1:8a094db1347f 165 //set reset period
elijahsj 1:8a094db1347f 166 MXC_WDT2->ctrl |= (rst_period << MXC_F_WDT2_CTRL_RST_PERIOD_POS);
elijahsj 1:8a094db1347f 167
elijahsj 1:8a094db1347f 168 //int flag has to be clear before interrupt enable can be written
elijahsj 1:8a094db1347f 169 MXC_WDT2->flags = MXC_F_WDT2_FLAGS_RESET_OUT;
elijahsj 1:8a094db1347f 170
elijahsj 1:8a094db1347f 171 //enable reset0
elijahsj 1:8a094db1347f 172 interruptEnable |= MXC_F_WDT2_ENABLE_RESET_OUT;
elijahsj 1:8a094db1347f 173
elijahsj 1:8a094db1347f 174 //lock ctrl to read-only
elijahsj 1:8a094db1347f 175 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
elijahsj 1:8a094db1347f 176
elijahsj 1:8a094db1347f 177 //enable RSTN on WDT2 reset
elijahsj 1:8a094db1347f 178 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG;
elijahsj 1:8a094db1347f 179
elijahsj 1:8a094db1347f 180 return E_NO_ERROR;
elijahsj 1:8a094db1347f 181 }
elijahsj 1:8a094db1347f 182
elijahsj 1:8a094db1347f 183 /* ************************************************************************* */
elijahsj 1:8a094db1347f 184 int WDT2_DisableReset(uint8_t unlock_key)
elijahsj 1:8a094db1347f 185 {
elijahsj 1:8a094db1347f 186 //unlock register to be writable
elijahsj 1:8a094db1347f 187 MXC_WDT2->lock_ctrl = unlock_key;
elijahsj 1:8a094db1347f 188
elijahsj 1:8a094db1347f 189 //check to make sure it unlocked
elijahsj 1:8a094db1347f 190 if (MXC_WDT2->lock_ctrl & 0x01)
elijahsj 1:8a094db1347f 191 return E_BAD_STATE;
elijahsj 1:8a094db1347f 192
elijahsj 1:8a094db1347f 193 //disable reset
elijahsj 1:8a094db1347f 194 interruptEnable &= ~MXC_F_WDT2_ENABLE_RESET_OUT;
elijahsj 1:8a094db1347f 195 MXC_WDT2->enable = interruptEnable;
elijahsj 1:8a094db1347f 196
elijahsj 1:8a094db1347f 197 //lock register to read-only
elijahsj 1:8a094db1347f 198 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
elijahsj 1:8a094db1347f 199
elijahsj 1:8a094db1347f 200 //disable RSTN on WDT2 reset
elijahsj 1:8a094db1347f 201 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG;
elijahsj 1:8a094db1347f 202
elijahsj 1:8a094db1347f 203 return E_NO_ERROR;
elijahsj 1:8a094db1347f 204 }
elijahsj 1:8a094db1347f 205
elijahsj 1:8a094db1347f 206 /* ************************************************************************* */
elijahsj 1:8a094db1347f 207 int WDT2_Start(uint8_t unlock_key)
elijahsj 1:8a094db1347f 208 {
elijahsj 1:8a094db1347f 209 //check if watchdog is already running
elijahsj 1:8a094db1347f 210 if(WDT2_IsActive())
elijahsj 1:8a094db1347f 211 return E_BAD_STATE;
elijahsj 1:8a094db1347f 212
elijahsj 1:8a094db1347f 213 //unlock ctrl to be writable
elijahsj 1:8a094db1347f 214 MXC_WDT2->lock_ctrl = unlock_key;
elijahsj 1:8a094db1347f 215
elijahsj 1:8a094db1347f 216 //check to make sure it unlocked
elijahsj 1:8a094db1347f 217 if (MXC_WDT2->lock_ctrl & 0x01)
elijahsj 1:8a094db1347f 218 return E_BAD_STATE;
elijahsj 1:8a094db1347f 219
elijahsj 1:8a094db1347f 220 WDT2_Reset();
elijahsj 1:8a094db1347f 221
elijahsj 1:8a094db1347f 222 //enable interrupts
elijahsj 1:8a094db1347f 223 MXC_WDT2->enable = interruptEnable;
elijahsj 1:8a094db1347f 224
elijahsj 1:8a094db1347f 225 //start timer
elijahsj 1:8a094db1347f 226 MXC_WDT2->ctrl |= (MXC_F_WDT2_CTRL_EN_TIMER);
elijahsj 1:8a094db1347f 227
elijahsj 1:8a094db1347f 228 //lock ctrl to read-only
elijahsj 1:8a094db1347f 229 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
elijahsj 1:8a094db1347f 230
elijahsj 1:8a094db1347f 231 return E_NO_ERROR;
elijahsj 1:8a094db1347f 232 }
elijahsj 1:8a094db1347f 233
elijahsj 1:8a094db1347f 234 /* ************************************************************************* */
elijahsj 1:8a094db1347f 235 void WDT2_Reset(void)
elijahsj 1:8a094db1347f 236 {
elijahsj 1:8a094db1347f 237 //reset the watchdog counter
elijahsj 1:8a094db1347f 238 MXC_WDT2->clear = MXC_V_WDT2_RESET_KEY_0;
elijahsj 1:8a094db1347f 239 MXC_WDT2->clear = MXC_V_WDT2_RESET_KEY_1;
elijahsj 1:8a094db1347f 240
elijahsj 1:8a094db1347f 241 //clear all interrupt flags
elijahsj 1:8a094db1347f 242 MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL;
elijahsj 1:8a094db1347f 243
elijahsj 1:8a094db1347f 244 //wait for all interrupts to clear
elijahsj 1:8a094db1347f 245 while(MXC_WDT2->flags != 0) {
elijahsj 1:8a094db1347f 246 MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL;
elijahsj 1:8a094db1347f 247 }
elijahsj 1:8a094db1347f 248
elijahsj 1:8a094db1347f 249 return;
elijahsj 1:8a094db1347f 250 }
elijahsj 1:8a094db1347f 251
elijahsj 1:8a094db1347f 252 /* ************************************************************************* */
elijahsj 1:8a094db1347f 253 int WDT2_Stop(uint8_t unlock_key)
elijahsj 1:8a094db1347f 254 {
elijahsj 1:8a094db1347f 255 //check if watchdog is not running
elijahsj 1:8a094db1347f 256 if(!WDT2_IsActive())
elijahsj 1:8a094db1347f 257 return E_BAD_STATE;
elijahsj 1:8a094db1347f 258
elijahsj 1:8a094db1347f 259 //unlock ctrl to be writable
elijahsj 1:8a094db1347f 260 MXC_WDT2->lock_ctrl = unlock_key;
elijahsj 1:8a094db1347f 261
elijahsj 1:8a094db1347f 262 //check to make sure it unlocked
elijahsj 1:8a094db1347f 263 if (MXC_WDT2->lock_ctrl & 0x01)
elijahsj 1:8a094db1347f 264 return E_BAD_STATE;
elijahsj 1:8a094db1347f 265
elijahsj 1:8a094db1347f 266 //disabled the timer and interrupts
elijahsj 1:8a094db1347f 267 MXC_WDT2->enable = 0;
elijahsj 1:8a094db1347f 268 MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_EN_TIMER);
elijahsj 1:8a094db1347f 269
elijahsj 1:8a094db1347f 270 //lock ctrl to read-only
elijahsj 1:8a094db1347f 271 MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
elijahsj 1:8a094db1347f 272
elijahsj 1:8a094db1347f 273 return E_NO_ERROR;
elijahsj 1:8a094db1347f 274 }
elijahsj 1:8a094db1347f 275 /**@} end of group wdt2*/