Elijah Stanger-Jones / mbed-dev-f303

test

targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.c@1:8a094db1347f, 2020-11-09 (annotated)

Committer:
elijahsj
Date:
Mon Nov 09 00:02:47 2020 -0500
Revision:
1:8a094db1347f
test

Who changed what in which revision?

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elijahsj 1:8a094db1347f 1 /**
elijahsj 1:8a094db1347f 2 * @file
elijahsj 1:8a094db1347f 3 * @brief Peripheral Management Unit (PMU) Function Implementations.
elijahsj 1:8a094db1347f 4 */
elijahsj 1:8a094db1347f 5 /* *****************************************************************************
elijahsj 1:8a094db1347f 6 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
elijahsj 1:8a094db1347f 7 *
elijahsj 1:8a094db1347f 8 * Permission is hereby granted, free of charge, to any person obtaining a
elijahsj 1:8a094db1347f 9 * copy of this software and associated documentation files (the "Software"),
elijahsj 1:8a094db1347f 10 * to deal in the Software without restriction, including without limitation
elijahsj 1:8a094db1347f 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
elijahsj 1:8a094db1347f 12 * and/or sell copies of the Software, and to permit persons to whom the
elijahsj 1:8a094db1347f 13 * Software is furnished to do so, subject to the following conditions:
elijahsj 1:8a094db1347f 14 *
elijahsj 1:8a094db1347f 15 * The above copyright notice and this permission notice shall be included
elijahsj 1:8a094db1347f 16 * in all copies or substantial portions of the Software.
elijahsj 1:8a094db1347f 17 *
elijahsj 1:8a094db1347f 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
elijahsj 1:8a094db1347f 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
elijahsj 1:8a094db1347f 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
elijahsj 1:8a094db1347f 21 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
elijahsj 1:8a094db1347f 22 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
elijahsj 1:8a094db1347f 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
elijahsj 1:8a094db1347f 24 * OTHER DEALINGS IN THE SOFTWARE.
elijahsj 1:8a094db1347f 25 *
elijahsj 1:8a094db1347f 26 * Except as contained in this notice, the name of Maxim Integrated
elijahsj 1:8a094db1347f 27 * Products, Inc. shall not be used except as stated in the Maxim Integrated
elijahsj 1:8a094db1347f 28 * Products, Inc. Branding Policy.
elijahsj 1:8a094db1347f 29 *
elijahsj 1:8a094db1347f 30 * The mere transfer of this software does not imply any licenses
elijahsj 1:8a094db1347f 31 * of trade secrets, proprietary technology, copyrights, patents,
elijahsj 1:8a094db1347f 32 * trademarks, maskwork rights, or any other form of intellectual
elijahsj 1:8a094db1347f 33 * property whatsoever. Maxim Integrated Products, Inc. retains all
elijahsj 1:8a094db1347f 34 * ownership rights.
elijahsj 1:8a094db1347f 35 *
elijahsj 1:8a094db1347f 36 * $Date: 2016-09-08 17:44:03 -0500 (Thu, 08 Sep 2016) $
elijahsj 1:8a094db1347f 37 * $Revision: 24328 $
elijahsj 1:8a094db1347f 38 *
elijahsj 1:8a094db1347f 39 **************************************************************************** */
elijahsj 1:8a094db1347f 40
elijahsj 1:8a094db1347f 41 /* **** Includes **** */
elijahsj 1:8a094db1347f 42 #include <stdio.h>
elijahsj 1:8a094db1347f 43 #include <stddef.h>
elijahsj 1:8a094db1347f 44 #include "mxc_config.h"
elijahsj 1:8a094db1347f 45 #include "mxc_assert.h"
elijahsj 1:8a094db1347f 46 #include "pmu.h"
elijahsj 1:8a094db1347f 47 /**
elijahsj 1:8a094db1347f 48 * @ingroup pmuGroup
elijahsj 1:8a094db1347f 49 * @{
elijahsj 1:8a094db1347f 50 */
elijahsj 1:8a094db1347f 51
elijahsj 1:8a094db1347f 52 #if (MXC_PMU_REV == 0)
elijahsj 1:8a094db1347f 53 /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 -- workaround */
elijahsj 1:8a094db1347f 54 #include "clkman_regs.h"
elijahsj 1:8a094db1347f 55 /* Channel 5 infinite loop program */
elijahsj 1:8a094db1347f 56 static const uint32_t pmu_0[] = {
elijahsj 1:8a094db1347f 57 PMU_JUMP(0, 0, (uint32_t)pmu_0)
elijahsj 1:8a094db1347f 58 };
elijahsj 1:8a094db1347f 59 #endif
elijahsj 1:8a094db1347f 60
elijahsj 1:8a094db1347f 61 /* **** Local Function Prototypes **** */
elijahsj 1:8a094db1347f 62 static void (*callbacks[MXC_CFG_PMU_CHANNELS])(int);
elijahsj 1:8a094db1347f 63
elijahsj 1:8a094db1347f 64
elijahsj 1:8a094db1347f 65 /* ************************************************************************* */
elijahsj 1:8a094db1347f 66 void PMU_Handler(void)
elijahsj 1:8a094db1347f 67 {
elijahsj 1:8a094db1347f 68 int channel;
elijahsj 1:8a094db1347f 69 uint32_t cfg1, cfg2;
elijahsj 1:8a094db1347f 70 mxc_pmu_regs_t *MXC_PMUn;
elijahsj 1:8a094db1347f 71
elijahsj 1:8a094db1347f 72 for (channel = 0; channel < MXC_CFG_PMU_CHANNELS; channel++) {
elijahsj 1:8a094db1347f 73 MXC_PMUn = &MXC_PMU0[channel];
elijahsj 1:8a094db1347f 74
elijahsj 1:8a094db1347f 75 if (MXC_PMUn->cfg & MXC_F_PMU_CFG_INTERRUPT) {
elijahsj 1:8a094db1347f 76 cfg1 = MXC_PMUn->cfg;
elijahsj 1:8a094db1347f 77 /* Since any set flags will be cleared by the write-back below, mask them off */
elijahsj 1:8a094db1347f 78 cfg2 = cfg1 & ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT);
elijahsj 1:8a094db1347f 79
elijahsj 1:8a094db1347f 80 /* Clear the interrupt flag */
elijahsj 1:8a094db1347f 81 MXC_PMUn->cfg = cfg2 | MXC_F_PMU_CFG_INTERRUPT;
elijahsj 1:8a094db1347f 82
elijahsj 1:8a094db1347f 83 if (callbacks[channel]) {
elijahsj 1:8a094db1347f 84 callbacks[channel](cfg1);
elijahsj 1:8a094db1347f 85 }
elijahsj 1:8a094db1347f 86 }
elijahsj 1:8a094db1347f 87 }
elijahsj 1:8a094db1347f 88 }
elijahsj 1:8a094db1347f 89
elijahsj 1:8a094db1347f 90 /* ************************************************************************* */
elijahsj 1:8a094db1347f 91 int PMU_Start(unsigned int channel, const void *program_address, pmu_callback callback)
elijahsj 1:8a094db1347f 92 {
elijahsj 1:8a094db1347f 93 if(channel >= MXC_CFG_PMU_CHANNELS)
elijahsj 1:8a094db1347f 94 return E_BAD_PARAM;
elijahsj 1:8a094db1347f 95
elijahsj 1:8a094db1347f 96 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
elijahsj 1:8a094db1347f 97 uint32_t cfg = MXC_PMUn->cfg;
elijahsj 1:8a094db1347f 98
elijahsj 1:8a094db1347f 99 /* is this channel already running? */
elijahsj 1:8a094db1347f 100 if (cfg & MXC_F_PMU_CFG_ENABLE) {
elijahsj 1:8a094db1347f 101 return E_BUSY;
elijahsj 1:8a094db1347f 102 }
elijahsj 1:8a094db1347f 103
elijahsj 1:8a094db1347f 104 #if (MXC_PMU_REV == 0)
elijahsj 1:8a094db1347f 105 /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 */
elijahsj 1:8a094db1347f 106 if (channel == 5) {
elijahsj 1:8a094db1347f 107 /* Channel 5 is used for the work-around */
elijahsj 1:8a094db1347f 108 return E_BUSY;
elijahsj 1:8a094db1347f 109 }
elijahsj 1:8a094db1347f 110 /* Select always-ON clock for PMU */
elijahsj 1:8a094db1347f 111 MXC_CLKMAN->clk_gate_ctrl0 |= MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER;
elijahsj 1:8a094db1347f 112 /* Start channel 5 with infinite-loop program */
elijahsj 1:8a094db1347f 113 MXC_PMU5->cfg &= ~MXC_F_PMU_CFG_ENABLE; /* Clear enable and wipe W1C flags */
elijahsj 1:8a094db1347f 114 MXC_PMU5->dscadr = (uint32_t)pmu_0;
elijahsj 1:8a094db1347f 115 MXC_PMU5->cfg = MXC_F_PMU_CFG_ENABLE | (0x1c << MXC_F_PMU_CFG_BURST_SIZE_POS);
elijahsj 1:8a094db1347f 116 #endif
elijahsj 1:8a094db1347f 117 /* Set callback */
elijahsj 1:8a094db1347f 118 callbacks[channel] = callback;
elijahsj 1:8a094db1347f 119
elijahsj 1:8a094db1347f 120 /* Set start op-code */
elijahsj 1:8a094db1347f 121 MXC_PMUn->dscadr = (uint32_t)program_address;
elijahsj 1:8a094db1347f 122
elijahsj 1:8a094db1347f 123 /* Configure the channel */
elijahsj 1:8a094db1347f 124 cfg = (cfg & ~(MXC_F_PMU_CFG_MANUAL | MXC_F_PMU_CFG_BURST_SIZE)) | (0x1c << MXC_F_PMU_CFG_BURST_SIZE_POS);
elijahsj 1:8a094db1347f 125
elijahsj 1:8a094db1347f 126 /* Enable if necessary */
elijahsj 1:8a094db1347f 127 if (callback) {
elijahsj 1:8a094db1347f 128 cfg |= MXC_F_PMU_CFG_INT_EN;
elijahsj 1:8a094db1347f 129 } else {
elijahsj 1:8a094db1347f 130 cfg &= ~MXC_F_PMU_CFG_INT_EN;
elijahsj 1:8a094db1347f 131 }
elijahsj 1:8a094db1347f 132
elijahsj 1:8a094db1347f 133 /* Start the channel */
elijahsj 1:8a094db1347f 134 cfg |= MXC_F_PMU_CFG_ENABLE;
elijahsj 1:8a094db1347f 135
elijahsj 1:8a094db1347f 136 /*If any W1C flags are set, this write will clear them */
elijahsj 1:8a094db1347f 137 MXC_PMUn->cfg = cfg;
elijahsj 1:8a094db1347f 138
elijahsj 1:8a094db1347f 139 return E_NO_ERROR;
elijahsj 1:8a094db1347f 140 }
elijahsj 1:8a094db1347f 141
elijahsj 1:8a094db1347f 142 /* ************************************************************************* */
elijahsj 1:8a094db1347f 143 void PMU_Stop(unsigned int channel)
elijahsj 1:8a094db1347f 144 {
elijahsj 1:8a094db1347f 145 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
elijahsj 1:8a094db1347f 146 uint32_t cfg = MXC_PMUn->cfg;
elijahsj 1:8a094db1347f 147
elijahsj 1:8a094db1347f 148 /* Since any set flags will be cleared by the write-back below, mask them off */
elijahsj 1:8a094db1347f 149 cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT);
elijahsj 1:8a094db1347f 150
elijahsj 1:8a094db1347f 151 /* Clear the enable bit to stop the channel */
elijahsj 1:8a094db1347f 152 cfg &= ~MXC_F_PMU_CFG_ENABLE;
elijahsj 1:8a094db1347f 153
elijahsj 1:8a094db1347f 154 MXC_PMUn->cfg = cfg;
elijahsj 1:8a094db1347f 155
elijahsj 1:8a094db1347f 156 /* Remove callback */
elijahsj 1:8a094db1347f 157 callbacks[channel] = NULL;
elijahsj 1:8a094db1347f 158
elijahsj 1:8a094db1347f 159 #if (MXC_PMU_REV == 0)
elijahsj 1:8a094db1347f 160 /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 */
elijahsj 1:8a094db1347f 161 /* Check channels 0-4 for any running channels. If none found, stop channel 5 */
elijahsj 1:8a094db1347f 162 if ((MXC_PMU0->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
elijahsj 1:8a094db1347f 163 (MXC_PMU1->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
elijahsj 1:8a094db1347f 164 (MXC_PMU2->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
elijahsj 1:8a094db1347f 165 (MXC_PMU3->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
elijahsj 1:8a094db1347f 166 (MXC_PMU4->cfg & MXC_F_PMU_CFG_ENABLE) == 0) {
elijahsj 1:8a094db1347f 167 MXC_PMU5->cfg &= ~MXC_F_PMU_CFG_ENABLE;
elijahsj 1:8a094db1347f 168 }
elijahsj 1:8a094db1347f 169 #endif
elijahsj 1:8a094db1347f 170
elijahsj 1:8a094db1347f 171 }
elijahsj 1:8a094db1347f 172
elijahsj 1:8a094db1347f 173 /* ************************************************************************* */
elijahsj 1:8a094db1347f 174 int PMU_SetCounter(unsigned int channel, unsigned int counter, uint16_t value)
elijahsj 1:8a094db1347f 175 {
elijahsj 1:8a094db1347f 176 if((channel >= MXC_CFG_PMU_CHANNELS) || counter > 1)
elijahsj 1:8a094db1347f 177 return E_BAD_PARAM;
elijahsj 1:8a094db1347f 178
elijahsj 1:8a094db1347f 179 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
elijahsj 1:8a094db1347f 180
elijahsj 1:8a094db1347f 181 if (counter == 0) {
elijahsj 1:8a094db1347f 182 MXC_PMUn->loop = (MXC_PMUn->loop & ~MXC_F_PMU_LOOP_COUNTER_0) | (value << MXC_F_PMU_LOOP_COUNTER_0_POS);
elijahsj 1:8a094db1347f 183 } else {
elijahsj 1:8a094db1347f 184 MXC_PMUn->loop = (MXC_PMUn->loop & ~MXC_F_PMU_LOOP_COUNTER_1) | (value << MXC_F_PMU_LOOP_COUNTER_1_POS);
elijahsj 1:8a094db1347f 185 }
elijahsj 1:8a094db1347f 186
elijahsj 1:8a094db1347f 187 return E_NO_ERROR;
elijahsj 1:8a094db1347f 188 }
elijahsj 1:8a094db1347f 189
elijahsj 1:8a094db1347f 190 /* ************************************************************************* */
elijahsj 1:8a094db1347f 191 int PMU_SetTimeout(unsigned int channel, pmu_ps_sel_t timeoutClkScale, pmu_to_sel_t timeoutTicks)
elijahsj 1:8a094db1347f 192 {
elijahsj 1:8a094db1347f 193 if(channel >= MXC_CFG_PMU_CHANNELS)
elijahsj 1:8a094db1347f 194 return E_BAD_PARAM;
elijahsj 1:8a094db1347f 195
elijahsj 1:8a094db1347f 196 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
elijahsj 1:8a094db1347f 197 uint32_t cfg = MXC_PMUn->cfg;
elijahsj 1:8a094db1347f 198
elijahsj 1:8a094db1347f 199 /* Since any set flags will be cleared by the write-back below, mask them off */
elijahsj 1:8a094db1347f 200 cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT);
elijahsj 1:8a094db1347f 201
elijahsj 1:8a094db1347f 202 /* Adjust timeout settings */
elijahsj 1:8a094db1347f 203 cfg &= ~(MXC_F_PMU_CFG_TO_SEL | MXC_F_PMU_CFG_PS_SEL);
elijahsj 1:8a094db1347f 204 cfg |= ((timeoutClkScale << MXC_F_PMU_CFG_PS_SEL_POS) & MXC_F_PMU_CFG_PS_SEL) |
elijahsj 1:8a094db1347f 205 ((timeoutTicks << MXC_F_PMU_CFG_TO_SEL_POS) & MXC_F_PMU_CFG_TO_SEL);
elijahsj 1:8a094db1347f 206
elijahsj 1:8a094db1347f 207 MXC_PMUn->cfg = cfg;
elijahsj 1:8a094db1347f 208
elijahsj 1:8a094db1347f 209 return E_NO_ERROR;
elijahsj 1:8a094db1347f 210 }
elijahsj 1:8a094db1347f 211
elijahsj 1:8a094db1347f 212 /* ************************************************************************* */
elijahsj 1:8a094db1347f 213 uint32_t PMU_GetFlags(unsigned int channel)
elijahsj 1:8a094db1347f 214 {
elijahsj 1:8a094db1347f 215 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
elijahsj 1:8a094db1347f 216 uint32_t cfg = MXC_PMUn->cfg;
elijahsj 1:8a094db1347f 217
elijahsj 1:8a094db1347f 218 /* Mask off configuration bits leaving only flag bits */
elijahsj 1:8a094db1347f 219 cfg &= ~(MXC_F_PMU_CFG_ENABLE | MXC_F_PMU_CFG_MANUAL | MXC_F_PMU_CFG_TO_SEL | MXC_F_PMU_CFG_PS_SEL |
elijahsj 1:8a094db1347f 220 MXC_F_PMU_CFG_INT_EN | MXC_F_PMU_CFG_BURST_SIZE);
elijahsj 1:8a094db1347f 221
elijahsj 1:8a094db1347f 222 return cfg;
elijahsj 1:8a094db1347f 223 }
elijahsj 1:8a094db1347f 224
elijahsj 1:8a094db1347f 225 /* ************************************************************************* */
elijahsj 1:8a094db1347f 226 void PMU_ClearFlags(unsigned int channel, unsigned int mask)
elijahsj 1:8a094db1347f 227 {
elijahsj 1:8a094db1347f 228 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
elijahsj 1:8a094db1347f 229 uint32_t cfg = MXC_PMUn->cfg;
elijahsj 1:8a094db1347f 230
elijahsj 1:8a094db1347f 231 /* Since any set flags will be cleared by the write-back below, mask them off */
elijahsj 1:8a094db1347f 232 cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT);
elijahsj 1:8a094db1347f 233
elijahsj 1:8a094db1347f 234 /* Now, apply the caller-supplied bits to clear */
elijahsj 1:8a094db1347f 235 cfg |= mask;
elijahsj 1:8a094db1347f 236
elijahsj 1:8a094db1347f 237 MXC_PMUn->cfg = cfg;
elijahsj 1:8a094db1347f 238 }
elijahsj 1:8a094db1347f 239
elijahsj 1:8a094db1347f 240 /* ************************************************************************* */
elijahsj 1:8a094db1347f 241 uint32_t PMU_IsActive(unsigned int channel)
elijahsj 1:8a094db1347f 242 {
elijahsj 1:8a094db1347f 243 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
elijahsj 1:8a094db1347f 244 return (MXC_PMUn->cfg & MXC_F_PMU_CFG_ENABLE);
elijahsj 1:8a094db1347f 245 }
elijahsj 1:8a094db1347f 246 /**@} end of ingroup pmuGroup */