Elijah Stanger-Jones / mbed-dev-f303

test

targets/TARGET_NUVOTON/TARGET_M451/serial_api.c@2:4364577b5ad8, 2020-11-09 (annotated)

Committer:
elijahsj
Date:
Mon Nov 09 00:33:19 2020 -0500
Revision:
2:4364577b5ad8
Parent:
1:8a094db1347f 
copied mbed library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elijahsj 1:8a094db1347f 1 /* mbed Microcontroller Library
elijahsj 1:8a094db1347f 2 * Copyright (c) 2015-2016 Nuvoton
elijahsj 1:8a094db1347f 3 *
elijahsj 1:8a094db1347f 4 * Licensed under the Apache License, Version 2.0 (the "License");
elijahsj 1:8a094db1347f 5 * you may not use this file except in compliance with the License.
elijahsj 1:8a094db1347f 6 * You may obtain a copy of the License at
elijahsj 1:8a094db1347f 7 *
elijahsj 1:8a094db1347f 8 * http://www.apache.org/licenses/LICENSE-2.0
elijahsj 1:8a094db1347f 9 *
elijahsj 1:8a094db1347f 10 * Unless required by applicable law or agreed to in writing, software
elijahsj 1:8a094db1347f 11 * distributed under the License is distributed on an "AS IS" BASIS,
elijahsj 1:8a094db1347f 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elijahsj 1:8a094db1347f 13 * See the License for the specific language governing permissions and
elijahsj 1:8a094db1347f 14 * limitations under the License.
elijahsj 1:8a094db1347f 15 */
elijahsj 1:8a094db1347f 16
elijahsj 1:8a094db1347f 17 #include "serial_api.h"
elijahsj 1:8a094db1347f 18
elijahsj 1:8a094db1347f 19 #if DEVICE_SERIAL
elijahsj 1:8a094db1347f 20
elijahsj 1:8a094db1347f 21 #include "cmsis.h"
elijahsj 1:8a094db1347f 22 #include "mbed_error.h"
elijahsj 1:8a094db1347f 23 #include "mbed_assert.h"
elijahsj 1:8a094db1347f 24 #include "PeripheralPins.h"
elijahsj 1:8a094db1347f 25 #include "nu_modutil.h"
elijahsj 1:8a094db1347f 26 #include "nu_bitutil.h"
elijahsj 1:8a094db1347f 27 #include <string.h>
elijahsj 1:8a094db1347f 28
elijahsj 1:8a094db1347f 29 #if DEVICE_SERIAL_ASYNCH
elijahsj 1:8a094db1347f 30 #include "dma_api.h"
elijahsj 1:8a094db1347f 31 #include "dma.h"
elijahsj 1:8a094db1347f 32 #endif
elijahsj 1:8a094db1347f 33
elijahsj 1:8a094db1347f 34 struct nu_uart_var {
elijahsj 1:8a094db1347f 35 uint32_t ref_cnt; // Reference count of the H/W module
elijahsj 1:8a094db1347f 36 serial_t * obj;
elijahsj 1:8a094db1347f 37 uint32_t fifo_size_tx;
elijahsj 1:8a094db1347f 38 uint32_t fifo_size_rx;
elijahsj 1:8a094db1347f 39 void (*vec)(void);
elijahsj 1:8a094db1347f 40 #if DEVICE_SERIAL_ASYNCH
elijahsj 1:8a094db1347f 41 void (*vec_async)(void);
elijahsj 1:8a094db1347f 42 uint8_t pdma_perp_tx;
elijahsj 1:8a094db1347f 43 uint8_t pdma_perp_rx;
elijahsj 1:8a094db1347f 44 #endif
elijahsj 1:8a094db1347f 45 };
elijahsj 1:8a094db1347f 46
elijahsj 1:8a094db1347f 47 static void uart0_vec(void);
elijahsj 1:8a094db1347f 48 static void uart1_vec(void);
elijahsj 1:8a094db1347f 49 static void uart2_vec(void);
elijahsj 1:8a094db1347f 50 static void uart3_vec(void);
elijahsj 1:8a094db1347f 51 static void uart_irq(serial_t *obj);
elijahsj 1:8a094db1347f 52
elijahsj 1:8a094db1347f 53 #if DEVICE_SERIAL_ASYNCH
elijahsj 1:8a094db1347f 54 static void uart0_vec_async(void);
elijahsj 1:8a094db1347f 55 static void uart1_vec_async(void);
elijahsj 1:8a094db1347f 56 static void uart2_vec_async(void);
elijahsj 1:8a094db1347f 57 static void uart3_vec_async(void);
elijahsj 1:8a094db1347f 58 static void uart_irq_async(serial_t *obj);
elijahsj 1:8a094db1347f 59
elijahsj 1:8a094db1347f 60 static void uart_dma_handler_tx(uint32_t id, uint32_t event);
elijahsj 1:8a094db1347f 61 static void uart_dma_handler_rx(uint32_t id, uint32_t event);
elijahsj 1:8a094db1347f 62
elijahsj 1:8a094db1347f 63 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
elijahsj 1:8a094db1347f 64 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
elijahsj 1:8a094db1347f 65 static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable);
elijahsj 1:8a094db1347f 66 static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq);
elijahsj 1:8a094db1347f 67 static int serial_write_async(serial_t *obj);
elijahsj 1:8a094db1347f 68 static int serial_read_async(serial_t *obj);
elijahsj 1:8a094db1347f 69
elijahsj 1:8a094db1347f 70 static uint32_t serial_rx_event_check(serial_t *obj);
elijahsj 1:8a094db1347f 71 static uint32_t serial_tx_event_check(serial_t *obj);
elijahsj 1:8a094db1347f 72
elijahsj 1:8a094db1347f 73 static int serial_is_tx_complete(serial_t *obj);
elijahsj 1:8a094db1347f 74 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
elijahsj 1:8a094db1347f 75
elijahsj 1:8a094db1347f 76 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
elijahsj 1:8a094db1347f 77 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
elijahsj 1:8a094db1347f 78 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
elijahsj 1:8a094db1347f 79 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
elijahsj 1:8a094db1347f 80 static int serial_is_rx_complete(serial_t *obj);
elijahsj 1:8a094db1347f 81
elijahsj 1:8a094db1347f 82 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
elijahsj 1:8a094db1347f 83 static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
elijahsj 1:8a094db1347f 84 #endif
elijahsj 1:8a094db1347f 85
elijahsj 1:8a094db1347f 86 static struct nu_uart_var uart0_var = {
elijahsj 1:8a094db1347f 87 .ref_cnt = 0,
elijahsj 1:8a094db1347f 88 .obj = NULL,
elijahsj 1:8a094db1347f 89 .fifo_size_tx = 16,
elijahsj 1:8a094db1347f 90 .fifo_size_rx = 16,
elijahsj 1:8a094db1347f 91 .vec = uart0_vec,
elijahsj 1:8a094db1347f 92 #if DEVICE_SERIAL_ASYNCH
elijahsj 1:8a094db1347f 93 .vec_async = uart0_vec_async,
elijahsj 1:8a094db1347f 94 .pdma_perp_tx = PDMA_UART0_TX,
elijahsj 1:8a094db1347f 95 .pdma_perp_rx = PDMA_UART0_RX
elijahsj 1:8a094db1347f 96 #endif
elijahsj 1:8a094db1347f 97 };
elijahsj 1:8a094db1347f 98 static struct nu_uart_var uart1_var = {
elijahsj 1:8a094db1347f 99 .ref_cnt = 0,
elijahsj 1:8a094db1347f 100 .obj = NULL,
elijahsj 1:8a094db1347f 101 .fifo_size_tx = 16,
elijahsj 1:8a094db1347f 102 .fifo_size_rx = 16,
elijahsj 1:8a094db1347f 103 .vec = uart1_vec,
elijahsj 1:8a094db1347f 104 #if DEVICE_SERIAL_ASYNCH
elijahsj 1:8a094db1347f 105 .vec_async = uart1_vec_async,
elijahsj 1:8a094db1347f 106 .pdma_perp_tx = PDMA_UART1_TX,
elijahsj 1:8a094db1347f 107 .pdma_perp_rx = PDMA_UART1_RX
elijahsj 1:8a094db1347f 108 #endif
elijahsj 1:8a094db1347f 109 };
elijahsj 1:8a094db1347f 110 static struct nu_uart_var uart2_var = {
elijahsj 1:8a094db1347f 111 .ref_cnt = 0,
elijahsj 1:8a094db1347f 112 .obj = NULL,
elijahsj 1:8a094db1347f 113 .fifo_size_tx = 16,
elijahsj 1:8a094db1347f 114 .fifo_size_rx = 16,
elijahsj 1:8a094db1347f 115 .vec = uart2_vec,
elijahsj 1:8a094db1347f 116 #if DEVICE_SERIAL_ASYNCH
elijahsj 1:8a094db1347f 117 .vec_async = uart2_vec_async,
elijahsj 1:8a094db1347f 118 .pdma_perp_tx = PDMA_UART2_TX,
elijahsj 1:8a094db1347f 119 .pdma_perp_rx = PDMA_UART2_RX
elijahsj 1:8a094db1347f 120 #endif
elijahsj 1:8a094db1347f 121 };
elijahsj 1:8a094db1347f 122 static struct nu_uart_var uart3_var = {
elijahsj 1:8a094db1347f 123 .ref_cnt = 0,
elijahsj 1:8a094db1347f 124 .obj = NULL,
elijahsj 1:8a094db1347f 125 .fifo_size_tx = 16,
elijahsj 1:8a094db1347f 126 .fifo_size_rx = 16,
elijahsj 1:8a094db1347f 127 .vec = uart3_vec,
elijahsj 1:8a094db1347f 128 #if DEVICE_SERIAL_ASYNCH
elijahsj 1:8a094db1347f 129 .vec_async = uart3_vec_async,
elijahsj 1:8a094db1347f 130 .pdma_perp_tx = PDMA_UART3_TX,
elijahsj 1:8a094db1347f 131 .pdma_perp_rx = PDMA_UART3_RX
elijahsj 1:8a094db1347f 132 #endif
elijahsj 1:8a094db1347f 133 };
elijahsj 1:8a094db1347f 134
elijahsj 1:8a094db1347f 135
elijahsj 1:8a094db1347f 136 int stdio_uart_inited = 0;
elijahsj 1:8a094db1347f 137 serial_t stdio_uart;
elijahsj 1:8a094db1347f 138 static uint32_t uart_modinit_mask = 0;
elijahsj 1:8a094db1347f 139
elijahsj 1:8a094db1347f 140 static const struct nu_modinit_s uart_modinit_tab[] = {
elijahsj 1:8a094db1347f 141 {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
elijahsj 1:8a094db1347f 142 {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
elijahsj 1:8a094db1347f 143 {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
elijahsj 1:8a094db1347f 144 {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
elijahsj 1:8a094db1347f 145
elijahsj 1:8a094db1347f 146 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
elijahsj 1:8a094db1347f 147 };
elijahsj 1:8a094db1347f 148
elijahsj 1:8a094db1347f 149 extern void mbed_sdk_init(void);
elijahsj 1:8a094db1347f 150
elijahsj 1:8a094db1347f 151 void serial_init(serial_t *obj, PinName tx, PinName rx)
elijahsj 1:8a094db1347f 152 {
elijahsj 1:8a094db1347f 153 // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
elijahsj 1:8a094db1347f 154 mbed_sdk_init();
elijahsj 1:8a094db1347f 155
elijahsj 1:8a094db1347f 156 // Determine which UART_x the pins are used for
elijahsj 1:8a094db1347f 157 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
elijahsj 1:8a094db1347f 158 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
elijahsj 1:8a094db1347f 159 // Get the peripheral name (UART_x) from the pins and assign it to the object
elijahsj 1:8a094db1347f 160 obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
elijahsj 1:8a094db1347f 161 MBED_ASSERT((int)obj->serial.uart != NC);
elijahsj 1:8a094db1347f 162
elijahsj 1:8a094db1347f 163 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 164 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 165 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 166
elijahsj 1:8a094db1347f 167 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
elijahsj 1:8a094db1347f 168
elijahsj 1:8a094db1347f 169 if (! var->ref_cnt) {
elijahsj 1:8a094db1347f 170 // Reset this module
elijahsj 1:8a094db1347f 171 SYS_ResetModule(modinit->rsetidx);
elijahsj 1:8a094db1347f 172
elijahsj 1:8a094db1347f 173 // Select IP clock source
elijahsj 1:8a094db1347f 174 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
elijahsj 1:8a094db1347f 175 // Enable IP clock
elijahsj 1:8a094db1347f 176 CLK_EnableModuleClock(modinit->clkidx);
elijahsj 1:8a094db1347f 177
elijahsj 1:8a094db1347f 178 pinmap_pinout(tx, PinMap_UART_TX);
elijahsj 1:8a094db1347f 179 pinmap_pinout(rx, PinMap_UART_RX);
elijahsj 1:8a094db1347f 180
elijahsj 1:8a094db1347f 181 obj->serial.pin_tx = tx;
elijahsj 1:8a094db1347f 182 obj->serial.pin_rx = rx;
elijahsj 1:8a094db1347f 183 }
elijahsj 1:8a094db1347f 184 var->ref_cnt ++;
elijahsj 1:8a094db1347f 185
elijahsj 1:8a094db1347f 186 // Configure the UART module and set its baudrate
elijahsj 1:8a094db1347f 187 serial_baud(obj, 9600);
elijahsj 1:8a094db1347f 188 // Configure data bits, parity, and stop bits
elijahsj 1:8a094db1347f 189 serial_format(obj, 8, ParityNone, 1);
elijahsj 1:8a094db1347f 190
elijahsj 1:8a094db1347f 191 obj->serial.vec = var->vec;
elijahsj 1:8a094db1347f 192 obj->serial.irq_en = 0;
elijahsj 1:8a094db1347f 193
elijahsj 1:8a094db1347f 194 #if DEVICE_SERIAL_ASYNCH
elijahsj 1:8a094db1347f 195 obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
elijahsj 1:8a094db1347f 196 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
elijahsj 1:8a094db1347f 197 obj->serial.event = 0;
elijahsj 1:8a094db1347f 198 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
elijahsj 1:8a094db1347f 199 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
elijahsj 1:8a094db1347f 200 #endif
elijahsj 1:8a094db1347f 201
elijahsj 1:8a094db1347f 202 // For stdio management
elijahsj 1:8a094db1347f 203 if (obj->serial.uart == STDIO_UART) {
elijahsj 1:8a094db1347f 204 stdio_uart_inited = 1;
elijahsj 1:8a094db1347f 205 memcpy(&stdio_uart, obj, sizeof(serial_t));
elijahsj 1:8a094db1347f 206 }
elijahsj 1:8a094db1347f 207
elijahsj 1:8a094db1347f 208 if (var->ref_cnt) {
elijahsj 1:8a094db1347f 209 // Mark this module to be inited.
elijahsj 1:8a094db1347f 210 int i = modinit - uart_modinit_tab;
elijahsj 1:8a094db1347f 211 uart_modinit_mask |= 1 << i;
elijahsj 1:8a094db1347f 212 }
elijahsj 1:8a094db1347f 213 }
elijahsj 1:8a094db1347f 214
elijahsj 1:8a094db1347f 215 void serial_free(serial_t *obj)
elijahsj 1:8a094db1347f 216 {
elijahsj 1:8a094db1347f 217 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 218 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 219 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 220
elijahsj 1:8a094db1347f 221 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
elijahsj 1:8a094db1347f 222
elijahsj 1:8a094db1347f 223 var->ref_cnt --;
elijahsj 1:8a094db1347f 224 if (! var->ref_cnt) {
elijahsj 1:8a094db1347f 225 #if DEVICE_SERIAL_ASYNCH
elijahsj 1:8a094db1347f 226 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
elijahsj 1:8a094db1347f 227 dma_channel_free(obj->serial.dma_chn_id_tx);
elijahsj 1:8a094db1347f 228 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
elijahsj 1:8a094db1347f 229 }
elijahsj 1:8a094db1347f 230 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
elijahsj 1:8a094db1347f 231 dma_channel_free(obj->serial.dma_chn_id_rx);
elijahsj 1:8a094db1347f 232 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
elijahsj 1:8a094db1347f 233 }
elijahsj 1:8a094db1347f 234 #endif
elijahsj 1:8a094db1347f 235
elijahsj 1:8a094db1347f 236 UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
elijahsj 1:8a094db1347f 237
elijahsj 1:8a094db1347f 238 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elijahsj 1:8a094db1347f 239 NVIC_DisableIRQ(modinit->irq_n);
elijahsj 1:8a094db1347f 240
elijahsj 1:8a094db1347f 241 // Disable IP clock
elijahsj 1:8a094db1347f 242 CLK_DisableModuleClock(modinit->clkidx);
elijahsj 1:8a094db1347f 243 }
elijahsj 1:8a094db1347f 244
elijahsj 1:8a094db1347f 245 if (var->obj == obj) {
elijahsj 1:8a094db1347f 246 var->obj = NULL;
elijahsj 1:8a094db1347f 247 }
elijahsj 1:8a094db1347f 248
elijahsj 1:8a094db1347f 249 if (obj->serial.uart == STDIO_UART) {
elijahsj 1:8a094db1347f 250 stdio_uart_inited = 0;
elijahsj 1:8a094db1347f 251 }
elijahsj 1:8a094db1347f 252
elijahsj 1:8a094db1347f 253 if (! var->ref_cnt) {
elijahsj 1:8a094db1347f 254 // Mark this module to be deinited.
elijahsj 1:8a094db1347f 255 int i = modinit - uart_modinit_tab;
elijahsj 1:8a094db1347f 256 uart_modinit_mask &= ~(1 << i);
elijahsj 1:8a094db1347f 257 }
elijahsj 1:8a094db1347f 258 }
elijahsj 1:8a094db1347f 259
elijahsj 1:8a094db1347f 260 void serial_baud(serial_t *obj, int baudrate) {
elijahsj 1:8a094db1347f 261 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
elijahsj 1:8a094db1347f 262 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
elijahsj 1:8a094db1347f 263
elijahsj 1:8a094db1347f 264 obj->serial.baudrate = baudrate;
elijahsj 1:8a094db1347f 265 UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
elijahsj 1:8a094db1347f 266 }
elijahsj 1:8a094db1347f 267
elijahsj 1:8a094db1347f 268 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
elijahsj 1:8a094db1347f 269 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
elijahsj 1:8a094db1347f 270 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
elijahsj 1:8a094db1347f 271
elijahsj 1:8a094db1347f 272 // Sanity check arguments
elijahsj 1:8a094db1347f 273 MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8));
elijahsj 1:8a094db1347f 274 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || (parity == ParityForced1) || (parity == ParityForced0));
elijahsj 1:8a094db1347f 275 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
elijahsj 1:8a094db1347f 276
elijahsj 1:8a094db1347f 277 obj->serial.databits = data_bits;
elijahsj 1:8a094db1347f 278 obj->serial.parity = parity;
elijahsj 1:8a094db1347f 279 obj->serial.stopbits = stop_bits;
elijahsj 1:8a094db1347f 280
elijahsj 1:8a094db1347f 281 uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
elijahsj 1:8a094db1347f 282 (data_bits == 6) ? UART_WORD_LEN_6 :
elijahsj 1:8a094db1347f 283 (data_bits == 7) ? UART_WORD_LEN_7 :
elijahsj 1:8a094db1347f 284 UART_WORD_LEN_8;
elijahsj 1:8a094db1347f 285 uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
elijahsj 1:8a094db1347f 286 (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
elijahsj 1:8a094db1347f 287 UART_PARITY_NONE;
elijahsj 1:8a094db1347f 288 uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
elijahsj 1:8a094db1347f 289 UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
elijahsj 1:8a094db1347f 290 0, // Don't change baudrate
elijahsj 1:8a094db1347f 291 databits_intern,
elijahsj 1:8a094db1347f 292 parity_intern,
elijahsj 1:8a094db1347f 293 stopbits_intern);
elijahsj 1:8a094db1347f 294 }
elijahsj 1:8a094db1347f 295
elijahsj 1:8a094db1347f 296 #if DEVICE_SERIAL_FC
elijahsj 1:8a094db1347f 297
elijahsj 1:8a094db1347f 298 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
elijahsj 1:8a094db1347f 299 {
elijahsj 1:8a094db1347f 300 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elijahsj 1:8a094db1347f 301
elijahsj 1:8a094db1347f 302 // First, disable flow control completely.
elijahsj 1:8a094db1347f 303 uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
elijahsj 1:8a094db1347f 304
elijahsj 1:8a094db1347f 305 if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
elijahsj 1:8a094db1347f 306 // Check if RTS pin matches.
elijahsj 1:8a094db1347f 307 uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
elijahsj 1:8a094db1347f 308 MBED_ASSERT(uart_rts == obj->serial.uart);
elijahsj 1:8a094db1347f 309 // Enable the pin for RTS function
elijahsj 1:8a094db1347f 310 pinmap_pinout(rxflow, PinMap_UART_RTS);
elijahsj 1:8a094db1347f 311 // nRTS pin output is low level active
elijahsj 1:8a094db1347f 312 uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
elijahsj 1:8a094db1347f 313 uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
elijahsj 1:8a094db1347f 314 // Enable RTS
elijahsj 1:8a094db1347f 315 uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
elijahsj 1:8a094db1347f 316 }
elijahsj 1:8a094db1347f 317
elijahsj 1:8a094db1347f 318 if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC) {
elijahsj 1:8a094db1347f 319 // Check if CTS pin matches.
elijahsj 1:8a094db1347f 320 uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
elijahsj 1:8a094db1347f 321 MBED_ASSERT(uart_cts == obj->serial.uart);
elijahsj 1:8a094db1347f 322 // Enable the pin for CTS function
elijahsj 1:8a094db1347f 323 pinmap_pinout(txflow, PinMap_UART_CTS);
elijahsj 1:8a094db1347f 324 // nCTS pin input is low level active
elijahsj 1:8a094db1347f 325 uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
elijahsj 1:8a094db1347f 326 // Enable CTS
elijahsj 1:8a094db1347f 327 uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
elijahsj 1:8a094db1347f 328 }
elijahsj 1:8a094db1347f 329 }
elijahsj 1:8a094db1347f 330
elijahsj 1:8a094db1347f 331 #endif //DEVICE_SERIAL_FC
elijahsj 1:8a094db1347f 332
elijahsj 1:8a094db1347f 333 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
elijahsj 1:8a094db1347f 334 {
elijahsj 1:8a094db1347f 335 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
elijahsj 1:8a094db1347f 336 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
elijahsj 1:8a094db1347f 337
elijahsj 1:8a094db1347f 338 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 339 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 340 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 341
elijahsj 1:8a094db1347f 342 obj->serial.irq_handler = (uint32_t) handler;
elijahsj 1:8a094db1347f 343 obj->serial.irq_id = id;
elijahsj 1:8a094db1347f 344
elijahsj 1:8a094db1347f 345 // Restore sync-mode vector
elijahsj 1:8a094db1347f 346 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
elijahsj 1:8a094db1347f 347 }
elijahsj 1:8a094db1347f 348
elijahsj 1:8a094db1347f 349 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
elijahsj 1:8a094db1347f 350 {
elijahsj 1:8a094db1347f 351 obj->serial.irq_en = enable;
elijahsj 1:8a094db1347f 352 serial_enable_interrupt(obj, irq, enable);
elijahsj 1:8a094db1347f 353 }
elijahsj 1:8a094db1347f 354
elijahsj 1:8a094db1347f 355 int serial_getc(serial_t *obj)
elijahsj 1:8a094db1347f 356 {
elijahsj 1:8a094db1347f 357 // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
elijahsj 1:8a094db1347f 358 while (! serial_readable(obj));
elijahsj 1:8a094db1347f 359 int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elijahsj 1:8a094db1347f 360
elijahsj 1:8a094db1347f 361 // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
elijahsj 1:8a094db1347f 362 // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
elijahsj 1:8a094db1347f 363 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
elijahsj 1:8a094db1347f 364 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elijahsj 1:8a094db1347f 365 }
elijahsj 1:8a094db1347f 366
elijahsj 1:8a094db1347f 367 return c;
elijahsj 1:8a094db1347f 368 }
elijahsj 1:8a094db1347f 369
elijahsj 1:8a094db1347f 370 void serial_putc(serial_t *obj, int c)
elijahsj 1:8a094db1347f 371 {
elijahsj 1:8a094db1347f 372 // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
elijahsj 1:8a094db1347f 373 while (! serial_writable(obj));
elijahsj 1:8a094db1347f 374 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
elijahsj 1:8a094db1347f 375
elijahsj 1:8a094db1347f 376 // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
elijahsj 1:8a094db1347f 377 // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
elijahsj 1:8a094db1347f 378 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
elijahsj 1:8a094db1347f 379 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elijahsj 1:8a094db1347f 380 }
elijahsj 1:8a094db1347f 381 }
elijahsj 1:8a094db1347f 382
elijahsj 1:8a094db1347f 383 int serial_readable(serial_t *obj)
elijahsj 1:8a094db1347f 384 {
elijahsj 1:8a094db1347f 385 //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
elijahsj 1:8a094db1347f 386 return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
elijahsj 1:8a094db1347f 387 }
elijahsj 1:8a094db1347f 388
elijahsj 1:8a094db1347f 389 int serial_writable(serial_t *obj)
elijahsj 1:8a094db1347f 390 {
elijahsj 1:8a094db1347f 391 return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
elijahsj 1:8a094db1347f 392 }
elijahsj 1:8a094db1347f 393
elijahsj 1:8a094db1347f 394 void serial_pinout_tx(PinName tx)
elijahsj 1:8a094db1347f 395 {
elijahsj 1:8a094db1347f 396 pinmap_pinout(tx, PinMap_UART_TX);
elijahsj 1:8a094db1347f 397 }
elijahsj 1:8a094db1347f 398
elijahsj 1:8a094db1347f 399 void serial_break_set(serial_t *obj)
elijahsj 1:8a094db1347f 400 {
elijahsj 1:8a094db1347f 401 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
elijahsj 1:8a094db1347f 402 }
elijahsj 1:8a094db1347f 403
elijahsj 1:8a094db1347f 404 void serial_break_clear(serial_t *obj)
elijahsj 1:8a094db1347f 405 {
elijahsj 1:8a094db1347f 406 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
elijahsj 1:8a094db1347f 407 }
elijahsj 1:8a094db1347f 408
elijahsj 1:8a094db1347f 409 static void uart0_vec(void)
elijahsj 1:8a094db1347f 410 {
elijahsj 1:8a094db1347f 411 uart_irq(uart0_var.obj);
elijahsj 1:8a094db1347f 412 }
elijahsj 1:8a094db1347f 413
elijahsj 1:8a094db1347f 414 static void uart1_vec(void)
elijahsj 1:8a094db1347f 415 {
elijahsj 1:8a094db1347f 416 uart_irq(uart1_var.obj);
elijahsj 1:8a094db1347f 417 }
elijahsj 1:8a094db1347f 418
elijahsj 1:8a094db1347f 419 static void uart2_vec(void)
elijahsj 1:8a094db1347f 420 {
elijahsj 1:8a094db1347f 421 uart_irq(uart2_var.obj);
elijahsj 1:8a094db1347f 422 }
elijahsj 1:8a094db1347f 423
elijahsj 1:8a094db1347f 424 static void uart3_vec(void)
elijahsj 1:8a094db1347f 425 {
elijahsj 1:8a094db1347f 426 uart_irq(uart3_var.obj);
elijahsj 1:8a094db1347f 427 }
elijahsj 1:8a094db1347f 428
elijahsj 1:8a094db1347f 429 static void uart_irq(serial_t *obj)
elijahsj 1:8a094db1347f 430 {
elijahsj 1:8a094db1347f 431 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elijahsj 1:8a094db1347f 432
elijahsj 1:8a094db1347f 433 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
elijahsj 1:8a094db1347f 434 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
elijahsj 1:8a094db1347f 435 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elijahsj 1:8a094db1347f 436 if (obj->serial.irq_handler) {
elijahsj 1:8a094db1347f 437 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
elijahsj 1:8a094db1347f 438 }
elijahsj 1:8a094db1347f 439 }
elijahsj 1:8a094db1347f 440
elijahsj 1:8a094db1347f 441 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
elijahsj 1:8a094db1347f 442 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
elijahsj 1:8a094db1347f 443 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
elijahsj 1:8a094db1347f 444 if (obj->serial.irq_handler) {
elijahsj 1:8a094db1347f 445 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
elijahsj 1:8a094db1347f 446 }
elijahsj 1:8a094db1347f 447 }
elijahsj 1:8a094db1347f 448
elijahsj 1:8a094db1347f 449 // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
elijahsj 1:8a094db1347f 450 uart_base->INTSTS = uart_base->INTSTS;
elijahsj 1:8a094db1347f 451 uart_base->FIFOSTS = uart_base->FIFOSTS;
elijahsj 1:8a094db1347f 452 }
elijahsj 1:8a094db1347f 453
elijahsj 1:8a094db1347f 454
elijahsj 1:8a094db1347f 455 #if DEVICE_SERIAL_ASYNCH
elijahsj 1:8a094db1347f 456 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
elijahsj 1:8a094db1347f 457 {
elijahsj 1:8a094db1347f 458 MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
elijahsj 1:8a094db1347f 459
elijahsj 1:8a094db1347f 460 obj->serial.dma_usage_tx = hint;
elijahsj 1:8a094db1347f 461 serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
elijahsj 1:8a094db1347f 462
elijahsj 1:8a094db1347f 463 // UART IRQ is necessary for both interrupt way and DMA way
elijahsj 1:8a094db1347f 464 serial_tx_enable_event(obj, event, 1);
elijahsj 1:8a094db1347f 465 serial_tx_buffer_set(obj, tx, tx_length, tx_width);
elijahsj 1:8a094db1347f 466 //UART_HAL_DisableTransmitter(obj->serial.address);
elijahsj 1:8a094db1347f 467 //UART_HAL_FlushTxFifo(obj->serial.address);
elijahsj 1:8a094db1347f 468 //UART_HAL_EnableTransmitter(obj->serial.address);
elijahsj 1:8a094db1347f 469
elijahsj 1:8a094db1347f 470 int n_word = 0;
elijahsj 1:8a094db1347f 471 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
elijahsj 1:8a094db1347f 472 // Interrupt way
elijahsj 1:8a094db1347f 473 n_word = serial_write_async(obj);
elijahsj 1:8a094db1347f 474 serial_tx_enable_interrupt(obj, handler, 1);
elijahsj 1:8a094db1347f 475 } else {
elijahsj 1:8a094db1347f 476 // DMA way
elijahsj 1:8a094db1347f 477 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 478 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 479 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 480
elijahsj 1:8a094db1347f 481 PDMA_T *pdma_base = dma_modbase();
elijahsj 1:8a094db1347f 482
elijahsj 1:8a094db1347f 483 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
elijahsj 1:8a094db1347f 484 PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
elijahsj 1:8a094db1347f 485 ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
elijahsj 1:8a094db1347f 486 0, // Scatter-gather disabled
elijahsj 1:8a094db1347f 487 0); // Scatter-gather descriptor address
elijahsj 1:8a094db1347f 488 PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
elijahsj 1:8a094db1347f 489 (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
elijahsj 1:8a094db1347f 490 tx_length);
elijahsj 1:8a094db1347f 491 PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
elijahsj 1:8a094db1347f 492 (uint32_t) tx, // NOTE:
elijahsj 1:8a094db1347f 493 // NUC472: End of source address
elijahsj 1:8a094db1347f 494 // M451: Start of source address
elijahsj 1:8a094db1347f 495 PDMA_SAR_INC, // Source address incremental
elijahsj 1:8a094db1347f 496 (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address
elijahsj 1:8a094db1347f 497 PDMA_DAR_FIX); // Destination address fixed
elijahsj 1:8a094db1347f 498 PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
elijahsj 1:8a094db1347f 499 PDMA_REQ_SINGLE, // Single mode
elijahsj 1:8a094db1347f 500 0); // Burst size
elijahsj 1:8a094db1347f 501 PDMA_EnableInt(obj->serial.dma_chn_id_tx,
elijahsj 1:8a094db1347f 502 PDMA_INT_TRANS_DONE); // Interrupt type
elijahsj 1:8a094db1347f 503 // Register DMA event handler
elijahsj 1:8a094db1347f 504 dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
elijahsj 1:8a094db1347f 505 serial_tx_enable_interrupt(obj, handler, 1);
elijahsj 1:8a094db1347f 506 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
elijahsj 1:8a094db1347f 507 }
elijahsj 1:8a094db1347f 508
elijahsj 1:8a094db1347f 509 return n_word;
elijahsj 1:8a094db1347f 510 }
elijahsj 1:8a094db1347f 511
elijahsj 1:8a094db1347f 512 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
elijahsj 1:8a094db1347f 513 {
elijahsj 1:8a094db1347f 514 MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
elijahsj 1:8a094db1347f 515
elijahsj 1:8a094db1347f 516 obj->serial.dma_usage_rx = hint;
elijahsj 1:8a094db1347f 517 serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
elijahsj 1:8a094db1347f 518 // DMA doesn't support char match, so fall back to IRQ if it is requested.
elijahsj 1:8a094db1347f 519 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
elijahsj 1:8a094db1347f 520 (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
elijahsj 1:8a094db1347f 521 char_match != SERIAL_RESERVED_CHAR_MATCH) {
elijahsj 1:8a094db1347f 522 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
elijahsj 1:8a094db1347f 523 dma_channel_free(obj->serial.dma_chn_id_rx);
elijahsj 1:8a094db1347f 524 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
elijahsj 1:8a094db1347f 525 }
elijahsj 1:8a094db1347f 526
elijahsj 1:8a094db1347f 527 // UART IRQ is necessary for both interrupt way and DMA way
elijahsj 1:8a094db1347f 528 serial_rx_enable_event(obj, event, 1);
elijahsj 1:8a094db1347f 529 serial_rx_buffer_set(obj, rx, rx_length, rx_width);
elijahsj 1:8a094db1347f 530 serial_rx_set_char_match(obj, char_match);
elijahsj 1:8a094db1347f 531 //UART_HAL_DisableReceiver(obj->serial.address);
elijahsj 1:8a094db1347f 532 //UART_HAL_FlushRxFifo(obj->serial.address);
elijahsj 1:8a094db1347f 533 //UART_HAL_EnableReceiver(obj->serial.address);
elijahsj 1:8a094db1347f 534
elijahsj 1:8a094db1347f 535 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
elijahsj 1:8a094db1347f 536 // Interrupt way
elijahsj 1:8a094db1347f 537 serial_rx_enable_interrupt(obj, handler, 1);
elijahsj 1:8a094db1347f 538 } else {
elijahsj 1:8a094db1347f 539 // DMA way
elijahsj 1:8a094db1347f 540 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 541 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 542 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 543
elijahsj 1:8a094db1347f 544 PDMA_T *pdma_base = dma_modbase();
elijahsj 1:8a094db1347f 545
elijahsj 1:8a094db1347f 546 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
elijahsj 1:8a094db1347f 547 PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
elijahsj 1:8a094db1347f 548 ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
elijahsj 1:8a094db1347f 549 0, // Scatter-gather disabled
elijahsj 1:8a094db1347f 550 0); // Scatter-gather descriptor address
elijahsj 1:8a094db1347f 551 PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
elijahsj 1:8a094db1347f 552 (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
elijahsj 1:8a094db1347f 553 rx_length);
elijahsj 1:8a094db1347f 554 PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
elijahsj 1:8a094db1347f 555 (uint32_t) NU_MODBASE(obj->serial.uart), // Source address
elijahsj 1:8a094db1347f 556 PDMA_SAR_FIX, // Source address fixed
elijahsj 1:8a094db1347f 557 (uint32_t) rx, // NOTE:
elijahsj 1:8a094db1347f 558 // NUC472: End of destination address
elijahsj 1:8a094db1347f 559 // M451: Start of destination address
elijahsj 1:8a094db1347f 560 PDMA_DAR_INC); // Destination address incremental
elijahsj 1:8a094db1347f 561 PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
elijahsj 1:8a094db1347f 562 PDMA_REQ_SINGLE, // Single mode
elijahsj 1:8a094db1347f 563 0); // Burst size
elijahsj 1:8a094db1347f 564 PDMA_EnableInt(obj->serial.dma_chn_id_rx,
elijahsj 1:8a094db1347f 565 PDMA_INT_TRANS_DONE); // Interrupt type
elijahsj 1:8a094db1347f 566 // Register DMA event handler
elijahsj 1:8a094db1347f 567 dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
elijahsj 1:8a094db1347f 568 serial_rx_enable_interrupt(obj, handler, 1);
elijahsj 1:8a094db1347f 569 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
elijahsj 1:8a094db1347f 570 }
elijahsj 1:8a094db1347f 571 }
elijahsj 1:8a094db1347f 572
elijahsj 1:8a094db1347f 573 void serial_tx_abort_asynch(serial_t *obj)
elijahsj 1:8a094db1347f 574 {
elijahsj 1:8a094db1347f 575 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
elijahsj 1:8a094db1347f 576 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
elijahsj 1:8a094db1347f 577
elijahsj 1:8a094db1347f 578 if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
elijahsj 1:8a094db1347f 579 PDMA_T *pdma_base = dma_modbase();
elijahsj 1:8a094db1347f 580
elijahsj 1:8a094db1347f 581 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
elijahsj 1:8a094db1347f 582 PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
elijahsj 1:8a094db1347f 583 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
elijahsj 1:8a094db1347f 584 //PDMA_STOP(obj->serial.dma_chn_id_tx);
elijahsj 1:8a094db1347f 585 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
elijahsj 1:8a094db1347f 586 }
elijahsj 1:8a094db1347f 587 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
elijahsj 1:8a094db1347f 588 }
elijahsj 1:8a094db1347f 589
elijahsj 1:8a094db1347f 590 // Necessary for both interrupt way and DMA way
elijahsj 1:8a094db1347f 591 serial_enable_interrupt(obj, TxIrq, 0);
elijahsj 1:8a094db1347f 592 serial_rollback_interrupt(obj, TxIrq);
elijahsj 1:8a094db1347f 593 }
elijahsj 1:8a094db1347f 594
elijahsj 1:8a094db1347f 595 void serial_rx_abort_asynch(serial_t *obj)
elijahsj 1:8a094db1347f 596 {
elijahsj 1:8a094db1347f 597 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
elijahsj 1:8a094db1347f 598 PDMA_T *pdma_base = dma_modbase();
elijahsj 1:8a094db1347f 599
elijahsj 1:8a094db1347f 600 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
elijahsj 1:8a094db1347f 601 PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
elijahsj 1:8a094db1347f 602 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
elijahsj 1:8a094db1347f 603 //PDMA_STOP(obj->serial.dma_chn_id_rx);
elijahsj 1:8a094db1347f 604 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
elijahsj 1:8a094db1347f 605 }
elijahsj 1:8a094db1347f 606 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
elijahsj 1:8a094db1347f 607 }
elijahsj 1:8a094db1347f 608
elijahsj 1:8a094db1347f 609 // Necessary for both interrupt way and DMA way
elijahsj 1:8a094db1347f 610 serial_enable_interrupt(obj, RxIrq, 0);
elijahsj 1:8a094db1347f 611 serial_rollback_interrupt(obj, RxIrq);
elijahsj 1:8a094db1347f 612 }
elijahsj 1:8a094db1347f 613
elijahsj 1:8a094db1347f 614 uint8_t serial_tx_active(serial_t *obj)
elijahsj 1:8a094db1347f 615 {
elijahsj 1:8a094db1347f 616 // NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag.
elijahsj 1:8a094db1347f 617 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 618 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 619 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 620
elijahsj 1:8a094db1347f 621 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
elijahsj 1:8a094db1347f 622 return (obj->serial.vec == var->vec_async);
elijahsj 1:8a094db1347f 623 }
elijahsj 1:8a094db1347f 624
elijahsj 1:8a094db1347f 625 uint8_t serial_rx_active(serial_t *obj)
elijahsj 1:8a094db1347f 626 {
elijahsj 1:8a094db1347f 627 // NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag.
elijahsj 1:8a094db1347f 628 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 629 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 630 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 631
elijahsj 1:8a094db1347f 632 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
elijahsj 1:8a094db1347f 633 return (obj->serial.vec == var->vec_async);
elijahsj 1:8a094db1347f 634 }
elijahsj 1:8a094db1347f 635
elijahsj 1:8a094db1347f 636 int serial_irq_handler_asynch(serial_t *obj)
elijahsj 1:8a094db1347f 637 {
elijahsj 1:8a094db1347f 638 int event_rx = 0;
elijahsj 1:8a094db1347f 639 int event_tx = 0;
elijahsj 1:8a094db1347f 640
elijahsj 1:8a094db1347f 641 // Necessary for both interrupt way and DMA way
elijahsj 1:8a094db1347f 642 if (serial_is_irq_en(obj, RxIrq)) {
elijahsj 1:8a094db1347f 643 event_rx = serial_rx_event_check(obj);
elijahsj 1:8a094db1347f 644 if (event_rx) {
elijahsj 1:8a094db1347f 645 serial_rx_abort_asynch(obj);
elijahsj 1:8a094db1347f 646 }
elijahsj 1:8a094db1347f 647 }
elijahsj 1:8a094db1347f 648
elijahsj 1:8a094db1347f 649 if (serial_is_irq_en(obj, TxIrq)) {
elijahsj 1:8a094db1347f 650 event_tx = serial_tx_event_check(obj);
elijahsj 1:8a094db1347f 651 if (event_tx) {
elijahsj 1:8a094db1347f 652 serial_tx_abort_asynch(obj);
elijahsj 1:8a094db1347f 653 }
elijahsj 1:8a094db1347f 654 }
elijahsj 1:8a094db1347f 655
elijahsj 1:8a094db1347f 656 return (obj->serial.event & (event_rx | event_tx));
elijahsj 1:8a094db1347f 657 }
elijahsj 1:8a094db1347f 658
elijahsj 1:8a094db1347f 659 int serial_allow_powerdown(void)
elijahsj 1:8a094db1347f 660 {
elijahsj 1:8a094db1347f 661 uint32_t modinit_mask = uart_modinit_mask;
elijahsj 1:8a094db1347f 662 while (modinit_mask) {
elijahsj 1:8a094db1347f 663 int uart_idx = nu_ctz(modinit_mask);
elijahsj 1:8a094db1347f 664 const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
elijahsj 1:8a094db1347f 665 if (modinit->modname != NC) {
elijahsj 1:8a094db1347f 666 UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
elijahsj 1:8a094db1347f 667 // Disallow entering power-down mode if Tx FIFO has data to flush
elijahsj 1:8a094db1347f 668 if (! UART_IS_TX_EMPTY((uart_base))) {
elijahsj 1:8a094db1347f 669 return 0;
elijahsj 1:8a094db1347f 670 }
elijahsj 1:8a094db1347f 671 // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
elijahsj 1:8a094db1347f 672 if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
elijahsj 1:8a094db1347f 673 return 0;
elijahsj 1:8a094db1347f 674 }
elijahsj 1:8a094db1347f 675 // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
elijahsj 1:8a094db1347f 676 if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
elijahsj 1:8a094db1347f 677 return 0;
elijahsj 1:8a094db1347f 678 }
elijahsj 1:8a094db1347f 679 }
elijahsj 1:8a094db1347f 680 modinit_mask &= ~(1 << uart_idx);
elijahsj 1:8a094db1347f 681 }
elijahsj 1:8a094db1347f 682
elijahsj 1:8a094db1347f 683 return 1;
elijahsj 1:8a094db1347f 684 }
elijahsj 1:8a094db1347f 685
elijahsj 1:8a094db1347f 686 static void uart0_vec_async(void)
elijahsj 1:8a094db1347f 687 {
elijahsj 1:8a094db1347f 688 uart_irq_async(uart0_var.obj);
elijahsj 1:8a094db1347f 689 }
elijahsj 1:8a094db1347f 690
elijahsj 1:8a094db1347f 691 static void uart1_vec_async(void)
elijahsj 1:8a094db1347f 692 {
elijahsj 1:8a094db1347f 693 uart_irq_async(uart1_var.obj);
elijahsj 1:8a094db1347f 694 }
elijahsj 1:8a094db1347f 695
elijahsj 1:8a094db1347f 696 static void uart2_vec_async(void)
elijahsj 1:8a094db1347f 697 {
elijahsj 1:8a094db1347f 698 uart_irq_async(uart2_var.obj);
elijahsj 1:8a094db1347f 699 }
elijahsj 1:8a094db1347f 700
elijahsj 1:8a094db1347f 701 static void uart3_vec_async(void)
elijahsj 1:8a094db1347f 702 {
elijahsj 1:8a094db1347f 703 uart_irq_async(uart3_var.obj);
elijahsj 1:8a094db1347f 704 }
elijahsj 1:8a094db1347f 705
elijahsj 1:8a094db1347f 706 static void uart_irq_async(serial_t *obj)
elijahsj 1:8a094db1347f 707 {
elijahsj 1:8a094db1347f 708 if (serial_is_irq_en(obj, RxIrq)) {
elijahsj 1:8a094db1347f 709 (*obj->serial.irq_handler_rx_async)();
elijahsj 1:8a094db1347f 710 }
elijahsj 1:8a094db1347f 711 if (serial_is_irq_en(obj, TxIrq)) {
elijahsj 1:8a094db1347f 712 (*obj->serial.irq_handler_tx_async)();
elijahsj 1:8a094db1347f 713 }
elijahsj 1:8a094db1347f 714 }
elijahsj 1:8a094db1347f 715
elijahsj 1:8a094db1347f 716 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
elijahsj 1:8a094db1347f 717 {
elijahsj 1:8a094db1347f 718 obj->char_match = char_match;
elijahsj 1:8a094db1347f 719 obj->char_found = 0;
elijahsj 1:8a094db1347f 720 }
elijahsj 1:8a094db1347f 721
elijahsj 1:8a094db1347f 722 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
elijahsj 1:8a094db1347f 723 {
elijahsj 1:8a094db1347f 724 obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
elijahsj 1:8a094db1347f 725 obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
elijahsj 1:8a094db1347f 726
elijahsj 1:8a094db1347f 727 //if (event & SERIAL_EVENT_TX_COMPLETE) {
elijahsj 1:8a094db1347f 728 //}
elijahsj 1:8a094db1347f 729 }
elijahsj 1:8a094db1347f 730
elijahsj 1:8a094db1347f 731 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
elijahsj 1:8a094db1347f 732 {
elijahsj 1:8a094db1347f 733 obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
elijahsj 1:8a094db1347f 734 obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
elijahsj 1:8a094db1347f 735
elijahsj 1:8a094db1347f 736 //if (event & SERIAL_EVENT_RX_COMPLETE) {
elijahsj 1:8a094db1347f 737 //}
elijahsj 1:8a094db1347f 738 //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
elijahsj 1:8a094db1347f 739 //}
elijahsj 1:8a094db1347f 740 if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
elijahsj 1:8a094db1347f 741 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
elijahsj 1:8a094db1347f 742 }
elijahsj 1:8a094db1347f 743 if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
elijahsj 1:8a094db1347f 744 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
elijahsj 1:8a094db1347f 745 }
elijahsj 1:8a094db1347f 746 if (event & SERIAL_EVENT_RX_OVERFLOW) {
elijahsj 1:8a094db1347f 747 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
elijahsj 1:8a094db1347f 748 }
elijahsj 1:8a094db1347f 749 //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
elijahsj 1:8a094db1347f 750 //}
elijahsj 1:8a094db1347f 751 }
elijahsj 1:8a094db1347f 752
elijahsj 1:8a094db1347f 753 static int serial_is_tx_complete(serial_t *obj)
elijahsj 1:8a094db1347f 754 {
elijahsj 1:8a094db1347f 755 // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
elijahsj 1:8a094db1347f 756 //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
elijahsj 1:8a094db1347f 757 // FIXME: Premature abort???
elijahsj 1:8a094db1347f 758 return (obj->tx_buff.pos == obj->tx_buff.length);
elijahsj 1:8a094db1347f 759 }
elijahsj 1:8a094db1347f 760
elijahsj 1:8a094db1347f 761 static int serial_is_rx_complete(serial_t *obj)
elijahsj 1:8a094db1347f 762 {
elijahsj 1:8a094db1347f 763 //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
elijahsj 1:8a094db1347f 764 return (obj->rx_buff.pos == obj->rx_buff.length);
elijahsj 1:8a094db1347f 765 }
elijahsj 1:8a094db1347f 766
elijahsj 1:8a094db1347f 767 static uint32_t serial_tx_event_check(serial_t *obj)
elijahsj 1:8a094db1347f 768 {
elijahsj 1:8a094db1347f 769 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elijahsj 1:8a094db1347f 770
elijahsj 1:8a094db1347f 771 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
elijahsj 1:8a094db1347f 772 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
elijahsj 1:8a094db1347f 773 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
elijahsj 1:8a094db1347f 774 }
elijahsj 1:8a094db1347f 775
elijahsj 1:8a094db1347f 776 uint32_t event = 0;
elijahsj 1:8a094db1347f 777
elijahsj 1:8a094db1347f 778 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
elijahsj 1:8a094db1347f 779 serial_write_async(obj);
elijahsj 1:8a094db1347f 780 }
elijahsj 1:8a094db1347f 781
elijahsj 1:8a094db1347f 782 if (serial_is_tx_complete(obj)) {
elijahsj 1:8a094db1347f 783 event |= SERIAL_EVENT_TX_COMPLETE;
elijahsj 1:8a094db1347f 784 }
elijahsj 1:8a094db1347f 785
elijahsj 1:8a094db1347f 786 return event;
elijahsj 1:8a094db1347f 787 }
elijahsj 1:8a094db1347f 788
elijahsj 1:8a094db1347f 789 static uint32_t serial_rx_event_check(serial_t *obj)
elijahsj 1:8a094db1347f 790 {
elijahsj 1:8a094db1347f 791 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elijahsj 1:8a094db1347f 792
elijahsj 1:8a094db1347f 793 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
elijahsj 1:8a094db1347f 794 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
elijahsj 1:8a094db1347f 795 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elijahsj 1:8a094db1347f 796 }
elijahsj 1:8a094db1347f 797
elijahsj 1:8a094db1347f 798 uint32_t event = 0;
elijahsj 1:8a094db1347f 799
elijahsj 1:8a094db1347f 800 if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
elijahsj 1:8a094db1347f 801 uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
elijahsj 1:8a094db1347f 802 }
elijahsj 1:8a094db1347f 803 if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
elijahsj 1:8a094db1347f 804 uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
elijahsj 1:8a094db1347f 805 event |= SERIAL_EVENT_RX_FRAMING_ERROR;
elijahsj 1:8a094db1347f 806 }
elijahsj 1:8a094db1347f 807 if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
elijahsj 1:8a094db1347f 808 uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
elijahsj 1:8a094db1347f 809 event |= SERIAL_EVENT_RX_PARITY_ERROR;
elijahsj 1:8a094db1347f 810 }
elijahsj 1:8a094db1347f 811
elijahsj 1:8a094db1347f 812 if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
elijahsj 1:8a094db1347f 813 uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
elijahsj 1:8a094db1347f 814 event |= SERIAL_EVENT_RX_OVERFLOW;
elijahsj 1:8a094db1347f 815 }
elijahsj 1:8a094db1347f 816
elijahsj 1:8a094db1347f 817 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
elijahsj 1:8a094db1347f 818 serial_read_async(obj);
elijahsj 1:8a094db1347f 819 }
elijahsj 1:8a094db1347f 820
elijahsj 1:8a094db1347f 821 if (serial_is_rx_complete(obj)) {
elijahsj 1:8a094db1347f 822 event |= SERIAL_EVENT_RX_COMPLETE;
elijahsj 1:8a094db1347f 823 }
elijahsj 1:8a094db1347f 824 if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
elijahsj 1:8a094db1347f 825 event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
elijahsj 1:8a094db1347f 826 // FIXME: Timing to reset char_found?
elijahsj 1:8a094db1347f 827 //obj->char_found = 0;
elijahsj 1:8a094db1347f 828 }
elijahsj 1:8a094db1347f 829
elijahsj 1:8a094db1347f 830 return event;
elijahsj 1:8a094db1347f 831 }
elijahsj 1:8a094db1347f 832
elijahsj 1:8a094db1347f 833 static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
elijahsj 1:8a094db1347f 834 {
elijahsj 1:8a094db1347f 835 serial_t *obj = (serial_t *) id;
elijahsj 1:8a094db1347f 836
elijahsj 1:8a094db1347f 837 // FIXME: Pass this error to caller
elijahsj 1:8a094db1347f 838 if (event_dma & DMA_EVENT_ABORT) {
elijahsj 1:8a094db1347f 839 }
elijahsj 1:8a094db1347f 840 // Expect UART IRQ will catch this transfer done event
elijahsj 1:8a094db1347f 841 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
elijahsj 1:8a094db1347f 842 obj->tx_buff.pos = obj->tx_buff.length;
elijahsj 1:8a094db1347f 843 }
elijahsj 1:8a094db1347f 844 // FIXME: Pass this error to caller
elijahsj 1:8a094db1347f 845 if (event_dma & DMA_EVENT_TIMEOUT) {
elijahsj 1:8a094db1347f 846 }
elijahsj 1:8a094db1347f 847
elijahsj 1:8a094db1347f 848 uart_irq_async(obj);
elijahsj 1:8a094db1347f 849 }
elijahsj 1:8a094db1347f 850
elijahsj 1:8a094db1347f 851 static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
elijahsj 1:8a094db1347f 852 {
elijahsj 1:8a094db1347f 853 serial_t *obj = (serial_t *) id;
elijahsj 1:8a094db1347f 854
elijahsj 1:8a094db1347f 855 // FIXME: Pass this error to caller
elijahsj 1:8a094db1347f 856 if (event_dma & DMA_EVENT_ABORT) {
elijahsj 1:8a094db1347f 857 }
elijahsj 1:8a094db1347f 858 // Expect UART IRQ will catch this transfer done event
elijahsj 1:8a094db1347f 859 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
elijahsj 1:8a094db1347f 860 obj->rx_buff.pos = obj->rx_buff.length;
elijahsj 1:8a094db1347f 861 }
elijahsj 1:8a094db1347f 862 // FIXME: Pass this error to caller
elijahsj 1:8a094db1347f 863 if (event_dma & DMA_EVENT_TIMEOUT) {
elijahsj 1:8a094db1347f 864 }
elijahsj 1:8a094db1347f 865
elijahsj 1:8a094db1347f 866 uart_irq_async(obj);
elijahsj 1:8a094db1347f 867 }
elijahsj 1:8a094db1347f 868
elijahsj 1:8a094db1347f 869 static int serial_write_async(serial_t *obj)
elijahsj 1:8a094db1347f 870 {
elijahsj 1:8a094db1347f 871 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 872 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 873 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 874
elijahsj 1:8a094db1347f 875 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elijahsj 1:8a094db1347f 876
elijahsj 1:8a094db1347f 877 uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
elijahsj 1:8a094db1347f 878 uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
elijahsj 1:8a094db1347f 879 if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
elijahsj 1:8a094db1347f 880 tx_fifo_busy = tx_fifo_max;
elijahsj 1:8a094db1347f 881 }
elijahsj 1:8a094db1347f 882 uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
elijahsj 1:8a094db1347f 883 if (tx_fifo_free == 0) {
elijahsj 1:8a094db1347f 884 // Simulate clear of the interrupt flag
elijahsj 1:8a094db1347f 885 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
elijahsj 1:8a094db1347f 886 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elijahsj 1:8a094db1347f 887 }
elijahsj 1:8a094db1347f 888 return 0;
elijahsj 1:8a094db1347f 889 }
elijahsj 1:8a094db1347f 890
elijahsj 1:8a094db1347f 891 uint32_t bytes_per_word = obj->tx_buff.width / 8;
elijahsj 1:8a094db1347f 892
elijahsj 1:8a094db1347f 893 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
elijahsj 1:8a094db1347f 894 int n_words = 0;
elijahsj 1:8a094db1347f 895 while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
elijahsj 1:8a094db1347f 896 switch (bytes_per_word) {
elijahsj 1:8a094db1347f 897 case 4:
elijahsj 1:8a094db1347f 898 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
elijahsj 1:8a094db1347f 899 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
elijahsj 1:8a094db1347f 900 case 2:
elijahsj 1:8a094db1347f 901 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
elijahsj 1:8a094db1347f 902 case 1:
elijahsj 1:8a094db1347f 903 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
elijahsj 1:8a094db1347f 904 }
elijahsj 1:8a094db1347f 905
elijahsj 1:8a094db1347f 906 n_words ++;
elijahsj 1:8a094db1347f 907 tx_fifo_free -= bytes_per_word;
elijahsj 1:8a094db1347f 908 obj->tx_buff.pos ++;
elijahsj 1:8a094db1347f 909 }
elijahsj 1:8a094db1347f 910
elijahsj 1:8a094db1347f 911 if (n_words) {
elijahsj 1:8a094db1347f 912 // Simulate clear of the interrupt flag
elijahsj 1:8a094db1347f 913 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
elijahsj 1:8a094db1347f 914 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elijahsj 1:8a094db1347f 915 }
elijahsj 1:8a094db1347f 916 }
elijahsj 1:8a094db1347f 917
elijahsj 1:8a094db1347f 918 return n_words;
elijahsj 1:8a094db1347f 919 }
elijahsj 1:8a094db1347f 920
elijahsj 1:8a094db1347f 921 static int serial_read_async(serial_t *obj)
elijahsj 1:8a094db1347f 922 {
elijahsj 1:8a094db1347f 923 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 924 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 925 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 926
elijahsj 1:8a094db1347f 927 uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
elijahsj 1:8a094db1347f 928 //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
elijahsj 1:8a094db1347f 929 //if (rx_fifo_free == 0) {
elijahsj 1:8a094db1347f 930 // return 0;
elijahsj 1:8a094db1347f 931 //}
elijahsj 1:8a094db1347f 932
elijahsj 1:8a094db1347f 933 uint32_t bytes_per_word = obj->rx_buff.width / 8;
elijahsj 1:8a094db1347f 934
elijahsj 1:8a094db1347f 935 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
elijahsj 1:8a094db1347f 936 int n_words = 0;
elijahsj 1:8a094db1347f 937 while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
elijahsj 1:8a094db1347f 938 switch (bytes_per_word) {
elijahsj 1:8a094db1347f 939 case 4:
elijahsj 1:8a094db1347f 940 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elijahsj 1:8a094db1347f 941 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elijahsj 1:8a094db1347f 942 case 2:
elijahsj 1:8a094db1347f 943 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elijahsj 1:8a094db1347f 944 case 1:
elijahsj 1:8a094db1347f 945 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elijahsj 1:8a094db1347f 946 }
elijahsj 1:8a094db1347f 947
elijahsj 1:8a094db1347f 948 n_words ++;
elijahsj 1:8a094db1347f 949 rx_fifo_busy -= bytes_per_word;
elijahsj 1:8a094db1347f 950 obj->rx_buff.pos ++;
elijahsj 1:8a094db1347f 951
elijahsj 1:8a094db1347f 952 if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
elijahsj 1:8a094db1347f 953 obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
elijahsj 1:8a094db1347f 954 uint8_t *rx_cmp = rx;
elijahsj 1:8a094db1347f 955 switch (bytes_per_word) {
elijahsj 1:8a094db1347f 956 case 4:
elijahsj 1:8a094db1347f 957 rx_cmp -= 2;
elijahsj 1:8a094db1347f 958 case 2:
elijahsj 1:8a094db1347f 959 rx_cmp --;
elijahsj 1:8a094db1347f 960 case 1:
elijahsj 1:8a094db1347f 961 rx_cmp --;
elijahsj 1:8a094db1347f 962 }
elijahsj 1:8a094db1347f 963 if (*rx_cmp == obj->char_match) {
elijahsj 1:8a094db1347f 964 obj->char_found = 1;
elijahsj 1:8a094db1347f 965 break;
elijahsj 1:8a094db1347f 966 }
elijahsj 1:8a094db1347f 967 }
elijahsj 1:8a094db1347f 968 }
elijahsj 1:8a094db1347f 969
elijahsj 1:8a094db1347f 970 if (n_words) {
elijahsj 1:8a094db1347f 971 // Simulate clear of the interrupt flag
elijahsj 1:8a094db1347f 972 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
elijahsj 1:8a094db1347f 973 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elijahsj 1:8a094db1347f 974 }
elijahsj 1:8a094db1347f 975 }
elijahsj 1:8a094db1347f 976
elijahsj 1:8a094db1347f 977 return n_words;
elijahsj 1:8a094db1347f 978 }
elijahsj 1:8a094db1347f 979
elijahsj 1:8a094db1347f 980 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
elijahsj 1:8a094db1347f 981 {
elijahsj 1:8a094db1347f 982 obj->tx_buff.buffer = (void *) tx;
elijahsj 1:8a094db1347f 983 obj->tx_buff.length = length;
elijahsj 1:8a094db1347f 984 obj->tx_buff.pos = 0;
elijahsj 1:8a094db1347f 985 obj->tx_buff.width = width;
elijahsj 1:8a094db1347f 986 }
elijahsj 1:8a094db1347f 987
elijahsj 1:8a094db1347f 988 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
elijahsj 1:8a094db1347f 989 {
elijahsj 1:8a094db1347f 990 obj->rx_buff.buffer = rx;
elijahsj 1:8a094db1347f 991 obj->rx_buff.length = length;
elijahsj 1:8a094db1347f 992 obj->rx_buff.pos = 0;
elijahsj 1:8a094db1347f 993 obj->rx_buff.width = width;
elijahsj 1:8a094db1347f 994 }
elijahsj 1:8a094db1347f 995
elijahsj 1:8a094db1347f 996 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
elijahsj 1:8a094db1347f 997 {
elijahsj 1:8a094db1347f 998 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 999 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 1000 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 1001
elijahsj 1:8a094db1347f 1002 // Necessary for both interrupt way and DMA way
elijahsj 1:8a094db1347f 1003 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
elijahsj 1:8a094db1347f 1004 // With our own async vector, tx/rx handlers can be different.
elijahsj 1:8a094db1347f 1005 obj->serial.vec = var->vec_async;
elijahsj 1:8a094db1347f 1006 obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
elijahsj 1:8a094db1347f 1007 serial_enable_interrupt(obj, TxIrq, enable);
elijahsj 1:8a094db1347f 1008 }
elijahsj 1:8a094db1347f 1009
elijahsj 1:8a094db1347f 1010 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
elijahsj 1:8a094db1347f 1011 {
elijahsj 1:8a094db1347f 1012 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 1013 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 1014 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 1015
elijahsj 1:8a094db1347f 1016 // Necessary for both interrupt way and DMA way
elijahsj 1:8a094db1347f 1017 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
elijahsj 1:8a094db1347f 1018 // With our own async vector, tx/rx handlers can be different.
elijahsj 1:8a094db1347f 1019 obj->serial.vec = var->vec_async;
elijahsj 1:8a094db1347f 1020 obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
elijahsj 1:8a094db1347f 1021 serial_enable_interrupt(obj, RxIrq, enable);
elijahsj 1:8a094db1347f 1022 }
elijahsj 1:8a094db1347f 1023
elijahsj 1:8a094db1347f 1024 static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable)
elijahsj 1:8a094db1347f 1025 {
elijahsj 1:8a094db1347f 1026 if (enable) {
elijahsj 1:8a094db1347f 1027 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 1028 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 1029 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 1030
elijahsj 1:8a094db1347f 1031 NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
elijahsj 1:8a094db1347f 1032 NVIC_EnableIRQ(modinit->irq_n);
elijahsj 1:8a094db1347f 1033
elijahsj 1:8a094db1347f 1034 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
elijahsj 1:8a094db1347f 1035 // Multiple serial S/W objects for single UART H/W module possibly.
elijahsj 1:8a094db1347f 1036 // Bind serial S/W object to UART H/W module as interrupt is enabled.
elijahsj 1:8a094db1347f 1037 var->obj = obj;
elijahsj 1:8a094db1347f 1038
elijahsj 1:8a094db1347f 1039 switch (irq) {
elijahsj 1:8a094db1347f 1040 // NOTE: Setting inten_msk first to avoid race condition
elijahsj 1:8a094db1347f 1041 case RxIrq:
elijahsj 1:8a094db1347f 1042 obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
elijahsj 1:8a094db1347f 1043 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elijahsj 1:8a094db1347f 1044 break;
elijahsj 1:8a094db1347f 1045 case TxIrq:
elijahsj 1:8a094db1347f 1046 obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
elijahsj 1:8a094db1347f 1047 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elijahsj 1:8a094db1347f 1048 break;
elijahsj 1:8a094db1347f 1049 }
elijahsj 1:8a094db1347f 1050 }
elijahsj 1:8a094db1347f 1051 else { // disable
elijahsj 1:8a094db1347f 1052 switch (irq) {
elijahsj 1:8a094db1347f 1053 case RxIrq:
elijahsj 1:8a094db1347f 1054 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elijahsj 1:8a094db1347f 1055 obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
elijahsj 1:8a094db1347f 1056 break;
elijahsj 1:8a094db1347f 1057 case TxIrq:
elijahsj 1:8a094db1347f 1058 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elijahsj 1:8a094db1347f 1059 obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
elijahsj 1:8a094db1347f 1060 break;
elijahsj 1:8a094db1347f 1061 }
elijahsj 1:8a094db1347f 1062 }
elijahsj 1:8a094db1347f 1063 }
elijahsj 1:8a094db1347f 1064
elijahsj 1:8a094db1347f 1065 static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq)
elijahsj 1:8a094db1347f 1066 {
elijahsj 1:8a094db1347f 1067 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elijahsj 1:8a094db1347f 1068 MBED_ASSERT(modinit != NULL);
elijahsj 1:8a094db1347f 1069 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
elijahsj 1:8a094db1347f 1070
elijahsj 1:8a094db1347f 1071 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
elijahsj 1:8a094db1347f 1072
elijahsj 1:8a094db1347f 1073 obj->serial.vec = var->vec;
elijahsj 1:8a094db1347f 1074 serial_enable_interrupt(obj, irq, obj->serial.irq_en);
elijahsj 1:8a094db1347f 1075 }
elijahsj 1:8a094db1347f 1076
elijahsj 1:8a094db1347f 1077 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
elijahsj 1:8a094db1347f 1078 {
elijahsj 1:8a094db1347f 1079 if (*dma_usage != DMA_USAGE_NEVER) {
elijahsj 1:8a094db1347f 1080 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
elijahsj 1:8a094db1347f 1081 *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
elijahsj 1:8a094db1347f 1082 }
elijahsj 1:8a094db1347f 1083 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
elijahsj 1:8a094db1347f 1084 *dma_usage = DMA_USAGE_NEVER;
elijahsj 1:8a094db1347f 1085 }
elijahsj 1:8a094db1347f 1086 }
elijahsj 1:8a094db1347f 1087 else {
elijahsj 1:8a094db1347f 1088 dma_channel_free(*dma_ch);
elijahsj 1:8a094db1347f 1089 *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
elijahsj 1:8a094db1347f 1090 }
elijahsj 1:8a094db1347f 1091 }
elijahsj 1:8a094db1347f 1092
elijahsj 1:8a094db1347f 1093 static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
elijahsj 1:8a094db1347f 1094 {
elijahsj 1:8a094db1347f 1095 int inten_msk = 0;
elijahsj 1:8a094db1347f 1096
elijahsj 1:8a094db1347f 1097 switch (irq) {
elijahsj 1:8a094db1347f 1098 case RxIrq:
elijahsj 1:8a094db1347f 1099 inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
elijahsj 1:8a094db1347f 1100 break;
elijahsj 1:8a094db1347f 1101 case TxIrq:
elijahsj 1:8a094db1347f 1102 inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
elijahsj 1:8a094db1347f 1103 break;
elijahsj 1:8a094db1347f 1104 }
elijahsj 1:8a094db1347f 1105
elijahsj 1:8a094db1347f 1106 return !! inten_msk;
elijahsj 1:8a094db1347f 1107 }
elijahsj 1:8a094db1347f 1108
elijahsj 1:8a094db1347f 1109 #endif // #if DEVICE_SERIAL_ASYNCH
elijahsj 1:8a094db1347f 1110 #endif // #if DEVICE_SERIAL