Elijah Stanger-Jones / mbed-dev-f303

test

targets/TARGET_Maxim/TARGET_MAX32600/serial_api.c@2:4364577b5ad8, 2020-11-09 (annotated)

Committer:
elijahsj
Date:
Mon Nov 09 00:33:19 2020 -0500
Revision:
2:4364577b5ad8
Parent:
1:8a094db1347f 
copied mbed library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elijahsj 1:8a094db1347f 1 /*******************************************************************************
elijahsj 1:8a094db1347f 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
elijahsj 1:8a094db1347f 3 *
elijahsj 1:8a094db1347f 4 * Permission is hereby granted, free of charge, to any person obtaining a
elijahsj 1:8a094db1347f 5 * copy of this software and associated documentation files (the "Software"),
elijahsj 1:8a094db1347f 6 * to deal in the Software without restriction, including without limitation
elijahsj 1:8a094db1347f 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
elijahsj 1:8a094db1347f 8 * and/or sell copies of the Software, and to permit persons to whom the
elijahsj 1:8a094db1347f 9 * Software is furnished to do so, subject to the following conditions:
elijahsj 1:8a094db1347f 10 *
elijahsj 1:8a094db1347f 11 * The above copyright notice and this permission notice shall be included
elijahsj 1:8a094db1347f 12 * in all copies or substantial portions of the Software.
elijahsj 1:8a094db1347f 13 *
elijahsj 1:8a094db1347f 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
elijahsj 1:8a094db1347f 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
elijahsj 1:8a094db1347f 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
elijahsj 1:8a094db1347f 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
elijahsj 1:8a094db1347f 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
elijahsj 1:8a094db1347f 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
elijahsj 1:8a094db1347f 20 * OTHER DEALINGS IN THE SOFTWARE.
elijahsj 1:8a094db1347f 21 *
elijahsj 1:8a094db1347f 22 * Except as contained in this notice, the name of Maxim Integrated
elijahsj 1:8a094db1347f 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
elijahsj 1:8a094db1347f 24 * Products, Inc. Branding Policy.
elijahsj 1:8a094db1347f 25 *
elijahsj 1:8a094db1347f 26 * The mere transfer of this software does not imply any licenses
elijahsj 1:8a094db1347f 27 * of trade secrets, proprietary technology, copyrights, patents,
elijahsj 1:8a094db1347f 28 * trademarks, maskwork rights, or any other form of intellectual
elijahsj 1:8a094db1347f 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
elijahsj 1:8a094db1347f 30 * ownership rights.
elijahsj 1:8a094db1347f 31 *******************************************************************************
elijahsj 1:8a094db1347f 32 */
elijahsj 1:8a094db1347f 33
elijahsj 1:8a094db1347f 34 #include <string.h>
elijahsj 1:8a094db1347f 35 #include "mbed_assert.h"
elijahsj 1:8a094db1347f 36 #include "cmsis.h"
elijahsj 1:8a094db1347f 37 #include "serial_api.h"
elijahsj 1:8a094db1347f 38 #include "gpio_api.h"
elijahsj 1:8a094db1347f 39 #include "uart_regs.h"
elijahsj 1:8a094db1347f 40 #include "ioman_regs.h"
elijahsj 1:8a094db1347f 41 #include "PeripheralPins.h"
elijahsj 1:8a094db1347f 42
elijahsj 1:8a094db1347f 43 #define UART_NUM 2
elijahsj 1:8a094db1347f 44 #define DEFAULT_BAUD 9600
elijahsj 1:8a094db1347f 45 #define DEFAULT_STOP 1
elijahsj 1:8a094db1347f 46 #define DEFAULT_PARITY ParityNone
elijahsj 1:8a094db1347f 47
elijahsj 1:8a094db1347f 48 #define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAME_ERROR | \
elijahsj 1:8a094db1347f 49 MXC_F_UART_INTFL_RX_PARITY_ERROR | \
elijahsj 1:8a094db1347f 50 MXC_F_UART_INTFL_RX_OVERRUN)
elijahsj 1:8a094db1347f 51
elijahsj 1:8a094db1347f 52 // Variables for managing the stdio UART
elijahsj 1:8a094db1347f 53 int stdio_uart_inited;
elijahsj 1:8a094db1347f 54 serial_t stdio_uart;
elijahsj 1:8a094db1347f 55
elijahsj 1:8a094db1347f 56 // Variables for interrupt driven
elijahsj 1:8a094db1347f 57 static uart_irq_handler irq_handler;
elijahsj 1:8a094db1347f 58 static uint32_t serial_irq_ids[UART_NUM];
elijahsj 1:8a094db1347f 59
elijahsj 1:8a094db1347f 60 //******************************************************************************
elijahsj 1:8a094db1347f 61 void serial_init(serial_t *obj, PinName tx, PinName rx)
elijahsj 1:8a094db1347f 62 {
elijahsj 1:8a094db1347f 63 // Determine which uart is associated with each pin
elijahsj 1:8a094db1347f 64 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
elijahsj 1:8a094db1347f 65 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
elijahsj 1:8a094db1347f 66 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
elijahsj 1:8a094db1347f 67
elijahsj 1:8a094db1347f 68 // Make sure that both pins are pointing to the same uart
elijahsj 1:8a094db1347f 69 MBED_ASSERT(uart != (UARTName)NC);
elijahsj 1:8a094db1347f 70
elijahsj 1:8a094db1347f 71 // Set the obj pointer to the proper uart
elijahsj 1:8a094db1347f 72 obj->uart = (mxc_uart_regs_t*)uart;
elijahsj 1:8a094db1347f 73
elijahsj 1:8a094db1347f 74 // Set the uart index
elijahsj 1:8a094db1347f 75 obj->index = MXC_UART_BASE_TO_INSTANCE(obj->uart);
elijahsj 1:8a094db1347f 76
elijahsj 1:8a094db1347f 77 // Configure the pins
elijahsj 1:8a094db1347f 78 pinmap_pinout(tx, PinMap_UART_TX);
elijahsj 1:8a094db1347f 79 pinmap_pinout(rx, PinMap_UART_RX);
elijahsj 1:8a094db1347f 80
elijahsj 1:8a094db1347f 81 // Flush the RX and TX FIFOs, clear the settings
elijahsj 1:8a094db1347f 82 obj->uart->ctrl = ( MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH);
elijahsj 1:8a094db1347f 83
elijahsj 1:8a094db1347f 84 // Disable interrupts
elijahsj 1:8a094db1347f 85 obj->uart->inten = 0;
elijahsj 1:8a094db1347f 86 obj->uart->intfl = 0;
elijahsj 1:8a094db1347f 87
elijahsj 1:8a094db1347f 88 // Configure to default settings
elijahsj 1:8a094db1347f 89 serial_baud(obj, DEFAULT_BAUD);
elijahsj 1:8a094db1347f 90 serial_format(obj, 8, ParityNone, 1);
elijahsj 1:8a094db1347f 91
elijahsj 1:8a094db1347f 92 // Manage stdio UART
elijahsj 1:8a094db1347f 93 if(uart == STDIO_UART) {
elijahsj 1:8a094db1347f 94 stdio_uart_inited = 1;
elijahsj 1:8a094db1347f 95 memcpy(&stdio_uart, obj, sizeof(serial_t));
elijahsj 1:8a094db1347f 96 }
elijahsj 1:8a094db1347f 97 }
elijahsj 1:8a094db1347f 98
elijahsj 1:8a094db1347f 99 //******************************************************************************
elijahsj 1:8a094db1347f 100 void serial_baud(serial_t *obj, int baudrate)
elijahsj 1:8a094db1347f 101 {
elijahsj 1:8a094db1347f 102 uint32_t idiv = 0, ddiv = 0, div = 0;
elijahsj 1:8a094db1347f 103
elijahsj 1:8a094db1347f 104 // Calculate the integer and decimal portions
elijahsj 1:8a094db1347f 105 div = SystemCoreClock / ((baudrate / 100) * 128);
elijahsj 1:8a094db1347f 106 idiv = (div / 100);
elijahsj 1:8a094db1347f 107 ddiv = (div - idiv * 100) * 128 / 100;
elijahsj 1:8a094db1347f 108
elijahsj 1:8a094db1347f 109 obj->uart->baud_int = idiv;
elijahsj 1:8a094db1347f 110 obj->uart->baud_div_128 = ddiv;
elijahsj 1:8a094db1347f 111
elijahsj 1:8a094db1347f 112 // Enable the baud clock
elijahsj 1:8a094db1347f 113 obj->uart->ctrl |= MXC_F_UART_CTRL_BAUD_CLK_EN;
elijahsj 1:8a094db1347f 114 }
elijahsj 1:8a094db1347f 115
elijahsj 1:8a094db1347f 116 //******************************************************************************
elijahsj 1:8a094db1347f 117 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
elijahsj 1:8a094db1347f 118 {
elijahsj 1:8a094db1347f 119
elijahsj 1:8a094db1347f 120 // Check the validity of the inputs
elijahsj 1:8a094db1347f 121 MBED_ASSERT((data_bits > 4) && (data_bits < 9));
elijahsj 1:8a094db1347f 122 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) ||
elijahsj 1:8a094db1347f 123 (parity == ParityEven) || (parity == ParityForced1) ||
elijahsj 1:8a094db1347f 124 (parity == ParityForced0));
elijahsj 1:8a094db1347f 125 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
elijahsj 1:8a094db1347f 126
elijahsj 1:8a094db1347f 127 // Adjust the stop and data bits
elijahsj 1:8a094db1347f 128 stop_bits -= 1;
elijahsj 1:8a094db1347f 129 data_bits -= 5;
elijahsj 1:8a094db1347f 130
elijahsj 1:8a094db1347f 131 // Adjust the parity setting
elijahsj 1:8a094db1347f 132 int paren = 0, mode = 0;
elijahsj 1:8a094db1347f 133 switch (parity) {
elijahsj 1:8a094db1347f 134 case ParityNone:
elijahsj 1:8a094db1347f 135 paren = 0;
elijahsj 1:8a094db1347f 136 mode = 0;
elijahsj 1:8a094db1347f 137 break;
elijahsj 1:8a094db1347f 138 case ParityOdd :
elijahsj 1:8a094db1347f 139 paren = 1;
elijahsj 1:8a094db1347f 140 mode = 0;
elijahsj 1:8a094db1347f 141 break;
elijahsj 1:8a094db1347f 142 case ParityEven:
elijahsj 1:8a094db1347f 143 paren = 1;
elijahsj 1:8a094db1347f 144 mode = 1;
elijahsj 1:8a094db1347f 145 break;
elijahsj 1:8a094db1347f 146 case ParityForced1:
elijahsj 1:8a094db1347f 147 // Hardware does not support forced parity
elijahsj 1:8a094db1347f 148 MBED_ASSERT(0);
elijahsj 1:8a094db1347f 149 break;
elijahsj 1:8a094db1347f 150 case ParityForced0:
elijahsj 1:8a094db1347f 151 // Hardware does not support forced parity
elijahsj 1:8a094db1347f 152 MBED_ASSERT(0);
elijahsj 1:8a094db1347f 153 break;
elijahsj 1:8a094db1347f 154 default:
elijahsj 1:8a094db1347f 155 paren = 1;
elijahsj 1:8a094db1347f 156 mode = 0;
elijahsj 1:8a094db1347f 157 break;
elijahsj 1:8a094db1347f 158 }
elijahsj 1:8a094db1347f 159
elijahsj 1:8a094db1347f 160 obj->uart->ctrl |= ((data_bits << MXC_F_UART_CTRL_CHAR_LENGTH_POS) |
elijahsj 1:8a094db1347f 161 (stop_bits << MXC_F_UART_CTRL_STOP_BIT_MODE_POS) |
elijahsj 1:8a094db1347f 162 (paren << MXC_F_UART_CTRL_PARITY_ENABLE_POS) |
elijahsj 1:8a094db1347f 163 (mode << MXC_F_UART_CTRL_PARITY_MODE_POS));
elijahsj 1:8a094db1347f 164 }
elijahsj 1:8a094db1347f 165
elijahsj 1:8a094db1347f 166 //******************************************************************************
elijahsj 1:8a094db1347f 167 void uart_handler(mxc_uart_regs_t* uart, int id)
elijahsj 1:8a094db1347f 168 {
elijahsj 1:8a094db1347f 169 // Check for errors or RX Threshold
elijahsj 1:8a094db1347f 170 if(uart->intfl & (MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS)) {
elijahsj 1:8a094db1347f 171 irq_handler(serial_irq_ids[id], RxIrq);
elijahsj 1:8a094db1347f 172 uart->intfl &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS);
elijahsj 1:8a094db1347f 173 }
elijahsj 1:8a094db1347f 174
elijahsj 1:8a094db1347f 175 // Check for TX Threshold
elijahsj 1:8a094db1347f 176 if(uart->intfl & MXC_F_UART_INTFL_TX_ALMOST_EMPTY) {
elijahsj 1:8a094db1347f 177 irq_handler(serial_irq_ids[id], TxIrq);
elijahsj 1:8a094db1347f 178 uart->intfl &= ~(MXC_F_UART_INTFL_TX_ALMOST_EMPTY);
elijahsj 1:8a094db1347f 179 }
elijahsj 1:8a094db1347f 180 }
elijahsj 1:8a094db1347f 181
elijahsj 1:8a094db1347f 182 void uart0_handler(void)
elijahsj 1:8a094db1347f 183 {
elijahsj 1:8a094db1347f 184 uart_handler(MXC_UART0, 0);
elijahsj 1:8a094db1347f 185 }
elijahsj 1:8a094db1347f 186 void uart1_handler(void)
elijahsj 1:8a094db1347f 187 {
elijahsj 1:8a094db1347f 188 uart_handler(MXC_UART1, 1);
elijahsj 1:8a094db1347f 189 }
elijahsj 1:8a094db1347f 190
elijahsj 1:8a094db1347f 191 //******************************************************************************
elijahsj 1:8a094db1347f 192 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
elijahsj 1:8a094db1347f 193 {
elijahsj 1:8a094db1347f 194 irq_handler = handler;
elijahsj 1:8a094db1347f 195 serial_irq_ids[obj->index] = id;
elijahsj 1:8a094db1347f 196 }
elijahsj 1:8a094db1347f 197
elijahsj 1:8a094db1347f 198 //******************************************************************************
elijahsj 1:8a094db1347f 199 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
elijahsj 1:8a094db1347f 200 {
elijahsj 1:8a094db1347f 201 if(obj->index == 0) {
elijahsj 1:8a094db1347f 202 NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler);
elijahsj 1:8a094db1347f 203 NVIC_EnableIRQ(UART0_IRQn);
elijahsj 1:8a094db1347f 204 } else {
elijahsj 1:8a094db1347f 205 NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler);
elijahsj 1:8a094db1347f 206 NVIC_EnableIRQ(UART1_IRQn);
elijahsj 1:8a094db1347f 207 }
elijahsj 1:8a094db1347f 208
elijahsj 1:8a094db1347f 209 if(irq == RxIrq) {
elijahsj 1:8a094db1347f 210 // Set the RX FIFO Threshold to 1
elijahsj 1:8a094db1347f 211 obj->uart->ctrl &= ~MXC_F_UART_CTRL_RX_THRESHOLD;
elijahsj 1:8a094db1347f 212 obj->uart->ctrl |= 0x1;
elijahsj 1:8a094db1347f 213 // Enable RX FIFO Threshold Interrupt
elijahsj 1:8a094db1347f 214 if(enable) {
elijahsj 1:8a094db1347f 215 // Clear pending interrupts
elijahsj 1:8a094db1347f 216 obj->uart->intfl = 0;
elijahsj 1:8a094db1347f 217 obj->uart->inten |= (MXC_F_UART_INTFL_RX_OVER_THRESHOLD |
elijahsj 1:8a094db1347f 218 UART_ERRORS);
elijahsj 1:8a094db1347f 219 } else {
elijahsj 1:8a094db1347f 220 // Clear pending interrupts
elijahsj 1:8a094db1347f 221 obj->uart->intfl = 0;
elijahsj 1:8a094db1347f 222 obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD |
elijahsj 1:8a094db1347f 223 UART_ERRORS);
elijahsj 1:8a094db1347f 224 }
elijahsj 1:8a094db1347f 225
elijahsj 1:8a094db1347f 226 } else if (irq == TxIrq) {
elijahsj 1:8a094db1347f 227 // Enable TX Almost empty Interrupt
elijahsj 1:8a094db1347f 228 if(enable) {
elijahsj 1:8a094db1347f 229 // Clear pending interrupts
elijahsj 1:8a094db1347f 230 obj->uart->intfl = 0;
elijahsj 1:8a094db1347f 231 obj->uart->inten |= MXC_F_UART_INTFL_TX_ALMOST_EMPTY;
elijahsj 1:8a094db1347f 232 } else {
elijahsj 1:8a094db1347f 233 // Clear pending interrupts
elijahsj 1:8a094db1347f 234 obj->uart->intfl = 0;
elijahsj 1:8a094db1347f 235 obj->uart->inten &= ~MXC_F_UART_INTFL_TX_ALMOST_EMPTY;
elijahsj 1:8a094db1347f 236 }
elijahsj 1:8a094db1347f 237
elijahsj 1:8a094db1347f 238 } else {
elijahsj 1:8a094db1347f 239 MBED_ASSERT(0);
elijahsj 1:8a094db1347f 240 }
elijahsj 1:8a094db1347f 241 }
elijahsj 1:8a094db1347f 242
elijahsj 1:8a094db1347f 243
elijahsj 1:8a094db1347f 244 //******************************************************************************
elijahsj 1:8a094db1347f 245 int serial_getc(serial_t *obj)
elijahsj 1:8a094db1347f 246 {
elijahsj 1:8a094db1347f 247 int c;
elijahsj 1:8a094db1347f 248
elijahsj 1:8a094db1347f 249 // Wait for data to be available
elijahsj 1:8a094db1347f 250 while(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY) {}
elijahsj 1:8a094db1347f 251 c = obj->uart->tx_rx_fifo & 0xFF;
elijahsj 1:8a094db1347f 252
elijahsj 1:8a094db1347f 253 return c;
elijahsj 1:8a094db1347f 254 }
elijahsj 1:8a094db1347f 255
elijahsj 1:8a094db1347f 256 //******************************************************************************
elijahsj 1:8a094db1347f 257 void serial_putc(serial_t *obj, int c)
elijahsj 1:8a094db1347f 258 {
elijahsj 1:8a094db1347f 259 // Wait for TXFIFO to not be full
elijahsj 1:8a094db1347f 260 while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {}
elijahsj 1:8a094db1347f 261 obj->uart->tx_rx_fifo = c;
elijahsj 1:8a094db1347f 262 }
elijahsj 1:8a094db1347f 263
elijahsj 1:8a094db1347f 264 //******************************************************************************
elijahsj 1:8a094db1347f 265 int serial_readable(serial_t *obj)
elijahsj 1:8a094db1347f 266 {
elijahsj 1:8a094db1347f 267 return (!(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY));
elijahsj 1:8a094db1347f 268 }
elijahsj 1:8a094db1347f 269
elijahsj 1:8a094db1347f 270 //******************************************************************************
elijahsj 1:8a094db1347f 271 int serial_writable(serial_t *obj)
elijahsj 1:8a094db1347f 272 {
elijahsj 1:8a094db1347f 273 return (!(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL));
elijahsj 1:8a094db1347f 274 }
elijahsj 1:8a094db1347f 275
elijahsj 1:8a094db1347f 276 //******************************************************************************
elijahsj 1:8a094db1347f 277 void serial_clear(serial_t *obj)
elijahsj 1:8a094db1347f 278 {
elijahsj 1:8a094db1347f 279 // Clear the rx and tx fifos
elijahsj 1:8a094db1347f 280 obj->uart->ctrl |= (MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH );
elijahsj 1:8a094db1347f 281 }
elijahsj 1:8a094db1347f 282
elijahsj 1:8a094db1347f 283 //******************************************************************************
elijahsj 1:8a094db1347f 284 void serial_break_set(serial_t *obj)
elijahsj 1:8a094db1347f 285 {
elijahsj 1:8a094db1347f 286 // Make sure that nothing is being sent
elijahsj 1:8a094db1347f 287 while (!(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_EMPTY));
elijahsj 1:8a094db1347f 288 while (obj->uart->status & MXC_F_UART_STATUS_TX_BUSY);
elijahsj 1:8a094db1347f 289
elijahsj 1:8a094db1347f 290 // Configure the GPIO to outpu 0
elijahsj 1:8a094db1347f 291 gpio_t tx_gpio;
elijahsj 1:8a094db1347f 292 switch (((UARTName)(obj->uart))) {
elijahsj 1:8a094db1347f 293 case UART_0:
elijahsj 1:8a094db1347f 294 gpio_init_out(&tx_gpio, UART0_TX);
elijahsj 1:8a094db1347f 295 break;
elijahsj 1:8a094db1347f 296 case UART_1:
elijahsj 1:8a094db1347f 297 gpio_init_out(&tx_gpio, UART1_TX);
elijahsj 1:8a094db1347f 298 break;
elijahsj 1:8a094db1347f 299 default:
elijahsj 1:8a094db1347f 300 gpio_init_out(&tx_gpio, (PinName)NC);
elijahsj 1:8a094db1347f 301 break;
elijahsj 1:8a094db1347f 302 }
elijahsj 1:8a094db1347f 303
elijahsj 1:8a094db1347f 304 gpio_write(&tx_gpio, 0);
elijahsj 1:8a094db1347f 305
elijahsj 1:8a094db1347f 306 // GPIO is setup now, but we need to maps gpio to the pin
elijahsj 1:8a094db1347f 307 switch (((UARTName)(obj->uart))) {
elijahsj 1:8a094db1347f 308 case UART_0:
elijahsj 1:8a094db1347f 309 MXC_IOMAN->uart0_req &= ~MXC_F_IOMAN_UART_CORE_IO;
elijahsj 1:8a094db1347f 310 MBED_ASSERT((MXC_IOMAN->uart0_ack & (MXC_F_IOMAN_UART_CORE_IO | MXC_F_IOMAN_UART_CORE_IO)) == 0);
elijahsj 1:8a094db1347f 311 break;
elijahsj 1:8a094db1347f 312 case UART_1:
elijahsj 1:8a094db1347f 313 MXC_IOMAN->uart1_req &= ~MXC_F_IOMAN_UART_CORE_IO;
elijahsj 1:8a094db1347f 314 MBED_ASSERT((MXC_IOMAN->uart1_ack & (MXC_F_IOMAN_UART_CORE_IO | MXC_F_IOMAN_UART_CORE_IO)) == 0);
elijahsj 1:8a094db1347f 315 break;
elijahsj 1:8a094db1347f 316 default:
elijahsj 1:8a094db1347f 317 break;
elijahsj 1:8a094db1347f 318 }
elijahsj 1:8a094db1347f 319 }
elijahsj 1:8a094db1347f 320
elijahsj 1:8a094db1347f 321 //******************************************************************************
elijahsj 1:8a094db1347f 322 void serial_break_clear(serial_t *obj)
elijahsj 1:8a094db1347f 323 {
elijahsj 1:8a094db1347f 324 // Configure the GPIO to output 1
elijahsj 1:8a094db1347f 325 gpio_t tx_gpio;
elijahsj 1:8a094db1347f 326 switch (((UARTName)(obj->uart))) {
elijahsj 1:8a094db1347f 327 case UART_0:
elijahsj 1:8a094db1347f 328 gpio_init_out(&tx_gpio, UART0_TX);
elijahsj 1:8a094db1347f 329 break;
elijahsj 1:8a094db1347f 330 case UART_1:
elijahsj 1:8a094db1347f 331 gpio_init_out(&tx_gpio, UART1_TX);
elijahsj 1:8a094db1347f 332 break;
elijahsj 1:8a094db1347f 333 default:
elijahsj 1:8a094db1347f 334 gpio_init_out(&tx_gpio, (PinName)NC);
elijahsj 1:8a094db1347f 335 break;
elijahsj 1:8a094db1347f 336 }
elijahsj 1:8a094db1347f 337
elijahsj 1:8a094db1347f 338 gpio_write(&tx_gpio, 1);
elijahsj 1:8a094db1347f 339
elijahsj 1:8a094db1347f 340 // Renable UART
elijahsj 1:8a094db1347f 341 switch (((UARTName)(obj->uart))) {
elijahsj 1:8a094db1347f 342 case UART_0:
elijahsj 1:8a094db1347f 343 serial_pinout_tx(UART0_TX);
elijahsj 1:8a094db1347f 344 break;
elijahsj 1:8a094db1347f 345 case UART_1:
elijahsj 1:8a094db1347f 346 serial_pinout_tx(UART1_TX);
elijahsj 1:8a094db1347f 347 break;
elijahsj 1:8a094db1347f 348 default:
elijahsj 1:8a094db1347f 349 serial_pinout_tx((PinName)NC);
elijahsj 1:8a094db1347f 350 break;
elijahsj 1:8a094db1347f 351 }
elijahsj 1:8a094db1347f 352 }
elijahsj 1:8a094db1347f 353
elijahsj 1:8a094db1347f 354 //******************************************************************************
elijahsj 1:8a094db1347f 355 void serial_pinout_tx(PinName tx)
elijahsj 1:8a094db1347f 356 {
elijahsj 1:8a094db1347f 357 pinmap_pinout(tx, PinMap_UART_TX);
elijahsj 1:8a094db1347f 358 }
elijahsj 1:8a094db1347f 359
elijahsj 1:8a094db1347f 360
elijahsj 1:8a094db1347f 361 //******************************************************************************
elijahsj 1:8a094db1347f 362 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
elijahsj 1:8a094db1347f 363 {
elijahsj 1:8a094db1347f 364 if(FlowControlNone == type) {
elijahsj 1:8a094db1347f 365 // Disable hardware flow control
elijahsj 1:8a094db1347f 366 obj->uart->ctrl &= ~(MXC_F_UART_CTRL_HW_FLOW_CTRL_EN);
elijahsj 1:8a094db1347f 367 return;
elijahsj 1:8a094db1347f 368 }
elijahsj 1:8a094db1347f 369
elijahsj 1:8a094db1347f 370 // Check to see if we can use HW flow control
elijahsj 1:8a094db1347f 371 UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
elijahsj 1:8a094db1347f 372 UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
elijahsj 1:8a094db1347f 373 UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
elijahsj 1:8a094db1347f 374
elijahsj 1:8a094db1347f 375 if((FlowControlCTS == type) || (FlowControlRTSCTS== type)) {
elijahsj 1:8a094db1347f 376 // Make sure pin is in the PinMap
elijahsj 1:8a094db1347f 377 MBED_ASSERT(uart_cts != (UARTName)NC);
elijahsj 1:8a094db1347f 378
elijahsj 1:8a094db1347f 379 // Enable the pin for CTS function
elijahsj 1:8a094db1347f 380 pinmap_pinout(txflow, PinMap_UART_CTS);
elijahsj 1:8a094db1347f 381 }
elijahsj 1:8a094db1347f 382
elijahsj 1:8a094db1347f 383 if((FlowControlRTS == type) || (FlowControlRTSCTS== type)) {
elijahsj 1:8a094db1347f 384 // Make sure pin is in the PinMap
elijahsj 1:8a094db1347f 385 MBED_ASSERT(uart_rts != (UARTName)NC);
elijahsj 1:8a094db1347f 386
elijahsj 1:8a094db1347f 387 // Enable the pin for RTS function
elijahsj 1:8a094db1347f 388 pinmap_pinout(rxflow, PinMap_UART_RTS);
elijahsj 1:8a094db1347f 389 }
elijahsj 1:8a094db1347f 390
elijahsj 1:8a094db1347f 391 if(FlowControlRTSCTS == type){
elijahsj 1:8a094db1347f 392 // Make sure that the pins are pointing to the same UART
elijahsj 1:8a094db1347f 393 MBED_ASSERT(uart != (UARTName)NC);
elijahsj 1:8a094db1347f 394 }
elijahsj 1:8a094db1347f 395
elijahsj 1:8a094db1347f 396 // Enable hardware flow control
elijahsj 1:8a094db1347f 397 obj->uart->ctrl |= MXC_F_UART_CTRL_HW_FLOW_CTRL_EN;
elijahsj 1:8a094db1347f 398 }