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Diff: TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma.h
- Revision:
- 108:34e6b704fe68
- Parent:
- 93:e188a91d3eaa
diff -r 4f6c30876dfa -r 34e6b704fe68 TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma.h --- a/TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma.h Wed Sep 16 15:32:31 2015 +0100 +++ b/TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma.h Fri Oct 02 07:35:07 2015 +0200 @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_dma.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -55,6 +55,7 @@ */ /* Exported types ------------------------------------------------------------*/ + /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ @@ -87,7 +88,6 @@ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_Priority_level */ - } DMA_InitTypeDef; /** @@ -106,12 +106,11 @@ typedef enum { HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */ + HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */ HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ - HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ - + HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ }HAL_DMA_StateTypeDef; /** @@ -121,9 +120,7 @@ { HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ - -}HAL_DMA_LevelCompleteTypeDef; - +}HAL_DMA_LevelCompleteTypeDef; /** * @brief DMA handle Structure definition @@ -136,7 +133,7 @@ HAL_LockTypeDef Lock; /*!< DMA locking object */ - HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ void *Parent; /*!< Parent object state */ @@ -147,13 +144,14 @@ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ __IO uint32_t ErrorCode; /*!< DMA Error code */ - } DMA_HandleTypeDef; + /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup DMA_Exported_Constants DMA Exported Constants * @{ */ @@ -175,29 +173,15 @@ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) /** * @} */ - -/** @defgroup DMA_Data_buffer_size DMA Data buffer size - * @{ - */ -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) -/** - * @} - */ - + /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ */ #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) /** * @} */ @@ -207,9 +191,6 @@ */ #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) /** * @} */ @@ -220,25 +201,16 @@ #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) /** * @} */ - /** @defgroup DMA_Memory_data_size DMA Memory data size * @{ */ #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) /** * @} */ @@ -248,9 +220,6 @@ */ #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */ #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) /** * @} */ @@ -262,11 +231,6 @@ #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) /** * @} */ @@ -275,11 +239,9 @@ /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions * @{ */ - #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) - /** * @} */ @@ -317,16 +279,78 @@ #define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */ #define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_DMA_RMP) +/** @defgroup HAL_DMA_remapping HAL DMA remapping + * Elements values convention: 0xYYYYYYYY + * - YYYYYYYY : Position in the SYSCFG register CFGR1 + * @{ + */ +#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap + 0: No remap (ADC DMA requests mapped on DMA channel 1 + 1: Remap (ADC DMA requests mapped on DMA channel 2 */ +#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap + 0: No remap (USART1_TX DMA request mapped on DMA channel 2 + 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ +#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap + 0: No remap (USART1_RX DMA request mapped on DMA channel 3 + 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ +#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap + 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) + 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ +#define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap + 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 + 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ +#if defined (STM32F070xB) +#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only. + 0: Disabled, need to remap before use + 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ + +#endif + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) +#define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only + 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) + 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ +#define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only + 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) + 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ +#define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) + 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ +#define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) + 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ +#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) + 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ +#define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) + 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ +#define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) + 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ +#define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) + 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ +#define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) + 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ +#endif /** * @} */ +#endif /* SYSCFG_CFGR1_DMA_RMP */ /** * @} */ -/* Exported macros -----------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Macros DMA Exported Macros * @{ */ @@ -340,14 +364,14 @@ /** * @brief Enable the specified DMA Channel. * @param __HANDLE__: DMA handle - * @retval None. + * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) /** * @brief Disable the specified DMA Channel. * @param __HANDLE__: DMA handle - * @retval None. + * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) @@ -379,7 +403,7 @@ #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) /** - * @brief Checks whether the specified DMA Channel interrupt has occurred or not. + * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt source to check. * This parameter can be one of the following values: @@ -390,6 +414,18 @@ */ #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#if defined(SYSCFG_CFGR1_DMA_RMP) +/** @brief DMA remapping enable/disable macros + * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping + */ +#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ + SYSCFG->CFGR1 |= (__DMA_REMAP__); \ + }while(0) +#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ + SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ + }while(0) +#endif /* SYSCFG_CFGR1_DMA_RMP */ + /** * @} */ @@ -398,11 +434,11 @@ #include "stm32f0xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA_Exported_Functions DMA Exported Functions +/** @addtogroup DMA_Exported_Functions * @{ */ + /** @addtogroup DMA_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions *****************************/ @@ -413,10 +449,9 @@ */ /** @addtogroup DMA_Exported_Functions_Group2 - * @brief I/O operation functions * @{ */ -/* IO operation functions *****************************************************/ +/* Input and Output operation functions *****************************************************/ HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); @@ -426,16 +461,86 @@ * @} */ -/* Peripheral State and Error functions ***************************************/ /** @addtogroup DMA_Exported_Functions_Group3 - * @brief Peripheral State functions * @{ */ +/* Peripheral State and Error functions ***************************************/ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Macros + * @{ */ +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +#if defined(SYSCFG_CFGR1_DMA_RMP) + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \ + ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \ + ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \ + ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ + ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \ + ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \ + ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \ + ((RMP) == DMA_REMAP_TIM3_DMA_CH6)) +#elif defined (STM32F070xB) +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ + ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) +#else +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) +#endif + +#endif /* SYSCFG_CFGR1_DMA_RMP */ + + +/** + * @} + */ /** * @} @@ -443,10 +548,6 @@ /** * @} - */ - -/** - * @} */ #ifdef __cplusplus