Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.
Dependents: 1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB
Fork of mbed by
TARGET_MAXWSNENV/pwrseq_regs.h@99:dbbf35b96557, 2015-05-13 (annotated)
- Committer:
- Kojto
- Date:
- Wed May 13 08:08:21 2015 +0200
- Revision:
- 99:dbbf35b96557
Release 99 of the mbed library
Changes:
- new targets - MAXWSNENV, DISCO_L053C8
- STM32F4xx - ST Cube driver
- KSDK mcu - SPI timing fix
- Nordic - update to softdevice s130
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 99:dbbf35b96557 | 1 | /******************************************************************************* |
Kojto | 99:dbbf35b96557 | 2 | * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. |
Kojto | 99:dbbf35b96557 | 3 | * |
Kojto | 99:dbbf35b96557 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
Kojto | 99:dbbf35b96557 | 5 | * copy of this software and associated documentation files (the "Software"), |
Kojto | 99:dbbf35b96557 | 6 | * to deal in the Software without restriction, including without limitation |
Kojto | 99:dbbf35b96557 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
Kojto | 99:dbbf35b96557 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
Kojto | 99:dbbf35b96557 | 9 | * Software is furnished to do so, subject to the following conditions: |
Kojto | 99:dbbf35b96557 | 10 | * |
Kojto | 99:dbbf35b96557 | 11 | * The above copyright notice and this permission notice shall be included |
Kojto | 99:dbbf35b96557 | 12 | * in all copies or substantial portions of the Software. |
Kojto | 99:dbbf35b96557 | 13 | * |
Kojto | 99:dbbf35b96557 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
Kojto | 99:dbbf35b96557 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
Kojto | 99:dbbf35b96557 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
Kojto | 99:dbbf35b96557 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
Kojto | 99:dbbf35b96557 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
Kojto | 99:dbbf35b96557 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
Kojto | 99:dbbf35b96557 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
Kojto | 99:dbbf35b96557 | 21 | * |
Kojto | 99:dbbf35b96557 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
Kojto | 99:dbbf35b96557 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
Kojto | 99:dbbf35b96557 | 24 | * Products, Inc. Branding Policy. |
Kojto | 99:dbbf35b96557 | 25 | * |
Kojto | 99:dbbf35b96557 | 26 | * The mere transfer of this software does not imply any licenses |
Kojto | 99:dbbf35b96557 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
Kojto | 99:dbbf35b96557 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
Kojto | 99:dbbf35b96557 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
Kojto | 99:dbbf35b96557 | 30 | * ownership rights. |
Kojto | 99:dbbf35b96557 | 31 | ******************************************************************************* |
Kojto | 99:dbbf35b96557 | 32 | */ |
Kojto | 99:dbbf35b96557 | 33 | |
Kojto | 99:dbbf35b96557 | 34 | #ifndef _MXC_PWRSEQ_REGS_H |
Kojto | 99:dbbf35b96557 | 35 | #define _MXC_PWRSEQ_REGS_H |
Kojto | 99:dbbf35b96557 | 36 | |
Kojto | 99:dbbf35b96557 | 37 | #ifdef __cplusplus |
Kojto | 99:dbbf35b96557 | 38 | extern "C" { |
Kojto | 99:dbbf35b96557 | 39 | #endif |
Kojto | 99:dbbf35b96557 | 40 | |
Kojto | 99:dbbf35b96557 | 41 | #include <stdint.h> |
Kojto | 99:dbbf35b96557 | 42 | |
Kojto | 99:dbbf35b96557 | 43 | /** |
Kojto | 99:dbbf35b96557 | 44 | * @file pwrseq_regs.h |
Kojto | 99:dbbf35b96557 | 45 | * @addtogroup pwrseq PWRSEQ |
Kojto | 99:dbbf35b96557 | 46 | * @{ |
Kojto | 99:dbbf35b96557 | 47 | */ |
Kojto | 99:dbbf35b96557 | 48 | |
Kojto | 99:dbbf35b96557 | 49 | /* Offset Register Description |
Kojto | 99:dbbf35b96557 | 50 | ====== ================================================= */ |
Kojto | 99:dbbf35b96557 | 51 | typedef struct { |
Kojto | 99:dbbf35b96557 | 52 | __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */ |
Kojto | 99:dbbf35b96557 | 53 | __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */ |
Kojto | 99:dbbf35b96557 | 54 | __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */ |
Kojto | 99:dbbf35b96557 | 55 | __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */ |
Kojto | 99:dbbf35b96557 | 56 | __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 */ |
Kojto | 99:dbbf35b96557 | 57 | __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */ |
Kojto | 99:dbbf35b96557 | 58 | __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */ |
Kojto | 99:dbbf35b96557 | 59 | __I uint32_t rsv001C; /* 0x001C */ |
Kojto | 99:dbbf35b96557 | 60 | __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */ |
Kojto | 99:dbbf35b96557 | 61 | __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */ |
Kojto | 99:dbbf35b96557 | 62 | } mxc_pwrseq_regs_t; |
Kojto | 99:dbbf35b96557 | 63 | |
Kojto | 99:dbbf35b96557 | 64 | |
Kojto | 99:dbbf35b96557 | 65 | /* |
Kojto | 99:dbbf35b96557 | 66 | Register offsets for module PWRSEQ. |
Kojto | 99:dbbf35b96557 | 67 | */ |
Kojto | 99:dbbf35b96557 | 68 | #define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL) |
Kojto | 99:dbbf35b96557 | 69 | #define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL) |
Kojto | 99:dbbf35b96557 | 70 | #define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL) |
Kojto | 99:dbbf35b96557 | 71 | #define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL) |
Kojto | 99:dbbf35b96557 | 72 | #define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL) |
Kojto | 99:dbbf35b96557 | 73 | #define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL) |
Kojto | 99:dbbf35b96557 | 74 | #define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL) |
Kojto | 99:dbbf35b96557 | 75 | #define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL) |
Kojto | 99:dbbf35b96557 | 76 | #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL) |
Kojto | 99:dbbf35b96557 | 77 | |
Kojto | 99:dbbf35b96557 | 78 | |
Kojto | 99:dbbf35b96557 | 79 | /* |
Kojto | 99:dbbf35b96557 | 80 | Field positions and masks for module PWRSEQ. |
Kojto | 99:dbbf35b96557 | 81 | */ |
Kojto | 99:dbbf35b96557 | 82 | #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0 |
Kojto | 99:dbbf35b96557 | 83 | #define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS)) |
Kojto | 99:dbbf35b96557 | 84 | #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1 |
Kojto | 99:dbbf35b96557 | 85 | #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS)) |
Kojto | 99:dbbf35b96557 | 86 | #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2 |
Kojto | 99:dbbf35b96557 | 87 | #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS)) |
Kojto | 99:dbbf35b96557 | 88 | #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS 3 |
Kojto | 99:dbbf35b96557 | 89 | #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS)) |
Kojto | 99:dbbf35b96557 | 90 | #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS 4 |
Kojto | 99:dbbf35b96557 | 91 | #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS)) |
Kojto | 99:dbbf35b96557 | 92 | #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS 5 |
Kojto | 99:dbbf35b96557 | 93 | #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS)) |
Kojto | 99:dbbf35b96557 | 94 | #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS 6 |
Kojto | 99:dbbf35b96557 | 95 | #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS)) |
Kojto | 99:dbbf35b96557 | 96 | #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7 |
Kojto | 99:dbbf35b96557 | 97 | #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS)) |
Kojto | 99:dbbf35b96557 | 98 | #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8 |
Kojto | 99:dbbf35b96557 | 99 | #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS)) |
Kojto | 99:dbbf35b96557 | 100 | #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9 |
Kojto | 99:dbbf35b96557 | 101 | #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS)) |
Kojto | 99:dbbf35b96557 | 102 | #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10 |
Kojto | 99:dbbf35b96557 | 103 | #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS)) |
Kojto | 99:dbbf35b96557 | 104 | #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11 |
Kojto | 99:dbbf35b96557 | 105 | #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS)) |
Kojto | 99:dbbf35b96557 | 106 | #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12 |
Kojto | 99:dbbf35b96557 | 107 | #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS)) |
Kojto | 99:dbbf35b96557 | 108 | #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS 13 |
Kojto | 99:dbbf35b96557 | 109 | #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS)) |
Kojto | 99:dbbf35b96557 | 110 | #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS 14 |
Kojto | 99:dbbf35b96557 | 111 | #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS)) |
Kojto | 99:dbbf35b96557 | 112 | #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS 15 |
Kojto | 99:dbbf35b96557 | 113 | #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS)) |
Kojto | 99:dbbf35b96557 | 114 | #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS 16 |
Kojto | 99:dbbf35b96557 | 115 | #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS)) |
Kojto | 99:dbbf35b96557 | 116 | #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17 |
Kojto | 99:dbbf35b96557 | 117 | #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS)) |
Kojto | 99:dbbf35b96557 | 118 | #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS 18 |
Kojto | 99:dbbf35b96557 | 119 | #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS)) |
Kojto | 99:dbbf35b96557 | 120 | #define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS 19 |
Kojto | 99:dbbf35b96557 | 121 | #define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS)) |
Kojto | 99:dbbf35b96557 | 122 | |
Kojto | 99:dbbf35b96557 | 123 | #define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS 0 |
Kojto | 99:dbbf35b96557 | 124 | #define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS)) |
Kojto | 99:dbbf35b96557 | 125 | #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS 8 |
Kojto | 99:dbbf35b96557 | 126 | #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS)) |
Kojto | 99:dbbf35b96557 | 127 | #define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS 9 |
Kojto | 99:dbbf35b96557 | 128 | #define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS)) |
Kojto | 99:dbbf35b96557 | 129 | #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS 10 |
Kojto | 99:dbbf35b96557 | 130 | #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS)) |
Kojto | 99:dbbf35b96557 | 131 | #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS 11 |
Kojto | 99:dbbf35b96557 | 132 | #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS)) |
Kojto | 99:dbbf35b96557 | 133 | #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS 12 |
Kojto | 99:dbbf35b96557 | 134 | #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS)) |
Kojto | 99:dbbf35b96557 | 135 | #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS 13 |
Kojto | 99:dbbf35b96557 | 136 | #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS)) |
Kojto | 99:dbbf35b96557 | 137 | #define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS 14 |
Kojto | 99:dbbf35b96557 | 138 | #define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS)) |
Kojto | 99:dbbf35b96557 | 139 | |
Kojto | 99:dbbf35b96557 | 140 | #define MXC_F_PWRSEQ_REG2_PWR_RST3_POS 0 |
Kojto | 99:dbbf35b96557 | 141 | #define MXC_F_PWRSEQ_REG2_PWR_RST3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS)) |
Kojto | 99:dbbf35b96557 | 142 | #define MXC_F_PWRSEQ_REG2_PWR_W3_POS 5 |
Kojto | 99:dbbf35b96557 | 143 | #define MXC_F_PWRSEQ_REG2_PWR_W3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS)) |
Kojto | 99:dbbf35b96557 | 144 | #define MXC_F_PWRSEQ_REG2_PWR_W1_POS 10 |
Kojto | 99:dbbf35b96557 | 145 | #define MXC_F_PWRSEQ_REG2_PWR_W1 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS)) |
Kojto | 99:dbbf35b96557 | 146 | #define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS 15 |
Kojto | 99:dbbf35b96557 | 147 | #define MXC_F_PWRSEQ_REG2_PWR_W1_LOW ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS)) |
Kojto | 99:dbbf35b96557 | 148 | #define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS 20 |
Kojto | 99:dbbf35b96557 | 149 | #define MXC_F_PWRSEQ_REG2_PWR_WRTC ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS)) |
Kojto | 99:dbbf35b96557 | 150 | #define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS 25 |
Kojto | 99:dbbf35b96557 | 151 | #define MXC_F_PWRSEQ_REG2_PWR_WVDDA3 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS)) |
Kojto | 99:dbbf35b96557 | 152 | |
Kojto | 99:dbbf35b96557 | 153 | #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0 |
Kojto | 99:dbbf35b96557 | 154 | #define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS)) |
Kojto | 99:dbbf35b96557 | 155 | #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS 3 |
Kojto | 99:dbbf35b96557 | 156 | #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS)) |
Kojto | 99:dbbf35b96557 | 157 | #define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS 5 |
Kojto | 99:dbbf35b96557 | 158 | #define MXC_F_PWRSEQ_REG3_PWR_SVMSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS)) |
Kojto | 99:dbbf35b96557 | 159 | #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS 8 |
Kojto | 99:dbbf35b96557 | 160 | #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS)) |
Kojto | 99:dbbf35b96557 | 161 | #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS 10 |
Kojto | 99:dbbf35b96557 | 162 | #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS)) |
Kojto | 99:dbbf35b96557 | 163 | #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 13 |
Kojto | 99:dbbf35b96557 | 164 | #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS)) |
Kojto | 99:dbbf35b96557 | 165 | #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 15 |
Kojto | 99:dbbf35b96557 | 166 | #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS)) |
Kojto | 99:dbbf35b96557 | 167 | #define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS 16 |
Kojto | 99:dbbf35b96557 | 168 | #define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS)) |
Kojto | 99:dbbf35b96557 | 169 | #define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS 17 |
Kojto | 99:dbbf35b96557 | 170 | #define MXC_F_PWRSEQ_REG3_PWR_BO_TC ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS)) |
Kojto | 99:dbbf35b96557 | 171 | |
Kojto | 99:dbbf35b96557 | 172 | #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0 |
Kojto | 99:dbbf35b96557 | 173 | #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS)) |
Kojto | 99:dbbf35b96557 | 174 | #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1 |
Kojto | 99:dbbf35b96557 | 175 | #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS)) |
Kojto | 99:dbbf35b96557 | 176 | #define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS 2 |
Kojto | 99:dbbf35b96557 | 177 | #define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS)) |
Kojto | 99:dbbf35b96557 | 178 | #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3 |
Kojto | 99:dbbf35b96557 | 179 | #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS)) |
Kojto | 99:dbbf35b96557 | 180 | #define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS 4 |
Kojto | 99:dbbf35b96557 | 181 | #define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS)) |
Kojto | 99:dbbf35b96557 | 182 | #define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS 5 |
Kojto | 99:dbbf35b96557 | 183 | #define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS)) |
Kojto | 99:dbbf35b96557 | 184 | #define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS 6 |
Kojto | 99:dbbf35b96557 | 185 | #define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS)) |
Kojto | 99:dbbf35b96557 | 186 | |
Kojto | 99:dbbf35b96557 | 187 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0 |
Kojto | 99:dbbf35b96557 | 188 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS)) |
Kojto | 99:dbbf35b96557 | 189 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS 6 |
Kojto | 99:dbbf35b96557 | 190 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8 ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS)) |
Kojto | 99:dbbf35b96557 | 191 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS 10 |
Kojto | 99:dbbf35b96557 | 192 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS)) |
Kojto | 99:dbbf35b96557 | 193 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS 15 |
Kojto | 99:dbbf35b96557 | 194 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS)) |
Kojto | 99:dbbf35b96557 | 195 | |
Kojto | 99:dbbf35b96557 | 196 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0 |
Kojto | 99:dbbf35b96557 | 197 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS)) |
Kojto | 99:dbbf35b96557 | 198 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3 |
Kojto | 99:dbbf35b96557 | 199 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS)) |
Kojto | 99:dbbf35b96557 | 200 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7 |
Kojto | 99:dbbf35b96557 | 201 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS)) |
Kojto | 99:dbbf35b96557 | 202 | |
Kojto | 99:dbbf35b96557 | 203 | #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0 |
Kojto | 99:dbbf35b96557 | 204 | #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS)) |
Kojto | 99:dbbf35b96557 | 205 | #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1 |
Kojto | 99:dbbf35b96557 | 206 | #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS)) |
Kojto | 99:dbbf35b96557 | 207 | #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS 2 |
Kojto | 99:dbbf35b96557 | 208 | #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS)) |
Kojto | 99:dbbf35b96557 | 209 | #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS 3 |
Kojto | 99:dbbf35b96557 | 210 | #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS)) |
Kojto | 99:dbbf35b96557 | 211 | #define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS 4 |
Kojto | 99:dbbf35b96557 | 212 | #define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS)) |
Kojto | 99:dbbf35b96557 | 213 | #define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS 5 |
Kojto | 99:dbbf35b96557 | 214 | #define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS)) |
Kojto | 99:dbbf35b96557 | 215 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS 6 |
Kojto | 99:dbbf35b96557 | 216 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS)) |
Kojto | 99:dbbf35b96557 | 217 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS 7 |
Kojto | 99:dbbf35b96557 | 218 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS)) |
Kojto | 99:dbbf35b96557 | 219 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS 8 |
Kojto | 99:dbbf35b96557 | 220 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS)) |
Kojto | 99:dbbf35b96557 | 221 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS 9 |
Kojto | 99:dbbf35b96557 | 222 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS)) |
Kojto | 99:dbbf35b96557 | 223 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS 10 |
Kojto | 99:dbbf35b96557 | 224 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS)) |
Kojto | 99:dbbf35b96557 | 225 | #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS 11 |
Kojto | 99:dbbf35b96557 | 226 | #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS)) |
Kojto | 99:dbbf35b96557 | 227 | #define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS 12 |
Kojto | 99:dbbf35b96557 | 228 | #define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS)) |
Kojto | 99:dbbf35b96557 | 229 | #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 13 |
Kojto | 99:dbbf35b96557 | 230 | #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS)) |
Kojto | 99:dbbf35b96557 | 231 | #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 14 |
Kojto | 99:dbbf35b96557 | 232 | #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS)) |
Kojto | 99:dbbf35b96557 | 233 | #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 15 |
Kojto | 99:dbbf35b96557 | 234 | #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS)) |
Kojto | 99:dbbf35b96557 | 235 | #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 16 |
Kojto | 99:dbbf35b96557 | 236 | #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS)) |
Kojto | 99:dbbf35b96557 | 237 | #define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS 17 |
Kojto | 99:dbbf35b96557 | 238 | #define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS)) |
Kojto | 99:dbbf35b96557 | 239 | #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18 |
Kojto | 99:dbbf35b96557 | 240 | #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) |
Kojto | 99:dbbf35b96557 | 241 | #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19 |
Kojto | 99:dbbf35b96557 | 242 | #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) |
Kojto | 99:dbbf35b96557 | 243 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS 20 |
Kojto | 99:dbbf35b96557 | 244 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS)) |
Kojto | 99:dbbf35b96557 | 245 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS 21 |
Kojto | 99:dbbf35b96557 | 246 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS)) |
Kojto | 99:dbbf35b96557 | 247 | |
Kojto | 99:dbbf35b96557 | 248 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1 |
Kojto | 99:dbbf35b96557 | 249 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS)) |
Kojto | 99:dbbf35b96557 | 250 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS 2 |
Kojto | 99:dbbf35b96557 | 251 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS)) |
Kojto | 99:dbbf35b96557 | 252 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS 3 |
Kojto | 99:dbbf35b96557 | 253 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS)) |
Kojto | 99:dbbf35b96557 | 254 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS 4 |
Kojto | 99:dbbf35b96557 | 255 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS)) |
Kojto | 99:dbbf35b96557 | 256 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS 5 |
Kojto | 99:dbbf35b96557 | 257 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS)) |
Kojto | 99:dbbf35b96557 | 258 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS 6 |
Kojto | 99:dbbf35b96557 | 259 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS)) |
Kojto | 99:dbbf35b96557 | 260 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS 7 |
Kojto | 99:dbbf35b96557 | 261 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS)) |
Kojto | 99:dbbf35b96557 | 262 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS 8 |
Kojto | 99:dbbf35b96557 | 263 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS)) |
Kojto | 99:dbbf35b96557 | 264 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS 9 |
Kojto | 99:dbbf35b96557 | 265 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS)) |
Kojto | 99:dbbf35b96557 | 266 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS 10 |
Kojto | 99:dbbf35b96557 | 267 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS)) |
Kojto | 99:dbbf35b96557 | 268 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS 11 |
Kojto | 99:dbbf35b96557 | 269 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS)) |
Kojto | 99:dbbf35b96557 | 270 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS 12 |
Kojto | 99:dbbf35b96557 | 271 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS)) |
Kojto | 99:dbbf35b96557 | 272 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 13 |
Kojto | 99:dbbf35b96557 | 273 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS)) |
Kojto | 99:dbbf35b96557 | 274 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 14 |
Kojto | 99:dbbf35b96557 | 275 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS)) |
Kojto | 99:dbbf35b96557 | 276 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 15 |
Kojto | 99:dbbf35b96557 | 277 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS)) |
Kojto | 99:dbbf35b96557 | 278 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 16 |
Kojto | 99:dbbf35b96557 | 279 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS)) |
Kojto | 99:dbbf35b96557 | 280 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS 17 |
Kojto | 99:dbbf35b96557 | 281 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS)) |
Kojto | 99:dbbf35b96557 | 282 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18 |
Kojto | 99:dbbf35b96557 | 283 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) |
Kojto | 99:dbbf35b96557 | 284 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19 |
Kojto | 99:dbbf35b96557 | 285 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) |
Kojto | 99:dbbf35b96557 | 286 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS 20 |
Kojto | 99:dbbf35b96557 | 287 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS)) |
Kojto | 99:dbbf35b96557 | 288 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS 21 |
Kojto | 99:dbbf35b96557 | 289 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS)) |
Kojto | 99:dbbf35b96557 | 290 | |
Kojto | 99:dbbf35b96557 | 291 | #ifdef __cplusplus |
Kojto | 99:dbbf35b96557 | 292 | } |
Kojto | 99:dbbf35b96557 | 293 | #endif |
Kojto | 99:dbbf35b96557 | 294 | |
Kojto | 99:dbbf35b96557 | 295 | /** |
Kojto | 99:dbbf35b96557 | 296 | * @} |
Kojto | 99:dbbf35b96557 | 297 | */ |
Kojto | 99:dbbf35b96557 | 298 | |
Kojto | 99:dbbf35b96557 | 299 | #endif /* _MXC_PWRSEQ_REGS_H */ |