Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

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Fork of mbed by mbed official

TARGET_ARCH_MAX/stm32f4xx_ll_sdmmc.h@106:ba1f97679dad, 2015-09-02 (annotated)

Committer:
Kojto
Date:
Wed Sep 02 14:17:43 2015 +0100
Revision:
106:ba1f97679dad
Parent:
99:dbbf35b96557
Child:
110:165afa46840b
Release 106  of the mbed library



Changes:

- new platform - Nucleo F446RE

- STM32F4 Cube driver update v2.3.2

- ST cmsis driver v2.3.2

- nordic bugfix gcc linker start address

- lpc11u68 - bugfix for serial ports

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_ll_sdmmc.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
Kojto 106:ba1f97679dad 5 * @version V1.3.2
Kojto 106:ba1f97679dad 6 * @date 26-June-2015
bogdanm 89:552587b429a1 7 * @brief Header file of SDMMC HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_LL_SDMMC_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_LL_SDMMC_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_Driver
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
bogdanm 89:552587b429a1 52
Kojto 99:dbbf35b96557 53 /** @addtogroup SDMMC_LL
bogdanm 89:552587b429a1 54 * @{
bogdanm 89:552587b429a1 55 */
bogdanm 89:552587b429a1 56
bogdanm 89:552587b429a1 57 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
bogdanm 92:4fc01daae5a5 59 * @{
bogdanm 92:4fc01daae5a5 60 */
bogdanm 92:4fc01daae5a5 61
bogdanm 89:552587b429a1 62 /**
bogdanm 89:552587b429a1 63 * @brief SDMMC Configuration Structure definition
bogdanm 89:552587b429a1 64 */
bogdanm 89:552587b429a1 65 typedef struct
bogdanm 89:552587b429a1 66 {
bogdanm 89:552587b429a1 67 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
bogdanm 89:552587b429a1 68 This parameter can be a value of @ref SDIO_Clock_Edge */
bogdanm 89:552587b429a1 69
bogdanm 89:552587b429a1 70 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
bogdanm 89:552587b429a1 71 enabled or disabled.
bogdanm 89:552587b429a1 72 This parameter can be a value of @ref SDIO_Clock_Bypass */
bogdanm 89:552587b429a1 73
bogdanm 89:552587b429a1 74 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
bogdanm 89:552587b429a1 75 disabled when the bus is idle.
bogdanm 89:552587b429a1 76 This parameter can be a value of @ref SDIO_Clock_Power_Save */
bogdanm 89:552587b429a1 77
bogdanm 89:552587b429a1 78 uint32_t BusWide; /*!< Specifies the SDIO bus width.
bogdanm 89:552587b429a1 79 This parameter can be a value of @ref SDIO_Bus_Wide */
bogdanm 89:552587b429a1 80
bogdanm 89:552587b429a1 81 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
bogdanm 89:552587b429a1 82 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
bogdanm 89:552587b429a1 83
bogdanm 89:552587b429a1 84 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
bogdanm 89:552587b429a1 85 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 86
bogdanm 89:552587b429a1 87 }SDIO_InitTypeDef;
bogdanm 89:552587b429a1 88
bogdanm 89:552587b429a1 89
bogdanm 89:552587b429a1 90 /**
bogdanm 89:552587b429a1 91 * @brief SDIO Command Control structure
bogdanm 89:552587b429a1 92 */
bogdanm 89:552587b429a1 93 typedef struct
bogdanm 89:552587b429a1 94 {
bogdanm 89:552587b429a1 95 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
bogdanm 89:552587b429a1 96 to a card as part of a command message. If a command
bogdanm 89:552587b429a1 97 contains an argument, it must be loaded into this register
bogdanm 89:552587b429a1 98 before writing the command to the command register. */
bogdanm 89:552587b429a1 99
bogdanm 89:552587b429a1 100 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
bogdanm 89:552587b429a1 101 Max_Data = 64 */
bogdanm 89:552587b429a1 102
bogdanm 89:552587b429a1 103 uint32_t Response; /*!< Specifies the SDIO response type.
bogdanm 89:552587b429a1 104 This parameter can be a value of @ref SDIO_Response_Type */
bogdanm 89:552587b429a1 105
bogdanm 89:552587b429a1 106 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
bogdanm 89:552587b429a1 107 enabled or disabled.
bogdanm 89:552587b429a1 108 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
bogdanm 89:552587b429a1 109
bogdanm 89:552587b429a1 110 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
bogdanm 89:552587b429a1 111 is enabled or disabled.
bogdanm 89:552587b429a1 112 This parameter can be a value of @ref SDIO_CPSM_State */
bogdanm 89:552587b429a1 113 }SDIO_CmdInitTypeDef;
bogdanm 89:552587b429a1 114
bogdanm 89:552587b429a1 115
bogdanm 89:552587b429a1 116 /**
bogdanm 89:552587b429a1 117 * @brief SDIO Data Control structure
bogdanm 89:552587b429a1 118 */
bogdanm 89:552587b429a1 119 typedef struct
bogdanm 89:552587b429a1 120 {
bogdanm 89:552587b429a1 121 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
bogdanm 89:552587b429a1 122
bogdanm 89:552587b429a1 123 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
bogdanm 89:552587b429a1 124
bogdanm 89:552587b429a1 125 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
bogdanm 89:552587b429a1 126 This parameter can be a value of @ref SDIO_Data_Block_Size */
bogdanm 89:552587b429a1 127
bogdanm 89:552587b429a1 128 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
bogdanm 89:552587b429a1 129 is a read or write.
bogdanm 89:552587b429a1 130 This parameter can be a value of @ref SDIO_Transfer_Direction */
bogdanm 89:552587b429a1 131
bogdanm 89:552587b429a1 132 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
bogdanm 89:552587b429a1 133 This parameter can be a value of @ref SDIO_Transfer_Type */
bogdanm 89:552587b429a1 134
bogdanm 89:552587b429a1 135 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
bogdanm 89:552587b429a1 136 is enabled or disabled.
bogdanm 89:552587b429a1 137 This parameter can be a value of @ref SDIO_DPSM_State */
bogdanm 89:552587b429a1 138 }SDIO_DataInitTypeDef;
bogdanm 89:552587b429a1 139
bogdanm 92:4fc01daae5a5 140 /**
bogdanm 92:4fc01daae5a5 141 * @}
bogdanm 92:4fc01daae5a5 142 */
bogdanm 92:4fc01daae5a5 143
bogdanm 89:552587b429a1 144 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 145 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
bogdanm 89:552587b429a1 146 * @{
bogdanm 89:552587b429a1 147 */
bogdanm 89:552587b429a1 148
Kojto 99:dbbf35b96557 149 /** @defgroup SDIO_Clock_Edge Clock Edge
bogdanm 89:552587b429a1 150 * @{
bogdanm 89:552587b429a1 151 */
bogdanm 89:552587b429a1 152 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 153 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
bogdanm 89:552587b429a1 154
bogdanm 89:552587b429a1 155 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
bogdanm 89:552587b429a1 156 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
bogdanm 89:552587b429a1 157 /**
bogdanm 89:552587b429a1 158 * @}
bogdanm 89:552587b429a1 159 */
bogdanm 89:552587b429a1 160
Kojto 99:dbbf35b96557 161 /** @defgroup SDIO_Clock_Bypass Clock Bypass
bogdanm 89:552587b429a1 162 * @{
bogdanm 89:552587b429a1 163 */
bogdanm 89:552587b429a1 164 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 165 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
bogdanm 89:552587b429a1 166
bogdanm 89:552587b429a1 167 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
bogdanm 89:552587b429a1 168 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
bogdanm 89:552587b429a1 169 /**
bogdanm 89:552587b429a1 170 * @}
bogdanm 89:552587b429a1 171 */
bogdanm 89:552587b429a1 172
Kojto 99:dbbf35b96557 173 /** @defgroup SDIO_Clock_Power_Save Clock Power Saving
bogdanm 89:552587b429a1 174 * @{
bogdanm 89:552587b429a1 175 */
bogdanm 89:552587b429a1 176 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 177 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
bogdanm 89:552587b429a1 178
bogdanm 89:552587b429a1 179 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
bogdanm 89:552587b429a1 180 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
bogdanm 89:552587b429a1 181 /**
bogdanm 89:552587b429a1 182 * @}
bogdanm 89:552587b429a1 183 */
bogdanm 89:552587b429a1 184
Kojto 99:dbbf35b96557 185 /** @defgroup SDIO_Bus_Wide Bus Width
bogdanm 89:552587b429a1 186 * @{
bogdanm 89:552587b429a1 187 */
bogdanm 89:552587b429a1 188 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 189 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
bogdanm 92:4fc01daae5a5 190 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
bogdanm 89:552587b429a1 191
bogdanm 89:552587b429a1 192 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
bogdanm 89:552587b429a1 193 ((WIDE) == SDIO_BUS_WIDE_4B) || \
bogdanm 89:552587b429a1 194 ((WIDE) == SDIO_BUS_WIDE_8B))
bogdanm 89:552587b429a1 195 /**
bogdanm 89:552587b429a1 196 * @}
bogdanm 89:552587b429a1 197 */
bogdanm 89:552587b429a1 198
Kojto 99:dbbf35b96557 199 /** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
bogdanm 89:552587b429a1 200 * @{
bogdanm 89:552587b429a1 201 */
bogdanm 89:552587b429a1 202 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 203 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
bogdanm 89:552587b429a1 204
bogdanm 89:552587b429a1 205 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
bogdanm 89:552587b429a1 206 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
bogdanm 89:552587b429a1 207 /**
bogdanm 89:552587b429a1 208 * @}
bogdanm 89:552587b429a1 209 */
bogdanm 89:552587b429a1 210
Kojto 99:dbbf35b96557 211 /** @defgroup SDIO_Clock_Division Clock Division
bogdanm 89:552587b429a1 212 * @{
bogdanm 89:552587b429a1 213 */
bogdanm 89:552587b429a1 214 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
bogdanm 89:552587b429a1 215 /**
bogdanm 89:552587b429a1 216 * @}
bogdanm 89:552587b429a1 217 */
bogdanm 89:552587b429a1 218
Kojto 99:dbbf35b96557 219 /** @defgroup SDIO_Command_Index Command Index
bogdanm 89:552587b429a1 220 * @{
bogdanm 89:552587b429a1 221 */
bogdanm 89:552587b429a1 222 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
bogdanm 89:552587b429a1 223 /**
bogdanm 89:552587b429a1 224 * @}
bogdanm 89:552587b429a1 225 */
bogdanm 89:552587b429a1 226
Kojto 99:dbbf35b96557 227 /** @defgroup SDIO_Response_Type Response Type
bogdanm 89:552587b429a1 228 * @{
bogdanm 89:552587b429a1 229 */
bogdanm 89:552587b429a1 230 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 231 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
bogdanm 92:4fc01daae5a5 232 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
bogdanm 89:552587b429a1 233
bogdanm 89:552587b429a1 234 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
bogdanm 89:552587b429a1 235 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
bogdanm 89:552587b429a1 236 ((RESPONSE) == SDIO_RESPONSE_LONG))
bogdanm 89:552587b429a1 237 /**
bogdanm 89:552587b429a1 238 * @}
bogdanm 89:552587b429a1 239 */
bogdanm 89:552587b429a1 240
Kojto 99:dbbf35b96557 241 /** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
bogdanm 89:552587b429a1 242 * @{
bogdanm 89:552587b429a1 243 */
bogdanm 89:552587b429a1 244 #define SDIO_WAIT_NO ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 245 #define SDIO_WAIT_IT SDIO_CMD_WAITINT
bogdanm 92:4fc01daae5a5 246 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
bogdanm 89:552587b429a1 247
bogdanm 89:552587b429a1 248 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
bogdanm 89:552587b429a1 249 ((WAIT) == SDIO_WAIT_IT) || \
bogdanm 89:552587b429a1 250 ((WAIT) == SDIO_WAIT_PEND))
bogdanm 89:552587b429a1 251 /**
bogdanm 89:552587b429a1 252 * @}
bogdanm 89:552587b429a1 253 */
bogdanm 89:552587b429a1 254
Kojto 99:dbbf35b96557 255 /** @defgroup SDIO_CPSM_State CPSM State
bogdanm 89:552587b429a1 256 * @{
bogdanm 89:552587b429a1 257 */
bogdanm 89:552587b429a1 258 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 259 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
bogdanm 89:552587b429a1 260
bogdanm 89:552587b429a1 261 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
bogdanm 89:552587b429a1 262 ((CPSM) == SDIO_CPSM_ENABLE))
bogdanm 89:552587b429a1 263 /**
bogdanm 89:552587b429a1 264 * @}
bogdanm 89:552587b429a1 265 */
bogdanm 89:552587b429a1 266
Kojto 99:dbbf35b96557 267 /** @defgroup SDIO_Response_Registers Response Register
bogdanm 89:552587b429a1 268 * @{
bogdanm 89:552587b429a1 269 */
bogdanm 89:552587b429a1 270 #define SDIO_RESP1 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 271 #define SDIO_RESP2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 272 #define SDIO_RESP3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 273 #define SDIO_RESP4 ((uint32_t)0x0000000C)
bogdanm 89:552587b429a1 274
bogdanm 89:552587b429a1 275 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
bogdanm 89:552587b429a1 276 ((RESP) == SDIO_RESP2) || \
bogdanm 89:552587b429a1 277 ((RESP) == SDIO_RESP3) || \
bogdanm 89:552587b429a1 278 ((RESP) == SDIO_RESP4))
bogdanm 89:552587b429a1 279 /**
bogdanm 89:552587b429a1 280 * @}
bogdanm 89:552587b429a1 281 */
bogdanm 89:552587b429a1 282
Kojto 99:dbbf35b96557 283 /** @defgroup SDIO_Data_Length Data Lenght
bogdanm 89:552587b429a1 284 * @{
bogdanm 89:552587b429a1 285 */
bogdanm 89:552587b429a1 286 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
bogdanm 89:552587b429a1 287 /**
bogdanm 89:552587b429a1 288 * @}
bogdanm 89:552587b429a1 289 */
bogdanm 89:552587b429a1 290
Kojto 99:dbbf35b96557 291 /** @defgroup SDIO_Data_Block_Size Data Block Size
bogdanm 89:552587b429a1 292 * @{
bogdanm 89:552587b429a1 293 */
bogdanm 89:552587b429a1 294 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 295 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
bogdanm 92:4fc01daae5a5 296 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
bogdanm 89:552587b429a1 297 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
bogdanm 92:4fc01daae5a5 298 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
bogdanm 89:552587b429a1 299 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
bogdanm 89:552587b429a1 300 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
bogdanm 89:552587b429a1 301 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
bogdanm 92:4fc01daae5a5 302 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
bogdanm 89:552587b429a1 303 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
bogdanm 89:552587b429a1 304 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
bogdanm 89:552587b429a1 305 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
bogdanm 89:552587b429a1 306 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
bogdanm 89:552587b429a1 307 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
bogdanm 89:552587b429a1 308 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
bogdanm 89:552587b429a1 309
bogdanm 89:552587b429a1 310 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
bogdanm 89:552587b429a1 311 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
bogdanm 89:552587b429a1 312 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
bogdanm 89:552587b429a1 313 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
bogdanm 89:552587b429a1 314 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
bogdanm 89:552587b429a1 315 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
bogdanm 89:552587b429a1 316 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
bogdanm 89:552587b429a1 317 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
bogdanm 89:552587b429a1 318 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
bogdanm 89:552587b429a1 319 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
bogdanm 89:552587b429a1 320 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
bogdanm 89:552587b429a1 321 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
bogdanm 89:552587b429a1 322 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
bogdanm 89:552587b429a1 323 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
bogdanm 89:552587b429a1 324 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
bogdanm 89:552587b429a1 325 /**
bogdanm 89:552587b429a1 326 * @}
bogdanm 89:552587b429a1 327 */
bogdanm 89:552587b429a1 328
Kojto 99:dbbf35b96557 329 /** @defgroup SDIO_Transfer_Direction Transfer Direction
bogdanm 89:552587b429a1 330 * @{
bogdanm 89:552587b429a1 331 */
bogdanm 89:552587b429a1 332 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 333 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
bogdanm 89:552587b429a1 334
bogdanm 89:552587b429a1 335 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
bogdanm 89:552587b429a1 336 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
bogdanm 89:552587b429a1 337 /**
bogdanm 89:552587b429a1 338 * @}
bogdanm 89:552587b429a1 339 */
bogdanm 89:552587b429a1 340
Kojto 99:dbbf35b96557 341 /** @defgroup SDIO_Transfer_Type Transfer Type
bogdanm 89:552587b429a1 342 * @{
bogdanm 89:552587b429a1 343 */
bogdanm 89:552587b429a1 344 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 345 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
bogdanm 89:552587b429a1 346
bogdanm 89:552587b429a1 347 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
bogdanm 89:552587b429a1 348 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
bogdanm 89:552587b429a1 349 /**
bogdanm 89:552587b429a1 350 * @}
bogdanm 89:552587b429a1 351 */
bogdanm 89:552587b429a1 352
Kojto 99:dbbf35b96557 353 /** @defgroup SDIO_DPSM_State DPSM State
bogdanm 89:552587b429a1 354 * @{
bogdanm 89:552587b429a1 355 */
bogdanm 89:552587b429a1 356 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 357 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
bogdanm 89:552587b429a1 358
bogdanm 89:552587b429a1 359 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
bogdanm 89:552587b429a1 360 ((DPSM) == SDIO_DPSM_ENABLE))
bogdanm 89:552587b429a1 361 /**
bogdanm 89:552587b429a1 362 * @}
bogdanm 89:552587b429a1 363 */
bogdanm 89:552587b429a1 364
Kojto 99:dbbf35b96557 365 /** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
bogdanm 89:552587b429a1 366 * @{
bogdanm 89:552587b429a1 367 */
Kojto 99:dbbf35b96557 368 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 369 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 370
bogdanm 89:552587b429a1 371 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
bogdanm 89:552587b429a1 372 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
bogdanm 89:552587b429a1 373 /**
bogdanm 89:552587b429a1 374 * @}
bogdanm 89:552587b429a1 375 */
bogdanm 89:552587b429a1 376
Kojto 99:dbbf35b96557 377 /** @defgroup SDIO_Interrupt_sources Interrupt Sources
bogdanm 89:552587b429a1 378 * @{
bogdanm 89:552587b429a1 379 */
bogdanm 92:4fc01daae5a5 380 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
bogdanm 92:4fc01daae5a5 381 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
bogdanm 92:4fc01daae5a5 382 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
bogdanm 92:4fc01daae5a5 383 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
bogdanm 92:4fc01daae5a5 384 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
bogdanm 92:4fc01daae5a5 385 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
bogdanm 92:4fc01daae5a5 386 #define SDIO_IT_CMDREND SDIO_STA_CMDREND
bogdanm 92:4fc01daae5a5 387 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
bogdanm 92:4fc01daae5a5 388 #define SDIO_IT_DATAEND SDIO_STA_DATAEND
bogdanm 92:4fc01daae5a5 389 #define SDIO_IT_STBITERR SDIO_STA_STBITERR
bogdanm 92:4fc01daae5a5 390 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
bogdanm 92:4fc01daae5a5 391 #define SDIO_IT_CMDACT SDIO_STA_CMDACT
bogdanm 92:4fc01daae5a5 392 #define SDIO_IT_TXACT SDIO_STA_TXACT
bogdanm 92:4fc01daae5a5 393 #define SDIO_IT_RXACT SDIO_STA_RXACT
bogdanm 92:4fc01daae5a5 394 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
bogdanm 92:4fc01daae5a5 395 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
bogdanm 92:4fc01daae5a5 396 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
bogdanm 92:4fc01daae5a5 397 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
bogdanm 92:4fc01daae5a5 398 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
bogdanm 92:4fc01daae5a5 399 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
bogdanm 92:4fc01daae5a5 400 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
bogdanm 92:4fc01daae5a5 401 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
bogdanm 92:4fc01daae5a5 402 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
bogdanm 92:4fc01daae5a5 403 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
bogdanm 89:552587b429a1 404 /**
bogdanm 89:552587b429a1 405 * @}
bogdanm 89:552587b429a1 406 */
bogdanm 89:552587b429a1 407
Kojto 99:dbbf35b96557 408 /** @defgroup SDIO_Flags Flags
bogdanm 89:552587b429a1 409 * @{
bogdanm 89:552587b429a1 410 */
bogdanm 92:4fc01daae5a5 411 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
bogdanm 92:4fc01daae5a5 412 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
bogdanm 92:4fc01daae5a5 413 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
bogdanm 92:4fc01daae5a5 414 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
bogdanm 92:4fc01daae5a5 415 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
bogdanm 92:4fc01daae5a5 416 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
bogdanm 92:4fc01daae5a5 417 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
bogdanm 92:4fc01daae5a5 418 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
bogdanm 92:4fc01daae5a5 419 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
bogdanm 92:4fc01daae5a5 420 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
bogdanm 92:4fc01daae5a5 421 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
bogdanm 92:4fc01daae5a5 422 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
bogdanm 92:4fc01daae5a5 423 #define SDIO_FLAG_TXACT SDIO_STA_TXACT
bogdanm 92:4fc01daae5a5 424 #define SDIO_FLAG_RXACT SDIO_STA_RXACT
bogdanm 92:4fc01daae5a5 425 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
bogdanm 92:4fc01daae5a5 426 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
bogdanm 92:4fc01daae5a5 427 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
bogdanm 92:4fc01daae5a5 428 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
bogdanm 92:4fc01daae5a5 429 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
bogdanm 92:4fc01daae5a5 430 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
bogdanm 92:4fc01daae5a5 431 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
bogdanm 92:4fc01daae5a5 432 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
bogdanm 92:4fc01daae5a5 433 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
bogdanm 92:4fc01daae5a5 434 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
Kojto 99:dbbf35b96557 435 /**
Kojto 99:dbbf35b96557 436 * @}
Kojto 99:dbbf35b96557 437 */
bogdanm 89:552587b429a1 438
bogdanm 89:552587b429a1 439 /**
bogdanm 89:552587b429a1 440 * @}
bogdanm 89:552587b429a1 441 */
Kojto 99:dbbf35b96557 442 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 443 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
bogdanm 89:552587b429a1 444 * @{
Kojto 99:dbbf35b96557 445 */
bogdanm 89:552587b429a1 446
Kojto 99:dbbf35b96557 447 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
Kojto 99:dbbf35b96557 448 * @{
bogdanm 89:552587b429a1 449 */
bogdanm 89:552587b429a1 450 /* ------------ SDIO registers bit address in the alias region -------------- */
bogdanm 89:552587b429a1 451 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
bogdanm 89:552587b429a1 452
bogdanm 89:552587b429a1 453 /* --- CLKCR Register ---*/
bogdanm 89:552587b429a1 454 /* Alias word address of CLKEN bit */
bogdanm 89:552587b429a1 455 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
Kojto 99:dbbf35b96557 456 #define CLKEN_BITNUMBER 0x08
Kojto 99:dbbf35b96557 457 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
bogdanm 89:552587b429a1 458
bogdanm 89:552587b429a1 459 /* --- CMD Register ---*/
bogdanm 89:552587b429a1 460 /* Alias word address of SDIOSUSPEND bit */
bogdanm 89:552587b429a1 461 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
Kojto 99:dbbf35b96557 462 #define SDIOSUSPEND_BITNUMBER 0x0B
Kojto 99:dbbf35b96557 463 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
bogdanm 89:552587b429a1 464
bogdanm 89:552587b429a1 465 /* Alias word address of ENCMDCOMPL bit */
Kojto 99:dbbf35b96557 466 #define ENCMDCOMPL_BITNUMBER 0x0C
Kojto 99:dbbf35b96557 467 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
bogdanm 89:552587b429a1 468
bogdanm 89:552587b429a1 469 /* Alias word address of NIEN bit */
Kojto 99:dbbf35b96557 470 #define NIEN_BITNUMBER 0x0D
Kojto 99:dbbf35b96557 471 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
bogdanm 89:552587b429a1 472
bogdanm 89:552587b429a1 473 /* Alias word address of ATACMD bit */
Kojto 99:dbbf35b96557 474 #define ATACMD_BITNUMBER 0x0E
Kojto 99:dbbf35b96557 475 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
bogdanm 89:552587b429a1 476
bogdanm 89:552587b429a1 477 /* --- DCTRL Register ---*/
bogdanm 89:552587b429a1 478 /* Alias word address of DMAEN bit */
bogdanm 89:552587b429a1 479 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
Kojto 99:dbbf35b96557 480 #define DMAEN_BITNUMBER 0x03
Kojto 99:dbbf35b96557 481 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
bogdanm 89:552587b429a1 482
bogdanm 89:552587b429a1 483 /* Alias word address of RWSTART bit */
Kojto 99:dbbf35b96557 484 #define RWSTART_BITNUMBER 0x08
Kojto 99:dbbf35b96557 485 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
bogdanm 89:552587b429a1 486
bogdanm 89:552587b429a1 487 /* Alias word address of RWSTOP bit */
Kojto 99:dbbf35b96557 488 #define RWSTOP_BITNUMBER 0x09
Kojto 99:dbbf35b96557 489 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
bogdanm 89:552587b429a1 490
bogdanm 89:552587b429a1 491 /* Alias word address of RWMOD bit */
Kojto 99:dbbf35b96557 492 #define RWMOD_BITNUMBER 0x0A
Kojto 99:dbbf35b96557 493 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
bogdanm 89:552587b429a1 494
bogdanm 89:552587b429a1 495 /* Alias word address of SDIOEN bit */
Kojto 99:dbbf35b96557 496 #define SDIOEN_BITNUMBER 0x0B
Kojto 99:dbbf35b96557 497 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
Kojto 99:dbbf35b96557 498 /**
Kojto 99:dbbf35b96557 499 * @}
Kojto 99:dbbf35b96557 500 */
Kojto 99:dbbf35b96557 501
Kojto 99:dbbf35b96557 502 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
Kojto 99:dbbf35b96557 503 * @brief SDMMC_LL registers bit address in the alias region
Kojto 99:dbbf35b96557 504 * @{
Kojto 99:dbbf35b96557 505 */
bogdanm 89:552587b429a1 506
bogdanm 89:552587b429a1 507 /* ---------------------- SDIO registers bit mask --------------------------- */
bogdanm 89:552587b429a1 508 /* --- CLKCR Register ---*/
bogdanm 92:4fc01daae5a5 509 /* CLKCR register clear mask */
bogdanm 92:4fc01daae5a5 510 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
bogdanm 92:4fc01daae5a5 511 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
bogdanm 92:4fc01daae5a5 512 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
bogdanm 89:552587b429a1 513
bogdanm 89:552587b429a1 514 /* --- PWRCTRL Register ---*/
bogdanm 89:552587b429a1 515 /* --- DCTRL Register ---*/
bogdanm 89:552587b429a1 516 /* SDIO DCTRL Clear Mask */
bogdanm 92:4fc01daae5a5 517 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
bogdanm 92:4fc01daae5a5 518 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
bogdanm 89:552587b429a1 519
bogdanm 89:552587b429a1 520 /* --- CMD Register ---*/
bogdanm 89:552587b429a1 521 /* CMD Register clear mask */
bogdanm 92:4fc01daae5a5 522 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
bogdanm 92:4fc01daae5a5 523 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
bogdanm 92:4fc01daae5a5 524 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
bogdanm 89:552587b429a1 525
bogdanm 89:552587b429a1 526 /* SDIO RESP Registers Address */
bogdanm 89:552587b429a1 527 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
bogdanm 89:552587b429a1 528
Kojto 99:dbbf35b96557 529 /* SDIO Initialization Frequency (400KHz max) */
bogdanm 89:552587b429a1 530 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
bogdanm 89:552587b429a1 531
bogdanm 89:552587b429a1 532 /* SDIO Data Transfer Frequency (25MHz max) */
bogdanm 89:552587b429a1 533 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
Kojto 99:dbbf35b96557 534 /**
Kojto 99:dbbf35b96557 535 * @}
Kojto 99:dbbf35b96557 536 */
bogdanm 89:552587b429a1 537
Kojto 99:dbbf35b96557 538 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
Kojto 99:dbbf35b96557 539 * @brief macros to handle interrupts and specific clock configurations
Kojto 99:dbbf35b96557 540 * @{
Kojto 99:dbbf35b96557 541 */
Kojto 99:dbbf35b96557 542
bogdanm 89:552587b429a1 543 /**
bogdanm 89:552587b429a1 544 * @brief Enable the SDIO device.
bogdanm 89:552587b429a1 545 * @retval None
bogdanm 89:552587b429a1 546 */
bogdanm 89:552587b429a1 547 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
bogdanm 89:552587b429a1 548
bogdanm 89:552587b429a1 549 /**
bogdanm 89:552587b429a1 550 * @brief Disable the SDIO device.
bogdanm 89:552587b429a1 551 * @retval None
bogdanm 89:552587b429a1 552 */
bogdanm 89:552587b429a1 553 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
bogdanm 89:552587b429a1 554
bogdanm 89:552587b429a1 555 /**
bogdanm 89:552587b429a1 556 * @brief Enable the SDIO DMA transfer.
bogdanm 89:552587b429a1 557 * @retval None
bogdanm 89:552587b429a1 558 */
bogdanm 89:552587b429a1 559 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
bogdanm 89:552587b429a1 560
bogdanm 89:552587b429a1 561 /**
bogdanm 89:552587b429a1 562 * @brief Disable the SDIO DMA transfer.
bogdanm 89:552587b429a1 563 * @retval None
bogdanm 89:552587b429a1 564 */
bogdanm 89:552587b429a1 565 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
bogdanm 89:552587b429a1 566
bogdanm 89:552587b429a1 567 /**
bogdanm 89:552587b429a1 568 * @brief Enable the SDIO device interrupt.
bogdanm 89:552587b429a1 569 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 570 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
bogdanm 89:552587b429a1 571 * This parameter can be one or a combination of the following values:
bogdanm 89:552587b429a1 572 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 89:552587b429a1 573 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 89:552587b429a1 574 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 89:552587b429a1 575 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 89:552587b429a1 576 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 89:552587b429a1 577 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 89:552587b429a1 578 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 89:552587b429a1 579 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 89:552587b429a1 580 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm 89:552587b429a1 581 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 89:552587b429a1 582 * bus mode interrupt
bogdanm 89:552587b429a1 583 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm 89:552587b429a1 584 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm 89:552587b429a1 585 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm 89:552587b429a1 586 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm 89:552587b429a1 587 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm 89:552587b429a1 588 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm 89:552587b429a1 589 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm 89:552587b429a1 590 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm 89:552587b429a1 591 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm 89:552587b429a1 592 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm 89:552587b429a1 593 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm 89:552587b429a1 594 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm 89:552587b429a1 595 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 89:552587b429a1 596 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm 89:552587b429a1 597 * @retval None
bogdanm 89:552587b429a1 598 */
bogdanm 89:552587b429a1 599 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
bogdanm 89:552587b429a1 600
bogdanm 89:552587b429a1 601 /**
bogdanm 89:552587b429a1 602 * @brief Disable the SDIO device interrupt.
bogdanm 89:552587b429a1 603 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 604 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
bogdanm 89:552587b429a1 605 * This parameter can be one or a combination of the following values:
bogdanm 89:552587b429a1 606 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 89:552587b429a1 607 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 89:552587b429a1 608 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 89:552587b429a1 609 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 89:552587b429a1 610 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 89:552587b429a1 611 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 89:552587b429a1 612 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 89:552587b429a1 613 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 89:552587b429a1 614 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm 89:552587b429a1 615 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 89:552587b429a1 616 * bus mode interrupt
bogdanm 89:552587b429a1 617 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm 89:552587b429a1 618 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm 89:552587b429a1 619 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm 89:552587b429a1 620 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm 89:552587b429a1 621 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm 89:552587b429a1 622 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm 89:552587b429a1 623 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm 89:552587b429a1 624 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm 89:552587b429a1 625 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm 89:552587b429a1 626 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm 89:552587b429a1 627 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm 89:552587b429a1 628 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm 89:552587b429a1 629 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 89:552587b429a1 630 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm 89:552587b429a1 631 * @retval None
bogdanm 89:552587b429a1 632 */
bogdanm 89:552587b429a1 633 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
bogdanm 89:552587b429a1 634
bogdanm 89:552587b429a1 635 /**
bogdanm 89:552587b429a1 636 * @brief Checks whether the specified SDIO flag is set or not.
bogdanm 89:552587b429a1 637 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 638 * @param __FLAG__: specifies the flag to check.
bogdanm 89:552587b429a1 639 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 640 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
bogdanm 89:552587b429a1 641 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
bogdanm 89:552587b429a1 642 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
bogdanm 89:552587b429a1 643 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
bogdanm 89:552587b429a1 644 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
bogdanm 89:552587b429a1 645 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
bogdanm 89:552587b429a1 646 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
bogdanm 89:552587b429a1 647 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
bogdanm 89:552587b429a1 648 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
bogdanm 89:552587b429a1 649 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
bogdanm 89:552587b429a1 650 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
bogdanm 89:552587b429a1 651 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
bogdanm 89:552587b429a1 652 * @arg SDIO_FLAG_TXACT: Data transmit in progress
bogdanm 89:552587b429a1 653 * @arg SDIO_FLAG_RXACT: Data receive in progress
bogdanm 89:552587b429a1 654 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
bogdanm 89:552587b429a1 655 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
bogdanm 89:552587b429a1 656 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
bogdanm 89:552587b429a1 657 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
bogdanm 89:552587b429a1 658 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
bogdanm 89:552587b429a1 659 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
bogdanm 89:552587b429a1 660 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
bogdanm 89:552587b429a1 661 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
bogdanm 89:552587b429a1 662 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
bogdanm 89:552587b429a1 663 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm 89:552587b429a1 664 * @retval The new state of SDIO_FLAG (SET or RESET).
bogdanm 89:552587b429a1 665 */
bogdanm 89:552587b429a1 666 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
bogdanm 89:552587b429a1 667
bogdanm 89:552587b429a1 668
bogdanm 89:552587b429a1 669 /**
bogdanm 92:4fc01daae5a5 670 * @brief Clears the SDIO pending flags.
bogdanm 89:552587b429a1 671 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 672 * @param __FLAG__: specifies the flag to clear.
bogdanm 89:552587b429a1 673 * This parameter can be one or a combination of the following values:
bogdanm 89:552587b429a1 674 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
bogdanm 89:552587b429a1 675 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
bogdanm 89:552587b429a1 676 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
bogdanm 89:552587b429a1 677 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
bogdanm 89:552587b429a1 678 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
bogdanm 89:552587b429a1 679 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
bogdanm 89:552587b429a1 680 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
bogdanm 89:552587b429a1 681 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
bogdanm 89:552587b429a1 682 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
bogdanm 89:552587b429a1 683 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
bogdanm 89:552587b429a1 684 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
bogdanm 89:552587b429a1 685 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
bogdanm 89:552587b429a1 686 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm 89:552587b429a1 687 * @retval None
bogdanm 89:552587b429a1 688 */
bogdanm 89:552587b429a1 689 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
bogdanm 89:552587b429a1 690
bogdanm 89:552587b429a1 691 /**
bogdanm 89:552587b429a1 692 * @brief Checks whether the specified SDIO interrupt has occurred or not.
bogdanm 89:552587b429a1 693 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 694 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
bogdanm 89:552587b429a1 695 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 696 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 89:552587b429a1 697 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 89:552587b429a1 698 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 89:552587b429a1 699 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 89:552587b429a1 700 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 89:552587b429a1 701 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 89:552587b429a1 702 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 89:552587b429a1 703 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 89:552587b429a1 704 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm 89:552587b429a1 705 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 89:552587b429a1 706 * bus mode interrupt
bogdanm 89:552587b429a1 707 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm 89:552587b429a1 708 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm 89:552587b429a1 709 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm 89:552587b429a1 710 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm 89:552587b429a1 711 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm 89:552587b429a1 712 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm 89:552587b429a1 713 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm 89:552587b429a1 714 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm 89:552587b429a1 715 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm 89:552587b429a1 716 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm 89:552587b429a1 717 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm 89:552587b429a1 718 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm 89:552587b429a1 719 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 89:552587b429a1 720 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm 89:552587b429a1 721 * @retval The new state of SDIO_IT (SET or RESET).
bogdanm 89:552587b429a1 722 */
bogdanm 89:552587b429a1 723 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 89:552587b429a1 724
bogdanm 89:552587b429a1 725 /**
bogdanm 89:552587b429a1 726 * @brief Clears the SDIO's interrupt pending bits.
bogdanm 89:552587b429a1 727 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 728 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 89:552587b429a1 729 * This parameter can be one or a combination of the following values:
bogdanm 89:552587b429a1 730 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 89:552587b429a1 731 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 89:552587b429a1 732 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 89:552587b429a1 733 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 89:552587b429a1 734 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 89:552587b429a1 735 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 89:552587b429a1 736 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 89:552587b429a1 737 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 89:552587b429a1 738 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
bogdanm 89:552587b429a1 739 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 89:552587b429a1 740 * bus mode interrupt
bogdanm 89:552587b429a1 741 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 89:552587b429a1 742 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm 89:552587b429a1 743 * @retval None
bogdanm 89:552587b429a1 744 */
bogdanm 89:552587b429a1 745 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
bogdanm 89:552587b429a1 746
bogdanm 89:552587b429a1 747 /**
bogdanm 89:552587b429a1 748 * @brief Enable Start the SD I/O Read Wait operation.
bogdanm 89:552587b429a1 749 * @retval None
bogdanm 89:552587b429a1 750 */
bogdanm 89:552587b429a1 751 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
bogdanm 89:552587b429a1 752
bogdanm 89:552587b429a1 753 /**
bogdanm 89:552587b429a1 754 * @brief Disable Start the SD I/O Read Wait operations.
bogdanm 89:552587b429a1 755 * @retval None
bogdanm 89:552587b429a1 756 */
bogdanm 89:552587b429a1 757 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
bogdanm 89:552587b429a1 758
bogdanm 89:552587b429a1 759 /**
bogdanm 89:552587b429a1 760 * @brief Enable Start the SD I/O Read Wait operation.
bogdanm 89:552587b429a1 761 * @retval None
bogdanm 89:552587b429a1 762 */
bogdanm 89:552587b429a1 763 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
bogdanm 89:552587b429a1 764
bogdanm 89:552587b429a1 765 /**
bogdanm 89:552587b429a1 766 * @brief Disable Stop the SD I/O Read Wait operations.
bogdanm 89:552587b429a1 767 * @retval None
bogdanm 89:552587b429a1 768 */
bogdanm 89:552587b429a1 769 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
bogdanm 89:552587b429a1 770
bogdanm 89:552587b429a1 771 /**
bogdanm 89:552587b429a1 772 * @brief Enable the SD I/O Mode Operation.
bogdanm 89:552587b429a1 773 * @retval None
bogdanm 89:552587b429a1 774 */
bogdanm 89:552587b429a1 775 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
bogdanm 89:552587b429a1 776
bogdanm 89:552587b429a1 777 /**
bogdanm 89:552587b429a1 778 * @brief Disable the SD I/O Mode Operation.
bogdanm 89:552587b429a1 779 * @retval None
bogdanm 89:552587b429a1 780 */
bogdanm 89:552587b429a1 781 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
bogdanm 89:552587b429a1 782
bogdanm 89:552587b429a1 783 /**
bogdanm 89:552587b429a1 784 * @brief Enable the SD I/O Suspend command sending.
bogdanm 89:552587b429a1 785 * @retval None
bogdanm 89:552587b429a1 786 */
bogdanm 89:552587b429a1 787 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
bogdanm 89:552587b429a1 788
bogdanm 89:552587b429a1 789 /**
bogdanm 89:552587b429a1 790 * @brief Disable the SD I/O Suspend command sending.
bogdanm 89:552587b429a1 791 * @retval None
bogdanm 89:552587b429a1 792 */
bogdanm 89:552587b429a1 793 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
Kojto 99:dbbf35b96557 794
Kojto 99:dbbf35b96557 795 #if !defined(STM32F446xx)
bogdanm 89:552587b429a1 796 /**
bogdanm 89:552587b429a1 797 * @brief Enable the command completion signal.
bogdanm 89:552587b429a1 798 * @retval None
bogdanm 89:552587b429a1 799 */
bogdanm 89:552587b429a1 800 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
bogdanm 89:552587b429a1 801
bogdanm 89:552587b429a1 802 /**
bogdanm 89:552587b429a1 803 * @brief Disable the command completion signal.
bogdanm 89:552587b429a1 804 * @retval None
bogdanm 89:552587b429a1 805 */
bogdanm 89:552587b429a1 806 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
bogdanm 89:552587b429a1 807
bogdanm 89:552587b429a1 808 /**
bogdanm 89:552587b429a1 809 * @brief Enable the CE-ATA interrupt.
bogdanm 89:552587b429a1 810 * @retval None
bogdanm 89:552587b429a1 811 */
bogdanm 89:552587b429a1 812 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
bogdanm 89:552587b429a1 813
bogdanm 89:552587b429a1 814 /**
bogdanm 89:552587b429a1 815 * @brief Disable the CE-ATA interrupt.
bogdanm 89:552587b429a1 816 * @retval None
bogdanm 89:552587b429a1 817 */
bogdanm 89:552587b429a1 818 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
bogdanm 89:552587b429a1 819
bogdanm 89:552587b429a1 820 /**
bogdanm 89:552587b429a1 821 * @brief Enable send CE-ATA command (CMD61).
bogdanm 89:552587b429a1 822 * @retval None
bogdanm 89:552587b429a1 823 */
bogdanm 89:552587b429a1 824 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
bogdanm 89:552587b429a1 825
bogdanm 89:552587b429a1 826 /**
bogdanm 89:552587b429a1 827 * @brief Disable send CE-ATA command (CMD61).
bogdanm 89:552587b429a1 828 * @retval None
bogdanm 89:552587b429a1 829 */
bogdanm 89:552587b429a1 830 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
Kojto 99:dbbf35b96557 831 #endif /* !defined(STM32F446xx) */
bogdanm 89:552587b429a1 832 /**
bogdanm 89:552587b429a1 833 * @}
bogdanm 89:552587b429a1 834 */
bogdanm 89:552587b429a1 835
bogdanm 92:4fc01daae5a5 836 /**
bogdanm 92:4fc01daae5a5 837 * @}
bogdanm 92:4fc01daae5a5 838 */
bogdanm 92:4fc01daae5a5 839
bogdanm 89:552587b429a1 840 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 841 /** @addtogroup SDMMC_LL_Exported_Functions
bogdanm 92:4fc01daae5a5 842 * @{
bogdanm 92:4fc01daae5a5 843 */
bogdanm 92:4fc01daae5a5 844
bogdanm 89:552587b429a1 845 /* Initialization/de-initialization functions **********************************/
Kojto 99:dbbf35b96557 846 /** @addtogroup HAL_SDMMC_LL_Group1
bogdanm 92:4fc01daae5a5 847 * @{
bogdanm 92:4fc01daae5a5 848 */
bogdanm 89:552587b429a1 849 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
bogdanm 92:4fc01daae5a5 850 /**
bogdanm 92:4fc01daae5a5 851 * @}
bogdanm 92:4fc01daae5a5 852 */
bogdanm 92:4fc01daae5a5 853
bogdanm 89:552587b429a1 854 /* I/O operation functions *****************************************************/
Kojto 99:dbbf35b96557 855 /** @addtogroup HAL_SDMMC_LL_Group2
bogdanm 92:4fc01daae5a5 856 * @{
bogdanm 92:4fc01daae5a5 857 */
bogdanm 89:552587b429a1 858 /* Blocking mode: Polling */
bogdanm 89:552587b429a1 859 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 860 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
bogdanm 92:4fc01daae5a5 861 /**
bogdanm 92:4fc01daae5a5 862 * @}
bogdanm 92:4fc01daae5a5 863 */
bogdanm 92:4fc01daae5a5 864
bogdanm 89:552587b429a1 865 /* Peripheral Control functions ************************************************/
Kojto 99:dbbf35b96557 866 /** @addtogroup HAL_SDMMC_LL_Group3
bogdanm 92:4fc01daae5a5 867 * @{
bogdanm 92:4fc01daae5a5 868 */
bogdanm 89:552587b429a1 869 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 870 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 871 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 872
bogdanm 89:552587b429a1 873 /* Command path state machine (CPSM) management functions */
bogdanm 89:552587b429a1 874 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
bogdanm 89:552587b429a1 875 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 876 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
bogdanm 89:552587b429a1 877
bogdanm 89:552587b429a1 878 /* Data path state machine (DPSM) management functions */
bogdanm 89:552587b429a1 879 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
bogdanm 89:552587b429a1 880 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 881 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 882
bogdanm 89:552587b429a1 883 /* SDIO IO Cards mode management functions */
bogdanm 89:552587b429a1 884 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
bogdanm 89:552587b429a1 885
bogdanm 92:4fc01daae5a5 886 /**
bogdanm 92:4fc01daae5a5 887 * @}
bogdanm 92:4fc01daae5a5 888 */
bogdanm 92:4fc01daae5a5 889
bogdanm 92:4fc01daae5a5 890 /**
bogdanm 92:4fc01daae5a5 891 * @}
bogdanm 92:4fc01daae5a5 892 */
bogdanm 92:4fc01daae5a5 893
bogdanm 92:4fc01daae5a5 894 /**
bogdanm 92:4fc01daae5a5 895 * @}
bogdanm 92:4fc01daae5a5 896 */
bogdanm 92:4fc01daae5a5 897
bogdanm 92:4fc01daae5a5 898 /**
bogdanm 92:4fc01daae5a5 899 * @}
bogdanm 92:4fc01daae5a5 900 */
bogdanm 92:4fc01daae5a5 901
bogdanm 89:552587b429a1 902 #ifdef __cplusplus
bogdanm 89:552587b429a1 903 }
bogdanm 89:552587b429a1 904 #endif
bogdanm 89:552587b429a1 905
bogdanm 89:552587b429a1 906 #endif /* __STM32F4xx_LL_SDMMC_H */
bogdanm 89:552587b429a1 907
bogdanm 89:552587b429a1 908 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/