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TARGET_MTS_DRAGONFLY_F411RE/stm32f411xe.h@101:7cff1c4259d7, 2015-06-09 (annotated)

Committer:
Kojto
Date:
Tue Jun 09 14:29:26 2015 +0100
Revision:
101:7cff1c4259d7
Child:
106:ba1f97679dad
Release 101 of the mbed library



Changes:

- new platform: APPNEARME_MICRONFCBOARD, MTS_DRAGONFLY_F411RE, MAX32600MBED, WIZwiki_W7500

- Silabs memory optimization in gpio, pwm fixes

- SPI  - ssel documentation fixes and its use

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /**
Kojto 101:7cff1c4259d7 2 ******************************************************************************
Kojto 101:7cff1c4259d7 3 * @file stm32f411xe.h
Kojto 101:7cff1c4259d7 4 * @author MCD Application Team
Kojto 101:7cff1c4259d7 5 * @version V2.3.0
Kojto 101:7cff1c4259d7 6 * @date 02-March-2015
Kojto 101:7cff1c4259d7 7 * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
Kojto 101:7cff1c4259d7 8 *
Kojto 101:7cff1c4259d7 9 * This file contains:
Kojto 101:7cff1c4259d7 10 * - Data structures and the address mapping for all peripherals
Kojto 101:7cff1c4259d7 11 * - Peripheral's registers declarations and bits definition
Kojto 101:7cff1c4259d7 12 * - Macros to access peripheral’s registers hardware
Kojto 101:7cff1c4259d7 13 *
Kojto 101:7cff1c4259d7 14 ******************************************************************************
Kojto 101:7cff1c4259d7 15 * @attention
Kojto 101:7cff1c4259d7 16 *
Kojto 101:7cff1c4259d7 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 101:7cff1c4259d7 18 *
Kojto 101:7cff1c4259d7 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 101:7cff1c4259d7 20 * are permitted provided that the following conditions are met:
Kojto 101:7cff1c4259d7 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 101:7cff1c4259d7 22 * this list of conditions and the following disclaimer.
Kojto 101:7cff1c4259d7 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 101:7cff1c4259d7 24 * this list of conditions and the following disclaimer in the documentation
Kojto 101:7cff1c4259d7 25 * and/or other materials provided with the distribution.
Kojto 101:7cff1c4259d7 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 101:7cff1c4259d7 27 * may be used to endorse or promote products derived from this software
Kojto 101:7cff1c4259d7 28 * without specific prior written permission.
Kojto 101:7cff1c4259d7 29 *
Kojto 101:7cff1c4259d7 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 101:7cff1c4259d7 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 101:7cff1c4259d7 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 101:7cff1c4259d7 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 101:7cff1c4259d7 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 101:7cff1c4259d7 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 101:7cff1c4259d7 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 101:7cff1c4259d7 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 101:7cff1c4259d7 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 101:7cff1c4259d7 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 101:7cff1c4259d7 40 *
Kojto 101:7cff1c4259d7 41 ******************************************************************************
Kojto 101:7cff1c4259d7 42 */
Kojto 101:7cff1c4259d7 43
Kojto 101:7cff1c4259d7 44 /** @addtogroup CMSIS
Kojto 101:7cff1c4259d7 45 * @{
Kojto 101:7cff1c4259d7 46 */
Kojto 101:7cff1c4259d7 47
Kojto 101:7cff1c4259d7 48 /** @addtogroup stm32f401xe
Kojto 101:7cff1c4259d7 49 * @{
Kojto 101:7cff1c4259d7 50 */
Kojto 101:7cff1c4259d7 51
Kojto 101:7cff1c4259d7 52 #ifndef __STM32F401xE_H
Kojto 101:7cff1c4259d7 53 #define __STM32F401xE_H
Kojto 101:7cff1c4259d7 54
Kojto 101:7cff1c4259d7 55 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 56 extern "C" {
Kojto 101:7cff1c4259d7 57 #endif /* __cplusplus */
Kojto 101:7cff1c4259d7 58
Kojto 101:7cff1c4259d7 59
Kojto 101:7cff1c4259d7 60 /** @addtogroup Configuration_section_for_CMSIS
Kojto 101:7cff1c4259d7 61 * @{
Kojto 101:7cff1c4259d7 62 */
Kojto 101:7cff1c4259d7 63
Kojto 101:7cff1c4259d7 64 /**
Kojto 101:7cff1c4259d7 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
Kojto 101:7cff1c4259d7 66 */
Kojto 101:7cff1c4259d7 67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
Kojto 101:7cff1c4259d7 68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
Kojto 101:7cff1c4259d7 69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
Kojto 101:7cff1c4259d7 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 101:7cff1c4259d7 71 #define __FPU_PRESENT 1 /*!< FPU present */
Kojto 101:7cff1c4259d7 72
Kojto 101:7cff1c4259d7 73 /**
Kojto 101:7cff1c4259d7 74 * @}
Kojto 101:7cff1c4259d7 75 */
Kojto 101:7cff1c4259d7 76
Kojto 101:7cff1c4259d7 77 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 101:7cff1c4259d7 78 * @{
Kojto 101:7cff1c4259d7 79 */
Kojto 101:7cff1c4259d7 80
Kojto 101:7cff1c4259d7 81 /**
Kojto 101:7cff1c4259d7 82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
Kojto 101:7cff1c4259d7 83 * in @ref Library_configuration_section
Kojto 101:7cff1c4259d7 84 */
Kojto 101:7cff1c4259d7 85 typedef enum
Kojto 101:7cff1c4259d7 86 {
Kojto 101:7cff1c4259d7 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
Kojto 101:7cff1c4259d7 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 101:7cff1c4259d7 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
Kojto 101:7cff1c4259d7 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
Kojto 101:7cff1c4259d7 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
Kojto 101:7cff1c4259d7 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
Kojto 101:7cff1c4259d7 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
Kojto 101:7cff1c4259d7 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
Kojto 101:7cff1c4259d7 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
Kojto 101:7cff1c4259d7 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
Kojto 101:7cff1c4259d7 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 101:7cff1c4259d7 98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
Kojto 101:7cff1c4259d7 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Kojto 101:7cff1c4259d7 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
Kojto 101:7cff1c4259d7 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
Kojto 101:7cff1c4259d7 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
Kojto 101:7cff1c4259d7 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
Kojto 101:7cff1c4259d7 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
Kojto 101:7cff1c4259d7 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
Kojto 101:7cff1c4259d7 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
Kojto 101:7cff1c4259d7 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
Kojto 101:7cff1c4259d7 108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
Kojto 101:7cff1c4259d7 109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
Kojto 101:7cff1c4259d7 110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
Kojto 101:7cff1c4259d7 111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
Kojto 101:7cff1c4259d7 112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
Kojto 101:7cff1c4259d7 113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
Kojto 101:7cff1c4259d7 114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
Kojto 101:7cff1c4259d7 115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
Kojto 101:7cff1c4259d7 116 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
Kojto 101:7cff1c4259d7 117 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
Kojto 101:7cff1c4259d7 118 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
Kojto 101:7cff1c4259d7 119 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
Kojto 101:7cff1c4259d7 120 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
Kojto 101:7cff1c4259d7 121 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
Kojto 101:7cff1c4259d7 122 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
Kojto 101:7cff1c4259d7 123 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
Kojto 101:7cff1c4259d7 124 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
Kojto 101:7cff1c4259d7 125 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
Kojto 101:7cff1c4259d7 126 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
Kojto 101:7cff1c4259d7 127 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
Kojto 101:7cff1c4259d7 128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
Kojto 101:7cff1c4259d7 129 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
Kojto 101:7cff1c4259d7 130 USART1_IRQn = 37, /*!< USART1 global Interrupt */
Kojto 101:7cff1c4259d7 131 USART2_IRQn = 38, /*!< USART2 global Interrupt */
Kojto 101:7cff1c4259d7 132 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 101:7cff1c4259d7 133 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
Kojto 101:7cff1c4259d7 134 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
Kojto 101:7cff1c4259d7 135 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
Kojto 101:7cff1c4259d7 136 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
Kojto 101:7cff1c4259d7 137 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
Kojto 101:7cff1c4259d7 138 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
Kojto 101:7cff1c4259d7 139 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
Kojto 101:7cff1c4259d7 140 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
Kojto 101:7cff1c4259d7 141 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
Kojto 101:7cff1c4259d7 142 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
Kojto 101:7cff1c4259d7 143 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
Kojto 101:7cff1c4259d7 144 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
Kojto 101:7cff1c4259d7 145 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
Kojto 101:7cff1c4259d7 146 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
Kojto 101:7cff1c4259d7 147 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
Kojto 101:7cff1c4259d7 148 USART6_IRQn = 71, /*!< USART6 global interrupt */
Kojto 101:7cff1c4259d7 149 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
Kojto 101:7cff1c4259d7 150 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
Kojto 101:7cff1c4259d7 151 FPU_IRQn = 81, /*!< FPU global interrupt */
Kojto 101:7cff1c4259d7 152 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
Kojto 101:7cff1c4259d7 153 SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
Kojto 101:7cff1c4259d7 154 } IRQn_Type;
Kojto 101:7cff1c4259d7 155
Kojto 101:7cff1c4259d7 156 /**
Kojto 101:7cff1c4259d7 157 * @}
Kojto 101:7cff1c4259d7 158 */
Kojto 101:7cff1c4259d7 159
Kojto 101:7cff1c4259d7 160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
Kojto 101:7cff1c4259d7 161 #include "system_stm32f4xx.h"
Kojto 101:7cff1c4259d7 162 #include <stdint.h>
Kojto 101:7cff1c4259d7 163
Kojto 101:7cff1c4259d7 164 /** @addtogroup Peripheral_registers_structures
Kojto 101:7cff1c4259d7 165 * @{
Kojto 101:7cff1c4259d7 166 */
Kojto 101:7cff1c4259d7 167
Kojto 101:7cff1c4259d7 168 /**
Kojto 101:7cff1c4259d7 169 * @brief Analog to Digital Converter
Kojto 101:7cff1c4259d7 170 */
Kojto 101:7cff1c4259d7 171
Kojto 101:7cff1c4259d7 172 typedef struct
Kojto 101:7cff1c4259d7 173 {
Kojto 101:7cff1c4259d7 174 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 175 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 176 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 177 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 178 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
Kojto 101:7cff1c4259d7 179 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
Kojto 101:7cff1c4259d7 180 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
Kojto 101:7cff1c4259d7 181 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
Kojto 101:7cff1c4259d7 182 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
Kojto 101:7cff1c4259d7 183 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
Kojto 101:7cff1c4259d7 184 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
Kojto 101:7cff1c4259d7 185 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
Kojto 101:7cff1c4259d7 186 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
Kojto 101:7cff1c4259d7 187 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
Kojto 101:7cff1c4259d7 188 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
Kojto 101:7cff1c4259d7 189 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
Kojto 101:7cff1c4259d7 190 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
Kojto 101:7cff1c4259d7 191 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
Kojto 101:7cff1c4259d7 192 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
Kojto 101:7cff1c4259d7 193 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
Kojto 101:7cff1c4259d7 194 } ADC_TypeDef;
Kojto 101:7cff1c4259d7 195
Kojto 101:7cff1c4259d7 196 typedef struct
Kojto 101:7cff1c4259d7 197 {
Kojto 101:7cff1c4259d7 198 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
Kojto 101:7cff1c4259d7 199 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
Kojto 101:7cff1c4259d7 200 __IO uint32_t CDR; /*!< ADC common regular data register for dual
Kojto 101:7cff1c4259d7 201 AND triple modes, Address offset: ADC1 base address + 0x308 */
Kojto 101:7cff1c4259d7 202 } ADC_Common_TypeDef;
Kojto 101:7cff1c4259d7 203
Kojto 101:7cff1c4259d7 204 /**
Kojto 101:7cff1c4259d7 205 * @brief CRC calculation unit
Kojto 101:7cff1c4259d7 206 */
Kojto 101:7cff1c4259d7 207
Kojto 101:7cff1c4259d7 208 typedef struct
Kojto 101:7cff1c4259d7 209 {
Kojto 101:7cff1c4259d7 210 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 211 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 212 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 101:7cff1c4259d7 213 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 101:7cff1c4259d7 214 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 215 } CRC_TypeDef;
Kojto 101:7cff1c4259d7 216
Kojto 101:7cff1c4259d7 217 /**
Kojto 101:7cff1c4259d7 218 * @brief Debug MCU
Kojto 101:7cff1c4259d7 219 */
Kojto 101:7cff1c4259d7 220
Kojto 101:7cff1c4259d7 221 typedef struct
Kojto 101:7cff1c4259d7 222 {
Kojto 101:7cff1c4259d7 223 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 224 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 225 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 226 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 227 }DBGMCU_TypeDef;
Kojto 101:7cff1c4259d7 228
Kojto 101:7cff1c4259d7 229
Kojto 101:7cff1c4259d7 230 /**
Kojto 101:7cff1c4259d7 231 * @brief DMA Controller
Kojto 101:7cff1c4259d7 232 */
Kojto 101:7cff1c4259d7 233
Kojto 101:7cff1c4259d7 234 typedef struct
Kojto 101:7cff1c4259d7 235 {
Kojto 101:7cff1c4259d7 236 __IO uint32_t CR; /*!< DMA stream x configuration register */
Kojto 101:7cff1c4259d7 237 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
Kojto 101:7cff1c4259d7 238 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
Kojto 101:7cff1c4259d7 239 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
Kojto 101:7cff1c4259d7 240 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
Kojto 101:7cff1c4259d7 241 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
Kojto 101:7cff1c4259d7 242 } DMA_Stream_TypeDef;
Kojto 101:7cff1c4259d7 243
Kojto 101:7cff1c4259d7 244 typedef struct
Kojto 101:7cff1c4259d7 245 {
Kojto 101:7cff1c4259d7 246 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 247 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 248 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 249 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 250 } DMA_TypeDef;
Kojto 101:7cff1c4259d7 251
Kojto 101:7cff1c4259d7 252
Kojto 101:7cff1c4259d7 253 /**
Kojto 101:7cff1c4259d7 254 * @brief External Interrupt/Event Controller
Kojto 101:7cff1c4259d7 255 */
Kojto 101:7cff1c4259d7 256
Kojto 101:7cff1c4259d7 257 typedef struct
Kojto 101:7cff1c4259d7 258 {
Kojto 101:7cff1c4259d7 259 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 260 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 261 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 262 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 263 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 101:7cff1c4259d7 264 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
Kojto 101:7cff1c4259d7 265 } EXTI_TypeDef;
Kojto 101:7cff1c4259d7 266
Kojto 101:7cff1c4259d7 267 /**
Kojto 101:7cff1c4259d7 268 * @brief FLASH Registers
Kojto 101:7cff1c4259d7 269 */
Kojto 101:7cff1c4259d7 270
Kojto 101:7cff1c4259d7 271 typedef struct
Kojto 101:7cff1c4259d7 272 {
Kojto 101:7cff1c4259d7 273 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 274 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 275 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 276 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 277 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
Kojto 101:7cff1c4259d7 278 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
Kojto 101:7cff1c4259d7 279 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
Kojto 101:7cff1c4259d7 280 } FLASH_TypeDef;
Kojto 101:7cff1c4259d7 281
Kojto 101:7cff1c4259d7 282 /**
Kojto 101:7cff1c4259d7 283 * @brief General Purpose I/O
Kojto 101:7cff1c4259d7 284 */
Kojto 101:7cff1c4259d7 285
Kojto 101:7cff1c4259d7 286 typedef struct
Kojto 101:7cff1c4259d7 287 {
Kojto 101:7cff1c4259d7 288 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 289 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 290 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 291 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 292 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 101:7cff1c4259d7 293 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 101:7cff1c4259d7 294 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
Kojto 101:7cff1c4259d7 295 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 101:7cff1c4259d7 296 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
Kojto 101:7cff1c4259d7 297 } GPIO_TypeDef;
Kojto 101:7cff1c4259d7 298
Kojto 101:7cff1c4259d7 299 /**
Kojto 101:7cff1c4259d7 300 * @brief System configuration controller
Kojto 101:7cff1c4259d7 301 */
Kojto 101:7cff1c4259d7 302
Kojto 101:7cff1c4259d7 303 typedef struct
Kojto 101:7cff1c4259d7 304 {
Kojto 101:7cff1c4259d7 305 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 306 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 307 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
Kojto 101:7cff1c4259d7 308 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
Kojto 101:7cff1c4259d7 309 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
Kojto 101:7cff1c4259d7 310 } SYSCFG_TypeDef;
Kojto 101:7cff1c4259d7 311
Kojto 101:7cff1c4259d7 312 /**
Kojto 101:7cff1c4259d7 313 * @brief Inter-integrated Circuit Interface
Kojto 101:7cff1c4259d7 314 */
Kojto 101:7cff1c4259d7 315
Kojto 101:7cff1c4259d7 316 typedef struct
Kojto 101:7cff1c4259d7 317 {
Kojto 101:7cff1c4259d7 318 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 319 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 320 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 321 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 322 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
Kojto 101:7cff1c4259d7 323 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
Kojto 101:7cff1c4259d7 324 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
Kojto 101:7cff1c4259d7 325 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
Kojto 101:7cff1c4259d7 326 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
Kojto 101:7cff1c4259d7 327 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
Kojto 101:7cff1c4259d7 328 } I2C_TypeDef;
Kojto 101:7cff1c4259d7 329
Kojto 101:7cff1c4259d7 330 /**
Kojto 101:7cff1c4259d7 331 * @brief Independent WATCHDOG
Kojto 101:7cff1c4259d7 332 */
Kojto 101:7cff1c4259d7 333
Kojto 101:7cff1c4259d7 334 typedef struct
Kojto 101:7cff1c4259d7 335 {
Kojto 101:7cff1c4259d7 336 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 337 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 338 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 339 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 340 } IWDG_TypeDef;
Kojto 101:7cff1c4259d7 341
Kojto 101:7cff1c4259d7 342 /**
Kojto 101:7cff1c4259d7 343 * @brief Power Control
Kojto 101:7cff1c4259d7 344 */
Kojto 101:7cff1c4259d7 345
Kojto 101:7cff1c4259d7 346 typedef struct
Kojto 101:7cff1c4259d7 347 {
Kojto 101:7cff1c4259d7 348 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 349 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 350 } PWR_TypeDef;
Kojto 101:7cff1c4259d7 351
Kojto 101:7cff1c4259d7 352 /**
Kojto 101:7cff1c4259d7 353 * @brief Reset and Clock Control
Kojto 101:7cff1c4259d7 354 */
Kojto 101:7cff1c4259d7 355
Kojto 101:7cff1c4259d7 356 typedef struct
Kojto 101:7cff1c4259d7 357 {
Kojto 101:7cff1c4259d7 358 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 359 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 360 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 361 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 362 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
Kojto 101:7cff1c4259d7 363 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
Kojto 101:7cff1c4259d7 364 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
Kojto 101:7cff1c4259d7 365 uint32_t RESERVED0; /*!< Reserved, 0x1C */
Kojto 101:7cff1c4259d7 366 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
Kojto 101:7cff1c4259d7 367 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
Kojto 101:7cff1c4259d7 368 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
Kojto 101:7cff1c4259d7 369 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
Kojto 101:7cff1c4259d7 370 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
Kojto 101:7cff1c4259d7 371 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
Kojto 101:7cff1c4259d7 372 uint32_t RESERVED2; /*!< Reserved, 0x3C */
Kojto 101:7cff1c4259d7 373 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
Kojto 101:7cff1c4259d7 374 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
Kojto 101:7cff1c4259d7 375 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
Kojto 101:7cff1c4259d7 376 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
Kojto 101:7cff1c4259d7 377 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
Kojto 101:7cff1c4259d7 378 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
Kojto 101:7cff1c4259d7 379 uint32_t RESERVED4; /*!< Reserved, 0x5C */
Kojto 101:7cff1c4259d7 380 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
Kojto 101:7cff1c4259d7 381 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
Kojto 101:7cff1c4259d7 382 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
Kojto 101:7cff1c4259d7 383 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
Kojto 101:7cff1c4259d7 384 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
Kojto 101:7cff1c4259d7 385 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
Kojto 101:7cff1c4259d7 386 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
Kojto 101:7cff1c4259d7 387 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
Kojto 101:7cff1c4259d7 388
Kojto 101:7cff1c4259d7 389 } RCC_TypeDef;
Kojto 101:7cff1c4259d7 390
Kojto 101:7cff1c4259d7 391 /**
Kojto 101:7cff1c4259d7 392 * @brief Real-Time Clock
Kojto 101:7cff1c4259d7 393 */
Kojto 101:7cff1c4259d7 394
Kojto 101:7cff1c4259d7 395 typedef struct
Kojto 101:7cff1c4259d7 396 {
Kojto 101:7cff1c4259d7 397 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 398 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 399 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 400 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 401 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 101:7cff1c4259d7 402 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 101:7cff1c4259d7 403 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
Kojto 101:7cff1c4259d7 404 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 101:7cff1c4259d7 405 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
Kojto 101:7cff1c4259d7 406 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 101:7cff1c4259d7 407 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 101:7cff1c4259d7 408 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 101:7cff1c4259d7 409 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 101:7cff1c4259d7 410 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 101:7cff1c4259d7 411 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 101:7cff1c4259d7 412 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 101:7cff1c4259d7 413 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 101:7cff1c4259d7 414 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 101:7cff1c4259d7 415 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
Kojto 101:7cff1c4259d7 416 uint32_t RESERVED7; /*!< Reserved, 0x4C */
Kojto 101:7cff1c4259d7 417 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
Kojto 101:7cff1c4259d7 418 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 101:7cff1c4259d7 419 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 101:7cff1c4259d7 420 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 101:7cff1c4259d7 421 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 101:7cff1c4259d7 422 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
Kojto 101:7cff1c4259d7 423 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
Kojto 101:7cff1c4259d7 424 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
Kojto 101:7cff1c4259d7 425 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
Kojto 101:7cff1c4259d7 426 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
Kojto 101:7cff1c4259d7 427 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
Kojto 101:7cff1c4259d7 428 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
Kojto 101:7cff1c4259d7 429 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
Kojto 101:7cff1c4259d7 430 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
Kojto 101:7cff1c4259d7 431 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
Kojto 101:7cff1c4259d7 432 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
Kojto 101:7cff1c4259d7 433 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
Kojto 101:7cff1c4259d7 434 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
Kojto 101:7cff1c4259d7 435 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
Kojto 101:7cff1c4259d7 436 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
Kojto 101:7cff1c4259d7 437 } RTC_TypeDef;
Kojto 101:7cff1c4259d7 438
Kojto 101:7cff1c4259d7 439
Kojto 101:7cff1c4259d7 440 /**
Kojto 101:7cff1c4259d7 441 * @brief SD host Interface
Kojto 101:7cff1c4259d7 442 */
Kojto 101:7cff1c4259d7 443
Kojto 101:7cff1c4259d7 444 typedef struct
Kojto 101:7cff1c4259d7 445 {
Kojto 101:7cff1c4259d7 446 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 447 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 448 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 449 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 450 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
Kojto 101:7cff1c4259d7 451 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
Kojto 101:7cff1c4259d7 452 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
Kojto 101:7cff1c4259d7 453 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
Kojto 101:7cff1c4259d7 454 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
Kojto 101:7cff1c4259d7 455 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
Kojto 101:7cff1c4259d7 456 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
Kojto 101:7cff1c4259d7 457 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
Kojto 101:7cff1c4259d7 458 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
Kojto 101:7cff1c4259d7 459 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
Kojto 101:7cff1c4259d7 460 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
Kojto 101:7cff1c4259d7 461 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
Kojto 101:7cff1c4259d7 462 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
Kojto 101:7cff1c4259d7 463 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
Kojto 101:7cff1c4259d7 464 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
Kojto 101:7cff1c4259d7 465 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
Kojto 101:7cff1c4259d7 466 } SDIO_TypeDef;
Kojto 101:7cff1c4259d7 467
Kojto 101:7cff1c4259d7 468 /**
Kojto 101:7cff1c4259d7 469 * @brief Serial Peripheral Interface
Kojto 101:7cff1c4259d7 470 */
Kojto 101:7cff1c4259d7 471
Kojto 101:7cff1c4259d7 472 typedef struct
Kojto 101:7cff1c4259d7 473 {
Kojto 101:7cff1c4259d7 474 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 101:7cff1c4259d7 475 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 476 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 477 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 478 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 101:7cff1c4259d7 479 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 101:7cff1c4259d7 480 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 101:7cff1c4259d7 481 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 101:7cff1c4259d7 482 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 101:7cff1c4259d7 483 } SPI_TypeDef;
Kojto 101:7cff1c4259d7 484
Kojto 101:7cff1c4259d7 485 /**
Kojto 101:7cff1c4259d7 486 * @brief TIM
Kojto 101:7cff1c4259d7 487 */
Kojto 101:7cff1c4259d7 488
Kojto 101:7cff1c4259d7 489 typedef struct
Kojto 101:7cff1c4259d7 490 {
Kojto 101:7cff1c4259d7 491 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 492 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 493 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 494 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 495 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 101:7cff1c4259d7 496 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 101:7cff1c4259d7 497 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 101:7cff1c4259d7 498 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 101:7cff1c4259d7 499 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 101:7cff1c4259d7 500 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 101:7cff1c4259d7 501 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
Kojto 101:7cff1c4259d7 502 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 101:7cff1c4259d7 503 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 101:7cff1c4259d7 504 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 101:7cff1c4259d7 505 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 101:7cff1c4259d7 506 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 101:7cff1c4259d7 507 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 101:7cff1c4259d7 508 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 101:7cff1c4259d7 509 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 101:7cff1c4259d7 510 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
Kojto 101:7cff1c4259d7 511 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 101:7cff1c4259d7 512 } TIM_TypeDef;
Kojto 101:7cff1c4259d7 513
Kojto 101:7cff1c4259d7 514 /**
Kojto 101:7cff1c4259d7 515 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 101:7cff1c4259d7 516 */
Kojto 101:7cff1c4259d7 517
Kojto 101:7cff1c4259d7 518 typedef struct
Kojto 101:7cff1c4259d7 519 {
Kojto 101:7cff1c4259d7 520 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 521 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 522 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 523 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
Kojto 101:7cff1c4259d7 524 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
Kojto 101:7cff1c4259d7 525 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
Kojto 101:7cff1c4259d7 526 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
Kojto 101:7cff1c4259d7 527 } USART_TypeDef;
Kojto 101:7cff1c4259d7 528
Kojto 101:7cff1c4259d7 529 /**
Kojto 101:7cff1c4259d7 530 * @brief Window WATCHDOG
Kojto 101:7cff1c4259d7 531 */
Kojto 101:7cff1c4259d7 532
Kojto 101:7cff1c4259d7 533 typedef struct
Kojto 101:7cff1c4259d7 534 {
Kojto 101:7cff1c4259d7 535 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 101:7cff1c4259d7 536 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 101:7cff1c4259d7 537 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 101:7cff1c4259d7 538 } WWDG_TypeDef;
Kojto 101:7cff1c4259d7 539
Kojto 101:7cff1c4259d7 540
Kojto 101:7cff1c4259d7 541 /**
Kojto 101:7cff1c4259d7 542 * @brief __USB_OTG_Core_register
Kojto 101:7cff1c4259d7 543 */
Kojto 101:7cff1c4259d7 544 typedef struct
Kojto 101:7cff1c4259d7 545 {
Kojto 101:7cff1c4259d7 546 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
Kojto 101:7cff1c4259d7 547 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
Kojto 101:7cff1c4259d7 548 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
Kojto 101:7cff1c4259d7 549 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
Kojto 101:7cff1c4259d7 550 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
Kojto 101:7cff1c4259d7 551 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
Kojto 101:7cff1c4259d7 552 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
Kojto 101:7cff1c4259d7 553 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
Kojto 101:7cff1c4259d7 554 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
Kojto 101:7cff1c4259d7 555 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
Kojto 101:7cff1c4259d7 556 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
Kojto 101:7cff1c4259d7 557 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
Kojto 101:7cff1c4259d7 558 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
Kojto 101:7cff1c4259d7 559 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
Kojto 101:7cff1c4259d7 560 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
Kojto 101:7cff1c4259d7 561 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
Kojto 101:7cff1c4259d7 562 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
Kojto 101:7cff1c4259d7 563 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
Kojto 101:7cff1c4259d7 564 }
Kojto 101:7cff1c4259d7 565 USB_OTG_GlobalTypeDef;
Kojto 101:7cff1c4259d7 566
Kojto 101:7cff1c4259d7 567
Kojto 101:7cff1c4259d7 568
Kojto 101:7cff1c4259d7 569 /**
Kojto 101:7cff1c4259d7 570 * @brief __device_Registers
Kojto 101:7cff1c4259d7 571 */
Kojto 101:7cff1c4259d7 572 typedef struct
Kojto 101:7cff1c4259d7 573 {
Kojto 101:7cff1c4259d7 574 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
Kojto 101:7cff1c4259d7 575 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
Kojto 101:7cff1c4259d7 576 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
Kojto 101:7cff1c4259d7 577 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
Kojto 101:7cff1c4259d7 578 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
Kojto 101:7cff1c4259d7 579 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
Kojto 101:7cff1c4259d7 580 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
Kojto 101:7cff1c4259d7 581 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
Kojto 101:7cff1c4259d7 582 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
Kojto 101:7cff1c4259d7 583 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
Kojto 101:7cff1c4259d7 584 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
Kojto 101:7cff1c4259d7 585 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
Kojto 101:7cff1c4259d7 586 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
Kojto 101:7cff1c4259d7 587 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
Kojto 101:7cff1c4259d7 588 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
Kojto 101:7cff1c4259d7 589 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
Kojto 101:7cff1c4259d7 590 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
Kojto 101:7cff1c4259d7 591 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
Kojto 101:7cff1c4259d7 592 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
Kojto 101:7cff1c4259d7 593 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
Kojto 101:7cff1c4259d7 594 }
Kojto 101:7cff1c4259d7 595 USB_OTG_DeviceTypeDef;
Kojto 101:7cff1c4259d7 596
Kojto 101:7cff1c4259d7 597
Kojto 101:7cff1c4259d7 598 /**
Kojto 101:7cff1c4259d7 599 * @brief __IN_Endpoint-Specific_Register
Kojto 101:7cff1c4259d7 600 */
Kojto 101:7cff1c4259d7 601 typedef struct
Kojto 101:7cff1c4259d7 602 {
Kojto 101:7cff1c4259d7 603 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
Kojto 101:7cff1c4259d7 604 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
Kojto 101:7cff1c4259d7 605 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
Kojto 101:7cff1c4259d7 606 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
Kojto 101:7cff1c4259d7 607 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
Kojto 101:7cff1c4259d7 608 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
Kojto 101:7cff1c4259d7 609 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
Kojto 101:7cff1c4259d7 610 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
Kojto 101:7cff1c4259d7 611 }
Kojto 101:7cff1c4259d7 612 USB_OTG_INEndpointTypeDef;
Kojto 101:7cff1c4259d7 613
Kojto 101:7cff1c4259d7 614
Kojto 101:7cff1c4259d7 615 /**
Kojto 101:7cff1c4259d7 616 * @brief __OUT_Endpoint-Specific_Registers
Kojto 101:7cff1c4259d7 617 */
Kojto 101:7cff1c4259d7 618 typedef struct
Kojto 101:7cff1c4259d7 619 {
Kojto 101:7cff1c4259d7 620 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
Kojto 101:7cff1c4259d7 621 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
Kojto 101:7cff1c4259d7 622 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
Kojto 101:7cff1c4259d7 623 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
Kojto 101:7cff1c4259d7 624 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
Kojto 101:7cff1c4259d7 625 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
Kojto 101:7cff1c4259d7 626 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
Kojto 101:7cff1c4259d7 627 }
Kojto 101:7cff1c4259d7 628 USB_OTG_OUTEndpointTypeDef;
Kojto 101:7cff1c4259d7 629
Kojto 101:7cff1c4259d7 630
Kojto 101:7cff1c4259d7 631 /**
Kojto 101:7cff1c4259d7 632 * @brief __Host_Mode_Register_Structures
Kojto 101:7cff1c4259d7 633 */
Kojto 101:7cff1c4259d7 634 typedef struct
Kojto 101:7cff1c4259d7 635 {
Kojto 101:7cff1c4259d7 636 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
Kojto 101:7cff1c4259d7 637 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
Kojto 101:7cff1c4259d7 638 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
Kojto 101:7cff1c4259d7 639 uint32_t Reserved40C; /* Reserved 40Ch*/
Kojto 101:7cff1c4259d7 640 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
Kojto 101:7cff1c4259d7 641 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
Kojto 101:7cff1c4259d7 642 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
Kojto 101:7cff1c4259d7 643 }
Kojto 101:7cff1c4259d7 644 USB_OTG_HostTypeDef;
Kojto 101:7cff1c4259d7 645
Kojto 101:7cff1c4259d7 646
Kojto 101:7cff1c4259d7 647 /**
Kojto 101:7cff1c4259d7 648 * @brief __Host_Channel_Specific_Registers
Kojto 101:7cff1c4259d7 649 */
Kojto 101:7cff1c4259d7 650 typedef struct
Kojto 101:7cff1c4259d7 651 {
Kojto 101:7cff1c4259d7 652 __IO uint32_t HCCHAR;
Kojto 101:7cff1c4259d7 653 __IO uint32_t HCSPLT;
Kojto 101:7cff1c4259d7 654 __IO uint32_t HCINT;
Kojto 101:7cff1c4259d7 655 __IO uint32_t HCINTMSK;
Kojto 101:7cff1c4259d7 656 __IO uint32_t HCTSIZ;
Kojto 101:7cff1c4259d7 657 __IO uint32_t HCDMA;
Kojto 101:7cff1c4259d7 658 uint32_t Reserved[2];
Kojto 101:7cff1c4259d7 659 }
Kojto 101:7cff1c4259d7 660 USB_OTG_HostChannelTypeDef;
Kojto 101:7cff1c4259d7 661
Kojto 101:7cff1c4259d7 662
Kojto 101:7cff1c4259d7 663 /**
Kojto 101:7cff1c4259d7 664 * @brief Peripheral_memory_map
Kojto 101:7cff1c4259d7 665 */
Kojto 101:7cff1c4259d7 666 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
Kojto 101:7cff1c4259d7 667 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
Kojto 101:7cff1c4259d7 668 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
Kojto 101:7cff1c4259d7 669 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
Kojto 101:7cff1c4259d7 670 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
Kojto 101:7cff1c4259d7 671 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
Kojto 101:7cff1c4259d7 672 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
Kojto 101:7cff1c4259d7 673 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
Kojto 101:7cff1c4259d7 674 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
Kojto 101:7cff1c4259d7 675 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
Kojto 101:7cff1c4259d7 676 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
Kojto 101:7cff1c4259d7 677 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
Kojto 101:7cff1c4259d7 678 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
Kojto 101:7cff1c4259d7 679 #define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
Kojto 101:7cff1c4259d7 680
Kojto 101:7cff1c4259d7 681 /* Legacy defines */
Kojto 101:7cff1c4259d7 682 #define SRAM_BASE SRAM1_BASE
Kojto 101:7cff1c4259d7 683 #define SRAM_BB_BASE SRAM1_BB_BASE
Kojto 101:7cff1c4259d7 684
Kojto 101:7cff1c4259d7 685
Kojto 101:7cff1c4259d7 686 /*!< Peripheral memory map */
Kojto 101:7cff1c4259d7 687 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 101:7cff1c4259d7 688 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
Kojto 101:7cff1c4259d7 689 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 101:7cff1c4259d7 690 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
Kojto 101:7cff1c4259d7 691
Kojto 101:7cff1c4259d7 692 /*!< APB1 peripherals */
Kojto 101:7cff1c4259d7 693 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
Kojto 101:7cff1c4259d7 694 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
Kojto 101:7cff1c4259d7 695 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
Kojto 101:7cff1c4259d7 696 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
Kojto 101:7cff1c4259d7 697 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
Kojto 101:7cff1c4259d7 698 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
Kojto 101:7cff1c4259d7 699 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
Kojto 101:7cff1c4259d7 700 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
Kojto 101:7cff1c4259d7 701 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
Kojto 101:7cff1c4259d7 702 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
Kojto 101:7cff1c4259d7 703 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
Kojto 101:7cff1c4259d7 704 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
Kojto 101:7cff1c4259d7 705 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
Kojto 101:7cff1c4259d7 706 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
Kojto 101:7cff1c4259d7 707 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
Kojto 101:7cff1c4259d7 708 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
Kojto 101:7cff1c4259d7 709
Kojto 101:7cff1c4259d7 710 /*!< APB2 peripherals */
Kojto 101:7cff1c4259d7 711 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
Kojto 101:7cff1c4259d7 712 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
Kojto 101:7cff1c4259d7 713 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
Kojto 101:7cff1c4259d7 714 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
Kojto 101:7cff1c4259d7 715 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
Kojto 101:7cff1c4259d7 716 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
Kojto 101:7cff1c4259d7 717 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
Kojto 101:7cff1c4259d7 718 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
Kojto 101:7cff1c4259d7 719 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
Kojto 101:7cff1c4259d7 720 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
Kojto 101:7cff1c4259d7 721 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
Kojto 101:7cff1c4259d7 722 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
Kojto 101:7cff1c4259d7 723 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
Kojto 101:7cff1c4259d7 724 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
Kojto 101:7cff1c4259d7 725
Kojto 101:7cff1c4259d7 726 /*!< AHB1 peripherals */
Kojto 101:7cff1c4259d7 727 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
Kojto 101:7cff1c4259d7 728 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
Kojto 101:7cff1c4259d7 729 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
Kojto 101:7cff1c4259d7 730 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
Kojto 101:7cff1c4259d7 731 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
Kojto 101:7cff1c4259d7 732 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
Kojto 101:7cff1c4259d7 733 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
Kojto 101:7cff1c4259d7 734 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
Kojto 101:7cff1c4259d7 735 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
Kojto 101:7cff1c4259d7 736 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
Kojto 101:7cff1c4259d7 737 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
Kojto 101:7cff1c4259d7 738 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
Kojto 101:7cff1c4259d7 739 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
Kojto 101:7cff1c4259d7 740 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
Kojto 101:7cff1c4259d7 741 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
Kojto 101:7cff1c4259d7 742 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
Kojto 101:7cff1c4259d7 743 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
Kojto 101:7cff1c4259d7 744 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
Kojto 101:7cff1c4259d7 745 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
Kojto 101:7cff1c4259d7 746 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
Kojto 101:7cff1c4259d7 747 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
Kojto 101:7cff1c4259d7 748 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
Kojto 101:7cff1c4259d7 749 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
Kojto 101:7cff1c4259d7 750 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
Kojto 101:7cff1c4259d7 751 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
Kojto 101:7cff1c4259d7 752 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
Kojto 101:7cff1c4259d7 753 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
Kojto 101:7cff1c4259d7 754
Kojto 101:7cff1c4259d7 755 /* Debug MCU registers base address */
Kojto 101:7cff1c4259d7 756 #define DBGMCU_BASE ((uint32_t )0xE0042000)
Kojto 101:7cff1c4259d7 757
Kojto 101:7cff1c4259d7 758 /*!< USB registers base address */
Kojto 101:7cff1c4259d7 759 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
Kojto 101:7cff1c4259d7 760
Kojto 101:7cff1c4259d7 761 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
Kojto 101:7cff1c4259d7 762 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
Kojto 101:7cff1c4259d7 763 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
Kojto 101:7cff1c4259d7 764 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
Kojto 101:7cff1c4259d7 765 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
Kojto 101:7cff1c4259d7 766 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
Kojto 101:7cff1c4259d7 767 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
Kojto 101:7cff1c4259d7 768 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
Kojto 101:7cff1c4259d7 769 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
Kojto 101:7cff1c4259d7 770 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
Kojto 101:7cff1c4259d7 771 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
Kojto 101:7cff1c4259d7 772 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
Kojto 101:7cff1c4259d7 773
Kojto 101:7cff1c4259d7 774 /**
Kojto 101:7cff1c4259d7 775 * @}
Kojto 101:7cff1c4259d7 776 */
Kojto 101:7cff1c4259d7 777
Kojto 101:7cff1c4259d7 778 /** @addtogroup Peripheral_declaration
Kojto 101:7cff1c4259d7 779 * @{
Kojto 101:7cff1c4259d7 780 */
Kojto 101:7cff1c4259d7 781 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 101:7cff1c4259d7 782 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 101:7cff1c4259d7 783 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto 101:7cff1c4259d7 784 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto 101:7cff1c4259d7 785 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 101:7cff1c4259d7 786 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 101:7cff1c4259d7 787 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 101:7cff1c4259d7 788 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
Kojto 101:7cff1c4259d7 789 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 101:7cff1c4259d7 790 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto 101:7cff1c4259d7 791 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
Kojto 101:7cff1c4259d7 792 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 101:7cff1c4259d7 793 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 101:7cff1c4259d7 794 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 101:7cff1c4259d7 795 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
Kojto 101:7cff1c4259d7 796 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 101:7cff1c4259d7 797 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 101:7cff1c4259d7 798 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 101:7cff1c4259d7 799 #define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto 101:7cff1c4259d7 800 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 101:7cff1c4259d7 801 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 101:7cff1c4259d7 802 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
Kojto 101:7cff1c4259d7 803 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 101:7cff1c4259d7 804 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
Kojto 101:7cff1c4259d7 805 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 101:7cff1c4259d7 806 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 101:7cff1c4259d7 807 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto 101:7cff1c4259d7 808 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto 101:7cff1c4259d7 809 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto 101:7cff1c4259d7 810 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
Kojto 101:7cff1c4259d7 811 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 101:7cff1c4259d7 812 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 101:7cff1c4259d7 813 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 101:7cff1c4259d7 814 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 101:7cff1c4259d7 815 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto 101:7cff1c4259d7 816 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto 101:7cff1c4259d7 817 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 101:7cff1c4259d7 818 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 101:7cff1c4259d7 819 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 101:7cff1c4259d7 820 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 101:7cff1c4259d7 821 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Kojto 101:7cff1c4259d7 822 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
Kojto 101:7cff1c4259d7 823 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
Kojto 101:7cff1c4259d7 824 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
Kojto 101:7cff1c4259d7 825 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
Kojto 101:7cff1c4259d7 826 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
Kojto 101:7cff1c4259d7 827 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
Kojto 101:7cff1c4259d7 828 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
Kojto 101:7cff1c4259d7 829 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto 101:7cff1c4259d7 830 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
Kojto 101:7cff1c4259d7 831 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
Kojto 101:7cff1c4259d7 832 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
Kojto 101:7cff1c4259d7 833 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
Kojto 101:7cff1c4259d7 834 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
Kojto 101:7cff1c4259d7 835 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
Kojto 101:7cff1c4259d7 836 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
Kojto 101:7cff1c4259d7 837 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
Kojto 101:7cff1c4259d7 838
Kojto 101:7cff1c4259d7 839 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 101:7cff1c4259d7 840
Kojto 101:7cff1c4259d7 841 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
Kojto 101:7cff1c4259d7 842
Kojto 101:7cff1c4259d7 843 /**
Kojto 101:7cff1c4259d7 844 * @}
Kojto 101:7cff1c4259d7 845 */
Kojto 101:7cff1c4259d7 846
Kojto 101:7cff1c4259d7 847 /** @addtogroup Exported_constants
Kojto 101:7cff1c4259d7 848 * @{
Kojto 101:7cff1c4259d7 849 */
Kojto 101:7cff1c4259d7 850
Kojto 101:7cff1c4259d7 851 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 101:7cff1c4259d7 852 * @{
Kojto 101:7cff1c4259d7 853 */
Kojto 101:7cff1c4259d7 854
Kojto 101:7cff1c4259d7 855 /******************************************************************************/
Kojto 101:7cff1c4259d7 856 /* Peripheral Registers_Bits_Definition */
Kojto 101:7cff1c4259d7 857 /******************************************************************************/
Kojto 101:7cff1c4259d7 858
Kojto 101:7cff1c4259d7 859 /******************************************************************************/
Kojto 101:7cff1c4259d7 860 /* */
Kojto 101:7cff1c4259d7 861 /* Analog to Digital Converter */
Kojto 101:7cff1c4259d7 862 /* */
Kojto 101:7cff1c4259d7 863 /******************************************************************************/
Kojto 101:7cff1c4259d7 864 /******************** Bit definition for ADC_SR register ********************/
Kojto 101:7cff1c4259d7 865 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
Kojto 101:7cff1c4259d7 866 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
Kojto 101:7cff1c4259d7 867 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
Kojto 101:7cff1c4259d7 868 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
Kojto 101:7cff1c4259d7 869 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
Kojto 101:7cff1c4259d7 870 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
Kojto 101:7cff1c4259d7 871
Kojto 101:7cff1c4259d7 872 /******************* Bit definition for ADC_CR1 register ********************/
Kojto 101:7cff1c4259d7 873 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 101:7cff1c4259d7 874 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 875 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 876 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 877 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 878 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 879 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
Kojto 101:7cff1c4259d7 880 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
Kojto 101:7cff1c4259d7 881 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
Kojto 101:7cff1c4259d7 882 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
Kojto 101:7cff1c4259d7 883 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
Kojto 101:7cff1c4259d7 884 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
Kojto 101:7cff1c4259d7 885 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
Kojto 101:7cff1c4259d7 886 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
Kojto 101:7cff1c4259d7 887 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
Kojto 101:7cff1c4259d7 888 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 889 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 890 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 891 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
Kojto 101:7cff1c4259d7 892 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
Kojto 101:7cff1c4259d7 893 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
Kojto 101:7cff1c4259d7 894 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 895 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 896 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
Kojto 101:7cff1c4259d7 897
Kojto 101:7cff1c4259d7 898 /******************* Bit definition for ADC_CR2 register ********************/
Kojto 101:7cff1c4259d7 899 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
Kojto 101:7cff1c4259d7 900 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
Kojto 101:7cff1c4259d7 901 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
Kojto 101:7cff1c4259d7 902 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
Kojto 101:7cff1c4259d7 903 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
Kojto 101:7cff1c4259d7 904 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
Kojto 101:7cff1c4259d7 905 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
Kojto 101:7cff1c4259d7 906 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 907 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 908 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 909 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 910 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
Kojto 101:7cff1c4259d7 911 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 912 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 913 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
Kojto 101:7cff1c4259d7 914 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
Kojto 101:7cff1c4259d7 915 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 916 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 917 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 918 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 919 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
Kojto 101:7cff1c4259d7 920 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 921 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 922 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
Kojto 101:7cff1c4259d7 923
Kojto 101:7cff1c4259d7 924 /****************** Bit definition for ADC_SMPR1 register *******************/
Kojto 101:7cff1c4259d7 925 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
Kojto 101:7cff1c4259d7 926 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 927 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 928 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 929 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
Kojto 101:7cff1c4259d7 930 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 931 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 932 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 933 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
Kojto 101:7cff1c4259d7 934 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 935 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 936 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 937 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
Kojto 101:7cff1c4259d7 938 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 939 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 940 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 941 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
Kojto 101:7cff1c4259d7 942 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 943 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 944 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 945 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
Kojto 101:7cff1c4259d7 946 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 947 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 948 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 949 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
Kojto 101:7cff1c4259d7 950 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 951 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 952 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 953 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
Kojto 101:7cff1c4259d7 954 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 955 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 956 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 957 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
Kojto 101:7cff1c4259d7 958 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 959 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 960 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 961
Kojto 101:7cff1c4259d7 962 /****************** Bit definition for ADC_SMPR2 register *******************/
Kojto 101:7cff1c4259d7 963 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
Kojto 101:7cff1c4259d7 964 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 965 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 966 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 967 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
Kojto 101:7cff1c4259d7 968 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 969 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 970 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 971 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
Kojto 101:7cff1c4259d7 972 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 973 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 974 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 975 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
Kojto 101:7cff1c4259d7 976 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 977 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 978 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 979 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
Kojto 101:7cff1c4259d7 980 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 981 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 982 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 983 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
Kojto 101:7cff1c4259d7 984 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 985 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 986 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 987 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
Kojto 101:7cff1c4259d7 988 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 989 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 990 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 991 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
Kojto 101:7cff1c4259d7 992 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 993 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 994 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 995 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
Kojto 101:7cff1c4259d7 996 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 997 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 998 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 999 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
Kojto 101:7cff1c4259d7 1000 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1001 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1002 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1003
Kojto 101:7cff1c4259d7 1004 /****************** Bit definition for ADC_JOFR1 register *******************/
Kojto 101:7cff1c4259d7 1005 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
Kojto 101:7cff1c4259d7 1006
Kojto 101:7cff1c4259d7 1007 /****************** Bit definition for ADC_JOFR2 register *******************/
Kojto 101:7cff1c4259d7 1008 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
Kojto 101:7cff1c4259d7 1009
Kojto 101:7cff1c4259d7 1010 /****************** Bit definition for ADC_JOFR3 register *******************/
Kojto 101:7cff1c4259d7 1011 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
Kojto 101:7cff1c4259d7 1012
Kojto 101:7cff1c4259d7 1013 /****************** Bit definition for ADC_JOFR4 register *******************/
Kojto 101:7cff1c4259d7 1014 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
Kojto 101:7cff1c4259d7 1015
Kojto 101:7cff1c4259d7 1016 /******************* Bit definition for ADC_HTR register ********************/
Kojto 101:7cff1c4259d7 1017 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
Kojto 101:7cff1c4259d7 1018
Kojto 101:7cff1c4259d7 1019 /******************* Bit definition for ADC_LTR register ********************/
Kojto 101:7cff1c4259d7 1020 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
Kojto 101:7cff1c4259d7 1021
Kojto 101:7cff1c4259d7 1022 /******************* Bit definition for ADC_SQR1 register *******************/
Kojto 101:7cff1c4259d7 1023 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1024 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1025 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1026 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1027 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1028 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1029 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1030 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1031 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1032 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1033 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1034 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1035 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1036 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1037 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1038 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1039 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1040 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1041 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1042 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1043 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1044 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1045 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1046 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1047 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
Kojto 101:7cff1c4259d7 1048 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1049 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1050 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1051 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1052
Kojto 101:7cff1c4259d7 1053 /******************* Bit definition for ADC_SQR2 register *******************/
Kojto 101:7cff1c4259d7 1054 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1055 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1056 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1057 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1058 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1059 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1060 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1061 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1062 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1063 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1064 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1065 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1066 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1067 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1068 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1069 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1070 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1071 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1072 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1073 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1074 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1075 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1076 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1077 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1078 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1079 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1080 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1081 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1082 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1083 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1084 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1085 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1086 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1087 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1088 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1089 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1090
Kojto 101:7cff1c4259d7 1091 /******************* Bit definition for ADC_SQR3 register *******************/
Kojto 101:7cff1c4259d7 1092 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1093 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1094 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1095 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1096 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1097 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1098 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1099 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1100 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1101 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1102 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1103 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1104 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1105 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1106 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1107 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1108 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1109 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1110 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1111 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1112 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1113 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1114 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1115 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1116 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1117 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1118 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1119 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1120 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1121 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1122 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
Kojto 101:7cff1c4259d7 1123 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1124 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1125 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1126 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1127 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1128
Kojto 101:7cff1c4259d7 1129 /******************* Bit definition for ADC_JSQR register *******************/
Kojto 101:7cff1c4259d7 1130 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
Kojto 101:7cff1c4259d7 1131 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1132 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1133 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1134 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1135 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1136 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
Kojto 101:7cff1c4259d7 1137 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1138 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1139 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1140 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1141 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1142 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
Kojto 101:7cff1c4259d7 1143 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1144 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1145 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1146 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1147 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1148 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
Kojto 101:7cff1c4259d7 1149 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1150 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1151 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1152 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1153 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1154 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
Kojto 101:7cff1c4259d7 1155 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1156 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1157
Kojto 101:7cff1c4259d7 1158 /******************* Bit definition for ADC_JDR1 register *******************/
Kojto 101:7cff1c4259d7 1159 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 101:7cff1c4259d7 1160
Kojto 101:7cff1c4259d7 1161 /******************* Bit definition for ADC_JDR2 register *******************/
Kojto 101:7cff1c4259d7 1162 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 101:7cff1c4259d7 1163
Kojto 101:7cff1c4259d7 1164 /******************* Bit definition for ADC_JDR3 register *******************/
Kojto 101:7cff1c4259d7 1165 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 101:7cff1c4259d7 1166
Kojto 101:7cff1c4259d7 1167 /******************* Bit definition for ADC_JDR4 register *******************/
Kojto 101:7cff1c4259d7 1168 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 101:7cff1c4259d7 1169
Kojto 101:7cff1c4259d7 1170 /******************** Bit definition for ADC_DR register ********************/
Kojto 101:7cff1c4259d7 1171 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
Kojto 101:7cff1c4259d7 1172 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
Kojto 101:7cff1c4259d7 1173
Kojto 101:7cff1c4259d7 1174 /******************* Bit definition for ADC_CSR register ********************/
Kojto 101:7cff1c4259d7 1175 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
Kojto 101:7cff1c4259d7 1176 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
Kojto 101:7cff1c4259d7 1177 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
Kojto 101:7cff1c4259d7 1178 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
Kojto 101:7cff1c4259d7 1179 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
Kojto 101:7cff1c4259d7 1180 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
Kojto 101:7cff1c4259d7 1181 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
Kojto 101:7cff1c4259d7 1182 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
Kojto 101:7cff1c4259d7 1183 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
Kojto 101:7cff1c4259d7 1184 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
Kojto 101:7cff1c4259d7 1185 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
Kojto 101:7cff1c4259d7 1186 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
Kojto 101:7cff1c4259d7 1187 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
Kojto 101:7cff1c4259d7 1188 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
Kojto 101:7cff1c4259d7 1189 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
Kojto 101:7cff1c4259d7 1190 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
Kojto 101:7cff1c4259d7 1191 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
Kojto 101:7cff1c4259d7 1192 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
Kojto 101:7cff1c4259d7 1193
Kojto 101:7cff1c4259d7 1194 /******************* Bit definition for ADC_CCR register ********************/
Kojto 101:7cff1c4259d7 1195 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
Kojto 101:7cff1c4259d7 1196 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1197 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1198 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1199 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1200 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 1201 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
Kojto 101:7cff1c4259d7 1202 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1203 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1204 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 1205 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 1206 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
Kojto 101:7cff1c4259d7 1207 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
Kojto 101:7cff1c4259d7 1208 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1209 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1210 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
Kojto 101:7cff1c4259d7 1211 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 1212 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 1213 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
Kojto 101:7cff1c4259d7 1214 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
Kojto 101:7cff1c4259d7 1215
Kojto 101:7cff1c4259d7 1216 /******************* Bit definition for ADC_CDR register ********************/
Kojto 101:7cff1c4259d7 1217 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
Kojto 101:7cff1c4259d7 1218 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
Kojto 101:7cff1c4259d7 1219
Kojto 101:7cff1c4259d7 1220 /******************************************************************************/
Kojto 101:7cff1c4259d7 1221 /* */
Kojto 101:7cff1c4259d7 1222 /* CRC calculation unit */
Kojto 101:7cff1c4259d7 1223 /* */
Kojto 101:7cff1c4259d7 1224 /******************************************************************************/
Kojto 101:7cff1c4259d7 1225 /******************* Bit definition for CRC_DR register *********************/
Kojto 101:7cff1c4259d7 1226 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
Kojto 101:7cff1c4259d7 1227
Kojto 101:7cff1c4259d7 1228
Kojto 101:7cff1c4259d7 1229 /******************* Bit definition for CRC_IDR register ********************/
Kojto 101:7cff1c4259d7 1230 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
Kojto 101:7cff1c4259d7 1231
Kojto 101:7cff1c4259d7 1232
Kojto 101:7cff1c4259d7 1233 /******************** Bit definition for CRC_CR register ********************/
Kojto 101:7cff1c4259d7 1234 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
Kojto 101:7cff1c4259d7 1235
Kojto 101:7cff1c4259d7 1236 /******************************************************************************/
Kojto 101:7cff1c4259d7 1237 /* */
Kojto 101:7cff1c4259d7 1238 /* Debug MCU */
Kojto 101:7cff1c4259d7 1239 /* */
Kojto 101:7cff1c4259d7 1240 /******************************************************************************/
Kojto 101:7cff1c4259d7 1241
Kojto 101:7cff1c4259d7 1242 /******************************************************************************/
Kojto 101:7cff1c4259d7 1243 /* */
Kojto 101:7cff1c4259d7 1244 /* DMA Controller */
Kojto 101:7cff1c4259d7 1245 /* */
Kojto 101:7cff1c4259d7 1246 /******************************************************************************/
Kojto 101:7cff1c4259d7 1247 /******************** Bits definition for DMA_SxCR register *****************/
Kojto 101:7cff1c4259d7 1248 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
Kojto 101:7cff1c4259d7 1249 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 1250 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 1251 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 1252 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
Kojto 101:7cff1c4259d7 1253 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 1254 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 1255 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
Kojto 101:7cff1c4259d7 1256 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 1257 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 1258 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 1259 #define DMA_SxCR_CT ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 1260 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 1261 #define DMA_SxCR_PL ((uint32_t)0x00030000)
Kojto 101:7cff1c4259d7 1262 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1263 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 1264 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 1265 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
Kojto 101:7cff1c4259d7 1266 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 1267 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 1268 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
Kojto 101:7cff1c4259d7 1269 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1270 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 1271 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1272 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1273 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1274 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
Kojto 101:7cff1c4259d7 1275 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1276 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1277 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1278 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1279 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1280 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1281 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1282 #define DMA_SxCR_EN ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1283
Kojto 101:7cff1c4259d7 1284 /******************** Bits definition for DMA_SxCNDTR register **************/
Kojto 101:7cff1c4259d7 1285 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
Kojto 101:7cff1c4259d7 1286 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1287 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1288 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1289 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1290 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1291 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1292 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1293 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1294 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1295 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1296 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1297 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1298 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 1299 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 1300 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 1301 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 1302
Kojto 101:7cff1c4259d7 1303 /******************** Bits definition for DMA_SxFCR register ****************/
Kojto 101:7cff1c4259d7 1304 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1305 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
Kojto 101:7cff1c4259d7 1306 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1307 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1308 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1309 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1310 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
Kojto 101:7cff1c4259d7 1311 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1312 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1313
Kojto 101:7cff1c4259d7 1314 /******************** Bits definition for DMA_LISR register *****************/
Kojto 101:7cff1c4259d7 1315 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 1316 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 1317 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 1318 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 1319 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 1320 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 1321 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 1322 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 1323 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 1324 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1325 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1326 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1327 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1328 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1329 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1330 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1331 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1332 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1333 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1334 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1335
Kojto 101:7cff1c4259d7 1336 /******************** Bits definition for DMA_HISR register *****************/
Kojto 101:7cff1c4259d7 1337 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 1338 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 1339 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 1340 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 1341 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 1342 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 1343 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 1344 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 1345 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 1346 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1347 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1348 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1349 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1350 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1351 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1352 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1353 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1354 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1355 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1356 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1357
Kojto 101:7cff1c4259d7 1358 /******************** Bits definition for DMA_LIFCR register ****************/
Kojto 101:7cff1c4259d7 1359 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 1360 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 1361 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 1362 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 1363 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 1364 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 1365 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 1366 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 1367 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 1368 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1369 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1370 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1371 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1372 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1373 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1374 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1375 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1376 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1377 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1378 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1379
Kojto 101:7cff1c4259d7 1380 /******************** Bits definition for DMA_HIFCR register ****************/
Kojto 101:7cff1c4259d7 1381 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 1382 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 1383 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 1384 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 1385 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 1386 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 1387 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 1388 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 1389 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 1390 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1391 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1392 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1393 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1394 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1395 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1396 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1397 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1398 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1399 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1400 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1401
Kojto 101:7cff1c4259d7 1402
Kojto 101:7cff1c4259d7 1403 /******************************************************************************/
Kojto 101:7cff1c4259d7 1404 /* */
Kojto 101:7cff1c4259d7 1405 /* External Interrupt/Event Controller */
Kojto 101:7cff1c4259d7 1406 /* */
Kojto 101:7cff1c4259d7 1407 /******************************************************************************/
Kojto 101:7cff1c4259d7 1408 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 101:7cff1c4259d7 1409 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
Kojto 101:7cff1c4259d7 1410 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
Kojto 101:7cff1c4259d7 1411 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
Kojto 101:7cff1c4259d7 1412 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
Kojto 101:7cff1c4259d7 1413 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
Kojto 101:7cff1c4259d7 1414 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
Kojto 101:7cff1c4259d7 1415 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
Kojto 101:7cff1c4259d7 1416 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
Kojto 101:7cff1c4259d7 1417 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
Kojto 101:7cff1c4259d7 1418 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
Kojto 101:7cff1c4259d7 1419 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
Kojto 101:7cff1c4259d7 1420 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
Kojto 101:7cff1c4259d7 1421 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
Kojto 101:7cff1c4259d7 1422 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
Kojto 101:7cff1c4259d7 1423 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
Kojto 101:7cff1c4259d7 1424 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
Kojto 101:7cff1c4259d7 1425 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
Kojto 101:7cff1c4259d7 1426 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
Kojto 101:7cff1c4259d7 1427 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
Kojto 101:7cff1c4259d7 1428 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
Kojto 101:7cff1c4259d7 1429 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
Kojto 101:7cff1c4259d7 1430 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
Kojto 101:7cff1c4259d7 1431 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
Kojto 101:7cff1c4259d7 1432
Kojto 101:7cff1c4259d7 1433 /******************* Bit definition for EXTI_EMR register *******************/
Kojto 101:7cff1c4259d7 1434 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Kojto 101:7cff1c4259d7 1435 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
Kojto 101:7cff1c4259d7 1436 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
Kojto 101:7cff1c4259d7 1437 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
Kojto 101:7cff1c4259d7 1438 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
Kojto 101:7cff1c4259d7 1439 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
Kojto 101:7cff1c4259d7 1440 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
Kojto 101:7cff1c4259d7 1441 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
Kojto 101:7cff1c4259d7 1442 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
Kojto 101:7cff1c4259d7 1443 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
Kojto 101:7cff1c4259d7 1444 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
Kojto 101:7cff1c4259d7 1445 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
Kojto 101:7cff1c4259d7 1446 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
Kojto 101:7cff1c4259d7 1447 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
Kojto 101:7cff1c4259d7 1448 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
Kojto 101:7cff1c4259d7 1449 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
Kojto 101:7cff1c4259d7 1450 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
Kojto 101:7cff1c4259d7 1451 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
Kojto 101:7cff1c4259d7 1452 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
Kojto 101:7cff1c4259d7 1453 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
Kojto 101:7cff1c4259d7 1454 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
Kojto 101:7cff1c4259d7 1455 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
Kojto 101:7cff1c4259d7 1456 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
Kojto 101:7cff1c4259d7 1457
Kojto 101:7cff1c4259d7 1458 /****************** Bit definition for EXTI_RTSR register *******************/
Kojto 101:7cff1c4259d7 1459 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Kojto 101:7cff1c4259d7 1460 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
Kojto 101:7cff1c4259d7 1461 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
Kojto 101:7cff1c4259d7 1462 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
Kojto 101:7cff1c4259d7 1463 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
Kojto 101:7cff1c4259d7 1464 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
Kojto 101:7cff1c4259d7 1465 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
Kojto 101:7cff1c4259d7 1466 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
Kojto 101:7cff1c4259d7 1467 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
Kojto 101:7cff1c4259d7 1468 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
Kojto 101:7cff1c4259d7 1469 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
Kojto 101:7cff1c4259d7 1470 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
Kojto 101:7cff1c4259d7 1471 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
Kojto 101:7cff1c4259d7 1472 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
Kojto 101:7cff1c4259d7 1473 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
Kojto 101:7cff1c4259d7 1474 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
Kojto 101:7cff1c4259d7 1475 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
Kojto 101:7cff1c4259d7 1476 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
Kojto 101:7cff1c4259d7 1477 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
Kojto 101:7cff1c4259d7 1478 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
Kojto 101:7cff1c4259d7 1479 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
Kojto 101:7cff1c4259d7 1480 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
Kojto 101:7cff1c4259d7 1481 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
Kojto 101:7cff1c4259d7 1482
Kojto 101:7cff1c4259d7 1483 /****************** Bit definition for EXTI_FTSR register *******************/
Kojto 101:7cff1c4259d7 1484 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Kojto 101:7cff1c4259d7 1485 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
Kojto 101:7cff1c4259d7 1486 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
Kojto 101:7cff1c4259d7 1487 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
Kojto 101:7cff1c4259d7 1488 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
Kojto 101:7cff1c4259d7 1489 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
Kojto 101:7cff1c4259d7 1490 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
Kojto 101:7cff1c4259d7 1491 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
Kojto 101:7cff1c4259d7 1492 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
Kojto 101:7cff1c4259d7 1493 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
Kojto 101:7cff1c4259d7 1494 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
Kojto 101:7cff1c4259d7 1495 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
Kojto 101:7cff1c4259d7 1496 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
Kojto 101:7cff1c4259d7 1497 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
Kojto 101:7cff1c4259d7 1498 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
Kojto 101:7cff1c4259d7 1499 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
Kojto 101:7cff1c4259d7 1500 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
Kojto 101:7cff1c4259d7 1501 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
Kojto 101:7cff1c4259d7 1502 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
Kojto 101:7cff1c4259d7 1503 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
Kojto 101:7cff1c4259d7 1504 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
Kojto 101:7cff1c4259d7 1505 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
Kojto 101:7cff1c4259d7 1506 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
Kojto 101:7cff1c4259d7 1507
Kojto 101:7cff1c4259d7 1508 /****************** Bit definition for EXTI_SWIER register ******************/
Kojto 101:7cff1c4259d7 1509 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Kojto 101:7cff1c4259d7 1510 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
Kojto 101:7cff1c4259d7 1511 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
Kojto 101:7cff1c4259d7 1512 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
Kojto 101:7cff1c4259d7 1513 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
Kojto 101:7cff1c4259d7 1514 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
Kojto 101:7cff1c4259d7 1515 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
Kojto 101:7cff1c4259d7 1516 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
Kojto 101:7cff1c4259d7 1517 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
Kojto 101:7cff1c4259d7 1518 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
Kojto 101:7cff1c4259d7 1519 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
Kojto 101:7cff1c4259d7 1520 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
Kojto 101:7cff1c4259d7 1521 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
Kojto 101:7cff1c4259d7 1522 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
Kojto 101:7cff1c4259d7 1523 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
Kojto 101:7cff1c4259d7 1524 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
Kojto 101:7cff1c4259d7 1525 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
Kojto 101:7cff1c4259d7 1526 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
Kojto 101:7cff1c4259d7 1527 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
Kojto 101:7cff1c4259d7 1528 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
Kojto 101:7cff1c4259d7 1529 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
Kojto 101:7cff1c4259d7 1530 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
Kojto 101:7cff1c4259d7 1531 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
Kojto 101:7cff1c4259d7 1532
Kojto 101:7cff1c4259d7 1533 /******************* Bit definition for EXTI_PR register ********************/
Kojto 101:7cff1c4259d7 1534 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
Kojto 101:7cff1c4259d7 1535 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
Kojto 101:7cff1c4259d7 1536 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
Kojto 101:7cff1c4259d7 1537 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
Kojto 101:7cff1c4259d7 1538 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
Kojto 101:7cff1c4259d7 1539 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
Kojto 101:7cff1c4259d7 1540 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
Kojto 101:7cff1c4259d7 1541 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
Kojto 101:7cff1c4259d7 1542 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
Kojto 101:7cff1c4259d7 1543 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
Kojto 101:7cff1c4259d7 1544 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
Kojto 101:7cff1c4259d7 1545 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
Kojto 101:7cff1c4259d7 1546 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
Kojto 101:7cff1c4259d7 1547 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
Kojto 101:7cff1c4259d7 1548 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
Kojto 101:7cff1c4259d7 1549 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
Kojto 101:7cff1c4259d7 1550 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
Kojto 101:7cff1c4259d7 1551 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
Kojto 101:7cff1c4259d7 1552 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
Kojto 101:7cff1c4259d7 1553 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
Kojto 101:7cff1c4259d7 1554 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
Kojto 101:7cff1c4259d7 1555 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
Kojto 101:7cff1c4259d7 1556 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
Kojto 101:7cff1c4259d7 1557
Kojto 101:7cff1c4259d7 1558 /******************************************************************************/
Kojto 101:7cff1c4259d7 1559 /* */
Kojto 101:7cff1c4259d7 1560 /* FLASH */
Kojto 101:7cff1c4259d7 1561 /* */
Kojto 101:7cff1c4259d7 1562 /******************************************************************************/
Kojto 101:7cff1c4259d7 1563 /******************* Bits definition for FLASH_ACR register *****************/
Kojto 101:7cff1c4259d7 1564 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
Kojto 101:7cff1c4259d7 1565 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
Kojto 101:7cff1c4259d7 1566 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1567 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1568 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
Kojto 101:7cff1c4259d7 1569 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1570 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
Kojto 101:7cff1c4259d7 1571 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
Kojto 101:7cff1c4259d7 1572 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
Kojto 101:7cff1c4259d7 1573
Kojto 101:7cff1c4259d7 1574 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1575 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1576 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1577 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1578 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 1579 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
Kojto 101:7cff1c4259d7 1580 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
Kojto 101:7cff1c4259d7 1581
Kojto 101:7cff1c4259d7 1582 /******************* Bits definition for FLASH_SR register ******************/
Kojto 101:7cff1c4259d7 1583 #define FLASH_SR_EOP ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1584 #define FLASH_SR_SOP ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1585 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1586 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1587 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1588 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1589 #define FLASH_SR_BSY ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1590
Kojto 101:7cff1c4259d7 1591 /******************* Bits definition for FLASH_CR register ******************/
Kojto 101:7cff1c4259d7 1592 #define FLASH_CR_PG ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1593 #define FLASH_CR_SER ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1594 #define FLASH_CR_MER ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1595 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
Kojto 101:7cff1c4259d7 1596 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1597 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1598 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1599 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1600 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1601 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
Kojto 101:7cff1c4259d7 1602 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1603 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1604 #define FLASH_CR_STRT ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1605 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 1606 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
Kojto 101:7cff1c4259d7 1607
Kojto 101:7cff1c4259d7 1608 /******************* Bits definition for FLASH_OPTCR register ***************/
Kojto 101:7cff1c4259d7 1609 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1610 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1611 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1612 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1613 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
Kojto 101:7cff1c4259d7 1614
Kojto 101:7cff1c4259d7 1615 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1616 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1617 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1618 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
Kojto 101:7cff1c4259d7 1619 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1620 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1621 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1622 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1623 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 1624 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 1625 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 1626 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 1627 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
Kojto 101:7cff1c4259d7 1628 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1629 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 1630 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 1631 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 1632 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 1633 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 1634 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 1635 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 1636 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 1637 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 1638 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 1639 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 1640
Kojto 101:7cff1c4259d7 1641 /****************** Bits definition for FLASH_OPTCR1 register ***************/
Kojto 101:7cff1c4259d7 1642 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
Kojto 101:7cff1c4259d7 1643 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1644 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 1645 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 1646 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 1647 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 1648 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 1649 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 1650 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 1651 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 1652 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 1653 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 1654 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 1655
Kojto 101:7cff1c4259d7 1656 /******************************************************************************/
Kojto 101:7cff1c4259d7 1657 /* */
Kojto 101:7cff1c4259d7 1658 /* General Purpose I/O */
Kojto 101:7cff1c4259d7 1659 /* */
Kojto 101:7cff1c4259d7 1660 /******************************************************************************/
Kojto 101:7cff1c4259d7 1661 /****************** Bits definition for GPIO_MODER register *****************/
Kojto 101:7cff1c4259d7 1662 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto 101:7cff1c4259d7 1663 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1664 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1665
Kojto 101:7cff1c4259d7 1666 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto 101:7cff1c4259d7 1667 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1668 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1669
Kojto 101:7cff1c4259d7 1670 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto 101:7cff1c4259d7 1671 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1672 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1673
Kojto 101:7cff1c4259d7 1674 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto 101:7cff1c4259d7 1675 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1676 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1677
Kojto 101:7cff1c4259d7 1678 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto 101:7cff1c4259d7 1679 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1680 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1681
Kojto 101:7cff1c4259d7 1682 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto 101:7cff1c4259d7 1683 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1684 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1685
Kojto 101:7cff1c4259d7 1686 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto 101:7cff1c4259d7 1687 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 1688 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 1689
Kojto 101:7cff1c4259d7 1690 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto 101:7cff1c4259d7 1691 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 1692 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 1693
Kojto 101:7cff1c4259d7 1694 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto 101:7cff1c4259d7 1695 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1696 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 1697
Kojto 101:7cff1c4259d7 1698 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto 101:7cff1c4259d7 1699 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 1700 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 1701
Kojto 101:7cff1c4259d7 1702 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto 101:7cff1c4259d7 1703 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 1704 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 1705
Kojto 101:7cff1c4259d7 1706 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto 101:7cff1c4259d7 1707 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 1708 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 1709
Kojto 101:7cff1c4259d7 1710 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto 101:7cff1c4259d7 1711 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 1712 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 1713
Kojto 101:7cff1c4259d7 1714 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto 101:7cff1c4259d7 1715 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 1716 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 1717
Kojto 101:7cff1c4259d7 1718 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto 101:7cff1c4259d7 1719 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto 101:7cff1c4259d7 1720 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto 101:7cff1c4259d7 1721
Kojto 101:7cff1c4259d7 1722 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto 101:7cff1c4259d7 1723 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto 101:7cff1c4259d7 1724 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto 101:7cff1c4259d7 1725
Kojto 101:7cff1c4259d7 1726 /****************** Bits definition for GPIO_OTYPER register ****************/
Kojto 101:7cff1c4259d7 1727 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1728 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1729 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1730 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1731 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1732 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1733 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1734 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1735 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1736 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1737 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1738 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1739 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 1740 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 1741 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 1742 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 1743
Kojto 101:7cff1c4259d7 1744 /****************** Bits definition for GPIO_OSPEEDR register ***************/
Kojto 101:7cff1c4259d7 1745 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
Kojto 101:7cff1c4259d7 1746 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1747 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1748
Kojto 101:7cff1c4259d7 1749 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto 101:7cff1c4259d7 1750 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1751 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1752
Kojto 101:7cff1c4259d7 1753 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
Kojto 101:7cff1c4259d7 1754 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1755 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1756
Kojto 101:7cff1c4259d7 1757 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto 101:7cff1c4259d7 1758 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1759 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1760
Kojto 101:7cff1c4259d7 1761 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
Kojto 101:7cff1c4259d7 1762 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1763 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1764
Kojto 101:7cff1c4259d7 1765 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto 101:7cff1c4259d7 1766 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1767 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1768
Kojto 101:7cff1c4259d7 1769 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
Kojto 101:7cff1c4259d7 1770 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 1771 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 1772
Kojto 101:7cff1c4259d7 1773 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto 101:7cff1c4259d7 1774 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 1775 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 1776
Kojto 101:7cff1c4259d7 1777 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
Kojto 101:7cff1c4259d7 1778 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1779 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 1780
Kojto 101:7cff1c4259d7 1781 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto 101:7cff1c4259d7 1782 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 1783 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 1784
Kojto 101:7cff1c4259d7 1785 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
Kojto 101:7cff1c4259d7 1786 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 1787 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 1788
Kojto 101:7cff1c4259d7 1789 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto 101:7cff1c4259d7 1790 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 1791 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 1792
Kojto 101:7cff1c4259d7 1793 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
Kojto 101:7cff1c4259d7 1794 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 1795 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 1796
Kojto 101:7cff1c4259d7 1797 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto 101:7cff1c4259d7 1798 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 1799 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 1800
Kojto 101:7cff1c4259d7 1801 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
Kojto 101:7cff1c4259d7 1802 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto 101:7cff1c4259d7 1803 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto 101:7cff1c4259d7 1804
Kojto 101:7cff1c4259d7 1805 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto 101:7cff1c4259d7 1806 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto 101:7cff1c4259d7 1807 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto 101:7cff1c4259d7 1808
Kojto 101:7cff1c4259d7 1809 /****************** Bits definition for GPIO_PUPDR register *****************/
Kojto 101:7cff1c4259d7 1810 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto 101:7cff1c4259d7 1811 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1812 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1813
Kojto 101:7cff1c4259d7 1814 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto 101:7cff1c4259d7 1815 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1816 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1817
Kojto 101:7cff1c4259d7 1818 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto 101:7cff1c4259d7 1819 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1820 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1821
Kojto 101:7cff1c4259d7 1822 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto 101:7cff1c4259d7 1823 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1824 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1825
Kojto 101:7cff1c4259d7 1826 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto 101:7cff1c4259d7 1827 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1828 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1829
Kojto 101:7cff1c4259d7 1830 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto 101:7cff1c4259d7 1831 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1832 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1833
Kojto 101:7cff1c4259d7 1834 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto 101:7cff1c4259d7 1835 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 1836 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 1837
Kojto 101:7cff1c4259d7 1838 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto 101:7cff1c4259d7 1839 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 1840 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 1841
Kojto 101:7cff1c4259d7 1842 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto 101:7cff1c4259d7 1843 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1844 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 1845
Kojto 101:7cff1c4259d7 1846 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto 101:7cff1c4259d7 1847 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 1848 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 1849
Kojto 101:7cff1c4259d7 1850 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto 101:7cff1c4259d7 1851 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 1852 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 1853
Kojto 101:7cff1c4259d7 1854 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto 101:7cff1c4259d7 1855 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 1856 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 1857
Kojto 101:7cff1c4259d7 1858 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto 101:7cff1c4259d7 1859 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 1860 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 1861
Kojto 101:7cff1c4259d7 1862 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto 101:7cff1c4259d7 1863 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 1864 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 1865
Kojto 101:7cff1c4259d7 1866 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto 101:7cff1c4259d7 1867 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto 101:7cff1c4259d7 1868 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto 101:7cff1c4259d7 1869
Kojto 101:7cff1c4259d7 1870 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto 101:7cff1c4259d7 1871 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto 101:7cff1c4259d7 1872 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto 101:7cff1c4259d7 1873
Kojto 101:7cff1c4259d7 1874 /****************** Bits definition for GPIO_IDR register *******************/
Kojto 101:7cff1c4259d7 1875 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1876 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1877 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1878 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1879 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1880 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1881 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1882 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1883 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1884 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1885 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1886 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1887 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 1888 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 1889 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 1890 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 1891 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
Kojto 101:7cff1c4259d7 1892 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
Kojto 101:7cff1c4259d7 1893 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
Kojto 101:7cff1c4259d7 1894 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
Kojto 101:7cff1c4259d7 1895 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
Kojto 101:7cff1c4259d7 1896 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
Kojto 101:7cff1c4259d7 1897 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
Kojto 101:7cff1c4259d7 1898 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
Kojto 101:7cff1c4259d7 1899 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
Kojto 101:7cff1c4259d7 1900 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
Kojto 101:7cff1c4259d7 1901 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
Kojto 101:7cff1c4259d7 1902 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
Kojto 101:7cff1c4259d7 1903 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
Kojto 101:7cff1c4259d7 1904 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
Kojto 101:7cff1c4259d7 1905 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
Kojto 101:7cff1c4259d7 1906 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
Kojto 101:7cff1c4259d7 1907 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
Kojto 101:7cff1c4259d7 1908
Kojto 101:7cff1c4259d7 1909 /****************** Bits definition for GPIO_ODR register *******************/
Kojto 101:7cff1c4259d7 1910 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1911 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1912 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1913 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1914 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1915 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1916 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1917 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1918 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1919 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1920 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1921 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1922 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 1923 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 1924 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 1925 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 1926 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
Kojto 101:7cff1c4259d7 1927 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
Kojto 101:7cff1c4259d7 1928 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
Kojto 101:7cff1c4259d7 1929 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
Kojto 101:7cff1c4259d7 1930 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
Kojto 101:7cff1c4259d7 1931 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
Kojto 101:7cff1c4259d7 1932 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
Kojto 101:7cff1c4259d7 1933 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
Kojto 101:7cff1c4259d7 1934 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
Kojto 101:7cff1c4259d7 1935 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
Kojto 101:7cff1c4259d7 1936 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
Kojto 101:7cff1c4259d7 1937 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
Kojto 101:7cff1c4259d7 1938 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
Kojto 101:7cff1c4259d7 1939 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
Kojto 101:7cff1c4259d7 1940 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
Kojto 101:7cff1c4259d7 1941 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
Kojto 101:7cff1c4259d7 1942 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
Kojto 101:7cff1c4259d7 1943
Kojto 101:7cff1c4259d7 1944 /****************** Bits definition for GPIO_BSRR register ******************/
Kojto 101:7cff1c4259d7 1945 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1946 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1947 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1948 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1949 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1950 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1951 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1952 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1953 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1954 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1955 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1956 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1957 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 1958 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 1959 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 1960 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 1961 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1962 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 1963 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 1964 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 1965 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 1966 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 1967 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 1968 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 1969 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 1970 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 1971 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 1972 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 1973 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto 101:7cff1c4259d7 1974 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto 101:7cff1c4259d7 1975 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto 101:7cff1c4259d7 1976 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto 101:7cff1c4259d7 1977
Kojto 101:7cff1c4259d7 1978 /****************** Bit definition for GPIO_LCKR register *********************/
Kojto 101:7cff1c4259d7 1979 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 1980 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 1981 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 1982 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 1983 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 1984 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 1985 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 1986 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 1987 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 1988 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 1989 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 1990 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 1991 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 1992 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 1993 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 1994 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 1995 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 1996
Kojto 101:7cff1c4259d7 1997 /******************************************************************************/
Kojto 101:7cff1c4259d7 1998 /* */
Kojto 101:7cff1c4259d7 1999 /* Inter-integrated Circuit Interface */
Kojto 101:7cff1c4259d7 2000 /* */
Kojto 101:7cff1c4259d7 2001 /******************************************************************************/
Kojto 101:7cff1c4259d7 2002 /******************* Bit definition for I2C_CR1 register ********************/
Kojto 101:7cff1c4259d7 2003 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
Kojto 101:7cff1c4259d7 2004 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
Kojto 101:7cff1c4259d7 2005 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
Kojto 101:7cff1c4259d7 2006 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
Kojto 101:7cff1c4259d7 2007 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
Kojto 101:7cff1c4259d7 2008 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
Kojto 101:7cff1c4259d7 2009 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
Kojto 101:7cff1c4259d7 2010 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
Kojto 101:7cff1c4259d7 2011 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
Kojto 101:7cff1c4259d7 2012 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
Kojto 101:7cff1c4259d7 2013 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
Kojto 101:7cff1c4259d7 2014 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
Kojto 101:7cff1c4259d7 2015 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
Kojto 101:7cff1c4259d7 2016 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
Kojto 101:7cff1c4259d7 2017
Kojto 101:7cff1c4259d7 2018 /******************* Bit definition for I2C_CR2 register ********************/
Kojto 101:7cff1c4259d7 2019 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
Kojto 101:7cff1c4259d7 2020 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 2021 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 2022 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 2023 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 2024 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 2025 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 2026
Kojto 101:7cff1c4259d7 2027 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
Kojto 101:7cff1c4259d7 2028 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
Kojto 101:7cff1c4259d7 2029 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
Kojto 101:7cff1c4259d7 2030 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
Kojto 101:7cff1c4259d7 2031 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
Kojto 101:7cff1c4259d7 2032
Kojto 101:7cff1c4259d7 2033 /******************* Bit definition for I2C_OAR1 register *******************/
Kojto 101:7cff1c4259d7 2034 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
Kojto 101:7cff1c4259d7 2035 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
Kojto 101:7cff1c4259d7 2036
Kojto 101:7cff1c4259d7 2037 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 2038 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 2039 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 2040 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 2041 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 2042 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 2043 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 2044 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 101:7cff1c4259d7 2045 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
Kojto 101:7cff1c4259d7 2046 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
Kojto 101:7cff1c4259d7 2047
Kojto 101:7cff1c4259d7 2048 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
Kojto 101:7cff1c4259d7 2049
Kojto 101:7cff1c4259d7 2050 /******************* Bit definition for I2C_OAR2 register *******************/
Kojto 101:7cff1c4259d7 2051 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
Kojto 101:7cff1c4259d7 2052 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
Kojto 101:7cff1c4259d7 2053
Kojto 101:7cff1c4259d7 2054 /******************** Bit definition for I2C_DR register ********************/
Kojto 101:7cff1c4259d7 2055 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
Kojto 101:7cff1c4259d7 2056
Kojto 101:7cff1c4259d7 2057 /******************* Bit definition for I2C_SR1 register ********************/
Kojto 101:7cff1c4259d7 2058 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
Kojto 101:7cff1c4259d7 2059 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
Kojto 101:7cff1c4259d7 2060 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
Kojto 101:7cff1c4259d7 2061 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
Kojto 101:7cff1c4259d7 2062 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
Kojto 101:7cff1c4259d7 2063 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
Kojto 101:7cff1c4259d7 2064 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
Kojto 101:7cff1c4259d7 2065 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
Kojto 101:7cff1c4259d7 2066 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
Kojto 101:7cff1c4259d7 2067 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
Kojto 101:7cff1c4259d7 2068 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
Kojto 101:7cff1c4259d7 2069 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
Kojto 101:7cff1c4259d7 2070 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
Kojto 101:7cff1c4259d7 2071 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
Kojto 101:7cff1c4259d7 2072
Kojto 101:7cff1c4259d7 2073 /******************* Bit definition for I2C_SR2 register ********************/
Kojto 101:7cff1c4259d7 2074 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
Kojto 101:7cff1c4259d7 2075 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
Kojto 101:7cff1c4259d7 2076 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
Kojto 101:7cff1c4259d7 2077 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
Kojto 101:7cff1c4259d7 2078 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
Kojto 101:7cff1c4259d7 2079 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
Kojto 101:7cff1c4259d7 2080 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
Kojto 101:7cff1c4259d7 2081 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
Kojto 101:7cff1c4259d7 2082
Kojto 101:7cff1c4259d7 2083 /******************* Bit definition for I2C_CCR register ********************/
Kojto 101:7cff1c4259d7 2084 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
Kojto 101:7cff1c4259d7 2085 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
Kojto 101:7cff1c4259d7 2086 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
Kojto 101:7cff1c4259d7 2087
Kojto 101:7cff1c4259d7 2088 /****************** Bit definition for I2C_TRISE register *******************/
Kojto 101:7cff1c4259d7 2089 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
Kojto 101:7cff1c4259d7 2090
Kojto 101:7cff1c4259d7 2091 /****************** Bit definition for I2C_FLTR register *******************/
Kojto 101:7cff1c4259d7 2092 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
Kojto 101:7cff1c4259d7 2093 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
Kojto 101:7cff1c4259d7 2094
Kojto 101:7cff1c4259d7 2095 /******************************************************************************/
Kojto 101:7cff1c4259d7 2096 /* */
Kojto 101:7cff1c4259d7 2097 /* Independent WATCHDOG */
Kojto 101:7cff1c4259d7 2098 /* */
Kojto 101:7cff1c4259d7 2099 /******************************************************************************/
Kojto 101:7cff1c4259d7 2100 /******************* Bit definition for IWDG_KR register ********************/
Kojto 101:7cff1c4259d7 2101 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
Kojto 101:7cff1c4259d7 2102
Kojto 101:7cff1c4259d7 2103 /******************* Bit definition for IWDG_PR register ********************/
Kojto 101:7cff1c4259d7 2104 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
Kojto 101:7cff1c4259d7 2105 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 2106 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 2107 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 2108
Kojto 101:7cff1c4259d7 2109 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 101:7cff1c4259d7 2110 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
Kojto 101:7cff1c4259d7 2111
Kojto 101:7cff1c4259d7 2112 /******************* Bit definition for IWDG_SR register ********************/
Kojto 101:7cff1c4259d7 2113 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
Kojto 101:7cff1c4259d7 2114 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
Kojto 101:7cff1c4259d7 2115
Kojto 101:7cff1c4259d7 2116
Kojto 101:7cff1c4259d7 2117 /******************************************************************************/
Kojto 101:7cff1c4259d7 2118 /* */
Kojto 101:7cff1c4259d7 2119 /* Power Control */
Kojto 101:7cff1c4259d7 2120 /* */
Kojto 101:7cff1c4259d7 2121 /******************************************************************************/
Kojto 101:7cff1c4259d7 2122 /******************** Bit definition for PWR_CR register ********************/
Kojto 101:7cff1c4259d7 2123 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
Kojto 101:7cff1c4259d7 2124 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
Kojto 101:7cff1c4259d7 2125 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
Kojto 101:7cff1c4259d7 2126 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
Kojto 101:7cff1c4259d7 2127 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
Kojto 101:7cff1c4259d7 2128
Kojto 101:7cff1c4259d7 2129 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 101:7cff1c4259d7 2130 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 101:7cff1c4259d7 2131 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 101:7cff1c4259d7 2132 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 101:7cff1c4259d7 2133
Kojto 101:7cff1c4259d7 2134 /*!< PVD level configuration */
Kojto 101:7cff1c4259d7 2135 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
Kojto 101:7cff1c4259d7 2136 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
Kojto 101:7cff1c4259d7 2137 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
Kojto 101:7cff1c4259d7 2138 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
Kojto 101:7cff1c4259d7 2139 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
Kojto 101:7cff1c4259d7 2140 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
Kojto 101:7cff1c4259d7 2141 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
Kojto 101:7cff1c4259d7 2142 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
Kojto 101:7cff1c4259d7 2143
Kojto 101:7cff1c4259d7 2144 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
Kojto 101:7cff1c4259d7 2145 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
Kojto 101:7cff1c4259d7 2146 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
Kojto 101:7cff1c4259d7 2147 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
Kojto 101:7cff1c4259d7 2148 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
Kojto 101:7cff1c4259d7 2149
Kojto 101:7cff1c4259d7 2150 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
Kojto 101:7cff1c4259d7 2151 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 101:7cff1c4259d7 2152 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 101:7cff1c4259d7 2153
Kojto 101:7cff1c4259d7 2154 #define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
Kojto 101:7cff1c4259d7 2155 #define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
Kojto 101:7cff1c4259d7 2156 /* Legacy define */
Kojto 101:7cff1c4259d7 2157 #define PWR_CR_PMODE PWR_CR_VOS
Kojto 101:7cff1c4259d7 2158
Kojto 101:7cff1c4259d7 2159 /******************* Bit definition for PWR_CSR register ********************/
Kojto 101:7cff1c4259d7 2160 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
Kojto 101:7cff1c4259d7 2161 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
Kojto 101:7cff1c4259d7 2162 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
Kojto 101:7cff1c4259d7 2163 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
Kojto 101:7cff1c4259d7 2164 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
Kojto 101:7cff1c4259d7 2165 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
Kojto 101:7cff1c4259d7 2166 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
Kojto 101:7cff1c4259d7 2167
Kojto 101:7cff1c4259d7 2168 /* Legacy define */
Kojto 101:7cff1c4259d7 2169 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
Kojto 101:7cff1c4259d7 2170
Kojto 101:7cff1c4259d7 2171 /******************************************************************************/
Kojto 101:7cff1c4259d7 2172 /* */
Kojto 101:7cff1c4259d7 2173 /* Reset and Clock Control */
Kojto 101:7cff1c4259d7 2174 /* */
Kojto 101:7cff1c4259d7 2175 /******************************************************************************/
Kojto 101:7cff1c4259d7 2176 /******************** Bit definition for RCC_CR register ********************/
Kojto 101:7cff1c4259d7 2177 #define RCC_CR_HSION ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2178 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2179
Kojto 101:7cff1c4259d7 2180 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
Kojto 101:7cff1c4259d7 2181 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
Kojto 101:7cff1c4259d7 2182 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
Kojto 101:7cff1c4259d7 2183 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
Kojto 101:7cff1c4259d7 2184 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
Kojto 101:7cff1c4259d7 2185 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
Kojto 101:7cff1c4259d7 2186
Kojto 101:7cff1c4259d7 2187 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
Kojto 101:7cff1c4259d7 2188 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
Kojto 101:7cff1c4259d7 2189 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
Kojto 101:7cff1c4259d7 2190 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
Kojto 101:7cff1c4259d7 2191 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
Kojto 101:7cff1c4259d7 2192 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
Kojto 101:7cff1c4259d7 2193 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
Kojto 101:7cff1c4259d7 2194 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
Kojto 101:7cff1c4259d7 2195 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
Kojto 101:7cff1c4259d7 2196
Kojto 101:7cff1c4259d7 2197 #define RCC_CR_HSEON ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2198 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2199 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2200 #define RCC_CR_CSSON ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 2201 #define RCC_CR_PLLON ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 2202 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 2203 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 2204 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 2205
Kojto 101:7cff1c4259d7 2206 /******************** Bit definition for RCC_PLLCFGR register ***************/
Kojto 101:7cff1c4259d7 2207 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
Kojto 101:7cff1c4259d7 2208 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2209 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2210 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2211 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2212 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2213 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2214
Kojto 101:7cff1c4259d7 2215 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
Kojto 101:7cff1c4259d7 2216 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 2217 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2218 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2219 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2220 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 2221 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2222 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2223 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2224 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2225
Kojto 101:7cff1c4259d7 2226 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
Kojto 101:7cff1c4259d7 2227 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2228 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2229
Kojto 101:7cff1c4259d7 2230 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2231 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2232 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
Kojto 101:7cff1c4259d7 2233
Kojto 101:7cff1c4259d7 2234 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
Kojto 101:7cff1c4259d7 2235 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 2236 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 2237 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 2238 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 2239
Kojto 101:7cff1c4259d7 2240 /******************** Bit definition for RCC_CFGR register ******************/
Kojto 101:7cff1c4259d7 2241 /*!< SW configuration */
Kojto 101:7cff1c4259d7 2242 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
Kojto 101:7cff1c4259d7 2243 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 101:7cff1c4259d7 2244 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 101:7cff1c4259d7 2245
Kojto 101:7cff1c4259d7 2246 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
Kojto 101:7cff1c4259d7 2247 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
Kojto 101:7cff1c4259d7 2248 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
Kojto 101:7cff1c4259d7 2249
Kojto 101:7cff1c4259d7 2250 /*!< SWS configuration */
Kojto 101:7cff1c4259d7 2251 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 101:7cff1c4259d7 2252 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 101:7cff1c4259d7 2253 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 101:7cff1c4259d7 2254
Kojto 101:7cff1c4259d7 2255 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
Kojto 101:7cff1c4259d7 2256 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
Kojto 101:7cff1c4259d7 2257 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
Kojto 101:7cff1c4259d7 2258
Kojto 101:7cff1c4259d7 2259 /*!< HPRE configuration */
Kojto 101:7cff1c4259d7 2260 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 101:7cff1c4259d7 2261 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 101:7cff1c4259d7 2262 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 101:7cff1c4259d7 2263 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 101:7cff1c4259d7 2264 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Kojto 101:7cff1c4259d7 2265
Kojto 101:7cff1c4259d7 2266 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
Kojto 101:7cff1c4259d7 2267 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
Kojto 101:7cff1c4259d7 2268 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
Kojto 101:7cff1c4259d7 2269 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
Kojto 101:7cff1c4259d7 2270 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
Kojto 101:7cff1c4259d7 2271 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
Kojto 101:7cff1c4259d7 2272 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
Kojto 101:7cff1c4259d7 2273 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
Kojto 101:7cff1c4259d7 2274 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
Kojto 101:7cff1c4259d7 2275
Kojto 101:7cff1c4259d7 2276 /*!< PPRE1 configuration */
Kojto 101:7cff1c4259d7 2277 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 101:7cff1c4259d7 2278 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 101:7cff1c4259d7 2279 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 101:7cff1c4259d7 2280 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 101:7cff1c4259d7 2281
Kojto 101:7cff1c4259d7 2282 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 101:7cff1c4259d7 2283 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
Kojto 101:7cff1c4259d7 2284 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
Kojto 101:7cff1c4259d7 2285 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
Kojto 101:7cff1c4259d7 2286 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
Kojto 101:7cff1c4259d7 2287
Kojto 101:7cff1c4259d7 2288 /*!< PPRE2 configuration */
Kojto 101:7cff1c4259d7 2289 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 101:7cff1c4259d7 2290 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
Kojto 101:7cff1c4259d7 2291 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
Kojto 101:7cff1c4259d7 2292 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
Kojto 101:7cff1c4259d7 2293
Kojto 101:7cff1c4259d7 2294 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 101:7cff1c4259d7 2295 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
Kojto 101:7cff1c4259d7 2296 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
Kojto 101:7cff1c4259d7 2297 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
Kojto 101:7cff1c4259d7 2298 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
Kojto 101:7cff1c4259d7 2299
Kojto 101:7cff1c4259d7 2300 /*!< RTCPRE configuration */
Kojto 101:7cff1c4259d7 2301 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
Kojto 101:7cff1c4259d7 2302 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2303 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2304 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2305 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 2306 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 2307
Kojto 101:7cff1c4259d7 2308 /*!< MCO1 configuration */
Kojto 101:7cff1c4259d7 2309 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
Kojto 101:7cff1c4259d7 2310 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2311 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2312
Kojto 101:7cff1c4259d7 2313 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 2314
Kojto 101:7cff1c4259d7 2315 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
Kojto 101:7cff1c4259d7 2316 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 2317 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 2318 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 2319
Kojto 101:7cff1c4259d7 2320 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
Kojto 101:7cff1c4259d7 2321 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 2322 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
Kojto 101:7cff1c4259d7 2323 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
Kojto 101:7cff1c4259d7 2324
Kojto 101:7cff1c4259d7 2325 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
Kojto 101:7cff1c4259d7 2326 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
Kojto 101:7cff1c4259d7 2327 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
Kojto 101:7cff1c4259d7 2328
Kojto 101:7cff1c4259d7 2329 /******************** Bit definition for RCC_CIR register *******************/
Kojto 101:7cff1c4259d7 2330 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2331 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2332 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2333 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2334 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2335 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2336
Kojto 101:7cff1c4259d7 2337 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2338 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2339 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2340 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 2341 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2342 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2343 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2344
Kojto 101:7cff1c4259d7 2345 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2346 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2347 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2348 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 2349 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 2350 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2351
Kojto 101:7cff1c4259d7 2352 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 2353
Kojto 101:7cff1c4259d7 2354 /******************** Bit definition for RCC_AHB1RSTR register **************/
Kojto 101:7cff1c4259d7 2355 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2356 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2357 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2358 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2359 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2360 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2361 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2362 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2363 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2364
Kojto 101:7cff1c4259d7 2365 /******************** Bit definition for RCC_AHB2RSTR register **************/
Kojto 101:7cff1c4259d7 2366 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2367
Kojto 101:7cff1c4259d7 2368 /******************** Bit definition for RCC_AHB3RSTR register **************/
Kojto 101:7cff1c4259d7 2369
Kojto 101:7cff1c4259d7 2370 /******************** Bit definition for RCC_APB1RSTR register **************/
Kojto 101:7cff1c4259d7 2371 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2372 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2373 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2374 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2375 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2376 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2377 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 2378 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2379 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2380 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2381 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 2382 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
Kojto 101:7cff1c4259d7 2383
Kojto 101:7cff1c4259d7 2384 /******************** Bit definition for RCC_APB2RSTR register **************/
Kojto 101:7cff1c4259d7 2385 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2386 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2387 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2388 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2389 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2390 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2391 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2392 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2393 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2394 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2395 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2396 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 2397
Kojto 101:7cff1c4259d7 2398 /* Old SPI1RST bit definition, maintained for legacy purpose */
Kojto 101:7cff1c4259d7 2399 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
Kojto 101:7cff1c4259d7 2400
Kojto 101:7cff1c4259d7 2401 /******************** Bit definition for RCC_AHB1ENR register ***************/
Kojto 101:7cff1c4259d7 2402 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2403 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2404 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2405 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2406 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2407 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2408 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2409 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2410 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 2411 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2412 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2413
Kojto 101:7cff1c4259d7 2414 /******************** Bit definition for RCC_AHB2ENR register ***************/
Kojto 101:7cff1c4259d7 2415 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2416
Kojto 101:7cff1c4259d7 2417 /******************** Bit definition for RCC_AHB3ENR register ***************/
Kojto 101:7cff1c4259d7 2418
Kojto 101:7cff1c4259d7 2419 /******************** Bit definition for RCC_APB1ENR register ***************/
Kojto 101:7cff1c4259d7 2420 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2421 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2422 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2423 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2424 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2425 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2426 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 2427 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2428 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2429 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2430 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 2431 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
Kojto 101:7cff1c4259d7 2432
Kojto 101:7cff1c4259d7 2433 /******************** Bit definition for RCC_APB2ENR register ***************/
Kojto 101:7cff1c4259d7 2434 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2435 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2436 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2437 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2438 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2439 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2440 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2441 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2442 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2443 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2444 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2445 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 2446
Kojto 101:7cff1c4259d7 2447 /******************** Bit definition for RCC_AHB1LPENR register *************/
Kojto 101:7cff1c4259d7 2448 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2449 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2450 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2451 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2452 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2453 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2454 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2455 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 2456 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2457 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2458 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2459 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 2460 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2461 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2462
Kojto 101:7cff1c4259d7 2463 /******************** Bit definition for RCC_AHB2LPENR register *************/
Kojto 101:7cff1c4259d7 2464 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2465
Kojto 101:7cff1c4259d7 2466 /******************** Bit definition for RCC_AHB3LPENR register *************/
Kojto 101:7cff1c4259d7 2467
Kojto 101:7cff1c4259d7 2468 /******************** Bit definition for RCC_APB1LPENR register *************/
Kojto 101:7cff1c4259d7 2469 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2470 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2471 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2472 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2473 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2474 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2475 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 2476 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2477 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2478 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2479 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 2480 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
Kojto 101:7cff1c4259d7 2481 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
Kojto 101:7cff1c4259d7 2482
Kojto 101:7cff1c4259d7 2483 /******************** Bit definition for RCC_APB2LPENR register *************/
Kojto 101:7cff1c4259d7 2484 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2485 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2486 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2487 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2488 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2489 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2490 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2491 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2492 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2493 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2494 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2495 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 2496
Kojto 101:7cff1c4259d7 2497 /******************** Bit definition for RCC_BDCR register ******************/
Kojto 101:7cff1c4259d7 2498 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2499 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2500 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2501 #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2502
Kojto 101:7cff1c4259d7 2503 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
Kojto 101:7cff1c4259d7 2504 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2505 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2506
Kojto 101:7cff1c4259d7 2507 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 2508 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2509
Kojto 101:7cff1c4259d7 2510 /******************** Bit definition for RCC_CSR register *******************/
Kojto 101:7cff1c4259d7 2511 #define RCC_CSR_LSION ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2512 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2513 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 2514 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 2515 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 2516 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 2517 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
Kojto 101:7cff1c4259d7 2518 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
Kojto 101:7cff1c4259d7 2519 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
Kojto 101:7cff1c4259d7 2520 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
Kojto 101:7cff1c4259d7 2521
Kojto 101:7cff1c4259d7 2522 /******************** Bit definition for RCC_SSCGR register *****************/
Kojto 101:7cff1c4259d7 2523 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
Kojto 101:7cff1c4259d7 2524 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
Kojto 101:7cff1c4259d7 2525 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
Kojto 101:7cff1c4259d7 2526 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
Kojto 101:7cff1c4259d7 2527
Kojto 101:7cff1c4259d7 2528 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
Kojto 101:7cff1c4259d7 2529 #define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
Kojto 101:7cff1c4259d7 2530 #define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2531 #define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2532 #define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2533 #define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2534 #define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2535 #define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2536
Kojto 101:7cff1c4259d7 2537 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
Kojto 101:7cff1c4259d7 2538 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 2539 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2540 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2541 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2542 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 2543 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2544 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2545 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2546 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2547
Kojto 101:7cff1c4259d7 2548 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
Kojto 101:7cff1c4259d7 2549 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
Kojto 101:7cff1c4259d7 2550 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
Kojto 101:7cff1c4259d7 2551 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
Kojto 101:7cff1c4259d7 2552
Kojto 101:7cff1c4259d7 2553
Kojto 101:7cff1c4259d7 2554 /******************************************************************************/
Kojto 101:7cff1c4259d7 2555 /* */
Kojto 101:7cff1c4259d7 2556 /* Real-Time Clock (RTC) */
Kojto 101:7cff1c4259d7 2557 /* */
Kojto 101:7cff1c4259d7 2558 /******************************************************************************/
Kojto 101:7cff1c4259d7 2559 /******************** Bits definition for RTC_TR register *******************/
Kojto 101:7cff1c4259d7 2560 #define RTC_TR_PM ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2561 #define RTC_TR_HT ((uint32_t)0x00300000)
Kojto 101:7cff1c4259d7 2562 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 2563 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2564 #define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto 101:7cff1c4259d7 2565 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2566 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2567 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2568 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 2569 #define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto 101:7cff1c4259d7 2570 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2571 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2572 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2573 #define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto 101:7cff1c4259d7 2574 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2575 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2576 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 2577 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2578 #define RTC_TR_ST ((uint32_t)0x00000070)
Kojto 101:7cff1c4259d7 2579 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2580 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2581 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 2582 #define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto 101:7cff1c4259d7 2583 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2584 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2585 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2586 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2587
Kojto 101:7cff1c4259d7 2588 /******************** Bits definition for RTC_DR register *******************/
Kojto 101:7cff1c4259d7 2589 #define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto 101:7cff1c4259d7 2590 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 2591 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2592 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2593 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 2594 #define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto 101:7cff1c4259d7 2595 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2596 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2597 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2598 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 2599 #define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto 101:7cff1c4259d7 2600 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2601 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2602 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 2603 #define RTC_DR_MT ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2604 #define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto 101:7cff1c4259d7 2605 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2606 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2607 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 2608 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2609 #define RTC_DR_DT ((uint32_t)0x00000030)
Kojto 101:7cff1c4259d7 2610 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2611 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2612 #define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto 101:7cff1c4259d7 2613 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2614 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2615 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2616 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2617
Kojto 101:7cff1c4259d7 2618 /******************** Bits definition for RTC_CR register *******************/
Kojto 101:7cff1c4259d7 2619 #define RTC_CR_COE ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 2620 #define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto 101:7cff1c4259d7 2621 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2622 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2623 #define RTC_CR_POL ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 2624 #define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 2625 #define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2626 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2627 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2628 #define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 2629 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2630 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2631 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2632 #define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2633 #define RTC_CR_WUTE ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 2634 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2635 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2636 #define RTC_CR_DCE ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2637 #define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 2638 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2639 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2640 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2641 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
Kojto 101:7cff1c4259d7 2642 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2643 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2644 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2645
Kojto 101:7cff1c4259d7 2646 /******************** Bits definition for RTC_ISR register ******************/
Kojto 101:7cff1c4259d7 2647 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2648 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2649 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2650 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2651 #define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2652 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 2653 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2654 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2655 #define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2656 #define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 2657 #define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2658 #define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2659 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2660 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2661 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2662 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2663
Kojto 101:7cff1c4259d7 2664 /******************** Bits definition for RTC_PRER register *****************/
Kojto 101:7cff1c4259d7 2665 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto 101:7cff1c4259d7 2666 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
Kojto 101:7cff1c4259d7 2667
Kojto 101:7cff1c4259d7 2668 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 101:7cff1c4259d7 2669 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
Kojto 101:7cff1c4259d7 2670
Kojto 101:7cff1c4259d7 2671 /******************** Bits definition for RTC_CALIBR register ***************/
Kojto 101:7cff1c4259d7 2672 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2673 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
Kojto 101:7cff1c4259d7 2674
Kojto 101:7cff1c4259d7 2675 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 101:7cff1c4259d7 2676 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto 101:7cff1c4259d7 2677 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto 101:7cff1c4259d7 2678 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto 101:7cff1c4259d7 2679 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto 101:7cff1c4259d7 2680 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto 101:7cff1c4259d7 2681 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto 101:7cff1c4259d7 2682 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 2683 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 2684 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 2685 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 2686 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 2687 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2688 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto 101:7cff1c4259d7 2689 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 2690 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2691 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto 101:7cff1c4259d7 2692 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2693 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2694 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2695 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 2696 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 2697 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto 101:7cff1c4259d7 2698 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2699 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2700 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2701 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto 101:7cff1c4259d7 2702 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2703 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2704 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 2705 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2706 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2707 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto 101:7cff1c4259d7 2708 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2709 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2710 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 2711 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto 101:7cff1c4259d7 2712 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2713 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2714 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2715 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2716
Kojto 101:7cff1c4259d7 2717 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 101:7cff1c4259d7 2718 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
Kojto 101:7cff1c4259d7 2719 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
Kojto 101:7cff1c4259d7 2720 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
Kojto 101:7cff1c4259d7 2721 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
Kojto 101:7cff1c4259d7 2722 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
Kojto 101:7cff1c4259d7 2723 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
Kojto 101:7cff1c4259d7 2724 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 2725 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 2726 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 2727 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 2728 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 2729 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2730 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
Kojto 101:7cff1c4259d7 2731 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 2732 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2733 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
Kojto 101:7cff1c4259d7 2734 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2735 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2736 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2737 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 2738 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 2739 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
Kojto 101:7cff1c4259d7 2740 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2741 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2742 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2743 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
Kojto 101:7cff1c4259d7 2744 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2745 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2746 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 2747 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2748 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2749 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
Kojto 101:7cff1c4259d7 2750 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2751 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2752 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 2753 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
Kojto 101:7cff1c4259d7 2754 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2755 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2756 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2757 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2758
Kojto 101:7cff1c4259d7 2759 /******************** Bits definition for RTC_WPR register ******************/
Kojto 101:7cff1c4259d7 2760 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto 101:7cff1c4259d7 2761
Kojto 101:7cff1c4259d7 2762 /******************** Bits definition for RTC_SSR register ******************/
Kojto 101:7cff1c4259d7 2763 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto 101:7cff1c4259d7 2764
Kojto 101:7cff1c4259d7 2765 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 101:7cff1c4259d7 2766 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto 101:7cff1c4259d7 2767 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto 101:7cff1c4259d7 2768
Kojto 101:7cff1c4259d7 2769 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 101:7cff1c4259d7 2770 #define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 2771 #define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto 101:7cff1c4259d7 2772 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto 101:7cff1c4259d7 2773 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 2774 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto 101:7cff1c4259d7 2775 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2776 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2777 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2778 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto 101:7cff1c4259d7 2779 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto 101:7cff1c4259d7 2780 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2781 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2782 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2783 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto 101:7cff1c4259d7 2784 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2785 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2786 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 2787 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2788 #define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto 101:7cff1c4259d7 2789 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2790 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2791 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 2792 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto 101:7cff1c4259d7 2793 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2794 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2795 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2796 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2797
Kojto 101:7cff1c4259d7 2798 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 101:7cff1c4259d7 2799 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto 101:7cff1c4259d7 2800 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2801 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2802 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 2803 #define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2804 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto 101:7cff1c4259d7 2805 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2806 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2807 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 2808 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2809 #define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto 101:7cff1c4259d7 2810 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2811 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2812 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto 101:7cff1c4259d7 2813 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2814 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2815 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2816 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2817
Kojto 101:7cff1c4259d7 2818 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 101:7cff1c4259d7 2819 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto 101:7cff1c4259d7 2820
Kojto 101:7cff1c4259d7 2821 /******************** Bits definition for RTC_CAL register *****************/
Kojto 101:7cff1c4259d7 2822 #define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 2823 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2824 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2825 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto 101:7cff1c4259d7 2826 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2827 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2828 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2829 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2830 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2831 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 2832 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 2833 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2834 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2835
Kojto 101:7cff1c4259d7 2836 /******************** Bits definition for RTC_TAFCR register ****************/
Kojto 101:7cff1c4259d7 2837 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 2838 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 2839 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 2840 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto 101:7cff1c4259d7 2841 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto 101:7cff1c4259d7 2842 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto 101:7cff1c4259d7 2843 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto 101:7cff1c4259d7 2844 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Kojto 101:7cff1c4259d7 2845 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 2846 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 2847 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto 101:7cff1c4259d7 2848 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 2849 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 2850 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 2851 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 2852 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 2853 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 2854 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 2855 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 2856 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 2857
Kojto 101:7cff1c4259d7 2858 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 101:7cff1c4259d7 2859 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto 101:7cff1c4259d7 2860 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 2861 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 2862 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 2863 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 2864 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto 101:7cff1c4259d7 2865
Kojto 101:7cff1c4259d7 2866 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 101:7cff1c4259d7 2867 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
Kojto 101:7cff1c4259d7 2868 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 101:7cff1c4259d7 2869 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 2870 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 2871 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 101:7cff1c4259d7 2872 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
Kojto 101:7cff1c4259d7 2873
Kojto 101:7cff1c4259d7 2874 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 101:7cff1c4259d7 2875 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2876
Kojto 101:7cff1c4259d7 2877 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 101:7cff1c4259d7 2878 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2879
Kojto 101:7cff1c4259d7 2880 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 101:7cff1c4259d7 2881 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2882
Kojto 101:7cff1c4259d7 2883 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 101:7cff1c4259d7 2884 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2885
Kojto 101:7cff1c4259d7 2886 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 101:7cff1c4259d7 2887 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2888
Kojto 101:7cff1c4259d7 2889 /******************** Bits definition for RTC_BKP5R register ****************/
Kojto 101:7cff1c4259d7 2890 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2891
Kojto 101:7cff1c4259d7 2892 /******************** Bits definition for RTC_BKP6R register ****************/
Kojto 101:7cff1c4259d7 2893 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2894
Kojto 101:7cff1c4259d7 2895 /******************** Bits definition for RTC_BKP7R register ****************/
Kojto 101:7cff1c4259d7 2896 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2897
Kojto 101:7cff1c4259d7 2898 /******************** Bits definition for RTC_BKP8R register ****************/
Kojto 101:7cff1c4259d7 2899 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2900
Kojto 101:7cff1c4259d7 2901 /******************** Bits definition for RTC_BKP9R register ****************/
Kojto 101:7cff1c4259d7 2902 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2903
Kojto 101:7cff1c4259d7 2904 /******************** Bits definition for RTC_BKP10R register ***************/
Kojto 101:7cff1c4259d7 2905 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2906
Kojto 101:7cff1c4259d7 2907 /******************** Bits definition for RTC_BKP11R register ***************/
Kojto 101:7cff1c4259d7 2908 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2909
Kojto 101:7cff1c4259d7 2910 /******************** Bits definition for RTC_BKP12R register ***************/
Kojto 101:7cff1c4259d7 2911 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2912
Kojto 101:7cff1c4259d7 2913 /******************** Bits definition for RTC_BKP13R register ***************/
Kojto 101:7cff1c4259d7 2914 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2915
Kojto 101:7cff1c4259d7 2916 /******************** Bits definition for RTC_BKP14R register ***************/
Kojto 101:7cff1c4259d7 2917 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2918
Kojto 101:7cff1c4259d7 2919 /******************** Bits definition for RTC_BKP15R register ***************/
Kojto 101:7cff1c4259d7 2920 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2921
Kojto 101:7cff1c4259d7 2922 /******************** Bits definition for RTC_BKP16R register ***************/
Kojto 101:7cff1c4259d7 2923 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2924
Kojto 101:7cff1c4259d7 2925 /******************** Bits definition for RTC_BKP17R register ***************/
Kojto 101:7cff1c4259d7 2926 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2927
Kojto 101:7cff1c4259d7 2928 /******************** Bits definition for RTC_BKP18R register ***************/
Kojto 101:7cff1c4259d7 2929 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2930
Kojto 101:7cff1c4259d7 2931 /******************** Bits definition for RTC_BKP19R register ***************/
Kojto 101:7cff1c4259d7 2932 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
Kojto 101:7cff1c4259d7 2933
Kojto 101:7cff1c4259d7 2934
Kojto 101:7cff1c4259d7 2935
Kojto 101:7cff1c4259d7 2936 /******************************************************************************/
Kojto 101:7cff1c4259d7 2937 /* */
Kojto 101:7cff1c4259d7 2938 /* SD host Interface */
Kojto 101:7cff1c4259d7 2939 /* */
Kojto 101:7cff1c4259d7 2940 /******************************************************************************/
Kojto 101:7cff1c4259d7 2941 /****************** Bit definition for SDIO_POWER register ******************/
Kojto 101:7cff1c4259d7 2942 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
Kojto 101:7cff1c4259d7 2943 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 2944 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 2945
Kojto 101:7cff1c4259d7 2946 /****************** Bit definition for SDIO_CLKCR register ******************/
Kojto 101:7cff1c4259d7 2947 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
Kojto 101:7cff1c4259d7 2948 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
Kojto 101:7cff1c4259d7 2949 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
Kojto 101:7cff1c4259d7 2950 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
Kojto 101:7cff1c4259d7 2951
Kojto 101:7cff1c4259d7 2952 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
Kojto 101:7cff1c4259d7 2953 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 2954 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 2955
Kojto 101:7cff1c4259d7 2956 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
Kojto 101:7cff1c4259d7 2957 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
Kojto 101:7cff1c4259d7 2958
Kojto 101:7cff1c4259d7 2959 /******************* Bit definition for SDIO_ARG register *******************/
Kojto 101:7cff1c4259d7 2960 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
Kojto 101:7cff1c4259d7 2961
Kojto 101:7cff1c4259d7 2962 /******************* Bit definition for SDIO_CMD register *******************/
Kojto 101:7cff1c4259d7 2963 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
Kojto 101:7cff1c4259d7 2964
Kojto 101:7cff1c4259d7 2965 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
Kojto 101:7cff1c4259d7 2966 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
Kojto 101:7cff1c4259d7 2967 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
Kojto 101:7cff1c4259d7 2968
Kojto 101:7cff1c4259d7 2969 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
Kojto 101:7cff1c4259d7 2970 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
Kojto 101:7cff1c4259d7 2971 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
Kojto 101:7cff1c4259d7 2972 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
Kojto 101:7cff1c4259d7 2973 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
Kojto 101:7cff1c4259d7 2974 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
Kojto 101:7cff1c4259d7 2975 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
Kojto 101:7cff1c4259d7 2976
Kojto 101:7cff1c4259d7 2977 /***************** Bit definition for SDIO_RESPCMD register *****************/
Kojto 101:7cff1c4259d7 2978 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
Kojto 101:7cff1c4259d7 2979
Kojto 101:7cff1c4259d7 2980 /****************** Bit definition for SDIO_RESP0 register ******************/
Kojto 101:7cff1c4259d7 2981 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 101:7cff1c4259d7 2982
Kojto 101:7cff1c4259d7 2983 /****************** Bit definition for SDIO_RESP1 register ******************/
Kojto 101:7cff1c4259d7 2984 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 101:7cff1c4259d7 2985
Kojto 101:7cff1c4259d7 2986 /****************** Bit definition for SDIO_RESP2 register ******************/
Kojto 101:7cff1c4259d7 2987 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 101:7cff1c4259d7 2988
Kojto 101:7cff1c4259d7 2989 /****************** Bit definition for SDIO_RESP3 register ******************/
Kojto 101:7cff1c4259d7 2990 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 101:7cff1c4259d7 2991
Kojto 101:7cff1c4259d7 2992 /****************** Bit definition for SDIO_RESP4 register ******************/
Kojto 101:7cff1c4259d7 2993 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 101:7cff1c4259d7 2994
Kojto 101:7cff1c4259d7 2995 /****************** Bit definition for SDIO_DTIMER register *****************/
Kojto 101:7cff1c4259d7 2996 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
Kojto 101:7cff1c4259d7 2997
Kojto 101:7cff1c4259d7 2998 /****************** Bit definition for SDIO_DLEN register *******************/
Kojto 101:7cff1c4259d7 2999 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
Kojto 101:7cff1c4259d7 3000
Kojto 101:7cff1c4259d7 3001 /****************** Bit definition for SDIO_DCTRL register ******************/
Kojto 101:7cff1c4259d7 3002 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
Kojto 101:7cff1c4259d7 3003 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
Kojto 101:7cff1c4259d7 3004 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
Kojto 101:7cff1c4259d7 3005 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
Kojto 101:7cff1c4259d7 3006
Kojto 101:7cff1c4259d7 3007 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
Kojto 101:7cff1c4259d7 3008 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3009 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3010 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3011 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3012
Kojto 101:7cff1c4259d7 3013 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
Kojto 101:7cff1c4259d7 3014 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
Kojto 101:7cff1c4259d7 3015 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
Kojto 101:7cff1c4259d7 3016 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
Kojto 101:7cff1c4259d7 3017
Kojto 101:7cff1c4259d7 3018 /****************** Bit definition for SDIO_DCOUNT register *****************/
Kojto 101:7cff1c4259d7 3019 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
Kojto 101:7cff1c4259d7 3020
Kojto 101:7cff1c4259d7 3021 /****************** Bit definition for SDIO_STA register ********************/
Kojto 101:7cff1c4259d7 3022 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
Kojto 101:7cff1c4259d7 3023 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
Kojto 101:7cff1c4259d7 3024 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
Kojto 101:7cff1c4259d7 3025 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
Kojto 101:7cff1c4259d7 3026 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
Kojto 101:7cff1c4259d7 3027 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
Kojto 101:7cff1c4259d7 3028 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
Kojto 101:7cff1c4259d7 3029 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
Kojto 101:7cff1c4259d7 3030 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
Kojto 101:7cff1c4259d7 3031 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
Kojto 101:7cff1c4259d7 3032 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
Kojto 101:7cff1c4259d7 3033 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
Kojto 101:7cff1c4259d7 3034 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
Kojto 101:7cff1c4259d7 3035 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
Kojto 101:7cff1c4259d7 3036 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
Kojto 101:7cff1c4259d7 3037 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
Kojto 101:7cff1c4259d7 3038 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
Kojto 101:7cff1c4259d7 3039 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
Kojto 101:7cff1c4259d7 3040 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
Kojto 101:7cff1c4259d7 3041 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
Kojto 101:7cff1c4259d7 3042 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
Kojto 101:7cff1c4259d7 3043 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
Kojto 101:7cff1c4259d7 3044 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
Kojto 101:7cff1c4259d7 3045 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
Kojto 101:7cff1c4259d7 3046
Kojto 101:7cff1c4259d7 3047 /******************* Bit definition for SDIO_ICR register *******************/
Kojto 101:7cff1c4259d7 3048 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
Kojto 101:7cff1c4259d7 3049 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
Kojto 101:7cff1c4259d7 3050 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
Kojto 101:7cff1c4259d7 3051 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
Kojto 101:7cff1c4259d7 3052 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
Kojto 101:7cff1c4259d7 3053 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
Kojto 101:7cff1c4259d7 3054 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
Kojto 101:7cff1c4259d7 3055 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
Kojto 101:7cff1c4259d7 3056 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
Kojto 101:7cff1c4259d7 3057 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
Kojto 101:7cff1c4259d7 3058 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
Kojto 101:7cff1c4259d7 3059 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
Kojto 101:7cff1c4259d7 3060 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
Kojto 101:7cff1c4259d7 3061
Kojto 101:7cff1c4259d7 3062 /****************** Bit definition for SDIO_MASK register *******************/
Kojto 101:7cff1c4259d7 3063 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
Kojto 101:7cff1c4259d7 3064 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
Kojto 101:7cff1c4259d7 3065 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
Kojto 101:7cff1c4259d7 3066 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
Kojto 101:7cff1c4259d7 3067 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
Kojto 101:7cff1c4259d7 3068 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
Kojto 101:7cff1c4259d7 3069 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
Kojto 101:7cff1c4259d7 3070 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
Kojto 101:7cff1c4259d7 3071 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
Kojto 101:7cff1c4259d7 3072 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
Kojto 101:7cff1c4259d7 3073 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
Kojto 101:7cff1c4259d7 3074 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
Kojto 101:7cff1c4259d7 3075 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
Kojto 101:7cff1c4259d7 3076 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
Kojto 101:7cff1c4259d7 3077 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
Kojto 101:7cff1c4259d7 3078 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
Kojto 101:7cff1c4259d7 3079 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
Kojto 101:7cff1c4259d7 3080 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
Kojto 101:7cff1c4259d7 3081 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
Kojto 101:7cff1c4259d7 3082 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
Kojto 101:7cff1c4259d7 3083 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
Kojto 101:7cff1c4259d7 3084 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
Kojto 101:7cff1c4259d7 3085 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
Kojto 101:7cff1c4259d7 3086 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
Kojto 101:7cff1c4259d7 3087
Kojto 101:7cff1c4259d7 3088 /***************** Bit definition for SDIO_FIFOCNT register *****************/
Kojto 101:7cff1c4259d7 3089 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
Kojto 101:7cff1c4259d7 3090
Kojto 101:7cff1c4259d7 3091 /****************** Bit definition for SDIO_FIFO register *******************/
Kojto 101:7cff1c4259d7 3092 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
Kojto 101:7cff1c4259d7 3093
Kojto 101:7cff1c4259d7 3094 /******************************************************************************/
Kojto 101:7cff1c4259d7 3095 /* */
Kojto 101:7cff1c4259d7 3096 /* Serial Peripheral Interface */
Kojto 101:7cff1c4259d7 3097 /* */
Kojto 101:7cff1c4259d7 3098 /******************************************************************************/
Kojto 101:7cff1c4259d7 3099 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 101:7cff1c4259d7 3100 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
Kojto 101:7cff1c4259d7 3101 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
Kojto 101:7cff1c4259d7 3102 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
Kojto 101:7cff1c4259d7 3103
Kojto 101:7cff1c4259d7 3104 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
Kojto 101:7cff1c4259d7 3105 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3106 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3107 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3108
Kojto 101:7cff1c4259d7 3109 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
Kojto 101:7cff1c4259d7 3110 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
Kojto 101:7cff1c4259d7 3111 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
Kojto 101:7cff1c4259d7 3112 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
Kojto 101:7cff1c4259d7 3113 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
Kojto 101:7cff1c4259d7 3114 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
Kojto 101:7cff1c4259d7 3115 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
Kojto 101:7cff1c4259d7 3116 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
Kojto 101:7cff1c4259d7 3117 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
Kojto 101:7cff1c4259d7 3118 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
Kojto 101:7cff1c4259d7 3119
Kojto 101:7cff1c4259d7 3120 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 101:7cff1c4259d7 3121 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
Kojto 101:7cff1c4259d7 3122 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
Kojto 101:7cff1c4259d7 3123 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
Kojto 101:7cff1c4259d7 3124 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
Kojto 101:7cff1c4259d7 3125 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
Kojto 101:7cff1c4259d7 3126 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
Kojto 101:7cff1c4259d7 3127 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
Kojto 101:7cff1c4259d7 3128
Kojto 101:7cff1c4259d7 3129 /******************** Bit definition for SPI_SR register ********************/
Kojto 101:7cff1c4259d7 3130 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
Kojto 101:7cff1c4259d7 3131 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
Kojto 101:7cff1c4259d7 3132 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
Kojto 101:7cff1c4259d7 3133 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
Kojto 101:7cff1c4259d7 3134 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
Kojto 101:7cff1c4259d7 3135 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
Kojto 101:7cff1c4259d7 3136 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
Kojto 101:7cff1c4259d7 3137 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
Kojto 101:7cff1c4259d7 3138 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
Kojto 101:7cff1c4259d7 3139
Kojto 101:7cff1c4259d7 3140 /******************** Bit definition for SPI_DR register ********************/
Kojto 101:7cff1c4259d7 3141 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
Kojto 101:7cff1c4259d7 3142
Kojto 101:7cff1c4259d7 3143 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 101:7cff1c4259d7 3144 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
Kojto 101:7cff1c4259d7 3145
Kojto 101:7cff1c4259d7 3146 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 101:7cff1c4259d7 3147 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
Kojto 101:7cff1c4259d7 3148
Kojto 101:7cff1c4259d7 3149 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 101:7cff1c4259d7 3150 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
Kojto 101:7cff1c4259d7 3151
Kojto 101:7cff1c4259d7 3152 /****************** Bit definition for SPI_I2SCFGR register *****************/
Kojto 101:7cff1c4259d7 3153 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
Kojto 101:7cff1c4259d7 3154
Kojto 101:7cff1c4259d7 3155 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 101:7cff1c4259d7 3156 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3157 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3158
Kojto 101:7cff1c4259d7 3159 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
Kojto 101:7cff1c4259d7 3160
Kojto 101:7cff1c4259d7 3161 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 101:7cff1c4259d7 3162 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3163 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3164
Kojto 101:7cff1c4259d7 3165 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
Kojto 101:7cff1c4259d7 3166
Kojto 101:7cff1c4259d7 3167 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 101:7cff1c4259d7 3168 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3169 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3170
Kojto 101:7cff1c4259d7 3171 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
Kojto 101:7cff1c4259d7 3172 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
Kojto 101:7cff1c4259d7 3173
Kojto 101:7cff1c4259d7 3174 /****************** Bit definition for SPI_I2SPR register *******************/
Kojto 101:7cff1c4259d7 3175 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
Kojto 101:7cff1c4259d7 3176 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
Kojto 101:7cff1c4259d7 3177 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
Kojto 101:7cff1c4259d7 3178
Kojto 101:7cff1c4259d7 3179 /******************************************************************************/
Kojto 101:7cff1c4259d7 3180 /* */
Kojto 101:7cff1c4259d7 3181 /* SYSCFG */
Kojto 101:7cff1c4259d7 3182 /* */
Kojto 101:7cff1c4259d7 3183 /******************************************************************************/
Kojto 101:7cff1c4259d7 3184 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
Kojto 101:7cff1c4259d7 3185 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
Kojto 101:7cff1c4259d7 3186 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 3187 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 3188 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 3189
Kojto 101:7cff1c4259d7 3190 /****************** Bit definition for SYSCFG_PMC register ******************/
Kojto 101:7cff1c4259d7 3191 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
Kojto 101:7cff1c4259d7 3192
Kojto 101:7cff1c4259d7 3193 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 101:7cff1c4259d7 3194 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
Kojto 101:7cff1c4259d7 3195 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
Kojto 101:7cff1c4259d7 3196 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
Kojto 101:7cff1c4259d7 3197 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
Kojto 101:7cff1c4259d7 3198 /**
Kojto 101:7cff1c4259d7 3199 * @brief EXTI0 configuration
Kojto 101:7cff1c4259d7 3200 */
Kojto 101:7cff1c4259d7 3201 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
Kojto 101:7cff1c4259d7 3202 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
Kojto 101:7cff1c4259d7 3203 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
Kojto 101:7cff1c4259d7 3204 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
Kojto 101:7cff1c4259d7 3205 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
Kojto 101:7cff1c4259d7 3206 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
Kojto 101:7cff1c4259d7 3207
Kojto 101:7cff1c4259d7 3208 /**
Kojto 101:7cff1c4259d7 3209 * @brief EXTI1 configuration
Kojto 101:7cff1c4259d7 3210 */
Kojto 101:7cff1c4259d7 3211 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
Kojto 101:7cff1c4259d7 3212 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
Kojto 101:7cff1c4259d7 3213 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
Kojto 101:7cff1c4259d7 3214 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
Kojto 101:7cff1c4259d7 3215 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
Kojto 101:7cff1c4259d7 3216 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
Kojto 101:7cff1c4259d7 3217
Kojto 101:7cff1c4259d7 3218 /**
Kojto 101:7cff1c4259d7 3219 * @brief EXTI2 configuration
Kojto 101:7cff1c4259d7 3220 */
Kojto 101:7cff1c4259d7 3221 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
Kojto 101:7cff1c4259d7 3222 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
Kojto 101:7cff1c4259d7 3223 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
Kojto 101:7cff1c4259d7 3224 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
Kojto 101:7cff1c4259d7 3225 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
Kojto 101:7cff1c4259d7 3226 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
Kojto 101:7cff1c4259d7 3227
Kojto 101:7cff1c4259d7 3228 /**
Kojto 101:7cff1c4259d7 3229 * @brief EXTI3 configuration
Kojto 101:7cff1c4259d7 3230 */
Kojto 101:7cff1c4259d7 3231 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
Kojto 101:7cff1c4259d7 3232 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
Kojto 101:7cff1c4259d7 3233 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
Kojto 101:7cff1c4259d7 3234 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
Kojto 101:7cff1c4259d7 3235 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
Kojto 101:7cff1c4259d7 3236 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
Kojto 101:7cff1c4259d7 3237
Kojto 101:7cff1c4259d7 3238 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto 101:7cff1c4259d7 3239 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
Kojto 101:7cff1c4259d7 3240 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
Kojto 101:7cff1c4259d7 3241 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
Kojto 101:7cff1c4259d7 3242 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
Kojto 101:7cff1c4259d7 3243 /**
Kojto 101:7cff1c4259d7 3244 * @brief EXTI4 configuration
Kojto 101:7cff1c4259d7 3245 */
Kojto 101:7cff1c4259d7 3246 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
Kojto 101:7cff1c4259d7 3247 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
Kojto 101:7cff1c4259d7 3248 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
Kojto 101:7cff1c4259d7 3249 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
Kojto 101:7cff1c4259d7 3250 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
Kojto 101:7cff1c4259d7 3251 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
Kojto 101:7cff1c4259d7 3252
Kojto 101:7cff1c4259d7 3253 /**
Kojto 101:7cff1c4259d7 3254 * @brief EXTI5 configuration
Kojto 101:7cff1c4259d7 3255 */
Kojto 101:7cff1c4259d7 3256 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
Kojto 101:7cff1c4259d7 3257 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
Kojto 101:7cff1c4259d7 3258 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
Kojto 101:7cff1c4259d7 3259 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
Kojto 101:7cff1c4259d7 3260 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
Kojto 101:7cff1c4259d7 3261 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
Kojto 101:7cff1c4259d7 3262
Kojto 101:7cff1c4259d7 3263 /**
Kojto 101:7cff1c4259d7 3264 * @brief EXTI6 configuration
Kojto 101:7cff1c4259d7 3265 */
Kojto 101:7cff1c4259d7 3266 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
Kojto 101:7cff1c4259d7 3267 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
Kojto 101:7cff1c4259d7 3268 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
Kojto 101:7cff1c4259d7 3269 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
Kojto 101:7cff1c4259d7 3270 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
Kojto 101:7cff1c4259d7 3271 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
Kojto 101:7cff1c4259d7 3272
Kojto 101:7cff1c4259d7 3273 /**
Kojto 101:7cff1c4259d7 3274 * @brief EXTI7 configuration
Kojto 101:7cff1c4259d7 3275 */
Kojto 101:7cff1c4259d7 3276 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
Kojto 101:7cff1c4259d7 3277 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
Kojto 101:7cff1c4259d7 3278 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
Kojto 101:7cff1c4259d7 3279 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
Kojto 101:7cff1c4259d7 3280 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
Kojto 101:7cff1c4259d7 3281 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
Kojto 101:7cff1c4259d7 3282
Kojto 101:7cff1c4259d7 3283
Kojto 101:7cff1c4259d7 3284 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto 101:7cff1c4259d7 3285 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
Kojto 101:7cff1c4259d7 3286 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
Kojto 101:7cff1c4259d7 3287 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
Kojto 101:7cff1c4259d7 3288 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
Kojto 101:7cff1c4259d7 3289
Kojto 101:7cff1c4259d7 3290 /**
Kojto 101:7cff1c4259d7 3291 * @brief EXTI8 configuration
Kojto 101:7cff1c4259d7 3292 */
Kojto 101:7cff1c4259d7 3293 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
Kojto 101:7cff1c4259d7 3294 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
Kojto 101:7cff1c4259d7 3295 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
Kojto 101:7cff1c4259d7 3296 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
Kojto 101:7cff1c4259d7 3297 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
Kojto 101:7cff1c4259d7 3298 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
Kojto 101:7cff1c4259d7 3299
Kojto 101:7cff1c4259d7 3300 /**
Kojto 101:7cff1c4259d7 3301 * @brief EXTI9 configuration
Kojto 101:7cff1c4259d7 3302 */
Kojto 101:7cff1c4259d7 3303 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
Kojto 101:7cff1c4259d7 3304 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
Kojto 101:7cff1c4259d7 3305 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
Kojto 101:7cff1c4259d7 3306 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
Kojto 101:7cff1c4259d7 3307 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
Kojto 101:7cff1c4259d7 3308 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
Kojto 101:7cff1c4259d7 3309
Kojto 101:7cff1c4259d7 3310 /**
Kojto 101:7cff1c4259d7 3311 * @brief EXTI10 configuration
Kojto 101:7cff1c4259d7 3312 */
Kojto 101:7cff1c4259d7 3313 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
Kojto 101:7cff1c4259d7 3314 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
Kojto 101:7cff1c4259d7 3315 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
Kojto 101:7cff1c4259d7 3316 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
Kojto 101:7cff1c4259d7 3317 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
Kojto 101:7cff1c4259d7 3318 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
Kojto 101:7cff1c4259d7 3319
Kojto 101:7cff1c4259d7 3320 /**
Kojto 101:7cff1c4259d7 3321 * @brief EXTI11 configuration
Kojto 101:7cff1c4259d7 3322 */
Kojto 101:7cff1c4259d7 3323 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
Kojto 101:7cff1c4259d7 3324 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
Kojto 101:7cff1c4259d7 3325 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
Kojto 101:7cff1c4259d7 3326 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
Kojto 101:7cff1c4259d7 3327 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
Kojto 101:7cff1c4259d7 3328 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
Kojto 101:7cff1c4259d7 3329
Kojto 101:7cff1c4259d7 3330 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
Kojto 101:7cff1c4259d7 3331 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
Kojto 101:7cff1c4259d7 3332 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
Kojto 101:7cff1c4259d7 3333 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
Kojto 101:7cff1c4259d7 3334 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
Kojto 101:7cff1c4259d7 3335 /**
Kojto 101:7cff1c4259d7 3336 * @brief EXTI12 configuration
Kojto 101:7cff1c4259d7 3337 */
Kojto 101:7cff1c4259d7 3338 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
Kojto 101:7cff1c4259d7 3339 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
Kojto 101:7cff1c4259d7 3340 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
Kojto 101:7cff1c4259d7 3341 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
Kojto 101:7cff1c4259d7 3342 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
Kojto 101:7cff1c4259d7 3343 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
Kojto 101:7cff1c4259d7 3344
Kojto 101:7cff1c4259d7 3345 /**
Kojto 101:7cff1c4259d7 3346 * @brief EXTI13 configuration
Kojto 101:7cff1c4259d7 3347 */
Kojto 101:7cff1c4259d7 3348 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
Kojto 101:7cff1c4259d7 3349 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
Kojto 101:7cff1c4259d7 3350 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
Kojto 101:7cff1c4259d7 3351 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
Kojto 101:7cff1c4259d7 3352 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
Kojto 101:7cff1c4259d7 3353 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
Kojto 101:7cff1c4259d7 3354
Kojto 101:7cff1c4259d7 3355 /**
Kojto 101:7cff1c4259d7 3356 * @brief EXTI14 configuration
Kojto 101:7cff1c4259d7 3357 */
Kojto 101:7cff1c4259d7 3358 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
Kojto 101:7cff1c4259d7 3359 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
Kojto 101:7cff1c4259d7 3360 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
Kojto 101:7cff1c4259d7 3361 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
Kojto 101:7cff1c4259d7 3362 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
Kojto 101:7cff1c4259d7 3363 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
Kojto 101:7cff1c4259d7 3364
Kojto 101:7cff1c4259d7 3365 /**
Kojto 101:7cff1c4259d7 3366 * @brief EXTI15 configuration
Kojto 101:7cff1c4259d7 3367 */
Kojto 101:7cff1c4259d7 3368 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
Kojto 101:7cff1c4259d7 3369 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
Kojto 101:7cff1c4259d7 3370 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
Kojto 101:7cff1c4259d7 3371 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
Kojto 101:7cff1c4259d7 3372 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
Kojto 101:7cff1c4259d7 3373 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
Kojto 101:7cff1c4259d7 3374
Kojto 101:7cff1c4259d7 3375 /****************** Bit definition for SYSCFG_CMPCR register ****************/
Kojto 101:7cff1c4259d7 3376 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
Kojto 101:7cff1c4259d7 3377 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
Kojto 101:7cff1c4259d7 3378
Kojto 101:7cff1c4259d7 3379 /******************************************************************************/
Kojto 101:7cff1c4259d7 3380 /* */
Kojto 101:7cff1c4259d7 3381 /* TIM */
Kojto 101:7cff1c4259d7 3382 /* */
Kojto 101:7cff1c4259d7 3383 /******************************************************************************/
Kojto 101:7cff1c4259d7 3384 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 101:7cff1c4259d7 3385 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
Kojto 101:7cff1c4259d7 3386 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
Kojto 101:7cff1c4259d7 3387 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
Kojto 101:7cff1c4259d7 3388 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
Kojto 101:7cff1c4259d7 3389 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
Kojto 101:7cff1c4259d7 3390
Kojto 101:7cff1c4259d7 3391 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 101:7cff1c4259d7 3392 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3393 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3394
Kojto 101:7cff1c4259d7 3395 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
Kojto 101:7cff1c4259d7 3396
Kojto 101:7cff1c4259d7 3397 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
Kojto 101:7cff1c4259d7 3398 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3399 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3400
Kojto 101:7cff1c4259d7 3401 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 101:7cff1c4259d7 3402 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
Kojto 101:7cff1c4259d7 3403 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
Kojto 101:7cff1c4259d7 3404 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
Kojto 101:7cff1c4259d7 3405
Kojto 101:7cff1c4259d7 3406 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 101:7cff1c4259d7 3407 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3408 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3409 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3410
Kojto 101:7cff1c4259d7 3411 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
Kojto 101:7cff1c4259d7 3412 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
Kojto 101:7cff1c4259d7 3413 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
Kojto 101:7cff1c4259d7 3414 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
Kojto 101:7cff1c4259d7 3415 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
Kojto 101:7cff1c4259d7 3416 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
Kojto 101:7cff1c4259d7 3417 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
Kojto 101:7cff1c4259d7 3418 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
Kojto 101:7cff1c4259d7 3419
Kojto 101:7cff1c4259d7 3420 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 101:7cff1c4259d7 3421 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 101:7cff1c4259d7 3422 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3423 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3424 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3425
Kojto 101:7cff1c4259d7 3426 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
Kojto 101:7cff1c4259d7 3427 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3428 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3429 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3430
Kojto 101:7cff1c4259d7 3431 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
Kojto 101:7cff1c4259d7 3432
Kojto 101:7cff1c4259d7 3433 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 101:7cff1c4259d7 3434 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3435 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3436 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3437 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3438
Kojto 101:7cff1c4259d7 3439 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 101:7cff1c4259d7 3440 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3441 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3442
Kojto 101:7cff1c4259d7 3443 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
Kojto 101:7cff1c4259d7 3444 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
Kojto 101:7cff1c4259d7 3445
Kojto 101:7cff1c4259d7 3446 /******************* Bit definition for TIM_DIER register *******************/
Kojto 101:7cff1c4259d7 3447 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
Kojto 101:7cff1c4259d7 3448 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
Kojto 101:7cff1c4259d7 3449 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
Kojto 101:7cff1c4259d7 3450 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
Kojto 101:7cff1c4259d7 3451 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
Kojto 101:7cff1c4259d7 3452 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
Kojto 101:7cff1c4259d7 3453 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
Kojto 101:7cff1c4259d7 3454 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
Kojto 101:7cff1c4259d7 3455 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
Kojto 101:7cff1c4259d7 3456 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
Kojto 101:7cff1c4259d7 3457 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
Kojto 101:7cff1c4259d7 3458 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
Kojto 101:7cff1c4259d7 3459 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
Kojto 101:7cff1c4259d7 3460 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
Kojto 101:7cff1c4259d7 3461 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
Kojto 101:7cff1c4259d7 3462
Kojto 101:7cff1c4259d7 3463 /******************** Bit definition for TIM_SR register ********************/
Kojto 101:7cff1c4259d7 3464 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
Kojto 101:7cff1c4259d7 3465 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
Kojto 101:7cff1c4259d7 3466 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
Kojto 101:7cff1c4259d7 3467 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
Kojto 101:7cff1c4259d7 3468 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
Kojto 101:7cff1c4259d7 3469 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
Kojto 101:7cff1c4259d7 3470 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
Kojto 101:7cff1c4259d7 3471 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
Kojto 101:7cff1c4259d7 3472 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 101:7cff1c4259d7 3473 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 101:7cff1c4259d7 3474 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 101:7cff1c4259d7 3475 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 101:7cff1c4259d7 3476
Kojto 101:7cff1c4259d7 3477 /******************* Bit definition for TIM_EGR register ********************/
Kojto 101:7cff1c4259d7 3478 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
Kojto 101:7cff1c4259d7 3479 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
Kojto 101:7cff1c4259d7 3480 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
Kojto 101:7cff1c4259d7 3481 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
Kojto 101:7cff1c4259d7 3482 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
Kojto 101:7cff1c4259d7 3483 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
Kojto 101:7cff1c4259d7 3484 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
Kojto 101:7cff1c4259d7 3485 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
Kojto 101:7cff1c4259d7 3486
Kojto 101:7cff1c4259d7 3487 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 101:7cff1c4259d7 3488 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 101:7cff1c4259d7 3489 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3490 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3491
Kojto 101:7cff1c4259d7 3492 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
Kojto 101:7cff1c4259d7 3493 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
Kojto 101:7cff1c4259d7 3494
Kojto 101:7cff1c4259d7 3495 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 101:7cff1c4259d7 3496 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3497 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3498 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3499
Kojto 101:7cff1c4259d7 3500 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
Kojto 101:7cff1c4259d7 3501
Kojto 101:7cff1c4259d7 3502 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 101:7cff1c4259d7 3503 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3504 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3505
Kojto 101:7cff1c4259d7 3506 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
Kojto 101:7cff1c4259d7 3507 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
Kojto 101:7cff1c4259d7 3508
Kojto 101:7cff1c4259d7 3509 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 101:7cff1c4259d7 3510 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3511 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3512 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3513
Kojto 101:7cff1c4259d7 3514 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
Kojto 101:7cff1c4259d7 3515
Kojto 101:7cff1c4259d7 3516 /*----------------------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 3517
Kojto 101:7cff1c4259d7 3518 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 101:7cff1c4259d7 3519 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3520 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3521
Kojto 101:7cff1c4259d7 3522 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 101:7cff1c4259d7 3523 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3524 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3525 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3526 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3527
Kojto 101:7cff1c4259d7 3528 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 101:7cff1c4259d7 3529 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3530 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3531
Kojto 101:7cff1c4259d7 3532 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 101:7cff1c4259d7 3533 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3534 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3535 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3536 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3537
Kojto 101:7cff1c4259d7 3538 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 101:7cff1c4259d7 3539 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 101:7cff1c4259d7 3540 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3541 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3542
Kojto 101:7cff1c4259d7 3543 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
Kojto 101:7cff1c4259d7 3544 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
Kojto 101:7cff1c4259d7 3545
Kojto 101:7cff1c4259d7 3546 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 101:7cff1c4259d7 3547 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3548 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3549 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3550
Kojto 101:7cff1c4259d7 3551 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
Kojto 101:7cff1c4259d7 3552
Kojto 101:7cff1c4259d7 3553 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 101:7cff1c4259d7 3554 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3555 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3556
Kojto 101:7cff1c4259d7 3557 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
Kojto 101:7cff1c4259d7 3558 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
Kojto 101:7cff1c4259d7 3559
Kojto 101:7cff1c4259d7 3560 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 101:7cff1c4259d7 3561 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3562 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3563 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3564
Kojto 101:7cff1c4259d7 3565 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
Kojto 101:7cff1c4259d7 3566
Kojto 101:7cff1c4259d7 3567 /*----------------------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 3568
Kojto 101:7cff1c4259d7 3569 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 101:7cff1c4259d7 3570 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3571 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3572
Kojto 101:7cff1c4259d7 3573 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 101:7cff1c4259d7 3574 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3575 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3576 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3577 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3578
Kojto 101:7cff1c4259d7 3579 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 101:7cff1c4259d7 3580 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3581 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3582
Kojto 101:7cff1c4259d7 3583 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 101:7cff1c4259d7 3584 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3585 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3586 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3587 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3588
Kojto 101:7cff1c4259d7 3589 /******************* Bit definition for TIM_CCER register *******************/
Kojto 101:7cff1c4259d7 3590 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
Kojto 101:7cff1c4259d7 3591 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
Kojto 101:7cff1c4259d7 3592 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
Kojto 101:7cff1c4259d7 3593 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 101:7cff1c4259d7 3594 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
Kojto 101:7cff1c4259d7 3595 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
Kojto 101:7cff1c4259d7 3596 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
Kojto 101:7cff1c4259d7 3597 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 101:7cff1c4259d7 3598 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
Kojto 101:7cff1c4259d7 3599 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
Kojto 101:7cff1c4259d7 3600 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
Kojto 101:7cff1c4259d7 3601 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 101:7cff1c4259d7 3602 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
Kojto 101:7cff1c4259d7 3603 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
Kojto 101:7cff1c4259d7 3604 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 101:7cff1c4259d7 3605
Kojto 101:7cff1c4259d7 3606 /******************* Bit definition for TIM_CNT register ********************/
Kojto 101:7cff1c4259d7 3607 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
Kojto 101:7cff1c4259d7 3608
Kojto 101:7cff1c4259d7 3609 /******************* Bit definition for TIM_PSC register ********************/
Kojto 101:7cff1c4259d7 3610 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
Kojto 101:7cff1c4259d7 3611
Kojto 101:7cff1c4259d7 3612 /******************* Bit definition for TIM_ARR register ********************/
Kojto 101:7cff1c4259d7 3613 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
Kojto 101:7cff1c4259d7 3614
Kojto 101:7cff1c4259d7 3615 /******************* Bit definition for TIM_RCR register ********************/
Kojto 101:7cff1c4259d7 3616 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
Kojto 101:7cff1c4259d7 3617
Kojto 101:7cff1c4259d7 3618 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 101:7cff1c4259d7 3619 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
Kojto 101:7cff1c4259d7 3620
Kojto 101:7cff1c4259d7 3621 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 101:7cff1c4259d7 3622 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
Kojto 101:7cff1c4259d7 3623
Kojto 101:7cff1c4259d7 3624 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 101:7cff1c4259d7 3625 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
Kojto 101:7cff1c4259d7 3626
Kojto 101:7cff1c4259d7 3627 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 101:7cff1c4259d7 3628 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
Kojto 101:7cff1c4259d7 3629
Kojto 101:7cff1c4259d7 3630 /******************* Bit definition for TIM_BDTR register *******************/
Kojto 101:7cff1c4259d7 3631 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 101:7cff1c4259d7 3632 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3633 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3634 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3635 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3636 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 3637 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 3638 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 3639 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
Kojto 101:7cff1c4259d7 3640
Kojto 101:7cff1c4259d7 3641 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 101:7cff1c4259d7 3642 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3643 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3644
Kojto 101:7cff1c4259d7 3645 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
Kojto 101:7cff1c4259d7 3646 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
Kojto 101:7cff1c4259d7 3647 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
Kojto 101:7cff1c4259d7 3648 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
Kojto 101:7cff1c4259d7 3649 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
Kojto 101:7cff1c4259d7 3650 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
Kojto 101:7cff1c4259d7 3651
Kojto 101:7cff1c4259d7 3652 /******************* Bit definition for TIM_DCR register ********************/
Kojto 101:7cff1c4259d7 3653 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 101:7cff1c4259d7 3654 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3655 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3656 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3657 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3658 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 3659
Kojto 101:7cff1c4259d7 3660 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 101:7cff1c4259d7 3661 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3662 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3663 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3664 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3665 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 3666
Kojto 101:7cff1c4259d7 3667 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 101:7cff1c4259d7 3668 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
Kojto 101:7cff1c4259d7 3669
Kojto 101:7cff1c4259d7 3670 /******************* Bit definition for TIM_OR register *********************/
Kojto 101:7cff1c4259d7 3671 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
Kojto 101:7cff1c4259d7 3672 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3673 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3674 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
Kojto 101:7cff1c4259d7 3675 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3676 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3677
Kojto 101:7cff1c4259d7 3678
Kojto 101:7cff1c4259d7 3679 /******************************************************************************/
Kojto 101:7cff1c4259d7 3680 /* */
Kojto 101:7cff1c4259d7 3681 /* Universal Synchronous Asynchronous Receiver Transmitter */
Kojto 101:7cff1c4259d7 3682 /* */
Kojto 101:7cff1c4259d7 3683 /******************************************************************************/
Kojto 101:7cff1c4259d7 3684 /******************* Bit definition for USART_SR register *******************/
Kojto 101:7cff1c4259d7 3685 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
Kojto 101:7cff1c4259d7 3686 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
Kojto 101:7cff1c4259d7 3687 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
Kojto 101:7cff1c4259d7 3688 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
Kojto 101:7cff1c4259d7 3689 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
Kojto 101:7cff1c4259d7 3690 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
Kojto 101:7cff1c4259d7 3691 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
Kojto 101:7cff1c4259d7 3692 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
Kojto 101:7cff1c4259d7 3693 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
Kojto 101:7cff1c4259d7 3694 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
Kojto 101:7cff1c4259d7 3695
Kojto 101:7cff1c4259d7 3696 /******************* Bit definition for USART_DR register *******************/
Kojto 101:7cff1c4259d7 3697 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
Kojto 101:7cff1c4259d7 3698
Kojto 101:7cff1c4259d7 3699 /****************** Bit definition for USART_BRR register *******************/
Kojto 101:7cff1c4259d7 3700 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
Kojto 101:7cff1c4259d7 3701 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
Kojto 101:7cff1c4259d7 3702
Kojto 101:7cff1c4259d7 3703 /****************** Bit definition for USART_CR1 register *******************/
Kojto 101:7cff1c4259d7 3704 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
Kojto 101:7cff1c4259d7 3705 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
Kojto 101:7cff1c4259d7 3706 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
Kojto 101:7cff1c4259d7 3707 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
Kojto 101:7cff1c4259d7 3708 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
Kojto 101:7cff1c4259d7 3709 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
Kojto 101:7cff1c4259d7 3710 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
Kojto 101:7cff1c4259d7 3711 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
Kojto 101:7cff1c4259d7 3712 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
Kojto 101:7cff1c4259d7 3713 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
Kojto 101:7cff1c4259d7 3714 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
Kojto 101:7cff1c4259d7 3715 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
Kojto 101:7cff1c4259d7 3716 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
Kojto 101:7cff1c4259d7 3717 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
Kojto 101:7cff1c4259d7 3718 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
Kojto 101:7cff1c4259d7 3719
Kojto 101:7cff1c4259d7 3720 /****************** Bit definition for USART_CR2 register *******************/
Kojto 101:7cff1c4259d7 3721 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
Kojto 101:7cff1c4259d7 3722 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
Kojto 101:7cff1c4259d7 3723 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
Kojto 101:7cff1c4259d7 3724 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
Kojto 101:7cff1c4259d7 3725 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
Kojto 101:7cff1c4259d7 3726 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
Kojto 101:7cff1c4259d7 3727 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
Kojto 101:7cff1c4259d7 3728
Kojto 101:7cff1c4259d7 3729 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
Kojto 101:7cff1c4259d7 3730 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3731 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3732
Kojto 101:7cff1c4259d7 3733 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
Kojto 101:7cff1c4259d7 3734
Kojto 101:7cff1c4259d7 3735 /****************** Bit definition for USART_CR3 register *******************/
Kojto 101:7cff1c4259d7 3736 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
Kojto 101:7cff1c4259d7 3737 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
Kojto 101:7cff1c4259d7 3738 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
Kojto 101:7cff1c4259d7 3739 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
Kojto 101:7cff1c4259d7 3740 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
Kojto 101:7cff1c4259d7 3741 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
Kojto 101:7cff1c4259d7 3742 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
Kojto 101:7cff1c4259d7 3743 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
Kojto 101:7cff1c4259d7 3744 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
Kojto 101:7cff1c4259d7 3745 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
Kojto 101:7cff1c4259d7 3746 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
Kojto 101:7cff1c4259d7 3747 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
Kojto 101:7cff1c4259d7 3748
Kojto 101:7cff1c4259d7 3749 /****************** Bit definition for USART_GTPR register ******************/
Kojto 101:7cff1c4259d7 3750 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
Kojto 101:7cff1c4259d7 3751 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3752 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3753 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3754 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3755 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 3756 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 3757 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 3758 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
Kojto 101:7cff1c4259d7 3759
Kojto 101:7cff1c4259d7 3760 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
Kojto 101:7cff1c4259d7 3761
Kojto 101:7cff1c4259d7 3762 /******************************************************************************/
Kojto 101:7cff1c4259d7 3763 /* */
Kojto 101:7cff1c4259d7 3764 /* Window WATCHDOG */
Kojto 101:7cff1c4259d7 3765 /* */
Kojto 101:7cff1c4259d7 3766 /******************************************************************************/
Kojto 101:7cff1c4259d7 3767 /******************* Bit definition for WWDG_CR register ********************/
Kojto 101:7cff1c4259d7 3768 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 101:7cff1c4259d7 3769 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3770 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3771 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3772 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3773 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 3774 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 3775 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 3776
Kojto 101:7cff1c4259d7 3777 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
Kojto 101:7cff1c4259d7 3778
Kojto 101:7cff1c4259d7 3779 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 101:7cff1c4259d7 3780 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
Kojto 101:7cff1c4259d7 3781 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3782 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3783 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3784 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3785 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 3786 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 3787 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 3788
Kojto 101:7cff1c4259d7 3789 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 101:7cff1c4259d7 3790 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3791 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3792
Kojto 101:7cff1c4259d7 3793 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
Kojto 101:7cff1c4259d7 3794
Kojto 101:7cff1c4259d7 3795 /******************* Bit definition for WWDG_SR register ********************/
Kojto 101:7cff1c4259d7 3796 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
Kojto 101:7cff1c4259d7 3797
Kojto 101:7cff1c4259d7 3798
Kojto 101:7cff1c4259d7 3799 /******************************************************************************/
Kojto 101:7cff1c4259d7 3800 /* */
Kojto 101:7cff1c4259d7 3801 /* DBG */
Kojto 101:7cff1c4259d7 3802 /* */
Kojto 101:7cff1c4259d7 3803 /******************************************************************************/
Kojto 101:7cff1c4259d7 3804 /******************** Bit definition for DBGMCU_IDCODE register *************/
Kojto 101:7cff1c4259d7 3805 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
Kojto 101:7cff1c4259d7 3806 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
Kojto 101:7cff1c4259d7 3807
Kojto 101:7cff1c4259d7 3808 /******************** Bit definition for DBGMCU_CR register *****************/
Kojto 101:7cff1c4259d7 3809 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 3810 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 3811 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 3812 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 3813
Kojto 101:7cff1c4259d7 3814 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
Kojto 101:7cff1c4259d7 3815 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
Kojto 101:7cff1c4259d7 3816 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
Kojto 101:7cff1c4259d7 3817
Kojto 101:7cff1c4259d7 3818 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto 101:7cff1c4259d7 3819 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 3820 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 3821 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 3822 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 3823 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
Kojto 101:7cff1c4259d7 3824 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
Kojto 101:7cff1c4259d7 3825 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
Kojto 101:7cff1c4259d7 3826 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
Kojto 101:7cff1c4259d7 3827 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 3828 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
Kojto 101:7cff1c4259d7 3829 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
Kojto 101:7cff1c4259d7 3830 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
Kojto 101:7cff1c4259d7 3831 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
Kojto 101:7cff1c4259d7 3832 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
Kojto 101:7cff1c4259d7 3833 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
Kojto 101:7cff1c4259d7 3834 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
Kojto 101:7cff1c4259d7 3835 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
Kojto 101:7cff1c4259d7 3836 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
Kojto 101:7cff1c4259d7 3837 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
Kojto 101:7cff1c4259d7 3838
Kojto 101:7cff1c4259d7 3839 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto 101:7cff1c4259d7 3840 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 3841 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 3842 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
Kojto 101:7cff1c4259d7 3843 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
Kojto 101:7cff1c4259d7 3844 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
Kojto 101:7cff1c4259d7 3845
Kojto 101:7cff1c4259d7 3846 /******************************************************************************/
Kojto 101:7cff1c4259d7 3847 /* */
Kojto 101:7cff1c4259d7 3848 /* USB_OTG */
Kojto 101:7cff1c4259d7 3849 /* */
Kojto 101:7cff1c4259d7 3850 /******************************************************************************/
Kojto 101:7cff1c4259d7 3851 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
Kojto 101:7cff1c4259d7 3852 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
Kojto 101:7cff1c4259d7 3853 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
Kojto 101:7cff1c4259d7 3854 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
Kojto 101:7cff1c4259d7 3855 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
Kojto 101:7cff1c4259d7 3856 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
Kojto 101:7cff1c4259d7 3857 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
Kojto 101:7cff1c4259d7 3858 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
Kojto 101:7cff1c4259d7 3859 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
Kojto 101:7cff1c4259d7 3860 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
Kojto 101:7cff1c4259d7 3861 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
Kojto 101:7cff1c4259d7 3862
Kojto 101:7cff1c4259d7 3863 /******************** Bit definition forUSB_OTG_HCFG register ********************/
Kojto 101:7cff1c4259d7 3864
Kojto 101:7cff1c4259d7 3865 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
Kojto 101:7cff1c4259d7 3866 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3867 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3868 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
Kojto 101:7cff1c4259d7 3869
Kojto 101:7cff1c4259d7 3870 /******************** Bit definition forUSB_OTG_DCFG register ********************/
Kojto 101:7cff1c4259d7 3871
Kojto 101:7cff1c4259d7 3872 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
Kojto 101:7cff1c4259d7 3873 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3874 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3875 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
Kojto 101:7cff1c4259d7 3876
Kojto 101:7cff1c4259d7 3877 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
Kojto 101:7cff1c4259d7 3878 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3879 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3880 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3881 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3882 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 3883 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 3884 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 3885
Kojto 101:7cff1c4259d7 3886 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
Kojto 101:7cff1c4259d7 3887 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3888 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3889
Kojto 101:7cff1c4259d7 3890 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
Kojto 101:7cff1c4259d7 3891 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3892 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3893
Kojto 101:7cff1c4259d7 3894 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
Kojto 101:7cff1c4259d7 3895 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
Kojto 101:7cff1c4259d7 3896 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
Kojto 101:7cff1c4259d7 3897 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
Kojto 101:7cff1c4259d7 3898
Kojto 101:7cff1c4259d7 3899 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
Kojto 101:7cff1c4259d7 3900 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
Kojto 101:7cff1c4259d7 3901 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
Kojto 101:7cff1c4259d7 3902 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
Kojto 101:7cff1c4259d7 3903 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
Kojto 101:7cff1c4259d7 3904 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
Kojto 101:7cff1c4259d7 3905 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
Kojto 101:7cff1c4259d7 3906
Kojto 101:7cff1c4259d7 3907 /******************** Bit definition forUSB_OTG_DCTL register ********************/
Kojto 101:7cff1c4259d7 3908 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
Kojto 101:7cff1c4259d7 3909 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
Kojto 101:7cff1c4259d7 3910 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
Kojto 101:7cff1c4259d7 3911 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
Kojto 101:7cff1c4259d7 3912
Kojto 101:7cff1c4259d7 3913 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
Kojto 101:7cff1c4259d7 3914 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3915 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3916 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3917 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
Kojto 101:7cff1c4259d7 3918 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
Kojto 101:7cff1c4259d7 3919 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
Kojto 101:7cff1c4259d7 3920 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
Kojto 101:7cff1c4259d7 3921 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
Kojto 101:7cff1c4259d7 3922
Kojto 101:7cff1c4259d7 3923 /******************** Bit definition forUSB_OTG_HFIR register ********************/
Kojto 101:7cff1c4259d7 3924 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
Kojto 101:7cff1c4259d7 3925
Kojto 101:7cff1c4259d7 3926 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
Kojto 101:7cff1c4259d7 3927 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
Kojto 101:7cff1c4259d7 3928 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
Kojto 101:7cff1c4259d7 3929
Kojto 101:7cff1c4259d7 3930 /******************** Bit definition forUSB_OTG_DSTS register ********************/
Kojto 101:7cff1c4259d7 3931 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
Kojto 101:7cff1c4259d7 3932
Kojto 101:7cff1c4259d7 3933 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
Kojto 101:7cff1c4259d7 3934 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3935 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3936 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
Kojto 101:7cff1c4259d7 3937 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
Kojto 101:7cff1c4259d7 3938
Kojto 101:7cff1c4259d7 3939 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
Kojto 101:7cff1c4259d7 3940 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
Kojto 101:7cff1c4259d7 3941
Kojto 101:7cff1c4259d7 3942 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
Kojto 101:7cff1c4259d7 3943 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3944 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3945 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3946 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3947 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
Kojto 101:7cff1c4259d7 3948 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
Kojto 101:7cff1c4259d7 3949 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
Kojto 101:7cff1c4259d7 3950
Kojto 101:7cff1c4259d7 3951 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
Kojto 101:7cff1c4259d7 3952
Kojto 101:7cff1c4259d7 3953 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
Kojto 101:7cff1c4259d7 3954 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3955 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3956 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3957 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
Kojto 101:7cff1c4259d7 3958 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
Kojto 101:7cff1c4259d7 3959 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
Kojto 101:7cff1c4259d7 3960
Kojto 101:7cff1c4259d7 3961 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
Kojto 101:7cff1c4259d7 3962 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3963 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3964 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3965 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3966 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
Kojto 101:7cff1c4259d7 3967 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
Kojto 101:7cff1c4259d7 3968 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
Kojto 101:7cff1c4259d7 3969 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
Kojto 101:7cff1c4259d7 3970 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
Kojto 101:7cff1c4259d7 3971 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
Kojto 101:7cff1c4259d7 3972 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
Kojto 101:7cff1c4259d7 3973 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
Kojto 101:7cff1c4259d7 3974 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
Kojto 101:7cff1c4259d7 3975 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
Kojto 101:7cff1c4259d7 3976 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
Kojto 101:7cff1c4259d7 3977 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
Kojto 101:7cff1c4259d7 3978 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
Kojto 101:7cff1c4259d7 3979
Kojto 101:7cff1c4259d7 3980 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
Kojto 101:7cff1c4259d7 3981 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
Kojto 101:7cff1c4259d7 3982 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
Kojto 101:7cff1c4259d7 3983 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
Kojto 101:7cff1c4259d7 3984 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
Kojto 101:7cff1c4259d7 3985 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
Kojto 101:7cff1c4259d7 3986
Kojto 101:7cff1c4259d7 3987 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
Kojto 101:7cff1c4259d7 3988 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 3989 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 3990 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 3991 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 3992 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 3993 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
Kojto 101:7cff1c4259d7 3994 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
Kojto 101:7cff1c4259d7 3995
Kojto 101:7cff1c4259d7 3996 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
Kojto 101:7cff1c4259d7 3997 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 101:7cff1c4259d7 3998 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 101:7cff1c4259d7 3999 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 101:7cff1c4259d7 4000 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 101:7cff1c4259d7 4001 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 101:7cff1c4259d7 4002 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 101:7cff1c4259d7 4003 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
Kojto 101:7cff1c4259d7 4004 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 101:7cff1c4259d7 4005
Kojto 101:7cff1c4259d7 4006 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
Kojto 101:7cff1c4259d7 4007 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
Kojto 101:7cff1c4259d7 4008
Kojto 101:7cff1c4259d7 4009 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
Kojto 101:7cff1c4259d7 4010 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4011 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4012 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4013 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4014 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 4015 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 4016 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 4017 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 101:7cff1c4259d7 4018
Kojto 101:7cff1c4259d7 4019 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
Kojto 101:7cff1c4259d7 4020 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4021 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4022 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4023 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4024 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 4025 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 4026 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 4027 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
Kojto 101:7cff1c4259d7 4028
Kojto 101:7cff1c4259d7 4029 /******************** Bit definition forUSB_OTG_HAINT register ********************/
Kojto 101:7cff1c4259d7 4030 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
Kojto 101:7cff1c4259d7 4031
Kojto 101:7cff1c4259d7 4032 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
Kojto 101:7cff1c4259d7 4033 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 101:7cff1c4259d7 4034 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 101:7cff1c4259d7 4035 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
Kojto 101:7cff1c4259d7 4036 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
Kojto 101:7cff1c4259d7 4037 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
Kojto 101:7cff1c4259d7 4038 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
Kojto 101:7cff1c4259d7 4039 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 101:7cff1c4259d7 4040
Kojto 101:7cff1c4259d7 4041 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
Kojto 101:7cff1c4259d7 4042 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
Kojto 101:7cff1c4259d7 4043 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
Kojto 101:7cff1c4259d7 4044 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
Kojto 101:7cff1c4259d7 4045 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
Kojto 101:7cff1c4259d7 4046 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
Kojto 101:7cff1c4259d7 4047 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
Kojto 101:7cff1c4259d7 4048 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
Kojto 101:7cff1c4259d7 4049 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
Kojto 101:7cff1c4259d7 4050 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
Kojto 101:7cff1c4259d7 4051 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
Kojto 101:7cff1c4259d7 4052 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
Kojto 101:7cff1c4259d7 4053 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
Kojto 101:7cff1c4259d7 4054 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
Kojto 101:7cff1c4259d7 4055 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
Kojto 101:7cff1c4259d7 4056 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
Kojto 101:7cff1c4259d7 4057 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
Kojto 101:7cff1c4259d7 4058 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
Kojto 101:7cff1c4259d7 4059 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
Kojto 101:7cff1c4259d7 4060 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
Kojto 101:7cff1c4259d7 4061 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
Kojto 101:7cff1c4259d7 4062 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
Kojto 101:7cff1c4259d7 4063 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
Kojto 101:7cff1c4259d7 4064 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
Kojto 101:7cff1c4259d7 4065 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
Kojto 101:7cff1c4259d7 4066 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
Kojto 101:7cff1c4259d7 4067 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
Kojto 101:7cff1c4259d7 4068
Kojto 101:7cff1c4259d7 4069 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
Kojto 101:7cff1c4259d7 4070 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
Kojto 101:7cff1c4259d7 4071 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
Kojto 101:7cff1c4259d7 4072 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
Kojto 101:7cff1c4259d7 4073 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
Kojto 101:7cff1c4259d7 4074 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
Kojto 101:7cff1c4259d7 4075 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
Kojto 101:7cff1c4259d7 4076 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
Kojto 101:7cff1c4259d7 4077 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
Kojto 101:7cff1c4259d7 4078 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
Kojto 101:7cff1c4259d7 4079 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
Kojto 101:7cff1c4259d7 4080 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
Kojto 101:7cff1c4259d7 4081 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
Kojto 101:7cff1c4259d7 4082 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
Kojto 101:7cff1c4259d7 4083 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
Kojto 101:7cff1c4259d7 4084 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
Kojto 101:7cff1c4259d7 4085 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
Kojto 101:7cff1c4259d7 4086 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
Kojto 101:7cff1c4259d7 4087 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
Kojto 101:7cff1c4259d7 4088 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
Kojto 101:7cff1c4259d7 4089 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
Kojto 101:7cff1c4259d7 4090 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
Kojto 101:7cff1c4259d7 4091 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
Kojto 101:7cff1c4259d7 4092 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
Kojto 101:7cff1c4259d7 4093 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
Kojto 101:7cff1c4259d7 4094 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
Kojto 101:7cff1c4259d7 4095 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
Kojto 101:7cff1c4259d7 4096
Kojto 101:7cff1c4259d7 4097 /******************** Bit definition forUSB_OTG_DAINT register ********************/
Kojto 101:7cff1c4259d7 4098 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
Kojto 101:7cff1c4259d7 4099 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
Kojto 101:7cff1c4259d7 4100
Kojto 101:7cff1c4259d7 4101 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
Kojto 101:7cff1c4259d7 4102 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
Kojto 101:7cff1c4259d7 4103
Kojto 101:7cff1c4259d7 4104 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
Kojto 101:7cff1c4259d7 4105 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
Kojto 101:7cff1c4259d7 4106 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
Kojto 101:7cff1c4259d7 4107 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
Kojto 101:7cff1c4259d7 4108 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
Kojto 101:7cff1c4259d7 4109
Kojto 101:7cff1c4259d7 4110 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
Kojto 101:7cff1c4259d7 4111 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
Kojto 101:7cff1c4259d7 4112 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
Kojto 101:7cff1c4259d7 4113
Kojto 101:7cff1c4259d7 4114 /******************** Bit definition for OTG register ********************/
Kojto 101:7cff1c4259d7 4115
Kojto 101:7cff1c4259d7 4116 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
Kojto 101:7cff1c4259d7 4117 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4118 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4119 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4120 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4121 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
Kojto 101:7cff1c4259d7 4122
Kojto 101:7cff1c4259d7 4123 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
Kojto 101:7cff1c4259d7 4124 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4125 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4126
Kojto 101:7cff1c4259d7 4127 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
Kojto 101:7cff1c4259d7 4128 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4129 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4130 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4131 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4132
Kojto 101:7cff1c4259d7 4133 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
Kojto 101:7cff1c4259d7 4134 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4135 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4136 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4137 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4138
Kojto 101:7cff1c4259d7 4139 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
Kojto 101:7cff1c4259d7 4140 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4141 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4142 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4143 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4144
Kojto 101:7cff1c4259d7 4145 /******************** Bit definition for OTG register ********************/
Kojto 101:7cff1c4259d7 4146
Kojto 101:7cff1c4259d7 4147 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
Kojto 101:7cff1c4259d7 4148 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4149 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4150 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4151 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4152 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
Kojto 101:7cff1c4259d7 4153
Kojto 101:7cff1c4259d7 4154 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
Kojto 101:7cff1c4259d7 4155 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4156 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4157
Kojto 101:7cff1c4259d7 4158 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
Kojto 101:7cff1c4259d7 4159 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4160 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4161 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4162 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4163
Kojto 101:7cff1c4259d7 4164 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
Kojto 101:7cff1c4259d7 4165 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4166 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4167 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4168 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4169
Kojto 101:7cff1c4259d7 4170 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
Kojto 101:7cff1c4259d7 4171 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4172 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4173 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4174 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4175
Kojto 101:7cff1c4259d7 4176 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
Kojto 101:7cff1c4259d7 4177 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
Kojto 101:7cff1c4259d7 4178
Kojto 101:7cff1c4259d7 4179 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
Kojto 101:7cff1c4259d7 4180 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
Kojto 101:7cff1c4259d7 4181
Kojto 101:7cff1c4259d7 4182 /******************** Bit definition for OTG register ********************/
Kojto 101:7cff1c4259d7 4183 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
Kojto 101:7cff1c4259d7 4184 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
Kojto 101:7cff1c4259d7 4185 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
Kojto 101:7cff1c4259d7 4186 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
Kojto 101:7cff1c4259d7 4187
Kojto 101:7cff1c4259d7 4188 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
Kojto 101:7cff1c4259d7 4189 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
Kojto 101:7cff1c4259d7 4190
Kojto 101:7cff1c4259d7 4191 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
Kojto 101:7cff1c4259d7 4192 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
Kojto 101:7cff1c4259d7 4193
Kojto 101:7cff1c4259d7 4194 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
Kojto 101:7cff1c4259d7 4195 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4196 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4197 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4198 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4199 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 4200 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 4201 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 4202 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 101:7cff1c4259d7 4203
Kojto 101:7cff1c4259d7 4204 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
Kojto 101:7cff1c4259d7 4205 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4206 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4207 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4208 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4209 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 4210 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 4211 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 4212
Kojto 101:7cff1c4259d7 4213 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
Kojto 101:7cff1c4259d7 4214 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
Kojto 101:7cff1c4259d7 4215 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
Kojto 101:7cff1c4259d7 4216
Kojto 101:7cff1c4259d7 4217 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
Kojto 101:7cff1c4259d7 4218 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4219 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4220 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4221 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4222 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 4223 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 4224 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 4225 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
Kojto 101:7cff1c4259d7 4226 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
Kojto 101:7cff1c4259d7 4227 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
Kojto 101:7cff1c4259d7 4228
Kojto 101:7cff1c4259d7 4229 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
Kojto 101:7cff1c4259d7 4230 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4231 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4232 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4233 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4234 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 4235 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 4236 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 4237 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
Kojto 101:7cff1c4259d7 4238 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
Kojto 101:7cff1c4259d7 4239 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
Kojto 101:7cff1c4259d7 4240
Kojto 101:7cff1c4259d7 4241 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
Kojto 101:7cff1c4259d7 4242 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
Kojto 101:7cff1c4259d7 4243
Kojto 101:7cff1c4259d7 4244 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
Kojto 101:7cff1c4259d7 4245 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
Kojto 101:7cff1c4259d7 4246 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
Kojto 101:7cff1c4259d7 4247
Kojto 101:7cff1c4259d7 4248 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
Kojto 101:7cff1c4259d7 4249 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
Kojto 101:7cff1c4259d7 4250 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
Kojto 101:7cff1c4259d7 4251 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
Kojto 101:7cff1c4259d7 4252 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
Kojto 101:7cff1c4259d7 4253 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
Kojto 101:7cff1c4259d7 4254 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
Kojto 101:7cff1c4259d7 4255
Kojto 101:7cff1c4259d7 4256 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
Kojto 101:7cff1c4259d7 4257 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
Kojto 101:7cff1c4259d7 4258 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
Kojto 101:7cff1c4259d7 4259
Kojto 101:7cff1c4259d7 4260 /******************** Bit definition forUSB_OTG_CID register ********************/
Kojto 101:7cff1c4259d7 4261 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
Kojto 101:7cff1c4259d7 4262
Kojto 101:7cff1c4259d7 4263 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
Kojto 101:7cff1c4259d7 4264 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 101:7cff1c4259d7 4265 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 101:7cff1c4259d7 4266 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 101:7cff1c4259d7 4267 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 101:7cff1c4259d7 4268 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 101:7cff1c4259d7 4269 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 101:7cff1c4259d7 4270 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
Kojto 101:7cff1c4259d7 4271 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 101:7cff1c4259d7 4272 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
Kojto 101:7cff1c4259d7 4273
Kojto 101:7cff1c4259d7 4274 /******************** Bit definition forUSB_OTG_HPRT register ********************/
Kojto 101:7cff1c4259d7 4275 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
Kojto 101:7cff1c4259d7 4276 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
Kojto 101:7cff1c4259d7 4277 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
Kojto 101:7cff1c4259d7 4278 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
Kojto 101:7cff1c4259d7 4279 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
Kojto 101:7cff1c4259d7 4280 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
Kojto 101:7cff1c4259d7 4281 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
Kojto 101:7cff1c4259d7 4282 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
Kojto 101:7cff1c4259d7 4283 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
Kojto 101:7cff1c4259d7 4284
Kojto 101:7cff1c4259d7 4285 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
Kojto 101:7cff1c4259d7 4286 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4287 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4288 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
Kojto 101:7cff1c4259d7 4289
Kojto 101:7cff1c4259d7 4290 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
Kojto 101:7cff1c4259d7 4291 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4292 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4293 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4294 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4295
Kojto 101:7cff1c4259d7 4296 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
Kojto 101:7cff1c4259d7 4297 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4298 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4299
Kojto 101:7cff1c4259d7 4300 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
Kojto 101:7cff1c4259d7 4301 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 101:7cff1c4259d7 4302 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 101:7cff1c4259d7 4303 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
Kojto 101:7cff1c4259d7 4304 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 101:7cff1c4259d7 4305 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 101:7cff1c4259d7 4306 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 101:7cff1c4259d7 4307 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
Kojto 101:7cff1c4259d7 4308 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 101:7cff1c4259d7 4309 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
Kojto 101:7cff1c4259d7 4310 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
Kojto 101:7cff1c4259d7 4311 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
Kojto 101:7cff1c4259d7 4312
Kojto 101:7cff1c4259d7 4313 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
Kojto 101:7cff1c4259d7 4314 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
Kojto 101:7cff1c4259d7 4315 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
Kojto 101:7cff1c4259d7 4316
Kojto 101:7cff1c4259d7 4317 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
Kojto 101:7cff1c4259d7 4318 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
Kojto 101:7cff1c4259d7 4319 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
Kojto 101:7cff1c4259d7 4320 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
Kojto 101:7cff1c4259d7 4321 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
Kojto 101:7cff1c4259d7 4322
Kojto 101:7cff1c4259d7 4323 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 101:7cff1c4259d7 4324 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4325 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4326 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
Kojto 101:7cff1c4259d7 4327
Kojto 101:7cff1c4259d7 4328 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
Kojto 101:7cff1c4259d7 4329 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4330 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4331 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4332 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4333 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
Kojto 101:7cff1c4259d7 4334 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
Kojto 101:7cff1c4259d7 4335 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
Kojto 101:7cff1c4259d7 4336 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
Kojto 101:7cff1c4259d7 4337 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
Kojto 101:7cff1c4259d7 4338 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
Kojto 101:7cff1c4259d7 4339
Kojto 101:7cff1c4259d7 4340 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
Kojto 101:7cff1c4259d7 4341 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
Kojto 101:7cff1c4259d7 4342
Kojto 101:7cff1c4259d7 4343 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
Kojto 101:7cff1c4259d7 4344 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4345 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4346 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4347 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4348 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
Kojto 101:7cff1c4259d7 4349 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
Kojto 101:7cff1c4259d7 4350
Kojto 101:7cff1c4259d7 4351 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 101:7cff1c4259d7 4352 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4353 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4354
Kojto 101:7cff1c4259d7 4355 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
Kojto 101:7cff1c4259d7 4356 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4357 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4358
Kojto 101:7cff1c4259d7 4359 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
Kojto 101:7cff1c4259d7 4360 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4361 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4362 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4363 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4364 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 4365 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 4366 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 4367 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
Kojto 101:7cff1c4259d7 4368 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
Kojto 101:7cff1c4259d7 4369 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
Kojto 101:7cff1c4259d7 4370
Kojto 101:7cff1c4259d7 4371 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
Kojto 101:7cff1c4259d7 4372
Kojto 101:7cff1c4259d7 4373 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
Kojto 101:7cff1c4259d7 4374 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4375 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4376 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4377 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4378 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 4379 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 4380 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 4381
Kojto 101:7cff1c4259d7 4382 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
Kojto 101:7cff1c4259d7 4383 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4384 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4385 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
Kojto 101:7cff1c4259d7 4386 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
Kojto 101:7cff1c4259d7 4387 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
Kojto 101:7cff1c4259d7 4388 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
Kojto 101:7cff1c4259d7 4389 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
Kojto 101:7cff1c4259d7 4390
Kojto 101:7cff1c4259d7 4391 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
Kojto 101:7cff1c4259d7 4392 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4393 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4394 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
Kojto 101:7cff1c4259d7 4395 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
Kojto 101:7cff1c4259d7 4396
Kojto 101:7cff1c4259d7 4397 /******************** Bit definition forUSB_OTG_HCINT register ********************/
Kojto 101:7cff1c4259d7 4398 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
Kojto 101:7cff1c4259d7 4399 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
Kojto 101:7cff1c4259d7 4400 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
Kojto 101:7cff1c4259d7 4401 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
Kojto 101:7cff1c4259d7 4402 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
Kojto 101:7cff1c4259d7 4403 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
Kojto 101:7cff1c4259d7 4404 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
Kojto 101:7cff1c4259d7 4405 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
Kojto 101:7cff1c4259d7 4406 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
Kojto 101:7cff1c4259d7 4407 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
Kojto 101:7cff1c4259d7 4408 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
Kojto 101:7cff1c4259d7 4409
Kojto 101:7cff1c4259d7 4410 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
Kojto 101:7cff1c4259d7 4411 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
Kojto 101:7cff1c4259d7 4412 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
Kojto 101:7cff1c4259d7 4413 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
Kojto 101:7cff1c4259d7 4414 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
Kojto 101:7cff1c4259d7 4415 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
Kojto 101:7cff1c4259d7 4416 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
Kojto 101:7cff1c4259d7 4417 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
Kojto 101:7cff1c4259d7 4418 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
Kojto 101:7cff1c4259d7 4419 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
Kojto 101:7cff1c4259d7 4420 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
Kojto 101:7cff1c4259d7 4421 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
Kojto 101:7cff1c4259d7 4422
Kojto 101:7cff1c4259d7 4423 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
Kojto 101:7cff1c4259d7 4424 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
Kojto 101:7cff1c4259d7 4425 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
Kojto 101:7cff1c4259d7 4426 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
Kojto 101:7cff1c4259d7 4427 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
Kojto 101:7cff1c4259d7 4428 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
Kojto 101:7cff1c4259d7 4429 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
Kojto 101:7cff1c4259d7 4430 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
Kojto 101:7cff1c4259d7 4431 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
Kojto 101:7cff1c4259d7 4432 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
Kojto 101:7cff1c4259d7 4433 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
Kojto 101:7cff1c4259d7 4434 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
Kojto 101:7cff1c4259d7 4435
Kojto 101:7cff1c4259d7 4436 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
Kojto 101:7cff1c4259d7 4437
Kojto 101:7cff1c4259d7 4438 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 101:7cff1c4259d7 4439 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 101:7cff1c4259d7 4440 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
Kojto 101:7cff1c4259d7 4441 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
Kojto 101:7cff1c4259d7 4442 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 101:7cff1c4259d7 4443 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 101:7cff1c4259d7 4444 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
Kojto 101:7cff1c4259d7 4445 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
Kojto 101:7cff1c4259d7 4446 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4447 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4448
Kojto 101:7cff1c4259d7 4449 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
Kojto 101:7cff1c4259d7 4450 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
Kojto 101:7cff1c4259d7 4451
Kojto 101:7cff1c4259d7 4452 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
Kojto 101:7cff1c4259d7 4453 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
Kojto 101:7cff1c4259d7 4454
Kojto 101:7cff1c4259d7 4455 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
Kojto 101:7cff1c4259d7 4456 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
Kojto 101:7cff1c4259d7 4457
Kojto 101:7cff1c4259d7 4458 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
Kojto 101:7cff1c4259d7 4459 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
Kojto 101:7cff1c4259d7 4460 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
Kojto 101:7cff1c4259d7 4461
Kojto 101:7cff1c4259d7 4462 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
Kojto 101:7cff1c4259d7 4463
Kojto 101:7cff1c4259d7 4464 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4465 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
Kojto 101:7cff1c4259d7 4466 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
Kojto 101:7cff1c4259d7 4467 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
Kojto 101:7cff1c4259d7 4468 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
Kojto 101:7cff1c4259d7 4469 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 101:7cff1c4259d7 4470 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4471 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4472 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
Kojto 101:7cff1c4259d7 4473 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
Kojto 101:7cff1c4259d7 4474 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
Kojto 101:7cff1c4259d7 4475 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
Kojto 101:7cff1c4259d7 4476 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
Kojto 101:7cff1c4259d7 4477 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
Kojto 101:7cff1c4259d7 4478
Kojto 101:7cff1c4259d7 4479 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
Kojto 101:7cff1c4259d7 4480 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
Kojto 101:7cff1c4259d7 4481 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
Kojto 101:7cff1c4259d7 4482 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
Kojto 101:7cff1c4259d7 4483 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
Kojto 101:7cff1c4259d7 4484 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
Kojto 101:7cff1c4259d7 4485 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
Kojto 101:7cff1c4259d7 4486
Kojto 101:7cff1c4259d7 4487 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
Kojto 101:7cff1c4259d7 4488
Kojto 101:7cff1c4259d7 4489 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 101:7cff1c4259d7 4490 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 101:7cff1c4259d7 4491
Kojto 101:7cff1c4259d7 4492 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
Kojto 101:7cff1c4259d7 4493 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4494 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4495
Kojto 101:7cff1c4259d7 4496 /******************** Bit definition for PCGCCTL register ********************/
Kojto 101:7cff1c4259d7 4497 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
Kojto 101:7cff1c4259d7 4498 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 101:7cff1c4259d7 4499 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 101:7cff1c4259d7 4500
Kojto 101:7cff1c4259d7 4501 /**
Kojto 101:7cff1c4259d7 4502 * @}
Kojto 101:7cff1c4259d7 4503 */
Kojto 101:7cff1c4259d7 4504
Kojto 101:7cff1c4259d7 4505 /**
Kojto 101:7cff1c4259d7 4506 * @}
Kojto 101:7cff1c4259d7 4507 */
Kojto 101:7cff1c4259d7 4508
Kojto 101:7cff1c4259d7 4509 /** @addtogroup Exported_macros
Kojto 101:7cff1c4259d7 4510 * @{
Kojto 101:7cff1c4259d7 4511 */
Kojto 101:7cff1c4259d7 4512
Kojto 101:7cff1c4259d7 4513 /******************************* ADC Instances ********************************/
Kojto 101:7cff1c4259d7 4514 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 101:7cff1c4259d7 4515
Kojto 101:7cff1c4259d7 4516 /******************************* CRC Instances ********************************/
Kojto 101:7cff1c4259d7 4517 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 101:7cff1c4259d7 4518
Kojto 101:7cff1c4259d7 4519 /******************************** DMA Instances *******************************/
Kojto 101:7cff1c4259d7 4520 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
Kojto 101:7cff1c4259d7 4521 ((INSTANCE) == DMA1_Stream1) || \
Kojto 101:7cff1c4259d7 4522 ((INSTANCE) == DMA1_Stream2) || \
Kojto 101:7cff1c4259d7 4523 ((INSTANCE) == DMA1_Stream3) || \
Kojto 101:7cff1c4259d7 4524 ((INSTANCE) == DMA1_Stream4) || \
Kojto 101:7cff1c4259d7 4525 ((INSTANCE) == DMA1_Stream5) || \
Kojto 101:7cff1c4259d7 4526 ((INSTANCE) == DMA1_Stream6) || \
Kojto 101:7cff1c4259d7 4527 ((INSTANCE) == DMA1_Stream7) || \
Kojto 101:7cff1c4259d7 4528 ((INSTANCE) == DMA2_Stream0) || \
Kojto 101:7cff1c4259d7 4529 ((INSTANCE) == DMA2_Stream1) || \
Kojto 101:7cff1c4259d7 4530 ((INSTANCE) == DMA2_Stream2) || \
Kojto 101:7cff1c4259d7 4531 ((INSTANCE) == DMA2_Stream3) || \
Kojto 101:7cff1c4259d7 4532 ((INSTANCE) == DMA2_Stream4) || \
Kojto 101:7cff1c4259d7 4533 ((INSTANCE) == DMA2_Stream5) || \
Kojto 101:7cff1c4259d7 4534 ((INSTANCE) == DMA2_Stream6) || \
Kojto 101:7cff1c4259d7 4535 ((INSTANCE) == DMA2_Stream7))
Kojto 101:7cff1c4259d7 4536
Kojto 101:7cff1c4259d7 4537 /******************************* GPIO Instances *******************************/
Kojto 101:7cff1c4259d7 4538 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 101:7cff1c4259d7 4539 ((INSTANCE) == GPIOB) || \
Kojto 101:7cff1c4259d7 4540 ((INSTANCE) == GPIOC) || \
Kojto 101:7cff1c4259d7 4541 ((INSTANCE) == GPIOD) || \
Kojto 101:7cff1c4259d7 4542 ((INSTANCE) == GPIOE) || \
Kojto 101:7cff1c4259d7 4543 ((INSTANCE) == GPIOH))
Kojto 101:7cff1c4259d7 4544
Kojto 101:7cff1c4259d7 4545 /******************************** I2C Instances *******************************/
Kojto 101:7cff1c4259d7 4546 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 101:7cff1c4259d7 4547 ((INSTANCE) == I2C2) || \
Kojto 101:7cff1c4259d7 4548 ((INSTANCE) == I2C3))
Kojto 101:7cff1c4259d7 4549
Kojto 101:7cff1c4259d7 4550 /******************************** I2S Instances *******************************/
Kojto 101:7cff1c4259d7 4551 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 101:7cff1c4259d7 4552 ((INSTANCE) == SPI2) || \
Kojto 101:7cff1c4259d7 4553 ((INSTANCE) == SPI3) || \
Kojto 101:7cff1c4259d7 4554 ((INSTANCE) == SPI4) || \
Kojto 101:7cff1c4259d7 4555 ((INSTANCE) == SPI5))
Kojto 101:7cff1c4259d7 4556
Kojto 101:7cff1c4259d7 4557 /*************************** I2S Extended Instances ***************************/
Kojto 101:7cff1c4259d7 4558 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
Kojto 101:7cff1c4259d7 4559 ((INSTANCE) == SPI3) || \
Kojto 101:7cff1c4259d7 4560 ((INSTANCE) == I2S2ext) || \
Kojto 101:7cff1c4259d7 4561 ((INSTANCE) == I2S3ext))
Kojto 101:7cff1c4259d7 4562
Kojto 101:7cff1c4259d7 4563
Kojto 101:7cff1c4259d7 4564 /****************************** RTC Instances *********************************/
Kojto 101:7cff1c4259d7 4565 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 101:7cff1c4259d7 4566
Kojto 101:7cff1c4259d7 4567 /******************************** SPI Instances *******************************/
Kojto 101:7cff1c4259d7 4568 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 101:7cff1c4259d7 4569 ((INSTANCE) == SPI2) || \
Kojto 101:7cff1c4259d7 4570 ((INSTANCE) == SPI3) || \
Kojto 101:7cff1c4259d7 4571 ((INSTANCE) == SPI4) || \
Kojto 101:7cff1c4259d7 4572 ((INSTANCE) == SPI5))
Kojto 101:7cff1c4259d7 4573 /*************************** SPI Extended Instances ***************************/
Kojto 101:7cff1c4259d7 4574 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 101:7cff1c4259d7 4575 ((INSTANCE) == SPI2) || \
Kojto 101:7cff1c4259d7 4576 ((INSTANCE) == SPI3) || \
Kojto 101:7cff1c4259d7 4577 ((INSTANCE) == SPI4) || \
Kojto 101:7cff1c4259d7 4578 ((INSTANCE) == SPI5) || \
Kojto 101:7cff1c4259d7 4579 ((INSTANCE) == I2S2ext) || \
Kojto 101:7cff1c4259d7 4580 ((INSTANCE) == I2S3ext))
Kojto 101:7cff1c4259d7 4581
Kojto 101:7cff1c4259d7 4582 /****************** TIM Instances : All supported instances *******************/
Kojto 101:7cff1c4259d7 4583 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4584 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4585 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4586 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4587 ((INSTANCE) == TIM5) || \
Kojto 101:7cff1c4259d7 4588 ((INSTANCE) == TIM9) || \
Kojto 101:7cff1c4259d7 4589 ((INSTANCE) == TIM10) || \
Kojto 101:7cff1c4259d7 4590 ((INSTANCE) == TIM11))
Kojto 101:7cff1c4259d7 4591
Kojto 101:7cff1c4259d7 4592 /************* TIM Instances : at least 1 capture/compare channel *************/
Kojto 101:7cff1c4259d7 4593 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4594 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4595 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4596 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4597 ((INSTANCE) == TIM5) || \
Kojto 101:7cff1c4259d7 4598 ((INSTANCE) == TIM9) || \
Kojto 101:7cff1c4259d7 4599 ((INSTANCE) == TIM10) || \
Kojto 101:7cff1c4259d7 4600 ((INSTANCE) == TIM11))
Kojto 101:7cff1c4259d7 4601
Kojto 101:7cff1c4259d7 4602 /************ TIM Instances : at least 2 capture/compare channels *************/
Kojto 101:7cff1c4259d7 4603 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4604 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4605 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4606 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4607 ((INSTANCE) == TIM5) || \
Kojto 101:7cff1c4259d7 4608 ((INSTANCE) == TIM9))
Kojto 101:7cff1c4259d7 4609
Kojto 101:7cff1c4259d7 4610 /************ TIM Instances : at least 3 capture/compare channels *************/
Kojto 101:7cff1c4259d7 4611 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4612 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4613 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4614 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4615 ((INSTANCE) == TIM5))
Kojto 101:7cff1c4259d7 4616
Kojto 101:7cff1c4259d7 4617 /************ TIM Instances : at least 4 capture/compare channels *************/
Kojto 101:7cff1c4259d7 4618 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4619 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4620 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4621 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4622 ((INSTANCE) == TIM5))
Kojto 101:7cff1c4259d7 4623
Kojto 101:7cff1c4259d7 4624 /******************** TIM Instances : Advanced-control timers *****************/
Kojto 101:7cff1c4259d7 4625 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
Kojto 101:7cff1c4259d7 4626
Kojto 101:7cff1c4259d7 4627 /******************* TIM Instances : Timer input XOR function *****************/
Kojto 101:7cff1c4259d7 4628 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4629 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4630 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4631 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4632 ((INSTANCE) == TIM5))
Kojto 101:7cff1c4259d7 4633
Kojto 101:7cff1c4259d7 4634 /****************** TIM Instances : DMA requests generation (UDE) *************/
Kojto 101:7cff1c4259d7 4635 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4636 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4637 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4638 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4639 ((INSTANCE) == TIM5))
Kojto 101:7cff1c4259d7 4640
Kojto 101:7cff1c4259d7 4641 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
Kojto 101:7cff1c4259d7 4642 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4643 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4644 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4645 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4646 ((INSTANCE) == TIM5))
Kojto 101:7cff1c4259d7 4647
Kojto 101:7cff1c4259d7 4648 /************ TIM Instances : DMA requests generation (COMDE) *****************/
Kojto 101:7cff1c4259d7 4649 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4650 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4651 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4652 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4653 ((INSTANCE) == TIM5))
Kojto 101:7cff1c4259d7 4654
Kojto 101:7cff1c4259d7 4655 /******************** TIM Instances : DMA burst feature ***********************/
Kojto 101:7cff1c4259d7 4656 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4657 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4658 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4659 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4660 ((INSTANCE) == TIM5))
Kojto 101:7cff1c4259d7 4661
Kojto 101:7cff1c4259d7 4662 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
Kojto 101:7cff1c4259d7 4663 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4664 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4665 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4666 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4667 ((INSTANCE) == TIM5) || \
Kojto 101:7cff1c4259d7 4668 ((INSTANCE) == TIM9))
Kojto 101:7cff1c4259d7 4669
Kojto 101:7cff1c4259d7 4670 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
Kojto 101:7cff1c4259d7 4671 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4672 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4673 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4674 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4675 ((INSTANCE) == TIM5) || \
Kojto 101:7cff1c4259d7 4676 ((INSTANCE) == TIM9))
Kojto 101:7cff1c4259d7 4677
Kojto 101:7cff1c4259d7 4678 /********************** TIM Instances : 32 bit Counter ************************/
Kojto 101:7cff1c4259d7 4679 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4680 ((INSTANCE) == TIM5))
Kojto 101:7cff1c4259d7 4681
Kojto 101:7cff1c4259d7 4682 /***************** TIM Instances : external trigger input availabe ************/
Kojto 101:7cff1c4259d7 4683 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 101:7cff1c4259d7 4684 ((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4685 ((INSTANCE) == TIM3) || \
Kojto 101:7cff1c4259d7 4686 ((INSTANCE) == TIM4) || \
Kojto 101:7cff1c4259d7 4687 ((INSTANCE) == TIM5))
Kojto 101:7cff1c4259d7 4688
Kojto 101:7cff1c4259d7 4689 /****************** TIM Instances : remapping capability **********************/
Kojto 101:7cff1c4259d7 4690 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 101:7cff1c4259d7 4691 ((INSTANCE) == TIM5) || \
Kojto 101:7cff1c4259d7 4692 ((INSTANCE) == TIM11))
Kojto 101:7cff1c4259d7 4693
Kojto 101:7cff1c4259d7 4694 /******************* TIM Instances : output(s) available **********************/
Kojto 101:7cff1c4259d7 4695 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 101:7cff1c4259d7 4696 ((((INSTANCE) == TIM1) && \
Kojto 101:7cff1c4259d7 4697 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 101:7cff1c4259d7 4698 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 101:7cff1c4259d7 4699 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 101:7cff1c4259d7 4700 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 101:7cff1c4259d7 4701 || \
Kojto 101:7cff1c4259d7 4702 (((INSTANCE) == TIM2) && \
Kojto 101:7cff1c4259d7 4703 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 101:7cff1c4259d7 4704 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 101:7cff1c4259d7 4705 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 101:7cff1c4259d7 4706 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 101:7cff1c4259d7 4707 || \
Kojto 101:7cff1c4259d7 4708 (((INSTANCE) == TIM3) && \
Kojto 101:7cff1c4259d7 4709 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 101:7cff1c4259d7 4710 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 101:7cff1c4259d7 4711 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 101:7cff1c4259d7 4712 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 101:7cff1c4259d7 4713 || \
Kojto 101:7cff1c4259d7 4714 (((INSTANCE) == TIM4) && \
Kojto 101:7cff1c4259d7 4715 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 101:7cff1c4259d7 4716 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 101:7cff1c4259d7 4717 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 101:7cff1c4259d7 4718 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 101:7cff1c4259d7 4719 || \
Kojto 101:7cff1c4259d7 4720 (((INSTANCE) == TIM5) && \
Kojto 101:7cff1c4259d7 4721 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 101:7cff1c4259d7 4722 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 101:7cff1c4259d7 4723 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 101:7cff1c4259d7 4724 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 101:7cff1c4259d7 4725 || \
Kojto 101:7cff1c4259d7 4726 (((INSTANCE) == TIM9) && \
Kojto 101:7cff1c4259d7 4727 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 101:7cff1c4259d7 4728 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 101:7cff1c4259d7 4729 || \
Kojto 101:7cff1c4259d7 4730 (((INSTANCE) == TIM10) && \
Kojto 101:7cff1c4259d7 4731 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 101:7cff1c4259d7 4732 || \
Kojto 101:7cff1c4259d7 4733 (((INSTANCE) == TIM11) && \
Kojto 101:7cff1c4259d7 4734 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 101:7cff1c4259d7 4735
Kojto 101:7cff1c4259d7 4736 /************ TIM Instances : complementary output(s) available ***************/
Kojto 101:7cff1c4259d7 4737 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 101:7cff1c4259d7 4738 ((((INSTANCE) == TIM1) && \
Kojto 101:7cff1c4259d7 4739 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 101:7cff1c4259d7 4740 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 101:7cff1c4259d7 4741 ((CHANNEL) == TIM_CHANNEL_3))))
Kojto 101:7cff1c4259d7 4742
Kojto 101:7cff1c4259d7 4743 /******************** USART Instances : Synchronous mode **********************/
Kojto 101:7cff1c4259d7 4744 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 101:7cff1c4259d7 4745 ((INSTANCE) == USART2) || \
Kojto 101:7cff1c4259d7 4746 ((INSTANCE) == USART6))
Kojto 101:7cff1c4259d7 4747
Kojto 101:7cff1c4259d7 4748 /******************** UART Instances : Asynchronous mode **********************/
Kojto 101:7cff1c4259d7 4749 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 101:7cff1c4259d7 4750 ((INSTANCE) == USART2) || \
Kojto 101:7cff1c4259d7 4751 ((INSTANCE) == USART6))
Kojto 101:7cff1c4259d7 4752
Kojto 101:7cff1c4259d7 4753 /****************** UART Instances : Hardware Flow control ********************/
Kojto 101:7cff1c4259d7 4754 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 101:7cff1c4259d7 4755 ((INSTANCE) == USART2) || \
Kojto 101:7cff1c4259d7 4756 ((INSTANCE) == USART6))
Kojto 101:7cff1c4259d7 4757
Kojto 101:7cff1c4259d7 4758 /********************* UART Instances : Smard card mode ***********************/
Kojto 101:7cff1c4259d7 4759 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 101:7cff1c4259d7 4760 ((INSTANCE) == USART2) || \
Kojto 101:7cff1c4259d7 4761 ((INSTANCE) == USART6))
Kojto 101:7cff1c4259d7 4762
Kojto 101:7cff1c4259d7 4763 /*********************** UART Instances : IRDA mode ***************************/
Kojto 101:7cff1c4259d7 4764 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 101:7cff1c4259d7 4765 ((INSTANCE) == USART2) || \
Kojto 101:7cff1c4259d7 4766 ((INSTANCE) == USART6))
Kojto 101:7cff1c4259d7 4767
Kojto 101:7cff1c4259d7 4768 /****************************** IWDG Instances ********************************/
Kojto 101:7cff1c4259d7 4769 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 101:7cff1c4259d7 4770
Kojto 101:7cff1c4259d7 4771 /****************************** WWDG Instances ********************************/
Kojto 101:7cff1c4259d7 4772 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 101:7cff1c4259d7 4773
Kojto 101:7cff1c4259d7 4774 /****************************** SDIO Instances ********************************/
Kojto 101:7cff1c4259d7 4775 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
Kojto 101:7cff1c4259d7 4776
Kojto 101:7cff1c4259d7 4777 /****************************** USB Exported Constants ************************/
Kojto 101:7cff1c4259d7 4778 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
Kojto 101:7cff1c4259d7 4779 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
Kojto 101:7cff1c4259d7 4780 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
Kojto 101:7cff1c4259d7 4781 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
Kojto 101:7cff1c4259d7 4782
Kojto 101:7cff1c4259d7 4783 /**
Kojto 101:7cff1c4259d7 4784 * @}
Kojto 101:7cff1c4259d7 4785 */
Kojto 101:7cff1c4259d7 4786
Kojto 101:7cff1c4259d7 4787 /**
Kojto 101:7cff1c4259d7 4788 * @}
Kojto 101:7cff1c4259d7 4789 */
Kojto 101:7cff1c4259d7 4790
Kojto 101:7cff1c4259d7 4791 /**
Kojto 101:7cff1c4259d7 4792 * @}
Kojto 101:7cff1c4259d7 4793 */
Kojto 101:7cff1c4259d7 4794
Kojto 101:7cff1c4259d7 4795 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 4796 }
Kojto 101:7cff1c4259d7 4797 #endif /* __cplusplus */
Kojto 101:7cff1c4259d7 4798
Kojto 101:7cff1c4259d7 4799 #endif /* __STM32F411xE_H */
Kojto 101:7cff1c4259d7 4800
Kojto 101:7cff1c4259d7 4801
Kojto 101:7cff1c4259d7 4802
Kojto 101:7cff1c4259d7 4803 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/