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Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

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TARGET_NUCLEO_F746ZG/stm32f7xx_ll_fmc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 116:c0f6e94411f5

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	115:87f2f5183dfb	1	/**
Kojto	115:87f2f5183dfb	2	******************************************************************************
Kojto	115:87f2f5183dfb	3	* @file stm32f7xx_ll_fmc.h
Kojto	115:87f2f5183dfb	4	* @author MCD Application Team
Kojto	116:c0f6e94411f5	5	* @version V1.0.4
Kojto	116:c0f6e94411f5	6	* @date 09-December-2015
Kojto	115:87f2f5183dfb	7	* @brief Header file of FMC HAL module.
Kojto	115:87f2f5183dfb	8	******************************************************************************
Kojto	115:87f2f5183dfb	9	* @attention
Kojto	115:87f2f5183dfb	10	*
Kojto	115:87f2f5183dfb	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	115:87f2f5183dfb	12	*
Kojto	115:87f2f5183dfb	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	115:87f2f5183dfb	14	* are permitted provided that the following conditions are met:
Kojto	115:87f2f5183dfb	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	115:87f2f5183dfb	16	* this list of conditions and the following disclaimer.
Kojto	115:87f2f5183dfb	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	115:87f2f5183dfb	18	* this list of conditions and the following disclaimer in the documentation
Kojto	115:87f2f5183dfb	19	* and/or other materials provided with the distribution.
Kojto	115:87f2f5183dfb	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	115:87f2f5183dfb	21	* may be used to endorse or promote products derived from this software
Kojto	115:87f2f5183dfb	22	* without specific prior written permission.
Kojto	115:87f2f5183dfb	23	*
Kojto	115:87f2f5183dfb	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	115:87f2f5183dfb	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	115:87f2f5183dfb	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	115:87f2f5183dfb	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	115:87f2f5183dfb	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	115:87f2f5183dfb	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	115:87f2f5183dfb	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	115:87f2f5183dfb	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	115:87f2f5183dfb	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	115:87f2f5183dfb	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	115:87f2f5183dfb	34	*
Kojto	115:87f2f5183dfb	35	******************************************************************************
Kojto	115:87f2f5183dfb	36	*/
Kojto	115:87f2f5183dfb	37
Kojto	115:87f2f5183dfb	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	115:87f2f5183dfb	39	#ifndef __STM32F7xx_LL_FMC_H
Kojto	115:87f2f5183dfb	40	#define __STM32F7xx_LL_FMC_H
Kojto	115:87f2f5183dfb	41
Kojto	115:87f2f5183dfb	42	#ifdef __cplusplus
Kojto	115:87f2f5183dfb	43	extern "C" {
Kojto	115:87f2f5183dfb	44	#endif
Kojto	115:87f2f5183dfb	45
Kojto	115:87f2f5183dfb	46	/* Includes ------------------------------------------------------------------*/
Kojto	115:87f2f5183dfb	47	#include "stm32f7xx_hal_def.h"
Kojto	115:87f2f5183dfb	48
Kojto	115:87f2f5183dfb	49	/** @addtogroup STM32F7xx_HAL_Driver
Kojto	115:87f2f5183dfb	50	* @{
Kojto	115:87f2f5183dfb	51	*/
Kojto	115:87f2f5183dfb	52
Kojto	115:87f2f5183dfb	53	/** @addtogroup FMC_LL
Kojto	115:87f2f5183dfb	54	* @{
Kojto	115:87f2f5183dfb	55	*/
Kojto	115:87f2f5183dfb	56
Kojto	115:87f2f5183dfb	57	/** @addtogroup FMC_LL_Private_Macros
Kojto	115:87f2f5183dfb	58	* @{
Kojto	115:87f2f5183dfb	59	*/
Kojto	115:87f2f5183dfb	60	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
Kojto	115:87f2f5183dfb	61	((BANK) == FMC_NORSRAM_BANK2) \|\| \
Kojto	115:87f2f5183dfb	62	((BANK) == FMC_NORSRAM_BANK3) \|\| \
Kojto	115:87f2f5183dfb	63	((BANK) == FMC_NORSRAM_BANK4))
Kojto	115:87f2f5183dfb	64
Kojto	115:87f2f5183dfb	65	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	66	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
Kojto	115:87f2f5183dfb	67
Kojto	115:87f2f5183dfb	68	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
Kojto	115:87f2f5183dfb	69	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
Kojto	115:87f2f5183dfb	70	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
Kojto	115:87f2f5183dfb	71
Kojto	115:87f2f5183dfb	72	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	115:87f2f5183dfb	73	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	115:87f2f5183dfb	74	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto	115:87f2f5183dfb	75
Kojto	115:87f2f5183dfb	76	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
Kojto	115:87f2f5183dfb	77	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
Kojto	115:87f2f5183dfb	78	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
Kojto	115:87f2f5183dfb	79	((__MODE__) == FMC_ACCESS_MODE_D))
Kojto	115:87f2f5183dfb	80
Kojto	115:87f2f5183dfb	81	#define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)
Kojto	115:87f2f5183dfb	82
Kojto	115:87f2f5183dfb	83	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	84	((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))
Kojto	115:87f2f5183dfb	85
Kojto	115:87f2f5183dfb	86	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) \|\| \
Kojto	115:87f2f5183dfb	87	((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))
Kojto	115:87f2f5183dfb	88
Kojto	115:87f2f5183dfb	89	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	90	((STATE) == FMC_NAND_ECC_ENABLE))
Kojto	115:87f2f5183dfb	91
Kojto	115:87f2f5183dfb	92	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
Kojto	115:87f2f5183dfb	93	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
Kojto	115:87f2f5183dfb	94	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
Kojto	115:87f2f5183dfb	95	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
Kojto	115:87f2f5183dfb	96	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
Kojto	115:87f2f5183dfb	97	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto	115:87f2f5183dfb	98
Kojto	115:87f2f5183dfb	99	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	115:87f2f5183dfb	100	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	115:87f2f5183dfb	101	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
Kojto	115:87f2f5183dfb	102
Kojto	115:87f2f5183dfb	103	#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	104	((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
Kojto	115:87f2f5183dfb	105
Kojto	115:87f2f5183dfb	106	#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	107	((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
Kojto	115:87f2f5183dfb	108	((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
Kojto	115:87f2f5183dfb	109
Kojto	115:87f2f5183dfb	110	#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	111	((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
Kojto	115:87f2f5183dfb	112
Kojto	115:87f2f5183dfb	113	#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
Kojto	115:87f2f5183dfb	114	((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
Kojto	115:87f2f5183dfb	115	((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
Kojto	115:87f2f5183dfb	116
Kojto	115:87f2f5183dfb	117	#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
Kojto	115:87f2f5183dfb	118	((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	119	((__COMMAND__) == FMC_SDRAM_CMD_PALL) \|\| \
Kojto	115:87f2f5183dfb	120	((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
Kojto	115:87f2f5183dfb	121	((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
Kojto	115:87f2f5183dfb	122	((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
Kojto	115:87f2f5183dfb	123	((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
Kojto	115:87f2f5183dfb	124
Kojto	115:87f2f5183dfb	125	#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
Kojto	115:87f2f5183dfb	126	((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
Kojto	115:87f2f5183dfb	127	((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
Kojto	115:87f2f5183dfb	128
Kojto	115:87f2f5183dfb	129	/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
Kojto	115:87f2f5183dfb	130	* @{
Kojto	115:87f2f5183dfb	131	*/
Kojto	115:87f2f5183dfb	132	#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
Kojto	115:87f2f5183dfb	133	/**
Kojto	115:87f2f5183dfb	134	* @}
Kojto	115:87f2f5183dfb	135	*/
Kojto	115:87f2f5183dfb	136
Kojto	115:87f2f5183dfb	137	/** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time
Kojto	115:87f2f5183dfb	138	* @{
Kojto	115:87f2f5183dfb	139	*/
Kojto	115:87f2f5183dfb	140	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
Kojto	115:87f2f5183dfb	141	/**
Kojto	115:87f2f5183dfb	142	* @}
Kojto	115:87f2f5183dfb	143	*/
Kojto	115:87f2f5183dfb	144
Kojto	115:87f2f5183dfb	145	/** @defgroup FMC_Setup_Time FMC Setup Time
Kojto	115:87f2f5183dfb	146	* @{
Kojto	115:87f2f5183dfb	147	*/
Kojto	115:87f2f5183dfb	148	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254)
Kojto	115:87f2f5183dfb	149	/**
Kojto	115:87f2f5183dfb	150	* @}
Kojto	115:87f2f5183dfb	151	*/
Kojto	115:87f2f5183dfb	152
Kojto	115:87f2f5183dfb	153	/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time
Kojto	115:87f2f5183dfb	154	* @{
Kojto	115:87f2f5183dfb	155	*/
Kojto	115:87f2f5183dfb	156	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254)
Kojto	115:87f2f5183dfb	157	/**
Kojto	115:87f2f5183dfb	158	* @}
Kojto	115:87f2f5183dfb	159	*/
Kojto	115:87f2f5183dfb	160
Kojto	115:87f2f5183dfb	161	/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time
Kojto	115:87f2f5183dfb	162	* @{
Kojto	115:87f2f5183dfb	163	*/
Kojto	115:87f2f5183dfb	164	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254)
Kojto	115:87f2f5183dfb	165	/**
Kojto	115:87f2f5183dfb	166	* @}
Kojto	115:87f2f5183dfb	167	*/
Kojto	115:87f2f5183dfb	168
Kojto	115:87f2f5183dfb	169	/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time
Kojto	115:87f2f5183dfb	170	* @{
Kojto	115:87f2f5183dfb	171	*/
Kojto	115:87f2f5183dfb	172	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254)
Kojto	115:87f2f5183dfb	173	/**
Kojto	115:87f2f5183dfb	174	* @}
Kojto	115:87f2f5183dfb	175	*/
Kojto	115:87f2f5183dfb	176
Kojto	115:87f2f5183dfb	177	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	178	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
Kojto	115:87f2f5183dfb	179
Kojto	115:87f2f5183dfb	180	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
Kojto	115:87f2f5183dfb	181	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto	115:87f2f5183dfb	182
Kojto	115:87f2f5183dfb	183	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
Kojto	115:87f2f5183dfb	184	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
Kojto	115:87f2f5183dfb	185
Kojto	115:87f2f5183dfb	186	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	187	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
Kojto	115:87f2f5183dfb	188
Kojto	115:87f2f5183dfb	189	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	190	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
Kojto	115:87f2f5183dfb	191
Kojto	115:87f2f5183dfb	192	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	193	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
Kojto	115:87f2f5183dfb	194
Kojto	115:87f2f5183dfb	195	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	196	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto	115:87f2f5183dfb	197
Kojto	115:87f2f5183dfb	198	/** @defgroup FMC_Data_Latency FMC Data Latency
Kojto	115:87f2f5183dfb	199	* @{
Kojto	115:87f2f5183dfb	200	*/
Kojto	115:87f2f5183dfb	201	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
Kojto	115:87f2f5183dfb	202	/**
Kojto	115:87f2f5183dfb	203	* @}
Kojto	115:87f2f5183dfb	204	*/
Kojto	115:87f2f5183dfb	205
Kojto	115:87f2f5183dfb	206	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	207	((__BURST__) == FMC_WRITE_BURST_ENABLE))
Kojto	115:87f2f5183dfb	208
Kojto	115:87f2f5183dfb	209	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
Kojto	115:87f2f5183dfb	210	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto	115:87f2f5183dfb	211
Kojto	115:87f2f5183dfb	212
Kojto	115:87f2f5183dfb	213	/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
Kojto	115:87f2f5183dfb	214	* @{
Kojto	115:87f2f5183dfb	215	*/
Kojto	115:87f2f5183dfb	216	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
Kojto	115:87f2f5183dfb	217	/**
Kojto	115:87f2f5183dfb	218	* @}
Kojto	115:87f2f5183dfb	219	*/
Kojto	115:87f2f5183dfb	220
Kojto	115:87f2f5183dfb	221	/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
Kojto	115:87f2f5183dfb	222	* @{
Kojto	115:87f2f5183dfb	223	*/
Kojto	115:87f2f5183dfb	224	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
Kojto	115:87f2f5183dfb	225	/**
Kojto	115:87f2f5183dfb	226	* @}
Kojto	115:87f2f5183dfb	227	*/
Kojto	115:87f2f5183dfb	228
Kojto	115:87f2f5183dfb	229	/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
Kojto	115:87f2f5183dfb	230	* @{
Kojto	115:87f2f5183dfb	231	*/
Kojto	115:87f2f5183dfb	232	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
Kojto	115:87f2f5183dfb	233	/**
Kojto	115:87f2f5183dfb	234	* @}
Kojto	115:87f2f5183dfb	235	*/
Kojto	115:87f2f5183dfb	236
Kojto	115:87f2f5183dfb	237	/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
Kojto	115:87f2f5183dfb	238	* @{
Kojto	115:87f2f5183dfb	239	*/
Kojto	115:87f2f5183dfb	240	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
Kojto	115:87f2f5183dfb	241	/**
Kojto	115:87f2f5183dfb	242	* @}
Kojto	115:87f2f5183dfb	243	*/
Kojto	115:87f2f5183dfb	244
Kojto	115:87f2f5183dfb	245	/** @defgroup FMC_CLK_Division FMC CLK Division
Kojto	115:87f2f5183dfb	246	* @{
Kojto	115:87f2f5183dfb	247	*/
Kojto	115:87f2f5183dfb	248	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
Kojto	115:87f2f5183dfb	249	/**
Kojto	115:87f2f5183dfb	250	* @}
Kojto	115:87f2f5183dfb	251	*/
Kojto	115:87f2f5183dfb	252
Kojto	115:87f2f5183dfb	253	/** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay
Kojto	115:87f2f5183dfb	254	* @{
Kojto	115:87f2f5183dfb	255	*/
Kojto	115:87f2f5183dfb	256	#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
Kojto	115:87f2f5183dfb	257	/**
Kojto	115:87f2f5183dfb	258	* @}
Kojto	115:87f2f5183dfb	259	*/
Kojto	115:87f2f5183dfb	260
Kojto	115:87f2f5183dfb	261	/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay
Kojto	115:87f2f5183dfb	262	* @{
Kojto	115:87f2f5183dfb	263	*/
Kojto	115:87f2f5183dfb	264	#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
Kojto	115:87f2f5183dfb	265	/**
Kojto	115:87f2f5183dfb	266	* @}
Kojto	115:87f2f5183dfb	267	*/
Kojto	115:87f2f5183dfb	268
Kojto	115:87f2f5183dfb	269	/** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time
Kojto	115:87f2f5183dfb	270	* @{
Kojto	115:87f2f5183dfb	271	*/
Kojto	115:87f2f5183dfb	272	#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
Kojto	115:87f2f5183dfb	273	/**
Kojto	115:87f2f5183dfb	274	* @}
Kojto	115:87f2f5183dfb	275	*/
Kojto	115:87f2f5183dfb	276
Kojto	115:87f2f5183dfb	277	/** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay
Kojto	115:87f2f5183dfb	278	* @{
Kojto	115:87f2f5183dfb	279	*/
Kojto	115:87f2f5183dfb	280	#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
Kojto	115:87f2f5183dfb	281	/**
Kojto	115:87f2f5183dfb	282	* @}
Kojto	115:87f2f5183dfb	283	*/
Kojto	115:87f2f5183dfb	284
Kojto	115:87f2f5183dfb	285	/** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time
Kojto	115:87f2f5183dfb	286	* @{
Kojto	115:87f2f5183dfb	287	*/
Kojto	115:87f2f5183dfb	288	#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
Kojto	115:87f2f5183dfb	289	/**
Kojto	115:87f2f5183dfb	290	* @}
Kojto	115:87f2f5183dfb	291	*/
Kojto	115:87f2f5183dfb	292
Kojto	115:87f2f5183dfb	293	/** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay
Kojto	115:87f2f5183dfb	294	* @{
Kojto	115:87f2f5183dfb	295	*/
Kojto	115:87f2f5183dfb	296	#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
Kojto	115:87f2f5183dfb	297	/**
Kojto	115:87f2f5183dfb	298	* @}
Kojto	115:87f2f5183dfb	299	*/
Kojto	115:87f2f5183dfb	300
Kojto	115:87f2f5183dfb	301	/** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay
Kojto	115:87f2f5183dfb	302	* @{
Kojto	115:87f2f5183dfb	303	*/
Kojto	115:87f2f5183dfb	304	#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
Kojto	115:87f2f5183dfb	305	/**
Kojto	115:87f2f5183dfb	306	* @}
Kojto	115:87f2f5183dfb	307	*/
Kojto	115:87f2f5183dfb	308
Kojto	115:87f2f5183dfb	309	/** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number
Kojto	115:87f2f5183dfb	310	* @{
Kojto	115:87f2f5183dfb	311	*/
Kojto	115:87f2f5183dfb	312	#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))
Kojto	115:87f2f5183dfb	313	/**
Kojto	115:87f2f5183dfb	314	* @}
Kojto	115:87f2f5183dfb	315	*/
Kojto	115:87f2f5183dfb	316
Kojto	115:87f2f5183dfb	317	/** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition
Kojto	115:87f2f5183dfb	318	* @{
Kojto	115:87f2f5183dfb	319	*/
Kojto	115:87f2f5183dfb	320	#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)
Kojto	115:87f2f5183dfb	321	/**
Kojto	115:87f2f5183dfb	322	* @}
Kojto	115:87f2f5183dfb	323	*/
Kojto	115:87f2f5183dfb	324
Kojto	115:87f2f5183dfb	325	/** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate
Kojto	115:87f2f5183dfb	326	* @{
Kojto	115:87f2f5183dfb	327	*/
Kojto	115:87f2f5183dfb	328	#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)
Kojto	115:87f2f5183dfb	329	/**
Kojto	115:87f2f5183dfb	330	* @}
Kojto	115:87f2f5183dfb	331	*/
Kojto	115:87f2f5183dfb	332
Kojto	115:87f2f5183dfb	333	/** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance
Kojto	115:87f2f5183dfb	334	* @{
Kojto	115:87f2f5183dfb	335	*/
Kojto	115:87f2f5183dfb	336	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
Kojto	115:87f2f5183dfb	337	/**
Kojto	115:87f2f5183dfb	338	* @}
Kojto	115:87f2f5183dfb	339	*/
Kojto	115:87f2f5183dfb	340
Kojto	115:87f2f5183dfb	341	/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance
Kojto	115:87f2f5183dfb	342	* @{
Kojto	115:87f2f5183dfb	343	*/
Kojto	115:87f2f5183dfb	344	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
Kojto	115:87f2f5183dfb	345	/**
Kojto	115:87f2f5183dfb	346	* @}
Kojto	115:87f2f5183dfb	347	*/
Kojto	115:87f2f5183dfb	348
Kojto	115:87f2f5183dfb	349	/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
Kojto	115:87f2f5183dfb	350	* @{
Kojto	115:87f2f5183dfb	351	*/
Kojto	115:87f2f5183dfb	352	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
Kojto	115:87f2f5183dfb	353	/**
Kojto	115:87f2f5183dfb	354	* @}
Kojto	115:87f2f5183dfb	355	*/
Kojto	115:87f2f5183dfb	356
Kojto	115:87f2f5183dfb	357	/** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance
Kojto	115:87f2f5183dfb	358	* @{
Kojto	115:87f2f5183dfb	359	*/
Kojto	115:87f2f5183dfb	360	#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
Kojto	115:87f2f5183dfb	361	/**
Kojto	115:87f2f5183dfb	362	* @}
Kojto	115:87f2f5183dfb	363	*/
Kojto	115:87f2f5183dfb	364
Kojto	115:87f2f5183dfb	365	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
Kojto	115:87f2f5183dfb	366	((BANK) == FMC_SDRAM_BANK2))
Kojto	115:87f2f5183dfb	367
Kojto	115:87f2f5183dfb	368	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
Kojto	115:87f2f5183dfb	369	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
Kojto	115:87f2f5183dfb	370	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
Kojto	115:87f2f5183dfb	371	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
Kojto	115:87f2f5183dfb	372
Kojto	115:87f2f5183dfb	373	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
Kojto	115:87f2f5183dfb	374	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
Kojto	115:87f2f5183dfb	375	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
Kojto	115:87f2f5183dfb	376
Kojto	115:87f2f5183dfb	377	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
Kojto	115:87f2f5183dfb	378	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
Kojto	115:87f2f5183dfb	379
Kojto	115:87f2f5183dfb	380
Kojto	115:87f2f5183dfb	381	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
Kojto	115:87f2f5183dfb	382	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
Kojto	115:87f2f5183dfb	383	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
Kojto	115:87f2f5183dfb	384
Kojto	115:87f2f5183dfb	385	#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) \|\| \
Kojto	115:87f2f5183dfb	386	((__SIZE__) == FMC_PAGE_SIZE_128) \|\| \
Kojto	115:87f2f5183dfb	387	((__SIZE__) == FMC_PAGE_SIZE_256) \|\| \
Kojto	116:c0f6e94411f5	388	((__SIZE__) == FMC_PAGE_SIZE_512) \|\| \
Kojto	115:87f2f5183dfb	389	((__SIZE__) == FMC_PAGE_SIZE_1024))
Kojto	115:87f2f5183dfb	390
Kojto	115:87f2f5183dfb	391	#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) \|\| \
Kojto	115:87f2f5183dfb	392	((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
Kojto	115:87f2f5183dfb	393	/**
Kojto	115:87f2f5183dfb	394	* @}
Kojto	115:87f2f5183dfb	395	*/
Kojto	115:87f2f5183dfb	396
Kojto	115:87f2f5183dfb	397	/* Exported typedef ----------------------------------------------------------*/
Kojto	115:87f2f5183dfb	398	/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types
Kojto	115:87f2f5183dfb	399	* @{
Kojto	115:87f2f5183dfb	400	*/
Kojto	115:87f2f5183dfb	401	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
Kojto	115:87f2f5183dfb	402	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
Kojto	115:87f2f5183dfb	403	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
Kojto	115:87f2f5183dfb	404	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
Kojto	115:87f2f5183dfb	405
Kojto	115:87f2f5183dfb	406	#define FMC_NORSRAM_DEVICE FMC_Bank1
Kojto	115:87f2f5183dfb	407	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
Kojto	115:87f2f5183dfb	408	#define FMC_NAND_DEVICE FMC_Bank3
Kojto	115:87f2f5183dfb	409	#define FMC_SDRAM_DEVICE FMC_Bank5_6
Kojto	115:87f2f5183dfb	410
Kojto	115:87f2f5183dfb	411	/**
Kojto	115:87f2f5183dfb	412	* @brief FMC NORSRAM Configuration Structure definition
Kojto	115:87f2f5183dfb	413	*/
Kojto	115:87f2f5183dfb	414	typedef struct
Kojto	115:87f2f5183dfb	415	{
Kojto	115:87f2f5183dfb	416	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
Kojto	115:87f2f5183dfb	417	This parameter can be a value of @ref FMC_NORSRAM_Bank */
Kojto	115:87f2f5183dfb	418
Kojto	115:87f2f5183dfb	419	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
Kojto	115:87f2f5183dfb	420	multiplexed on the data bus or not.
Kojto	115:87f2f5183dfb	421	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
Kojto	115:87f2f5183dfb	422
Kojto	115:87f2f5183dfb	423	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
Kojto	115:87f2f5183dfb	424	the corresponding memory device.
Kojto	115:87f2f5183dfb	425	This parameter can be a value of @ref FMC_Memory_Type */
Kojto	115:87f2f5183dfb	426
Kojto	115:87f2f5183dfb	427	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto	115:87f2f5183dfb	428	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
Kojto	115:87f2f5183dfb	429
Kojto	115:87f2f5183dfb	430	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
Kojto	115:87f2f5183dfb	431	valid only with synchronous burst Flash memories.
Kojto	115:87f2f5183dfb	432	This parameter can be a value of @ref FMC_Burst_Access_Mode */
Kojto	115:87f2f5183dfb	433
Kojto	115:87f2f5183dfb	434	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
Kojto	115:87f2f5183dfb	435	the Flash memory in burst mode.
Kojto	115:87f2f5183dfb	436	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
Kojto	115:87f2f5183dfb	437
Kojto	115:87f2f5183dfb	438	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
Kojto	115:87f2f5183dfb	439	clock cycle before the wait state or during the wait state,
Kojto	115:87f2f5183dfb	440	valid only when accessing memories in burst mode.
Kojto	115:87f2f5183dfb	441	This parameter can be a value of @ref FMC_Wait_Timing */
Kojto	115:87f2f5183dfb	442
Kojto	115:87f2f5183dfb	443	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
Kojto	115:87f2f5183dfb	444	This parameter can be a value of @ref FMC_Write_Operation */
Kojto	115:87f2f5183dfb	445
Kojto	115:87f2f5183dfb	446	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
Kojto	115:87f2f5183dfb	447	signal, valid for Flash memory access in burst mode.
Kojto	115:87f2f5183dfb	448	This parameter can be a value of @ref FMC_Wait_Signal */
Kojto	115:87f2f5183dfb	449
Kojto	115:87f2f5183dfb	450	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
Kojto	115:87f2f5183dfb	451	This parameter can be a value of @ref FMC_Extended_Mode */
Kojto	115:87f2f5183dfb	452
Kojto	115:87f2f5183dfb	453	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
Kojto	115:87f2f5183dfb	454	valid only with asynchronous Flash memories.
Kojto	115:87f2f5183dfb	455	This parameter can be a value of @ref FMC_AsynchronousWait */
Kojto	115:87f2f5183dfb	456
Kojto	115:87f2f5183dfb	457	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
Kojto	115:87f2f5183dfb	458	This parameter can be a value of @ref FMC_Write_Burst */
Kojto	115:87f2f5183dfb	459
Kojto	115:87f2f5183dfb	460	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
Kojto	115:87f2f5183dfb	461	This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto	115:87f2f5183dfb	462	through FMC_BCR2..4 registers.
Kojto	115:87f2f5183dfb	463	This parameter can be a value of @ref FMC_Continous_Clock */
Kojto	115:87f2f5183dfb	464
Kojto	115:87f2f5183dfb	465	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto	115:87f2f5183dfb	466	This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto	115:87f2f5183dfb	467	through FMC_BCR2..4 registers.
Kojto	115:87f2f5183dfb	468	This parameter can be a value of @ref FMC_Write_FIFO */
Kojto	115:87f2f5183dfb	469
Kojto	115:87f2f5183dfb	470	uint32_t PageSize; /*!< Specifies the memory page size.
Kojto	115:87f2f5183dfb	471	This parameter can be a value of @ref FMC_Page_Size */
Kojto	115:87f2f5183dfb	472
Kojto	115:87f2f5183dfb	473	}FMC_NORSRAM_InitTypeDef;
Kojto	115:87f2f5183dfb	474
Kojto	115:87f2f5183dfb	475	/**
Kojto	115:87f2f5183dfb	476	* @brief FMC NORSRAM Timing parameters structure definition
Kojto	115:87f2f5183dfb	477	*/
Kojto	115:87f2f5183dfb	478	typedef struct
Kojto	115:87f2f5183dfb	479	{
Kojto	115:87f2f5183dfb	480	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto	115:87f2f5183dfb	481	the duration of the address setup time.
Kojto	115:87f2f5183dfb	482	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto	115:87f2f5183dfb	483	@note This parameter is not used with synchronous NOR Flash memories. */
Kojto	115:87f2f5183dfb	484
Kojto	115:87f2f5183dfb	485	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
Kojto	115:87f2f5183dfb	486	the duration of the address hold time.
Kojto	115:87f2f5183dfb	487	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
Kojto	115:87f2f5183dfb	488	@note This parameter is not used with synchronous NOR Flash memories. */
Kojto	115:87f2f5183dfb	489
Kojto	115:87f2f5183dfb	490	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto	115:87f2f5183dfb	491	the duration of the data setup time.
Kojto	115:87f2f5183dfb	492	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
Kojto	115:87f2f5183dfb	493	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
Kojto	115:87f2f5183dfb	494	NOR Flash memories. */
Kojto	115:87f2f5183dfb	495
Kojto	115:87f2f5183dfb	496	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
Kojto	115:87f2f5183dfb	497	the duration of the bus turnaround.
Kojto	115:87f2f5183dfb	498	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto	115:87f2f5183dfb	499	@note This parameter is only used for multiplexed NOR Flash memories. */
Kojto	115:87f2f5183dfb	500
Kojto	115:87f2f5183dfb	501	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
Kojto	115:87f2f5183dfb	502	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
Kojto	115:87f2f5183dfb	503	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
Kojto	115:87f2f5183dfb	504	accesses. */
Kojto	115:87f2f5183dfb	505
Kojto	115:87f2f5183dfb	506	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
Kojto	115:87f2f5183dfb	507	to the memory before getting the first data.
Kojto	115:87f2f5183dfb	508	The parameter value depends on the memory type as shown below:
Kojto	115:87f2f5183dfb	509	- It must be set to 0 in case of a CRAM
Kojto	115:87f2f5183dfb	510	- It is don't care in asynchronous NOR, SRAM or ROM accesses
Kojto	115:87f2f5183dfb	511	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
Kojto	115:87f2f5183dfb	512	with synchronous burst mode enable */
Kojto	115:87f2f5183dfb	513
Kojto	115:87f2f5183dfb	514	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
Kojto	115:87f2f5183dfb	515	This parameter can be a value of @ref FMC_Access_Mode */
Kojto	115:87f2f5183dfb	516	}FMC_NORSRAM_TimingTypeDef;
Kojto	115:87f2f5183dfb	517
Kojto	115:87f2f5183dfb	518	/**
Kojto	115:87f2f5183dfb	519	* @brief FMC NAND Configuration Structure definition
Kojto	115:87f2f5183dfb	520	*/
Kojto	115:87f2f5183dfb	521	typedef struct
Kojto	115:87f2f5183dfb	522	{
Kojto	115:87f2f5183dfb	523	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
Kojto	115:87f2f5183dfb	524	This parameter can be a value of @ref FMC_NAND_Bank */
Kojto	115:87f2f5183dfb	525
Kojto	115:87f2f5183dfb	526	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
Kojto	115:87f2f5183dfb	527	This parameter can be any value of @ref FMC_Wait_feature */
Kojto	115:87f2f5183dfb	528
Kojto	115:87f2f5183dfb	529	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto	115:87f2f5183dfb	530	This parameter can be any value of @ref FMC_NAND_Data_Width */
Kojto	115:87f2f5183dfb	531
Kojto	115:87f2f5183dfb	532	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
Kojto	115:87f2f5183dfb	533	This parameter can be any value of @ref FMC_ECC */
Kojto	115:87f2f5183dfb	534
Kojto	115:87f2f5183dfb	535	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
Kojto	115:87f2f5183dfb	536	This parameter can be any value of @ref FMC_ECC_Page_Size */
Kojto	115:87f2f5183dfb	537
Kojto	115:87f2f5183dfb	538	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	115:87f2f5183dfb	539	delay between CLE low and RE low.
Kojto	115:87f2f5183dfb	540	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto	115:87f2f5183dfb	541
Kojto	115:87f2f5183dfb	542	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	115:87f2f5183dfb	543	delay between ALE low and RE low.
Kojto	115:87f2f5183dfb	544	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	115:87f2f5183dfb	545	}FMC_NAND_InitTypeDef;
Kojto	115:87f2f5183dfb	546
Kojto	115:87f2f5183dfb	547	/**
Kojto	115:87f2f5183dfb	548	* @brief FMC NAND Timing parameters structure definition
Kojto	115:87f2f5183dfb	549	*/
Kojto	115:87f2f5183dfb	550	typedef struct
Kojto	115:87f2f5183dfb	551	{
Kojto	115:87f2f5183dfb	552	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
Kojto	115:87f2f5183dfb	553	the command assertion for NAND-Flash read or write access
Kojto	115:87f2f5183dfb	554	to common/Attribute or I/O memory space (depending on
Kojto	115:87f2f5183dfb	555	the memory space timing to be configured).
Kojto	115:87f2f5183dfb	556	This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
Kojto	115:87f2f5183dfb	557
Kojto	115:87f2f5183dfb	558	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
Kojto	115:87f2f5183dfb	559	command for NAND-Flash read or write access to
Kojto	115:87f2f5183dfb	560	common/Attribute or I/O memory space (depending on the
Kojto	115:87f2f5183dfb	561	memory space timing to be configured).
Kojto	115:87f2f5183dfb	562	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
Kojto	115:87f2f5183dfb	563
Kojto	115:87f2f5183dfb	564	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
Kojto	115:87f2f5183dfb	565	(and data for write access) after the command de-assertion
Kojto	115:87f2f5183dfb	566	for NAND-Flash read or write access to common/Attribute
Kojto	115:87f2f5183dfb	567	or I/O memory space (depending on the memory space timing
Kojto	115:87f2f5183dfb	568	to be configured).
Kojto	115:87f2f5183dfb	569	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
Kojto	115:87f2f5183dfb	570
Kojto	115:87f2f5183dfb	571	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
Kojto	115:87f2f5183dfb	572	data bus is kept in HiZ after the start of a NAND-Flash
Kojto	115:87f2f5183dfb	573	write access to common/Attribute or I/O memory space (depending
Kojto	115:87f2f5183dfb	574	on the memory space timing to be configured).
Kojto	115:87f2f5183dfb	575	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
Kojto	115:87f2f5183dfb	576	}FMC_NAND_PCC_TimingTypeDef;
Kojto	115:87f2f5183dfb	577
Kojto	115:87f2f5183dfb	578	/**
Kojto	115:87f2f5183dfb	579	* @brief FMC SDRAM Configuration Structure definition
Kojto	115:87f2f5183dfb	580	*/
Kojto	115:87f2f5183dfb	581	typedef struct
Kojto	115:87f2f5183dfb	582	{
Kojto	115:87f2f5183dfb	583	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
Kojto	115:87f2f5183dfb	584	This parameter can be a value of @ref FMC_SDRAM_Bank */
Kojto	115:87f2f5183dfb	585
Kojto	115:87f2f5183dfb	586	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
Kojto	115:87f2f5183dfb	587	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
Kojto	115:87f2f5183dfb	588
Kojto	115:87f2f5183dfb	589	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
Kojto	115:87f2f5183dfb	590	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
Kojto	115:87f2f5183dfb	591
Kojto	115:87f2f5183dfb	592	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
Kojto	115:87f2f5183dfb	593	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
Kojto	115:87f2f5183dfb	594
Kojto	115:87f2f5183dfb	595	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
Kojto	115:87f2f5183dfb	596	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
Kojto	115:87f2f5183dfb	597
Kojto	115:87f2f5183dfb	598	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
Kojto	115:87f2f5183dfb	599	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
Kojto	115:87f2f5183dfb	600
Kojto	115:87f2f5183dfb	601	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
Kojto	115:87f2f5183dfb	602	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
Kojto	115:87f2f5183dfb	603
Kojto	115:87f2f5183dfb	604	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
Kojto	115:87f2f5183dfb	605	to disable the clock before changing frequency.
Kojto	115:87f2f5183dfb	606	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
Kojto	115:87f2f5183dfb	607
Kojto	115:87f2f5183dfb	608	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
Kojto	115:87f2f5183dfb	609	commands during the CAS latency and stores data in the Read FIFO.
Kojto	115:87f2f5183dfb	610	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
Kojto	115:87f2f5183dfb	611
Kojto	115:87f2f5183dfb	612	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
Kojto	115:87f2f5183dfb	613	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
Kojto	115:87f2f5183dfb	614	}FMC_SDRAM_InitTypeDef;
Kojto	115:87f2f5183dfb	615
Kojto	115:87f2f5183dfb	616	/**
Kojto	115:87f2f5183dfb	617	* @brief FMC SDRAM Timing parameters structure definition
Kojto	115:87f2f5183dfb	618	*/
Kojto	115:87f2f5183dfb	619	typedef struct
Kojto	115:87f2f5183dfb	620	{
Kojto	115:87f2f5183dfb	621	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
Kojto	115:87f2f5183dfb	622	an active or Refresh command in number of memory clock cycles.
Kojto	115:87f2f5183dfb	623	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	115:87f2f5183dfb	624
Kojto	115:87f2f5183dfb	625	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
Kojto	115:87f2f5183dfb	626	issuing the Activate command in number of memory clock cycles.
Kojto	115:87f2f5183dfb	627	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	115:87f2f5183dfb	628
Kojto	115:87f2f5183dfb	629	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
Kojto	115:87f2f5183dfb	630	cycles.
Kojto	115:87f2f5183dfb	631	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	115:87f2f5183dfb	632
Kojto	115:87f2f5183dfb	633	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
Kojto	115:87f2f5183dfb	634	and the delay between two consecutive Refresh commands in number of
Kojto	115:87f2f5183dfb	635	memory clock cycles.
Kojto	115:87f2f5183dfb	636	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	115:87f2f5183dfb	637
Kojto	115:87f2f5183dfb	638	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
Kojto	115:87f2f5183dfb	639	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	115:87f2f5183dfb	640
Kojto	115:87f2f5183dfb	641	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
Kojto	115:87f2f5183dfb	642	in number of memory clock cycles.
Kojto	115:87f2f5183dfb	643	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	115:87f2f5183dfb	644
Kojto	115:87f2f5183dfb	645	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
Kojto	115:87f2f5183dfb	646	command in number of memory clock cycles.
Kojto	115:87f2f5183dfb	647	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	115:87f2f5183dfb	648	}FMC_SDRAM_TimingTypeDef;
Kojto	115:87f2f5183dfb	649
Kojto	115:87f2f5183dfb	650	/**
Kojto	115:87f2f5183dfb	651	* @brief SDRAM command parameters structure definition
Kojto	115:87f2f5183dfb	652	*/
Kojto	115:87f2f5183dfb	653	typedef struct
Kojto	115:87f2f5183dfb	654	{
Kojto	115:87f2f5183dfb	655	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
Kojto	115:87f2f5183dfb	656	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
Kojto	115:87f2f5183dfb	657
Kojto	115:87f2f5183dfb	658	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
Kojto	115:87f2f5183dfb	659	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
Kojto	115:87f2f5183dfb	660
Kojto	115:87f2f5183dfb	661	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
Kojto	115:87f2f5183dfb	662	in auto refresh mode.
Kojto	115:87f2f5183dfb	663	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	115:87f2f5183dfb	664	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
Kojto	115:87f2f5183dfb	665	}FMC_SDRAM_CommandTypeDef;
Kojto	115:87f2f5183dfb	666	/**
Kojto	115:87f2f5183dfb	667	* @}
Kojto	115:87f2f5183dfb	668	*/
Kojto	115:87f2f5183dfb	669
Kojto	115:87f2f5183dfb	670	/* Exported constants --------------------------------------------------------*/
Kojto	115:87f2f5183dfb	671	/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
Kojto	115:87f2f5183dfb	672	* @{
Kojto	115:87f2f5183dfb	673	*/
Kojto	115:87f2f5183dfb	674
Kojto	115:87f2f5183dfb	675	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
Kojto	115:87f2f5183dfb	676	* @{
Kojto	115:87f2f5183dfb	677	*/
Kojto	115:87f2f5183dfb	678
Kojto	115:87f2f5183dfb	679	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
Kojto	115:87f2f5183dfb	680	* @{
Kojto	115:87f2f5183dfb	681	*/
Kojto	115:87f2f5183dfb	682	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	683	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	684	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	685	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
Kojto	115:87f2f5183dfb	686	/**
Kojto	115:87f2f5183dfb	687	* @}
Kojto	115:87f2f5183dfb	688	*/
Kojto	115:87f2f5183dfb	689
Kojto	115:87f2f5183dfb	690	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
Kojto	115:87f2f5183dfb	691	* @{
Kojto	115:87f2f5183dfb	692	*/
Kojto	115:87f2f5183dfb	693	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	694	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	695	/**
Kojto	115:87f2f5183dfb	696	* @}
Kojto	115:87f2f5183dfb	697	*/
Kojto	115:87f2f5183dfb	698
Kojto	115:87f2f5183dfb	699	/** @defgroup FMC_Memory_Type FMC Memory Type
Kojto	115:87f2f5183dfb	700	* @{
Kojto	115:87f2f5183dfb	701	*/
Kojto	115:87f2f5183dfb	702	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	703	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	704	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	705	/**
Kojto	115:87f2f5183dfb	706	* @}
Kojto	115:87f2f5183dfb	707	*/
Kojto	115:87f2f5183dfb	708
Kojto	115:87f2f5183dfb	709	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
Kojto	115:87f2f5183dfb	710	* @{
Kojto	115:87f2f5183dfb	711	*/
Kojto	115:87f2f5183dfb	712	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	713	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	714	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	715	/**
Kojto	115:87f2f5183dfb	716	* @}
Kojto	115:87f2f5183dfb	717	*/
Kojto	115:87f2f5183dfb	718
Kojto	115:87f2f5183dfb	719	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
Kojto	115:87f2f5183dfb	720	* @{
Kojto	115:87f2f5183dfb	721	*/
Kojto	115:87f2f5183dfb	722	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	723	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	724	/**
Kojto	115:87f2f5183dfb	725	* @}
Kojto	115:87f2f5183dfb	726	*/
Kojto	115:87f2f5183dfb	727
Kojto	115:87f2f5183dfb	728	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
Kojto	115:87f2f5183dfb	729	* @{
Kojto	115:87f2f5183dfb	730	*/
Kojto	115:87f2f5183dfb	731	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	732	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	733	/**
Kojto	115:87f2f5183dfb	734	* @}
Kojto	115:87f2f5183dfb	735	*/
Kojto	115:87f2f5183dfb	736
Kojto	115:87f2f5183dfb	737	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
Kojto	115:87f2f5183dfb	738	* @{
Kojto	115:87f2f5183dfb	739	*/
Kojto	115:87f2f5183dfb	740	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	741	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	742	/**
Kojto	115:87f2f5183dfb	743	* @}
Kojto	115:87f2f5183dfb	744	*/
Kojto	115:87f2f5183dfb	745
Kojto	115:87f2f5183dfb	746	/** @defgroup FMC_Wait_Timing FMC Wait Timing
Kojto	115:87f2f5183dfb	747	* @{
Kojto	115:87f2f5183dfb	748	*/
Kojto	115:87f2f5183dfb	749	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	750	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	751	/**
Kojto	115:87f2f5183dfb	752	* @}
Kojto	115:87f2f5183dfb	753	*/
Kojto	115:87f2f5183dfb	754
Kojto	115:87f2f5183dfb	755	/** @defgroup FMC_Write_Operation FMC Write Operation
Kojto	115:87f2f5183dfb	756	* @{
Kojto	115:87f2f5183dfb	757	*/
Kojto	115:87f2f5183dfb	758	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	759	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	760	/**
Kojto	115:87f2f5183dfb	761	* @}
Kojto	115:87f2f5183dfb	762	*/
Kojto	115:87f2f5183dfb	763
Kojto	115:87f2f5183dfb	764	/** @defgroup FMC_Wait_Signal FMC Wait Signal
Kojto	115:87f2f5183dfb	765	* @{
Kojto	115:87f2f5183dfb	766	*/
Kojto	115:87f2f5183dfb	767	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	768	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	769	/**
Kojto	115:87f2f5183dfb	770	* @}
Kojto	115:87f2f5183dfb	771	*/
Kojto	115:87f2f5183dfb	772
Kojto	115:87f2f5183dfb	773	/** @defgroup FMC_Extended_Mode FMC Extended Mode
Kojto	115:87f2f5183dfb	774	* @{
Kojto	115:87f2f5183dfb	775	*/
Kojto	115:87f2f5183dfb	776	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	777	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	778	/**
Kojto	115:87f2f5183dfb	779	* @}
Kojto	115:87f2f5183dfb	780	*/
Kojto	115:87f2f5183dfb	781
Kojto	115:87f2f5183dfb	782	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
Kojto	115:87f2f5183dfb	783	* @{
Kojto	115:87f2f5183dfb	784	*/
Kojto	115:87f2f5183dfb	785	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	786	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	787	/**
Kojto	115:87f2f5183dfb	788	* @}
Kojto	115:87f2f5183dfb	789	*/
Kojto	115:87f2f5183dfb	790
Kojto	115:87f2f5183dfb	791	/** @defgroup FMC_Page_Size FMC Page Size
Kojto	115:87f2f5183dfb	792	* @{
Kojto	115:87f2f5183dfb	793	*/
Kojto	115:87f2f5183dfb	794	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	795	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
Kojto	115:87f2f5183dfb	796	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
Kojto	116:c0f6e94411f5	797	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 \| FMC_BCR1_CPSIZE_1))
Kojto	115:87f2f5183dfb	798	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
Kojto	115:87f2f5183dfb	799	/**
Kojto	115:87f2f5183dfb	800	* @}
Kojto	115:87f2f5183dfb	801	*/
Kojto	115:87f2f5183dfb	802
Kojto	115:87f2f5183dfb	803	/** @defgroup FMC_Write_Burst FMC Write Burst
Kojto	115:87f2f5183dfb	804	* @{
Kojto	115:87f2f5183dfb	805	*/
Kojto	115:87f2f5183dfb	806	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	807	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	808	/**
Kojto	115:87f2f5183dfb	809	* @}
Kojto	115:87f2f5183dfb	810	*/
Kojto	115:87f2f5183dfb	811
Kojto	115:87f2f5183dfb	812	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
Kojto	115:87f2f5183dfb	813	* @{
Kojto	115:87f2f5183dfb	814	*/
Kojto	115:87f2f5183dfb	815	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	816	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	817	/**
Kojto	115:87f2f5183dfb	818	* @}
Kojto	115:87f2f5183dfb	819	*/
Kojto	115:87f2f5183dfb	820
Kojto	115:87f2f5183dfb	821	/** @defgroup FMC_Write_FIFO FMC Write FIFO
Kojto	115:87f2f5183dfb	822	* @{
Kojto	115:87f2f5183dfb	823	*/
Kojto	116:c0f6e94411f5	824	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
Kojto	116:c0f6e94411f5	825	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	826	/**
Kojto	115:87f2f5183dfb	827	* @}
Kojto	115:87f2f5183dfb	828	*/
Kojto	115:87f2f5183dfb	829
Kojto	115:87f2f5183dfb	830	/** @defgroup FMC_Access_Mode FMC Access Mode
Kojto	115:87f2f5183dfb	831	* @{
Kojto	115:87f2f5183dfb	832	*/
Kojto	115:87f2f5183dfb	833	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	834	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	835	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	836	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
Kojto	115:87f2f5183dfb	837	/**
Kojto	115:87f2f5183dfb	838	* @}
Kojto	115:87f2f5183dfb	839	*/
Kojto	115:87f2f5183dfb	840
Kojto	115:87f2f5183dfb	841	/**
Kojto	115:87f2f5183dfb	842	* @}
Kojto	115:87f2f5183dfb	843	*/
Kojto	115:87f2f5183dfb	844
Kojto	115:87f2f5183dfb	845	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
Kojto	115:87f2f5183dfb	846	* @{
Kojto	115:87f2f5183dfb	847	*/
Kojto	115:87f2f5183dfb	848	/** @defgroup FMC_NAND_Bank FMC NAND Bank
Kojto	115:87f2f5183dfb	849	* @{
Kojto	115:87f2f5183dfb	850	*/
Kojto	115:87f2f5183dfb	851	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	852	/**
Kojto	115:87f2f5183dfb	853	* @}
Kojto	115:87f2f5183dfb	854	*/
Kojto	115:87f2f5183dfb	855
Kojto	115:87f2f5183dfb	856	/** @defgroup FMC_Wait_feature FMC Wait feature
Kojto	115:87f2f5183dfb	857	* @{
Kojto	115:87f2f5183dfb	858	*/
Kojto	115:87f2f5183dfb	859	#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	860	#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	861	/**
Kojto	115:87f2f5183dfb	862	* @}
Kojto	115:87f2f5183dfb	863	*/
Kojto	115:87f2f5183dfb	864
Kojto	115:87f2f5183dfb	865	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
Kojto	115:87f2f5183dfb	866	* @{
Kojto	115:87f2f5183dfb	867	*/
Kojto	115:87f2f5183dfb	868	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	869	/**
Kojto	115:87f2f5183dfb	870	* @}
Kojto	115:87f2f5183dfb	871	*/
Kojto	115:87f2f5183dfb	872
Kojto	115:87f2f5183dfb	873	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
Kojto	115:87f2f5183dfb	874	* @{
Kojto	115:87f2f5183dfb	875	*/
Kojto	115:87f2f5183dfb	876	#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	877	#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	878	/**
Kojto	115:87f2f5183dfb	879	* @}
Kojto	115:87f2f5183dfb	880	*/
Kojto	115:87f2f5183dfb	881
Kojto	115:87f2f5183dfb	882	/** @defgroup FMC_ECC FMC ECC
Kojto	115:87f2f5183dfb	883	* @{
Kojto	115:87f2f5183dfb	884	*/
Kojto	115:87f2f5183dfb	885	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	886	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	887	/**
Kojto	115:87f2f5183dfb	888	* @}
Kojto	115:87f2f5183dfb	889	*/
Kojto	115:87f2f5183dfb	890
Kojto	115:87f2f5183dfb	891	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
Kojto	115:87f2f5183dfb	892	* @{
Kojto	115:87f2f5183dfb	893	*/
Kojto	115:87f2f5183dfb	894	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	895	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	896	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	897	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
Kojto	115:87f2f5183dfb	898	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	899	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
Kojto	115:87f2f5183dfb	900	/**
Kojto	115:87f2f5183dfb	901	* @}
Kojto	115:87f2f5183dfb	902	*/
Kojto	115:87f2f5183dfb	903
Kojto	115:87f2f5183dfb	904	/**
Kojto	115:87f2f5183dfb	905	* @}
Kojto	115:87f2f5183dfb	906	*/
Kojto	115:87f2f5183dfb	907
Kojto	115:87f2f5183dfb	908	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
Kojto	115:87f2f5183dfb	909	* @{
Kojto	115:87f2f5183dfb	910	*/
Kojto	115:87f2f5183dfb	911	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
Kojto	115:87f2f5183dfb	912	* @{
Kojto	115:87f2f5183dfb	913	*/
Kojto	115:87f2f5183dfb	914	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	915	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	916	/**
Kojto	115:87f2f5183dfb	917	* @}
Kojto	115:87f2f5183dfb	918	*/
Kojto	115:87f2f5183dfb	919
Kojto	115:87f2f5183dfb	920	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
Kojto	115:87f2f5183dfb	921	* @{
Kojto	115:87f2f5183dfb	922	*/
Kojto	115:87f2f5183dfb	923	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	924	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	925	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	926	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
Kojto	115:87f2f5183dfb	927	/**
Kojto	115:87f2f5183dfb	928	* @}
Kojto	115:87f2f5183dfb	929	*/
Kojto	115:87f2f5183dfb	930
Kojto	115:87f2f5183dfb	931	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
Kojto	115:87f2f5183dfb	932	* @{
Kojto	115:87f2f5183dfb	933	*/
Kojto	115:87f2f5183dfb	934	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	935	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	936	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	937	/**
Kojto	115:87f2f5183dfb	938	* @}
Kojto	115:87f2f5183dfb	939	*/
Kojto	115:87f2f5183dfb	940
Kojto	115:87f2f5183dfb	941	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
Kojto	115:87f2f5183dfb	942	* @{
Kojto	115:87f2f5183dfb	943	*/
Kojto	115:87f2f5183dfb	944	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	945	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	946	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	947	/**
Kojto	115:87f2f5183dfb	948	* @}
Kojto	115:87f2f5183dfb	949	*/
Kojto	115:87f2f5183dfb	950
Kojto	115:87f2f5183dfb	951	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
Kojto	115:87f2f5183dfb	952	* @{
Kojto	115:87f2f5183dfb	953	*/
Kojto	115:87f2f5183dfb	954	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	955	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	956	/**
Kojto	115:87f2f5183dfb	957	* @}
Kojto	115:87f2f5183dfb	958	*/
Kojto	115:87f2f5183dfb	959
Kojto	115:87f2f5183dfb	960	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
Kojto	115:87f2f5183dfb	961	* @{
Kojto	115:87f2f5183dfb	962	*/
Kojto	115:87f2f5183dfb	963	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	964	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	965	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
Kojto	115:87f2f5183dfb	966	/**
Kojto	115:87f2f5183dfb	967	* @}
Kojto	115:87f2f5183dfb	968	*/
Kojto	115:87f2f5183dfb	969
Kojto	115:87f2f5183dfb	970	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
Kojto	115:87f2f5183dfb	971	* @{
Kojto	115:87f2f5183dfb	972	*/
Kojto	115:87f2f5183dfb	973	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	974	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	975	/**
Kojto	115:87f2f5183dfb	976	* @}
Kojto	115:87f2f5183dfb	977	*/
Kojto	115:87f2f5183dfb	978
Kojto	115:87f2f5183dfb	979	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
Kojto	115:87f2f5183dfb	980	* @{
Kojto	115:87f2f5183dfb	981	*/
Kojto	115:87f2f5183dfb	982	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	983	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	984	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
Kojto	115:87f2f5183dfb	985	/**
Kojto	115:87f2f5183dfb	986	* @}
Kojto	115:87f2f5183dfb	987	*/
Kojto	115:87f2f5183dfb	988
Kojto	115:87f2f5183dfb	989	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
Kojto	115:87f2f5183dfb	990	* @{
Kojto	115:87f2f5183dfb	991	*/
Kojto	115:87f2f5183dfb	992	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	993	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	994	/**
Kojto	115:87f2f5183dfb	995	* @}
Kojto	115:87f2f5183dfb	996	*/
Kojto	115:87f2f5183dfb	997
Kojto	115:87f2f5183dfb	998	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
Kojto	115:87f2f5183dfb	999	* @{
Kojto	115:87f2f5183dfb	1000	*/
Kojto	115:87f2f5183dfb	1001	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1002	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	1003	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	1004	/**
Kojto	115:87f2f5183dfb	1005	* @}
Kojto	115:87f2f5183dfb	1006	*/
Kojto	115:87f2f5183dfb	1007
Kojto	115:87f2f5183dfb	1008	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
Kojto	115:87f2f5183dfb	1009	* @{
Kojto	115:87f2f5183dfb	1010	*/
Kojto	115:87f2f5183dfb	1011	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1012	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	1013	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	1014	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
Kojto	115:87f2f5183dfb	1015	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	1016	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
Kojto	115:87f2f5183dfb	1017	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
Kojto	115:87f2f5183dfb	1018	/**
Kojto	115:87f2f5183dfb	1019	* @}
Kojto	115:87f2f5183dfb	1020	*/
Kojto	115:87f2f5183dfb	1021
Kojto	115:87f2f5183dfb	1022	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
Kojto	115:87f2f5183dfb	1023	* @{
Kojto	115:87f2f5183dfb	1024	*/
Kojto	115:87f2f5183dfb	1025	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
Kojto	115:87f2f5183dfb	1026	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
Kojto	115:87f2f5183dfb	1027	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
Kojto	115:87f2f5183dfb	1028	/**
Kojto	115:87f2f5183dfb	1029	* @}
Kojto	115:87f2f5183dfb	1030	*/
Kojto	115:87f2f5183dfb	1031
Kojto	115:87f2f5183dfb	1032	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
Kojto	115:87f2f5183dfb	1033	* @{
Kojto	115:87f2f5183dfb	1034	*/
Kojto	115:87f2f5183dfb	1035	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1036	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
Kojto	115:87f2f5183dfb	1037	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
Kojto	115:87f2f5183dfb	1038	/**
Kojto	115:87f2f5183dfb	1039	* @}
Kojto	115:87f2f5183dfb	1040	*/
Kojto	115:87f2f5183dfb	1041
Kojto	115:87f2f5183dfb	1042	/**
Kojto	115:87f2f5183dfb	1043	* @}
Kojto	115:87f2f5183dfb	1044	*/
Kojto	115:87f2f5183dfb	1045
Kojto	115:87f2f5183dfb	1046	/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
Kojto	115:87f2f5183dfb	1047	* @{
Kojto	115:87f2f5183dfb	1048	*/
Kojto	115:87f2f5183dfb	1049	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	1050	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	1051	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	1052	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	1053	/**
Kojto	115:87f2f5183dfb	1054	* @}
Kojto	115:87f2f5183dfb	1055	*/
Kojto	115:87f2f5183dfb	1056
Kojto	115:87f2f5183dfb	1057	/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
Kojto	115:87f2f5183dfb	1058	* @{
Kojto	115:87f2f5183dfb	1059	*/
Kojto	115:87f2f5183dfb	1060	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	1061	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	1062	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	1063	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	1064	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
Kojto	115:87f2f5183dfb	1065	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
Kojto	115:87f2f5183dfb	1066	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
Kojto	115:87f2f5183dfb	1067	/**
Kojto	115:87f2f5183dfb	1068	* @}
Kojto	115:87f2f5183dfb	1069	*/
Kojto	115:87f2f5183dfb	1070	/**
Kojto	115:87f2f5183dfb	1071	* @}
Kojto	115:87f2f5183dfb	1072	*/
Kojto	115:87f2f5183dfb	1073
Kojto	115:87f2f5183dfb	1074	/**
Kojto	115:87f2f5183dfb	1075	* @}
Kojto	115:87f2f5183dfb	1076	*/
Kojto	115:87f2f5183dfb	1077
Kojto	115:87f2f5183dfb	1078	/* Private macro -------------------------------------------------------------*/
Kojto	115:87f2f5183dfb	1079	/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
Kojto	115:87f2f5183dfb	1080	* @{
Kojto	115:87f2f5183dfb	1081	*/
Kojto	115:87f2f5183dfb	1082
Kojto	115:87f2f5183dfb	1083	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
Kojto	115:87f2f5183dfb	1084	* @brief macros to handle NOR device enable/disable and read/write operations
Kojto	115:87f2f5183dfb	1085	* @{
Kojto	115:87f2f5183dfb	1086	*/
Kojto	115:87f2f5183dfb	1087
Kojto	115:87f2f5183dfb	1088	/**
Kojto	115:87f2f5183dfb	1089	* @brief Enable the NORSRAM device access.
Kojto	115:87f2f5183dfb	1090	* @param __INSTANCE__: FMC_NORSRAM Instance
Kojto	115:87f2f5183dfb	1091	* @param __BANK__: FMC_NORSRAM Bank
Kojto	115:87f2f5183dfb	1092	* @retval None
Kojto	115:87f2f5183dfb	1093	*/
Kojto	115:87f2f5183dfb	1094	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
Kojto	115:87f2f5183dfb	1095
Kojto	115:87f2f5183dfb	1096	/**
Kojto	115:87f2f5183dfb	1097	* @brief Disable the NORSRAM device access.
Kojto	115:87f2f5183dfb	1098	* @param __INSTANCE__: FMC_NORSRAM Instance
Kojto	115:87f2f5183dfb	1099	* @param __BANK__: FMC_NORSRAM Bank
Kojto	115:87f2f5183dfb	1100	* @retval None
Kojto	115:87f2f5183dfb	1101	*/
Kojto	115:87f2f5183dfb	1102	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
Kojto	115:87f2f5183dfb	1103
Kojto	115:87f2f5183dfb	1104	/**
Kojto	115:87f2f5183dfb	1105	* @}
Kojto	115:87f2f5183dfb	1106	*/
Kojto	115:87f2f5183dfb	1107
Kojto	115:87f2f5183dfb	1108	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
Kojto	115:87f2f5183dfb	1109	* @brief macros to handle NAND device enable/disable
Kojto	115:87f2f5183dfb	1110	* @{
Kojto	115:87f2f5183dfb	1111	*/
Kojto	115:87f2f5183dfb	1112
Kojto	115:87f2f5183dfb	1113	/**
Kojto	115:87f2f5183dfb	1114	* @brief Enable the NAND device access.
Kojto	115:87f2f5183dfb	1115	* @param __INSTANCE__: FMC_NAND Instance
Kojto	115:87f2f5183dfb	1116	* @retval None
Kojto	115:87f2f5183dfb	1117	*/
Kojto	115:87f2f5183dfb	1118	#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
Kojto	115:87f2f5183dfb	1119
Kojto	115:87f2f5183dfb	1120	/**
Kojto	115:87f2f5183dfb	1121	* @brief Disable the NAND device access.
Kojto	115:87f2f5183dfb	1122	* @param __INSTANCE__: FMC_NAND Instance
Kojto	115:87f2f5183dfb	1123	* @retval None
Kojto	115:87f2f5183dfb	1124	*/
Kojto	115:87f2f5183dfb	1125	#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
Kojto	115:87f2f5183dfb	1126
Kojto	115:87f2f5183dfb	1127	/**
Kojto	115:87f2f5183dfb	1128	* @}
Kojto	115:87f2f5183dfb	1129	*/
Kojto	115:87f2f5183dfb	1130
Kojto	115:87f2f5183dfb	1131	/** @defgroup FMC_Interrupt FMC Interrupt
Kojto	115:87f2f5183dfb	1132	* @brief macros to handle FMC interrupts
Kojto	115:87f2f5183dfb	1133	* @{
Kojto	115:87f2f5183dfb	1134	*/
Kojto	115:87f2f5183dfb	1135
Kojto	115:87f2f5183dfb	1136	/**
Kojto	115:87f2f5183dfb	1137	* @brief Enable the NAND device interrupt.
Kojto	115:87f2f5183dfb	1138	* @param __INSTANCE__: FMC_NAND instance
Kojto	115:87f2f5183dfb	1139	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	115:87f2f5183dfb	1140	* This parameter can be any combination of the following values:
Kojto	115:87f2f5183dfb	1141	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	115:87f2f5183dfb	1142	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	115:87f2f5183dfb	1143	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	115:87f2f5183dfb	1144	* @retval None
Kojto	115:87f2f5183dfb	1145	*/
Kojto	115:87f2f5183dfb	1146	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
Kojto	115:87f2f5183dfb	1147
Kojto	115:87f2f5183dfb	1148	/**
Kojto	115:87f2f5183dfb	1149	* @brief Disable the NAND device interrupt.
Kojto	115:87f2f5183dfb	1150	* @param __INSTANCE__: FMC_NAND Instance
Kojto	115:87f2f5183dfb	1151	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	115:87f2f5183dfb	1152	* This parameter can be any combination of the following values:
Kojto	115:87f2f5183dfb	1153	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	115:87f2f5183dfb	1154	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	115:87f2f5183dfb	1155	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	115:87f2f5183dfb	1156	* @retval None
Kojto	115:87f2f5183dfb	1157	*/
Kojto	115:87f2f5183dfb	1158	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
Kojto	115:87f2f5183dfb	1159
Kojto	115:87f2f5183dfb	1160	/**
Kojto	115:87f2f5183dfb	1161	* @brief Get flag status of the NAND device.
Kojto	115:87f2f5183dfb	1162	* @param __INSTANCE__: FMC_NAND Instance
Kojto	115:87f2f5183dfb	1163	* @param __BANK__: FMC_NAND Bank
Kojto	115:87f2f5183dfb	1164	* @param __FLAG__: FMC_NAND flag
Kojto	115:87f2f5183dfb	1165	* This parameter can be any combination of the following values:
Kojto	115:87f2f5183dfb	1166	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	115:87f2f5183dfb	1167	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	115:87f2f5183dfb	1168	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	115:87f2f5183dfb	1169	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	115:87f2f5183dfb	1170	* @retval The state of FLAG (SET or RESET).
Kojto	115:87f2f5183dfb	1171	*/
Kojto	115:87f2f5183dfb	1172	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
Kojto	115:87f2f5183dfb	1173
Kojto	115:87f2f5183dfb	1174	/**
Kojto	115:87f2f5183dfb	1175	* @brief Clear flag status of the NAND device.
Kojto	115:87f2f5183dfb	1176	* @param __INSTANCE__: FMC_NAND Instance
Kojto	115:87f2f5183dfb	1177	* @param __FLAG__: FMC_NAND flag
Kojto	115:87f2f5183dfb	1178	* This parameter can be any combination of the following values:
Kojto	115:87f2f5183dfb	1179	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	115:87f2f5183dfb	1180	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	115:87f2f5183dfb	1181	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	115:87f2f5183dfb	1182	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	115:87f2f5183dfb	1183	* @retval None
Kojto	115:87f2f5183dfb	1184	*/
Kojto	115:87f2f5183dfb	1185	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
Kojto	115:87f2f5183dfb	1186
Kojto	115:87f2f5183dfb	1187	/**
Kojto	115:87f2f5183dfb	1188	* @brief Enable the SDRAM device interrupt.
Kojto	115:87f2f5183dfb	1189	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	115:87f2f5183dfb	1190	* @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto	115:87f2f5183dfb	1191	* This parameter can be any combination of the following values:
Kojto	115:87f2f5183dfb	1192	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto	115:87f2f5183dfb	1193	* @retval None
Kojto	115:87f2f5183dfb	1194	*/
Kojto	115:87f2f5183dfb	1195	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
Kojto	115:87f2f5183dfb	1196
Kojto	115:87f2f5183dfb	1197	/**
Kojto	115:87f2f5183dfb	1198	* @brief Disable the SDRAM device interrupt.
Kojto	115:87f2f5183dfb	1199	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	115:87f2f5183dfb	1200	* @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto	115:87f2f5183dfb	1201	* This parameter can be any combination of the following values:
Kojto	115:87f2f5183dfb	1202	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto	115:87f2f5183dfb	1203	* @retval None
Kojto	115:87f2f5183dfb	1204	*/
Kojto	115:87f2f5183dfb	1205	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
Kojto	115:87f2f5183dfb	1206
Kojto	115:87f2f5183dfb	1207	/**
Kojto	115:87f2f5183dfb	1208	* @brief Get flag status of the SDRAM device.
Kojto	115:87f2f5183dfb	1209	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	115:87f2f5183dfb	1210	* @param __FLAG__: FMC_SDRAM flag
Kojto	115:87f2f5183dfb	1211	* This parameter can be any combination of the following values:
Kojto	115:87f2f5183dfb	1212	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
Kojto	115:87f2f5183dfb	1213	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
Kojto	115:87f2f5183dfb	1214	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
Kojto	115:87f2f5183dfb	1215	* @retval The state of FLAG (SET or RESET).
Kojto	115:87f2f5183dfb	1216	*/
Kojto	115:87f2f5183dfb	1217	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
Kojto	115:87f2f5183dfb	1218
Kojto	115:87f2f5183dfb	1219	/**
Kojto	115:87f2f5183dfb	1220	* @brief Clear flag status of the SDRAM device.
Kojto	115:87f2f5183dfb	1221	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	115:87f2f5183dfb	1222	* @param __FLAG__: FMC_SDRAM flag
Kojto	115:87f2f5183dfb	1223	* This parameter can be any combination of the following values:
Kojto	115:87f2f5183dfb	1224	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
Kojto	115:87f2f5183dfb	1225	* @retval None
Kojto	115:87f2f5183dfb	1226	*/
Kojto	115:87f2f5183dfb	1227	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
Kojto	115:87f2f5183dfb	1228	/**
Kojto	115:87f2f5183dfb	1229	* @}
Kojto	115:87f2f5183dfb	1230	*/
Kojto	115:87f2f5183dfb	1231
Kojto	115:87f2f5183dfb	1232	/**
Kojto	115:87f2f5183dfb	1233	* @}
Kojto	115:87f2f5183dfb	1234	*/
Kojto	115:87f2f5183dfb	1235
Kojto	115:87f2f5183dfb	1236	/* Private functions ---------------------------------------------------------*/
Kojto	115:87f2f5183dfb	1237	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
Kojto	115:87f2f5183dfb	1238	* @{
Kojto	115:87f2f5183dfb	1239	*/
Kojto	115:87f2f5183dfb	1240
Kojto	115:87f2f5183dfb	1241	/** @defgroup FMC_LL_NORSRAM NOR SRAM
Kojto	115:87f2f5183dfb	1242	* @{
Kojto	115:87f2f5183dfb	1243	*/
Kojto	115:87f2f5183dfb	1244	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto	115:87f2f5183dfb	1245	* @{
Kojto	115:87f2f5183dfb	1246	*/
Kojto	115:87f2f5183dfb	1247	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
Kojto	115:87f2f5183dfb	1248	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
Kojto	115:87f2f5183dfb	1249	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
Kojto	115:87f2f5183dfb	1250	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
Kojto	115:87f2f5183dfb	1251	/**
Kojto	115:87f2f5183dfb	1252	* @}
Kojto	115:87f2f5183dfb	1253	*/
Kojto	115:87f2f5183dfb	1254
Kojto	115:87f2f5183dfb	1255	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto	115:87f2f5183dfb	1256	* @{
Kojto	115:87f2f5183dfb	1257	*/
Kojto	115:87f2f5183dfb	1258	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto	115:87f2f5183dfb	1259	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto	115:87f2f5183dfb	1260	/**
Kojto	115:87f2f5183dfb	1261	* @}
Kojto	115:87f2f5183dfb	1262	*/
Kojto	115:87f2f5183dfb	1263	/**
Kojto	115:87f2f5183dfb	1264	* @}
Kojto	115:87f2f5183dfb	1265	*/
Kojto	115:87f2f5183dfb	1266
Kojto	115:87f2f5183dfb	1267	/** @defgroup FMC_LL_NAND NAND
Kojto	115:87f2f5183dfb	1268	* @{
Kojto	115:87f2f5183dfb	1269	*/
Kojto	115:87f2f5183dfb	1270	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto	115:87f2f5183dfb	1271	* @{
Kojto	115:87f2f5183dfb	1272	*/
Kojto	115:87f2f5183dfb	1273	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
Kojto	115:87f2f5183dfb	1274	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
Kojto	115:87f2f5183dfb	1275	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
Kojto	115:87f2f5183dfb	1276	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	115:87f2f5183dfb	1277	/**
Kojto	115:87f2f5183dfb	1278	* @}
Kojto	115:87f2f5183dfb	1279	*/
Kojto	115:87f2f5183dfb	1280
Kojto	115:87f2f5183dfb	1281	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto	115:87f2f5183dfb	1282	* @{
Kojto	115:87f2f5183dfb	1283	*/
Kojto	115:87f2f5183dfb	1284	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	115:87f2f5183dfb	1285	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	115:87f2f5183dfb	1286	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
Kojto	115:87f2f5183dfb	1287	/**
Kojto	115:87f2f5183dfb	1288	* @}
Kojto	115:87f2f5183dfb	1289	*/
Kojto	115:87f2f5183dfb	1290
Kojto	115:87f2f5183dfb	1291	/** @defgroup FMC_LL_SDRAM SDRAM
Kojto	115:87f2f5183dfb	1292	* @{
Kojto	115:87f2f5183dfb	1293	*/
Kojto	115:87f2f5183dfb	1294	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
Kojto	115:87f2f5183dfb	1295	* @{
Kojto	115:87f2f5183dfb	1296	*/
Kojto	115:87f2f5183dfb	1297	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
Kojto	115:87f2f5183dfb	1298	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
Kojto	115:87f2f5183dfb	1299	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	115:87f2f5183dfb	1300
Kojto	115:87f2f5183dfb	1301	/**
Kojto	115:87f2f5183dfb	1302	* @}
Kojto	115:87f2f5183dfb	1303	*/
Kojto	115:87f2f5183dfb	1304
Kojto	115:87f2f5183dfb	1305	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
Kojto	115:87f2f5183dfb	1306	* @{
Kojto	115:87f2f5183dfb	1307	*/
Kojto	115:87f2f5183dfb	1308	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	115:87f2f5183dfb	1309	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	115:87f2f5183dfb	1310	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
Kojto	115:87f2f5183dfb	1311	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
Kojto	115:87f2f5183dfb	1312	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
Kojto	115:87f2f5183dfb	1313	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	115:87f2f5183dfb	1314	/**
Kojto	115:87f2f5183dfb	1315	* @}
Kojto	115:87f2f5183dfb	1316	*/
Kojto	115:87f2f5183dfb	1317
Kojto	115:87f2f5183dfb	1318	/**
Kojto	115:87f2f5183dfb	1319	* @}
Kojto	115:87f2f5183dfb	1320	*/
Kojto	115:87f2f5183dfb	1321
Kojto	115:87f2f5183dfb	1322	/**
Kojto	115:87f2f5183dfb	1323	* @}
Kojto	115:87f2f5183dfb	1324	*/
Kojto	115:87f2f5183dfb	1325
Kojto	115:87f2f5183dfb	1326	/**
Kojto	115:87f2f5183dfb	1327	* @}
Kojto	115:87f2f5183dfb	1328	*/
Kojto	115:87f2f5183dfb	1329
Kojto	115:87f2f5183dfb	1330	/**
Kojto	115:87f2f5183dfb	1331	* @}
Kojto	115:87f2f5183dfb	1332	*/
Kojto	115:87f2f5183dfb	1333	#ifdef __cplusplus
Kojto	115:87f2f5183dfb	1334	}
Kojto	115:87f2f5183dfb	1335	#endif
Kojto	115:87f2f5183dfb	1336
Kojto	115:87f2f5183dfb	1337	#endif /* __STM32F7xx_LL_FMC_H */
Kojto	115:87f2f5183dfb	1338
Kojto	115:87f2f5183dfb	1339	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F746ZG/stm32f7xx_ll_fmc.h@121:672067c3ada4, 2016-04-14 (annotated)

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