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Elijah Orr / mbed-renbed

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TARGET_NUCLEO_F746ZG/stm32f7xx_hal_eth.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 116:c0f6e94411f5

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	115:87f2f5183dfb	1	/**
Kojto	115:87f2f5183dfb	2	******************************************************************************
Kojto	115:87f2f5183dfb	3	* @file stm32f7xx_hal_eth.h
Kojto	115:87f2f5183dfb	4	* @author MCD Application Team
Kojto	116:c0f6e94411f5	5	* @version V1.0.4
Kojto	116:c0f6e94411f5	6	* @date 09-December-2015
Kojto	115:87f2f5183dfb	7	* @brief Header file of ETH HAL module.
Kojto	115:87f2f5183dfb	8	******************************************************************************
Kojto	115:87f2f5183dfb	9	* @attention
Kojto	115:87f2f5183dfb	10	*
Kojto	115:87f2f5183dfb	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	115:87f2f5183dfb	12	*
Kojto	115:87f2f5183dfb	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	115:87f2f5183dfb	14	* are permitted provided that the following conditions are met:
Kojto	115:87f2f5183dfb	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	115:87f2f5183dfb	16	* this list of conditions and the following disclaimer.
Kojto	115:87f2f5183dfb	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	115:87f2f5183dfb	18	* this list of conditions and the following disclaimer in the documentation
Kojto	115:87f2f5183dfb	19	* and/or other materials provided with the distribution.
Kojto	115:87f2f5183dfb	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	115:87f2f5183dfb	21	* may be used to endorse or promote products derived from this software
Kojto	115:87f2f5183dfb	22	* without specific prior written permission.
Kojto	115:87f2f5183dfb	23	*
Kojto	115:87f2f5183dfb	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	115:87f2f5183dfb	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	115:87f2f5183dfb	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	115:87f2f5183dfb	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	115:87f2f5183dfb	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	115:87f2f5183dfb	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	115:87f2f5183dfb	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	115:87f2f5183dfb	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	115:87f2f5183dfb	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	115:87f2f5183dfb	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	115:87f2f5183dfb	34	*
Kojto	115:87f2f5183dfb	35	******************************************************************************
Kojto	115:87f2f5183dfb	36	*/
Kojto	115:87f2f5183dfb	37
Kojto	115:87f2f5183dfb	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	115:87f2f5183dfb	39	#ifndef __STM32F7xx_HAL_ETH_H
Kojto	115:87f2f5183dfb	40	#define __STM32F7xx_HAL_ETH_H
Kojto	115:87f2f5183dfb	41
Kojto	115:87f2f5183dfb	42	#ifdef __cplusplus
Kojto	115:87f2f5183dfb	43	extern "C" {
Kojto	115:87f2f5183dfb	44	#endif
Kojto	115:87f2f5183dfb	45
Kojto	115:87f2f5183dfb	46	/* Includes ------------------------------------------------------------------*/
Kojto	115:87f2f5183dfb	47	#include "stm32f7xx_hal_def.h"
Kojto	115:87f2f5183dfb	48
Kojto	115:87f2f5183dfb	49	/** @addtogroup STM32F7xx_HAL_Driver
Kojto	115:87f2f5183dfb	50	* @{
Kojto	115:87f2f5183dfb	51	*/
Kojto	115:87f2f5183dfb	52
Kojto	115:87f2f5183dfb	53	/** @addtogroup ETH
Kojto	115:87f2f5183dfb	54	* @{
Kojto	115:87f2f5183dfb	55	*/
Kojto	115:87f2f5183dfb	56
Kojto	115:87f2f5183dfb	57	/** @addtogroup ETH_Private_Macros
Kojto	115:87f2f5183dfb	58	* @{
Kojto	115:87f2f5183dfb	59	*/
Kojto	115:87f2f5183dfb	60	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
Kojto	115:87f2f5183dfb	61	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	62	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
Kojto	115:87f2f5183dfb	63	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
Kojto	115:87f2f5183dfb	64	((SPEED) == ETH_SPEED_100M))
Kojto	115:87f2f5183dfb	65	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
Kojto	115:87f2f5183dfb	66	((MODE) == ETH_MODE_HALFDUPLEX))
Kojto	115:87f2f5183dfb	67	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
Kojto	115:87f2f5183dfb	68	((MODE) == ETH_RXINTERRUPT_MODE))
Kojto	115:87f2f5183dfb	69	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
Kojto	115:87f2f5183dfb	70	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
Kojto	115:87f2f5183dfb	71	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
Kojto	115:87f2f5183dfb	72	((MODE) == ETH_MEDIA_INTERFACE_RMII))
Kojto	115:87f2f5183dfb	73	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	74	((CMD) == ETH_WATCHDOG_DISABLE))
Kojto	115:87f2f5183dfb	75	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	76	((CMD) == ETH_JABBER_DISABLE))
Kojto	115:87f2f5183dfb	77	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
Kojto	115:87f2f5183dfb	78	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
Kojto	115:87f2f5183dfb	79	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
Kojto	115:87f2f5183dfb	80	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
Kojto	115:87f2f5183dfb	81	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
Kojto	115:87f2f5183dfb	82	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
Kojto	115:87f2f5183dfb	83	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
Kojto	115:87f2f5183dfb	84	((GAP) == ETH_INTERFRAMEGAP_40BIT))
Kojto	115:87f2f5183dfb	85	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	86	((CMD) == ETH_CARRIERSENCE_DISABLE))
Kojto	115:87f2f5183dfb	87	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	88	((CMD) == ETH_RECEIVEOWN_DISABLE))
Kojto	115:87f2f5183dfb	89	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	90	((CMD) == ETH_LOOPBACKMODE_DISABLE))
Kojto	115:87f2f5183dfb	91	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	92	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
Kojto	115:87f2f5183dfb	93	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	94	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
Kojto	115:87f2f5183dfb	95	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	96	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
Kojto	115:87f2f5183dfb	97	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
Kojto	115:87f2f5183dfb	98	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
Kojto	115:87f2f5183dfb	99	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
Kojto	115:87f2f5183dfb	100	((LIMIT) == ETH_BACKOFFLIMIT_1))
Kojto	115:87f2f5183dfb	101	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	102	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
Kojto	115:87f2f5183dfb	103	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	104	((CMD) == ETH_RECEIVEAll_DISABLE))
Kojto	115:87f2f5183dfb	105	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	106	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	107	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
Kojto	115:87f2f5183dfb	108	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
Kojto	115:87f2f5183dfb	109	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
Kojto	115:87f2f5183dfb	110	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
Kojto	115:87f2f5183dfb	111	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	112	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
Kojto	115:87f2f5183dfb	113	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
Kojto	115:87f2f5183dfb	114	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
Kojto	115:87f2f5183dfb	115	#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	116	((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
Kojto	115:87f2f5183dfb	117	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
Kojto	115:87f2f5183dfb	118	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
Kojto	115:87f2f5183dfb	119	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
Kojto	115:87f2f5183dfb	120	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
Kojto	115:87f2f5183dfb	121	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
Kojto	115:87f2f5183dfb	122	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
Kojto	115:87f2f5183dfb	123	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
Kojto	115:87f2f5183dfb	124	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
Kojto	115:87f2f5183dfb	125	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	126	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
Kojto	115:87f2f5183dfb	127	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
Kojto	115:87f2f5183dfb	128	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
Kojto	115:87f2f5183dfb	129	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
Kojto	115:87f2f5183dfb	130	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
Kojto	115:87f2f5183dfb	131	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	132	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
Kojto	115:87f2f5183dfb	133	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	134	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
Kojto	115:87f2f5183dfb	135	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	136	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
Kojto	115:87f2f5183dfb	137	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
Kojto	115:87f2f5183dfb	138	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
Kojto	115:87f2f5183dfb	139	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
Kojto	115:87f2f5183dfb	140	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
Kojto	115:87f2f5183dfb	141	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
Kojto	115:87f2f5183dfb	142	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
Kojto	115:87f2f5183dfb	143	((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto	115:87f2f5183dfb	144	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
Kojto	115:87f2f5183dfb	145	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
Kojto	115:87f2f5183dfb	146	((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto	115:87f2f5183dfb	147	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
Kojto	115:87f2f5183dfb	148	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
Kojto	115:87f2f5183dfb	149	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
Kojto	115:87f2f5183dfb	150	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
Kojto	115:87f2f5183dfb	151	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
Kojto	115:87f2f5183dfb	152	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
Kojto	115:87f2f5183dfb	153	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
Kojto	115:87f2f5183dfb	154	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
Kojto	115:87f2f5183dfb	155	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	156	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
Kojto	115:87f2f5183dfb	157	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	158	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
Kojto	115:87f2f5183dfb	159	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	160	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
Kojto	115:87f2f5183dfb	161	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	162	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
Kojto	115:87f2f5183dfb	163	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
Kojto	115:87f2f5183dfb	164	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
Kojto	115:87f2f5183dfb	165	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
Kojto	115:87f2f5183dfb	166	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
Kojto	115:87f2f5183dfb	167	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
Kojto	115:87f2f5183dfb	168	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
Kojto	115:87f2f5183dfb	169	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
Kojto	115:87f2f5183dfb	170	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
Kojto	115:87f2f5183dfb	171	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	172	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
Kojto	115:87f2f5183dfb	173	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	174	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
Kojto	115:87f2f5183dfb	175	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
Kojto	115:87f2f5183dfb	176	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
Kojto	115:87f2f5183dfb	177	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
Kojto	115:87f2f5183dfb	178	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
Kojto	115:87f2f5183dfb	179	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	180	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
Kojto	115:87f2f5183dfb	181	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	182	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
Kojto	115:87f2f5183dfb	183	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	184	((CMD) == ETH_FIXEDBURST_DISABLE))
Kojto	115:87f2f5183dfb	185	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
Kojto	115:87f2f5183dfb	186	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
Kojto	115:87f2f5183dfb	187	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
Kojto	115:87f2f5183dfb	188	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
Kojto	115:87f2f5183dfb	189	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
Kojto	115:87f2f5183dfb	190	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
Kojto	115:87f2f5183dfb	191	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
Kojto	115:87f2f5183dfb	192	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
Kojto	115:87f2f5183dfb	193	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
Kojto	115:87f2f5183dfb	194	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
Kojto	115:87f2f5183dfb	195	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
Kojto	115:87f2f5183dfb	196	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto	115:87f2f5183dfb	197	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
Kojto	115:87f2f5183dfb	198	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
Kojto	115:87f2f5183dfb	199	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
Kojto	115:87f2f5183dfb	200	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
Kojto	115:87f2f5183dfb	201	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
Kojto	115:87f2f5183dfb	202	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
Kojto	115:87f2f5183dfb	203	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
Kojto	115:87f2f5183dfb	204	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
Kojto	115:87f2f5183dfb	205	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
Kojto	115:87f2f5183dfb	206	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
Kojto	115:87f2f5183dfb	207	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
Kojto	115:87f2f5183dfb	208	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto	115:87f2f5183dfb	209	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
Kojto	115:87f2f5183dfb	210	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
Kojto	115:87f2f5183dfb	211	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
Kojto	115:87f2f5183dfb	212	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
Kojto	115:87f2f5183dfb	213	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
Kojto	115:87f2f5183dfb	214	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
Kojto	115:87f2f5183dfb	215	#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) \|\| \
Kojto	115:87f2f5183dfb	216	((FLAG) == ETH_DMATXDESC_IC) \|\| \
Kojto	115:87f2f5183dfb	217	((FLAG) == ETH_DMATXDESC_LS) \|\| \
Kojto	115:87f2f5183dfb	218	((FLAG) == ETH_DMATXDESC_FS) \|\| \
Kojto	115:87f2f5183dfb	219	((FLAG) == ETH_DMATXDESC_DC) \|\| \
Kojto	115:87f2f5183dfb	220	((FLAG) == ETH_DMATXDESC_DP) \|\| \
Kojto	115:87f2f5183dfb	221	((FLAG) == ETH_DMATXDESC_TTSE) \|\| \
Kojto	115:87f2f5183dfb	222	((FLAG) == ETH_DMATXDESC_TER) \|\| \
Kojto	115:87f2f5183dfb	223	((FLAG) == ETH_DMATXDESC_TCH) \|\| \
Kojto	115:87f2f5183dfb	224	((FLAG) == ETH_DMATXDESC_TTSS) \|\| \
Kojto	115:87f2f5183dfb	225	((FLAG) == ETH_DMATXDESC_IHE) \|\| \
Kojto	115:87f2f5183dfb	226	((FLAG) == ETH_DMATXDESC_ES) \|\| \
Kojto	115:87f2f5183dfb	227	((FLAG) == ETH_DMATXDESC_JT) \|\| \
Kojto	115:87f2f5183dfb	228	((FLAG) == ETH_DMATXDESC_FF) \|\| \
Kojto	115:87f2f5183dfb	229	((FLAG) == ETH_DMATXDESC_PCE) \|\| \
Kojto	115:87f2f5183dfb	230	((FLAG) == ETH_DMATXDESC_LCA) \|\| \
Kojto	115:87f2f5183dfb	231	((FLAG) == ETH_DMATXDESC_NC) \|\| \
Kojto	115:87f2f5183dfb	232	((FLAG) == ETH_DMATXDESC_LCO) \|\| \
Kojto	115:87f2f5183dfb	233	((FLAG) == ETH_DMATXDESC_EC) \|\| \
Kojto	115:87f2f5183dfb	234	((FLAG) == ETH_DMATXDESC_VF) \|\| \
Kojto	115:87f2f5183dfb	235	((FLAG) == ETH_DMATXDESC_CC) \|\| \
Kojto	115:87f2f5183dfb	236	((FLAG) == ETH_DMATXDESC_ED) \|\| \
Kojto	115:87f2f5183dfb	237	((FLAG) == ETH_DMATXDESC_UF) \|\| \
Kojto	115:87f2f5183dfb	238	((FLAG) == ETH_DMATXDESC_DB))
Kojto	115:87f2f5183dfb	239	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
Kojto	115:87f2f5183dfb	240	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
Kojto	115:87f2f5183dfb	241	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
Kojto	115:87f2f5183dfb	242	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
Kojto	115:87f2f5183dfb	243	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
Kojto	115:87f2f5183dfb	244	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
Kojto	115:87f2f5183dfb	245	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
Kojto	115:87f2f5183dfb	246	#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) \|\| \
Kojto	115:87f2f5183dfb	247	((FLAG) == ETH_DMARXDESC_AFM) \|\| \
Kojto	115:87f2f5183dfb	248	((FLAG) == ETH_DMARXDESC_ES) \|\| \
Kojto	115:87f2f5183dfb	249	((FLAG) == ETH_DMARXDESC_DE) \|\| \
Kojto	115:87f2f5183dfb	250	((FLAG) == ETH_DMARXDESC_SAF) \|\| \
Kojto	115:87f2f5183dfb	251	((FLAG) == ETH_DMARXDESC_LE) \|\| \
Kojto	115:87f2f5183dfb	252	((FLAG) == ETH_DMARXDESC_OE) \|\| \
Kojto	115:87f2f5183dfb	253	((FLAG) == ETH_DMARXDESC_VLAN) \|\| \
Kojto	115:87f2f5183dfb	254	((FLAG) == ETH_DMARXDESC_FS) \|\| \
Kojto	115:87f2f5183dfb	255	((FLAG) == ETH_DMARXDESC_LS) \|\| \
Kojto	115:87f2f5183dfb	256	((FLAG) == ETH_DMARXDESC_IPV4HCE) \|\| \
Kojto	115:87f2f5183dfb	257	((FLAG) == ETH_DMARXDESC_LC) \|\| \
Kojto	115:87f2f5183dfb	258	((FLAG) == ETH_DMARXDESC_FT) \|\| \
Kojto	115:87f2f5183dfb	259	((FLAG) == ETH_DMARXDESC_RWT) \|\| \
Kojto	115:87f2f5183dfb	260	((FLAG) == ETH_DMARXDESC_RE) \|\| \
Kojto	115:87f2f5183dfb	261	((FLAG) == ETH_DMARXDESC_DBE) \|\| \
Kojto	115:87f2f5183dfb	262	((FLAG) == ETH_DMARXDESC_CE) \|\| \
Kojto	115:87f2f5183dfb	263	((FLAG) == ETH_DMARXDESC_MAMPCE))
Kojto	115:87f2f5183dfb	264	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
Kojto	115:87f2f5183dfb	265	((BUFFER) == ETH_DMARXDESC_BUFFER2))
Kojto	115:87f2f5183dfb	266	#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) \|\| \
Kojto	115:87f2f5183dfb	267	((FLAG) == ETH_PMT_FLAG_MPR))
Kojto	115:87f2f5183dfb	268	#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
Kojto	115:87f2f5183dfb	269	#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) \|\| ((FLAG) == ETH_DMA_FLAG_PMT) \|\| \
Kojto	115:87f2f5183dfb	270	((FLAG) == ETH_DMA_FLAG_MMC) \|\| ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) \|\| \
Kojto	115:87f2f5183dfb	271	((FLAG) == ETH_DMA_FLAG_READWRITEERROR) \|\| ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) \|\| \
Kojto	115:87f2f5183dfb	272	((FLAG) == ETH_DMA_FLAG_NIS) \|\| ((FLAG) == ETH_DMA_FLAG_AIS) \|\| \
Kojto	115:87f2f5183dfb	273	((FLAG) == ETH_DMA_FLAG_ER) \|\| ((FLAG) == ETH_DMA_FLAG_FBE) \|\| \
Kojto	115:87f2f5183dfb	274	((FLAG) == ETH_DMA_FLAG_ET) \|\| ((FLAG) == ETH_DMA_FLAG_RWT) \|\| \
Kojto	115:87f2f5183dfb	275	((FLAG) == ETH_DMA_FLAG_RPS) \|\| ((FLAG) == ETH_DMA_FLAG_RBU) \|\| \
Kojto	115:87f2f5183dfb	276	((FLAG) == ETH_DMA_FLAG_R) \|\| ((FLAG) == ETH_DMA_FLAG_TU) \|\| \
Kojto	115:87f2f5183dfb	277	((FLAG) == ETH_DMA_FLAG_RO) \|\| ((FLAG) == ETH_DMA_FLAG_TJT) \|\| \
Kojto	115:87f2f5183dfb	278	((FLAG) == ETH_DMA_FLAG_TBU) \|\| ((FLAG) == ETH_DMA_FLAG_TPS) \|\| \
Kojto	115:87f2f5183dfb	279	((FLAG) == ETH_DMA_FLAG_T))
Kojto	115:87f2f5183dfb	280	#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
Kojto	115:87f2f5183dfb	281	#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) \|\| ((IT) == ETH_MAC_IT_MMCT) \|\| \
Kojto	115:87f2f5183dfb	282	((IT) == ETH_MAC_IT_MMCR) \|\| ((IT) == ETH_MAC_IT_MMC) \|\| \
Kojto	115:87f2f5183dfb	283	((IT) == ETH_MAC_IT_PMT))
Kojto	115:87f2f5183dfb	284	#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) \|\| ((FLAG) == ETH_MAC_FLAG_MMCT) \|\| \
Kojto	115:87f2f5183dfb	285	((FLAG) == ETH_MAC_FLAG_MMCR) \|\| ((FLAG) == ETH_MAC_FLAG_MMC) \|\| \
Kojto	115:87f2f5183dfb	286	((FLAG) == ETH_MAC_FLAG_PMT))
Kojto	115:87f2f5183dfb	287	#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
Kojto	115:87f2f5183dfb	288	#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) \|\| ((IT) == ETH_DMA_IT_PMT) \|\| \
Kojto	115:87f2f5183dfb	289	((IT) == ETH_DMA_IT_MMC) \|\| ((IT) == ETH_DMA_IT_NIS) \|\| \
Kojto	115:87f2f5183dfb	290	((IT) == ETH_DMA_IT_AIS) \|\| ((IT) == ETH_DMA_IT_ER) \|\| \
Kojto	115:87f2f5183dfb	291	((IT) == ETH_DMA_IT_FBE) \|\| ((IT) == ETH_DMA_IT_ET) \|\| \
Kojto	115:87f2f5183dfb	292	((IT) == ETH_DMA_IT_RWT) \|\| ((IT) == ETH_DMA_IT_RPS) \|\| \
Kojto	115:87f2f5183dfb	293	((IT) == ETH_DMA_IT_RBU) \|\| ((IT) == ETH_DMA_IT_R) \|\| \
Kojto	115:87f2f5183dfb	294	((IT) == ETH_DMA_IT_TU) \|\| ((IT) == ETH_DMA_IT_RO) \|\| \
Kojto	115:87f2f5183dfb	295	((IT) == ETH_DMA_IT_TJT) \|\| ((IT) == ETH_DMA_IT_TBU) \|\| \
Kojto	115:87f2f5183dfb	296	((IT) == ETH_DMA_IT_TPS) \|\| ((IT) == ETH_DMA_IT_T))
Kojto	115:87f2f5183dfb	297	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
Kojto	115:87f2f5183dfb	298	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
Kojto	115:87f2f5183dfb	299	#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) \|\| (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
Kojto	115:87f2f5183dfb	300	((IT) != 0x00))
Kojto	115:87f2f5183dfb	301	#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) \|\| ((IT) == ETH_MMC_IT_TGFMSC) \|\| \
Kojto	115:87f2f5183dfb	302	((IT) == ETH_MMC_IT_TGFSC) \|\| ((IT) == ETH_MMC_IT_RGUF) \|\| \
Kojto	115:87f2f5183dfb	303	((IT) == ETH_MMC_IT_RFAE) \|\| ((IT) == ETH_MMC_IT_RFCE))
Kojto	115:87f2f5183dfb	304	#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) \|\| \
Kojto	115:87f2f5183dfb	305	((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
Kojto	115:87f2f5183dfb	306
Kojto	115:87f2f5183dfb	307
Kojto	115:87f2f5183dfb	308	/**
Kojto	115:87f2f5183dfb	309	* @}
Kojto	115:87f2f5183dfb	310	*/
Kojto	115:87f2f5183dfb	311
Kojto	115:87f2f5183dfb	312	/** @addtogroup ETH_Private_Defines
Kojto	115:87f2f5183dfb	313	* @{
Kojto	115:87f2f5183dfb	314	*/
Kojto	115:87f2f5183dfb	315	/* Delay to wait when writing to some Ethernet registers */
Kojto	115:87f2f5183dfb	316	#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	317
Kojto	115:87f2f5183dfb	318	/* ETHERNET Errors */
Kojto	115:87f2f5183dfb	319	#define ETH_SUCCESS ((uint32_t)0)
Kojto	115:87f2f5183dfb	320	#define ETH_ERROR ((uint32_t)1)
Kojto	115:87f2f5183dfb	321
Kojto	115:87f2f5183dfb	322	/* ETHERNET DMA Tx descriptors Collision Count Shift */
Kojto	115:87f2f5183dfb	323	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
Kojto	115:87f2f5183dfb	324
Kojto	115:87f2f5183dfb	325	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
Kojto	115:87f2f5183dfb	326	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
Kojto	115:87f2f5183dfb	327
Kojto	115:87f2f5183dfb	328	/* ETHERNET DMA Rx descriptors Frame Length Shift */
Kojto	115:87f2f5183dfb	329	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
Kojto	115:87f2f5183dfb	330
Kojto	115:87f2f5183dfb	331	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
Kojto	115:87f2f5183dfb	332	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
Kojto	115:87f2f5183dfb	333
Kojto	115:87f2f5183dfb	334	/* ETHERNET DMA Rx descriptors Frame length Shift */
Kojto	115:87f2f5183dfb	335	#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
Kojto	115:87f2f5183dfb	336
Kojto	115:87f2f5183dfb	337	/* ETHERNET MAC address offsets */
Kojto	115:87f2f5183dfb	338	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
Kojto	115:87f2f5183dfb	339	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
Kojto	115:87f2f5183dfb	340
Kojto	115:87f2f5183dfb	341	/* ETHERNET MACMIIAR register Mask */
Kojto	115:87f2f5183dfb	342	#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
Kojto	115:87f2f5183dfb	343
Kojto	115:87f2f5183dfb	344	/* ETHERNET MACCR register Mask */
Kojto	115:87f2f5183dfb	345	#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
Kojto	115:87f2f5183dfb	346
Kojto	115:87f2f5183dfb	347	/* ETHERNET MACFCR register Mask */
Kojto	115:87f2f5183dfb	348	#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
Kojto	115:87f2f5183dfb	349
Kojto	115:87f2f5183dfb	350	/* ETHERNET DMAOMR register Mask */
Kojto	115:87f2f5183dfb	351	#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
Kojto	115:87f2f5183dfb	352
Kojto	115:87f2f5183dfb	353	/* ETHERNET Remote Wake-up frame register length */
Kojto	115:87f2f5183dfb	354	#define ETH_WAKEUP_REGISTER_LENGTH 8
Kojto	115:87f2f5183dfb	355
Kojto	115:87f2f5183dfb	356	/* ETHERNET Missed frames counter Shift */
Kojto	115:87f2f5183dfb	357	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
Kojto	115:87f2f5183dfb	358	/**
Kojto	115:87f2f5183dfb	359	* @}
Kojto	115:87f2f5183dfb	360	*/
Kojto	115:87f2f5183dfb	361
Kojto	115:87f2f5183dfb	362	/* Exported types ------------------------------------------------------------*/
Kojto	115:87f2f5183dfb	363	/** @defgroup ETH_Exported_Types ETH Exported Types
Kojto	115:87f2f5183dfb	364	* @{
Kojto	115:87f2f5183dfb	365	*/
Kojto	115:87f2f5183dfb	366
Kojto	115:87f2f5183dfb	367	/**
Kojto	115:87f2f5183dfb	368	* @brief HAL State structures definition
Kojto	115:87f2f5183dfb	369	*/
Kojto	115:87f2f5183dfb	370	typedef enum
Kojto	115:87f2f5183dfb	371	{
Kojto	115:87f2f5183dfb	372	HAL_ETH_STATE_RESET = 0x00, /!< Peripheral not yet Initialized or disabled /
Kojto	115:87f2f5183dfb	373	HAL_ETH_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
Kojto	115:87f2f5183dfb	374	HAL_ETH_STATE_BUSY = 0x02, /!< an internal process is ongoing /
Kojto	115:87f2f5183dfb	375	HAL_ETH_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
Kojto	115:87f2f5183dfb	376	HAL_ETH_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
Kojto	115:87f2f5183dfb	377	HAL_ETH_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
Kojto	115:87f2f5183dfb	378	HAL_ETH_STATE_BUSY_WR = 0x42, /!< Write process is ongoing /
Kojto	115:87f2f5183dfb	379	HAL_ETH_STATE_BUSY_RD = 0x82, /!< Read process is ongoing /
Kojto	115:87f2f5183dfb	380	HAL_ETH_STATE_TIMEOUT = 0x03, /!< Timeout state /
Kojto	115:87f2f5183dfb	381	HAL_ETH_STATE_ERROR = 0x04 /!< Reception process is ongoing /
Kojto	115:87f2f5183dfb	382	}HAL_ETH_StateTypeDef;
Kojto	115:87f2f5183dfb	383
Kojto	115:87f2f5183dfb	384	/**
Kojto	115:87f2f5183dfb	385	* @brief ETH Init Structure definition
Kojto	115:87f2f5183dfb	386	*/
Kojto	115:87f2f5183dfb	387
Kojto	115:87f2f5183dfb	388	typedef struct
Kojto	115:87f2f5183dfb	389	{
Kojto	115:87f2f5183dfb	390	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
Kojto	115:87f2f5183dfb	391	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
Kojto	115:87f2f5183dfb	392	and the mode (half/full-duplex).
Kojto	115:87f2f5183dfb	393	This parameter can be a value of @ref ETH_AutoNegotiation */
Kojto	115:87f2f5183dfb	394
Kojto	115:87f2f5183dfb	395	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
Kojto	115:87f2f5183dfb	396	This parameter can be a value of @ref ETH_Speed */
Kojto	115:87f2f5183dfb	397
Kojto	115:87f2f5183dfb	398	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
Kojto	115:87f2f5183dfb	399	This parameter can be a value of @ref ETH_Duplex_Mode */
Kojto	115:87f2f5183dfb	400
Kojto	115:87f2f5183dfb	401	uint16_t PhyAddress; /*!< Ethernet PHY address.
Kojto	115:87f2f5183dfb	402	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
Kojto	115:87f2f5183dfb	403
Kojto	115:87f2f5183dfb	404	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
Kojto	115:87f2f5183dfb	405
Kojto	115:87f2f5183dfb	406	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
Kojto	115:87f2f5183dfb	407	This parameter can be a value of @ref ETH_Rx_Mode */
Kojto	115:87f2f5183dfb	408
Kojto	115:87f2f5183dfb	409	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
Kojto	115:87f2f5183dfb	410	This parameter can be a value of @ref ETH_Checksum_Mode */
Kojto	115:87f2f5183dfb	411
Kojto	115:87f2f5183dfb	412	uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
Kojto	115:87f2f5183dfb	413	This parameter can be a value of @ref ETH_Media_Interface */
Kojto	115:87f2f5183dfb	414
Kojto	115:87f2f5183dfb	415	} ETH_InitTypeDef;
Kojto	115:87f2f5183dfb	416
Kojto	115:87f2f5183dfb	417
Kojto	115:87f2f5183dfb	418	/**
Kojto	115:87f2f5183dfb	419	* @brief ETH MAC Configuration Structure definition
Kojto	115:87f2f5183dfb	420	*/
Kojto	115:87f2f5183dfb	421
Kojto	115:87f2f5183dfb	422	typedef struct
Kojto	115:87f2f5183dfb	423	{
Kojto	115:87f2f5183dfb	424	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
Kojto	115:87f2f5183dfb	425	When enabled, the MAC allows no more then 2048 bytes to be received.
Kojto	115:87f2f5183dfb	426	When disabled, the MAC can receive up to 16384 bytes.
Kojto	115:87f2f5183dfb	427	This parameter can be a value of @ref ETH_Watchdog */
Kojto	115:87f2f5183dfb	428
Kojto	115:87f2f5183dfb	429	uint32_t Jabber; /*!< Selects or not Jabber timer
Kojto	115:87f2f5183dfb	430	When enabled, the MAC allows no more then 2048 bytes to be sent.
Kojto	115:87f2f5183dfb	431	When disabled, the MAC can send up to 16384 bytes.
Kojto	115:87f2f5183dfb	432	This parameter can be a value of @ref ETH_Jabber */
Kojto	115:87f2f5183dfb	433
Kojto	115:87f2f5183dfb	434	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
Kojto	115:87f2f5183dfb	435	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
Kojto	115:87f2f5183dfb	436
Kojto	115:87f2f5183dfb	437	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
Kojto	115:87f2f5183dfb	438	This parameter can be a value of @ref ETH_Carrier_Sense */
Kojto	115:87f2f5183dfb	439
Kojto	115:87f2f5183dfb	440	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
Kojto	115:87f2f5183dfb	441	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
Kojto	115:87f2f5183dfb	442	in Half-Duplex mode.
Kojto	115:87f2f5183dfb	443	This parameter can be a value of @ref ETH_Receive_Own */
Kojto	115:87f2f5183dfb	444
Kojto	115:87f2f5183dfb	445	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
Kojto	115:87f2f5183dfb	446	This parameter can be a value of @ref ETH_Loop_Back_Mode */
Kojto	115:87f2f5183dfb	447
Kojto	115:87f2f5183dfb	448	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
Kojto	115:87f2f5183dfb	449	This parameter can be a value of @ref ETH_Checksum_Offload */
Kojto	115:87f2f5183dfb	450
Kojto	115:87f2f5183dfb	451	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
Kojto	115:87f2f5183dfb	452	when a collision occurs (Half-Duplex mode).
Kojto	115:87f2f5183dfb	453	This parameter can be a value of @ref ETH_Retry_Transmission */
Kojto	115:87f2f5183dfb	454
Kojto	115:87f2f5183dfb	455	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
Kojto	115:87f2f5183dfb	456	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
Kojto	115:87f2f5183dfb	457
Kojto	115:87f2f5183dfb	458	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
Kojto	115:87f2f5183dfb	459	This parameter can be a value of @ref ETH_Back_Off_Limit */
Kojto	115:87f2f5183dfb	460
Kojto	115:87f2f5183dfb	461	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
Kojto	115:87f2f5183dfb	462	This parameter can be a value of @ref ETH_Deferral_Check */
Kojto	115:87f2f5183dfb	463
Kojto	115:87f2f5183dfb	464	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
Kojto	115:87f2f5183dfb	465	This parameter can be a value of @ref ETH_Receive_All */
Kojto	115:87f2f5183dfb	466
Kojto	115:87f2f5183dfb	467	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
Kojto	115:87f2f5183dfb	468	This parameter can be a value of @ref ETH_Source_Addr_Filter */
Kojto	115:87f2f5183dfb	469
Kojto	115:87f2f5183dfb	470	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
Kojto	115:87f2f5183dfb	471	This parameter can be a value of @ref ETH_Pass_Control_Frames */
Kojto	115:87f2f5183dfb	472
Kojto	115:87f2f5183dfb	473	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
Kojto	115:87f2f5183dfb	474	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
Kojto	115:87f2f5183dfb	475
Kojto	115:87f2f5183dfb	476	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
Kojto	115:87f2f5183dfb	477	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
Kojto	115:87f2f5183dfb	478
Kojto	115:87f2f5183dfb	479	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
Kojto	115:87f2f5183dfb	480	This parameter can be a value of @ref ETH_Promiscuous_Mode */
Kojto	115:87f2f5183dfb	481
Kojto	115:87f2f5183dfb	482	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
Kojto	115:87f2f5183dfb	483	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
Kojto	115:87f2f5183dfb	484
Kojto	115:87f2f5183dfb	485	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
Kojto	115:87f2f5183dfb	486	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
Kojto	115:87f2f5183dfb	487
Kojto	115:87f2f5183dfb	488	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
Kojto	115:87f2f5183dfb	489	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
Kojto	115:87f2f5183dfb	490
Kojto	115:87f2f5183dfb	491	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
Kojto	115:87f2f5183dfb	492	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
Kojto	115:87f2f5183dfb	493
Kojto	115:87f2f5183dfb	494	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
Kojto	115:87f2f5183dfb	495	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
Kojto	115:87f2f5183dfb	496
Kojto	115:87f2f5183dfb	497	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
Kojto	115:87f2f5183dfb	498	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
Kojto	115:87f2f5183dfb	499
Kojto	115:87f2f5183dfb	500	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
Kojto	115:87f2f5183dfb	501	automatic retransmission of PAUSE Frame.
Kojto	115:87f2f5183dfb	502	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
Kojto	115:87f2f5183dfb	503
Kojto	115:87f2f5183dfb	504	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
Kojto	115:87f2f5183dfb	505	unicast address and unique multicast address).
Kojto	115:87f2f5183dfb	506	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
Kojto	115:87f2f5183dfb	507
Kojto	115:87f2f5183dfb	508	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
Kojto	115:87f2f5183dfb	509	disable its transmitter for a specified time (Pause Time)
Kojto	115:87f2f5183dfb	510	This parameter can be a value of @ref ETH_Receive_Flow_Control */
Kojto	115:87f2f5183dfb	511
Kojto	115:87f2f5183dfb	512	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
Kojto	115:87f2f5183dfb	513	or the MAC back-pressure operation (Half-Duplex mode)
Kojto	115:87f2f5183dfb	514	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
Kojto	115:87f2f5183dfb	515
Kojto	115:87f2f5183dfb	516	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
Kojto	115:87f2f5183dfb	517	comparison and filtering.
Kojto	115:87f2f5183dfb	518	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
Kojto	115:87f2f5183dfb	519
Kojto	115:87f2f5183dfb	520	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
Kojto	115:87f2f5183dfb	521
Kojto	115:87f2f5183dfb	522	} ETH_MACInitTypeDef;
Kojto	115:87f2f5183dfb	523
Kojto	115:87f2f5183dfb	524
Kojto	115:87f2f5183dfb	525	/**
Kojto	115:87f2f5183dfb	526	* @brief ETH DMA Configuration Structure definition
Kojto	115:87f2f5183dfb	527	*/
Kojto	115:87f2f5183dfb	528
Kojto	115:87f2f5183dfb	529	typedef struct
Kojto	115:87f2f5183dfb	530	{
Kojto	115:87f2f5183dfb	531	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
Kojto	115:87f2f5183dfb	532	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
Kojto	115:87f2f5183dfb	533
Kojto	115:87f2f5183dfb	534	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
Kojto	115:87f2f5183dfb	535	This parameter can be a value of @ref ETH_Receive_Store_Forward */
Kojto	115:87f2f5183dfb	536
Kojto	115:87f2f5183dfb	537	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
Kojto	115:87f2f5183dfb	538	This parameter can be a value of @ref ETH_Flush_Received_Frame */
Kojto	115:87f2f5183dfb	539
Kojto	115:87f2f5183dfb	540	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
Kojto	115:87f2f5183dfb	541	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
Kojto	115:87f2f5183dfb	542
Kojto	115:87f2f5183dfb	543	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
Kojto	115:87f2f5183dfb	544	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
Kojto	115:87f2f5183dfb	545
Kojto	115:87f2f5183dfb	546	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
Kojto	115:87f2f5183dfb	547	This parameter can be a value of @ref ETH_Forward_Error_Frames */
Kojto	115:87f2f5183dfb	548
Kojto	115:87f2f5183dfb	549	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
Kojto	115:87f2f5183dfb	550	and length less than 64 bytes) including pad-bytes and CRC)
Kojto	115:87f2f5183dfb	551	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
Kojto	115:87f2f5183dfb	552
Kojto	115:87f2f5183dfb	553	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
Kojto	115:87f2f5183dfb	554	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
Kojto	115:87f2f5183dfb	555
Kojto	115:87f2f5183dfb	556	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
Kojto	115:87f2f5183dfb	557	frame of Transmit data even before obtaining the status for the first frame.
Kojto	115:87f2f5183dfb	558	This parameter can be a value of @ref ETH_Second_Frame_Operate */
Kojto	115:87f2f5183dfb	559
Kojto	115:87f2f5183dfb	560	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
Kojto	115:87f2f5183dfb	561	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
Kojto	115:87f2f5183dfb	562
Kojto	115:87f2f5183dfb	563	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
Kojto	115:87f2f5183dfb	564	This parameter can be a value of @ref ETH_Fixed_Burst */
Kojto	115:87f2f5183dfb	565
Kojto	115:87f2f5183dfb	566	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
Kojto	115:87f2f5183dfb	567	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
Kojto	115:87f2f5183dfb	568
Kojto	115:87f2f5183dfb	569	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
Kojto	115:87f2f5183dfb	570	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
Kojto	115:87f2f5183dfb	571
Kojto	115:87f2f5183dfb	572	uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
Kojto	115:87f2f5183dfb	573	This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
Kojto	115:87f2f5183dfb	574
Kojto	115:87f2f5183dfb	575	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
Kojto	115:87f2f5183dfb	576	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
Kojto	115:87f2f5183dfb	577
Kojto	115:87f2f5183dfb	578	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
Kojto	115:87f2f5183dfb	579	This parameter can be a value of @ref ETH_DMA_Arbitration */
Kojto	115:87f2f5183dfb	580	} ETH_DMAInitTypeDef;
Kojto	115:87f2f5183dfb	581
Kojto	115:87f2f5183dfb	582
Kojto	115:87f2f5183dfb	583	/**
Kojto	115:87f2f5183dfb	584	* @brief ETH DMA Descriptors data structure definition
Kojto	115:87f2f5183dfb	585	*/
Kojto	115:87f2f5183dfb	586
Kojto	115:87f2f5183dfb	587	typedef struct
Kojto	115:87f2f5183dfb	588	{
Kojto	115:87f2f5183dfb	589	__IO uint32_t Status; /!< Status /
Kojto	115:87f2f5183dfb	590
Kojto	115:87f2f5183dfb	591	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
Kojto	115:87f2f5183dfb	592
Kojto	115:87f2f5183dfb	593	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
Kojto	115:87f2f5183dfb	594
Kojto	115:87f2f5183dfb	595	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
Kojto	115:87f2f5183dfb	596
Kojto	115:87f2f5183dfb	597	/!< Enhanced ETHERNET DMA PTP Descriptors /
Kojto	115:87f2f5183dfb	598	uint32_t ExtendedStatus; /!< Extended status for PTP receive descriptor /
Kojto	115:87f2f5183dfb	599
Kojto	115:87f2f5183dfb	600	uint32_t Reserved1; /!< Reserved /
Kojto	115:87f2f5183dfb	601
Kojto	115:87f2f5183dfb	602	uint32_t TimeStampLow; /!< Time Stamp Low value for transmit and receive /
Kojto	115:87f2f5183dfb	603
Kojto	115:87f2f5183dfb	604	uint32_t TimeStampHigh; /!< Time Stamp High value for transmit and receive /
Kojto	115:87f2f5183dfb	605
Kojto	115:87f2f5183dfb	606	} ETH_DMADescTypeDef;
Kojto	115:87f2f5183dfb	607
Kojto	115:87f2f5183dfb	608
Kojto	115:87f2f5183dfb	609	/**
Kojto	115:87f2f5183dfb	610	* @brief Received Frame Informations structure definition
Kojto	115:87f2f5183dfb	611	*/
Kojto	115:87f2f5183dfb	612	typedef struct
Kojto	115:87f2f5183dfb	613	{
Kojto	115:87f2f5183dfb	614	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
Kojto	115:87f2f5183dfb	615
Kojto	115:87f2f5183dfb	616	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
Kojto	115:87f2f5183dfb	617
Kojto	115:87f2f5183dfb	618	uint32_t SegCount; /!< Segment count /
Kojto	115:87f2f5183dfb	619
Kojto	115:87f2f5183dfb	620	uint32_t length; /!< Frame length /
Kojto	115:87f2f5183dfb	621
Kojto	115:87f2f5183dfb	622	uint32_t buffer; /!< Frame buffer /
Kojto	115:87f2f5183dfb	623
Kojto	115:87f2f5183dfb	624	} ETH_DMARxFrameInfos;
Kojto	115:87f2f5183dfb	625
Kojto	115:87f2f5183dfb	626
Kojto	115:87f2f5183dfb	627	/**
Kojto	115:87f2f5183dfb	628	* @brief ETH Handle Structure definition
Kojto	115:87f2f5183dfb	629	*/
Kojto	115:87f2f5183dfb	630
Kojto	115:87f2f5183dfb	631	typedef struct
Kojto	115:87f2f5183dfb	632	{
Kojto	115:87f2f5183dfb	633	ETH_TypeDef Instance; /!< Register base address */
Kojto	115:87f2f5183dfb	634
Kojto	115:87f2f5183dfb	635	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
Kojto	115:87f2f5183dfb	636
Kojto	115:87f2f5183dfb	637	uint32_t LinkStatus; /!< Ethernet link status /
Kojto	115:87f2f5183dfb	638
Kojto	115:87f2f5183dfb	639	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
Kojto	115:87f2f5183dfb	640
Kojto	115:87f2f5183dfb	641	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
Kojto	115:87f2f5183dfb	642
Kojto	115:87f2f5183dfb	643	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
Kojto	115:87f2f5183dfb	644
Kojto	115:87f2f5183dfb	645	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
Kojto	115:87f2f5183dfb	646
Kojto	115:87f2f5183dfb	647	HAL_LockTypeDef Lock; /!< ETH Lock /
Kojto	115:87f2f5183dfb	648
Kojto	115:87f2f5183dfb	649	} ETH_HandleTypeDef;
Kojto	115:87f2f5183dfb	650
Kojto	115:87f2f5183dfb	651	/**
Kojto	115:87f2f5183dfb	652	* @}
Kojto	115:87f2f5183dfb	653	*/
Kojto	115:87f2f5183dfb	654
Kojto	115:87f2f5183dfb	655	/* Exported constants --------------------------------------------------------*/
Kojto	115:87f2f5183dfb	656	/** @defgroup ETH_Exported_Constants ETH Exported Constants
Kojto	115:87f2f5183dfb	657	* @{
Kojto	115:87f2f5183dfb	658	*/
Kojto	115:87f2f5183dfb	659
Kojto	115:87f2f5183dfb	660	/** @defgroup ETH_Buffers_setting ETH Buffers setting
Kojto	115:87f2f5183dfb	661	* @{
Kojto	115:87f2f5183dfb	662	*/
Kojto	115:87f2f5183dfb	663	#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC /
Kojto	115:87f2f5183dfb	664	#define ETH_HEADER ((uint32_t)14) /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
Kojto	115:87f2f5183dfb	665	#define ETH_CRC ((uint32_t)4) /!< Ethernet CRC /
Kojto	115:87f2f5183dfb	666	#define ETH_EXTRA ((uint32_t)2) /!< Extra bytes in some cases /
Kojto	115:87f2f5183dfb	667	#define ETH_VLAN_TAG ((uint32_t)4) /!< optional 802.1q VLAN Tag /
Kojto	115:87f2f5183dfb	668	#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /!< Minimum Ethernet payload size /
Kojto	115:87f2f5183dfb	669	#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /!< Maximum Ethernet payload size /
Kojto	115:87f2f5183dfb	670	#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /!< Jumbo frame payload size /
Kojto	115:87f2f5183dfb	671
Kojto	115:87f2f5183dfb	672	/* Ethernet driver receive buffers are organized in a chained linked-list, when
Kojto	115:87f2f5183dfb	673	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
Kojto	115:87f2f5183dfb	674	to the driver receive buffers memory.
Kojto	115:87f2f5183dfb	675
Kojto	115:87f2f5183dfb	676	Depending on the size of the received ethernet packet and the size of
Kojto	115:87f2f5183dfb	677	each ethernet driver receive buffer, the received packet can take one or more
Kojto	115:87f2f5183dfb	678	ethernet driver receive buffer.
Kojto	115:87f2f5183dfb	679
Kojto	115:87f2f5183dfb	680	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
Kojto	115:87f2f5183dfb	681	and the total count of the driver receive buffers ETH_RXBUFNB.
Kojto	115:87f2f5183dfb	682
Kojto	115:87f2f5183dfb	683	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
Kojto	115:87f2f5183dfb	684	example, they can be reconfigured in the application layer to fit the application
Kojto	115:87f2f5183dfb	685	needs */
Kojto	115:87f2f5183dfb	686
Kojto	115:87f2f5183dfb	687	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
Kojto	115:87f2f5183dfb	688	packet */
Kojto	115:87f2f5183dfb	689	#ifndef ETH_RX_BUF_SIZE
Kojto	115:87f2f5183dfb	690	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
Kojto	115:87f2f5183dfb	691	#endif
Kojto	115:87f2f5183dfb	692
Kojto	115:87f2f5183dfb	693	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
Kojto	115:87f2f5183dfb	694	#ifndef ETH_RXBUFNB
Kojto	115:87f2f5183dfb	695	#define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
Kojto	115:87f2f5183dfb	696	#endif
Kojto	115:87f2f5183dfb	697
Kojto	115:87f2f5183dfb	698
Kojto	115:87f2f5183dfb	699	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
Kojto	115:87f2f5183dfb	700	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
Kojto	115:87f2f5183dfb	701	driver transmit buffers memory to the TxFIFO.
Kojto	115:87f2f5183dfb	702
Kojto	115:87f2f5183dfb	703	Depending on the size of the Ethernet packet to be transmitted and the size of
Kojto	115:87f2f5183dfb	704	each ethernet driver transmit buffer, the packet to be transmitted can take
Kojto	115:87f2f5183dfb	705	one or more ethernet driver transmit buffer.
Kojto	115:87f2f5183dfb	706
Kojto	115:87f2f5183dfb	707	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
Kojto	115:87f2f5183dfb	708	and the total count of the driver transmit buffers ETH_TXBUFNB.
Kojto	115:87f2f5183dfb	709
Kojto	115:87f2f5183dfb	710	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
Kojto	115:87f2f5183dfb	711	example, they can be reconfigured in the application layer to fit the application
Kojto	115:87f2f5183dfb	712	needs */
Kojto	115:87f2f5183dfb	713
Kojto	115:87f2f5183dfb	714	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
Kojto	115:87f2f5183dfb	715	packet */
Kojto	115:87f2f5183dfb	716	#ifndef ETH_TX_BUF_SIZE
Kojto	115:87f2f5183dfb	717	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
Kojto	115:87f2f5183dfb	718	#endif
Kojto	115:87f2f5183dfb	719
Kojto	115:87f2f5183dfb	720	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
Kojto	115:87f2f5183dfb	721	#ifndef ETH_TXBUFNB
Kojto	115:87f2f5183dfb	722	#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
Kojto	115:87f2f5183dfb	723	#endif
Kojto	115:87f2f5183dfb	724
Kojto	115:87f2f5183dfb	725	/**
Kojto	115:87f2f5183dfb	726	* @}
Kojto	115:87f2f5183dfb	727	*/
Kojto	115:87f2f5183dfb	728
Kojto	115:87f2f5183dfb	729	/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
Kojto	115:87f2f5183dfb	730	* @{
Kojto	115:87f2f5183dfb	731	*/
Kojto	115:87f2f5183dfb	732
Kojto	115:87f2f5183dfb	733	/*
Kojto	115:87f2f5183dfb	734	DMA Tx Descriptor
Kojto	115:87f2f5183dfb	735	-----------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	736	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
Kojto	115:87f2f5183dfb	737	-----------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	738	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
Kojto	115:87f2f5183dfb	739	-----------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	740	TDES2 \| Buffer1 Address [31:0] \|
Kojto	115:87f2f5183dfb	741	-----------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	742	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
Kojto	115:87f2f5183dfb	743	-----------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	744	*/
Kojto	115:87f2f5183dfb	745
Kojto	115:87f2f5183dfb	746	/**
Kojto	115:87f2f5183dfb	747	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
Kojto	115:87f2f5183dfb	748	*/
Kojto	115:87f2f5183dfb	749	#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
Kojto	115:87f2f5183dfb	750	#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /!< Interrupt on Completion /
Kojto	115:87f2f5183dfb	751	#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /!< Last Segment /
Kojto	115:87f2f5183dfb	752	#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /!< First Segment /
Kojto	115:87f2f5183dfb	753	#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /!< Disable CRC /
Kojto	115:87f2f5183dfb	754	#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /!< Disable Padding /
Kojto	115:87f2f5183dfb	755	#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /!< Transmit Time Stamp Enable /
Kojto	115:87f2f5183dfb	756	#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /!< Checksum Insertion Control: 4 cases /
Kojto	115:87f2f5183dfb	757	#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /!< Do Nothing: Checksum Engine is bypassed /
Kojto	115:87f2f5183dfb	758	#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /!< IPV4 header Checksum Insertion /
Kojto	115:87f2f5183dfb	759	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
Kojto	115:87f2f5183dfb	760	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
Kojto	115:87f2f5183dfb	761	#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /!< Transmit End of Ring /
Kojto	115:87f2f5183dfb	762	#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /!< Second Address Chained /
Kojto	115:87f2f5183dfb	763	#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /!< Tx Time Stamp Status /
Kojto	115:87f2f5183dfb	764	#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /!< IP Header Error /
Kojto	115:87f2f5183dfb	765	#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
Kojto	115:87f2f5183dfb	766	#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /!< Jabber Timeout /
Kojto	115:87f2f5183dfb	767	#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
Kojto	115:87f2f5183dfb	768	#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /!< Payload Checksum Error /
Kojto	115:87f2f5183dfb	769	#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /!< Loss of Carrier: carrier lost during transmission /
Kojto	115:87f2f5183dfb	770	#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /!< No Carrier: no carrier signal from the transceiver /
Kojto	115:87f2f5183dfb	771	#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /!< Late Collision: transmission aborted due to collision /
Kojto	115:87f2f5183dfb	772	#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /!< Excessive Collision: transmission aborted after 16 collisions /
Kojto	115:87f2f5183dfb	773	#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /!< VLAN Frame /
Kojto	115:87f2f5183dfb	774	#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /!< Collision Count /
Kojto	115:87f2f5183dfb	775	#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /!< Excessive Deferral /
Kojto	115:87f2f5183dfb	776	#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /!< Underflow Error: late data arrival from the memory /
Kojto	115:87f2f5183dfb	777	#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /!< Deferred Bit /
Kojto	115:87f2f5183dfb	778
Kojto	115:87f2f5183dfb	779	/**
Kojto	115:87f2f5183dfb	780	* @brief Bit definition of TDES1 register
Kojto	115:87f2f5183dfb	781	*/
Kojto	115:87f2f5183dfb	782	#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /!< Transmit Buffer2 Size /
Kojto	115:87f2f5183dfb	783	#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /!< Transmit Buffer1 Size /
Kojto	115:87f2f5183dfb	784
Kojto	115:87f2f5183dfb	785	/**
Kojto	115:87f2f5183dfb	786	* @brief Bit definition of TDES2 register
Kojto	115:87f2f5183dfb	787	*/
Kojto	115:87f2f5183dfb	788	#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
Kojto	115:87f2f5183dfb	789
Kojto	115:87f2f5183dfb	790	/**
Kojto	115:87f2f5183dfb	791	* @brief Bit definition of TDES3 register
Kojto	115:87f2f5183dfb	792	*/
Kojto	115:87f2f5183dfb	793	#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
Kojto	115:87f2f5183dfb	794
Kojto	115:87f2f5183dfb	795	/*---------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	796	TDES6 \| Transmit Time Stamp Low [31:0] \|
Kojto	115:87f2f5183dfb	797	-----------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	798	TDES7 \| Transmit Time Stamp High [31:0] \|
Kojto	115:87f2f5183dfb	799	----------------------------------------------------------------------------------------------*/
Kojto	115:87f2f5183dfb	800
Kojto	115:87f2f5183dfb	801	/* Bit definition of TDES6 register */
Kojto	115:87f2f5183dfb	802	#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
Kojto	115:87f2f5183dfb	803
Kojto	115:87f2f5183dfb	804	/* Bit definition of TDES7 register */
Kojto	115:87f2f5183dfb	805	#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
Kojto	115:87f2f5183dfb	806
Kojto	115:87f2f5183dfb	807	/**
Kojto	115:87f2f5183dfb	808	* @}
Kojto	115:87f2f5183dfb	809	*/
Kojto	115:87f2f5183dfb	810	/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
Kojto	115:87f2f5183dfb	811	* @{
Kojto	115:87f2f5183dfb	812	*/
Kojto	115:87f2f5183dfb	813
Kojto	115:87f2f5183dfb	814	/*
Kojto	115:87f2f5183dfb	815	DMA Rx Descriptor
Kojto	115:87f2f5183dfb	816	--------------------------------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	817	RDES0 \| OWN(31) \| Status [30:0] \|
Kojto	115:87f2f5183dfb	818	---------------------------------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	819	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
Kojto	115:87f2f5183dfb	820	---------------------------------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	821	RDES2 \| Buffer1 Address [31:0] \|
Kojto	115:87f2f5183dfb	822	---------------------------------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	823	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
Kojto	115:87f2f5183dfb	824	---------------------------------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	825	*/
Kojto	115:87f2f5183dfb	826
Kojto	115:87f2f5183dfb	827	/**
Kojto	115:87f2f5183dfb	828	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
Kojto	115:87f2f5183dfb	829	*/
Kojto	115:87f2f5183dfb	830	#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
Kojto	115:87f2f5183dfb	831	#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /!< DA Filter Fail for the rx frame /
Kojto	115:87f2f5183dfb	832	#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /!< Receive descriptor frame length /
Kojto	115:87f2f5183dfb	833	#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
Kojto	115:87f2f5183dfb	834	#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /!< Descriptor error: no more descriptors for receive frame /
Kojto	115:87f2f5183dfb	835	#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /!< SA Filter Fail for the received frame /
Kojto	115:87f2f5183dfb	836	#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /!< Frame size not matching with length field /
Kojto	115:87f2f5183dfb	837	#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /!< Overflow Error: Frame was damaged due to buffer overflow /
Kojto	115:87f2f5183dfb	838	#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /!< VLAN Tag: received frame is a VLAN frame /
Kojto	115:87f2f5183dfb	839	#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /!< First descriptor of the frame /
Kojto	115:87f2f5183dfb	840	#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /!< Last descriptor of the frame /
Kojto	115:87f2f5183dfb	841	#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /!< IPC Checksum Error: Rx Ipv4 header checksum error /
Kojto	115:87f2f5183dfb	842	#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /!< Late collision occurred during reception /
Kojto	115:87f2f5183dfb	843	#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /!< Frame type - Ethernet, otherwise 802.3 /
Kojto	115:87f2f5183dfb	844	#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /!< Receive Watchdog Timeout: watchdog timer expired during reception /
Kojto	115:87f2f5183dfb	845	#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /!< Receive error: error reported by MII interface /
Kojto	115:87f2f5183dfb	846	#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /!< Dribble bit error: frame contains non int multiple of 8 bits /
Kojto	115:87f2f5183dfb	847	#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /!< CRC error /
Kojto	115:87f2f5183dfb	848	#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
Kojto	115:87f2f5183dfb	849
Kojto	115:87f2f5183dfb	850	/**
Kojto	115:87f2f5183dfb	851	* @brief Bit definition of RDES1 register
Kojto	115:87f2f5183dfb	852	*/
Kojto	115:87f2f5183dfb	853	#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /!< Disable Interrupt on Completion /
Kojto	115:87f2f5183dfb	854	#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /!< Receive Buffer2 Size /
Kojto	115:87f2f5183dfb	855	#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /!< Receive End of Ring /
Kojto	115:87f2f5183dfb	856	#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /!< Second Address Chained /
Kojto	115:87f2f5183dfb	857	#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /!< Receive Buffer1 Size /
Kojto	115:87f2f5183dfb	858
Kojto	115:87f2f5183dfb	859	/**
Kojto	115:87f2f5183dfb	860	* @brief Bit definition of RDES2 register
Kojto	115:87f2f5183dfb	861	*/
Kojto	115:87f2f5183dfb	862	#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
Kojto	115:87f2f5183dfb	863
Kojto	115:87f2f5183dfb	864	/**
Kojto	115:87f2f5183dfb	865	* @brief Bit definition of RDES3 register
Kojto	115:87f2f5183dfb	866	*/
Kojto	115:87f2f5183dfb	867	#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
Kojto	115:87f2f5183dfb	868
Kojto	115:87f2f5183dfb	869	/*---------------------------------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	870	RDES4 \| Reserved[31:15] \| Extended Status [14:0] \|
Kojto	115:87f2f5183dfb	871	---------------------------------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	872	RDES5 \| Reserved[31:0] \|
Kojto	115:87f2f5183dfb	873	---------------------------------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	874	RDES6 \| Receive Time Stamp Low [31:0] \|
Kojto	115:87f2f5183dfb	875	---------------------------------------------------------------------------------------------------------------------
Kojto	115:87f2f5183dfb	876	RDES7 \| Receive Time Stamp High [31:0] \|
Kojto	115:87f2f5183dfb	877	--------------------------------------------------------------------------------------------------------------------*/
Kojto	115:87f2f5183dfb	878
Kojto	115:87f2f5183dfb	879	/* Bit definition of RDES4 register */
Kojto	115:87f2f5183dfb	880	#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
Kojto	115:87f2f5183dfb	881	#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
Kojto	115:87f2f5183dfb	882	#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
Kojto	115:87f2f5183dfb	883	#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
Kojto	115:87f2f5183dfb	884	#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
Kojto	115:87f2f5183dfb	885	#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
Kojto	115:87f2f5183dfb	886	#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
Kojto	115:87f2f5183dfb	887	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
Kojto	115:87f2f5183dfb	888	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
Kojto	115:87f2f5183dfb	889	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
Kojto	115:87f2f5183dfb	890	#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
Kojto	115:87f2f5183dfb	891	#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
Kojto	115:87f2f5183dfb	892	#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
Kojto	115:87f2f5183dfb	893	#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
Kojto	115:87f2f5183dfb	894	#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
Kojto	115:87f2f5183dfb	895	#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
Kojto	115:87f2f5183dfb	896	#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
Kojto	115:87f2f5183dfb	897	#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
Kojto	115:87f2f5183dfb	898	#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
Kojto	115:87f2f5183dfb	899
Kojto	115:87f2f5183dfb	900	/* Bit definition of RDES6 register */
Kojto	115:87f2f5183dfb	901	#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
Kojto	115:87f2f5183dfb	902
Kojto	115:87f2f5183dfb	903	/* Bit definition of RDES7 register */
Kojto	115:87f2f5183dfb	904	#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
Kojto	115:87f2f5183dfb	905	/**
Kojto	115:87f2f5183dfb	906	* @}
Kojto	115:87f2f5183dfb	907	*/
Kojto	115:87f2f5183dfb	908	/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
Kojto	115:87f2f5183dfb	909	* @{
Kojto	115:87f2f5183dfb	910	*/
Kojto	115:87f2f5183dfb	911	#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	912	#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	913
Kojto	115:87f2f5183dfb	914	/**
Kojto	115:87f2f5183dfb	915	* @}
Kojto	115:87f2f5183dfb	916	*/
Kojto	115:87f2f5183dfb	917	/** @defgroup ETH_Speed ETH Speed
Kojto	115:87f2f5183dfb	918	* @{
Kojto	115:87f2f5183dfb	919	*/
Kojto	115:87f2f5183dfb	920	#define ETH_SPEED_10M ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	921	#define ETH_SPEED_100M ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	922
Kojto	115:87f2f5183dfb	923	/**
Kojto	115:87f2f5183dfb	924	* @}
Kojto	115:87f2f5183dfb	925	*/
Kojto	115:87f2f5183dfb	926	/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
Kojto	115:87f2f5183dfb	927	* @{
Kojto	115:87f2f5183dfb	928	*/
Kojto	115:87f2f5183dfb	929	#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	930	#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	931	/**
Kojto	115:87f2f5183dfb	932	* @}
Kojto	115:87f2f5183dfb	933	*/
Kojto	115:87f2f5183dfb	934	/** @defgroup ETH_Rx_Mode ETH Rx Mode
Kojto	115:87f2f5183dfb	935	* @{
Kojto	115:87f2f5183dfb	936	*/
Kojto	115:87f2f5183dfb	937	#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	938	#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	939	/**
Kojto	115:87f2f5183dfb	940	* @}
Kojto	115:87f2f5183dfb	941	*/
Kojto	115:87f2f5183dfb	942
Kojto	115:87f2f5183dfb	943	/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
Kojto	115:87f2f5183dfb	944	* @{
Kojto	115:87f2f5183dfb	945	*/
Kojto	115:87f2f5183dfb	946	#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	947	#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	948	/**
Kojto	115:87f2f5183dfb	949	* @}
Kojto	115:87f2f5183dfb	950	*/
Kojto	115:87f2f5183dfb	951
Kojto	115:87f2f5183dfb	952	/** @defgroup ETH_Media_Interface ETH Media Interface
Kojto	115:87f2f5183dfb	953	* @{
Kojto	115:87f2f5183dfb	954	*/
Kojto	115:87f2f5183dfb	955	#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	956	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
Kojto	115:87f2f5183dfb	957	/**
Kojto	115:87f2f5183dfb	958	* @}
Kojto	115:87f2f5183dfb	959	*/
Kojto	115:87f2f5183dfb	960
Kojto	115:87f2f5183dfb	961	/** @defgroup ETH_Watchdog ETH Watchdog
Kojto	115:87f2f5183dfb	962	* @{
Kojto	115:87f2f5183dfb	963	*/
Kojto	115:87f2f5183dfb	964	#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	965	#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	966	/**
Kojto	115:87f2f5183dfb	967	* @}
Kojto	115:87f2f5183dfb	968	*/
Kojto	115:87f2f5183dfb	969
Kojto	115:87f2f5183dfb	970	/** @defgroup ETH_Jabber ETH Jabber
Kojto	115:87f2f5183dfb	971	* @{
Kojto	115:87f2f5183dfb	972	*/
Kojto	115:87f2f5183dfb	973	#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	974	#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	975	/**
Kojto	115:87f2f5183dfb	976	* @}
Kojto	115:87f2f5183dfb	977	*/
Kojto	115:87f2f5183dfb	978
Kojto	115:87f2f5183dfb	979	/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
Kojto	115:87f2f5183dfb	980	* @{
Kojto	115:87f2f5183dfb	981	*/
Kojto	115:87f2f5183dfb	982	#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /!< minimum IFG between frames during transmission is 96Bit /
Kojto	115:87f2f5183dfb	983	#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /!< minimum IFG between frames during transmission is 88Bit /
Kojto	115:87f2f5183dfb	984	#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /!< minimum IFG between frames during transmission is 80Bit /
Kojto	115:87f2f5183dfb	985	#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /!< minimum IFG between frames during transmission is 72Bit /
Kojto	115:87f2f5183dfb	986	#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /!< minimum IFG between frames during transmission is 64Bit /
Kojto	115:87f2f5183dfb	987	#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /!< minimum IFG between frames during transmission is 56Bit /
Kojto	115:87f2f5183dfb	988	#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /!< minimum IFG between frames during transmission is 48Bit /
Kojto	115:87f2f5183dfb	989	#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /!< minimum IFG between frames during transmission is 40Bit /
Kojto	115:87f2f5183dfb	990	/**
Kojto	115:87f2f5183dfb	991	* @}
Kojto	115:87f2f5183dfb	992	*/
Kojto	115:87f2f5183dfb	993
Kojto	115:87f2f5183dfb	994	/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
Kojto	115:87f2f5183dfb	995	* @{
Kojto	115:87f2f5183dfb	996	*/
Kojto	115:87f2f5183dfb	997	#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	998	#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	999	/**
Kojto	115:87f2f5183dfb	1000	* @}
Kojto	115:87f2f5183dfb	1001	*/
Kojto	115:87f2f5183dfb	1002
Kojto	115:87f2f5183dfb	1003	/** @defgroup ETH_Receive_Own ETH Receive Own
Kojto	115:87f2f5183dfb	1004	* @{
Kojto	115:87f2f5183dfb	1005	*/
Kojto	115:87f2f5183dfb	1006	#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1007	#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	1008	/**
Kojto	115:87f2f5183dfb	1009	* @}
Kojto	115:87f2f5183dfb	1010	*/
Kojto	115:87f2f5183dfb	1011
Kojto	115:87f2f5183dfb	1012	/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
Kojto	115:87f2f5183dfb	1013	* @{
Kojto	115:87f2f5183dfb	1014	*/
Kojto	115:87f2f5183dfb	1015	#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	1016	#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1017	/**
Kojto	115:87f2f5183dfb	1018	* @}
Kojto	115:87f2f5183dfb	1019	*/
Kojto	115:87f2f5183dfb	1020
Kojto	115:87f2f5183dfb	1021	/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
Kojto	115:87f2f5183dfb	1022	* @{
Kojto	115:87f2f5183dfb	1023	*/
Kojto	115:87f2f5183dfb	1024	#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	1025	#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1026	/**
Kojto	115:87f2f5183dfb	1027	* @}
Kojto	115:87f2f5183dfb	1028	*/
Kojto	115:87f2f5183dfb	1029
Kojto	115:87f2f5183dfb	1030	/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
Kojto	115:87f2f5183dfb	1031	* @{
Kojto	115:87f2f5183dfb	1032	*/
Kojto	115:87f2f5183dfb	1033	#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1034	#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	1035	/**
Kojto	115:87f2f5183dfb	1036	* @}
Kojto	115:87f2f5183dfb	1037	*/
Kojto	115:87f2f5183dfb	1038
Kojto	115:87f2f5183dfb	1039	/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
Kojto	115:87f2f5183dfb	1040	* @{
Kojto	115:87f2f5183dfb	1041	*/
Kojto	115:87f2f5183dfb	1042	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	1043	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1044	/**
Kojto	115:87f2f5183dfb	1045	* @}
Kojto	115:87f2f5183dfb	1046	*/
Kojto	115:87f2f5183dfb	1047
Kojto	115:87f2f5183dfb	1048	/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
Kojto	115:87f2f5183dfb	1049	* @{
Kojto	115:87f2f5183dfb	1050	*/
Kojto	115:87f2f5183dfb	1051	#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1052	#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	1053	#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	1054	#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
Kojto	115:87f2f5183dfb	1055	/**
Kojto	115:87f2f5183dfb	1056	* @}
Kojto	115:87f2f5183dfb	1057	*/
Kojto	115:87f2f5183dfb	1058
Kojto	115:87f2f5183dfb	1059	/** @defgroup ETH_Deferral_Check ETH Deferral Check
Kojto	115:87f2f5183dfb	1060	* @{
Kojto	115:87f2f5183dfb	1061	*/
Kojto	115:87f2f5183dfb	1062	#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	1063	#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1064	/**
Kojto	115:87f2f5183dfb	1065	* @}
Kojto	115:87f2f5183dfb	1066	*/
Kojto	115:87f2f5183dfb	1067
Kojto	115:87f2f5183dfb	1068	/** @defgroup ETH_Receive_All ETH Receive All
Kojto	115:87f2f5183dfb	1069	* @{
Kojto	115:87f2f5183dfb	1070	*/
Kojto	115:87f2f5183dfb	1071	#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	1072	#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1073	/**
Kojto	115:87f2f5183dfb	1074	* @}
Kojto	115:87f2f5183dfb	1075	*/
Kojto	115:87f2f5183dfb	1076
Kojto	115:87f2f5183dfb	1077	/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
Kojto	115:87f2f5183dfb	1078	* @{
Kojto	115:87f2f5183dfb	1079	*/
Kojto	115:87f2f5183dfb	1080	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	1081	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
Kojto	115:87f2f5183dfb	1082	#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1083	/**
Kojto	115:87f2f5183dfb	1084	* @}
Kojto	115:87f2f5183dfb	1085	*/
Kojto	115:87f2f5183dfb	1086
Kojto	115:87f2f5183dfb	1087	/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
Kojto	115:87f2f5183dfb	1088	* @{
Kojto	115:87f2f5183dfb	1089	*/
Kojto	115:87f2f5183dfb	1090	#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /!< MAC filters all control frames from reaching the application /
Kojto	115:87f2f5183dfb	1091	#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /!< MAC forwards all control frames to application even if they fail the Address Filter /
Kojto	115:87f2f5183dfb	1092	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /!< MAC forwards control frames that pass the Address Filter. /
Kojto	115:87f2f5183dfb	1093	/**
Kojto	115:87f2f5183dfb	1094	* @}
Kojto	115:87f2f5183dfb	1095	*/
Kojto	115:87f2f5183dfb	1096
Kojto	115:87f2f5183dfb	1097	/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
Kojto	115:87f2f5183dfb	1098	* @{
Kojto	115:87f2f5183dfb	1099	*/
Kojto	115:87f2f5183dfb	1100	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1101	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	1102	/**
Kojto	115:87f2f5183dfb	1103	* @}
Kojto	115:87f2f5183dfb	1104	*/
Kojto	115:87f2f5183dfb	1105
Kojto	115:87f2f5183dfb	1106	/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
Kojto	115:87f2f5183dfb	1107	* @{
Kojto	115:87f2f5183dfb	1108	*/
Kojto	115:87f2f5183dfb	1109	#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1110	#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	1111	/**
Kojto	115:87f2f5183dfb	1112	* @}
Kojto	115:87f2f5183dfb	1113	*/
Kojto	115:87f2f5183dfb	1114
Kojto	115:87f2f5183dfb	1115	/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
Kojto	115:87f2f5183dfb	1116	* @{
Kojto	115:87f2f5183dfb	1117	*/
Kojto	115:87f2f5183dfb	1118	#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	1119	#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1120	/**
Kojto	115:87f2f5183dfb	1121	* @}
Kojto	115:87f2f5183dfb	1122	*/
Kojto	115:87f2f5183dfb	1123
Kojto	115:87f2f5183dfb	1124	/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
Kojto	115:87f2f5183dfb	1125	* @{
Kojto	115:87f2f5183dfb	1126	*/
Kojto	115:87f2f5183dfb	1127	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
Kojto	115:87f2f5183dfb	1128	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	1129	#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1130	#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	1131	/**
Kojto	115:87f2f5183dfb	1132	* @}
Kojto	115:87f2f5183dfb	1133	*/
Kojto	115:87f2f5183dfb	1134
Kojto	115:87f2f5183dfb	1135	/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
Kojto	115:87f2f5183dfb	1136	* @{
Kojto	115:87f2f5183dfb	1137	*/
Kojto	115:87f2f5183dfb	1138	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
Kojto	115:87f2f5183dfb	1139	#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	1140	#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1141	/**
Kojto	115:87f2f5183dfb	1142	* @}
Kojto	115:87f2f5183dfb	1143	*/
Kojto	115:87f2f5183dfb	1144
Kojto	115:87f2f5183dfb	1145	/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
Kojto	115:87f2f5183dfb	1146	* @{
Kojto	115:87f2f5183dfb	1147	*/
Kojto	115:87f2f5183dfb	1148	#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1149	#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	1150	/**
Kojto	115:87f2f5183dfb	1151	* @}
Kojto	115:87f2f5183dfb	1152	*/
Kojto	115:87f2f5183dfb	1153
Kojto	115:87f2f5183dfb	1154	/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
Kojto	115:87f2f5183dfb	1155	* @{
Kojto	115:87f2f5183dfb	1156	*/
Kojto	115:87f2f5183dfb	1157	#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /!< Pause time minus 4 slot times /
Kojto	115:87f2f5183dfb	1158	#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /!< Pause time minus 28 slot times /
Kojto	115:87f2f5183dfb	1159	#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /!< Pause time minus 144 slot times /
Kojto	115:87f2f5183dfb	1160	#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /!< Pause time minus 256 slot times /
Kojto	115:87f2f5183dfb	1161	/**
Kojto	115:87f2f5183dfb	1162	* @}
Kojto	115:87f2f5183dfb	1163	*/
Kojto	115:87f2f5183dfb	1164
Kojto	115:87f2f5183dfb	1165	/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
Kojto	115:87f2f5183dfb	1166	* @{
Kojto	115:87f2f5183dfb	1167	*/
Kojto	115:87f2f5183dfb	1168	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	1169	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1170	/**
Kojto	115:87f2f5183dfb	1171	* @}
Kojto	115:87f2f5183dfb	1172	*/
Kojto	115:87f2f5183dfb	1173
Kojto	115:87f2f5183dfb	1174	/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
Kojto	115:87f2f5183dfb	1175	* @{
Kojto	115:87f2f5183dfb	1176	*/
Kojto	115:87f2f5183dfb	1177	#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	1178	#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1179	/**
Kojto	115:87f2f5183dfb	1180	* @}
Kojto	115:87f2f5183dfb	1181	*/
Kojto	115:87f2f5183dfb	1182
Kojto	115:87f2f5183dfb	1183	/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
Kojto	115:87f2f5183dfb	1184	* @{
Kojto	115:87f2f5183dfb	1185	*/
Kojto	115:87f2f5183dfb	1186	#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	1187	#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1188	/**
Kojto	115:87f2f5183dfb	1189	* @}
Kojto	115:87f2f5183dfb	1190	*/
Kojto	115:87f2f5183dfb	1191
Kojto	115:87f2f5183dfb	1192	/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
Kojto	115:87f2f5183dfb	1193	* @{
Kojto	115:87f2f5183dfb	1194	*/
Kojto	115:87f2f5183dfb	1195	#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	1196	#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1197	/**
Kojto	115:87f2f5183dfb	1198	* @}
Kojto	115:87f2f5183dfb	1199	*/
Kojto	115:87f2f5183dfb	1200
Kojto	115:87f2f5183dfb	1201	/** @defgroup ETH_MAC_addresses ETH MAC addresses
Kojto	115:87f2f5183dfb	1202	* @{
Kojto	115:87f2f5183dfb	1203	*/
Kojto	115:87f2f5183dfb	1204	#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1205	#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	1206	#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	1207	#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
Kojto	115:87f2f5183dfb	1208	/**
Kojto	115:87f2f5183dfb	1209	* @}
Kojto	115:87f2f5183dfb	1210	*/
Kojto	115:87f2f5183dfb	1211
Kojto	115:87f2f5183dfb	1212	/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
Kojto	115:87f2f5183dfb	1213	* @{
Kojto	115:87f2f5183dfb	1214	*/
Kojto	115:87f2f5183dfb	1215	#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1216	#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	1217	/**
Kojto	115:87f2f5183dfb	1218	* @}
Kojto	115:87f2f5183dfb	1219	*/
Kojto	115:87f2f5183dfb	1220
Kojto	115:87f2f5183dfb	1221	/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
Kojto	115:87f2f5183dfb	1222	* @{
Kojto	115:87f2f5183dfb	1223	*/
Kojto	115:87f2f5183dfb	1224	#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /!< Mask MAC Address high reg bits [15:8] /
Kojto	115:87f2f5183dfb	1225	#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /!< Mask MAC Address high reg bits [7:0] /
Kojto	115:87f2f5183dfb	1226	#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /!< Mask MAC Address low reg bits [31:24] /
Kojto	115:87f2f5183dfb	1227	#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /!< Mask MAC Address low reg bits [23:16] /
Kojto	115:87f2f5183dfb	1228	#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /!< Mask MAC Address low reg bits [15:8] /
Kojto	115:87f2f5183dfb	1229	#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /!< Mask MAC Address low reg bits [70] /
Kojto	115:87f2f5183dfb	1230	/**
Kojto	115:87f2f5183dfb	1231	* @}
Kojto	115:87f2f5183dfb	1232	*/
Kojto	115:87f2f5183dfb	1233
Kojto	115:87f2f5183dfb	1234	/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
Kojto	115:87f2f5183dfb	1235	* @{
Kojto	115:87f2f5183dfb	1236	*/
Kojto	115:87f2f5183dfb	1237	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
Kojto	115:87f2f5183dfb	1238	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
Kojto	115:87f2f5183dfb	1239	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
Kojto	115:87f2f5183dfb	1240	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
Kojto	115:87f2f5183dfb	1241	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
Kojto	115:87f2f5183dfb	1242	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
Kojto	115:87f2f5183dfb	1243	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
Kojto	115:87f2f5183dfb	1244	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
Kojto	115:87f2f5183dfb	1245	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
Kojto	115:87f2f5183dfb	1246	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
Kojto	115:87f2f5183dfb	1247	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
Kojto	115:87f2f5183dfb	1248	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
Kojto	115:87f2f5183dfb	1249	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
Kojto	115:87f2f5183dfb	1250	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
Kojto	115:87f2f5183dfb	1251	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
Kojto	115:87f2f5183dfb	1252	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
Kojto	115:87f2f5183dfb	1253	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
Kojto	115:87f2f5183dfb	1254	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
Kojto	115:87f2f5183dfb	1255	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
Kojto	115:87f2f5183dfb	1256	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
Kojto	115:87f2f5183dfb	1257	#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
Kojto	115:87f2f5183dfb	1258	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
Kojto	115:87f2f5183dfb	1259	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
Kojto	115:87f2f5183dfb	1260	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
Kojto	115:87f2f5183dfb	1261	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
Kojto	115:87f2f5183dfb	1262	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
Kojto	115:87f2f5183dfb	1263	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
Kojto	115:87f2f5183dfb	1264	/**
Kojto	115:87f2f5183dfb	1265	* @}
Kojto	115:87f2f5183dfb	1266	*/
Kojto	115:87f2f5183dfb	1267
Kojto	115:87f2f5183dfb	1268	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
Kojto	115:87f2f5183dfb	1269	* @{
Kojto	115:87f2f5183dfb	1270	*/
Kojto	115:87f2f5183dfb	1271	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1272	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	1273	/**
Kojto	115:87f2f5183dfb	1274	* @}
Kojto	115:87f2f5183dfb	1275	*/
Kojto	115:87f2f5183dfb	1276
Kojto	115:87f2f5183dfb	1277	/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
Kojto	115:87f2f5183dfb	1278	* @{
Kojto	115:87f2f5183dfb	1279	*/
Kojto	115:87f2f5183dfb	1280	#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	1281	#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1282	/**
Kojto	115:87f2f5183dfb	1283	* @}
Kojto	115:87f2f5183dfb	1284	*/
Kojto	115:87f2f5183dfb	1285
Kojto	115:87f2f5183dfb	1286	/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
Kojto	115:87f2f5183dfb	1287	* @{
Kojto	115:87f2f5183dfb	1288	*/
Kojto	115:87f2f5183dfb	1289	#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1290	#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	1291	/**
Kojto	115:87f2f5183dfb	1292	* @}
Kojto	115:87f2f5183dfb	1293	*/
Kojto	115:87f2f5183dfb	1294
Kojto	115:87f2f5183dfb	1295	/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
Kojto	115:87f2f5183dfb	1296	* @{
Kojto	115:87f2f5183dfb	1297	*/
Kojto	115:87f2f5183dfb	1298	#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	1299	#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1300	/**
Kojto	115:87f2f5183dfb	1301	* @}
Kojto	115:87f2f5183dfb	1302	*/
Kojto	115:87f2f5183dfb	1303
Kojto	115:87f2f5183dfb	1304	/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
Kojto	115:87f2f5183dfb	1305	* @{
Kojto	115:87f2f5183dfb	1306	*/
Kojto	115:87f2f5183dfb	1307	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
Kojto	115:87f2f5183dfb	1308	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
Kojto	115:87f2f5183dfb	1309	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
Kojto	115:87f2f5183dfb	1310	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
Kojto	115:87f2f5183dfb	1311	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
Kojto	115:87f2f5183dfb	1312	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
Kojto	115:87f2f5183dfb	1313	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
Kojto	115:87f2f5183dfb	1314	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
Kojto	115:87f2f5183dfb	1315	/**
Kojto	115:87f2f5183dfb	1316	* @}
Kojto	115:87f2f5183dfb	1317	*/
Kojto	115:87f2f5183dfb	1318
Kojto	115:87f2f5183dfb	1319	/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
Kojto	115:87f2f5183dfb	1320	* @{
Kojto	115:87f2f5183dfb	1321	*/
Kojto	115:87f2f5183dfb	1322	#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	1323	#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1324	/**
Kojto	115:87f2f5183dfb	1325	* @}
Kojto	115:87f2f5183dfb	1326	*/
Kojto	115:87f2f5183dfb	1327
Kojto	115:87f2f5183dfb	1328	/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
Kojto	115:87f2f5183dfb	1329	* @{
Kojto	115:87f2f5183dfb	1330	*/
Kojto	115:87f2f5183dfb	1331	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	1332	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1333	/**
Kojto	115:87f2f5183dfb	1334	* @}
Kojto	115:87f2f5183dfb	1335	*/
Kojto	115:87f2f5183dfb	1336
Kojto	115:87f2f5183dfb	1337	/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
Kojto	115:87f2f5183dfb	1338	* @{
Kojto	115:87f2f5183dfb	1339	*/
Kojto	115:87f2f5183dfb	1340	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Receive FIFO is 64 Bytes /
Kojto	115:87f2f5183dfb	1341	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /!< threshold level of the MTL Receive FIFO is 32 Bytes /
Kojto	115:87f2f5183dfb	1342	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /!< threshold level of the MTL Receive FIFO is 96 Bytes /
Kojto	115:87f2f5183dfb	1343	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /!< threshold level of the MTL Receive FIFO is 128 Bytes /
Kojto	115:87f2f5183dfb	1344	/**
Kojto	115:87f2f5183dfb	1345	* @}
Kojto	115:87f2f5183dfb	1346	*/
Kojto	115:87f2f5183dfb	1347
Kojto	115:87f2f5183dfb	1348	/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
Kojto	115:87f2f5183dfb	1349	* @{
Kojto	115:87f2f5183dfb	1350	*/
Kojto	115:87f2f5183dfb	1351	#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	1352	#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1353	/**
Kojto	115:87f2f5183dfb	1354	* @}
Kojto	115:87f2f5183dfb	1355	*/
Kojto	115:87f2f5183dfb	1356
Kojto	115:87f2f5183dfb	1357	/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
Kojto	115:87f2f5183dfb	1358	* @{
Kojto	115:87f2f5183dfb	1359	*/
Kojto	115:87f2f5183dfb	1360	#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	1361	#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1362	/**
Kojto	115:87f2f5183dfb	1363	* @}
Kojto	115:87f2f5183dfb	1364	*/
Kojto	115:87f2f5183dfb	1365
Kojto	115:87f2f5183dfb	1366	/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
Kojto	115:87f2f5183dfb	1367	* @{
Kojto	115:87f2f5183dfb	1368	*/
Kojto	115:87f2f5183dfb	1369	#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	1370	#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1371	/**
Kojto	115:87f2f5183dfb	1372	* @}
Kojto	115:87f2f5183dfb	1373	*/
Kojto	115:87f2f5183dfb	1374
Kojto	115:87f2f5183dfb	1375	/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
Kojto	115:87f2f5183dfb	1376	* @{
Kojto	115:87f2f5183dfb	1377	*/
Kojto	115:87f2f5183dfb	1378	#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
Kojto	115:87f2f5183dfb	1379	#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
Kojto	115:87f2f5183dfb	1380	#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
Kojto	115:87f2f5183dfb	1381	#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
Kojto	115:87f2f5183dfb	1382	#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
Kojto	115:87f2f5183dfb	1383	#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
Kojto	115:87f2f5183dfb	1384	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
Kojto	115:87f2f5183dfb	1385	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
Kojto	115:87f2f5183dfb	1386	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
Kojto	115:87f2f5183dfb	1387	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
Kojto	115:87f2f5183dfb	1388	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
Kojto	115:87f2f5183dfb	1389	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
Kojto	115:87f2f5183dfb	1390	/**
Kojto	115:87f2f5183dfb	1391	* @}
Kojto	115:87f2f5183dfb	1392	*/
Kojto	115:87f2f5183dfb	1393
Kojto	115:87f2f5183dfb	1394	/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
Kojto	115:87f2f5183dfb	1395	* @{
Kojto	115:87f2f5183dfb	1396	*/
Kojto	115:87f2f5183dfb	1397	#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
Kojto	115:87f2f5183dfb	1398	#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
Kojto	115:87f2f5183dfb	1399	#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
Kojto	115:87f2f5183dfb	1400	#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
Kojto	115:87f2f5183dfb	1401	#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
Kojto	115:87f2f5183dfb	1402	#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
Kojto	115:87f2f5183dfb	1403	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
Kojto	115:87f2f5183dfb	1404	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
Kojto	115:87f2f5183dfb	1405	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
Kojto	115:87f2f5183dfb	1406	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
Kojto	115:87f2f5183dfb	1407	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
Kojto	115:87f2f5183dfb	1408	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
Kojto	115:87f2f5183dfb	1409	/**
Kojto	115:87f2f5183dfb	1410	* @}
Kojto	115:87f2f5183dfb	1411	*/
Kojto	115:87f2f5183dfb	1412
Kojto	115:87f2f5183dfb	1413	/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
Kojto	115:87f2f5183dfb	1414	* @{
Kojto	115:87f2f5183dfb	1415	*/
Kojto	115:87f2f5183dfb	1416	#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	1417	#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1418	/**
Kojto	115:87f2f5183dfb	1419	* @}
Kojto	115:87f2f5183dfb	1420	*/
Kojto	115:87f2f5183dfb	1421
Kojto	115:87f2f5183dfb	1422	/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
Kojto	115:87f2f5183dfb	1423	* @{
Kojto	115:87f2f5183dfb	1424	*/
Kojto	115:87f2f5183dfb	1425	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	1426	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	1427	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	1428	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
Kojto	115:87f2f5183dfb	1429	#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	1430	/**
Kojto	115:87f2f5183dfb	1431	* @}
Kojto	115:87f2f5183dfb	1432	*/
Kojto	115:87f2f5183dfb	1433
Kojto	115:87f2f5183dfb	1434	/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
Kojto	115:87f2f5183dfb	1435	* @{
Kojto	115:87f2f5183dfb	1436	*/
Kojto	115:87f2f5183dfb	1437	#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /!< Last Segment /
Kojto	115:87f2f5183dfb	1438	#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /!< First Segment /
Kojto	115:87f2f5183dfb	1439	/**
Kojto	115:87f2f5183dfb	1440	* @}
Kojto	115:87f2f5183dfb	1441	*/
Kojto	115:87f2f5183dfb	1442
Kojto	115:87f2f5183dfb	1443	/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
Kojto	115:87f2f5183dfb	1444	* @{
Kojto	115:87f2f5183dfb	1445	*/
Kojto	115:87f2f5183dfb	1446	#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /!< Checksum engine bypass /
Kojto	115:87f2f5183dfb	1447	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /!< IPv4 header checksum insertion /
Kojto	115:87f2f5183dfb	1448	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
Kojto	115:87f2f5183dfb	1449	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
Kojto	115:87f2f5183dfb	1450	/**
Kojto	115:87f2f5183dfb	1451	* @}
Kojto	115:87f2f5183dfb	1452	*/
Kojto	115:87f2f5183dfb	1453
Kojto	115:87f2f5183dfb	1454	/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
Kojto	115:87f2f5183dfb	1455	* @{
Kojto	115:87f2f5183dfb	1456	*/
Kojto	115:87f2f5183dfb	1457	#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /!< DMA Rx Desc Buffer1 /
Kojto	115:87f2f5183dfb	1458	#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /!< DMA Rx Desc Buffer2 /
Kojto	115:87f2f5183dfb	1459	/**
Kojto	115:87f2f5183dfb	1460	* @}
Kojto	115:87f2f5183dfb	1461	*/
Kojto	115:87f2f5183dfb	1462
Kojto	115:87f2f5183dfb	1463	/** @defgroup ETH_PMT_Flags ETH PMT Flags
Kojto	115:87f2f5183dfb	1464	* @{
Kojto	115:87f2f5183dfb	1465	*/
Kojto	115:87f2f5183dfb	1466	#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /!< Wake-Up Frame Filter Register Pointer Reset /
Kojto	115:87f2f5183dfb	1467	#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /!< Wake-Up Frame Received /
Kojto	115:87f2f5183dfb	1468	#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /!< Magic Packet Received /
Kojto	115:87f2f5183dfb	1469	/**
Kojto	115:87f2f5183dfb	1470	* @}
Kojto	115:87f2f5183dfb	1471	*/
Kojto	115:87f2f5183dfb	1472
Kojto	115:87f2f5183dfb	1473	/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
Kojto	115:87f2f5183dfb	1474	* @{
Kojto	115:87f2f5183dfb	1475	*/
Kojto	115:87f2f5183dfb	1476	#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /!< When Tx good frame counter reaches half the maximum value /
Kojto	115:87f2f5183dfb	1477	#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /!< When Tx good multi col counter reaches half the maximum value /
Kojto	115:87f2f5183dfb	1478	#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /!< When Tx good single col counter reaches half the maximum value /
Kojto	115:87f2f5183dfb	1479	/**
Kojto	115:87f2f5183dfb	1480	* @}
Kojto	115:87f2f5183dfb	1481	*/
Kojto	115:87f2f5183dfb	1482
Kojto	115:87f2f5183dfb	1483	/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
Kojto	115:87f2f5183dfb	1484	* @{
Kojto	115:87f2f5183dfb	1485	*/
Kojto	115:87f2f5183dfb	1486	#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /!< When Rx good unicast frames counter reaches half the maximum value /
Kojto	115:87f2f5183dfb	1487	#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /!< When Rx alignment error counter reaches half the maximum value /
Kojto	115:87f2f5183dfb	1488	#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /!< When Rx crc error counter reaches half the maximum value /
Kojto	115:87f2f5183dfb	1489	/**
Kojto	115:87f2f5183dfb	1490	* @}
Kojto	115:87f2f5183dfb	1491	*/
Kojto	115:87f2f5183dfb	1492
Kojto	115:87f2f5183dfb	1493	/** @defgroup ETH_MAC_Flags ETH MAC Flags
Kojto	115:87f2f5183dfb	1494	* @{
Kojto	115:87f2f5183dfb	1495	*/
Kojto	115:87f2f5183dfb	1496	#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /!< Time stamp trigger flag (on MAC) /
Kojto	115:87f2f5183dfb	1497	#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /!< MMC transmit flag /
Kojto	115:87f2f5183dfb	1498	#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /!< MMC receive flag /
Kojto	115:87f2f5183dfb	1499	#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /!< MMC flag (on MAC) /
Kojto	115:87f2f5183dfb	1500	#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /!< PMT flag (on MAC) /
Kojto	115:87f2f5183dfb	1501	/**
Kojto	115:87f2f5183dfb	1502	* @}
Kojto	115:87f2f5183dfb	1503	*/
Kojto	115:87f2f5183dfb	1504
Kojto	115:87f2f5183dfb	1505	/** @defgroup ETH_DMA_Flags ETH DMA Flags
Kojto	115:87f2f5183dfb	1506	* @{
Kojto	115:87f2f5183dfb	1507	*/
Kojto	115:87f2f5183dfb	1508	#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
Kojto	115:87f2f5183dfb	1509	#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
Kojto	115:87f2f5183dfb	1510	#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
Kojto	115:87f2f5183dfb	1511	#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /!< Error bits 0-Rx DMA, 1-Tx DMA /
Kojto	115:87f2f5183dfb	1512	#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /!< Error bits 0-write transfer, 1-read transfer /
Kojto	115:87f2f5183dfb	1513	#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /!< Error bits 0-data buffer, 1-desc. access /
Kojto	115:87f2f5183dfb	1514	#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary flag /
Kojto	115:87f2f5183dfb	1515	#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary flag /
Kojto	115:87f2f5183dfb	1516	#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /!< Early receive flag /
Kojto	115:87f2f5183dfb	1517	#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /!< Fatal bus error flag /
Kojto	115:87f2f5183dfb	1518	#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /!< Early transmit flag /
Kojto	115:87f2f5183dfb	1519	#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout flag /
Kojto	115:87f2f5183dfb	1520	#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /!< Receive process stopped flag /
Kojto	115:87f2f5183dfb	1521	#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable flag /
Kojto	115:87f2f5183dfb	1522	#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /!< Receive flag /
Kojto	115:87f2f5183dfb	1523	#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /!< Underflow flag /
Kojto	115:87f2f5183dfb	1524	#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /!< Overflow flag /
Kojto	115:87f2f5183dfb	1525	#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout flag /
Kojto	115:87f2f5183dfb	1526	#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable flag /
Kojto	115:87f2f5183dfb	1527	#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /!< Transmit process stopped flag /
Kojto	115:87f2f5183dfb	1528	#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /!< Transmit flag /
Kojto	115:87f2f5183dfb	1529	/**
Kojto	115:87f2f5183dfb	1530	* @}
Kojto	115:87f2f5183dfb	1531	*/
Kojto	115:87f2f5183dfb	1532
Kojto	115:87f2f5183dfb	1533	/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
Kojto	115:87f2f5183dfb	1534	* @{
Kojto	115:87f2f5183dfb	1535	*/
Kojto	115:87f2f5183dfb	1536	#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /!< Time stamp trigger interrupt (on MAC) /
Kojto	115:87f2f5183dfb	1537	#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /!< MMC transmit interrupt /
Kojto	115:87f2f5183dfb	1538	#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /!< MMC receive interrupt /
Kojto	115:87f2f5183dfb	1539	#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /!< MMC interrupt (on MAC) /
Kojto	115:87f2f5183dfb	1540	#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /!< PMT interrupt (on MAC) /
Kojto	115:87f2f5183dfb	1541	/**
Kojto	115:87f2f5183dfb	1542	* @}
Kojto	115:87f2f5183dfb	1543	*/
Kojto	115:87f2f5183dfb	1544
Kojto	115:87f2f5183dfb	1545	/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
Kojto	115:87f2f5183dfb	1546	* @{
Kojto	115:87f2f5183dfb	1547	*/
Kojto	115:87f2f5183dfb	1548	#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
Kojto	115:87f2f5183dfb	1549	#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
Kojto	115:87f2f5183dfb	1550	#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
Kojto	115:87f2f5183dfb	1551	#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary /
Kojto	115:87f2f5183dfb	1552	#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary /
Kojto	115:87f2f5183dfb	1553	#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /!< Early receive interrupt /
Kojto	115:87f2f5183dfb	1554	#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /!< Fatal bus error interrupt /
Kojto	115:87f2f5183dfb	1555	#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /!< Early transmit interrupt /
Kojto	115:87f2f5183dfb	1556	#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout interrupt /
Kojto	115:87f2f5183dfb	1557	#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /!< Receive process stopped interrupt /
Kojto	115:87f2f5183dfb	1558	#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable interrupt /
Kojto	115:87f2f5183dfb	1559	#define ETH_DMA_IT_R ((uint32_t)0x00000040) /!< Receive interrupt /
Kojto	115:87f2f5183dfb	1560	#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /!< Underflow interrupt /
Kojto	115:87f2f5183dfb	1561	#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /!< Overflow interrupt /
Kojto	115:87f2f5183dfb	1562	#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout interrupt /
Kojto	115:87f2f5183dfb	1563	#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable interrupt /
Kojto	115:87f2f5183dfb	1564	#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /!< Transmit process stopped interrupt /
Kojto	115:87f2f5183dfb	1565	#define ETH_DMA_IT_T ((uint32_t)0x00000001) /!< Transmit interrupt /
Kojto	115:87f2f5183dfb	1566	/**
Kojto	115:87f2f5183dfb	1567	* @}
Kojto	115:87f2f5183dfb	1568	*/
Kojto	115:87f2f5183dfb	1569
Kojto	115:87f2f5183dfb	1570	/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
Kojto	115:87f2f5183dfb	1571	* @{
Kojto	115:87f2f5183dfb	1572	*/
Kojto	115:87f2f5183dfb	1573	#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Tx Command issued /
Kojto	115:87f2f5183dfb	1574	#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /!< Running - fetching the Tx descriptor /
Kojto	115:87f2f5183dfb	1575	#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /!< Running - waiting for status /
Kojto	115:87f2f5183dfb	1576	#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /!< Running - reading the data from host memory /
Kojto	115:87f2f5183dfb	1577	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /!< Suspended - Tx Descriptor unavailable /
Kojto	115:87f2f5183dfb	1578	#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /!< Running - closing Rx descriptor /
Kojto	115:87f2f5183dfb	1579
Kojto	115:87f2f5183dfb	1580	/**
Kojto	115:87f2f5183dfb	1581	* @}
Kojto	115:87f2f5183dfb	1582	*/
Kojto	115:87f2f5183dfb	1583
Kojto	115:87f2f5183dfb	1584
Kojto	115:87f2f5183dfb	1585	/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
Kojto	115:87f2f5183dfb	1586	* @{
Kojto	115:87f2f5183dfb	1587	*/
Kojto	115:87f2f5183dfb	1588	#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Rx Command issued /
Kojto	115:87f2f5183dfb	1589	#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /!< Running - fetching the Rx descriptor /
Kojto	115:87f2f5183dfb	1590	#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /!< Running - waiting for packet /
Kojto	115:87f2f5183dfb	1591	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /!< Suspended - Rx Descriptor unavailable /
Kojto	115:87f2f5183dfb	1592	#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /!< Running - closing descriptor /
Kojto	115:87f2f5183dfb	1593	#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /!< Running - queuing the receive frame into host memory /
Kojto	115:87f2f5183dfb	1594
Kojto	115:87f2f5183dfb	1595	/**
Kojto	115:87f2f5183dfb	1596	* @}
Kojto	115:87f2f5183dfb	1597	*/
Kojto	115:87f2f5183dfb	1598
Kojto	115:87f2f5183dfb	1599	/** @defgroup ETH_DMA_overflow ETH DMA overflow
Kojto	115:87f2f5183dfb	1600	* @{
Kojto	115:87f2f5183dfb	1601	*/
Kojto	115:87f2f5183dfb	1602	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /!< Overflow bit for FIFO overflow counter /
Kojto	115:87f2f5183dfb	1603	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /!< Overflow bit for missed frame counter /
Kojto	115:87f2f5183dfb	1604	/**
Kojto	115:87f2f5183dfb	1605	* @}
Kojto	115:87f2f5183dfb	1606	*/
Kojto	115:87f2f5183dfb	1607
Kojto	115:87f2f5183dfb	1608	/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
Kojto	115:87f2f5183dfb	1609	* @{
Kojto	115:87f2f5183dfb	1610	*/
Kojto	115:87f2f5183dfb	1611	#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /!< External interrupt line 19 Connected to the ETH EXTI Line /
Kojto	115:87f2f5183dfb	1612
Kojto	115:87f2f5183dfb	1613	/**
Kojto	115:87f2f5183dfb	1614	* @}
Kojto	115:87f2f5183dfb	1615	*/
Kojto	115:87f2f5183dfb	1616
Kojto	115:87f2f5183dfb	1617	/**
Kojto	115:87f2f5183dfb	1618	* @}
Kojto	115:87f2f5183dfb	1619	*/
Kojto	115:87f2f5183dfb	1620
Kojto	115:87f2f5183dfb	1621	/* Exported macro ------------------------------------------------------------*/
Kojto	115:87f2f5183dfb	1622	/** @defgroup ETH_Exported_Macros ETH Exported Macros
Kojto	115:87f2f5183dfb	1623	* @brief macros to handle interrupts and specific clock configurations
Kojto	115:87f2f5183dfb	1624	* @{
Kojto	115:87f2f5183dfb	1625	*/
Kojto	115:87f2f5183dfb	1626
Kojto	115:87f2f5183dfb	1627	/** @brief Reset ETH handle state
Kojto	115:87f2f5183dfb	1628	* @param __HANDLE__: specifies the ETH handle.
Kojto	115:87f2f5183dfb	1629	* @retval None
Kojto	115:87f2f5183dfb	1630	*/
Kojto	115:87f2f5183dfb	1631	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
Kojto	115:87f2f5183dfb	1632
Kojto	115:87f2f5183dfb	1633	/**
Kojto	115:87f2f5183dfb	1634	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
Kojto	115:87f2f5183dfb	1635	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1636	* @param __FLAG__: specifies the flag of TDES0 to check.
Kojto	115:87f2f5183dfb	1637	* @retval the ETH_DMATxDescFlag (SET or RESET).
Kojto	115:87f2f5183dfb	1638	*/
Kojto	115:87f2f5183dfb	1639	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
Kojto	115:87f2f5183dfb	1640
Kojto	115:87f2f5183dfb	1641	/**
Kojto	115:87f2f5183dfb	1642	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
Kojto	115:87f2f5183dfb	1643	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1644	* @param __FLAG__: specifies the flag of RDES0 to check.
Kojto	115:87f2f5183dfb	1645	* @retval the ETH_DMATxDescFlag (SET or RESET).
Kojto	115:87f2f5183dfb	1646	*/
Kojto	115:87f2f5183dfb	1647	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
Kojto	115:87f2f5183dfb	1648
Kojto	115:87f2f5183dfb	1649	/**
Kojto	115:87f2f5183dfb	1650	* @brief Enables the specified DMA Rx Desc receive interrupt.
Kojto	115:87f2f5183dfb	1651	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1652	* @retval None
Kojto	115:87f2f5183dfb	1653	*/
Kojto	115:87f2f5183dfb	1654	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
Kojto	115:87f2f5183dfb	1655
Kojto	115:87f2f5183dfb	1656	/**
Kojto	115:87f2f5183dfb	1657	* @brief Disables the specified DMA Rx Desc receive interrupt.
Kojto	115:87f2f5183dfb	1658	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1659	* @retval None
Kojto	115:87f2f5183dfb	1660	*/
Kojto	115:87f2f5183dfb	1661	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
Kojto	115:87f2f5183dfb	1662
Kojto	115:87f2f5183dfb	1663	/**
Kojto	115:87f2f5183dfb	1664	* @brief Set the specified DMA Rx Desc Own bit.
Kojto	115:87f2f5183dfb	1665	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1666	* @retval None
Kojto	115:87f2f5183dfb	1667	*/
Kojto	115:87f2f5183dfb	1668	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
Kojto	115:87f2f5183dfb	1669
Kojto	115:87f2f5183dfb	1670	/**
Kojto	115:87f2f5183dfb	1671	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
Kojto	115:87f2f5183dfb	1672	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1673	* @retval The Transmit descriptor collision counter value.
Kojto	115:87f2f5183dfb	1674	*/
Kojto	115:87f2f5183dfb	1675	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
Kojto	115:87f2f5183dfb	1676
Kojto	115:87f2f5183dfb	1677	/**
Kojto	115:87f2f5183dfb	1678	* @brief Set the specified DMA Tx Desc Own bit.
Kojto	115:87f2f5183dfb	1679	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1680	* @retval None
Kojto	115:87f2f5183dfb	1681	*/
Kojto	115:87f2f5183dfb	1682	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
Kojto	115:87f2f5183dfb	1683
Kojto	115:87f2f5183dfb	1684	/**
Kojto	115:87f2f5183dfb	1685	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
Kojto	115:87f2f5183dfb	1686	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1687	* @retval None
Kojto	115:87f2f5183dfb	1688	*/
Kojto	115:87f2f5183dfb	1689	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
Kojto	115:87f2f5183dfb	1690
Kojto	115:87f2f5183dfb	1691	/**
Kojto	115:87f2f5183dfb	1692	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
Kojto	115:87f2f5183dfb	1693	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1694	* @retval None
Kojto	115:87f2f5183dfb	1695	*/
Kojto	115:87f2f5183dfb	1696	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
Kojto	115:87f2f5183dfb	1697
Kojto	115:87f2f5183dfb	1698	/**
Kojto	115:87f2f5183dfb	1699	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
Kojto	115:87f2f5183dfb	1700	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1701	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
Kojto	115:87f2f5183dfb	1702	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	1703	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
Kojto	115:87f2f5183dfb	1704	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
Kojto	115:87f2f5183dfb	1705	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
Kojto	115:87f2f5183dfb	1706	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
Kojto	115:87f2f5183dfb	1707	* @retval None
Kojto	115:87f2f5183dfb	1708	*/
Kojto	115:87f2f5183dfb	1709	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
Kojto	115:87f2f5183dfb	1710
Kojto	115:87f2f5183dfb	1711	/**
Kojto	115:87f2f5183dfb	1712	* @brief Enables the DMA Tx Desc CRC.
Kojto	115:87f2f5183dfb	1713	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1714	* @retval None
Kojto	115:87f2f5183dfb	1715	*/
Kojto	115:87f2f5183dfb	1716	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
Kojto	115:87f2f5183dfb	1717
Kojto	115:87f2f5183dfb	1718	/**
Kojto	115:87f2f5183dfb	1719	* @brief Disables the DMA Tx Desc CRC.
Kojto	115:87f2f5183dfb	1720	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1721	* @retval None
Kojto	115:87f2f5183dfb	1722	*/
Kojto	115:87f2f5183dfb	1723	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
Kojto	115:87f2f5183dfb	1724
Kojto	115:87f2f5183dfb	1725	/**
Kojto	115:87f2f5183dfb	1726	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
Kojto	115:87f2f5183dfb	1727	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1728	* @retval None
Kojto	115:87f2f5183dfb	1729	*/
Kojto	115:87f2f5183dfb	1730	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
Kojto	115:87f2f5183dfb	1731
Kojto	115:87f2f5183dfb	1732	/**
Kojto	115:87f2f5183dfb	1733	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
Kojto	115:87f2f5183dfb	1734	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1735	* @retval None
Kojto	115:87f2f5183dfb	1736	*/
Kojto	115:87f2f5183dfb	1737	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
Kojto	115:87f2f5183dfb	1738
Kojto	115:87f2f5183dfb	1739	/**
Kojto	115:87f2f5183dfb	1740	* @brief Enables the specified ETHERNET MAC interrupts.
Kojto	115:87f2f5183dfb	1741	* @param __HANDLE__ : ETH Handle
Kojto	115:87f2f5183dfb	1742	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
Kojto	115:87f2f5183dfb	1743	* enabled or disabled.
Kojto	115:87f2f5183dfb	1744	* This parameter can be any combination of the following values:
Kojto	115:87f2f5183dfb	1745	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
Kojto	115:87f2f5183dfb	1746	* @arg ETH_MAC_IT_PMT : PMT interrupt
Kojto	115:87f2f5183dfb	1747	* @retval None
Kojto	115:87f2f5183dfb	1748	*/
Kojto	115:87f2f5183dfb	1749	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
Kojto	115:87f2f5183dfb	1750
Kojto	115:87f2f5183dfb	1751	/**
Kojto	115:87f2f5183dfb	1752	* @brief Disables the specified ETHERNET MAC interrupts.
Kojto	115:87f2f5183dfb	1753	* @param __HANDLE__ : ETH Handle
Kojto	115:87f2f5183dfb	1754	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
Kojto	115:87f2f5183dfb	1755	* enabled or disabled.
Kojto	115:87f2f5183dfb	1756	* This parameter can be any combination of the following values:
Kojto	115:87f2f5183dfb	1757	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
Kojto	115:87f2f5183dfb	1758	* @arg ETH_MAC_IT_PMT : PMT interrupt
Kojto	115:87f2f5183dfb	1759	* @retval None
Kojto	115:87f2f5183dfb	1760	*/
Kojto	115:87f2f5183dfb	1761	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
Kojto	115:87f2f5183dfb	1762
Kojto	115:87f2f5183dfb	1763	/**
Kojto	115:87f2f5183dfb	1764	* @brief Initiate a Pause Control Frame (Full-duplex only).
Kojto	115:87f2f5183dfb	1765	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1766	* @retval None
Kojto	115:87f2f5183dfb	1767	*/
Kojto	115:87f2f5183dfb	1768	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
Kojto	115:87f2f5183dfb	1769
Kojto	115:87f2f5183dfb	1770	/**
Kojto	115:87f2f5183dfb	1771	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
Kojto	115:87f2f5183dfb	1772	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1773	* @retval The new state of flow control busy status bit (SET or RESET).
Kojto	115:87f2f5183dfb	1774	*/
Kojto	115:87f2f5183dfb	1775	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
Kojto	115:87f2f5183dfb	1776
Kojto	115:87f2f5183dfb	1777	/**
Kojto	115:87f2f5183dfb	1778	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
Kojto	115:87f2f5183dfb	1779	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1780	* @retval None
Kojto	115:87f2f5183dfb	1781	*/
Kojto	115:87f2f5183dfb	1782	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
Kojto	115:87f2f5183dfb	1783
Kojto	115:87f2f5183dfb	1784	/**
Kojto	115:87f2f5183dfb	1785	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
Kojto	115:87f2f5183dfb	1786	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1787	* @retval None
Kojto	115:87f2f5183dfb	1788	*/
Kojto	115:87f2f5183dfb	1789	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
Kojto	115:87f2f5183dfb	1790
Kojto	115:87f2f5183dfb	1791	/**
Kojto	115:87f2f5183dfb	1792	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
Kojto	115:87f2f5183dfb	1793	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1794	* @param __FLAG__: specifies the flag to check.
Kojto	115:87f2f5183dfb	1795	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	1796	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
Kojto	115:87f2f5183dfb	1797	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
Kojto	115:87f2f5183dfb	1798	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
Kojto	115:87f2f5183dfb	1799	* @arg ETH_MAC_FLAG_MMC : MMC flag
Kojto	115:87f2f5183dfb	1800	* @arg ETH_MAC_FLAG_PMT : PMT flag
Kojto	115:87f2f5183dfb	1801	* @retval The state of ETHERNET MAC flag.
Kojto	115:87f2f5183dfb	1802	*/
Kojto	115:87f2f5183dfb	1803	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
Kojto	115:87f2f5183dfb	1804
Kojto	115:87f2f5183dfb	1805	/**
Kojto	115:87f2f5183dfb	1806	* @brief Enables the specified ETHERNET DMA interrupts.
Kojto	115:87f2f5183dfb	1807	* @param __HANDLE__ : ETH Handle
Kojto	115:87f2f5183dfb	1808	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto	115:87f2f5183dfb	1809	* enabled @ref ETH_DMA_Interrupts
Kojto	115:87f2f5183dfb	1810	* @retval None
Kojto	115:87f2f5183dfb	1811	*/
Kojto	115:87f2f5183dfb	1812	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
Kojto	115:87f2f5183dfb	1813
Kojto	115:87f2f5183dfb	1814	/**
Kojto	115:87f2f5183dfb	1815	* @brief Disables the specified ETHERNET DMA interrupts.
Kojto	115:87f2f5183dfb	1816	* @param __HANDLE__ : ETH Handle
Kojto	115:87f2f5183dfb	1817	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto	115:87f2f5183dfb	1818	* disabled. @ref ETH_DMA_Interrupts
Kojto	115:87f2f5183dfb	1819	* @retval None
Kojto	115:87f2f5183dfb	1820	*/
Kojto	115:87f2f5183dfb	1821	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
Kojto	115:87f2f5183dfb	1822
Kojto	115:87f2f5183dfb	1823	/**
Kojto	115:87f2f5183dfb	1824	* @brief Clears the ETHERNET DMA IT pending bit.
Kojto	115:87f2f5183dfb	1825	* @param __HANDLE__ : ETH Handle
Kojto	115:87f2f5183dfb	1826	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
Kojto	115:87f2f5183dfb	1827	* @retval None
Kojto	115:87f2f5183dfb	1828	*/
Kojto	115:87f2f5183dfb	1829	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
Kojto	115:87f2f5183dfb	1830
Kojto	115:87f2f5183dfb	1831	/**
Kojto	115:87f2f5183dfb	1832	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
Kojto	115:87f2f5183dfb	1833	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1834	* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
Kojto	115:87f2f5183dfb	1835	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
Kojto	115:87f2f5183dfb	1836	*/
Kojto	115:87f2f5183dfb	1837	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
Kojto	115:87f2f5183dfb	1838
Kojto	115:87f2f5183dfb	1839	/**
Kojto	115:87f2f5183dfb	1840	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
Kojto	115:87f2f5183dfb	1841	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1842	* @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
Kojto	115:87f2f5183dfb	1843	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
Kojto	115:87f2f5183dfb	1844	*/
Kojto	115:87f2f5183dfb	1845	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
Kojto	115:87f2f5183dfb	1846
Kojto	115:87f2f5183dfb	1847	/**
Kojto	115:87f2f5183dfb	1848	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
Kojto	115:87f2f5183dfb	1849	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1850	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
Kojto	115:87f2f5183dfb	1851	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	1852	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
Kojto	115:87f2f5183dfb	1853	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
Kojto	115:87f2f5183dfb	1854	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
Kojto	115:87f2f5183dfb	1855	*/
Kojto	115:87f2f5183dfb	1856	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
Kojto	115:87f2f5183dfb	1857
Kojto	115:87f2f5183dfb	1858	/**
Kojto	115:87f2f5183dfb	1859	* @brief Set the DMA Receive status watchdog timer register value
Kojto	115:87f2f5183dfb	1860	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1861	* @param __VALUE__: DMA Receive status watchdog timer register value
Kojto	115:87f2f5183dfb	1862	* @retval None
Kojto	115:87f2f5183dfb	1863	*/
Kojto	115:87f2f5183dfb	1864	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
Kojto	115:87f2f5183dfb	1865
Kojto	115:87f2f5183dfb	1866	/**
Kojto	115:87f2f5183dfb	1867	* @brief Enables any unicast packet filtered by the MAC address
Kojto	115:87f2f5183dfb	1868	* recognition to be a wake-up frame.
Kojto	115:87f2f5183dfb	1869	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1870	* @retval None
Kojto	115:87f2f5183dfb	1871	*/
Kojto	115:87f2f5183dfb	1872	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
Kojto	115:87f2f5183dfb	1873
Kojto	115:87f2f5183dfb	1874	/**
Kojto	115:87f2f5183dfb	1875	* @brief Disables any unicast packet filtered by the MAC address
Kojto	115:87f2f5183dfb	1876	* recognition to be a wake-up frame.
Kojto	115:87f2f5183dfb	1877	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1878	* @retval None
Kojto	115:87f2f5183dfb	1879	*/
Kojto	115:87f2f5183dfb	1880	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
Kojto	115:87f2f5183dfb	1881
Kojto	115:87f2f5183dfb	1882	/**
Kojto	115:87f2f5183dfb	1883	* @brief Enables the MAC Wake-Up Frame Detection.
Kojto	115:87f2f5183dfb	1884	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1885	* @retval None
Kojto	115:87f2f5183dfb	1886	*/
Kojto	115:87f2f5183dfb	1887	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
Kojto	115:87f2f5183dfb	1888
Kojto	115:87f2f5183dfb	1889	/**
Kojto	115:87f2f5183dfb	1890	* @brief Disables the MAC Wake-Up Frame Detection.
Kojto	115:87f2f5183dfb	1891	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1892	* @retval None
Kojto	115:87f2f5183dfb	1893	*/
Kojto	115:87f2f5183dfb	1894	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Kojto	115:87f2f5183dfb	1895
Kojto	115:87f2f5183dfb	1896	/**
Kojto	115:87f2f5183dfb	1897	* @brief Enables the MAC Magic Packet Detection.
Kojto	115:87f2f5183dfb	1898	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1899	* @retval None
Kojto	115:87f2f5183dfb	1900	*/
Kojto	115:87f2f5183dfb	1901	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
Kojto	115:87f2f5183dfb	1902
Kojto	115:87f2f5183dfb	1903	/**
Kojto	115:87f2f5183dfb	1904	* @brief Disables the MAC Magic Packet Detection.
Kojto	115:87f2f5183dfb	1905	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1906	* @retval None
Kojto	115:87f2f5183dfb	1907	*/
Kojto	115:87f2f5183dfb	1908	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Kojto	115:87f2f5183dfb	1909
Kojto	115:87f2f5183dfb	1910	/**
Kojto	115:87f2f5183dfb	1911	* @brief Enables the MAC Power Down.
Kojto	115:87f2f5183dfb	1912	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1913	* @retval None
Kojto	115:87f2f5183dfb	1914	*/
Kojto	115:87f2f5183dfb	1915	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
Kojto	115:87f2f5183dfb	1916
Kojto	115:87f2f5183dfb	1917	/**
Kojto	115:87f2f5183dfb	1918	* @brief Disables the MAC Power Down.
Kojto	115:87f2f5183dfb	1919	* @param __HANDLE__: ETH Handle
Kojto	115:87f2f5183dfb	1920	* @retval None
Kojto	115:87f2f5183dfb	1921	*/
Kojto	115:87f2f5183dfb	1922	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
Kojto	115:87f2f5183dfb	1923
Kojto	115:87f2f5183dfb	1924	/**
Kojto	115:87f2f5183dfb	1925	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
Kojto	115:87f2f5183dfb	1926	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1927	* @param __FLAG__: specifies the flag to check.
Kojto	115:87f2f5183dfb	1928	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	1929	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
Kojto	115:87f2f5183dfb	1930	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
Kojto	115:87f2f5183dfb	1931	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
Kojto	115:87f2f5183dfb	1932	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
Kojto	115:87f2f5183dfb	1933	*/
Kojto	115:87f2f5183dfb	1934	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
Kojto	115:87f2f5183dfb	1935
Kojto	115:87f2f5183dfb	1936	/**
Kojto	115:87f2f5183dfb	1937	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
Kojto	115:87f2f5183dfb	1938	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1939	* @retval None
Kojto	115:87f2f5183dfb	1940	*/
Kojto	115:87f2f5183dfb	1941	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
Kojto	115:87f2f5183dfb	1942
Kojto	115:87f2f5183dfb	1943	/**
Kojto	115:87f2f5183dfb	1944	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
Kojto	115:87f2f5183dfb	1945	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1946	* @retval None
Kojto	115:87f2f5183dfb	1947	*/
Kojto	115:87f2f5183dfb	1948	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
Kojto	115:87f2f5183dfb	1949	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
Kojto	115:87f2f5183dfb	1950
Kojto	115:87f2f5183dfb	1951	/**
Kojto	115:87f2f5183dfb	1952	* @brief Enables the MMC Counter Freeze.
Kojto	115:87f2f5183dfb	1953	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1954	* @retval None
Kojto	115:87f2f5183dfb	1955	*/
Kojto	115:87f2f5183dfb	1956	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
Kojto	115:87f2f5183dfb	1957
Kojto	115:87f2f5183dfb	1958	/**
Kojto	115:87f2f5183dfb	1959	* @brief Disables the MMC Counter Freeze.
Kojto	115:87f2f5183dfb	1960	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1961	* @retval None
Kojto	115:87f2f5183dfb	1962	*/
Kojto	115:87f2f5183dfb	1963	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
Kojto	115:87f2f5183dfb	1964
Kojto	115:87f2f5183dfb	1965	/**
Kojto	115:87f2f5183dfb	1966	* @brief Enables the MMC Reset On Read.
Kojto	115:87f2f5183dfb	1967	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1968	* @retval None
Kojto	115:87f2f5183dfb	1969	*/
Kojto	115:87f2f5183dfb	1970	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
Kojto	115:87f2f5183dfb	1971
Kojto	115:87f2f5183dfb	1972	/**
Kojto	115:87f2f5183dfb	1973	* @brief Disables the MMC Reset On Read.
Kojto	115:87f2f5183dfb	1974	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1975	* @retval None
Kojto	115:87f2f5183dfb	1976	*/
Kojto	115:87f2f5183dfb	1977	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
Kojto	115:87f2f5183dfb	1978
Kojto	115:87f2f5183dfb	1979	/**
Kojto	115:87f2f5183dfb	1980	* @brief Enables the MMC Counter Stop Rollover.
Kojto	115:87f2f5183dfb	1981	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1982	* @retval None
Kojto	115:87f2f5183dfb	1983	*/
Kojto	115:87f2f5183dfb	1984	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
Kojto	115:87f2f5183dfb	1985
Kojto	115:87f2f5183dfb	1986	/**
Kojto	115:87f2f5183dfb	1987	* @brief Disables the MMC Counter Stop Rollover.
Kojto	115:87f2f5183dfb	1988	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1989	* @retval None
Kojto	115:87f2f5183dfb	1990	*/
Kojto	115:87f2f5183dfb	1991	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
Kojto	115:87f2f5183dfb	1992
Kojto	115:87f2f5183dfb	1993	/**
Kojto	115:87f2f5183dfb	1994	* @brief Resets the MMC Counters.
Kojto	115:87f2f5183dfb	1995	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	1996	* @retval None
Kojto	115:87f2f5183dfb	1997	*/
Kojto	115:87f2f5183dfb	1998	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
Kojto	115:87f2f5183dfb	1999
Kojto	115:87f2f5183dfb	2000	/**
Kojto	115:87f2f5183dfb	2001	* @brief Enables the specified ETHERNET MMC Rx interrupts.
Kojto	115:87f2f5183dfb	2002	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	2003	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	115:87f2f5183dfb	2004	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2005	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
Kojto	115:87f2f5183dfb	2006	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
Kojto	115:87f2f5183dfb	2007	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
Kojto	115:87f2f5183dfb	2008	* @retval None
Kojto	115:87f2f5183dfb	2009	*/
Kojto	115:87f2f5183dfb	2010	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
Kojto	115:87f2f5183dfb	2011	/**
Kojto	115:87f2f5183dfb	2012	* @brief Disables the specified ETHERNET MMC Rx interrupts.
Kojto	115:87f2f5183dfb	2013	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	2014	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	115:87f2f5183dfb	2015	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2016	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
Kojto	115:87f2f5183dfb	2017	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
Kojto	115:87f2f5183dfb	2018	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
Kojto	115:87f2f5183dfb	2019	* @retval None
Kojto	115:87f2f5183dfb	2020	*/
Kojto	115:87f2f5183dfb	2021	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFF)
Kojto	115:87f2f5183dfb	2022	/**
Kojto	115:87f2f5183dfb	2023	* @brief Enables the specified ETHERNET MMC Tx interrupts.
Kojto	115:87f2f5183dfb	2024	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	2025	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	115:87f2f5183dfb	2026	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2027	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
Kojto	115:87f2f5183dfb	2028	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
Kojto	115:87f2f5183dfb	2029	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
Kojto	115:87f2f5183dfb	2030	* @retval None
Kojto	115:87f2f5183dfb	2031	*/
Kojto	115:87f2f5183dfb	2032	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
Kojto	115:87f2f5183dfb	2033
Kojto	115:87f2f5183dfb	2034	/**
Kojto	115:87f2f5183dfb	2035	* @brief Disables the specified ETHERNET MMC Tx interrupts.
Kojto	115:87f2f5183dfb	2036	* @param __HANDLE__: ETH Handle.
Kojto	115:87f2f5183dfb	2037	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	115:87f2f5183dfb	2038	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2039	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
Kojto	115:87f2f5183dfb	2040	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
Kojto	115:87f2f5183dfb	2041	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
Kojto	115:87f2f5183dfb	2042	* @retval None
Kojto	115:87f2f5183dfb	2043	*/
Kojto	115:87f2f5183dfb	2044	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
Kojto	115:87f2f5183dfb	2045
Kojto	115:87f2f5183dfb	2046	/**
Kojto	115:87f2f5183dfb	2047	* @brief Enables the ETH External interrupt line.
Kojto	115:87f2f5183dfb	2048	* @retval None
Kojto	115:87f2f5183dfb	2049	*/
Kojto	115:87f2f5183dfb	2050	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
Kojto	115:87f2f5183dfb	2051
Kojto	115:87f2f5183dfb	2052	/**
Kojto	115:87f2f5183dfb	2053	* @brief Disables the ETH External interrupt line.
Kojto	115:87f2f5183dfb	2054	* @retval None
Kojto	115:87f2f5183dfb	2055	*/
Kojto	115:87f2f5183dfb	2056	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	115:87f2f5183dfb	2057
Kojto	115:87f2f5183dfb	2058	/**
Kojto	115:87f2f5183dfb	2059	* @brief Enable event on ETH External event line.
Kojto	115:87f2f5183dfb	2060	* @retval None.
Kojto	115:87f2f5183dfb	2061	*/
Kojto	115:87f2f5183dfb	2062	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR \|= (ETH_EXTI_LINE_WAKEUP)
Kojto	115:87f2f5183dfb	2063
Kojto	115:87f2f5183dfb	2064	/**
Kojto	115:87f2f5183dfb	2065	* @brief Disable event on ETH External event line
Kojto	115:87f2f5183dfb	2066	* @retval None.
Kojto	115:87f2f5183dfb	2067	*/
Kojto	115:87f2f5183dfb	2068	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	115:87f2f5183dfb	2069
Kojto	115:87f2f5183dfb	2070	/**
Kojto	115:87f2f5183dfb	2071	* @brief Get flag of the ETH External interrupt line.
Kojto	115:87f2f5183dfb	2072	* @retval None
Kojto	115:87f2f5183dfb	2073	*/
Kojto	115:87f2f5183dfb	2074	#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
Kojto	115:87f2f5183dfb	2075
Kojto	115:87f2f5183dfb	2076	/**
Kojto	115:87f2f5183dfb	2077	* @brief Clear flag of the ETH External interrupt line.
Kojto	115:87f2f5183dfb	2078	* @retval None
Kojto	115:87f2f5183dfb	2079	*/
Kojto	115:87f2f5183dfb	2080	#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
Kojto	115:87f2f5183dfb	2081
Kojto	115:87f2f5183dfb	2082	/**
Kojto	115:87f2f5183dfb	2083	* @brief Enables rising edge trigger to the ETH External interrupt line.
Kojto	115:87f2f5183dfb	2084	* @retval None
Kojto	115:87f2f5183dfb	2085	*/
Kojto	115:87f2f5183dfb	2086	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
Kojto	115:87f2f5183dfb	2087
Kojto	115:87f2f5183dfb	2088	/**
Kojto	115:87f2f5183dfb	2089	* @brief Disables the rising edge trigger to the ETH External interrupt line.
Kojto	115:87f2f5183dfb	2090	* @retval None
Kojto	115:87f2f5183dfb	2091	*/
Kojto	115:87f2f5183dfb	2092	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	115:87f2f5183dfb	2093
Kojto	115:87f2f5183dfb	2094	/**
Kojto	115:87f2f5183dfb	2095	* @brief Enables falling edge trigger to the ETH External interrupt line.
Kojto	115:87f2f5183dfb	2096	* @retval None
Kojto	115:87f2f5183dfb	2097	*/
Kojto	115:87f2f5183dfb	2098	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP)
Kojto	115:87f2f5183dfb	2099
Kojto	115:87f2f5183dfb	2100	/**
Kojto	115:87f2f5183dfb	2101	* @brief Disables falling edge trigger to the ETH External interrupt line.
Kojto	115:87f2f5183dfb	2102	* @retval None
Kojto	115:87f2f5183dfb	2103	*/
Kojto	115:87f2f5183dfb	2104	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	115:87f2f5183dfb	2105
Kojto	115:87f2f5183dfb	2106	/**
Kojto	115:87f2f5183dfb	2107	* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
Kojto	115:87f2f5183dfb	2108	* @retval None
Kojto	115:87f2f5183dfb	2109	*/
Kojto	115:87f2f5183dfb	2110	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP;\
Kojto	115:87f2f5183dfb	2111	EXTI->FTSR \|= ETH_EXTI_LINE_WAKEUP
Kojto	115:87f2f5183dfb	2112
Kojto	115:87f2f5183dfb	2113	/**
Kojto	115:87f2f5183dfb	2114	* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
Kojto	115:87f2f5183dfb	2115	* @retval None
Kojto	115:87f2f5183dfb	2116	*/
Kojto	115:87f2f5183dfb	2117	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
Kojto	115:87f2f5183dfb	2118	EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	115:87f2f5183dfb	2119
Kojto	115:87f2f5183dfb	2120	/**
Kojto	115:87f2f5183dfb	2121	* @brief Generate a Software interrupt on selected EXTI line.
Kojto	115:87f2f5183dfb	2122	* @retval None.
Kojto	115:87f2f5183dfb	2123	*/
Kojto	115:87f2f5183dfb	2124	#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER\|= ETH_EXTI_LINE_WAKEUP
Kojto	115:87f2f5183dfb	2125
Kojto	115:87f2f5183dfb	2126	/**
Kojto	115:87f2f5183dfb	2127	* @}
Kojto	115:87f2f5183dfb	2128	*/
Kojto	115:87f2f5183dfb	2129	/* Exported functions --------------------------------------------------------*/
Kojto	115:87f2f5183dfb	2130
Kojto	115:87f2f5183dfb	2131	/** @addtogroup ETH_Exported_Functions
Kojto	115:87f2f5183dfb	2132	* @{
Kojto	115:87f2f5183dfb	2133	*/
Kojto	115:87f2f5183dfb	2134
Kojto	115:87f2f5183dfb	2135	/* Initialization and de-initialization functions ****************************/
Kojto	115:87f2f5183dfb	2136
Kojto	115:87f2f5183dfb	2137	/** @addtogroup ETH_Exported_Functions_Group1
Kojto	115:87f2f5183dfb	2138	* @{
Kojto	115:87f2f5183dfb	2139	*/
Kojto	115:87f2f5183dfb	2140	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2141	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2142	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2143	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2144	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
Kojto	115:87f2f5183dfb	2145	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
Kojto	115:87f2f5183dfb	2146
Kojto	115:87f2f5183dfb	2147	/**
Kojto	115:87f2f5183dfb	2148	* @}
Kojto	115:87f2f5183dfb	2149	*/
Kojto	115:87f2f5183dfb	2150	/* IO operation functions ****************************************************/
Kojto	115:87f2f5183dfb	2151
Kojto	115:87f2f5183dfb	2152	/** @addtogroup ETH_Exported_Functions_Group2
Kojto	115:87f2f5183dfb	2153	* @{
Kojto	115:87f2f5183dfb	2154	*/
Kojto	115:87f2f5183dfb	2155	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
Kojto	115:87f2f5183dfb	2156	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2157	/* Communication with PHY functions*/
Kojto	115:87f2f5183dfb	2158	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
Kojto	115:87f2f5183dfb	2159	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
Kojto	115:87f2f5183dfb	2160	/* Non-Blocking mode: Interrupt */
Kojto	115:87f2f5183dfb	2161	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2162	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2163	/* Callback in non blocking modes (Interrupt) */
Kojto	115:87f2f5183dfb	2164	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2165	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2166	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2167	/**
Kojto	115:87f2f5183dfb	2168	* @}
Kojto	115:87f2f5183dfb	2169	*/
Kojto	115:87f2f5183dfb	2170
Kojto	115:87f2f5183dfb	2171	/* Peripheral Control functions **********************************************/
Kojto	115:87f2f5183dfb	2172
Kojto	115:87f2f5183dfb	2173	/** @addtogroup ETH_Exported_Functions_Group3
Kojto	115:87f2f5183dfb	2174	* @{
Kojto	115:87f2f5183dfb	2175	*/
Kojto	115:87f2f5183dfb	2176
Kojto	115:87f2f5183dfb	2177	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2178	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2179	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
Kojto	115:87f2f5183dfb	2180	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
Kojto	115:87f2f5183dfb	2181	/**
Kojto	115:87f2f5183dfb	2182	* @}
Kojto	115:87f2f5183dfb	2183	*/
Kojto	115:87f2f5183dfb	2184
Kojto	115:87f2f5183dfb	2185	/* Peripheral State functions ************************************************/
Kojto	115:87f2f5183dfb	2186
Kojto	115:87f2f5183dfb	2187	/** @addtogroup ETH_Exported_Functions_Group4
Kojto	115:87f2f5183dfb	2188	* @{
Kojto	115:87f2f5183dfb	2189	*/
Kojto	115:87f2f5183dfb	2190	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
Kojto	115:87f2f5183dfb	2191	/**
Kojto	115:87f2f5183dfb	2192	* @}
Kojto	115:87f2f5183dfb	2193	*/
Kojto	115:87f2f5183dfb	2194
Kojto	115:87f2f5183dfb	2195	/**
Kojto	115:87f2f5183dfb	2196	* @}
Kojto	115:87f2f5183dfb	2197	*/
Kojto	115:87f2f5183dfb	2198
Kojto	115:87f2f5183dfb	2199	/**
Kojto	115:87f2f5183dfb	2200	* @}
Kojto	115:87f2f5183dfb	2201	*/
Kojto	115:87f2f5183dfb	2202
Kojto	115:87f2f5183dfb	2203	/**
Kojto	115:87f2f5183dfb	2204	* @}
Kojto	115:87f2f5183dfb	2205	*/
Kojto	115:87f2f5183dfb	2206	#ifdef __cplusplus
Kojto	115:87f2f5183dfb	2207	}
Kojto	115:87f2f5183dfb	2208	#endif
Kojto	115:87f2f5183dfb	2209
Kojto	115:87f2f5183dfb	2210	#endif /* __STM32F7xx_HAL_ETH_H */
Kojto	115:87f2f5183dfb	2211
Kojto	115:87f2f5183dfb	2212
Kojto	115:87f2f5183dfb	2213
Kojto	115:87f2f5183dfb	2214	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F746ZG/stm32f7xx_hal_eth.h@121:672067c3ada4, 2016-04-14 (annotated)

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