Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

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TARGET_NUCLEO_F070RB/stm32f070xb.h@108:34e6b704fe68, 2015-10-02 (annotated)

Committer:
Kojto
Date:
Fri Oct 02 07:35:07 2015 +0200
Revision:
108:34e6b704fe68
Parent:
93:e188a91d3eaa 
Release 108  of the mbed library



Changes:

- new platforms - ELMO_F411RE, WIZNET_7500P, ARM_MPS2_BEID

- EFM32 - bugfixes in rtc, serial

- Cortex A cmsis - update files

- STML4 - RAM fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 93:e188a91d3eaa 1 /**
Kojto 93:e188a91d3eaa 2 ******************************************************************************
Kojto 93:e188a91d3eaa 3 * @file stm32f070xb.h
Kojto 93:e188a91d3eaa 4 * @author MCD Application Team
Kojto 108:34e6b704fe68 5 * @version V2.2.2
Kojto 108:34e6b704fe68 6 * @date 26-June-2015
Kojto 93:e188a91d3eaa 7 * @brief CMSIS STM32F070xB devices Peripheral Access Layer Header File.
Kojto 93:e188a91d3eaa 8 *
Kojto 93:e188a91d3eaa 9 * This file contains:
Kojto 93:e188a91d3eaa 10 * - Data structures and the address mapping for all peripherals
Kojto 93:e188a91d3eaa 11 * - Peripheral's registers declarations and bits definition
Kojto 93:e188a91d3eaa 12 * - Macros to access peripheral’s registers hardware
Kojto 93:e188a91d3eaa 13 *
Kojto 93:e188a91d3eaa 14 ******************************************************************************
Kojto 93:e188a91d3eaa 15 * @attention
Kojto 93:e188a91d3eaa 16 *
Kojto 108:34e6b704fe68 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 93:e188a91d3eaa 18 *
Kojto 93:e188a91d3eaa 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 93:e188a91d3eaa 20 * are permitted provided that the following conditions are met:
Kojto 93:e188a91d3eaa 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 93:e188a91d3eaa 22 * this list of conditions and the following disclaimer.
Kojto 93:e188a91d3eaa 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 93:e188a91d3eaa 24 * this list of conditions and the following disclaimer in the documentation
Kojto 93:e188a91d3eaa 25 * and/or other materials provided with the distribution.
Kojto 93:e188a91d3eaa 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 93:e188a91d3eaa 27 * may be used to endorse or promote products derived from this software
Kojto 93:e188a91d3eaa 28 * without specific prior written permission.
Kojto 93:e188a91d3eaa 29 *
Kojto 93:e188a91d3eaa 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 93:e188a91d3eaa 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 93:e188a91d3eaa 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 93:e188a91d3eaa 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 93:e188a91d3eaa 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 93:e188a91d3eaa 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 93:e188a91d3eaa 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 93:e188a91d3eaa 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 93:e188a91d3eaa 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 93:e188a91d3eaa 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 93:e188a91d3eaa 40 *
Kojto 93:e188a91d3eaa 41 ******************************************************************************
Kojto 93:e188a91d3eaa 42 */
Kojto 93:e188a91d3eaa 43
Kojto 93:e188a91d3eaa 44 /** @addtogroup CMSIS_Device
Kojto 93:e188a91d3eaa 45 * @{
Kojto 93:e188a91d3eaa 46 */
Kojto 93:e188a91d3eaa 47
Kojto 93:e188a91d3eaa 48 /** @addtogroup stm32f070xb
Kojto 93:e188a91d3eaa 49 * @{
Kojto 93:e188a91d3eaa 50 */
Kojto 93:e188a91d3eaa 51
Kojto 93:e188a91d3eaa 52 #ifndef __STM32F070xB_H
Kojto 93:e188a91d3eaa 53 #define __STM32F070xB_H
Kojto 93:e188a91d3eaa 54
Kojto 93:e188a91d3eaa 55 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 56 extern "C" {
Kojto 93:e188a91d3eaa 57 #endif /* __cplusplus */
Kojto 93:e188a91d3eaa 58
Kojto 93:e188a91d3eaa 59 /** @addtogroup Configuration_section_for_CMSIS
Kojto 93:e188a91d3eaa 60 * @{
Kojto 93:e188a91d3eaa 61 */
Kojto 93:e188a91d3eaa 62 /**
Kojto 93:e188a91d3eaa 63 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
Kojto 93:e188a91d3eaa 64 */
Kojto 93:e188a91d3eaa 65 #define __CM0_REV 0 /*!< Core Revision r0p0 */
Kojto 93:e188a91d3eaa 66 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
Kojto 93:e188a91d3eaa 67 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
Kojto 93:e188a91d3eaa 68 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 93:e188a91d3eaa 69
Kojto 93:e188a91d3eaa 70 /**
Kojto 93:e188a91d3eaa 71 * @}
Kojto 93:e188a91d3eaa 72 */
Kojto 93:e188a91d3eaa 73
Kojto 93:e188a91d3eaa 74 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 93:e188a91d3eaa 75 * @{
Kojto 93:e188a91d3eaa 76 */
Kojto 93:e188a91d3eaa 77
Kojto 93:e188a91d3eaa 78 /**
Kojto 93:e188a91d3eaa 79 * @brief STM32F070xB device Interrupt Number Definition
Kojto 93:e188a91d3eaa 80 */
Kojto 93:e188a91d3eaa 81 typedef enum
Kojto 93:e188a91d3eaa 82 {
Kojto 93:e188a91d3eaa 83 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
Kojto 93:e188a91d3eaa 84 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 93:e188a91d3eaa 85 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
Kojto 93:e188a91d3eaa 86 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
Kojto 93:e188a91d3eaa 87 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
Kojto 93:e188a91d3eaa 88 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
Kojto 93:e188a91d3eaa 89
Kojto 93:e188a91d3eaa 90 /****** STM32F070xB specific Interrupt Numbers **************************************************/
Kojto 93:e188a91d3eaa 91 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 93:e188a91d3eaa 92 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
Kojto 93:e188a91d3eaa 93 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
Kojto 93:e188a91d3eaa 94 RCC_IRQn = 4, /*!< RCC Global Interrupts */
Kojto 93:e188a91d3eaa 95 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
Kojto 93:e188a91d3eaa 96 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
Kojto 93:e188a91d3eaa 97 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
Kojto 93:e188a91d3eaa 98 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
Kojto 93:e188a91d3eaa 99 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
Kojto 93:e188a91d3eaa 100 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
Kojto 93:e188a91d3eaa 101 ADC1_IRQn = 12, /*!< ADC1 interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
Kojto 93:e188a91d3eaa 102 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
Kojto 93:e188a91d3eaa 103 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
Kojto 93:e188a91d3eaa 104 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
Kojto 93:e188a91d3eaa 105 TIM6_IRQn = 17, /*!< TIM6 global Interrupts */
Kojto 93:e188a91d3eaa 106 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
Kojto 93:e188a91d3eaa 107 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
Kojto 93:e188a91d3eaa 108 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
Kojto 93:e188a91d3eaa 109 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
Kojto 93:e188a91d3eaa 110 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
Kojto 93:e188a91d3eaa 111 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
Kojto 93:e188a91d3eaa 112 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
Kojto 93:e188a91d3eaa 113 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
Kojto 93:e188a91d3eaa 114 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
Kojto 93:e188a91d3eaa 115 USART1_IRQn = 27, /*!< USART1 global Interrupt */
Kojto 93:e188a91d3eaa 116 USART2_IRQn = 28, /*!< USART2 global Interrupt */
Kojto 93:e188a91d3eaa 117 USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupts */
Kojto 93:e188a91d3eaa 118 USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */
Kojto 93:e188a91d3eaa 119 } IRQn_Type;
Kojto 93:e188a91d3eaa 120
Kojto 93:e188a91d3eaa 121 /**
Kojto 93:e188a91d3eaa 122 * @}
Kojto 93:e188a91d3eaa 123 */
Kojto 93:e188a91d3eaa 124
Kojto 93:e188a91d3eaa 125 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
Kojto 93:e188a91d3eaa 126 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
Kojto 93:e188a91d3eaa 127 #include <stdint.h>
Kojto 93:e188a91d3eaa 128
Kojto 93:e188a91d3eaa 129 /** @addtogroup Peripheral_registers_structures
Kojto 93:e188a91d3eaa 130 * @{
Kojto 93:e188a91d3eaa 131 */
Kojto 93:e188a91d3eaa 132
Kojto 93:e188a91d3eaa 133 /**
Kojto 93:e188a91d3eaa 134 * @brief Analog to Digital Converter
Kojto 93:e188a91d3eaa 135 */
Kojto 93:e188a91d3eaa 136
Kojto 93:e188a91d3eaa 137 typedef struct
Kojto 93:e188a91d3eaa 138 {
Kojto 93:e188a91d3eaa 139 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
Kojto 93:e188a91d3eaa 140 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
Kojto 93:e188a91d3eaa 141 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
Kojto 93:e188a91d3eaa 142 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
Kojto 93:e188a91d3eaa 143 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
Kojto 93:e188a91d3eaa 144 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
Kojto 93:e188a91d3eaa 145 uint32_t RESERVED1; /*!< Reserved, 0x18 */
Kojto 93:e188a91d3eaa 146 uint32_t RESERVED2; /*!< Reserved, 0x1C */
Kojto 93:e188a91d3eaa 147 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
Kojto 93:e188a91d3eaa 148 uint32_t RESERVED3; /*!< Reserved, 0x24 */
Kojto 93:e188a91d3eaa 149 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
Kojto 93:e188a91d3eaa 150 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
Kojto 93:e188a91d3eaa 151 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
Kojto 93:e188a91d3eaa 152 }ADC_TypeDef;
Kojto 93:e188a91d3eaa 153
Kojto 93:e188a91d3eaa 154 typedef struct
Kojto 93:e188a91d3eaa 155 {
Kojto 93:e188a91d3eaa 156 __IO uint32_t CCR;
Kojto 93:e188a91d3eaa 157 }ADC_Common_TypeDef;
Kojto 93:e188a91d3eaa 158
Kojto 93:e188a91d3eaa 159 /**
Kojto 93:e188a91d3eaa 160 * @brief CRC calculation unit
Kojto 93:e188a91d3eaa 161 */
Kojto 93:e188a91d3eaa 162
Kojto 93:e188a91d3eaa 163 typedef struct
Kojto 93:e188a91d3eaa 164 {
Kojto 93:e188a91d3eaa 165 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 166 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 167 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 93:e188a91d3eaa 168 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 93:e188a91d3eaa 169 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 170 uint32_t RESERVED2; /*!< Reserved, 0x0C */
Kojto 93:e188a91d3eaa 171 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 172 __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */
Kojto 93:e188a91d3eaa 173 }CRC_TypeDef;
Kojto 93:e188a91d3eaa 174
Kojto 93:e188a91d3eaa 175 /**
Kojto 93:e188a91d3eaa 176 * @brief Debug MCU
Kojto 93:e188a91d3eaa 177 */
Kojto 93:e188a91d3eaa 178
Kojto 93:e188a91d3eaa 179 typedef struct
Kojto 93:e188a91d3eaa 180 {
Kojto 93:e188a91d3eaa 181 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 182 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 183 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 184 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 185 }DBGMCU_TypeDef;
Kojto 93:e188a91d3eaa 186
Kojto 93:e188a91d3eaa 187 /**
Kojto 93:e188a91d3eaa 188 * @brief DMA Controller
Kojto 93:e188a91d3eaa 189 */
Kojto 93:e188a91d3eaa 190
Kojto 93:e188a91d3eaa 191 typedef struct
Kojto 93:e188a91d3eaa 192 {
Kojto 93:e188a91d3eaa 193 __IO uint32_t CCR; /*!< DMA channel x configuration register */
Kojto 93:e188a91d3eaa 194 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
Kojto 93:e188a91d3eaa 195 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
Kojto 93:e188a91d3eaa 196 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
Kojto 93:e188a91d3eaa 197 }DMA_Channel_TypeDef;
Kojto 93:e188a91d3eaa 198
Kojto 93:e188a91d3eaa 199 typedef struct
Kojto 93:e188a91d3eaa 200 {
Kojto 93:e188a91d3eaa 201 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 202 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 203 }DMA_TypeDef;
Kojto 93:e188a91d3eaa 204
Kojto 93:e188a91d3eaa 205 /**
Kojto 93:e188a91d3eaa 206 * @brief External Interrupt/Event Controller
Kojto 93:e188a91d3eaa 207 */
Kojto 93:e188a91d3eaa 208
Kojto 93:e188a91d3eaa 209 typedef struct
Kojto 93:e188a91d3eaa 210 {
Kojto 93:e188a91d3eaa 211 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 212 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 213 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
Kojto 93:e188a91d3eaa 214 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 215 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 216 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 217 }EXTI_TypeDef;
Kojto 93:e188a91d3eaa 218
Kojto 93:e188a91d3eaa 219 /**
Kojto 93:e188a91d3eaa 220 * @brief FLASH Registers
Kojto 93:e188a91d3eaa 221 */
Kojto 93:e188a91d3eaa 222 typedef struct
Kojto 93:e188a91d3eaa 223 {
Kojto 93:e188a91d3eaa 224 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 225 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 226 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 227 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 228 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 229 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 230 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
Kojto 93:e188a91d3eaa 231 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 232 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 233 }FLASH_TypeDef;
Kojto 93:e188a91d3eaa 234
Kojto 93:e188a91d3eaa 235
Kojto 93:e188a91d3eaa 236 /**
Kojto 93:e188a91d3eaa 237 * @brief Option Bytes Registers
Kojto 93:e188a91d3eaa 238 */
Kojto 93:e188a91d3eaa 239 typedef struct
Kojto 93:e188a91d3eaa 240 {
Kojto 93:e188a91d3eaa 241 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 242 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
Kojto 93:e188a91d3eaa 243 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
Kojto 93:e188a91d3eaa 244 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
Kojto 93:e188a91d3eaa 245 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 246 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
Kojto 93:e188a91d3eaa 247 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 248 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
Kojto 93:e188a91d3eaa 249 }OB_TypeDef;
Kojto 93:e188a91d3eaa 250
Kojto 93:e188a91d3eaa 251 /**
Kojto 93:e188a91d3eaa 252 * @brief General Purpose I/O
Kojto 93:e188a91d3eaa 253 */
Kojto 93:e188a91d3eaa 254
Kojto 93:e188a91d3eaa 255 typedef struct
Kojto 93:e188a91d3eaa 256 {
Kojto 93:e188a91d3eaa 257 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 258 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 259 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 260 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 261 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 262 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 263 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
Kojto 93:e188a91d3eaa 264 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 265 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
Kojto 93:e188a91d3eaa 266 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 267 }GPIO_TypeDef;
Kojto 93:e188a91d3eaa 268
Kojto 93:e188a91d3eaa 269 /**
Kojto 93:e188a91d3eaa 270 * @brief SysTem Configuration
Kojto 93:e188a91d3eaa 271 */
Kojto 93:e188a91d3eaa 272
Kojto 93:e188a91d3eaa 273 typedef struct
Kojto 93:e188a91d3eaa 274 {
Kojto 93:e188a91d3eaa 275 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 276 uint32_t RESERVED; /*!< Reserved, 0x04 */
Kojto 93:e188a91d3eaa 277 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
Kojto 93:e188a91d3eaa 278 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 279 }SYSCFG_TypeDef;
Kojto 93:e188a91d3eaa 280
Kojto 93:e188a91d3eaa 281 /**
Kojto 93:e188a91d3eaa 282 * @brief Inter-integrated Circuit Interface
Kojto 93:e188a91d3eaa 283 */
Kojto 93:e188a91d3eaa 284
Kojto 93:e188a91d3eaa 285 typedef struct
Kojto 93:e188a91d3eaa 286 {
Kojto 93:e188a91d3eaa 287 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 288 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 289 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 290 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 291 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 292 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 293 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 294 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 295 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 296 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 297 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 298 }I2C_TypeDef;
Kojto 93:e188a91d3eaa 299
Kojto 93:e188a91d3eaa 300 /**
Kojto 93:e188a91d3eaa 301 * @brief Independent WATCHDOG
Kojto 93:e188a91d3eaa 302 */
Kojto 93:e188a91d3eaa 303
Kojto 93:e188a91d3eaa 304 typedef struct
Kojto 93:e188a91d3eaa 305 {
Kojto 93:e188a91d3eaa 306 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 307 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 308 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 309 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 310 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 311 }IWDG_TypeDef;
Kojto 93:e188a91d3eaa 312
Kojto 93:e188a91d3eaa 313 /**
Kojto 93:e188a91d3eaa 314 * @brief Power Control
Kojto 93:e188a91d3eaa 315 */
Kojto 93:e188a91d3eaa 316
Kojto 93:e188a91d3eaa 317 typedef struct
Kojto 93:e188a91d3eaa 318 {
Kojto 93:e188a91d3eaa 319 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 320 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 321 }PWR_TypeDef;
Kojto 93:e188a91d3eaa 322
Kojto 93:e188a91d3eaa 323 /**
Kojto 93:e188a91d3eaa 324 * @brief Reset and Clock Control
Kojto 93:e188a91d3eaa 325 */
Kojto 108:34e6b704fe68 326
Kojto 93:e188a91d3eaa 327 typedef struct
Kojto 93:e188a91d3eaa 328 {
Kojto 93:e188a91d3eaa 329 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 330 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 331 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 332 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 333 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 334 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 335 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 336 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 337 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 338 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 339 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 340 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
Kojto 93:e188a91d3eaa 341 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 342 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 343 }RCC_TypeDef;
Kojto 93:e188a91d3eaa 344
Kojto 93:e188a91d3eaa 345 /**
Kojto 93:e188a91d3eaa 346 * @brief Real-Time Clock
Kojto 93:e188a91d3eaa 347 */
Kojto 93:e188a91d3eaa 348 typedef struct
Kojto 93:e188a91d3eaa 349 {
Kojto 93:e188a91d3eaa 350 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 351 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 352 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 353 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 354 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 108:34e6b704fe68 355 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 108:34e6b704fe68 356 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 357 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 108:34e6b704fe68 358 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 359 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 360 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 361 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 93:e188a91d3eaa 362 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 363 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 364 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 93:e188a91d3eaa 365 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 93:e188a91d3eaa 366 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 93:e188a91d3eaa 367 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 93:e188a91d3eaa 368 }RTC_TypeDef;
Kojto 93:e188a91d3eaa 369
Kojto 93:e188a91d3eaa 370 /**
Kojto 93:e188a91d3eaa 371 * @brief Serial Peripheral Interface
Kojto 93:e188a91d3eaa 372 */
Kojto 93:e188a91d3eaa 373
Kojto 93:e188a91d3eaa 374 typedef struct
Kojto 93:e188a91d3eaa 375 {
Kojto 93:e188a91d3eaa 376 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 93:e188a91d3eaa 377 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 378 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 379 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 380 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 93:e188a91d3eaa 381 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 93:e188a91d3eaa 382 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 93:e188a91d3eaa 383 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 384 __IO uint32_t RESERVED1;/*!< Reserved, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 385 }SPI_TypeDef;
Kojto 93:e188a91d3eaa 386
Kojto 93:e188a91d3eaa 387 /**
Kojto 93:e188a91d3eaa 388 * @brief TIM
Kojto 93:e188a91d3eaa 389 */
Kojto 93:e188a91d3eaa 390 typedef struct
Kojto 93:e188a91d3eaa 391 {
Kojto 93:e188a91d3eaa 392 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 393 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 394 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 395 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 396 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 397 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 398 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 399 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 400 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 401 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 402 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 403 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 93:e188a91d3eaa 404 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 405 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 406 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 93:e188a91d3eaa 407 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 93:e188a91d3eaa 408 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 93:e188a91d3eaa 409 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 93:e188a91d3eaa 410 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 93:e188a91d3eaa 411 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
Kojto 93:e188a91d3eaa 412 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 93:e188a91d3eaa 413 }TIM_TypeDef;
Kojto 93:e188a91d3eaa 414
Kojto 93:e188a91d3eaa 415
Kojto 93:e188a91d3eaa 416 /**
Kojto 93:e188a91d3eaa 417 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 93:e188a91d3eaa 418 */
Kojto 93:e188a91d3eaa 419
Kojto 93:e188a91d3eaa 420 typedef struct
Kojto 93:e188a91d3eaa 421 {
Kojto 93:e188a91d3eaa 422 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 423 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 424 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 425 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 426 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 427 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 428 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 429 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 430 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 431 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 432 uint16_t RESERVED1; /*!< Reserved, 0x26 */
Kojto 93:e188a91d3eaa 433 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 434 uint16_t RESERVED2; /*!< Reserved, 0x2A */
Kojto 93:e188a91d3eaa 435 }USART_TypeDef;
Kojto 93:e188a91d3eaa 436
Kojto 93:e188a91d3eaa 437 /**
Kojto 93:e188a91d3eaa 438 * @brief Universal Serial Bus Full Speed Device
Kojto 93:e188a91d3eaa 439 */
Kojto 93:e188a91d3eaa 440
Kojto 93:e188a91d3eaa 441 typedef struct
Kojto 93:e188a91d3eaa 442 {
Kojto 93:e188a91d3eaa 443 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 444 __IO uint16_t RESERVED0; /*!< Reserved */
Kojto 93:e188a91d3eaa 445 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 446 __IO uint16_t RESERVED1; /*!< Reserved */
Kojto 93:e188a91d3eaa 447 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 448 __IO uint16_t RESERVED2; /*!< Reserved */
Kojto 93:e188a91d3eaa 449 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 450 __IO uint16_t RESERVED3; /*!< Reserved */
Kojto 93:e188a91d3eaa 451 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 452 __IO uint16_t RESERVED4; /*!< Reserved */
Kojto 93:e188a91d3eaa 453 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 454 __IO uint16_t RESERVED5; /*!< Reserved */
Kojto 93:e188a91d3eaa 455 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 456 __IO uint16_t RESERVED6; /*!< Reserved */
Kojto 93:e188a91d3eaa 457 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 458 __IO uint16_t RESERVED7[17]; /*!< Reserved */
Kojto 93:e188a91d3eaa 459 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
Kojto 93:e188a91d3eaa 460 __IO uint16_t RESERVED8; /*!< Reserved */
Kojto 93:e188a91d3eaa 461 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
Kojto 93:e188a91d3eaa 462 __IO uint16_t RESERVED9; /*!< Reserved */
Kojto 93:e188a91d3eaa 463 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
Kojto 93:e188a91d3eaa 464 __IO uint16_t RESERVEDA; /*!< Reserved */
Kojto 93:e188a91d3eaa 465 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
Kojto 93:e188a91d3eaa 466 __IO uint16_t RESERVEDB; /*!< Reserved */
Kojto 93:e188a91d3eaa 467 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
Kojto 93:e188a91d3eaa 468 __IO uint16_t RESERVEDC; /*!< Reserved */
Kojto 93:e188a91d3eaa 469 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
Kojto 93:e188a91d3eaa 470 __IO uint16_t RESERVEDD; /*!< Reserved */
Kojto 93:e188a91d3eaa 471 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
Kojto 93:e188a91d3eaa 472 __IO uint16_t RESERVEDE; /*!< Reserved */
Kojto 93:e188a91d3eaa 473 }USB_TypeDef;
Kojto 93:e188a91d3eaa 474
Kojto 93:e188a91d3eaa 475 /**
Kojto 93:e188a91d3eaa 476 * @brief Window WATCHDOG
Kojto 93:e188a91d3eaa 477 */
Kojto 93:e188a91d3eaa 478 typedef struct
Kojto 93:e188a91d3eaa 479 {
Kojto 93:e188a91d3eaa 480 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 481 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 482 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 483 }WWDG_TypeDef;
Kojto 93:e188a91d3eaa 484
Kojto 93:e188a91d3eaa 485 /**
Kojto 93:e188a91d3eaa 486 * @}
Kojto 93:e188a91d3eaa 487 */
Kojto 93:e188a91d3eaa 488
Kojto 93:e188a91d3eaa 489 /** @addtogroup Peripheral_memory_map
Kojto 93:e188a91d3eaa 490 * @{
Kojto 93:e188a91d3eaa 491 */
Kojto 93:e188a91d3eaa 492
Kojto 93:e188a91d3eaa 493 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
Kojto 108:34e6b704fe68 494 #define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
Kojto 93:e188a91d3eaa 495 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
Kojto 93:e188a91d3eaa 496 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
Kojto 93:e188a91d3eaa 497
Kojto 93:e188a91d3eaa 498 /*!< Peripheral memory map */
Kojto 93:e188a91d3eaa 499 #define APBPERIPH_BASE PERIPH_BASE
Kojto 93:e188a91d3eaa 500 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 93:e188a91d3eaa 501 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
Kojto 93:e188a91d3eaa 502
Kojto 93:e188a91d3eaa 503 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
Kojto 93:e188a91d3eaa 504 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
Kojto 93:e188a91d3eaa 505 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
Kojto 93:e188a91d3eaa 506 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
Kojto 93:e188a91d3eaa 507 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
Kojto 93:e188a91d3eaa 508 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
Kojto 93:e188a91d3eaa 509 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
Kojto 93:e188a91d3eaa 510 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
Kojto 93:e188a91d3eaa 511 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
Kojto 93:e188a91d3eaa 512 #define USART3_BASE (APBPERIPH_BASE + 0x00004800)
Kojto 93:e188a91d3eaa 513 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
Kojto 93:e188a91d3eaa 514 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
Kojto 93:e188a91d3eaa 515 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
Kojto 93:e188a91d3eaa 516 #define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
Kojto 93:e188a91d3eaa 517 #define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
Kojto 93:e188a91d3eaa 518 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
Kojto 93:e188a91d3eaa 519 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
Kojto 93:e188a91d3eaa 520 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
Kojto 93:e188a91d3eaa 521 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
Kojto 93:e188a91d3eaa 522 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
Kojto 93:e188a91d3eaa 523 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
Kojto 93:e188a91d3eaa 524 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
Kojto 93:e188a91d3eaa 525 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
Kojto 93:e188a91d3eaa 526 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
Kojto 93:e188a91d3eaa 527 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
Kojto 93:e188a91d3eaa 528 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
Kojto 93:e188a91d3eaa 529 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
Kojto 93:e188a91d3eaa 530
Kojto 93:e188a91d3eaa 531 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
Kojto 93:e188a91d3eaa 532 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
Kojto 93:e188a91d3eaa 533 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
Kojto 93:e188a91d3eaa 534 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
Kojto 93:e188a91d3eaa 535 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
Kojto 93:e188a91d3eaa 536 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
Kojto 93:e188a91d3eaa 537
Kojto 93:e188a91d3eaa 538 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
Kojto 93:e188a91d3eaa 539 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
Kojto 93:e188a91d3eaa 540 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
Kojto 93:e188a91d3eaa 541 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
Kojto 93:e188a91d3eaa 542
Kojto 93:e188a91d3eaa 543 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
Kojto 93:e188a91d3eaa 544 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
Kojto 93:e188a91d3eaa 545 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
Kojto 93:e188a91d3eaa 546 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
Kojto 93:e188a91d3eaa 547 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
Kojto 93:e188a91d3eaa 548
Kojto 93:e188a91d3eaa 549 /**
Kojto 93:e188a91d3eaa 550 * @}
Kojto 93:e188a91d3eaa 551 */
Kojto 93:e188a91d3eaa 552
Kojto 93:e188a91d3eaa 553 /** @addtogroup Peripheral_declaration
Kojto 93:e188a91d3eaa 554 * @{
Kojto 93:e188a91d3eaa 555 */
Kojto 93:e188a91d3eaa 556
Kojto 93:e188a91d3eaa 557 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 93:e188a91d3eaa 558 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 93:e188a91d3eaa 559 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto 93:e188a91d3eaa 560 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto 93:e188a91d3eaa 561 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 93:e188a91d3eaa 562 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 93:e188a91d3eaa 563 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 93:e188a91d3eaa 564 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 93:e188a91d3eaa 565 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 93:e188a91d3eaa 566 #define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto 93:e188a91d3eaa 567 #define USART4 ((USART_TypeDef *) USART4_BASE)
Kojto 93:e188a91d3eaa 568 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 93:e188a91d3eaa 569 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 93:e188a91d3eaa 570 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 93:e188a91d3eaa 571 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 93:e188a91d3eaa 572 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 93:e188a91d3eaa 573 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 93:e188a91d3eaa 574 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 93:e188a91d3eaa 575 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 93:e188a91d3eaa 576 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 93:e188a91d3eaa 577 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 93:e188a91d3eaa 578 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
Kojto 93:e188a91d3eaa 579 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
Kojto 93:e188a91d3eaa 580 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
Kojto 93:e188a91d3eaa 581 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 93:e188a91d3eaa 582 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 93:e188a91d3eaa 583 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto 93:e188a91d3eaa 584 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto 93:e188a91d3eaa 585 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto 93:e188a91d3eaa 586 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto 93:e188a91d3eaa 587 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto 93:e188a91d3eaa 588 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 93:e188a91d3eaa 589 #define OB ((OB_TypeDef *) OB_BASE)
Kojto 93:e188a91d3eaa 590 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 93:e188a91d3eaa 591 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 93:e188a91d3eaa 592 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 93:e188a91d3eaa 593 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 93:e188a91d3eaa 594 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 93:e188a91d3eaa 595 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 93:e188a91d3eaa 596 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 93:e188a91d3eaa 597 #define USB ((USB_TypeDef *) USB_BASE)
Kojto 93:e188a91d3eaa 598 /**
Kojto 93:e188a91d3eaa 599 * @}
Kojto 93:e188a91d3eaa 600 */
Kojto 93:e188a91d3eaa 601
Kojto 93:e188a91d3eaa 602 /** @addtogroup Exported_constants
Kojto 93:e188a91d3eaa 603 * @{
Kojto 93:e188a91d3eaa 604 */
Kojto 93:e188a91d3eaa 605
Kojto 93:e188a91d3eaa 606 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 93:e188a91d3eaa 607 * @{
Kojto 93:e188a91d3eaa 608 */
Kojto 93:e188a91d3eaa 609
Kojto 93:e188a91d3eaa 610 /******************************************************************************/
Kojto 93:e188a91d3eaa 611 /* Peripheral Registers Bits Definition */
Kojto 93:e188a91d3eaa 612 /******************************************************************************/
Kojto 93:e188a91d3eaa 613 /******************************************************************************/
Kojto 93:e188a91d3eaa 614 /* */
Kojto 93:e188a91d3eaa 615 /* Analog to Digital Converter (ADC) */
Kojto 93:e188a91d3eaa 616 /* */
Kojto 93:e188a91d3eaa 617 /******************************************************************************/
Kojto 93:e188a91d3eaa 618 /******************** Bits definition for ADC_ISR register ******************/
Kojto 93:e188a91d3eaa 619 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
Kojto 93:e188a91d3eaa 620 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
Kojto 93:e188a91d3eaa 621 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
Kojto 93:e188a91d3eaa 622 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
Kojto 93:e188a91d3eaa 623 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
Kojto 93:e188a91d3eaa 624 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
Kojto 93:e188a91d3eaa 625
Kojto 93:e188a91d3eaa 626 /* Old EOSEQ bit definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 627 #define ADC_ISR_EOS ADC_ISR_EOSEQ
Kojto 93:e188a91d3eaa 628
Kojto 93:e188a91d3eaa 629 /******************** Bits definition for ADC_IER register ******************/
Kojto 93:e188a91d3eaa 630 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
Kojto 93:e188a91d3eaa 631 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
Kojto 93:e188a91d3eaa 632 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
Kojto 93:e188a91d3eaa 633 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
Kojto 93:e188a91d3eaa 634 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
Kojto 93:e188a91d3eaa 635 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
Kojto 93:e188a91d3eaa 636
Kojto 93:e188a91d3eaa 637 /* Old EOSEQIE bit definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 638 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
Kojto 93:e188a91d3eaa 639
Kojto 93:e188a91d3eaa 640 /******************** Bits definition for ADC_CR register *******************/
Kojto 93:e188a91d3eaa 641 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
Kojto 93:e188a91d3eaa 642 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
Kojto 93:e188a91d3eaa 643 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
Kojto 93:e188a91d3eaa 644 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
Kojto 93:e188a91d3eaa 645 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
Kojto 93:e188a91d3eaa 646
Kojto 93:e188a91d3eaa 647 /******************* Bits definition for ADC_CFGR1 register *****************/
Kojto 93:e188a91d3eaa 648 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 93:e188a91d3eaa 649 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 650 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 651 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 652 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Kojto 93:e188a91d3eaa 653 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Kojto 93:e188a91d3eaa 654 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
Kojto 93:e188a91d3eaa 655 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
Kojto 93:e188a91d3eaa 656 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
Kojto 93:e188a91d3eaa 657 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
Kojto 93:e188a91d3eaa 658 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
Kojto 93:e188a91d3eaa 659 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
Kojto 93:e188a91d3eaa 660 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
Kojto 93:e188a91d3eaa 661 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
Kojto 93:e188a91d3eaa 662 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 663 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 664 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
Kojto 93:e188a91d3eaa 665 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 666 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 667 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 668 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
Kojto 93:e188a91d3eaa 669 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
Kojto 93:e188a91d3eaa 670 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 671 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 672 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
Kojto 93:e188a91d3eaa 673 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
Kojto 93:e188a91d3eaa 674 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
Kojto 93:e188a91d3eaa 675
Kojto 93:e188a91d3eaa 676 /* Old WAIT bit definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 677 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
Kojto 93:e188a91d3eaa 678
Kojto 93:e188a91d3eaa 679 /******************* Bits definition for ADC_CFGR2 register *****************/
Kojto 93:e188a91d3eaa 680 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
Kojto 93:e188a91d3eaa 681 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
Kojto 93:e188a91d3eaa 682 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
Kojto 93:e188a91d3eaa 683
Kojto 93:e188a91d3eaa 684 /* Old bit definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 685 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
Kojto 93:e188a91d3eaa 686 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
Kojto 93:e188a91d3eaa 687
Kojto 93:e188a91d3eaa 688 /****************** Bit definition for ADC_SMPR register ********************/
Kojto 93:e188a91d3eaa 689 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
Kojto 93:e188a91d3eaa 690 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 691 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 692 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 693
Kojto 93:e188a91d3eaa 694 /* Old bit definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 695 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
Kojto 93:e188a91d3eaa 696 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
Kojto 93:e188a91d3eaa 697 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
Kojto 93:e188a91d3eaa 698 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
Kojto 93:e188a91d3eaa 699
Kojto 93:e188a91d3eaa 700 /******************* Bit definition for ADC_TR register ********************/
Kojto 93:e188a91d3eaa 701 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
Kojto 93:e188a91d3eaa 702 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
Kojto 93:e188a91d3eaa 703
Kojto 93:e188a91d3eaa 704 /* Old bit definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 705 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
Kojto 93:e188a91d3eaa 706 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
Kojto 93:e188a91d3eaa 707
Kojto 93:e188a91d3eaa 708 /****************** Bit definition for ADC_CHSELR register ******************/
Kojto 93:e188a91d3eaa 709 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
Kojto 93:e188a91d3eaa 710 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
Kojto 93:e188a91d3eaa 711 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
Kojto 93:e188a91d3eaa 712 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
Kojto 93:e188a91d3eaa 713 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
Kojto 93:e188a91d3eaa 714 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
Kojto 93:e188a91d3eaa 715 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
Kojto 93:e188a91d3eaa 716 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
Kojto 93:e188a91d3eaa 717 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
Kojto 93:e188a91d3eaa 718 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
Kojto 93:e188a91d3eaa 719 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
Kojto 93:e188a91d3eaa 720 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
Kojto 93:e188a91d3eaa 721 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
Kojto 93:e188a91d3eaa 722 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
Kojto 93:e188a91d3eaa 723 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
Kojto 93:e188a91d3eaa 724 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
Kojto 93:e188a91d3eaa 725 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
Kojto 93:e188a91d3eaa 726 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
Kojto 93:e188a91d3eaa 727 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
Kojto 93:e188a91d3eaa 728
Kojto 93:e188a91d3eaa 729 /******************** Bit definition for ADC_DR register ********************/
Kojto 93:e188a91d3eaa 730 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
Kojto 93:e188a91d3eaa 731
Kojto 93:e188a91d3eaa 732 /******************* Bit definition for ADC_CCR register ********************/
Kojto 93:e188a91d3eaa 733 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
Kojto 93:e188a91d3eaa 734 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
Kojto 93:e188a91d3eaa 735
Kojto 93:e188a91d3eaa 736 /******************************************************************************/
Kojto 93:e188a91d3eaa 737 /* */
Kojto 93:e188a91d3eaa 738 /* CRC calculation unit (CRC) */
Kojto 93:e188a91d3eaa 739 /* */
Kojto 93:e188a91d3eaa 740 /******************************************************************************/
Kojto 93:e188a91d3eaa 741 /******************* Bit definition for CRC_DR register *********************/
Kojto 93:e188a91d3eaa 742 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
Kojto 93:e188a91d3eaa 743
Kojto 93:e188a91d3eaa 744 /******************* Bit definition for CRC_IDR register ********************/
Kojto 93:e188a91d3eaa 745 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
Kojto 93:e188a91d3eaa 746
Kojto 93:e188a91d3eaa 747 /******************** Bit definition for CRC_CR register ********************/
Kojto 93:e188a91d3eaa 748 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
Kojto 93:e188a91d3eaa 749 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
Kojto 93:e188a91d3eaa 750 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
Kojto 93:e188a91d3eaa 751 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
Kojto 93:e188a91d3eaa 752 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
Kojto 93:e188a91d3eaa 753
Kojto 93:e188a91d3eaa 754 /******************* Bit definition for CRC_INIT register *******************/
Kojto 93:e188a91d3eaa 755 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
Kojto 93:e188a91d3eaa 756
Kojto 93:e188a91d3eaa 757 /******************************************************************************/
Kojto 93:e188a91d3eaa 758 /* */
Kojto 93:e188a91d3eaa 759 /* Debug MCU (DBGMCU) */
Kojto 93:e188a91d3eaa 760 /* */
Kojto 93:e188a91d3eaa 761 /******************************************************************************/
Kojto 93:e188a91d3eaa 762
Kojto 93:e188a91d3eaa 763 /**************** Bit definition for DBGMCU_IDCODE register *****************/
Kojto 93:e188a91d3eaa 764 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
Kojto 93:e188a91d3eaa 765
Kojto 93:e188a91d3eaa 766 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
Kojto 93:e188a91d3eaa 767 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 768 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 769 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 770 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 93:e188a91d3eaa 771 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 93:e188a91d3eaa 772 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
Kojto 93:e188a91d3eaa 773 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
Kojto 93:e188a91d3eaa 774 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
Kojto 93:e188a91d3eaa 775 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
Kojto 93:e188a91d3eaa 776 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
Kojto 93:e188a91d3eaa 777 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
Kojto 93:e188a91d3eaa 778 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
Kojto 93:e188a91d3eaa 779 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
Kojto 93:e188a91d3eaa 780 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
Kojto 93:e188a91d3eaa 781 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
Kojto 93:e188a91d3eaa 782 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
Kojto 93:e188a91d3eaa 783
Kojto 93:e188a91d3eaa 784 /****************** Bit definition for DBGMCU_CR register *******************/
Kojto 93:e188a91d3eaa 785 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
Kojto 93:e188a91d3eaa 786 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
Kojto 93:e188a91d3eaa 787
Kojto 93:e188a91d3eaa 788 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
Kojto 93:e188a91d3eaa 789 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
Kojto 93:e188a91d3eaa 790 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
Kojto 93:e188a91d3eaa 791 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
Kojto 93:e188a91d3eaa 792 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
Kojto 93:e188a91d3eaa 793 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
Kojto 93:e188a91d3eaa 794 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
Kojto 93:e188a91d3eaa 795 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
Kojto 93:e188a91d3eaa 796 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
Kojto 93:e188a91d3eaa 797
Kojto 93:e188a91d3eaa 798 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
Kojto 93:e188a91d3eaa 799 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
Kojto 93:e188a91d3eaa 800 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
Kojto 93:e188a91d3eaa 801 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
Kojto 93:e188a91d3eaa 802 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
Kojto 93:e188a91d3eaa 803
Kojto 93:e188a91d3eaa 804 /******************************************************************************/
Kojto 93:e188a91d3eaa 805 /* */
Kojto 93:e188a91d3eaa 806 /* DMA Controller (DMA) */
Kojto 93:e188a91d3eaa 807 /* */
Kojto 93:e188a91d3eaa 808 /******************************************************************************/
Kojto 93:e188a91d3eaa 809 /******************* Bit definition for DMA_ISR register ********************/
Kojto 93:e188a91d3eaa 810 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
Kojto 93:e188a91d3eaa 811 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
Kojto 93:e188a91d3eaa 812 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
Kojto 93:e188a91d3eaa 813 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
Kojto 93:e188a91d3eaa 814 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
Kojto 93:e188a91d3eaa 815 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
Kojto 93:e188a91d3eaa 816 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
Kojto 93:e188a91d3eaa 817 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
Kojto 93:e188a91d3eaa 818 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
Kojto 93:e188a91d3eaa 819 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
Kojto 93:e188a91d3eaa 820 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
Kojto 93:e188a91d3eaa 821 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
Kojto 93:e188a91d3eaa 822 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
Kojto 93:e188a91d3eaa 823 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
Kojto 93:e188a91d3eaa 824 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
Kojto 93:e188a91d3eaa 825 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
Kojto 93:e188a91d3eaa 826 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
Kojto 93:e188a91d3eaa 827 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
Kojto 93:e188a91d3eaa 828 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
Kojto 93:e188a91d3eaa 829 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
Kojto 93:e188a91d3eaa 830
Kojto 93:e188a91d3eaa 831 /******************* Bit definition for DMA_IFCR register *******************/
Kojto 93:e188a91d3eaa 832 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
Kojto 93:e188a91d3eaa 833 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
Kojto 93:e188a91d3eaa 834 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
Kojto 93:e188a91d3eaa 835 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
Kojto 93:e188a91d3eaa 836 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
Kojto 93:e188a91d3eaa 837 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
Kojto 93:e188a91d3eaa 838 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
Kojto 93:e188a91d3eaa 839 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
Kojto 93:e188a91d3eaa 840 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
Kojto 93:e188a91d3eaa 841 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
Kojto 93:e188a91d3eaa 842 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
Kojto 93:e188a91d3eaa 843 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
Kojto 93:e188a91d3eaa 844 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
Kojto 93:e188a91d3eaa 845 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
Kojto 93:e188a91d3eaa 846 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
Kojto 93:e188a91d3eaa 847 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
Kojto 93:e188a91d3eaa 848 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
Kojto 93:e188a91d3eaa 849 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
Kojto 93:e188a91d3eaa 850 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
Kojto 93:e188a91d3eaa 851 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
Kojto 93:e188a91d3eaa 852
Kojto 93:e188a91d3eaa 853 /******************* Bit definition for DMA_CCR register ********************/
Kojto 93:e188a91d3eaa 854 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
Kojto 93:e188a91d3eaa 855 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
Kojto 93:e188a91d3eaa 856 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
Kojto 93:e188a91d3eaa 857 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
Kojto 93:e188a91d3eaa 858 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
Kojto 93:e188a91d3eaa 859 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
Kojto 93:e188a91d3eaa 860 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
Kojto 93:e188a91d3eaa 861 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
Kojto 93:e188a91d3eaa 862
Kojto 93:e188a91d3eaa 863 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
Kojto 93:e188a91d3eaa 864 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 865 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 866
Kojto 93:e188a91d3eaa 867 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
Kojto 93:e188a91d3eaa 868 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 869 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 870
Kojto 93:e188a91d3eaa 871 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
Kojto 93:e188a91d3eaa 872 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 873 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 874
Kojto 93:e188a91d3eaa 875 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
Kojto 93:e188a91d3eaa 876
Kojto 93:e188a91d3eaa 877 /****************** Bit definition for DMA_CNDTR register *******************/
Kojto 93:e188a91d3eaa 878 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
Kojto 93:e188a91d3eaa 879
Kojto 93:e188a91d3eaa 880 /****************** Bit definition for DMA_CPAR register ********************/
Kojto 93:e188a91d3eaa 881 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
Kojto 93:e188a91d3eaa 882
Kojto 93:e188a91d3eaa 883 /****************** Bit definition for DMA_CMAR register ********************/
Kojto 93:e188a91d3eaa 884 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 93:e188a91d3eaa 885
Kojto 93:e188a91d3eaa 886 /******************************************************************************/
Kojto 93:e188a91d3eaa 887 /* */
Kojto 93:e188a91d3eaa 888 /* External Interrupt/Event Controller (EXTI) */
Kojto 93:e188a91d3eaa 889 /* */
Kojto 93:e188a91d3eaa 890 /******************************************************************************/
Kojto 93:e188a91d3eaa 891 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 93:e188a91d3eaa 892 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
Kojto 93:e188a91d3eaa 893 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
Kojto 93:e188a91d3eaa 894 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
Kojto 93:e188a91d3eaa 895 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
Kojto 93:e188a91d3eaa 896 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
Kojto 93:e188a91d3eaa 897 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
Kojto 93:e188a91d3eaa 898 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
Kojto 93:e188a91d3eaa 899 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
Kojto 93:e188a91d3eaa 900 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
Kojto 93:e188a91d3eaa 901 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
Kojto 93:e188a91d3eaa 902 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
Kojto 93:e188a91d3eaa 903 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
Kojto 93:e188a91d3eaa 904 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
Kojto 93:e188a91d3eaa 905 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
Kojto 93:e188a91d3eaa 906 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
Kojto 93:e188a91d3eaa 907 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
Kojto 93:e188a91d3eaa 908 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
Kojto 93:e188a91d3eaa 909 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
Kojto 93:e188a91d3eaa 910 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
Kojto 93:e188a91d3eaa 911 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
Kojto 93:e188a91d3eaa 912 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
Kojto 93:e188a91d3eaa 913
Kojto 93:e188a91d3eaa 914 /****************** Bit definition for EXTI_EMR register ********************/
Kojto 93:e188a91d3eaa 915 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Kojto 93:e188a91d3eaa 916 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
Kojto 93:e188a91d3eaa 917 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
Kojto 93:e188a91d3eaa 918 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
Kojto 93:e188a91d3eaa 919 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
Kojto 93:e188a91d3eaa 920 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
Kojto 93:e188a91d3eaa 921 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
Kojto 93:e188a91d3eaa 922 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
Kojto 93:e188a91d3eaa 923 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
Kojto 93:e188a91d3eaa 924 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
Kojto 93:e188a91d3eaa 925 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
Kojto 93:e188a91d3eaa 926 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
Kojto 93:e188a91d3eaa 927 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
Kojto 93:e188a91d3eaa 928 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
Kojto 93:e188a91d3eaa 929 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
Kojto 93:e188a91d3eaa 930 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
Kojto 93:e188a91d3eaa 931 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
Kojto 93:e188a91d3eaa 932 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
Kojto 93:e188a91d3eaa 933 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
Kojto 93:e188a91d3eaa 934 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
Kojto 93:e188a91d3eaa 935 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
Kojto 93:e188a91d3eaa 936
Kojto 93:e188a91d3eaa 937 /******************* Bit definition for EXTI_RTSR register ******************/
Kojto 93:e188a91d3eaa 938 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Kojto 93:e188a91d3eaa 939 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
Kojto 93:e188a91d3eaa 940 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
Kojto 93:e188a91d3eaa 941 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
Kojto 93:e188a91d3eaa 942 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
Kojto 93:e188a91d3eaa 943 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
Kojto 93:e188a91d3eaa 944 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
Kojto 93:e188a91d3eaa 945 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
Kojto 93:e188a91d3eaa 946 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
Kojto 93:e188a91d3eaa 947 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
Kojto 93:e188a91d3eaa 948 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
Kojto 93:e188a91d3eaa 949 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
Kojto 93:e188a91d3eaa 950 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
Kojto 93:e188a91d3eaa 951 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
Kojto 93:e188a91d3eaa 952 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
Kojto 93:e188a91d3eaa 953 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
Kojto 93:e188a91d3eaa 954 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
Kojto 93:e188a91d3eaa 955 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
Kojto 93:e188a91d3eaa 956 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
Kojto 93:e188a91d3eaa 957 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
Kojto 93:e188a91d3eaa 958 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
Kojto 93:e188a91d3eaa 959 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
Kojto 93:e188a91d3eaa 960
Kojto 93:e188a91d3eaa 961 /******************* Bit definition for EXTI_FTSR register *******************/
Kojto 93:e188a91d3eaa 962 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Kojto 93:e188a91d3eaa 963 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
Kojto 93:e188a91d3eaa 964 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
Kojto 93:e188a91d3eaa 965 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
Kojto 93:e188a91d3eaa 966 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
Kojto 93:e188a91d3eaa 967 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
Kojto 93:e188a91d3eaa 968 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
Kojto 93:e188a91d3eaa 969 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
Kojto 93:e188a91d3eaa 970 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
Kojto 93:e188a91d3eaa 971 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
Kojto 93:e188a91d3eaa 972 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
Kojto 93:e188a91d3eaa 973 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
Kojto 93:e188a91d3eaa 974 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
Kojto 93:e188a91d3eaa 975 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
Kojto 93:e188a91d3eaa 976 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
Kojto 93:e188a91d3eaa 977 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
Kojto 93:e188a91d3eaa 978 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
Kojto 93:e188a91d3eaa 979 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
Kojto 93:e188a91d3eaa 980 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
Kojto 93:e188a91d3eaa 981 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
Kojto 93:e188a91d3eaa 982 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
Kojto 93:e188a91d3eaa 983 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
Kojto 93:e188a91d3eaa 984
Kojto 93:e188a91d3eaa 985 /******************* Bit definition for EXTI_SWIER register *******************/
Kojto 93:e188a91d3eaa 986 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Kojto 93:e188a91d3eaa 987 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
Kojto 93:e188a91d3eaa 988 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
Kojto 93:e188a91d3eaa 989 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
Kojto 93:e188a91d3eaa 990 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
Kojto 93:e188a91d3eaa 991 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
Kojto 93:e188a91d3eaa 992 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
Kojto 93:e188a91d3eaa 993 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
Kojto 93:e188a91d3eaa 994 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
Kojto 93:e188a91d3eaa 995 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
Kojto 93:e188a91d3eaa 996 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
Kojto 93:e188a91d3eaa 997 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
Kojto 93:e188a91d3eaa 998 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
Kojto 93:e188a91d3eaa 999 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
Kojto 93:e188a91d3eaa 1000 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
Kojto 93:e188a91d3eaa 1001 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
Kojto 93:e188a91d3eaa 1002 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
Kojto 93:e188a91d3eaa 1003 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
Kojto 93:e188a91d3eaa 1004 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
Kojto 93:e188a91d3eaa 1005 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
Kojto 93:e188a91d3eaa 1006 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
Kojto 93:e188a91d3eaa 1007 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
Kojto 93:e188a91d3eaa 1008
Kojto 93:e188a91d3eaa 1009 /****************** Bit definition for EXTI_PR register *********************/
Kojto 93:e188a91d3eaa 1010 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
Kojto 93:e188a91d3eaa 1011 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
Kojto 93:e188a91d3eaa 1012 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
Kojto 93:e188a91d3eaa 1013 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
Kojto 93:e188a91d3eaa 1014 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
Kojto 93:e188a91d3eaa 1015 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
Kojto 93:e188a91d3eaa 1016 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
Kojto 93:e188a91d3eaa 1017 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
Kojto 93:e188a91d3eaa 1018 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
Kojto 93:e188a91d3eaa 1019 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
Kojto 93:e188a91d3eaa 1020 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
Kojto 93:e188a91d3eaa 1021 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
Kojto 93:e188a91d3eaa 1022 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
Kojto 93:e188a91d3eaa 1023 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
Kojto 93:e188a91d3eaa 1024 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
Kojto 93:e188a91d3eaa 1025 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
Kojto 93:e188a91d3eaa 1026 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
Kojto 93:e188a91d3eaa 1027 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
Kojto 93:e188a91d3eaa 1028 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
Kojto 93:e188a91d3eaa 1029 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
Kojto 93:e188a91d3eaa 1030 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
Kojto 93:e188a91d3eaa 1031 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
Kojto 93:e188a91d3eaa 1032
Kojto 93:e188a91d3eaa 1033 /******************************************************************************/
Kojto 93:e188a91d3eaa 1034 /* */
Kojto 93:e188a91d3eaa 1035 /* FLASH and Option Bytes Registers */
Kojto 93:e188a91d3eaa 1036 /* */
Kojto 93:e188a91d3eaa 1037 /******************************************************************************/
Kojto 93:e188a91d3eaa 1038
Kojto 93:e188a91d3eaa 1039 /******************* Bit definition for FLASH_ACR register ******************/
Kojto 93:e188a91d3eaa 1040 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
Kojto 93:e188a91d3eaa 1041
Kojto 93:e188a91d3eaa 1042 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
Kojto 93:e188a91d3eaa 1043 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
Kojto 93:e188a91d3eaa 1044
Kojto 93:e188a91d3eaa 1045 /****************** Bit definition for FLASH_KEYR register ******************/
Kojto 93:e188a91d3eaa 1046 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
Kojto 93:e188a91d3eaa 1047
Kojto 93:e188a91d3eaa 1048 /***************** Bit definition for FLASH_OPTKEYR register ****************/
Kojto 93:e188a91d3eaa 1049 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
Kojto 93:e188a91d3eaa 1050
Kojto 93:e188a91d3eaa 1051 /****************** FLASH Keys **********************************************/
Kojto 108:34e6b704fe68 1052 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
Kojto 108:34e6b704fe68 1053 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
Kojto 93:e188a91d3eaa 1054 to unlock the write access to the FPEC. */
Kojto 93:e188a91d3eaa 1055
Kojto 93:e188a91d3eaa 1056 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
Kojto 93:e188a91d3eaa 1057 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
Kojto 93:e188a91d3eaa 1058 unlock the write access to the option byte block */
Kojto 93:e188a91d3eaa 1059
Kojto 93:e188a91d3eaa 1060 /****************** Bit definition for FLASH_SR register *******************/
Kojto 93:e188a91d3eaa 1061 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
Kojto 93:e188a91d3eaa 1062 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
Kojto 93:e188a91d3eaa 1063 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
Kojto 93:e188a91d3eaa 1064 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
Kojto 93:e188a91d3eaa 1065 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
Kojto 93:e188a91d3eaa 1066
Kojto 93:e188a91d3eaa 1067 /******************* Bit definition for FLASH_CR register *******************/
Kojto 93:e188a91d3eaa 1068 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
Kojto 93:e188a91d3eaa 1069 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
Kojto 93:e188a91d3eaa 1070 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
Kojto 93:e188a91d3eaa 1071 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
Kojto 93:e188a91d3eaa 1072 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
Kojto 93:e188a91d3eaa 1073 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
Kojto 93:e188a91d3eaa 1074 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
Kojto 93:e188a91d3eaa 1075 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
Kojto 93:e188a91d3eaa 1076 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
Kojto 93:e188a91d3eaa 1077 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
Kojto 93:e188a91d3eaa 1078 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
Kojto 93:e188a91d3eaa 1079
Kojto 93:e188a91d3eaa 1080 /******************* Bit definition for FLASH_AR register *******************/
Kojto 93:e188a91d3eaa 1081 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
Kojto 93:e188a91d3eaa 1082
Kojto 93:e188a91d3eaa 1083 /****************** Bit definition for FLASH_OBR register *******************/
Kojto 93:e188a91d3eaa 1084 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
Kojto 93:e188a91d3eaa 1085 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
Kojto 93:e188a91d3eaa 1086 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
Kojto 93:e188a91d3eaa 1087
Kojto 108:34e6b704fe68 1088 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
Kojto 93:e188a91d3eaa 1089 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
Kojto 93:e188a91d3eaa 1090 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
Kojto 93:e188a91d3eaa 1091 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
Kojto 93:e188a91d3eaa 1092 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
Kojto 93:e188a91d3eaa 1093 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
Kojto 108:34e6b704fe68 1094 #define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
Kojto 93:e188a91d3eaa 1095
Kojto 93:e188a91d3eaa 1096 /* Old BOOT1 bit definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 1097 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
Kojto 93:e188a91d3eaa 1098
Kojto 93:e188a91d3eaa 1099 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 1100 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
Kojto 93:e188a91d3eaa 1101
Kojto 93:e188a91d3eaa 1102 /****************** Bit definition for FLASH_WRPR register ******************/
Kojto 93:e188a91d3eaa 1103 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
Kojto 93:e188a91d3eaa 1104
Kojto 93:e188a91d3eaa 1105 /*----------------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 1106
Kojto 93:e188a91d3eaa 1107 /****************** Bit definition for OB_RDP register **********************/
Kojto 93:e188a91d3eaa 1108 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
Kojto 93:e188a91d3eaa 1109 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
Kojto 93:e188a91d3eaa 1110
Kojto 93:e188a91d3eaa 1111 /****************** Bit definition for OB_USER register *********************/
Kojto 93:e188a91d3eaa 1112 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
Kojto 93:e188a91d3eaa 1113 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
Kojto 93:e188a91d3eaa 1114
Kojto 93:e188a91d3eaa 1115 /****************** Bit definition for OB_WRP0 register *********************/
Kojto 93:e188a91d3eaa 1116 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
Kojto 93:e188a91d3eaa 1117 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
Kojto 93:e188a91d3eaa 1118
Kojto 93:e188a91d3eaa 1119 /****************** Bit definition for OB_WRP1 register *********************/
Kojto 93:e188a91d3eaa 1120 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
Kojto 93:e188a91d3eaa 1121 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
Kojto 93:e188a91d3eaa 1122
Kojto 93:e188a91d3eaa 1123 /****************** Bit definition for OB_WRP2 register *********************/
Kojto 93:e188a91d3eaa 1124 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
Kojto 93:e188a91d3eaa 1125 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
Kojto 93:e188a91d3eaa 1126
Kojto 93:e188a91d3eaa 1127 /****************** Bit definition for OB_WRP3 register *********************/
Kojto 93:e188a91d3eaa 1128 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
Kojto 93:e188a91d3eaa 1129 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
Kojto 93:e188a91d3eaa 1130
Kojto 93:e188a91d3eaa 1131 /******************************************************************************/
Kojto 93:e188a91d3eaa 1132 /* */
Kojto 93:e188a91d3eaa 1133 /* General Purpose IOs (GPIO) */
Kojto 93:e188a91d3eaa 1134 /* */
Kojto 93:e188a91d3eaa 1135 /******************************************************************************/
Kojto 93:e188a91d3eaa 1136 /******************* Bit definition for GPIO_MODER register *****************/
Kojto 93:e188a91d3eaa 1137 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto 93:e188a91d3eaa 1138 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1139 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1140 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto 93:e188a91d3eaa 1141 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1142 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1143 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto 93:e188a91d3eaa 1144 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1145 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1146 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto 93:e188a91d3eaa 1147 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1148 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1149 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto 93:e188a91d3eaa 1150 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1151 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1152 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto 93:e188a91d3eaa 1153 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1154 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1155 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto 93:e188a91d3eaa 1156 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1157 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1158 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto 93:e188a91d3eaa 1159 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1160 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1161 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto 93:e188a91d3eaa 1162 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1163 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 1164 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto 93:e188a91d3eaa 1165 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1166 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1167 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 1168 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1169 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1170 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto 93:e188a91d3eaa 1171 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1172 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 1173 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto 93:e188a91d3eaa 1174 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1175 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1176 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto 93:e188a91d3eaa 1177 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1178 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1179 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto 93:e188a91d3eaa 1180 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 1181 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 1182 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto 93:e188a91d3eaa 1183 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 1184 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 1185
Kojto 93:e188a91d3eaa 1186 /****************** Bit definition for GPIO_OTYPER register *****************/
Kojto 93:e188a91d3eaa 1187 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1188 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1189 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1190 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1191 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1192 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1193 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1194 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1195 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1196 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1197 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1198 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1199 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1200 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1201 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1202 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1203
Kojto 93:e188a91d3eaa 1204 /**************** Bit definition for GPIO_OSPEEDR register ******************/
Kojto 93:e188a91d3eaa 1205 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
Kojto 93:e188a91d3eaa 1206 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1207 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1208 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto 93:e188a91d3eaa 1209 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1210 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1211 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
Kojto 93:e188a91d3eaa 1212 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1213 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1214 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto 93:e188a91d3eaa 1215 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1216 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1217 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
Kojto 93:e188a91d3eaa 1218 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1219 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1220 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto 93:e188a91d3eaa 1221 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1222 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1223 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
Kojto 93:e188a91d3eaa 1224 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1225 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1226 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto 93:e188a91d3eaa 1227 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1228 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1229 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
Kojto 93:e188a91d3eaa 1230 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1231 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 1232 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto 93:e188a91d3eaa 1233 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1234 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1235 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 1236 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1237 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1238 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto 93:e188a91d3eaa 1239 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1240 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 1241 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
Kojto 93:e188a91d3eaa 1242 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1243 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1244 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto 93:e188a91d3eaa 1245 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1246 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1247 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
Kojto 93:e188a91d3eaa 1248 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 1249 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 1250 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto 93:e188a91d3eaa 1251 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 1252 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 1253
Kojto 93:e188a91d3eaa 1254 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
Kojto 93:e188a91d3eaa 1255 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
Kojto 93:e188a91d3eaa 1256 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
Kojto 93:e188a91d3eaa 1257 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
Kojto 93:e188a91d3eaa 1258 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
Kojto 93:e188a91d3eaa 1259 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
Kojto 93:e188a91d3eaa 1260 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
Kojto 93:e188a91d3eaa 1261 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
Kojto 93:e188a91d3eaa 1262 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
Kojto 93:e188a91d3eaa 1263 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
Kojto 93:e188a91d3eaa 1264 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
Kojto 93:e188a91d3eaa 1265 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
Kojto 93:e188a91d3eaa 1266 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
Kojto 93:e188a91d3eaa 1267 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
Kojto 93:e188a91d3eaa 1268 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
Kojto 93:e188a91d3eaa 1269 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
Kojto 93:e188a91d3eaa 1270 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
Kojto 93:e188a91d3eaa 1271 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
Kojto 93:e188a91d3eaa 1272 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
Kojto 93:e188a91d3eaa 1273 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
Kojto 93:e188a91d3eaa 1274 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
Kojto 93:e188a91d3eaa 1275 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
Kojto 93:e188a91d3eaa 1276 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
Kojto 93:e188a91d3eaa 1277 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
Kojto 93:e188a91d3eaa 1278 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
Kojto 93:e188a91d3eaa 1279 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
Kojto 93:e188a91d3eaa 1280 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
Kojto 93:e188a91d3eaa 1281 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
Kojto 93:e188a91d3eaa 1282 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
Kojto 93:e188a91d3eaa 1283 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
Kojto 93:e188a91d3eaa 1284 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
Kojto 93:e188a91d3eaa 1285 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
Kojto 93:e188a91d3eaa 1286 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
Kojto 93:e188a91d3eaa 1287 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
Kojto 93:e188a91d3eaa 1288 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
Kojto 93:e188a91d3eaa 1289 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
Kojto 93:e188a91d3eaa 1290 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
Kojto 93:e188a91d3eaa 1291 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
Kojto 93:e188a91d3eaa 1292 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
Kojto 93:e188a91d3eaa 1293 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
Kojto 93:e188a91d3eaa 1294 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
Kojto 93:e188a91d3eaa 1295 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
Kojto 93:e188a91d3eaa 1296 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
Kojto 93:e188a91d3eaa 1297 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
Kojto 93:e188a91d3eaa 1298 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
Kojto 93:e188a91d3eaa 1299 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
Kojto 93:e188a91d3eaa 1300 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
Kojto 93:e188a91d3eaa 1301 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
Kojto 93:e188a91d3eaa 1302 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
Kojto 93:e188a91d3eaa 1303
Kojto 93:e188a91d3eaa 1304 /******************* Bit definition for GPIO_PUPDR register ******************/
Kojto 93:e188a91d3eaa 1305 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto 93:e188a91d3eaa 1306 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1307 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1308 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto 93:e188a91d3eaa 1309 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1310 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1311 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto 93:e188a91d3eaa 1312 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1313 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1314 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto 93:e188a91d3eaa 1315 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1316 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1317 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto 93:e188a91d3eaa 1318 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1319 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1320 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto 93:e188a91d3eaa 1321 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1322 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1323 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto 93:e188a91d3eaa 1324 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1325 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1326 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto 93:e188a91d3eaa 1327 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1328 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1329 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto 93:e188a91d3eaa 1330 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1331 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 1332 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto 93:e188a91d3eaa 1333 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1334 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1335 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 1336 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1337 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1338 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto 93:e188a91d3eaa 1339 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1340 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 1341 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto 93:e188a91d3eaa 1342 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1343 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1344 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto 93:e188a91d3eaa 1345 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1346 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1347 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto 93:e188a91d3eaa 1348 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 1349 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 1350 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto 93:e188a91d3eaa 1351 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 1352 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 1353
Kojto 93:e188a91d3eaa 1354 /******************* Bit definition for GPIO_IDR register *******************/
Kojto 93:e188a91d3eaa 1355 #define GPIO_IDR_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1356 #define GPIO_IDR_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1357 #define GPIO_IDR_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1358 #define GPIO_IDR_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1359 #define GPIO_IDR_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1360 #define GPIO_IDR_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1361 #define GPIO_IDR_6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1362 #define GPIO_IDR_7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1363 #define GPIO_IDR_8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1364 #define GPIO_IDR_9 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1365 #define GPIO_IDR_10 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1366 #define GPIO_IDR_11 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1367 #define GPIO_IDR_12 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1368 #define GPIO_IDR_13 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1369 #define GPIO_IDR_14 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1370 #define GPIO_IDR_15 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1371
Kojto 93:e188a91d3eaa 1372 /****************** Bit definition for GPIO_ODR register ********************/
Kojto 93:e188a91d3eaa 1373 #define GPIO_ODR_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1374 #define GPIO_ODR_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1375 #define GPIO_ODR_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1376 #define GPIO_ODR_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1377 #define GPIO_ODR_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1378 #define GPIO_ODR_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1379 #define GPIO_ODR_6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1380 #define GPIO_ODR_7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1381 #define GPIO_ODR_8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1382 #define GPIO_ODR_9 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1383 #define GPIO_ODR_10 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1384 #define GPIO_ODR_11 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1385 #define GPIO_ODR_12 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1386 #define GPIO_ODR_13 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1387 #define GPIO_ODR_14 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1388 #define GPIO_ODR_15 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1389
Kojto 93:e188a91d3eaa 1390 /****************** Bit definition for GPIO_BSRR register ********************/
Kojto 93:e188a91d3eaa 1391 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1392 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1393 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1394 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1395 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1396 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1397 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1398 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1399 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1400 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1401 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1402 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1403 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1404 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1405 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1406 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1407 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1408 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 1409 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1410 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1411 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1412 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1413 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1414 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 1415 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1416 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1417 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1418 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1419 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 1420 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 1421 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 1422 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 1423
Kojto 93:e188a91d3eaa 1424 /****************** Bit definition for GPIO_LCKR register ********************/
Kojto 93:e188a91d3eaa 1425 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1426 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1427 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1428 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1429 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1430 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1431 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1432 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1433 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1434 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1435 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1436 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1437 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1438 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1439 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1440 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1441 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1442
Kojto 93:e188a91d3eaa 1443 /****************** Bit definition for GPIO_AFRL register ********************/
Kojto 93:e188a91d3eaa 1444 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 1445 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
Kojto 93:e188a91d3eaa 1446 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 1447 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
Kojto 93:e188a91d3eaa 1448 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
Kojto 93:e188a91d3eaa 1449 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
Kojto 93:e188a91d3eaa 1450 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
Kojto 93:e188a91d3eaa 1451 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
Kojto 93:e188a91d3eaa 1452
Kojto 93:e188a91d3eaa 1453 /****************** Bit definition for GPIO_AFRH register ********************/
Kojto 93:e188a91d3eaa 1454 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 1455 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
Kojto 93:e188a91d3eaa 1456 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 1457 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
Kojto 93:e188a91d3eaa 1458 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
Kojto 93:e188a91d3eaa 1459 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
Kojto 93:e188a91d3eaa 1460 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
Kojto 93:e188a91d3eaa 1461 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
Kojto 93:e188a91d3eaa 1462
Kojto 93:e188a91d3eaa 1463 /****************** Bit definition for GPIO_BRR register *********************/
Kojto 93:e188a91d3eaa 1464 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1465 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1466 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1467 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1468 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1469 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1470 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1471 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1472 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1473 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1474 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1475 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1476 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1477 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1478 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1479 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1480
Kojto 93:e188a91d3eaa 1481 /******************************************************************************/
Kojto 93:e188a91d3eaa 1482 /* */
Kojto 93:e188a91d3eaa 1483 /* Inter-integrated Circuit Interface (I2C) */
Kojto 93:e188a91d3eaa 1484 /* */
Kojto 93:e188a91d3eaa 1485 /******************************************************************************/
Kojto 93:e188a91d3eaa 1486
Kojto 93:e188a91d3eaa 1487 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 93:e188a91d3eaa 1488 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
Kojto 93:e188a91d3eaa 1489 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
Kojto 93:e188a91d3eaa 1490 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
Kojto 93:e188a91d3eaa 1491 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
Kojto 93:e188a91d3eaa 1492 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
Kojto 93:e188a91d3eaa 1493 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
Kojto 93:e188a91d3eaa 1494 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
Kojto 93:e188a91d3eaa 1495 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
Kojto 93:e188a91d3eaa 1496 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
Kojto 93:e188a91d3eaa 1497 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
Kojto 93:e188a91d3eaa 1498 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
Kojto 93:e188a91d3eaa 1499 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
Kojto 93:e188a91d3eaa 1500 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
Kojto 93:e188a91d3eaa 1501 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
Kojto 93:e188a91d3eaa 1502 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
Kojto 93:e188a91d3eaa 1503 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
Kojto 93:e188a91d3eaa 1504 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
Kojto 93:e188a91d3eaa 1505 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
Kojto 93:e188a91d3eaa 1506 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
Kojto 93:e188a91d3eaa 1507 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
Kojto 93:e188a91d3eaa 1508
Kojto 93:e188a91d3eaa 1509 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 93:e188a91d3eaa 1510 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
Kojto 93:e188a91d3eaa 1511 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
Kojto 93:e188a91d3eaa 1512 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
Kojto 93:e188a91d3eaa 1513 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
Kojto 93:e188a91d3eaa 1514 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
Kojto 93:e188a91d3eaa 1515 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
Kojto 93:e188a91d3eaa 1516 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
Kojto 93:e188a91d3eaa 1517 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
Kojto 93:e188a91d3eaa 1518 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
Kojto 93:e188a91d3eaa 1519 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
Kojto 93:e188a91d3eaa 1520 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
Kojto 93:e188a91d3eaa 1521
Kojto 93:e188a91d3eaa 1522 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 93:e188a91d3eaa 1523 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
Kojto 93:e188a91d3eaa 1524 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
Kojto 93:e188a91d3eaa 1525 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
Kojto 93:e188a91d3eaa 1526
Kojto 93:e188a91d3eaa 1527 /******************* Bit definition for I2C_OAR2 register ******************/
Kojto 93:e188a91d3eaa 1528 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
Kojto 93:e188a91d3eaa 1529 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
Kojto 93:e188a91d3eaa 1530 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
Kojto 93:e188a91d3eaa 1531
Kojto 93:e188a91d3eaa 1532 /******************* Bit definition for I2C_TIMINGR register ****************/
Kojto 93:e188a91d3eaa 1533 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
Kojto 93:e188a91d3eaa 1534 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
Kojto 93:e188a91d3eaa 1535 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
Kojto 93:e188a91d3eaa 1536 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
Kojto 93:e188a91d3eaa 1537 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
Kojto 93:e188a91d3eaa 1538
Kojto 93:e188a91d3eaa 1539 /******************* Bit definition for I2C_TIMEOUTR register ****************/
Kojto 93:e188a91d3eaa 1540 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
Kojto 93:e188a91d3eaa 1541 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
Kojto 93:e188a91d3eaa 1542 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
Kojto 93:e188a91d3eaa 1543 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
Kojto 93:e188a91d3eaa 1544 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
Kojto 93:e188a91d3eaa 1545
Kojto 93:e188a91d3eaa 1546 /****************** Bit definition for I2C_ISR register ********************/
Kojto 93:e188a91d3eaa 1547 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
Kojto 93:e188a91d3eaa 1548 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
Kojto 93:e188a91d3eaa 1549 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
Kojto 93:e188a91d3eaa 1550 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
Kojto 93:e188a91d3eaa 1551 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
Kojto 93:e188a91d3eaa 1552 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
Kojto 93:e188a91d3eaa 1553 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
Kojto 93:e188a91d3eaa 1554 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
Kojto 93:e188a91d3eaa 1555 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
Kojto 93:e188a91d3eaa 1556 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
Kojto 93:e188a91d3eaa 1557 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
Kojto 93:e188a91d3eaa 1558 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
Kojto 93:e188a91d3eaa 1559 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
Kojto 93:e188a91d3eaa 1560 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
Kojto 93:e188a91d3eaa 1561 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
Kojto 93:e188a91d3eaa 1562 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
Kojto 93:e188a91d3eaa 1563 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
Kojto 93:e188a91d3eaa 1564
Kojto 93:e188a91d3eaa 1565 /****************** Bit definition for I2C_ICR register ********************/
Kojto 93:e188a91d3eaa 1566 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
Kojto 93:e188a91d3eaa 1567 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
Kojto 93:e188a91d3eaa 1568 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
Kojto 93:e188a91d3eaa 1569 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
Kojto 93:e188a91d3eaa 1570 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
Kojto 93:e188a91d3eaa 1571 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
Kojto 93:e188a91d3eaa 1572 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
Kojto 93:e188a91d3eaa 1573 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
Kojto 93:e188a91d3eaa 1574 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
Kojto 93:e188a91d3eaa 1575
Kojto 93:e188a91d3eaa 1576 /****************** Bit definition for I2C_PECR register *******************/
Kojto 93:e188a91d3eaa 1577 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
Kojto 93:e188a91d3eaa 1578
Kojto 93:e188a91d3eaa 1579 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 93:e188a91d3eaa 1580 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
Kojto 93:e188a91d3eaa 1581
Kojto 93:e188a91d3eaa 1582 /****************** Bit definition for I2C_TXDR register *******************/
Kojto 93:e188a91d3eaa 1583 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
Kojto 93:e188a91d3eaa 1584
Kojto 93:e188a91d3eaa 1585 /*****************************************************************************/
Kojto 93:e188a91d3eaa 1586 /* */
Kojto 93:e188a91d3eaa 1587 /* Independent WATCHDOG (IWDG) */
Kojto 93:e188a91d3eaa 1588 /* */
Kojto 93:e188a91d3eaa 1589 /*****************************************************************************/
Kojto 93:e188a91d3eaa 1590 /******************* Bit definition for IWDG_KR register *******************/
Kojto 93:e188a91d3eaa 1591 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
Kojto 93:e188a91d3eaa 1592
Kojto 93:e188a91d3eaa 1593 /******************* Bit definition for IWDG_PR register *******************/
Kojto 93:e188a91d3eaa 1594 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
Kojto 93:e188a91d3eaa 1595 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 1596 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 1597 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 1598
Kojto 93:e188a91d3eaa 1599 /******************* Bit definition for IWDG_RLR register ******************/
Kojto 93:e188a91d3eaa 1600 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
Kojto 93:e188a91d3eaa 1601
Kojto 93:e188a91d3eaa 1602 /******************* Bit definition for IWDG_SR register *******************/
Kojto 93:e188a91d3eaa 1603 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
Kojto 93:e188a91d3eaa 1604 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
Kojto 93:e188a91d3eaa 1605 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
Kojto 93:e188a91d3eaa 1606
Kojto 93:e188a91d3eaa 1607 /******************* Bit definition for IWDG_KR register *******************/
Kojto 93:e188a91d3eaa 1608 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
Kojto 93:e188a91d3eaa 1609
Kojto 93:e188a91d3eaa 1610 /*****************************************************************************/
Kojto 93:e188a91d3eaa 1611 /* */
Kojto 93:e188a91d3eaa 1612 /* Power Control (PWR) */
Kojto 93:e188a91d3eaa 1613 /* */
Kojto 93:e188a91d3eaa 1614 /*****************************************************************************/
Kojto 93:e188a91d3eaa 1615
Kojto 93:e188a91d3eaa 1616 /******************** Bit definition for PWR_CR register *******************/
Kojto 93:e188a91d3eaa 1617 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
Kojto 93:e188a91d3eaa 1618 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
Kojto 93:e188a91d3eaa 1619 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
Kojto 93:e188a91d3eaa 1620 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
Kojto 93:e188a91d3eaa 1621 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
Kojto 93:e188a91d3eaa 1622
Kojto 93:e188a91d3eaa 1623 /******************* Bit definition for PWR_CSR register *******************/
Kojto 93:e188a91d3eaa 1624 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
Kojto 93:e188a91d3eaa 1625 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
Kojto 93:e188a91d3eaa 1626
Kojto 93:e188a91d3eaa 1627 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
Kojto 93:e188a91d3eaa 1628 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
Kojto 93:e188a91d3eaa 1629 #define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
Kojto 93:e188a91d3eaa 1630 #define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
Kojto 93:e188a91d3eaa 1631 #define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
Kojto 93:e188a91d3eaa 1632 #define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
Kojto 93:e188a91d3eaa 1633
Kojto 93:e188a91d3eaa 1634 /*****************************************************************************/
Kojto 93:e188a91d3eaa 1635 /* */
Kojto 93:e188a91d3eaa 1636 /* Reset and Clock Control */
Kojto 93:e188a91d3eaa 1637 /* */
Kojto 93:e188a91d3eaa 1638 /*****************************************************************************/
Kojto 93:e188a91d3eaa 1639
Kojto 93:e188a91d3eaa 1640 /******************** Bit definition for RCC_CR register *******************/
Kojto 93:e188a91d3eaa 1641 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
Kojto 93:e188a91d3eaa 1642 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
Kojto 93:e188a91d3eaa 1643
Kojto 93:e188a91d3eaa 1644 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
Kojto 93:e188a91d3eaa 1645 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1646 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1647 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1648 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1649 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1650
Kojto 93:e188a91d3eaa 1651 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
Kojto 93:e188a91d3eaa 1652 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1653 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1654 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1655 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1656 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1657 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 1658 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 1659 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 93:e188a91d3eaa 1660
Kojto 93:e188a91d3eaa 1661 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
Kojto 93:e188a91d3eaa 1662 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
Kojto 93:e188a91d3eaa 1663 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
Kojto 93:e188a91d3eaa 1664 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
Kojto 93:e188a91d3eaa 1665 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
Kojto 93:e188a91d3eaa 1666 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
Kojto 93:e188a91d3eaa 1667
Kojto 93:e188a91d3eaa 1668 /******************** Bit definition for RCC_CFGR register *****************/
Kojto 93:e188a91d3eaa 1669 /*!< SW configuration */
Kojto 93:e188a91d3eaa 1670 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
Kojto 93:e188a91d3eaa 1671 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 1672 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 1673
Kojto 93:e188a91d3eaa 1674 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
Kojto 93:e188a91d3eaa 1675 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
Kojto 93:e188a91d3eaa 1676 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
Kojto 93:e188a91d3eaa 1677
Kojto 93:e188a91d3eaa 1678 /*!< SWS configuration */
Kojto 93:e188a91d3eaa 1679 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 93:e188a91d3eaa 1680 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 1681 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 1682
Kojto 93:e188a91d3eaa 1683 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
Kojto 93:e188a91d3eaa 1684 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
Kojto 93:e188a91d3eaa 1685 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
Kojto 93:e188a91d3eaa 1686
Kojto 93:e188a91d3eaa 1687 /*!< HPRE configuration */
Kojto 93:e188a91d3eaa 1688 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 93:e188a91d3eaa 1689 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 1690 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 1691 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 1692 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Kojto 93:e188a91d3eaa 1693
Kojto 93:e188a91d3eaa 1694 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
Kojto 93:e188a91d3eaa 1695 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
Kojto 93:e188a91d3eaa 1696 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
Kojto 93:e188a91d3eaa 1697 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
Kojto 93:e188a91d3eaa 1698 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
Kojto 93:e188a91d3eaa 1699 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
Kojto 93:e188a91d3eaa 1700 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
Kojto 93:e188a91d3eaa 1701 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
Kojto 93:e188a91d3eaa 1702 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
Kojto 93:e188a91d3eaa 1703
Kojto 93:e188a91d3eaa 1704 /*!< PPRE configuration */
Kojto 93:e188a91d3eaa 1705 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
Kojto 93:e188a91d3eaa 1706 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 1707 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 1708 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 1709
Kojto 93:e188a91d3eaa 1710 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 93:e188a91d3eaa 1711 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
Kojto 93:e188a91d3eaa 1712 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
Kojto 93:e188a91d3eaa 1713 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
Kojto 93:e188a91d3eaa 1714 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
Kojto 93:e188a91d3eaa 1715
Kojto 93:e188a91d3eaa 1716 /*!< ADCPPRE configuration */
Kojto 93:e188a91d3eaa 1717 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
Kojto 93:e188a91d3eaa 1718
Kojto 93:e188a91d3eaa 1719 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
Kojto 93:e188a91d3eaa 1720 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
Kojto 93:e188a91d3eaa 1721
Kojto 93:e188a91d3eaa 1722 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
Kojto 93:e188a91d3eaa 1723 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
Kojto 93:e188a91d3eaa 1724 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
Kojto 93:e188a91d3eaa 1725 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
Kojto 93:e188a91d3eaa 1726
Kojto 93:e188a91d3eaa 1727 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
Kojto 93:e188a91d3eaa 1728 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
Kojto 93:e188a91d3eaa 1729 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
Kojto 93:e188a91d3eaa 1730
Kojto 93:e188a91d3eaa 1731 /*!< PLLMUL configuration */
Kojto 93:e188a91d3eaa 1732 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
Kojto 93:e188a91d3eaa 1733 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 1734 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 1735 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 1736 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
Kojto 93:e188a91d3eaa 1737
Kojto 93:e188a91d3eaa 1738 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
Kojto 93:e188a91d3eaa 1739 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
Kojto 93:e188a91d3eaa 1740 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
Kojto 93:e188a91d3eaa 1741 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
Kojto 93:e188a91d3eaa 1742 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
Kojto 93:e188a91d3eaa 1743 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
Kojto 93:e188a91d3eaa 1744 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
Kojto 93:e188a91d3eaa 1745 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
Kojto 93:e188a91d3eaa 1746 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
Kojto 93:e188a91d3eaa 1747 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
Kojto 93:e188a91d3eaa 1748 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
Kojto 93:e188a91d3eaa 1749 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
Kojto 93:e188a91d3eaa 1750 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
Kojto 93:e188a91d3eaa 1751 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
Kojto 93:e188a91d3eaa 1752 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
Kojto 93:e188a91d3eaa 1753
Kojto 93:e188a91d3eaa 1754 /*!< USB configuration */
Kojto 93:e188a91d3eaa 1755 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
Kojto 93:e188a91d3eaa 1756
Kojto 93:e188a91d3eaa 1757 /*!< MCO configuration */
Kojto 93:e188a91d3eaa 1758 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
Kojto 93:e188a91d3eaa 1759 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 1760 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 1761 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 1762 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
Kojto 93:e188a91d3eaa 1763
Kojto 93:e188a91d3eaa 1764 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Kojto 93:e188a91d3eaa 1765 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
Kojto 93:e188a91d3eaa 1766 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
Kojto 93:e188a91d3eaa 1767 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
Kojto 93:e188a91d3eaa 1768 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
Kojto 93:e188a91d3eaa 1769 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
Kojto 93:e188a91d3eaa 1770 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
Kojto 93:e188a91d3eaa 1771 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
Kojto 93:e188a91d3eaa 1772
Kojto 93:e188a91d3eaa 1773 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
Kojto 93:e188a91d3eaa 1774 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
Kojto 93:e188a91d3eaa 1775 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
Kojto 93:e188a91d3eaa 1776 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
Kojto 93:e188a91d3eaa 1777 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
Kojto 93:e188a91d3eaa 1778 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
Kojto 93:e188a91d3eaa 1779 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
Kojto 93:e188a91d3eaa 1780 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
Kojto 93:e188a91d3eaa 1781 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
Kojto 93:e188a91d3eaa 1782
Kojto 93:e188a91d3eaa 1783 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
Kojto 93:e188a91d3eaa 1784
Kojto 93:e188a91d3eaa 1785 /*!<****************** Bit definition for RCC_CIR register *****************/
Kojto 93:e188a91d3eaa 1786 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
Kojto 93:e188a91d3eaa 1787 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
Kojto 93:e188a91d3eaa 1788 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
Kojto 93:e188a91d3eaa 1789 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
Kojto 93:e188a91d3eaa 1790 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
Kojto 93:e188a91d3eaa 1791 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
Kojto 93:e188a91d3eaa 1792 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
Kojto 93:e188a91d3eaa 1793 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
Kojto 93:e188a91d3eaa 1794 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
Kojto 93:e188a91d3eaa 1795 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
Kojto 93:e188a91d3eaa 1796 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
Kojto 93:e188a91d3eaa 1797 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
Kojto 93:e188a91d3eaa 1798 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
Kojto 93:e188a91d3eaa 1799 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
Kojto 93:e188a91d3eaa 1800 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
Kojto 93:e188a91d3eaa 1801 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
Kojto 93:e188a91d3eaa 1802 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
Kojto 93:e188a91d3eaa 1803 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
Kojto 93:e188a91d3eaa 1804 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
Kojto 93:e188a91d3eaa 1805 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
Kojto 93:e188a91d3eaa 1806
Kojto 93:e188a91d3eaa 1807 /***************** Bit definition for RCC_APB2RSTR register ****************/
Kojto 93:e188a91d3eaa 1808 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
Kojto 93:e188a91d3eaa 1809 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
Kojto 93:e188a91d3eaa 1810 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
Kojto 93:e188a91d3eaa 1811 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
Kojto 93:e188a91d3eaa 1812 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
Kojto 93:e188a91d3eaa 1813 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
Kojto 93:e188a91d3eaa 1814 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
Kojto 93:e188a91d3eaa 1815 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
Kojto 93:e188a91d3eaa 1816 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
Kojto 93:e188a91d3eaa 1817
Kojto 93:e188a91d3eaa 1818 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
Kojto 93:e188a91d3eaa 1819 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
Kojto 93:e188a91d3eaa 1820
Kojto 93:e188a91d3eaa 1821 /***************** Bit definition for RCC_APB1RSTR register ****************/
Kojto 93:e188a91d3eaa 1822 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
Kojto 93:e188a91d3eaa 1823 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
Kojto 93:e188a91d3eaa 1824 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
Kojto 93:e188a91d3eaa 1825 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
Kojto 93:e188a91d3eaa 1826 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
Kojto 93:e188a91d3eaa 1827 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
Kojto 93:e188a91d3eaa 1828 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
Kojto 93:e188a91d3eaa 1829 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
Kojto 93:e188a91d3eaa 1830 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
Kojto 93:e188a91d3eaa 1831 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
Kojto 93:e188a91d3eaa 1832 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
Kojto 93:e188a91d3eaa 1833 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
Kojto 93:e188a91d3eaa 1834 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
Kojto 93:e188a91d3eaa 1835
Kojto 93:e188a91d3eaa 1836 /****************** Bit definition for RCC_AHBENR register *****************/
Kojto 93:e188a91d3eaa 1837 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
Kojto 93:e188a91d3eaa 1838 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
Kojto 93:e188a91d3eaa 1839 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
Kojto 93:e188a91d3eaa 1840 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
Kojto 93:e188a91d3eaa 1841 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
Kojto 93:e188a91d3eaa 1842 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
Kojto 93:e188a91d3eaa 1843 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
Kojto 93:e188a91d3eaa 1844 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
Kojto 93:e188a91d3eaa 1845 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
Kojto 93:e188a91d3eaa 1846
Kojto 93:e188a91d3eaa 1847 /* Old Bit definition maintained for legacy purpose */
Kojto 93:e188a91d3eaa 1848 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
Kojto 93:e188a91d3eaa 1849
Kojto 93:e188a91d3eaa 1850 /***************** Bit definition for RCC_APB2ENR register *****************/
Kojto 93:e188a91d3eaa 1851 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
Kojto 93:e188a91d3eaa 1852 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
Kojto 93:e188a91d3eaa 1853 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
Kojto 93:e188a91d3eaa 1854 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
Kojto 93:e188a91d3eaa 1855 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
Kojto 93:e188a91d3eaa 1856 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
Kojto 93:e188a91d3eaa 1857 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
Kojto 93:e188a91d3eaa 1858 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
Kojto 93:e188a91d3eaa 1859 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
Kojto 93:e188a91d3eaa 1860
Kojto 93:e188a91d3eaa 1861 /* Old Bit definition maintained for legacy purpose */
Kojto 93:e188a91d3eaa 1862 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
Kojto 93:e188a91d3eaa 1863 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
Kojto 93:e188a91d3eaa 1864
Kojto 93:e188a91d3eaa 1865 /***************** Bit definition for RCC_APB1ENR register *****************/
Kojto 93:e188a91d3eaa 1866 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
Kojto 93:e188a91d3eaa 1867 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
Kojto 93:e188a91d3eaa 1868 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
Kojto 93:e188a91d3eaa 1869 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
Kojto 93:e188a91d3eaa 1870 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
Kojto 93:e188a91d3eaa 1871 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
Kojto 93:e188a91d3eaa 1872 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
Kojto 93:e188a91d3eaa 1873 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
Kojto 93:e188a91d3eaa 1874 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
Kojto 93:e188a91d3eaa 1875 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
Kojto 93:e188a91d3eaa 1876 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
Kojto 93:e188a91d3eaa 1877 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
Kojto 93:e188a91d3eaa 1878 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
Kojto 93:e188a91d3eaa 1879
Kojto 93:e188a91d3eaa 1880 /******************* Bit definition for RCC_BDCR register ******************/
Kojto 93:e188a91d3eaa 1881 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
Kojto 93:e188a91d3eaa 1882 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
Kojto 93:e188a91d3eaa 1883 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
Kojto 93:e188a91d3eaa 1884
Kojto 93:e188a91d3eaa 1885 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
Kojto 93:e188a91d3eaa 1886 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 1887 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 1888
Kojto 93:e188a91d3eaa 1889 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
Kojto 93:e188a91d3eaa 1890 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 1891 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 1892
Kojto 93:e188a91d3eaa 1893 /*!< RTC configuration */
Kojto 93:e188a91d3eaa 1894 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Kojto 93:e188a91d3eaa 1895 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
Kojto 93:e188a91d3eaa 1896 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
Kojto 93:e188a91d3eaa 1897 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
Kojto 93:e188a91d3eaa 1898
Kojto 93:e188a91d3eaa 1899 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
Kojto 93:e188a91d3eaa 1900 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
Kojto 93:e188a91d3eaa 1901
Kojto 93:e188a91d3eaa 1902 /******************* Bit definition for RCC_CSR register *******************/
Kojto 93:e188a91d3eaa 1903 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
Kojto 93:e188a91d3eaa 1904 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
Kojto 93:e188a91d3eaa 1905 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
Kojto 93:e188a91d3eaa 1906 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
Kojto 93:e188a91d3eaa 1907 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
Kojto 93:e188a91d3eaa 1908 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
Kojto 93:e188a91d3eaa 1909 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
Kojto 93:e188a91d3eaa 1910 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
Kojto 93:e188a91d3eaa 1911 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
Kojto 93:e188a91d3eaa 1912 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
Kojto 93:e188a91d3eaa 1913 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
Kojto 93:e188a91d3eaa 1914
Kojto 93:e188a91d3eaa 1915 /* Old Bit definition maintained for legacy purpose */
Kojto 93:e188a91d3eaa 1916 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
Kojto 93:e188a91d3eaa 1917
Kojto 93:e188a91d3eaa 1918 /******************* Bit definition for RCC_AHBRSTR register ***************/
Kojto 93:e188a91d3eaa 1919 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
Kojto 93:e188a91d3eaa 1920 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
Kojto 93:e188a91d3eaa 1921 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
Kojto 93:e188a91d3eaa 1922 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
Kojto 93:e188a91d3eaa 1923 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
Kojto 93:e188a91d3eaa 1924
Kojto 93:e188a91d3eaa 1925 /******************* Bit definition for RCC_CFGR2 register *****************/
Kojto 93:e188a91d3eaa 1926 /*!< PREDIV configuration */
Kojto 93:e188a91d3eaa 1927 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
Kojto 93:e188a91d3eaa 1928 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 1929 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 1930 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 1931 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 93:e188a91d3eaa 1932
Kojto 93:e188a91d3eaa 1933 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
Kojto 93:e188a91d3eaa 1934 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
Kojto 93:e188a91d3eaa 1935 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
Kojto 93:e188a91d3eaa 1936 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
Kojto 93:e188a91d3eaa 1937 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
Kojto 93:e188a91d3eaa 1938 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
Kojto 93:e188a91d3eaa 1939 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
Kojto 93:e188a91d3eaa 1940 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
Kojto 93:e188a91d3eaa 1941 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
Kojto 93:e188a91d3eaa 1942 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
Kojto 93:e188a91d3eaa 1943 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
Kojto 93:e188a91d3eaa 1944 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
Kojto 93:e188a91d3eaa 1945 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
Kojto 93:e188a91d3eaa 1946 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
Kojto 93:e188a91d3eaa 1947 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
Kojto 93:e188a91d3eaa 1948 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
Kojto 93:e188a91d3eaa 1949
Kojto 93:e188a91d3eaa 1950 /******************* Bit definition for RCC_CFGR3 register *****************/
Kojto 93:e188a91d3eaa 1951 /*!< USART1 Clock source selection */
Kojto 93:e188a91d3eaa 1952 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
Kojto 93:e188a91d3eaa 1953 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 1954 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 1955
Kojto 93:e188a91d3eaa 1956 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
Kojto 93:e188a91d3eaa 1957 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
Kojto 93:e188a91d3eaa 1958 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
Kojto 93:e188a91d3eaa 1959 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
Kojto 93:e188a91d3eaa 1960
Kojto 93:e188a91d3eaa 1961 /*!< I2C1 Clock source selection */
Kojto 93:e188a91d3eaa 1962 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
Kojto 93:e188a91d3eaa 1963
Kojto 93:e188a91d3eaa 1964 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
Kojto 93:e188a91d3eaa 1965 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
Kojto 93:e188a91d3eaa 1966
Kojto 93:e188a91d3eaa 1967 /*!< USB Clock source selection */
Kojto 93:e188a91d3eaa 1968 #define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
Kojto 93:e188a91d3eaa 1969
Kojto 93:e188a91d3eaa 1970 #define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /*!< PLLCLK selected as USB clock source */
Kojto 93:e188a91d3eaa 1971
Kojto 93:e188a91d3eaa 1972 /******************* Bit definition for RCC_CR2 register *******************/
Kojto 93:e188a91d3eaa 1973 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
Kojto 93:e188a91d3eaa 1974 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
Kojto 93:e188a91d3eaa 1975 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
Kojto 93:e188a91d3eaa 1976 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
Kojto 93:e188a91d3eaa 1977 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
Kojto 93:e188a91d3eaa 1978
Kojto 93:e188a91d3eaa 1979 /*****************************************************************************/
Kojto 93:e188a91d3eaa 1980 /* */
Kojto 93:e188a91d3eaa 1981 /* Real-Time Clock (RTC) */
Kojto 93:e188a91d3eaa 1982 /* */
Kojto 93:e188a91d3eaa 1983 /*****************************************************************************/
Kojto 93:e188a91d3eaa 1984 /******************** Bits definition for RTC_TR register ******************/
Kojto 93:e188a91d3eaa 1985 #define RTC_TR_PM ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1986 #define RTC_TR_HT ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 1987 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1988 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1989 #define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto 93:e188a91d3eaa 1990 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1991 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 1992 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1993 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1994 #define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto 93:e188a91d3eaa 1995 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1996 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1997 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1998 #define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 1999 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2000 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2001 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2002 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2003 #define RTC_TR_ST ((uint32_t)0x00000070)
Kojto 93:e188a91d3eaa 2004 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2005 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2006 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2007 #define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 2008 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2009 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2010 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2011 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2012
Kojto 93:e188a91d3eaa 2013 /******************** Bits definition for RTC_DR register ******************/
Kojto 93:e188a91d3eaa 2014 #define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto 93:e188a91d3eaa 2015 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2016 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2017 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2018 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 2019 #define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto 93:e188a91d3eaa 2020 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2021 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2022 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2023 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2024 #define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto 93:e188a91d3eaa 2025 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2026 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2027 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2028 #define RTC_DR_MT ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2029 #define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 2030 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2031 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2032 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2033 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2034 #define RTC_DR_DT ((uint32_t)0x00000030)
Kojto 93:e188a91d3eaa 2035 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2036 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2037 #define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 2038 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2039 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2040 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2041 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2042
Kojto 93:e188a91d3eaa 2043 /******************** Bits definition for RTC_CR register ******************/
Kojto 93:e188a91d3eaa 2044 #define RTC_CR_COE ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 2045 #define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto 93:e188a91d3eaa 2046 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2047 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2048 #define RTC_CR_POL ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2049 #define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2050 #define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2051 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2052 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2053 #define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2054 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2055 #define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto 108:34e6b704fe68 2056 #define RTC_CR_WUTE ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2057 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2058 #define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2059 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2060 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2061 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto 108:34e6b704fe68 2062 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
Kojto 108:34e6b704fe68 2063 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
Kojto 108:34e6b704fe68 2064 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
Kojto 108:34e6b704fe68 2065 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2066
Kojto 93:e188a91d3eaa 2067 /******************** Bits definition for RTC_ISR register *****************/
Kojto 93:e188a91d3eaa 2068 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2069 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2070 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2071 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2072 #define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto 108:34e6b704fe68 2073 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2074 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2075 #define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2076 #define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2077 #define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2078 #define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2079 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto 108:34e6b704fe68 2080 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2081 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2082
Kojto 93:e188a91d3eaa 2083 /******************** Bits definition for RTC_PRER register ****************/
Kojto 93:e188a91d3eaa 2084 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto 93:e188a91d3eaa 2085 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Kojto 93:e188a91d3eaa 2086
Kojto 108:34e6b704fe68 2087 /******************** Bits definition for RTC_WUTR register ****************/
Kojto 108:34e6b704fe68 2088 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
Kojto 108:34e6b704fe68 2089
Kojto 93:e188a91d3eaa 2090 /******************** Bits definition for RTC_ALRMAR register **************/
Kojto 93:e188a91d3eaa 2091 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 2092 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 2093 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto 93:e188a91d3eaa 2094 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 2095 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 2096 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto 93:e188a91d3eaa 2097 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 2098 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 2099 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 2100 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 2101 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 2102 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2103 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 2104 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2105 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2106 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto 93:e188a91d3eaa 2107 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2108 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2109 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2110 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2111 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2112 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto 93:e188a91d3eaa 2113 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2114 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2115 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2116 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 2117 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2118 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2119 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2120 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2121 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2122 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto 93:e188a91d3eaa 2123 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2124 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2125 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2126 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 2127 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2128 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2129 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2130 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2131
Kojto 93:e188a91d3eaa 2132 /******************** Bits definition for RTC_WPR register *****************/
Kojto 93:e188a91d3eaa 2133 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto 93:e188a91d3eaa 2134
Kojto 93:e188a91d3eaa 2135 /******************** Bits definition for RTC_SSR register *****************/
Kojto 93:e188a91d3eaa 2136 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto 93:e188a91d3eaa 2137
Kojto 93:e188a91d3eaa 2138 /******************** Bits definition for RTC_SHIFTR register **************/
Kojto 93:e188a91d3eaa 2139 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto 93:e188a91d3eaa 2140 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 2141
Kojto 93:e188a91d3eaa 2142 /******************** Bits definition for RTC_TSTR register ****************/
Kojto 93:e188a91d3eaa 2143 #define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2144 #define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 2145 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2146 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2147 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto 93:e188a91d3eaa 2148 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2149 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2150 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2151 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2152 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto 93:e188a91d3eaa 2153 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2154 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2155 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2156 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 2157 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2158 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2159 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2160 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2161 #define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto 93:e188a91d3eaa 2162 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2163 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2164 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2165 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 2166 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2167 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2168 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2169 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2170
Kojto 93:e188a91d3eaa 2171 /******************** Bits definition for RTC_TSDR register ****************/
Kojto 93:e188a91d3eaa 2172 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto 93:e188a91d3eaa 2173 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2174 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2175 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2176 #define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2177 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 2178 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2179 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2180 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2181 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2182 #define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto 93:e188a91d3eaa 2183 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2184 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2185 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 2186 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2187 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2188 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2189 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2190
Kojto 93:e188a91d3eaa 2191 /******************** Bits definition for RTC_TSSSR register ***************/
Kojto 93:e188a91d3eaa 2192 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto 93:e188a91d3eaa 2193
Kojto 93:e188a91d3eaa 2194 /******************** Bits definition for RTC_CALR register ****************/
Kojto 93:e188a91d3eaa 2195 #define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2196 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2197 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2198 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto 93:e188a91d3eaa 2199 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2200 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2201 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2202 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2203 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2204 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2205 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2206 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2207 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2208
Kojto 93:e188a91d3eaa 2209 /******************** Bits definition for RTC_TAFCR register ***************/
Kojto 93:e188a91d3eaa 2210 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2211 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2212 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto 93:e188a91d3eaa 2213 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2214 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2215 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Kojto 93:e188a91d3eaa 2216 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2217 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2218 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto 93:e188a91d3eaa 2219 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2220 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2221 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2222 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2223 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2224 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2225 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2226 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2227 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2228
Kojto 93:e188a91d3eaa 2229 /******************** Bits definition for RTC_ALRMASSR register ************/
Kojto 93:e188a91d3eaa 2230 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto 93:e188a91d3eaa 2231 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 2232 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 2233 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 2234 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 2235 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto 93:e188a91d3eaa 2236
Kojto 93:e188a91d3eaa 2237 /*****************************************************************************/
Kojto 93:e188a91d3eaa 2238 /* */
Kojto 93:e188a91d3eaa 2239 /* Serial Peripheral Interface (SPI) */
Kojto 93:e188a91d3eaa 2240 /* */
Kojto 93:e188a91d3eaa 2241 /*****************************************************************************/
Kojto 93:e188a91d3eaa 2242 /******************* Bit definition for SPI_CR1 register *******************/
Kojto 93:e188a91d3eaa 2243 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
Kojto 93:e188a91d3eaa 2244 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
Kojto 93:e188a91d3eaa 2245 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
Kojto 93:e188a91d3eaa 2246 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 93:e188a91d3eaa 2247 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2248 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2249 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 2250 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
Kojto 93:e188a91d3eaa 2251 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
Kojto 93:e188a91d3eaa 2252 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
Kojto 93:e188a91d3eaa 2253 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
Kojto 93:e188a91d3eaa 2254 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
Kojto 93:e188a91d3eaa 2255 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
Kojto 93:e188a91d3eaa 2256 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
Kojto 93:e188a91d3eaa 2257 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
Kojto 93:e188a91d3eaa 2258 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
Kojto 93:e188a91d3eaa 2259 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
Kojto 93:e188a91d3eaa 2260
Kojto 93:e188a91d3eaa 2261 /******************* Bit definition for SPI_CR2 register *******************/
Kojto 93:e188a91d3eaa 2262 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
Kojto 93:e188a91d3eaa 2263 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
Kojto 93:e188a91d3eaa 2264 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
Kojto 93:e188a91d3eaa 2265 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
Kojto 93:e188a91d3eaa 2266 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
Kojto 93:e188a91d3eaa 2267 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
Kojto 93:e188a91d3eaa 2268 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
Kojto 93:e188a91d3eaa 2269 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
Kojto 93:e188a91d3eaa 2270 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
Kojto 93:e188a91d3eaa 2271 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2272 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2273 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 2274 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 93:e188a91d3eaa 2275 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
Kojto 93:e188a91d3eaa 2276 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
Kojto 93:e188a91d3eaa 2277 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
Kojto 93:e188a91d3eaa 2278
Kojto 93:e188a91d3eaa 2279 /******************** Bit definition for SPI_SR register *******************/
Kojto 93:e188a91d3eaa 2280 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
Kojto 93:e188a91d3eaa 2281 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
Kojto 93:e188a91d3eaa 2282 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
Kojto 93:e188a91d3eaa 2283 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
Kojto 93:e188a91d3eaa 2284 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
Kojto 93:e188a91d3eaa 2285 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
Kojto 93:e188a91d3eaa 2286 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
Kojto 93:e188a91d3eaa 2287 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
Kojto 93:e188a91d3eaa 2288 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2289 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2290 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
Kojto 93:e188a91d3eaa 2291 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2292 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2293
Kojto 93:e188a91d3eaa 2294 /******************** Bit definition for SPI_DR register *******************/
Kojto 93:e188a91d3eaa 2295 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
Kojto 93:e188a91d3eaa 2296
Kojto 93:e188a91d3eaa 2297 /******************* Bit definition for SPI_CRCPR register *****************/
Kojto 93:e188a91d3eaa 2298 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
Kojto 93:e188a91d3eaa 2299
Kojto 93:e188a91d3eaa 2300 /****************** Bit definition for SPI_RXCRCR register *****************/
Kojto 93:e188a91d3eaa 2301 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
Kojto 93:e188a91d3eaa 2302
Kojto 93:e188a91d3eaa 2303 /****************** Bit definition for SPI_TXCRCR register *****************/
Kojto 93:e188a91d3eaa 2304 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
Kojto 93:e188a91d3eaa 2305
Kojto 93:e188a91d3eaa 2306 /****************** Bit definition for SPI_I2SCFGR register ****************/
Kojto 93:e188a91d3eaa 2307 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!< Keep for compatibility */
Kojto 93:e188a91d3eaa 2308
Kojto 93:e188a91d3eaa 2309 /*****************************************************************************/
Kojto 93:e188a91d3eaa 2310 /* */
Kojto 93:e188a91d3eaa 2311 /* System Configuration (SYSCFG) */
Kojto 93:e188a91d3eaa 2312 /* */
Kojto 93:e188a91d3eaa 2313 /*****************************************************************************/
Kojto 93:e188a91d3eaa 2314 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
Kojto 93:e188a91d3eaa 2315 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
Kojto 93:e188a91d3eaa 2316 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
Kojto 93:e188a91d3eaa 2317 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
Kojto 93:e188a91d3eaa 2318
Kojto 108:34e6b704fe68 2319
Kojto 108:34e6b704fe68 2320 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x04001F00) /*!< DMA remap mask */
Kojto 93:e188a91d3eaa 2321 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
Kojto 93:e188a91d3eaa 2322 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
Kojto 93:e188a91d3eaa 2323 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
Kojto 93:e188a91d3eaa 2324 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
Kojto 93:e188a91d3eaa 2325 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
Kojto 108:34e6b704fe68 2326 #define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
Kojto 93:e188a91d3eaa 2327
Kojto 93:e188a91d3eaa 2328 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
Kojto 93:e188a91d3eaa 2329 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
Kojto 93:e188a91d3eaa 2330 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
Kojto 93:e188a91d3eaa 2331 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
Kojto 93:e188a91d3eaa 2332 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
Kojto 108:34e6b704fe68 2333
Kojto 93:e188a91d3eaa 2334
Kojto 93:e188a91d3eaa 2335 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
Kojto 108:34e6b704fe68 2336 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
Kojto 108:34e6b704fe68 2337 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
Kojto 108:34e6b704fe68 2338 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
Kojto 108:34e6b704fe68 2339 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
Kojto 93:e188a91d3eaa 2340
Kojto 93:e188a91d3eaa 2341 /**
Kojto 93:e188a91d3eaa 2342 * @brief EXTI0 configuration
Kojto 93:e188a91d3eaa 2343 */
Kojto 108:34e6b704fe68 2344 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
Kojto 108:34e6b704fe68 2345 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
Kojto 108:34e6b704fe68 2346 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
Kojto 108:34e6b704fe68 2347 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
Kojto 108:34e6b704fe68 2348 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
Kojto 93:e188a91d3eaa 2349
Kojto 93:e188a91d3eaa 2350 /**
Kojto 93:e188a91d3eaa 2351 * @brief EXTI1 configuration
Kojto 93:e188a91d3eaa 2352 */
Kojto 108:34e6b704fe68 2353 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
Kojto 108:34e6b704fe68 2354 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
Kojto 108:34e6b704fe68 2355 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
Kojto 108:34e6b704fe68 2356 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
Kojto 108:34e6b704fe68 2357 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
Kojto 93:e188a91d3eaa 2358
Kojto 93:e188a91d3eaa 2359 /**
Kojto 93:e188a91d3eaa 2360 * @brief EXTI2 configuration
Kojto 93:e188a91d3eaa 2361 */
Kojto 108:34e6b704fe68 2362 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
Kojto 108:34e6b704fe68 2363 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
Kojto 108:34e6b704fe68 2364 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
Kojto 108:34e6b704fe68 2365 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
Kojto 108:34e6b704fe68 2366 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
Kojto 93:e188a91d3eaa 2367
Kojto 93:e188a91d3eaa 2368 /**
Kojto 93:e188a91d3eaa 2369 * @brief EXTI3 configuration
Kojto 93:e188a91d3eaa 2370 */
Kojto 108:34e6b704fe68 2371 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
Kojto 108:34e6b704fe68 2372 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
Kojto 108:34e6b704fe68 2373 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
Kojto 108:34e6b704fe68 2374 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
Kojto 108:34e6b704fe68 2375 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
Kojto 93:e188a91d3eaa 2376
Kojto 93:e188a91d3eaa 2377 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
Kojto 108:34e6b704fe68 2378 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
Kojto 108:34e6b704fe68 2379 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
Kojto 108:34e6b704fe68 2380 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
Kojto 108:34e6b704fe68 2381 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
Kojto 93:e188a91d3eaa 2382
Kojto 93:e188a91d3eaa 2383 /**
Kojto 93:e188a91d3eaa 2384 * @brief EXTI4 configuration
Kojto 93:e188a91d3eaa 2385 */
Kojto 108:34e6b704fe68 2386 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
Kojto 108:34e6b704fe68 2387 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
Kojto 108:34e6b704fe68 2388 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
Kojto 108:34e6b704fe68 2389 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
Kojto 108:34e6b704fe68 2390 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
Kojto 93:e188a91d3eaa 2391
Kojto 93:e188a91d3eaa 2392 /**
Kojto 93:e188a91d3eaa 2393 * @brief EXTI5 configuration
Kojto 93:e188a91d3eaa 2394 */
Kojto 108:34e6b704fe68 2395 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
Kojto 108:34e6b704fe68 2396 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
Kojto 108:34e6b704fe68 2397 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
Kojto 108:34e6b704fe68 2398 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
Kojto 108:34e6b704fe68 2399 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
Kojto 93:e188a91d3eaa 2400
Kojto 93:e188a91d3eaa 2401 /**
Kojto 93:e188a91d3eaa 2402 * @brief EXTI6 configuration
Kojto 93:e188a91d3eaa 2403 */
Kojto 108:34e6b704fe68 2404 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
Kojto 108:34e6b704fe68 2405 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
Kojto 108:34e6b704fe68 2406 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
Kojto 108:34e6b704fe68 2407 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
Kojto 108:34e6b704fe68 2408 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
Kojto 93:e188a91d3eaa 2409
Kojto 93:e188a91d3eaa 2410 /**
Kojto 93:e188a91d3eaa 2411 * @brief EXTI7 configuration
Kojto 93:e188a91d3eaa 2412 */
Kojto 108:34e6b704fe68 2413 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
Kojto 108:34e6b704fe68 2414 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
Kojto 108:34e6b704fe68 2415 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
Kojto 108:34e6b704fe68 2416 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
Kojto 108:34e6b704fe68 2417 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
Kojto 93:e188a91d3eaa 2418
Kojto 93:e188a91d3eaa 2419 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
Kojto 108:34e6b704fe68 2420 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
Kojto 108:34e6b704fe68 2421 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
Kojto 108:34e6b704fe68 2422 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
Kojto 108:34e6b704fe68 2423 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
Kojto 93:e188a91d3eaa 2424
Kojto 93:e188a91d3eaa 2425 /**
Kojto 93:e188a91d3eaa 2426 * @brief EXTI8 configuration
Kojto 93:e188a91d3eaa 2427 */
Kojto 108:34e6b704fe68 2428 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
Kojto 108:34e6b704fe68 2429 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
Kojto 108:34e6b704fe68 2430 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
Kojto 108:34e6b704fe68 2431 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
Kojto 108:34e6b704fe68 2432 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
Kojto 93:e188a91d3eaa 2433
Kojto 93:e188a91d3eaa 2434 /**
Kojto 93:e188a91d3eaa 2435 * @brief EXTI9 configuration
Kojto 93:e188a91d3eaa 2436 */
Kojto 108:34e6b704fe68 2437 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
Kojto 108:34e6b704fe68 2438 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
Kojto 108:34e6b704fe68 2439 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
Kojto 108:34e6b704fe68 2440 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
Kojto 108:34e6b704fe68 2441 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
Kojto 93:e188a91d3eaa 2442
Kojto 93:e188a91d3eaa 2443 /**
Kojto 93:e188a91d3eaa 2444 * @brief EXTI10 configuration
Kojto 93:e188a91d3eaa 2445 */
Kojto 108:34e6b704fe68 2446 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
Kojto 108:34e6b704fe68 2447 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
Kojto 108:34e6b704fe68 2448 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
Kojto 108:34e6b704fe68 2449 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
Kojto 108:34e6b704fe68 2450 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
Kojto 93:e188a91d3eaa 2451
Kojto 93:e188a91d3eaa 2452 /**
Kojto 93:e188a91d3eaa 2453 * @brief EXTI11 configuration
Kojto 93:e188a91d3eaa 2454 */
Kojto 108:34e6b704fe68 2455 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
Kojto 108:34e6b704fe68 2456 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
Kojto 108:34e6b704fe68 2457 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
Kojto 108:34e6b704fe68 2458 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
Kojto 108:34e6b704fe68 2459 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
Kojto 93:e188a91d3eaa 2460
Kojto 93:e188a91d3eaa 2461 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
Kojto 108:34e6b704fe68 2462 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
Kojto 108:34e6b704fe68 2463 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
Kojto 108:34e6b704fe68 2464 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
Kojto 108:34e6b704fe68 2465 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
Kojto 93:e188a91d3eaa 2466
Kojto 93:e188a91d3eaa 2467 /**
Kojto 93:e188a91d3eaa 2468 * @brief EXTI12 configuration
Kojto 93:e188a91d3eaa 2469 */
Kojto 108:34e6b704fe68 2470 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
Kojto 108:34e6b704fe68 2471 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
Kojto 108:34e6b704fe68 2472 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
Kojto 108:34e6b704fe68 2473 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
Kojto 108:34e6b704fe68 2474 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
Kojto 93:e188a91d3eaa 2475
Kojto 93:e188a91d3eaa 2476 /**
Kojto 93:e188a91d3eaa 2477 * @brief EXTI13 configuration
Kojto 93:e188a91d3eaa 2478 */
Kojto 108:34e6b704fe68 2479 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
Kojto 108:34e6b704fe68 2480 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
Kojto 108:34e6b704fe68 2481 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
Kojto 108:34e6b704fe68 2482 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
Kojto 108:34e6b704fe68 2483 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
Kojto 93:e188a91d3eaa 2484
Kojto 93:e188a91d3eaa 2485 /**
Kojto 93:e188a91d3eaa 2486 * @brief EXTI14 configuration
Kojto 93:e188a91d3eaa 2487 */
Kojto 108:34e6b704fe68 2488 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
Kojto 108:34e6b704fe68 2489 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
Kojto 108:34e6b704fe68 2490 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
Kojto 108:34e6b704fe68 2491 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
Kojto 108:34e6b704fe68 2492 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
Kojto 93:e188a91d3eaa 2493
Kojto 93:e188a91d3eaa 2494 /**
Kojto 93:e188a91d3eaa 2495 * @brief EXTI15 configuration
Kojto 93:e188a91d3eaa 2496 */
Kojto 108:34e6b704fe68 2497 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
Kojto 108:34e6b704fe68 2498 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
Kojto 108:34e6b704fe68 2499 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
Kojto 108:34e6b704fe68 2500 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
Kojto 108:34e6b704fe68 2501 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
Kojto 93:e188a91d3eaa 2502
Kojto 93:e188a91d3eaa 2503 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
Kojto 93:e188a91d3eaa 2504 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
Kojto 93:e188a91d3eaa 2505 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
Kojto 93:e188a91d3eaa 2506 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
Kojto 93:e188a91d3eaa 2507 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
Kojto 93:e188a91d3eaa 2508
Kojto 93:e188a91d3eaa 2509 /*****************************************************************************/
Kojto 93:e188a91d3eaa 2510 /* */
Kojto 93:e188a91d3eaa 2511 /* Timers (TIM) */
Kojto 93:e188a91d3eaa 2512 /* */
Kojto 93:e188a91d3eaa 2513 /*****************************************************************************/
Kojto 93:e188a91d3eaa 2514 /******************* Bit definition for TIM_CR1 register *******************/
Kojto 93:e188a91d3eaa 2515 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
Kojto 93:e188a91d3eaa 2516 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
Kojto 93:e188a91d3eaa 2517 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
Kojto 93:e188a91d3eaa 2518 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
Kojto 93:e188a91d3eaa 2519 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
Kojto 93:e188a91d3eaa 2520
Kojto 93:e188a91d3eaa 2521 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 93:e188a91d3eaa 2522 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2523 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2524
Kojto 93:e188a91d3eaa 2525 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
Kojto 93:e188a91d3eaa 2526
Kojto 93:e188a91d3eaa 2527 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
Kojto 93:e188a91d3eaa 2528 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2529 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2530
Kojto 93:e188a91d3eaa 2531 /******************* Bit definition for TIM_CR2 register *******************/
Kojto 93:e188a91d3eaa 2532 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
Kojto 93:e188a91d3eaa 2533 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
Kojto 93:e188a91d3eaa 2534 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
Kojto 93:e188a91d3eaa 2535
Kojto 93:e188a91d3eaa 2536 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 93:e188a91d3eaa 2537 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2538 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2539 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2540
Kojto 93:e188a91d3eaa 2541 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
Kojto 93:e188a91d3eaa 2542 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
Kojto 93:e188a91d3eaa 2543 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
Kojto 93:e188a91d3eaa 2544 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
Kojto 93:e188a91d3eaa 2545 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
Kojto 93:e188a91d3eaa 2546 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
Kojto 93:e188a91d3eaa 2547 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
Kojto 93:e188a91d3eaa 2548 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
Kojto 93:e188a91d3eaa 2549
Kojto 93:e188a91d3eaa 2550 /******************* Bit definition for TIM_SMCR register ******************/
Kojto 93:e188a91d3eaa 2551 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 93:e188a91d3eaa 2552 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2553 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2554 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2555
Kojto 93:e188a91d3eaa 2556 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
Kojto 93:e188a91d3eaa 2557
Kojto 93:e188a91d3eaa 2558 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
Kojto 93:e188a91d3eaa 2559 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2560 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2561 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2562
Kojto 93:e188a91d3eaa 2563 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
Kojto 93:e188a91d3eaa 2564
Kojto 93:e188a91d3eaa 2565 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 93:e188a91d3eaa 2566 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2567 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2568 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2569 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 2570
Kojto 93:e188a91d3eaa 2571 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 93:e188a91d3eaa 2572 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2573 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2574
Kojto 93:e188a91d3eaa 2575 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
Kojto 93:e188a91d3eaa 2576 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
Kojto 93:e188a91d3eaa 2577
Kojto 93:e188a91d3eaa 2578 /******************* Bit definition for TIM_DIER register ******************/
Kojto 93:e188a91d3eaa 2579 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
Kojto 93:e188a91d3eaa 2580 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
Kojto 93:e188a91d3eaa 2581 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
Kojto 93:e188a91d3eaa 2582 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
Kojto 93:e188a91d3eaa 2583 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
Kojto 93:e188a91d3eaa 2584 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
Kojto 93:e188a91d3eaa 2585 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
Kojto 93:e188a91d3eaa 2586 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
Kojto 93:e188a91d3eaa 2587 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
Kojto 93:e188a91d3eaa 2588 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
Kojto 93:e188a91d3eaa 2589 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
Kojto 93:e188a91d3eaa 2590 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
Kojto 93:e188a91d3eaa 2591 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
Kojto 93:e188a91d3eaa 2592 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
Kojto 93:e188a91d3eaa 2593 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
Kojto 93:e188a91d3eaa 2594
Kojto 93:e188a91d3eaa 2595 /******************** Bit definition for TIM_SR register *******************/
Kojto 93:e188a91d3eaa 2596 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
Kojto 93:e188a91d3eaa 2597 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
Kojto 93:e188a91d3eaa 2598 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
Kojto 93:e188a91d3eaa 2599 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
Kojto 93:e188a91d3eaa 2600 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
Kojto 93:e188a91d3eaa 2601 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
Kojto 93:e188a91d3eaa 2602 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
Kojto 93:e188a91d3eaa 2603 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
Kojto 93:e188a91d3eaa 2604 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 93:e188a91d3eaa 2605 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 93:e188a91d3eaa 2606 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 93:e188a91d3eaa 2607 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 93:e188a91d3eaa 2608
Kojto 93:e188a91d3eaa 2609 /******************* Bit definition for TIM_EGR register *******************/
Kojto 93:e188a91d3eaa 2610 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
Kojto 93:e188a91d3eaa 2611 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
Kojto 93:e188a91d3eaa 2612 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
Kojto 93:e188a91d3eaa 2613 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
Kojto 93:e188a91d3eaa 2614 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
Kojto 93:e188a91d3eaa 2615 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
Kojto 93:e188a91d3eaa 2616 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
Kojto 93:e188a91d3eaa 2617 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
Kojto 93:e188a91d3eaa 2618
Kojto 93:e188a91d3eaa 2619 /****************** Bit definition for TIM_CCMR1 register ******************/
Kojto 93:e188a91d3eaa 2620 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 93:e188a91d3eaa 2621 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2622 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2623
Kojto 93:e188a91d3eaa 2624 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
Kojto 93:e188a91d3eaa 2625 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
Kojto 93:e188a91d3eaa 2626
Kojto 93:e188a91d3eaa 2627 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 93:e188a91d3eaa 2628 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2629 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2630 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2631
Kojto 93:e188a91d3eaa 2632 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
Kojto 93:e188a91d3eaa 2633
Kojto 93:e188a91d3eaa 2634 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 93:e188a91d3eaa 2635 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2636 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2637
Kojto 93:e188a91d3eaa 2638 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
Kojto 93:e188a91d3eaa 2639 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
Kojto 93:e188a91d3eaa 2640
Kojto 93:e188a91d3eaa 2641 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 93:e188a91d3eaa 2642 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2643 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2644 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2645
Kojto 93:e188a91d3eaa 2646 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
Kojto 93:e188a91d3eaa 2647
Kojto 93:e188a91d3eaa 2648 /*---------------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 2649
Kojto 93:e188a91d3eaa 2650 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 93:e188a91d3eaa 2651 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2652 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2653
Kojto 93:e188a91d3eaa 2654 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 93:e188a91d3eaa 2655 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2656 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2657 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2658 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 2659
Kojto 93:e188a91d3eaa 2660 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 93:e188a91d3eaa 2661 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2662 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2663
Kojto 93:e188a91d3eaa 2664 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 93:e188a91d3eaa 2665 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2666 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2667 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2668 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 2669
Kojto 93:e188a91d3eaa 2670 /****************** Bit definition for TIM_CCMR2 register ******************/
Kojto 93:e188a91d3eaa 2671 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 93:e188a91d3eaa 2672 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2673 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2674
Kojto 93:e188a91d3eaa 2675 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
Kojto 93:e188a91d3eaa 2676 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
Kojto 93:e188a91d3eaa 2677
Kojto 93:e188a91d3eaa 2678 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 93:e188a91d3eaa 2679 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2680 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2681 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2682
Kojto 93:e188a91d3eaa 2683 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
Kojto 93:e188a91d3eaa 2684
Kojto 93:e188a91d3eaa 2685 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 93:e188a91d3eaa 2686 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2687 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2688
Kojto 93:e188a91d3eaa 2689 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
Kojto 93:e188a91d3eaa 2690 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
Kojto 93:e188a91d3eaa 2691
Kojto 93:e188a91d3eaa 2692 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 93:e188a91d3eaa 2693 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2694 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2695 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2696
Kojto 93:e188a91d3eaa 2697 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
Kojto 93:e188a91d3eaa 2698
Kojto 93:e188a91d3eaa 2699 /*---------------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 2700
Kojto 93:e188a91d3eaa 2701 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 93:e188a91d3eaa 2702 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2703 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2704
Kojto 93:e188a91d3eaa 2705 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 93:e188a91d3eaa 2706 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2707 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2708 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2709 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 2710
Kojto 93:e188a91d3eaa 2711 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 93:e188a91d3eaa 2712 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2713 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2714
Kojto 93:e188a91d3eaa 2715 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 93:e188a91d3eaa 2716 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2717 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2718 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2719 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 2720
Kojto 93:e188a91d3eaa 2721 /******************* Bit definition for TIM_CCER register ******************/
Kojto 93:e188a91d3eaa 2722 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
Kojto 93:e188a91d3eaa 2723 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
Kojto 93:e188a91d3eaa 2724 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
Kojto 93:e188a91d3eaa 2725 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 93:e188a91d3eaa 2726 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
Kojto 93:e188a91d3eaa 2727 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
Kojto 93:e188a91d3eaa 2728 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
Kojto 93:e188a91d3eaa 2729 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 93:e188a91d3eaa 2730 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
Kojto 93:e188a91d3eaa 2731 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
Kojto 93:e188a91d3eaa 2732 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
Kojto 93:e188a91d3eaa 2733 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 93:e188a91d3eaa 2734 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
Kojto 93:e188a91d3eaa 2735 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
Kojto 93:e188a91d3eaa 2736 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 93:e188a91d3eaa 2737
Kojto 93:e188a91d3eaa 2738 /******************* Bit definition for TIM_CNT register *******************/
Kojto 93:e188a91d3eaa 2739 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
Kojto 93:e188a91d3eaa 2740
Kojto 93:e188a91d3eaa 2741 /******************* Bit definition for TIM_PSC register *******************/
Kojto 93:e188a91d3eaa 2742 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
Kojto 93:e188a91d3eaa 2743
Kojto 93:e188a91d3eaa 2744 /******************* Bit definition for TIM_ARR register *******************/
Kojto 93:e188a91d3eaa 2745 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
Kojto 93:e188a91d3eaa 2746
Kojto 93:e188a91d3eaa 2747 /******************* Bit definition for TIM_RCR register *******************/
Kojto 93:e188a91d3eaa 2748 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
Kojto 93:e188a91d3eaa 2749
Kojto 93:e188a91d3eaa 2750 /******************* Bit definition for TIM_CCR1 register ******************/
Kojto 93:e188a91d3eaa 2751 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
Kojto 93:e188a91d3eaa 2752
Kojto 93:e188a91d3eaa 2753 /******************* Bit definition for TIM_CCR2 register ******************/
Kojto 93:e188a91d3eaa 2754 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
Kojto 93:e188a91d3eaa 2755
Kojto 93:e188a91d3eaa 2756 /******************* Bit definition for TIM_CCR3 register ******************/
Kojto 93:e188a91d3eaa 2757 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
Kojto 93:e188a91d3eaa 2758
Kojto 93:e188a91d3eaa 2759 /******************* Bit definition for TIM_CCR4 register ******************/
Kojto 93:e188a91d3eaa 2760 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
Kojto 93:e188a91d3eaa 2761
Kojto 93:e188a91d3eaa 2762 /******************* Bit definition for TIM_BDTR register ******************/
Kojto 93:e188a91d3eaa 2763 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 93:e188a91d3eaa 2764 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2765 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2766 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2767 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 2768 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 2769 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 2770 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 2771 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 93:e188a91d3eaa 2772
Kojto 93:e188a91d3eaa 2773 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 93:e188a91d3eaa 2774 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2775 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2776
Kojto 93:e188a91d3eaa 2777 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
Kojto 93:e188a91d3eaa 2778 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
Kojto 93:e188a91d3eaa 2779 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
Kojto 93:e188a91d3eaa 2780 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
Kojto 93:e188a91d3eaa 2781 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
Kojto 93:e188a91d3eaa 2782 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
Kojto 93:e188a91d3eaa 2783
Kojto 93:e188a91d3eaa 2784 /******************* Bit definition for TIM_DCR register *******************/
Kojto 93:e188a91d3eaa 2785 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 93:e188a91d3eaa 2786 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2787 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2788 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2789 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 2790 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 2791
Kojto 93:e188a91d3eaa 2792 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 93:e188a91d3eaa 2793 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2794 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2795 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2796 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 2797 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 2798
Kojto 93:e188a91d3eaa 2799 /******************* Bit definition for TIM_DMAR register ******************/
Kojto 93:e188a91d3eaa 2800 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
Kojto 93:e188a91d3eaa 2801
Kojto 93:e188a91d3eaa 2802 /******************* Bit definition for TIM14_OR register ********************/
Kojto 93:e188a91d3eaa 2803 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
Kojto 93:e188a91d3eaa 2804 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2805 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2806
Kojto 93:e188a91d3eaa 2807 /******************************************************************************/
Kojto 93:e188a91d3eaa 2808 /* */
Kojto 93:e188a91d3eaa 2809 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto 93:e188a91d3eaa 2810 /* */
Kojto 93:e188a91d3eaa 2811 /******************************************************************************/
Kojto 93:e188a91d3eaa 2812 /****************** Bit definition for USART_CR1 register *******************/
Kojto 93:e188a91d3eaa 2813 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
Kojto 93:e188a91d3eaa 2814 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
Kojto 93:e188a91d3eaa 2815 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
Kojto 93:e188a91d3eaa 2816 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
Kojto 93:e188a91d3eaa 2817 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
Kojto 93:e188a91d3eaa 2818 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
Kojto 93:e188a91d3eaa 2819 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
Kojto 93:e188a91d3eaa 2820 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
Kojto 93:e188a91d3eaa 2821 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
Kojto 93:e188a91d3eaa 2822 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
Kojto 93:e188a91d3eaa 2823 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
Kojto 93:e188a91d3eaa 2824 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
Kojto 93:e188a91d3eaa 2825 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
Kojto 93:e188a91d3eaa 2826 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
Kojto 93:e188a91d3eaa 2827 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
Kojto 93:e188a91d3eaa 2828 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Kojto 93:e188a91d3eaa 2829 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2830 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2831 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 2832 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 93:e188a91d3eaa 2833 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 93:e188a91d3eaa 2834 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Kojto 93:e188a91d3eaa 2835 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2836 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2837 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 2838 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
Kojto 93:e188a91d3eaa 2839 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
Kojto 93:e188a91d3eaa 2840 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
Kojto 93:e188a91d3eaa 2841 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
Kojto 93:e188a91d3eaa 2842 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
Kojto 93:e188a91d3eaa 2843 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
Kojto 93:e188a91d3eaa 2844
Kojto 93:e188a91d3eaa 2845 /****************** Bit definition for USART_CR2 register *******************/
Kojto 93:e188a91d3eaa 2846 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
Kojto 93:e188a91d3eaa 2847 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
Kojto 93:e188a91d3eaa 2848 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
Kojto 93:e188a91d3eaa 2849 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
Kojto 93:e188a91d3eaa 2850 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
Kojto 93:e188a91d3eaa 2851 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
Kojto 93:e188a91d3eaa 2852 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2853 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2854 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< Keep for compatibility */
Kojto 93:e188a91d3eaa 2855 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
Kojto 93:e188a91d3eaa 2856 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
Kojto 93:e188a91d3eaa 2857 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
Kojto 93:e188a91d3eaa 2858 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
Kojto 93:e188a91d3eaa 2859 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
Kojto 93:e188a91d3eaa 2860 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
Kojto 93:e188a91d3eaa 2861 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Kojto 93:e188a91d3eaa 2862 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2863 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2864 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
Kojto 93:e188a91d3eaa 2865 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
Kojto 93:e188a91d3eaa 2866
Kojto 93:e188a91d3eaa 2867 /****************** Bit definition for USART_CR3 register *******************/
Kojto 93:e188a91d3eaa 2868 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
Kojto 93:e188a91d3eaa 2869 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< Keep for compatibility */
Kojto 93:e188a91d3eaa 2870 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
Kojto 93:e188a91d3eaa 2871 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Keep for compatibility */
Kojto 93:e188a91d3eaa 2872 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
Kojto 93:e188a91d3eaa 2873 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
Kojto 93:e188a91d3eaa 2874 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
Kojto 93:e188a91d3eaa 2875 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
Kojto 93:e188a91d3eaa 2876 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
Kojto 93:e188a91d3eaa 2877 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
Kojto 93:e188a91d3eaa 2878 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
Kojto 93:e188a91d3eaa 2879 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
Kojto 93:e188a91d3eaa 2880 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
Kojto 93:e188a91d3eaa 2881 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
Kojto 93:e188a91d3eaa 2882
Kojto 93:e188a91d3eaa 2883 /****************** Bit definition for USART_BRR register *******************/
Kojto 93:e188a91d3eaa 2884 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
Kojto 93:e188a91d3eaa 2885 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
Kojto 93:e188a91d3eaa 2886
Kojto 93:e188a91d3eaa 2887 /****************** Bit definition for USART_GTPR register ******************/
Kojto 93:e188a91d3eaa 2888 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
Kojto 93:e188a91d3eaa 2889 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
Kojto 93:e188a91d3eaa 2890
Kojto 93:e188a91d3eaa 2891
Kojto 93:e188a91d3eaa 2892 /******************* Bit definition for USART_RTOR register *****************/
Kojto 93:e188a91d3eaa 2893 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
Kojto 93:e188a91d3eaa 2894 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
Kojto 93:e188a91d3eaa 2895
Kojto 93:e188a91d3eaa 2896 /******************* Bit definition for USART_RQR register ******************/
Kojto 93:e188a91d3eaa 2897 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
Kojto 93:e188a91d3eaa 2898 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
Kojto 93:e188a91d3eaa 2899 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
Kojto 93:e188a91d3eaa 2900 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
Kojto 93:e188a91d3eaa 2901
Kojto 93:e188a91d3eaa 2902 /******************* Bit definition for USART_ISR register ******************/
Kojto 93:e188a91d3eaa 2903 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
Kojto 93:e188a91d3eaa 2904 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
Kojto 93:e188a91d3eaa 2905 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
Kojto 93:e188a91d3eaa 2906 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
Kojto 93:e188a91d3eaa 2907 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
Kojto 93:e188a91d3eaa 2908 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
Kojto 93:e188a91d3eaa 2909 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
Kojto 93:e188a91d3eaa 2910 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
Kojto 93:e188a91d3eaa 2911 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
Kojto 93:e188a91d3eaa 2912 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
Kojto 93:e188a91d3eaa 2913 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
Kojto 93:e188a91d3eaa 2914 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
Kojto 93:e188a91d3eaa 2915 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
Kojto 93:e188a91d3eaa 2916 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
Kojto 93:e188a91d3eaa 2917 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
Kojto 93:e188a91d3eaa 2918 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
Kojto 93:e188a91d3eaa 2919 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
Kojto 93:e188a91d3eaa 2920 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
Kojto 93:e188a91d3eaa 2921 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
Kojto 93:e188a91d3eaa 2922
Kojto 93:e188a91d3eaa 2923 /******************* Bit definition for USART_ICR register ******************/
Kojto 93:e188a91d3eaa 2924 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
Kojto 93:e188a91d3eaa 2925 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
Kojto 93:e188a91d3eaa 2926 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
Kojto 93:e188a91d3eaa 2927 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
Kojto 93:e188a91d3eaa 2928 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
Kojto 93:e188a91d3eaa 2929 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
Kojto 93:e188a91d3eaa 2930 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
Kojto 93:e188a91d3eaa 2931 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
Kojto 93:e188a91d3eaa 2932 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
Kojto 93:e188a91d3eaa 2933
Kojto 93:e188a91d3eaa 2934 /******************* Bit definition for USART_RDR register ******************/
Kojto 93:e188a91d3eaa 2935 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
Kojto 93:e188a91d3eaa 2936
Kojto 93:e188a91d3eaa 2937 /******************* Bit definition for USART_TDR register ******************/
Kojto 93:e188a91d3eaa 2938 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
Kojto 93:e188a91d3eaa 2939
Kojto 93:e188a91d3eaa 2940 /******************************************************************************/
Kojto 93:e188a91d3eaa 2941 /* */
Kojto 93:e188a91d3eaa 2942 /* USB Device General registers */
Kojto 93:e188a91d3eaa 2943 /* */
Kojto 93:e188a91d3eaa 2944 /******************************************************************************/
Kojto 93:e188a91d3eaa 2945 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
Kojto 93:e188a91d3eaa 2946 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
Kojto 93:e188a91d3eaa 2947 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
Kojto 93:e188a91d3eaa 2948 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
Kojto 93:e188a91d3eaa 2949 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
Kojto 93:e188a91d3eaa 2950 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
Kojto 93:e188a91d3eaa 2951 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
Kojto 93:e188a91d3eaa 2952
Kojto 93:e188a91d3eaa 2953 /**************************** ISTR interrupt events *************************/
Kojto 93:e188a91d3eaa 2954 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
Kojto 93:e188a91d3eaa 2955 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
Kojto 93:e188a91d3eaa 2956 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
Kojto 93:e188a91d3eaa 2957 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
Kojto 93:e188a91d3eaa 2958 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
Kojto 93:e188a91d3eaa 2959 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
Kojto 93:e188a91d3eaa 2960 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
Kojto 93:e188a91d3eaa 2961 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
Kojto 93:e188a91d3eaa 2962 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
Kojto 93:e188a91d3eaa 2963 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
Kojto 93:e188a91d3eaa 2964 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
Kojto 93:e188a91d3eaa 2965
Kojto 93:e188a91d3eaa 2966 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
Kojto 93:e188a91d3eaa 2967 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
Kojto 93:e188a91d3eaa 2968 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
Kojto 93:e188a91d3eaa 2969 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
Kojto 93:e188a91d3eaa 2970 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
Kojto 93:e188a91d3eaa 2971 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
Kojto 93:e188a91d3eaa 2972 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
Kojto 93:e188a91d3eaa 2973 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
Kojto 93:e188a91d3eaa 2974 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
Kojto 93:e188a91d3eaa 2975
Kojto 93:e188a91d3eaa 2976 /************************* CNTR control register bits definitions ***********/
Kojto 93:e188a91d3eaa 2977 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
Kojto 93:e188a91d3eaa 2978 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
Kojto 93:e188a91d3eaa 2979 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
Kojto 93:e188a91d3eaa 2980 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
Kojto 93:e188a91d3eaa 2981 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
Kojto 93:e188a91d3eaa 2982 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
Kojto 93:e188a91d3eaa 2983 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
Kojto 93:e188a91d3eaa 2984 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
Kojto 93:e188a91d3eaa 2985 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
Kojto 93:e188a91d3eaa 2986 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
Kojto 93:e188a91d3eaa 2987 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
Kojto 93:e188a91d3eaa 2988 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
Kojto 93:e188a91d3eaa 2989 #define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
Kojto 93:e188a91d3eaa 2990 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
Kojto 93:e188a91d3eaa 2991 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
Kojto 93:e188a91d3eaa 2992
Kojto 93:e188a91d3eaa 2993 /************************* BCDR control register bits definitions ***********/
Kojto 93:e188a91d3eaa 2994 #define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
Kojto 93:e188a91d3eaa 2995 #define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
Kojto 93:e188a91d3eaa 2996 #define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
Kojto 93:e188a91d3eaa 2997 #define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
Kojto 93:e188a91d3eaa 2998 #define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
Kojto 93:e188a91d3eaa 2999 #define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
Kojto 93:e188a91d3eaa 3000 #define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
Kojto 93:e188a91d3eaa 3001 #define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
Kojto 93:e188a91d3eaa 3002 #define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
Kojto 93:e188a91d3eaa 3003
Kojto 93:e188a91d3eaa 3004 /*************************** LPM register bits definitions ******************/
Kojto 93:e188a91d3eaa 3005 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
Kojto 93:e188a91d3eaa 3006 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
Kojto 93:e188a91d3eaa 3007 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
Kojto 93:e188a91d3eaa 3008 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
Kojto 93:e188a91d3eaa 3009
Kojto 93:e188a91d3eaa 3010 /******************** FNR Frame Number Register bit definitions ************/
Kojto 93:e188a91d3eaa 3011 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
Kojto 93:e188a91d3eaa 3012 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
Kojto 93:e188a91d3eaa 3013 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
Kojto 93:e188a91d3eaa 3014 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
Kojto 93:e188a91d3eaa 3015 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
Kojto 93:e188a91d3eaa 3016
Kojto 93:e188a91d3eaa 3017 /******************** DADDR Device ADDRess bit definitions ****************/
Kojto 93:e188a91d3eaa 3018 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
Kojto 93:e188a91d3eaa 3019 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
Kojto 93:e188a91d3eaa 3020
Kojto 93:e188a91d3eaa 3021 /****************************** Endpoint register *************************/
Kojto 93:e188a91d3eaa 3022 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
Kojto 93:e188a91d3eaa 3023 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
Kojto 93:e188a91d3eaa 3024 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
Kojto 93:e188a91d3eaa 3025 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
Kojto 93:e188a91d3eaa 3026 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
Kojto 93:e188a91d3eaa 3027 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
Kojto 93:e188a91d3eaa 3028 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
Kojto 93:e188a91d3eaa 3029 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
Kojto 93:e188a91d3eaa 3030 /* bit positions */
Kojto 93:e188a91d3eaa 3031 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
Kojto 93:e188a91d3eaa 3032 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
Kojto 93:e188a91d3eaa 3033 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
Kojto 93:e188a91d3eaa 3034 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
Kojto 93:e188a91d3eaa 3035 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
Kojto 93:e188a91d3eaa 3036 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
Kojto 93:e188a91d3eaa 3037 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
Kojto 93:e188a91d3eaa 3038 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
Kojto 93:e188a91d3eaa 3039 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
Kojto 93:e188a91d3eaa 3040 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
Kojto 93:e188a91d3eaa 3041
Kojto 93:e188a91d3eaa 3042 /* EndPoint REGister MASK (no toggle fields) */
Kojto 93:e188a91d3eaa 3043 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
Kojto 93:e188a91d3eaa 3044 /*!< EP_TYPE[1:0] EndPoint TYPE */
Kojto 93:e188a91d3eaa 3045 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
Kojto 93:e188a91d3eaa 3046 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
Kojto 93:e188a91d3eaa 3047 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
Kojto 93:e188a91d3eaa 3048 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
Kojto 93:e188a91d3eaa 3049 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
Kojto 93:e188a91d3eaa 3050 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
Kojto 93:e188a91d3eaa 3051
Kojto 93:e188a91d3eaa 3052 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
Kojto 93:e188a91d3eaa 3053 /*!< STAT_TX[1:0] STATus for TX transfer */
Kojto 93:e188a91d3eaa 3054 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
Kojto 93:e188a91d3eaa 3055 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
Kojto 93:e188a91d3eaa 3056 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
Kojto 93:e188a91d3eaa 3057 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
Kojto 93:e188a91d3eaa 3058 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
Kojto 93:e188a91d3eaa 3059 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
Kojto 93:e188a91d3eaa 3060 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
Kojto 93:e188a91d3eaa 3061 /*!< STAT_RX[1:0] STATus for RX transfer */
Kojto 93:e188a91d3eaa 3062 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
Kojto 93:e188a91d3eaa 3063 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
Kojto 93:e188a91d3eaa 3064 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
Kojto 93:e188a91d3eaa 3065 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
Kojto 93:e188a91d3eaa 3066 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
Kojto 93:e188a91d3eaa 3067 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
Kojto 93:e188a91d3eaa 3068 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
Kojto 93:e188a91d3eaa 3069
Kojto 93:e188a91d3eaa 3070 /******************************************************************************/
Kojto 93:e188a91d3eaa 3071 /* */
Kojto 93:e188a91d3eaa 3072 /* Window WATCHDOG (WWDG) */
Kojto 93:e188a91d3eaa 3073 /* */
Kojto 93:e188a91d3eaa 3074 /******************************************************************************/
Kojto 93:e188a91d3eaa 3075 /******************* Bit definition for WWDG_CR register ********************/
Kojto 93:e188a91d3eaa 3076 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 93:e188a91d3eaa 3077 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3078 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3079 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3080 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3081 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 3082 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 3083 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 3084
Kojto 93:e188a91d3eaa 3085 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
Kojto 93:e188a91d3eaa 3086
Kojto 93:e188a91d3eaa 3087 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 93:e188a91d3eaa 3088 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
Kojto 93:e188a91d3eaa 3089 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3090 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3091 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3092 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3093 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 3094 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 3095 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 3096
Kojto 93:e188a91d3eaa 3097 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 93:e188a91d3eaa 3098 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3099 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3100
Kojto 93:e188a91d3eaa 3101 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
Kojto 93:e188a91d3eaa 3102
Kojto 93:e188a91d3eaa 3103 /******************* Bit definition for WWDG_SR register ********************/
Kojto 93:e188a91d3eaa 3104 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
Kojto 93:e188a91d3eaa 3105
Kojto 93:e188a91d3eaa 3106 /**
Kojto 93:e188a91d3eaa 3107 * @}
Kojto 93:e188a91d3eaa 3108 */
Kojto 93:e188a91d3eaa 3109
Kojto 93:e188a91d3eaa 3110 /**
Kojto 93:e188a91d3eaa 3111 * @}
Kojto 93:e188a91d3eaa 3112 */
Kojto 93:e188a91d3eaa 3113
Kojto 93:e188a91d3eaa 3114
Kojto 93:e188a91d3eaa 3115 /** @addtogroup Exported_macro
Kojto 93:e188a91d3eaa 3116 * @{
Kojto 93:e188a91d3eaa 3117 */
Kojto 93:e188a91d3eaa 3118
Kojto 93:e188a91d3eaa 3119 /****************************** ADC Instances *********************************/
Kojto 93:e188a91d3eaa 3120 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 93:e188a91d3eaa 3121
Kojto 93:e188a91d3eaa 3122 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
Kojto 93:e188a91d3eaa 3123
Kojto 93:e188a91d3eaa 3124 /****************************** CRC Instances *********************************/
Kojto 93:e188a91d3eaa 3125 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 93:e188a91d3eaa 3126
Kojto 93:e188a91d3eaa 3127 /******************************* DMA Instances ******************************/
Kojto 93:e188a91d3eaa 3128 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 93:e188a91d3eaa 3129 ((INSTANCE) == DMA1_Channel2) || \
Kojto 93:e188a91d3eaa 3130 ((INSTANCE) == DMA1_Channel3) || \
Kojto 93:e188a91d3eaa 3131 ((INSTANCE) == DMA1_Channel4) || \
Kojto 93:e188a91d3eaa 3132 ((INSTANCE) == DMA1_Channel5))
Kojto 93:e188a91d3eaa 3133
Kojto 93:e188a91d3eaa 3134 /****************************** GPIO Instances ********************************/
Kojto 93:e188a91d3eaa 3135 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 93:e188a91d3eaa 3136 ((INSTANCE) == GPIOB) || \
Kojto 93:e188a91d3eaa 3137 ((INSTANCE) == GPIOC) || \
Kojto 93:e188a91d3eaa 3138 ((INSTANCE) == GPIOD) || \
Kojto 93:e188a91d3eaa 3139 ((INSTANCE) == GPIOF))
Kojto 93:e188a91d3eaa 3140
Kojto 93:e188a91d3eaa 3141 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 93:e188a91d3eaa 3142 ((INSTANCE) == GPIOB) || \
Kojto 93:e188a91d3eaa 3143 ((INSTANCE) == GPIOC) || \
Kojto 93:e188a91d3eaa 3144 ((INSTANCE) == GPIOD) || \
Kojto 93:e188a91d3eaa 3145 ((INSTANCE) == GPIOF))
Kojto 93:e188a91d3eaa 3146
Kojto 93:e188a91d3eaa 3147 /****************************** GPIO Lock Instances ****************************/
Kojto 93:e188a91d3eaa 3148 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 93:e188a91d3eaa 3149 ((INSTANCE) == GPIOB))
Kojto 93:e188a91d3eaa 3150
Kojto 93:e188a91d3eaa 3151 /****************************** I2C Instances *********************************/
Kojto 93:e188a91d3eaa 3152 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 93:e188a91d3eaa 3153 ((INSTANCE) == I2C2))
Kojto 93:e188a91d3eaa 3154
Kojto 108:34e6b704fe68 3155
Kojto 93:e188a91d3eaa 3156 /****************************** IWDG Instances ********************************/
Kojto 93:e188a91d3eaa 3157 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 93:e188a91d3eaa 3158
Kojto 93:e188a91d3eaa 3159 /****************************** RTC Instances *********************************/
Kojto 93:e188a91d3eaa 3160 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 93:e188a91d3eaa 3161
Kojto 93:e188a91d3eaa 3162 /****************************** SMBUS Instances *********************************/
Kojto 93:e188a91d3eaa 3163 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Kojto 93:e188a91d3eaa 3164
Kojto 93:e188a91d3eaa 3165 /****************************** SPI Instances *********************************/
Kojto 93:e188a91d3eaa 3166 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 93:e188a91d3eaa 3167 ((INSTANCE) == SPI2))
Kojto 93:e188a91d3eaa 3168
Kojto 93:e188a91d3eaa 3169 /****************************** TIM Instances *********************************/
Kojto 93:e188a91d3eaa 3170 #define IS_TIM_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3171 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3172 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 3173 ((INSTANCE) == TIM6) || \
Kojto 93:e188a91d3eaa 3174 ((INSTANCE) == TIM7) || \
Kojto 93:e188a91d3eaa 3175 ((INSTANCE) == TIM14) || \
Kojto 93:e188a91d3eaa 3176 ((INSTANCE) == TIM15) || \
Kojto 93:e188a91d3eaa 3177 ((INSTANCE) == TIM16) || \
Kojto 93:e188a91d3eaa 3178 ((INSTANCE) == TIM17))
Kojto 93:e188a91d3eaa 3179
Kojto 93:e188a91d3eaa 3180 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3181 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3182 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 3183 ((INSTANCE) == TIM14) || \
Kojto 93:e188a91d3eaa 3184 ((INSTANCE) == TIM15) || \
Kojto 93:e188a91d3eaa 3185 ((INSTANCE) == TIM16) || \
Kojto 93:e188a91d3eaa 3186 ((INSTANCE) == TIM17))
Kojto 93:e188a91d3eaa 3187
Kojto 93:e188a91d3eaa 3188 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3189 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3190 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 3191 ((INSTANCE) == TIM15))
Kojto 93:e188a91d3eaa 3192
Kojto 93:e188a91d3eaa 3193 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3194 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3195 ((INSTANCE) == TIM3))
Kojto 93:e188a91d3eaa 3196
Kojto 93:e188a91d3eaa 3197 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3198 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3199 ((INSTANCE) == TIM3))
Kojto 93:e188a91d3eaa 3200
Kojto 93:e188a91d3eaa 3201 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3202 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3203 ((INSTANCE) == TIM3))
Kojto 93:e188a91d3eaa 3204
Kojto 93:e188a91d3eaa 3205 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3206 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3207 ((INSTANCE) == TIM3))
Kojto 93:e188a91d3eaa 3208
Kojto 93:e188a91d3eaa 3209 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3210 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3211 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 3212 ((INSTANCE) == TIM15))
Kojto 93:e188a91d3eaa 3213
Kojto 93:e188a91d3eaa 3214 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3215 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3216 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 3217 ((INSTANCE) == TIM15))
Kojto 93:e188a91d3eaa 3218
Kojto 93:e188a91d3eaa 3219 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3220 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3221 ((INSTANCE) == TIM3))
Kojto 93:e188a91d3eaa 3222
Kojto 93:e188a91d3eaa 3223 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3224 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3225 ((INSTANCE) == TIM3))
Kojto 93:e188a91d3eaa 3226
Kojto 93:e188a91d3eaa 3227 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3228 (((INSTANCE) == TIM1))
Kojto 93:e188a91d3eaa 3229
Kojto 93:e188a91d3eaa 3230 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3231 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3232 ((INSTANCE) == TIM3))
Kojto 93:e188a91d3eaa 3233
Kojto 93:e188a91d3eaa 3234 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3235 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3236 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 3237 ((INSTANCE) == TIM6) || \
Kojto 93:e188a91d3eaa 3238 ((INSTANCE) == TIM7) || \
Kojto 93:e188a91d3eaa 3239 ((INSTANCE) == TIM15))
Kojto 93:e188a91d3eaa 3240
Kojto 93:e188a91d3eaa 3241 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3242 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3243 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 3244 ((INSTANCE) == TIM15))
Kojto 93:e188a91d3eaa 3245
Kojto 93:e188a91d3eaa 3246 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(0)
Kojto 93:e188a91d3eaa 3247
Kojto 93:e188a91d3eaa 3248 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3249 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3250 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 3251 ((INSTANCE) == TIM15) || \
Kojto 93:e188a91d3eaa 3252 ((INSTANCE) == TIM16) || \
Kojto 93:e188a91d3eaa 3253 ((INSTANCE) == TIM17))
Kojto 93:e188a91d3eaa 3254
Kojto 93:e188a91d3eaa 3255 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3256 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3257 ((INSTANCE) == TIM15) || \
Kojto 93:e188a91d3eaa 3258 ((INSTANCE) == TIM16) || \
Kojto 93:e188a91d3eaa 3259 ((INSTANCE) == TIM17))
Kojto 93:e188a91d3eaa 3260
Kojto 93:e188a91d3eaa 3261 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 93:e188a91d3eaa 3262 ((((INSTANCE) == TIM1) && \
Kojto 93:e188a91d3eaa 3263 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 3264 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 3265 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 93:e188a91d3eaa 3266 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 93:e188a91d3eaa 3267 || \
Kojto 93:e188a91d3eaa 3268 (((INSTANCE) == TIM3) && \
Kojto 93:e188a91d3eaa 3269 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 3270 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 3271 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 93:e188a91d3eaa 3272 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 93:e188a91d3eaa 3273 || \
Kojto 93:e188a91d3eaa 3274 (((INSTANCE) == TIM14) && \
Kojto 93:e188a91d3eaa 3275 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 93:e188a91d3eaa 3276 || \
Kojto 93:e188a91d3eaa 3277 (((INSTANCE) == TIM15) && \
Kojto 93:e188a91d3eaa 3278 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 3279 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 93:e188a91d3eaa 3280 || \
Kojto 93:e188a91d3eaa 3281 (((INSTANCE) == TIM16) && \
Kojto 93:e188a91d3eaa 3282 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 93:e188a91d3eaa 3283 || \
Kojto 93:e188a91d3eaa 3284 (((INSTANCE) == TIM17) && \
Kojto 93:e188a91d3eaa 3285 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 93:e188a91d3eaa 3286
Kojto 93:e188a91d3eaa 3287 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 93:e188a91d3eaa 3288 ((((INSTANCE) == TIM1) && \
Kojto 93:e188a91d3eaa 3289 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 3290 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 3291 ((CHANNEL) == TIM_CHANNEL_3))) \
Kojto 93:e188a91d3eaa 3292 || \
Kojto 93:e188a91d3eaa 3293 (((INSTANCE) == TIM15) && \
Kojto 93:e188a91d3eaa 3294 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 93:e188a91d3eaa 3295 || \
Kojto 93:e188a91d3eaa 3296 (((INSTANCE) == TIM16) && \
Kojto 93:e188a91d3eaa 3297 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 93:e188a91d3eaa 3298 || \
Kojto 93:e188a91d3eaa 3299 (((INSTANCE) == TIM17) && \
Kojto 93:e188a91d3eaa 3300 ((CHANNEL) == TIM_CHANNEL_1)))
Kojto 93:e188a91d3eaa 3301
Kojto 93:e188a91d3eaa 3302 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3303 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3304 ((INSTANCE) == TIM3))
Kojto 93:e188a91d3eaa 3305
Kojto 93:e188a91d3eaa 3306 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3307 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3308 ((INSTANCE) == TIM15) || \
Kojto 93:e188a91d3eaa 3309 ((INSTANCE) == TIM16) || \
Kojto 93:e188a91d3eaa 3310 ((INSTANCE) == TIM17))
Kojto 93:e188a91d3eaa 3311
Kojto 93:e188a91d3eaa 3312 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3313 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3314 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 3315 ((INSTANCE) == TIM14) || \
Kojto 93:e188a91d3eaa 3316 ((INSTANCE) == TIM15) || \
Kojto 93:e188a91d3eaa 3317 ((INSTANCE) == TIM16) || \
Kojto 93:e188a91d3eaa 3318 ((INSTANCE) == TIM17))
Kojto 93:e188a91d3eaa 3319
Kojto 93:e188a91d3eaa 3320 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3321 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3322 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 3323 ((INSTANCE) == TIM6) || \
Kojto 93:e188a91d3eaa 3324 ((INSTANCE) == TIM7) || \
Kojto 93:e188a91d3eaa 3325 ((INSTANCE) == TIM15) || \
Kojto 93:e188a91d3eaa 3326 ((INSTANCE) == TIM16) || \
Kojto 93:e188a91d3eaa 3327 ((INSTANCE) == TIM17))
Kojto 93:e188a91d3eaa 3328
Kojto 93:e188a91d3eaa 3329 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3330 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3331 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 3332 ((INSTANCE) == TIM15) || \
Kojto 93:e188a91d3eaa 3333 ((INSTANCE) == TIM16) || \
Kojto 93:e188a91d3eaa 3334 ((INSTANCE) == TIM17))
Kojto 93:e188a91d3eaa 3335
Kojto 93:e188a91d3eaa 3336 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3337 (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 3338 ((INSTANCE) == TIM15) || \
Kojto 93:e188a91d3eaa 3339 ((INSTANCE) == TIM16) || \
Kojto 93:e188a91d3eaa 3340 ((INSTANCE) == TIM17))
Kojto 93:e188a91d3eaa 3341
Kojto 93:e188a91d3eaa 3342 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
Kojto 93:e188a91d3eaa 3343 ((INSTANCE) == TIM14)
Kojto 93:e188a91d3eaa 3344
Kojto 93:e188a91d3eaa 3345 /******************** USART Instances : Synchronous mode **********************/
Kojto 93:e188a91d3eaa 3346 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 3347 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 3348 ((INSTANCE) == USART3) || \
Kojto 93:e188a91d3eaa 3349 ((INSTANCE) == USART4))
Kojto 93:e188a91d3eaa 3350
Kojto 93:e188a91d3eaa 3351 /******************** USART Instances : auto Baud rate detection **************/
Kojto 93:e188a91d3eaa 3352 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 3353 ((INSTANCE) == USART2))
Kojto 93:e188a91d3eaa 3354
Kojto 93:e188a91d3eaa 3355 /******************** UART Instances : Asynchronous mode **********************/
Kojto 93:e188a91d3eaa 3356 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 3357 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 3358 ((INSTANCE) == USART3) || \
Kojto 93:e188a91d3eaa 3359 ((INSTANCE) == USART4))
Kojto 93:e188a91d3eaa 3360
Kojto 93:e188a91d3eaa 3361 /******************** UART Instances : Half-Duplex mode **********************/
Kojto 93:e188a91d3eaa 3362 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 3363 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 3364 ((INSTANCE) == USART3) || \
Kojto 93:e188a91d3eaa 3365 ((INSTANCE) == USART4))
Kojto 93:e188a91d3eaa 3366
Kojto 93:e188a91d3eaa 3367 /****************** UART Instances : Hardware Flow control ********************/
Kojto 93:e188a91d3eaa 3368 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 3369 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 3370 ((INSTANCE) == USART3) || \
Kojto 93:e188a91d3eaa 3371 ((INSTANCE) == USART4))
Kojto 93:e188a91d3eaa 3372
Kojto 93:e188a91d3eaa 3373 /****************** UART Instances : Auto Baud Rate detection ********************/
Kojto 93:e188a91d3eaa 3374 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 3375 ((INSTANCE) == USART2))
Kojto 93:e188a91d3eaa 3376
Kojto 108:34e6b704fe68 3377 /****************** UART Instances : Driver enable detection ********************/
Kojto 108:34e6b704fe68 3378 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 108:34e6b704fe68 3379 ((INSTANCE) == USART2) || \
Kojto 108:34e6b704fe68 3380 ((INSTANCE) == USART3) || \
Kojto 108:34e6b704fe68 3381 ((INSTANCE) == USART4))
Kojto 93:e188a91d3eaa 3382
Kojto 93:e188a91d3eaa 3383 /****************************** USB Instances ********************************/
Kojto 93:e188a91d3eaa 3384 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
Kojto 93:e188a91d3eaa 3385
Kojto 93:e188a91d3eaa 3386 /****************************** WWDG Instances ********************************/
Kojto 93:e188a91d3eaa 3387 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 93:e188a91d3eaa 3388
Kojto 93:e188a91d3eaa 3389 /**
Kojto 93:e188a91d3eaa 3390 * @}
Kojto 93:e188a91d3eaa 3391 */
Kojto 93:e188a91d3eaa 3392
Kojto 93:e188a91d3eaa 3393
Kojto 93:e188a91d3eaa 3394 /******************************************************************************/
Kojto 93:e188a91d3eaa 3395 /* For a painless codes migration between the STM32F0xx device product */
Kojto 93:e188a91d3eaa 3396 /* lines, the aliases defined below are put in place to overcome the */
Kojto 93:e188a91d3eaa 3397 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 93:e188a91d3eaa 3398 /* No need to update developed interrupt code when moving across */
Kojto 93:e188a91d3eaa 3399 /* product lines within the same STM32F0 Family */
Kojto 93:e188a91d3eaa 3400 /******************************************************************************/
Kojto 93:e188a91d3eaa 3401
Kojto 93:e188a91d3eaa 3402 /* Aliases for __IRQn */
Kojto 93:e188a91d3eaa 3403 #define RCC_CRS_IRQn RCC_IRQn
Kojto 93:e188a91d3eaa 3404 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
Kojto 93:e188a91d3eaa 3405 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
Kojto 93:e188a91d3eaa 3406 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
Kojto 93:e188a91d3eaa 3407 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Kojto 93:e188a91d3eaa 3408 #define ADC1_COMP_IRQn ADC1_IRQn
Kojto 93:e188a91d3eaa 3409 #define TIM6_DAC_IRQn TIM6_IRQn
Kojto 93:e188a91d3eaa 3410 #define USART3_8_IRQn USART3_4_IRQn
Kojto 93:e188a91d3eaa 3411 #define USART3_6_IRQn USART3_4_IRQn
Kojto 93:e188a91d3eaa 3412
Kojto 93:e188a91d3eaa 3413 /* Aliases for __IRQHandler */
Kojto 93:e188a91d3eaa 3414 #define RCC_CRS_IRQHandler RCC_IRQHandler
Kojto 93:e188a91d3eaa 3415 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
Kojto 93:e188a91d3eaa 3416 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
Kojto 93:e188a91d3eaa 3417 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
Kojto 93:e188a91d3eaa 3418 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
Kojto 93:e188a91d3eaa 3419 #define ADC1_COMP_IRQHandler ADC1_IRQHandler
Kojto 93:e188a91d3eaa 3420 #define TIM6_DAC_IRQHandler TIM6_IRQHandler
Kojto 93:e188a91d3eaa 3421 #define USART3_8_IRQHandler USART3_4_IRQHandler
Kojto 93:e188a91d3eaa 3422 #define USART3_6_IRQHandler USART3_4_IRQHandler
Kojto 93:e188a91d3eaa 3423
Kojto 93:e188a91d3eaa 3424 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 3425 }
Kojto 93:e188a91d3eaa 3426 #endif /* __cplusplus */
Kojto 93:e188a91d3eaa 3427
Kojto 93:e188a91d3eaa 3428 #endif /* __STM32F070xB_H */
Kojto 93:e188a91d3eaa 3429
Kojto 93:e188a91d3eaa 3430 /**
Kojto 93:e188a91d3eaa 3431 * @}
Kojto 93:e188a91d3eaa 3432 */
Kojto 93:e188a91d3eaa 3433
Kojto 93:e188a91d3eaa 3434 /**
Kojto 93:e188a91d3eaa 3435 * @}
Kojto 93:e188a91d3eaa 3436 */
Kojto 93:e188a91d3eaa 3437
Kojto 93:e188a91d3eaa 3438 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/