Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_ARCH_MAX/stm32f4xx_hal_adc.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Parent:
106:ba1f97679dad 
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_adc.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
Kojto 110:165afa46840b 5 * @version V1.4.1
Kojto 110:165afa46840b 6 * @date 09-October-2015
Kojto 110:165afa46840b 7 * @brief Header file containing functions prototypes of ADC HAL library.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_ADC_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_ADC_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
bogdanm 89:552587b429a1 52
bogdanm 89:552587b429a1 53 /** @addtogroup ADC
bogdanm 89:552587b429a1 54 * @{
bogdanm 89:552587b429a1 55 */
bogdanm 89:552587b429a1 56
bogdanm 89:552587b429a1 57 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 58 /** @defgroup ADC_Exported_Types ADC Exported Types
Kojto 99:dbbf35b96557 59 * @{
Kojto 99:dbbf35b96557 60 */
bogdanm 89:552587b429a1 61
bogdanm 89:552587b429a1 62 /**
Kojto 99:dbbf35b96557 63 * @brief HAL State structures definition
bogdanm 89:552587b429a1 64 */
bogdanm 89:552587b429a1 65 typedef enum
bogdanm 89:552587b429a1 66 {
bogdanm 89:552587b429a1 67 HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
bogdanm 89:552587b429a1 68 HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
bogdanm 89:552587b429a1 69 HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
bogdanm 89:552587b429a1 70 HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
bogdanm 89:552587b429a1 71 HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */
bogdanm 89:552587b429a1 72 HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */
bogdanm 89:552587b429a1 73 HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 89:552587b429a1 74 HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
bogdanm 89:552587b429a1 75 HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
bogdanm 89:552587b429a1 76 HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
bogdanm 89:552587b429a1 77 HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */
bogdanm 89:552587b429a1 78 HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */
bogdanm 89:552587b429a1 79 HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */
bogdanm 89:552587b429a1 80
bogdanm 89:552587b429a1 81 }HAL_ADC_StateTypeDef;
bogdanm 89:552587b429a1 82
bogdanm 89:552587b429a1 83 /**
Kojto 99:dbbf35b96557 84 * @brief ADC Init structure definition
bogdanm 89:552587b429a1 85 */
bogdanm 89:552587b429a1 86 typedef struct
bogdanm 89:552587b429a1 87 {
bogdanm 89:552587b429a1 88 uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for
bogdanm 89:552587b429a1 89 all the ADCs.
bogdanm 89:552587b429a1 90 This parameter can be a value of @ref ADC_ClockPrescaler */
bogdanm 89:552587b429a1 91 uint32_t Resolution; /*!< Configures the ADC resolution dual mode.
bogdanm 89:552587b429a1 92 This parameter can be a value of @ref ADC_Resolution */
bogdanm 89:552587b429a1 93 uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
bogdanm 89:552587b429a1 94 This parameter can be a value of @ref ADC_data_align */
bogdanm 89:552587b429a1 95 uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or
bogdanm 89:552587b429a1 96 Single (one channel) mode.
bogdanm 89:552587b429a1 97 This parameter can be set to ENABLE or DISABLE */
bogdanm 89:552587b429a1 98 uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set
bogdanm 89:552587b429a1 99 at the end of single channel conversion or at the end of all conversions.
Kojto 106:ba1f97679dad 100 This parameter can be a value of @ref ADC_EOCSelection
Kojto 106:ba1f97679dad 101 Note: Impact on overrun when not using DMA: When EOCSelection is set to ADC_EOC_SINGLE_CONV,
Kojto 106:ba1f97679dad 102 overrun detection is automatically enabled, in this case each conversion data must be read.
Kojto 106:ba1f97679dad 103 To perform ADC conversions without having to read all conversion data, this parameter must
Kojto 106:ba1f97679dad 104 be set to ADC_EOC_SEQ_CONV */
bogdanm 89:552587b429a1 105 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
bogdanm 89:552587b429a1 106 This parameter can be set to ENABLE or DISABLE. */
bogdanm 89:552587b429a1 107 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
bogdanm 89:552587b429a1 108 This parameter can be set to ENABLE or DISABLE. */
bogdanm 89:552587b429a1 109 uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
bogdanm 89:552587b429a1 110 regular channel group.
bogdanm 89:552587b429a1 111 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
bogdanm 89:552587b429a1 112 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not
bogdanm 89:552587b429a1 113 for regular channels.
bogdanm 89:552587b429a1 114 This parameter can be set to ENABLE or DISABLE. */
bogdanm 89:552587b429a1 115 uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done
bogdanm 89:552587b429a1 116 using the sequencer for regular channel group.
bogdanm 89:552587b429a1 117 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
Kojto 99:dbbf35b96557 118 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
Kojto 99:dbbf35b96557 119 If set to ADC_SOFTWARE_START, external triggers are disabled.
Kojto 99:dbbf35b96557 120 This parameter can be a value of @ref ADC_External_trigger_Source_Regular
Kojto 99:dbbf35b96557 121 Note: This parameter can be modified only if there is no conversion is ongoing. */
Kojto 99:dbbf35b96557 122 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
Kojto 99:dbbf35b96557 123 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
Kojto 99:dbbf35b96557 124 This parameter can be a value of @ref ADC_External_trigger_edge_Regular
Kojto 99:dbbf35b96557 125 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 89:552587b429a1 126 }ADC_InitTypeDef;
bogdanm 89:552587b429a1 127
bogdanm 89:552587b429a1 128 /**
Kojto 99:dbbf35b96557 129 * @brief ADC handle Structure definition
bogdanm 89:552587b429a1 130 */
bogdanm 89:552587b429a1 131 typedef struct
bogdanm 89:552587b429a1 132 {
bogdanm 89:552587b429a1 133 ADC_TypeDef *Instance; /*!< Register base address */
bogdanm 89:552587b429a1 134
bogdanm 89:552587b429a1 135 ADC_InitTypeDef Init; /*!< ADC required parameters */
bogdanm 89:552587b429a1 136
bogdanm 89:552587b429a1 137 __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
bogdanm 89:552587b429a1 138
bogdanm 89:552587b429a1 139 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
bogdanm 89:552587b429a1 140
bogdanm 89:552587b429a1 141 HAL_LockTypeDef Lock; /*!< ADC locking object */
bogdanm 89:552587b429a1 142
bogdanm 89:552587b429a1 143 __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
bogdanm 89:552587b429a1 144
bogdanm 89:552587b429a1 145 __IO uint32_t ErrorCode; /*!< ADC Error code */
bogdanm 89:552587b429a1 146 }ADC_HandleTypeDef;
bogdanm 89:552587b429a1 147
bogdanm 89:552587b429a1 148 /**
Kojto 99:dbbf35b96557 149 * @brief ADC Configuration regular Channel structure definition
bogdanm 89:552587b429a1 150 */
bogdanm 89:552587b429a1 151 typedef struct
bogdanm 89:552587b429a1 152 {
bogdanm 89:552587b429a1 153 uint32_t Channel; /*!< The ADC channel to configure.
bogdanm 89:552587b429a1 154 This parameter can be a value of @ref ADC_channels */
bogdanm 89:552587b429a1 155 uint32_t Rank; /*!< The rank in the regular group sequencer.
bogdanm 89:552587b429a1 156 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
bogdanm 89:552587b429a1 157 uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.
bogdanm 89:552587b429a1 158 This parameter can be a value of @ref ADC_sampling_times */
bogdanm 89:552587b429a1 159 uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
bogdanm 89:552587b429a1 160 }ADC_ChannelConfTypeDef;
bogdanm 89:552587b429a1 161
bogdanm 89:552587b429a1 162 /**
Kojto 99:dbbf35b96557 163 * @brief ADC Configuration multi-mode structure definition
bogdanm 89:552587b429a1 164 */
bogdanm 89:552587b429a1 165 typedef struct
bogdanm 89:552587b429a1 166 {
bogdanm 89:552587b429a1 167 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
bogdanm 89:552587b429a1 168 This parameter can be a value of @ref ADC_analog_watchdog_selection */
bogdanm 89:552587b429a1 169 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm 89:552587b429a1 170 This parameter must be a 12-bit value. */
bogdanm 89:552587b429a1 171 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm 89:552587b429a1 172 This parameter must be a 12-bit value. */
bogdanm 89:552587b429a1 173 uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
bogdanm 89:552587b429a1 174 This parameter has an effect only if watchdog mode is configured on single channel
bogdanm 89:552587b429a1 175 This parameter can be a value of @ref ADC_channels */
bogdanm 89:552587b429a1 176 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
bogdanm 89:552587b429a1 177 is interrupt mode or in polling mode.
bogdanm 89:552587b429a1 178 This parameter can be set to ENABLE or DISABLE */
bogdanm 89:552587b429a1 179 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
bogdanm 89:552587b429a1 180 }ADC_AnalogWDGConfTypeDef;
Kojto 99:dbbf35b96557 181 /**
Kojto 99:dbbf35b96557 182 * @}
Kojto 99:dbbf35b96557 183 */
bogdanm 89:552587b429a1 184
bogdanm 89:552587b429a1 185 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 186 /** @defgroup ADC_Exported_Constants ADC Exported Constants
bogdanm 89:552587b429a1 187 * @{
bogdanm 89:552587b429a1 188 */
bogdanm 89:552587b429a1 189
Kojto 99:dbbf35b96557 190 /** @defgroup ADC_Error_Code ADC Error Code
bogdanm 89:552587b429a1 191 * @{
Kojto 99:dbbf35b96557 192 */
bogdanm 89:552587b429a1 193 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
bogdanm 89:552587b429a1 194 #define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */
bogdanm 89:552587b429a1 195 #define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */
bogdanm 89:552587b429a1 196 /**
bogdanm 89:552587b429a1 197 * @}
bogdanm 89:552587b429a1 198 */
bogdanm 89:552587b429a1 199
bogdanm 89:552587b429a1 200
Kojto 99:dbbf35b96557 201 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
bogdanm 89:552587b429a1 202 * @{
bogdanm 89:552587b429a1 203 */
Kojto 110:165afa46840b 204 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000)
Kojto 110:165afa46840b 205 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
Kojto 110:165afa46840b 206 #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
Kojto 110:165afa46840b 207 #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
bogdanm 89:552587b429a1 208 /**
bogdanm 89:552587b429a1 209 * @}
bogdanm 89:552587b429a1 210 */
bogdanm 89:552587b429a1 211
Kojto 99:dbbf35b96557 212 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
bogdanm 92:4fc01daae5a5 213 * @{
bogdanm 92:4fc01daae5a5 214 */
bogdanm 92:4fc01daae5a5 215 #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 216 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
bogdanm 92:4fc01daae5a5 217 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
bogdanm 92:4fc01daae5a5 218 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
bogdanm 92:4fc01daae5a5 219 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
bogdanm 92:4fc01daae5a5 220 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
bogdanm 92:4fc01daae5a5 221 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
bogdanm 92:4fc01daae5a5 222 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
bogdanm 92:4fc01daae5a5 223 #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
bogdanm 92:4fc01daae5a5 224 #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
bogdanm 92:4fc01daae5a5 225 #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
bogdanm 92:4fc01daae5a5 226 #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
bogdanm 92:4fc01daae5a5 227 #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
bogdanm 92:4fc01daae5a5 228 #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
bogdanm 92:4fc01daae5a5 229 #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
bogdanm 92:4fc01daae5a5 230 #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
bogdanm 92:4fc01daae5a5 231 /**
bogdanm 92:4fc01daae5a5 232 * @}
bogdanm 92:4fc01daae5a5 233 */
bogdanm 92:4fc01daae5a5 234
Kojto 99:dbbf35b96557 235 /** @defgroup ADC_Resolution ADC Resolution
bogdanm 89:552587b429a1 236 * @{
bogdanm 89:552587b429a1 237 */
Kojto 99:dbbf35b96557 238 #define ADC_RESOLUTION_12B ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 239 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
Kojto 99:dbbf35b96557 240 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
Kojto 99:dbbf35b96557 241 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
bogdanm 89:552587b429a1 242 /**
bogdanm 89:552587b429a1 243 * @}
bogdanm 89:552587b429a1 244 */
bogdanm 89:552587b429a1 245
Kojto 99:dbbf35b96557 246 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
bogdanm 89:552587b429a1 247 * @{
bogdanm 89:552587b429a1 248 */
bogdanm 89:552587b429a1 249 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 250 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
bogdanm 89:552587b429a1 251 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
bogdanm 89:552587b429a1 252 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
bogdanm 89:552587b429a1 253 /**
bogdanm 89:552587b429a1 254 * @}
bogdanm 89:552587b429a1 255 */
bogdanm 89:552587b429a1 256
Kojto 99:dbbf35b96557 257 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
bogdanm 89:552587b429a1 258 * @{
Kojto 99:dbbf35b96557 259 */
Kojto 99:dbbf35b96557 260 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
Kojto 99:dbbf35b96557 261 /* compatibility with other STM32 devices. */
bogdanm 89:552587b429a1 262 #define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 263 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
bogdanm 89:552587b429a1 264 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
bogdanm 89:552587b429a1 265 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
bogdanm 89:552587b429a1 266 #define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
bogdanm 89:552587b429a1 267 #define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
bogdanm 89:552587b429a1 268 #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
bogdanm 89:552587b429a1 269 #define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
bogdanm 89:552587b429a1 270 #define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
bogdanm 89:552587b429a1 271 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
bogdanm 89:552587b429a1 272 #define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
bogdanm 89:552587b429a1 273 #define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
bogdanm 89:552587b429a1 274 #define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
bogdanm 89:552587b429a1 275 #define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
bogdanm 89:552587b429a1 276 #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
bogdanm 89:552587b429a1 277 #define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
Kojto 99:dbbf35b96557 278 #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
bogdanm 89:552587b429a1 279 /**
bogdanm 89:552587b429a1 280 * @}
bogdanm 89:552587b429a1 281 */
bogdanm 89:552587b429a1 282
Kojto 99:dbbf35b96557 283 /** @defgroup ADC_data_align ADC Data Align
bogdanm 89:552587b429a1 284 * @{
bogdanm 89:552587b429a1 285 */
bogdanm 89:552587b429a1 286 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 287 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
bogdanm 89:552587b429a1 288 /**
bogdanm 89:552587b429a1 289 * @}
bogdanm 89:552587b429a1 290 */
bogdanm 89:552587b429a1 291
Kojto 99:dbbf35b96557 292 /** @defgroup ADC_channels ADC Common Channels
bogdanm 89:552587b429a1 293 * @{
bogdanm 89:552587b429a1 294 */
bogdanm 89:552587b429a1 295 #define ADC_CHANNEL_0 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 296 #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
bogdanm 89:552587b429a1 297 #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
bogdanm 89:552587b429a1 298 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
bogdanm 89:552587b429a1 299 #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
bogdanm 89:552587b429a1 300 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
bogdanm 89:552587b429a1 301 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
bogdanm 89:552587b429a1 302 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
bogdanm 89:552587b429a1 303 #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
bogdanm 89:552587b429a1 304 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
bogdanm 89:552587b429a1 305 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
bogdanm 89:552587b429a1 306 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
bogdanm 89:552587b429a1 307 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
bogdanm 89:552587b429a1 308 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
bogdanm 89:552587b429a1 309 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
bogdanm 89:552587b429a1 310 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
bogdanm 89:552587b429a1 311 #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
bogdanm 89:552587b429a1 312 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
bogdanm 89:552587b429a1 313 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
bogdanm 89:552587b429a1 314
bogdanm 89:552587b429a1 315 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
Kojto 99:dbbf35b96557 316 #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
bogdanm 89:552587b429a1 317 /**
bogdanm 89:552587b429a1 318 * @}
bogdanm 89:552587b429a1 319 */
bogdanm 89:552587b429a1 320
Kojto 99:dbbf35b96557 321 /** @defgroup ADC_sampling_times ADC Sampling Times
bogdanm 89:552587b429a1 322 * @{
bogdanm 89:552587b429a1 323 */
bogdanm 89:552587b429a1 324 #define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 325 #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
bogdanm 89:552587b429a1 326 #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
bogdanm 89:552587b429a1 327 #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
bogdanm 89:552587b429a1 328 #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
bogdanm 89:552587b429a1 329 #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
bogdanm 89:552587b429a1 330 #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
bogdanm 89:552587b429a1 331 #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
bogdanm 89:552587b429a1 332 /**
bogdanm 89:552587b429a1 333 * @}
bogdanm 89:552587b429a1 334 */
bogdanm 89:552587b429a1 335
Kojto 99:dbbf35b96557 336 /** @defgroup ADC_EOCSelection ADC EOC Selection
bogdanm 89:552587b429a1 337 * @{
bogdanm 89:552587b429a1 338 */
Kojto 99:dbbf35b96557 339 #define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 340 #define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001)
Kojto 99:dbbf35b96557 341 #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */
bogdanm 89:552587b429a1 342 /**
bogdanm 89:552587b429a1 343 * @}
bogdanm 89:552587b429a1 344 */
bogdanm 89:552587b429a1 345
Kojto 99:dbbf35b96557 346 /** @defgroup ADC_Event_type ADC Event Type
bogdanm 89:552587b429a1 347 * @{
bogdanm 89:552587b429a1 348 */
Kojto 99:dbbf35b96557 349 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
Kojto 99:dbbf35b96557 350 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
bogdanm 89:552587b429a1 351 /**
bogdanm 89:552587b429a1 352 * @}
bogdanm 89:552587b429a1 353 */
bogdanm 89:552587b429a1 354
Kojto 99:dbbf35b96557 355 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
bogdanm 89:552587b429a1 356 * @{
bogdanm 89:552587b429a1 357 */
bogdanm 89:552587b429a1 358 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
bogdanm 89:552587b429a1 359 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
bogdanm 89:552587b429a1 360 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
bogdanm 89:552587b429a1 361 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
bogdanm 89:552587b429a1 362 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
bogdanm 89:552587b429a1 363 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
bogdanm 89:552587b429a1 364 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 365 /**
bogdanm 89:552587b429a1 366 * @}
bogdanm 89:552587b429a1 367 */
bogdanm 89:552587b429a1 368
Kojto 99:dbbf35b96557 369 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
bogdanm 89:552587b429a1 370 * @{
bogdanm 89:552587b429a1 371 */
bogdanm 89:552587b429a1 372 #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
bogdanm 89:552587b429a1 373 #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
bogdanm 89:552587b429a1 374 #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
bogdanm 89:552587b429a1 375 #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
bogdanm 89:552587b429a1 376 /**
bogdanm 89:552587b429a1 377 * @}
bogdanm 89:552587b429a1 378 */
bogdanm 89:552587b429a1 379
Kojto 99:dbbf35b96557 380 /** @defgroup ADC_flags_definition ADC Flags Definition
bogdanm 89:552587b429a1 381 * @{
bogdanm 89:552587b429a1 382 */
bogdanm 89:552587b429a1 383 #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
bogdanm 89:552587b429a1 384 #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
bogdanm 89:552587b429a1 385 #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
bogdanm 89:552587b429a1 386 #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
bogdanm 89:552587b429a1 387 #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
bogdanm 89:552587b429a1 388 #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
bogdanm 89:552587b429a1 389 /**
bogdanm 89:552587b429a1 390 * @}
bogdanm 89:552587b429a1 391 */
bogdanm 89:552587b429a1 392
Kojto 99:dbbf35b96557 393 /** @defgroup ADC_channels_type ADC Channels Type
bogdanm 89:552587b429a1 394 * @{
bogdanm 89:552587b429a1 395 */
Kojto 99:dbbf35b96557 396 #define ADC_ALL_CHANNELS ((uint32_t)0x00000001)
Kojto 99:dbbf35b96557 397 #define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */
Kojto 99:dbbf35b96557 398 #define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
bogdanm 89:552587b429a1 399 /**
bogdanm 89:552587b429a1 400 * @}
bogdanm 89:552587b429a1 401 */
bogdanm 89:552587b429a1 402
bogdanm 89:552587b429a1 403 /**
bogdanm 89:552587b429a1 404 * @}
bogdanm 89:552587b429a1 405 */
bogdanm 89:552587b429a1 406
bogdanm 89:552587b429a1 407 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 408 /** @defgroup ADC_Exported_Macros ADC Exported Macros
Kojto 99:dbbf35b96557 409 * @{
Kojto 99:dbbf35b96557 410 */
bogdanm 89:552587b429a1 411
bogdanm 89:552587b429a1 412 /** @brief Reset ADC handle state
bogdanm 89:552587b429a1 413 * @param __HANDLE__: ADC handle
bogdanm 89:552587b429a1 414 * @retval None
bogdanm 89:552587b429a1 415 */
bogdanm 89:552587b429a1 416 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
bogdanm 89:552587b429a1 417
bogdanm 89:552587b429a1 418 /**
bogdanm 89:552587b429a1 419 * @brief Enable the ADC peripheral.
bogdanm 89:552587b429a1 420 * @param __HANDLE__: ADC handle
bogdanm 89:552587b429a1 421 * @retval None
bogdanm 89:552587b429a1 422 */
bogdanm 89:552587b429a1 423 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
bogdanm 89:552587b429a1 424
bogdanm 89:552587b429a1 425 /**
bogdanm 89:552587b429a1 426 * @brief Disable the ADC peripheral.
bogdanm 89:552587b429a1 427 * @param __HANDLE__: ADC handle
bogdanm 89:552587b429a1 428 * @retval None
bogdanm 89:552587b429a1 429 */
bogdanm 89:552587b429a1 430 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
bogdanm 89:552587b429a1 431
bogdanm 89:552587b429a1 432 /**
bogdanm 89:552587b429a1 433 * @brief Enable the ADC end of conversion interrupt.
bogdanm 89:552587b429a1 434 * @param __HANDLE__: specifies the ADC Handle.
bogdanm 89:552587b429a1 435 * @param __INTERRUPT__: ADC Interrupt.
bogdanm 89:552587b429a1 436 * @retval None
bogdanm 89:552587b429a1 437 */
bogdanm 89:552587b429a1 438 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
bogdanm 89:552587b429a1 439
bogdanm 89:552587b429a1 440 /**
bogdanm 89:552587b429a1 441 * @brief Disable the ADC end of conversion interrupt.
bogdanm 89:552587b429a1 442 * @param __HANDLE__: specifies the ADC Handle.
bogdanm 89:552587b429a1 443 * @param __INTERRUPT__: ADC interrupt.
bogdanm 89:552587b429a1 444 * @retval None
bogdanm 89:552587b429a1 445 */
bogdanm 89:552587b429a1 446 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
bogdanm 89:552587b429a1 447
bogdanm 89:552587b429a1 448 /** @brief Check if the specified ADC interrupt source is enabled or disabled.
bogdanm 89:552587b429a1 449 * @param __HANDLE__: specifies the ADC Handle.
bogdanm 89:552587b429a1 450 * @param __INTERRUPT__: specifies the ADC interrupt source to check.
bogdanm 89:552587b429a1 451 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 89:552587b429a1 452 */
Kojto 99:dbbf35b96557 453 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 89:552587b429a1 454
bogdanm 89:552587b429a1 455 /**
bogdanm 89:552587b429a1 456 * @brief Clear the ADC's pending flags.
bogdanm 89:552587b429a1 457 * @param __HANDLE__: specifies the ADC Handle.
bogdanm 89:552587b429a1 458 * @param __FLAG__: ADC flag.
bogdanm 89:552587b429a1 459 * @retval None
bogdanm 89:552587b429a1 460 */
bogdanm 92:4fc01daae5a5 461 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
bogdanm 89:552587b429a1 462
bogdanm 89:552587b429a1 463 /**
bogdanm 89:552587b429a1 464 * @brief Get the selected ADC's flag status.
bogdanm 89:552587b429a1 465 * @param __HANDLE__: specifies the ADC Handle.
bogdanm 89:552587b429a1 466 * @param __FLAG__: ADC flag.
bogdanm 89:552587b429a1 467 * @retval None
bogdanm 89:552587b429a1 468 */
bogdanm 89:552587b429a1 469 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm 89:552587b429a1 470
bogdanm 89:552587b429a1 471 /**
Kojto 99:dbbf35b96557 472 * @}
bogdanm 89:552587b429a1 473 */
bogdanm 89:552587b429a1 474
bogdanm 89:552587b429a1 475 /* Include ADC HAL Extension module */
bogdanm 89:552587b429a1 476 #include "stm32f4xx_hal_adc_ex.h"
bogdanm 89:552587b429a1 477
bogdanm 89:552587b429a1 478 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 479 /** @addtogroup ADC_Exported_Functions
Kojto 99:dbbf35b96557 480 * @{
Kojto 99:dbbf35b96557 481 */
Kojto 99:dbbf35b96557 482
Kojto 99:dbbf35b96557 483 /** @addtogroup ADC_Exported_Functions_Group1
Kojto 99:dbbf35b96557 484 * @{
Kojto 99:dbbf35b96557 485 */
bogdanm 89:552587b429a1 486 /* Initialization/de-initialization functions ***********************************/
bogdanm 89:552587b429a1 487 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
bogdanm 89:552587b429a1 488 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
Kojto 99:dbbf35b96557 489 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
Kojto 99:dbbf35b96557 490 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
Kojto 99:dbbf35b96557 491 /**
Kojto 99:dbbf35b96557 492 * @}
Kojto 99:dbbf35b96557 493 */
bogdanm 89:552587b429a1 494
Kojto 99:dbbf35b96557 495 /** @addtogroup ADC_Exported_Functions_Group2
Kojto 99:dbbf35b96557 496 * @{
Kojto 99:dbbf35b96557 497 */
bogdanm 89:552587b429a1 498 /* I/O operation functions ******************************************************/
bogdanm 89:552587b429a1 499 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
bogdanm 89:552587b429a1 500 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
bogdanm 89:552587b429a1 501 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
bogdanm 89:552587b429a1 502
bogdanm 89:552587b429a1 503 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
bogdanm 89:552587b429a1 504
bogdanm 89:552587b429a1 505 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
bogdanm 89:552587b429a1 506 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
bogdanm 89:552587b429a1 507
Kojto 99:dbbf35b96557 508 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
bogdanm 89:552587b429a1 509
bogdanm 89:552587b429a1 510 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
bogdanm 89:552587b429a1 511 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
bogdanm 89:552587b429a1 512
Kojto 99:dbbf35b96557 513 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
bogdanm 89:552587b429a1 514
Kojto 99:dbbf35b96557 515 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
Kojto 99:dbbf35b96557 516 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
Kojto 99:dbbf35b96557 517 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
Kojto 99:dbbf35b96557 518 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
Kojto 99:dbbf35b96557 519 /**
Kojto 99:dbbf35b96557 520 * @}
Kojto 99:dbbf35b96557 521 */
bogdanm 89:552587b429a1 522
Kojto 99:dbbf35b96557 523 /** @addtogroup ADC_Exported_Functions_Group3
Kojto 99:dbbf35b96557 524 * @{
Kojto 99:dbbf35b96557 525 */
bogdanm 89:552587b429a1 526 /* Peripheral Control functions *************************************************/
bogdanm 89:552587b429a1 527 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
bogdanm 89:552587b429a1 528 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
Kojto 99:dbbf35b96557 529 /**
Kojto 99:dbbf35b96557 530 * @}
Kojto 99:dbbf35b96557 531 */
bogdanm 89:552587b429a1 532
Kojto 99:dbbf35b96557 533 /** @addtogroup ADC_Exported_Functions_Group4
Kojto 99:dbbf35b96557 534 * @{
Kojto 99:dbbf35b96557 535 */
bogdanm 89:552587b429a1 536 /* Peripheral State functions ***************************************************/
bogdanm 89:552587b429a1 537 HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
Kojto 99:dbbf35b96557 538 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
Kojto 99:dbbf35b96557 539 /**
Kojto 99:dbbf35b96557 540 * @}
Kojto 99:dbbf35b96557 541 */
Kojto 99:dbbf35b96557 542
Kojto 99:dbbf35b96557 543 /**
Kojto 99:dbbf35b96557 544 * @}
Kojto 99:dbbf35b96557 545 */
Kojto 99:dbbf35b96557 546 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 547 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 548 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 549 /** @defgroup ADC_Private_Constants ADC Private Constants
Kojto 99:dbbf35b96557 550 * @{
Kojto 99:dbbf35b96557 551 */
Kojto 99:dbbf35b96557 552 /* Delay for ADC stabilization time. */
Kojto 99:dbbf35b96557 553 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
Kojto 99:dbbf35b96557 554 /* Unit: us */
Kojto 99:dbbf35b96557 555 #define ADC_STAB_DELAY_US ((uint32_t) 3)
Kojto 99:dbbf35b96557 556 /* Delay for temperature sensor stabilization time. */
Kojto 99:dbbf35b96557 557 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
Kojto 99:dbbf35b96557 558 /* Unit: us */
Kojto 99:dbbf35b96557 559 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
Kojto 99:dbbf35b96557 560 /**
Kojto 99:dbbf35b96557 561 * @}
Kojto 99:dbbf35b96557 562 */
Kojto 99:dbbf35b96557 563
Kojto 99:dbbf35b96557 564 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 565 /** @defgroup ADC_Private_Macros ADC Private Macros
Kojto 99:dbbf35b96557 566 * @{
Kojto 99:dbbf35b96557 567 */
Kojto 110:165afa46840b 568 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
Kojto 110:165afa46840b 569 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
Kojto 110:165afa46840b 570 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
Kojto 110:165afa46840b 571 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
Kojto 99:dbbf35b96557 572 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
Kojto 99:dbbf35b96557 573 ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
Kojto 99:dbbf35b96557 574 ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
Kojto 99:dbbf35b96557 575 ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
Kojto 99:dbbf35b96557 576 ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
Kojto 99:dbbf35b96557 577 ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
Kojto 99:dbbf35b96557 578 ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
Kojto 99:dbbf35b96557 579 ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
Kojto 99:dbbf35b96557 580 ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
Kojto 99:dbbf35b96557 581 ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
Kojto 99:dbbf35b96557 582 ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
Kojto 99:dbbf35b96557 583 ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
Kojto 99:dbbf35b96557 584 ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
Kojto 99:dbbf35b96557 585 ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
Kojto 99:dbbf35b96557 586 ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
Kojto 99:dbbf35b96557 587 ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
Kojto 99:dbbf35b96557 588 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
Kojto 99:dbbf35b96557 589 ((RESOLUTION) == ADC_RESOLUTION_10B) || \
Kojto 99:dbbf35b96557 590 ((RESOLUTION) == ADC_RESOLUTION_8B) || \
Kojto 99:dbbf35b96557 591 ((RESOLUTION) == ADC_RESOLUTION_6B))
Kojto 99:dbbf35b96557 592 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
Kojto 99:dbbf35b96557 593 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
Kojto 99:dbbf35b96557 594 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
Kojto 99:dbbf35b96557 595 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
Kojto 99:dbbf35b96557 596 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
Kojto 99:dbbf35b96557 597 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
Kojto 99:dbbf35b96557 598 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
Kojto 99:dbbf35b96557 599 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
Kojto 99:dbbf35b96557 600 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
Kojto 99:dbbf35b96557 601 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
Kojto 99:dbbf35b96557 602 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
Kojto 99:dbbf35b96557 603 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
Kojto 99:dbbf35b96557 604 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
Kojto 99:dbbf35b96557 605 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
Kojto 99:dbbf35b96557 606 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
Kojto 99:dbbf35b96557 607 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
Kojto 99:dbbf35b96557 608 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
Kojto 99:dbbf35b96557 609 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
Kojto 99:dbbf35b96557 610 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
Kojto 99:dbbf35b96557 611 ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
Kojto 99:dbbf35b96557 612 ((REGTRIG) == ADC_SOFTWARE_START))
Kojto 99:dbbf35b96557 613 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
Kojto 99:dbbf35b96557 614 ((ALIGN) == ADC_DATAALIGN_LEFT))
Kojto 99:dbbf35b96557 615 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
Kojto 99:dbbf35b96557 616 ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
Kojto 99:dbbf35b96557 617 ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
Kojto 99:dbbf35b96557 618 ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
Kojto 99:dbbf35b96557 619 ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
Kojto 99:dbbf35b96557 620 ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
Kojto 99:dbbf35b96557 621 ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
Kojto 99:dbbf35b96557 622 ((TIME) == ADC_SAMPLETIME_480CYCLES))
Kojto 99:dbbf35b96557 623 #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \
Kojto 99:dbbf35b96557 624 ((EOCSelection) == ADC_EOC_SEQ_CONV) || \
Kojto 99:dbbf35b96557 625 ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
Kojto 99:dbbf35b96557 626 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
Kojto 99:dbbf35b96557 627 ((EVENT) == ADC_OVR_EVENT))
Kojto 99:dbbf35b96557 628 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
Kojto 99:dbbf35b96557 629 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
Kojto 99:dbbf35b96557 630 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
Kojto 99:dbbf35b96557 631 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
Kojto 99:dbbf35b96557 632 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
Kojto 99:dbbf35b96557 633 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
Kojto 99:dbbf35b96557 634 ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
Kojto 99:dbbf35b96557 635 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
Kojto 99:dbbf35b96557 636 ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
Kojto 99:dbbf35b96557 637 ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
Kojto 99:dbbf35b96557 638 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
Kojto 99:dbbf35b96557 639
Kojto 99:dbbf35b96557 640 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
Kojto 99:dbbf35b96557 641 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
Kojto 99:dbbf35b96557 642 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
Kojto 99:dbbf35b96557 643 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
Kojto 99:dbbf35b96557 644 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
Kojto 99:dbbf35b96557 645 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
Kojto 99:dbbf35b96557 646 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
Kojto 99:dbbf35b96557 647 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
Kojto 99:dbbf35b96557 648
Kojto 99:dbbf35b96557 649 /**
Kojto 99:dbbf35b96557 650 * @brief Set ADC Regular channel sequence length.
Kojto 99:dbbf35b96557 651 * @param _NbrOfConversion_: Regular channel sequence length.
Kojto 99:dbbf35b96557 652 * @retval None
Kojto 99:dbbf35b96557 653 */
Kojto 99:dbbf35b96557 654 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
Kojto 99:dbbf35b96557 655
Kojto 99:dbbf35b96557 656 /**
Kojto 99:dbbf35b96557 657 * @brief Set the ADC's sample time for channel numbers between 10 and 18.
Kojto 99:dbbf35b96557 658 * @param _SAMPLETIME_: Sample time parameter.
Kojto 99:dbbf35b96557 659 * @param _CHANNELNB_: Channel number.
Kojto 99:dbbf35b96557 660 * @retval None
Kojto 99:dbbf35b96557 661 */
Kojto 99:dbbf35b96557 662 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
Kojto 99:dbbf35b96557 663
Kojto 99:dbbf35b96557 664 /**
Kojto 99:dbbf35b96557 665 * @brief Set the ADC's sample time for channel numbers between 0 and 9.
Kojto 99:dbbf35b96557 666 * @param _SAMPLETIME_: Sample time parameter.
Kojto 99:dbbf35b96557 667 * @param _CHANNELNB_: Channel number.
Kojto 99:dbbf35b96557 668 * @retval None
Kojto 99:dbbf35b96557 669 */
Kojto 99:dbbf35b96557 670 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
Kojto 99:dbbf35b96557 671
Kojto 99:dbbf35b96557 672 /**
Kojto 99:dbbf35b96557 673 * @brief Set the selected regular channel rank for rank between 1 and 6.
Kojto 99:dbbf35b96557 674 * @param _CHANNELNB_: Channel number.
Kojto 99:dbbf35b96557 675 * @param _RANKNB_: Rank number.
Kojto 99:dbbf35b96557 676 * @retval None
Kojto 99:dbbf35b96557 677 */
Kojto 99:dbbf35b96557 678 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
Kojto 99:dbbf35b96557 679
Kojto 99:dbbf35b96557 680 /**
Kojto 99:dbbf35b96557 681 * @brief Set the selected regular channel rank for rank between 7 and 12.
Kojto 99:dbbf35b96557 682 * @param _CHANNELNB_: Channel number.
Kojto 99:dbbf35b96557 683 * @param _RANKNB_: Rank number.
Kojto 99:dbbf35b96557 684 * @retval None
Kojto 99:dbbf35b96557 685 */
Kojto 99:dbbf35b96557 686 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
Kojto 99:dbbf35b96557 687
Kojto 99:dbbf35b96557 688 /**
Kojto 99:dbbf35b96557 689 * @brief Set the selected regular channel rank for rank between 13 and 16.
Kojto 99:dbbf35b96557 690 * @param _CHANNELNB_: Channel number.
Kojto 99:dbbf35b96557 691 * @param _RANKNB_: Rank number.
Kojto 99:dbbf35b96557 692 * @retval None
Kojto 99:dbbf35b96557 693 */
Kojto 99:dbbf35b96557 694 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
Kojto 99:dbbf35b96557 695
Kojto 99:dbbf35b96557 696 /**
Kojto 99:dbbf35b96557 697 * @brief Enable ADC continuous conversion mode.
Kojto 99:dbbf35b96557 698 * @param _CONTINUOUS_MODE_: Continuous mode.
Kojto 99:dbbf35b96557 699 * @retval None
Kojto 99:dbbf35b96557 700 */
Kojto 99:dbbf35b96557 701 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
Kojto 99:dbbf35b96557 702
Kojto 99:dbbf35b96557 703 /**
Kojto 99:dbbf35b96557 704 * @brief Configures the number of discontinuous conversions for the regular group channels.
Kojto 99:dbbf35b96557 705 * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
Kojto 99:dbbf35b96557 706 * @retval None
Kojto 99:dbbf35b96557 707 */
Kojto 99:dbbf35b96557 708 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
Kojto 99:dbbf35b96557 709
Kojto 99:dbbf35b96557 710 /**
Kojto 99:dbbf35b96557 711 * @brief Enable ADC scan mode.
Kojto 99:dbbf35b96557 712 * @param _SCANCONV_MODE_: Scan conversion mode.
Kojto 99:dbbf35b96557 713 * @retval None
Kojto 99:dbbf35b96557 714 */
Kojto 99:dbbf35b96557 715 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
Kojto 99:dbbf35b96557 716
Kojto 99:dbbf35b96557 717 /**
Kojto 99:dbbf35b96557 718 * @brief Enable the ADC end of conversion selection.
Kojto 99:dbbf35b96557 719 * @param _EOCSelection_MODE_: End of conversion selection mode.
Kojto 99:dbbf35b96557 720 * @retval None
Kojto 99:dbbf35b96557 721 */
Kojto 99:dbbf35b96557 722 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
Kojto 99:dbbf35b96557 723
Kojto 99:dbbf35b96557 724 /**
Kojto 99:dbbf35b96557 725 * @brief Enable the ADC DMA continuous request.
Kojto 99:dbbf35b96557 726 * @param _DMAContReq_MODE_: DMA continuous request mode.
Kojto 99:dbbf35b96557 727 * @retval None
Kojto 99:dbbf35b96557 728 */
Kojto 99:dbbf35b96557 729 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
Kojto 99:dbbf35b96557 730
Kojto 99:dbbf35b96557 731 /**
Kojto 99:dbbf35b96557 732 * @brief Return resolution bits in CR1 register.
Kojto 99:dbbf35b96557 733 * @param __HANDLE__: ADC handle
Kojto 99:dbbf35b96557 734 * @retval None
Kojto 99:dbbf35b96557 735 */
Kojto 99:dbbf35b96557 736 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
Kojto 99:dbbf35b96557 737
Kojto 99:dbbf35b96557 738 /**
Kojto 99:dbbf35b96557 739 * @}
Kojto 99:dbbf35b96557 740 */
Kojto 99:dbbf35b96557 741
Kojto 99:dbbf35b96557 742 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 743 /** @defgroup ADC_Private_Functions ADC Private Functions
Kojto 99:dbbf35b96557 744 * @{
Kojto 99:dbbf35b96557 745 */
Kojto 99:dbbf35b96557 746
Kojto 99:dbbf35b96557 747 /**
Kojto 99:dbbf35b96557 748 * @}
Kojto 99:dbbf35b96557 749 */
bogdanm 89:552587b429a1 750
bogdanm 89:552587b429a1 751 /**
bogdanm 89:552587b429a1 752 * @}
bogdanm 89:552587b429a1 753 */
bogdanm 89:552587b429a1 754
bogdanm 89:552587b429a1 755 /**
bogdanm 89:552587b429a1 756 * @}
bogdanm 89:552587b429a1 757 */
bogdanm 89:552587b429a1 758
bogdanm 89:552587b429a1 759 #ifdef __cplusplus
bogdanm 89:552587b429a1 760 }
bogdanm 89:552587b429a1 761 #endif
bogdanm 89:552587b429a1 762
bogdanm 89:552587b429a1 763 #endif /*__STM32F4xx_ADC_H */
bogdanm 89:552587b429a1 764
bogdanm 89:552587b429a1 765
bogdanm 89:552587b429a1 766 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/