Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h@99:dbbf35b96557, 2015-05-13 (annotated)

Committer:
Kojto
Date:
Wed May 13 08:08:21 2015 +0200
Revision:
99:dbbf35b96557
Parent:
90:cb3d968589d8
Child:
106:ba1f97679dad
Release 99 of the mbed library



Changes:

 - new targets - MAXWSNENV, DISCO_L053C8

 - STM32F4xx - ST Cube driver

 - KSDK mcu - SPI timing fix

 - Nordic - update to softdevice s130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_sram.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 99:dbbf35b96557 5 * @version V1.3.0
Kojto 99:dbbf35b96557 6 * @date 09-March-2015
emilmont 77:869cf507173a 7 * @brief Header file of SRAM HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_SRAM_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_SRAM_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
emilmont 77:869cf507173a 48 #include "stm32f4xx_ll_fsmc.h"
emilmont 77:869cf507173a 49 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 50
Kojto 99:dbbf35b96557 51 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F446xx)
emilmont 77:869cf507173a 52 #include "stm32f4xx_ll_fmc.h"
Kojto 99:dbbf35b96557 53 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
emilmont 77:869cf507173a 54
emilmont 77:869cf507173a 55
emilmont 77:869cf507173a 56 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 57 * @{
emilmont 77:869cf507173a 58 */
emilmont 77:869cf507173a 59
Kojto 99:dbbf35b96557 60 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
Kojto 99:dbbf35b96557 61 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 99:dbbf35b96557 62 defined(STM32F446xx)
emilmont 77:869cf507173a 63 /** @addtogroup SRAM
emilmont 77:869cf507173a 64 * @{
emilmont 77:869cf507173a 65 */
emilmont 77:869cf507173a 66
emilmont 77:869cf507173a 67 /* Exported typedef ----------------------------------------------------------*/
emilmont 77:869cf507173a 68
Kojto 99:dbbf35b96557 69 /** @defgroup SRAM_Exported_Types SRAM Exported Types
Kojto 99:dbbf35b96557 70 * @{
Kojto 99:dbbf35b96557 71 */
emilmont 77:869cf507173a 72 /**
emilmont 77:869cf507173a 73 * @brief HAL SRAM State structures definition
emilmont 77:869cf507173a 74 */
emilmont 77:869cf507173a 75 typedef enum
emilmont 77:869cf507173a 76 {
emilmont 77:869cf507173a 77 HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
emilmont 77:869cf507173a 78 HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
emilmont 77:869cf507173a 79 HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
emilmont 77:869cf507173a 80 HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
emilmont 77:869cf507173a 81 HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
emilmont 77:869cf507173a 82
emilmont 77:869cf507173a 83 }HAL_SRAM_StateTypeDef;
emilmont 77:869cf507173a 84
emilmont 77:869cf507173a 85 /**
emilmont 77:869cf507173a 86 * @brief SRAM handle Structure definition
emilmont 77:869cf507173a 87 */
emilmont 77:869cf507173a 88 typedef struct
emilmont 77:869cf507173a 89 {
emilmont 77:869cf507173a 90 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
emilmont 77:869cf507173a 91
emilmont 77:869cf507173a 92 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
emilmont 77:869cf507173a 93
emilmont 77:869cf507173a 94 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
emilmont 77:869cf507173a 95
emilmont 77:869cf507173a 96 HAL_LockTypeDef Lock; /*!< SRAM locking object */
emilmont 77:869cf507173a 97
emilmont 77:869cf507173a 98 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
emilmont 77:869cf507173a 99
emilmont 77:869cf507173a 100 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
emilmont 77:869cf507173a 101
emilmont 77:869cf507173a 102 }SRAM_HandleTypeDef;
emilmont 77:869cf507173a 103
Kojto 99:dbbf35b96557 104 /**
Kojto 99:dbbf35b96557 105 * @}
Kojto 99:dbbf35b96557 106 */
Kojto 99:dbbf35b96557 107
bogdanm 85:024bf7f99721 108 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 109 /* Exported macro ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 110
Kojto 99:dbbf35b96557 111 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
Kojto 99:dbbf35b96557 112 * @{
Kojto 99:dbbf35b96557 113 */
bogdanm 85:024bf7f99721 114 /** @brief Reset SRAM handle state
bogdanm 85:024bf7f99721 115 * @param __HANDLE__: SRAM handle
bogdanm 85:024bf7f99721 116 * @retval None
bogdanm 85:024bf7f99721 117 */
bogdanm 85:024bf7f99721 118 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
bogdanm 85:024bf7f99721 119
Kojto 99:dbbf35b96557 120 /**
Kojto 99:dbbf35b96557 121 * @}
Kojto 99:dbbf35b96557 122 */
emilmont 77:869cf507173a 123 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 124
Kojto 99:dbbf35b96557 125 /** @addtogroup SRAM_Exported_Functions
Kojto 99:dbbf35b96557 126 * @{
Kojto 99:dbbf35b96557 127 */
Kojto 99:dbbf35b96557 128
Kojto 99:dbbf35b96557 129 /** @addtogroup SRAM_Exported_Functions_Group1
Kojto 99:dbbf35b96557 130 * @{
Kojto 99:dbbf35b96557 131 */
emilmont 77:869cf507173a 132 /* Initialization/de-initialization functions **********************************/
emilmont 77:869cf507173a 133 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
emilmont 77:869cf507173a 134 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
Kojto 99:dbbf35b96557 135 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
Kojto 99:dbbf35b96557 136 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
emilmont 77:869cf507173a 137
Kojto 99:dbbf35b96557 138 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 139 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 140 /**
Kojto 99:dbbf35b96557 141 * @}
Kojto 99:dbbf35b96557 142 */
Kojto 99:dbbf35b96557 143
Kojto 99:dbbf35b96557 144 /** @addtogroup SRAM_Exported_Functions_Group2
Kojto 99:dbbf35b96557 145 * @{
Kojto 99:dbbf35b96557 146 */
emilmont 77:869cf507173a 147 /* I/O operation functions *****************************************************/
emilmont 77:869cf507173a 148 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 149 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 150 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 151 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 152 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 153 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 154 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 155 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
Kojto 99:dbbf35b96557 156 /**
Kojto 99:dbbf35b96557 157 * @}
Kojto 99:dbbf35b96557 158 */
emilmont 77:869cf507173a 159
Kojto 99:dbbf35b96557 160 /** @addtogroup SRAM_Exported_Functions_Group3
Kojto 99:dbbf35b96557 161 * @{
Kojto 99:dbbf35b96557 162 */
emilmont 77:869cf507173a 163 /* SRAM Control functions ******************************************************/
emilmont 77:869cf507173a 164 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
emilmont 77:869cf507173a 165 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
emilmont 77:869cf507173a 166 /**
emilmont 77:869cf507173a 167 * @}
emilmont 77:869cf507173a 168 */
emilmont 77:869cf507173a 169
Kojto 99:dbbf35b96557 170 /** @addtogroup SRAM_Exported_Functions_Group4
Kojto 99:dbbf35b96557 171 * @{
Kojto 99:dbbf35b96557 172 */
Kojto 99:dbbf35b96557 173 /* SRAM State functions *********************************************************/
Kojto 99:dbbf35b96557 174 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
Kojto 99:dbbf35b96557 175 /**
Kojto 99:dbbf35b96557 176 * @}
Kojto 99:dbbf35b96557 177 */
Kojto 99:dbbf35b96557 178
emilmont 77:869cf507173a 179 /**
emilmont 77:869cf507173a 180 * @}
emilmont 77:869cf507173a 181 */
Kojto 99:dbbf35b96557 182
Kojto 99:dbbf35b96557 183 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 184 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 185 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 186 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 187 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 188 /**
Kojto 99:dbbf35b96557 189 * @}
Kojto 99:dbbf35b96557 190 */
Kojto 99:dbbf35b96557 191
Kojto 99:dbbf35b96557 192 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
Kojto 99:dbbf35b96557 193 /**
Kojto 99:dbbf35b96557 194 * @}
Kojto 99:dbbf35b96557 195 */
emilmont 77:869cf507173a 196 #ifdef __cplusplus
emilmont 77:869cf507173a 197 }
emilmont 77:869cf507173a 198 #endif
emilmont 77:869cf507173a 199
emilmont 77:869cf507173a 200 #endif /* __STM32F4xx_HAL_SRAM_H */
emilmont 77:869cf507173a 201
emilmont 77:869cf507173a 202 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/