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TARGET_MTS_MDOT_F411RE/stm32f4xx_hal_dma.h@99:dbbf35b96557, 2015-05-13 (annotated)
- Committer:
- Kojto
- Date:
- Wed May 13 08:08:21 2015 +0200
- Revision:
- 99:dbbf35b96557
- Parent:
- 93:e188a91d3eaa
- Child:
- 106:ba1f97679dad
Release 99 of the mbed library
Changes:
- new targets - MAXWSNENV, DISCO_L053C8
- STM32F4xx - ST Cube driver
- KSDK mcu - SPI timing fix
- Nordic - update to softdevice s130
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kojto | 93:e188a91d3eaa | 1 | /** |
| Kojto | 93:e188a91d3eaa | 2 | ****************************************************************************** |
| Kojto | 93:e188a91d3eaa | 3 | * @file stm32f4xx_hal_dma.h |
| Kojto | 93:e188a91d3eaa | 4 | * @author MCD Application Team |
| Kojto | 99:dbbf35b96557 | 5 | * @version V1.3.0 |
| Kojto | 99:dbbf35b96557 | 6 | * @date 09-March-2015 |
| Kojto | 93:e188a91d3eaa | 7 | * @brief Header file of DMA HAL module. |
| Kojto | 93:e188a91d3eaa | 8 | ****************************************************************************** |
| Kojto | 93:e188a91d3eaa | 9 | * @attention |
| Kojto | 93:e188a91d3eaa | 10 | * |
| Kojto | 99:dbbf35b96557 | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| Kojto | 93:e188a91d3eaa | 12 | * |
| Kojto | 93:e188a91d3eaa | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| Kojto | 93:e188a91d3eaa | 14 | * are permitted provided that the following conditions are met: |
| Kojto | 93:e188a91d3eaa | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| Kojto | 93:e188a91d3eaa | 16 | * this list of conditions and the following disclaimer. |
| Kojto | 93:e188a91d3eaa | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Kojto | 93:e188a91d3eaa | 18 | * this list of conditions and the following disclaimer in the documentation |
| Kojto | 93:e188a91d3eaa | 19 | * and/or other materials provided with the distribution. |
| Kojto | 93:e188a91d3eaa | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Kojto | 93:e188a91d3eaa | 21 | * may be used to endorse or promote products derived from this software |
| Kojto | 93:e188a91d3eaa | 22 | * without specific prior written permission. |
| Kojto | 93:e188a91d3eaa | 23 | * |
| Kojto | 93:e188a91d3eaa | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Kojto | 93:e188a91d3eaa | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Kojto | 93:e188a91d3eaa | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Kojto | 93:e188a91d3eaa | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Kojto | 93:e188a91d3eaa | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Kojto | 93:e188a91d3eaa | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Kojto | 93:e188a91d3eaa | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Kojto | 93:e188a91d3eaa | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Kojto | 93:e188a91d3eaa | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Kojto | 93:e188a91d3eaa | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Kojto | 93:e188a91d3eaa | 34 | * |
| Kojto | 93:e188a91d3eaa | 35 | ****************************************************************************** |
| Kojto | 93:e188a91d3eaa | 36 | */ |
| Kojto | 93:e188a91d3eaa | 37 | |
| Kojto | 93:e188a91d3eaa | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Kojto | 93:e188a91d3eaa | 39 | #ifndef __STM32F4xx_HAL_DMA_H |
| Kojto | 93:e188a91d3eaa | 40 | #define __STM32F4xx_HAL_DMA_H |
| Kojto | 93:e188a91d3eaa | 41 | |
| Kojto | 93:e188a91d3eaa | 42 | #ifdef __cplusplus |
| Kojto | 93:e188a91d3eaa | 43 | extern "C" { |
| Kojto | 93:e188a91d3eaa | 44 | #endif |
| Kojto | 93:e188a91d3eaa | 45 | |
| Kojto | 93:e188a91d3eaa | 46 | /* Includes ------------------------------------------------------------------*/ |
| Kojto | 93:e188a91d3eaa | 47 | #include "stm32f4xx_hal_def.h" |
| Kojto | 93:e188a91d3eaa | 48 | |
| Kojto | 93:e188a91d3eaa | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| Kojto | 93:e188a91d3eaa | 50 | * @{ |
| Kojto | 93:e188a91d3eaa | 51 | */ |
| Kojto | 93:e188a91d3eaa | 52 | |
| Kojto | 93:e188a91d3eaa | 53 | /** @addtogroup DMA |
| Kojto | 93:e188a91d3eaa | 54 | * @{ |
| Kojto | 93:e188a91d3eaa | 55 | */ |
| Kojto | 93:e188a91d3eaa | 56 | |
| Kojto | 93:e188a91d3eaa | 57 | /* Exported types ------------------------------------------------------------*/ |
| Kojto | 93:e188a91d3eaa | 58 | |
| Kojto | 99:dbbf35b96557 | 59 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| Kojto | 99:dbbf35b96557 | 60 | * @brief DMA Exported Types |
| Kojto | 99:dbbf35b96557 | 61 | * @{ |
| Kojto | 99:dbbf35b96557 | 62 | */ |
| Kojto | 99:dbbf35b96557 | 63 | |
| Kojto | 93:e188a91d3eaa | 64 | /** |
| Kojto | 93:e188a91d3eaa | 65 | * @brief DMA Configuration Structure definition |
| Kojto | 93:e188a91d3eaa | 66 | */ |
| Kojto | 93:e188a91d3eaa | 67 | typedef struct |
| Kojto | 93:e188a91d3eaa | 68 | { |
| Kojto | 93:e188a91d3eaa | 69 | uint32_t Channel; /*!< Specifies the channel used for the specified stream. |
| Kojto | 93:e188a91d3eaa | 70 | This parameter can be a value of @ref DMA_Channel_selection */ |
| Kojto | 93:e188a91d3eaa | 71 | |
| Kojto | 93:e188a91d3eaa | 72 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| Kojto | 93:e188a91d3eaa | 73 | from memory to memory or from peripheral to memory. |
| Kojto | 93:e188a91d3eaa | 74 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| Kojto | 93:e188a91d3eaa | 75 | |
| Kojto | 93:e188a91d3eaa | 76 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| Kojto | 93:e188a91d3eaa | 77 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| Kojto | 93:e188a91d3eaa | 78 | |
| Kojto | 93:e188a91d3eaa | 79 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| Kojto | 93:e188a91d3eaa | 80 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| Kojto | 93:e188a91d3eaa | 81 | |
| Kojto | 93:e188a91d3eaa | 82 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| Kojto | 93:e188a91d3eaa | 83 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| Kojto | 93:e188a91d3eaa | 84 | |
| Kojto | 93:e188a91d3eaa | 85 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| Kojto | 93:e188a91d3eaa | 86 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| Kojto | 93:e188a91d3eaa | 87 | |
| Kojto | 93:e188a91d3eaa | 88 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. |
| Kojto | 93:e188a91d3eaa | 89 | This parameter can be a value of @ref DMA_mode |
| Kojto | 93:e188a91d3eaa | 90 | @note The circular buffer mode cannot be used if the memory-to-memory |
| Kojto | 93:e188a91d3eaa | 91 | data transfer is configured on the selected Stream */ |
| Kojto | 93:e188a91d3eaa | 92 | |
| Kojto | 93:e188a91d3eaa | 93 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. |
| Kojto | 93:e188a91d3eaa | 94 | This parameter can be a value of @ref DMA_Priority_level */ |
| Kojto | 93:e188a91d3eaa | 95 | |
| Kojto | 93:e188a91d3eaa | 96 | uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. |
| Kojto | 93:e188a91d3eaa | 97 | This parameter can be a value of @ref DMA_FIFO_direct_mode |
| Kojto | 93:e188a91d3eaa | 98 | @note The Direct mode (FIFO mode disabled) cannot be used if the |
| Kojto | 93:e188a91d3eaa | 99 | memory-to-memory data transfer is configured on the selected stream */ |
| Kojto | 93:e188a91d3eaa | 100 | |
| Kojto | 93:e188a91d3eaa | 101 | uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. |
| Kojto | 93:e188a91d3eaa | 102 | This parameter can be a value of @ref DMA_FIFO_threshold_level */ |
| Kojto | 93:e188a91d3eaa | 103 | |
| Kojto | 93:e188a91d3eaa | 104 | uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. |
| Kojto | 99:dbbf35b96557 | 105 | It specifies the amount of data to be transferred in a single non interruptible |
| Kojto | 93:e188a91d3eaa | 106 | transaction. |
| Kojto | 93:e188a91d3eaa | 107 | This parameter can be a value of @ref DMA_Memory_burst |
| Kojto | 93:e188a91d3eaa | 108 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| Kojto | 93:e188a91d3eaa | 109 | |
| Kojto | 93:e188a91d3eaa | 110 | uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. |
| Kojto | 93:e188a91d3eaa | 111 | It specifies the amount of data to be transferred in a single non interruptable |
| Kojto | 93:e188a91d3eaa | 112 | transaction. |
| Kojto | 93:e188a91d3eaa | 113 | This parameter can be a value of @ref DMA_Peripheral_burst |
| Kojto | 93:e188a91d3eaa | 114 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| Kojto | 93:e188a91d3eaa | 115 | }DMA_InitTypeDef; |
| Kojto | 93:e188a91d3eaa | 116 | |
| Kojto | 99:dbbf35b96557 | 117 | |
| Kojto | 93:e188a91d3eaa | 118 | /** |
| Kojto | 93:e188a91d3eaa | 119 | * @brief HAL DMA State structures definition |
| Kojto | 93:e188a91d3eaa | 120 | */ |
| Kojto | 93:e188a91d3eaa | 121 | typedef enum |
| Kojto | 93:e188a91d3eaa | 122 | { |
| Kojto | 93:e188a91d3eaa | 123 | HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ |
| Kojto | 93:e188a91d3eaa | 124 | HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ |
| Kojto | 93:e188a91d3eaa | 125 | HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */ |
| Kojto | 93:e188a91d3eaa | 126 | HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */ |
| Kojto | 93:e188a91d3eaa | 127 | HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */ |
| Kojto | 93:e188a91d3eaa | 128 | HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */ |
| Kojto | 93:e188a91d3eaa | 129 | HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ |
| Kojto | 93:e188a91d3eaa | 130 | HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */ |
| Kojto | 93:e188a91d3eaa | 131 | HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */ |
| Kojto | 93:e188a91d3eaa | 132 | HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ |
| Kojto | 93:e188a91d3eaa | 133 | HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ |
| Kojto | 93:e188a91d3eaa | 134 | }HAL_DMA_StateTypeDef; |
| Kojto | 93:e188a91d3eaa | 135 | |
| Kojto | 93:e188a91d3eaa | 136 | /** |
| Kojto | 93:e188a91d3eaa | 137 | * @brief HAL DMA Error Code structure definition |
| Kojto | 93:e188a91d3eaa | 138 | */ |
| Kojto | 93:e188a91d3eaa | 139 | typedef enum |
| Kojto | 93:e188a91d3eaa | 140 | { |
| Kojto | 93:e188a91d3eaa | 141 | HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ |
| Kojto | 93:e188a91d3eaa | 142 | HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ |
| Kojto | 93:e188a91d3eaa | 143 | }HAL_DMA_LevelCompleteTypeDef; |
| Kojto | 93:e188a91d3eaa | 144 | |
| Kojto | 93:e188a91d3eaa | 145 | /** |
| Kojto | 93:e188a91d3eaa | 146 | * @brief DMA handle Structure definition |
| Kojto | 93:e188a91d3eaa | 147 | */ |
| Kojto | 93:e188a91d3eaa | 148 | typedef struct __DMA_HandleTypeDef |
| Kojto | 93:e188a91d3eaa | 149 | { |
| Kojto | 93:e188a91d3eaa | 150 | DMA_Stream_TypeDef *Instance; /*!< Register base address */ |
| Kojto | 93:e188a91d3eaa | 151 | |
| Kojto | 93:e188a91d3eaa | 152 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| Kojto | 93:e188a91d3eaa | 153 | |
| Kojto | 93:e188a91d3eaa | 154 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| Kojto | 93:e188a91d3eaa | 155 | |
| Kojto | 93:e188a91d3eaa | 156 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| Kojto | 93:e188a91d3eaa | 157 | |
| Kojto | 93:e188a91d3eaa | 158 | void *Parent; /*!< Parent object state */ |
| Kojto | 93:e188a91d3eaa | 159 | |
| Kojto | 93:e188a91d3eaa | 160 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| Kojto | 93:e188a91d3eaa | 161 | |
| Kojto | 93:e188a91d3eaa | 162 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| Kojto | 93:e188a91d3eaa | 163 | |
| Kojto | 93:e188a91d3eaa | 164 | void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ |
| Kojto | 93:e188a91d3eaa | 165 | |
| Kojto | 93:e188a91d3eaa | 166 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| Kojto | 93:e188a91d3eaa | 167 | |
| Kojto | 99:dbbf35b96557 | 168 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| Kojto | 93:e188a91d3eaa | 169 | }DMA_HandleTypeDef; |
| Kojto | 93:e188a91d3eaa | 170 | |
| Kojto | 99:dbbf35b96557 | 171 | /** |
| Kojto | 99:dbbf35b96557 | 172 | * @} |
| Kojto | 99:dbbf35b96557 | 173 | */ |
| Kojto | 99:dbbf35b96557 | 174 | |
| Kojto | 93:e188a91d3eaa | 175 | /* Exported constants --------------------------------------------------------*/ |
| Kojto | 93:e188a91d3eaa | 176 | |
| Kojto | 99:dbbf35b96557 | 177 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| Kojto | 99:dbbf35b96557 | 178 | * @brief DMA Exported constants |
| Kojto | 93:e188a91d3eaa | 179 | * @{ |
| Kojto | 93:e188a91d3eaa | 180 | */ |
| Kojto | 93:e188a91d3eaa | 181 | |
| Kojto | 99:dbbf35b96557 | 182 | /** @defgroup DMA_Error_Code DMA Error Code |
| Kojto | 99:dbbf35b96557 | 183 | * @brief DMA Error Code |
| Kojto | 93:e188a91d3eaa | 184 | * @{ |
| Kojto | 93:e188a91d3eaa | 185 | */ |
| Kojto | 93:e188a91d3eaa | 186 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| Kojto | 93:e188a91d3eaa | 187 | #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ |
| Kojto | 93:e188a91d3eaa | 188 | #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */ |
| Kojto | 93:e188a91d3eaa | 189 | #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */ |
| Kojto | 93:e188a91d3eaa | 190 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ |
| Kojto | 93:e188a91d3eaa | 191 | /** |
| Kojto | 93:e188a91d3eaa | 192 | * @} |
| Kojto | 93:e188a91d3eaa | 193 | */ |
| Kojto | 93:e188a91d3eaa | 194 | |
| Kojto | 99:dbbf35b96557 | 195 | /** @defgroup DMA_Channel_selection DMA Channel selection |
| Kojto | 99:dbbf35b96557 | 196 | * @brief DMA channel selection |
| Kojto | 93:e188a91d3eaa | 197 | * @{ |
| Kojto | 93:e188a91d3eaa | 198 | */ |
| Kojto | 93:e188a91d3eaa | 199 | #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */ |
| Kojto | 93:e188a91d3eaa | 200 | #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */ |
| Kojto | 93:e188a91d3eaa | 201 | #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */ |
| Kojto | 93:e188a91d3eaa | 202 | #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */ |
| Kojto | 93:e188a91d3eaa | 203 | #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */ |
| Kojto | 93:e188a91d3eaa | 204 | #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */ |
| Kojto | 93:e188a91d3eaa | 205 | #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */ |
| Kojto | 93:e188a91d3eaa | 206 | #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */ |
| Kojto | 93:e188a91d3eaa | 207 | /** |
| Kojto | 93:e188a91d3eaa | 208 | * @} |
| Kojto | 93:e188a91d3eaa | 209 | */ |
| Kojto | 93:e188a91d3eaa | 210 | |
| Kojto | 99:dbbf35b96557 | 211 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
| Kojto | 99:dbbf35b96557 | 212 | * @brief DMA data transfer direction |
| Kojto | 93:e188a91d3eaa | 213 | * @{ |
| Kojto | 93:e188a91d3eaa | 214 | */ |
| Kojto | 93:e188a91d3eaa | 215 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ |
| Kojto | 93:e188a91d3eaa | 216 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ |
| Kojto | 93:e188a91d3eaa | 217 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ |
| Kojto | 93:e188a91d3eaa | 218 | /** |
| Kojto | 93:e188a91d3eaa | 219 | * @} |
| Kojto | 99:dbbf35b96557 | 220 | */ |
| Kojto | 93:e188a91d3eaa | 221 | |
| Kojto | 99:dbbf35b96557 | 222 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
| Kojto | 99:dbbf35b96557 | 223 | * @brief DMA peripheral incremented mode |
| Kojto | 93:e188a91d3eaa | 224 | * @{ |
| Kojto | 93:e188a91d3eaa | 225 | */ |
| Kojto | 93:e188a91d3eaa | 226 | #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ |
| Kojto | 93:e188a91d3eaa | 227 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */ |
| Kojto | 93:e188a91d3eaa | 228 | /** |
| Kojto | 93:e188a91d3eaa | 229 | * @} |
| Kojto | 93:e188a91d3eaa | 230 | */ |
| Kojto | 93:e188a91d3eaa | 231 | |
| Kojto | 99:dbbf35b96557 | 232 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
| Kojto | 99:dbbf35b96557 | 233 | * @brief DMA memory incremented mode |
| Kojto | 93:e188a91d3eaa | 234 | * @{ |
| Kojto | 93:e188a91d3eaa | 235 | */ |
| Kojto | 93:e188a91d3eaa | 236 | #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ |
| Kojto | 93:e188a91d3eaa | 237 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */ |
| Kojto | 93:e188a91d3eaa | 238 | /** |
| Kojto | 93:e188a91d3eaa | 239 | * @} |
| Kojto | 93:e188a91d3eaa | 240 | */ |
| Kojto | 93:e188a91d3eaa | 241 | |
| Kojto | 99:dbbf35b96557 | 242 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
| Kojto | 99:dbbf35b96557 | 243 | * @brief DMA peripheral data size |
| Kojto | 93:e188a91d3eaa | 244 | * @{ |
| Kojto | 93:e188a91d3eaa | 245 | */ |
| Kojto | 93:e188a91d3eaa | 246 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ |
| Kojto | 93:e188a91d3eaa | 247 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ |
| Kojto | 93:e188a91d3eaa | 248 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ |
| Kojto | 93:e188a91d3eaa | 249 | /** |
| Kojto | 93:e188a91d3eaa | 250 | * @} |
| Kojto | 93:e188a91d3eaa | 251 | */ |
| Kojto | 93:e188a91d3eaa | 252 | |
| Kojto | 99:dbbf35b96557 | 253 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
| Kojto | 99:dbbf35b96557 | 254 | * @brief DMA memory data size |
| Kojto | 93:e188a91d3eaa | 255 | * @{ |
| Kojto | 93:e188a91d3eaa | 256 | */ |
| Kojto | 93:e188a91d3eaa | 257 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ |
| Kojto | 93:e188a91d3eaa | 258 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ |
| Kojto | 93:e188a91d3eaa | 259 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ |
| Kojto | 93:e188a91d3eaa | 260 | /** |
| Kojto | 93:e188a91d3eaa | 261 | * @} |
| Kojto | 93:e188a91d3eaa | 262 | */ |
| Kojto | 93:e188a91d3eaa | 263 | |
| Kojto | 99:dbbf35b96557 | 264 | /** @defgroup DMA_mode DMA mode |
| Kojto | 99:dbbf35b96557 | 265 | * @brief DMA mode |
| Kojto | 93:e188a91d3eaa | 266 | * @{ |
| Kojto | 93:e188a91d3eaa | 267 | */ |
| Kojto | 93:e188a91d3eaa | 268 | #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ |
| Kojto | 93:e188a91d3eaa | 269 | #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ |
| Kojto | 93:e188a91d3eaa | 270 | #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ |
| Kojto | 93:e188a91d3eaa | 271 | /** |
| Kojto | 93:e188a91d3eaa | 272 | * @} |
| Kojto | 93:e188a91d3eaa | 273 | */ |
| Kojto | 93:e188a91d3eaa | 274 | |
| Kojto | 99:dbbf35b96557 | 275 | /** @defgroup DMA_Priority_level DMA Priority level |
| Kojto | 99:dbbf35b96557 | 276 | * @brief DMA priority levels |
| Kojto | 93:e188a91d3eaa | 277 | * @{ |
| Kojto | 93:e188a91d3eaa | 278 | */ |
| Kojto | 93:e188a91d3eaa | 279 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */ |
| Kojto | 93:e188a91d3eaa | 280 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ |
| Kojto | 93:e188a91d3eaa | 281 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ |
| Kojto | 93:e188a91d3eaa | 282 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ |
| Kojto | 93:e188a91d3eaa | 283 | /** |
| Kojto | 93:e188a91d3eaa | 284 | * @} |
| Kojto | 93:e188a91d3eaa | 285 | */ |
| Kojto | 93:e188a91d3eaa | 286 | |
| Kojto | 99:dbbf35b96557 | 287 | /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode |
| Kojto | 99:dbbf35b96557 | 288 | * @brief DMA FIFO direct mode |
| Kojto | 93:e188a91d3eaa | 289 | * @{ |
| Kojto | 93:e188a91d3eaa | 290 | */ |
| Kojto | 93:e188a91d3eaa | 291 | #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */ |
| Kojto | 93:e188a91d3eaa | 292 | #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ |
| Kojto | 93:e188a91d3eaa | 293 | /** |
| Kojto | 93:e188a91d3eaa | 294 | * @} |
| Kojto | 93:e188a91d3eaa | 295 | */ |
| Kojto | 93:e188a91d3eaa | 296 | |
| Kojto | 99:dbbf35b96557 | 297 | /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level |
| Kojto | 99:dbbf35b96557 | 298 | * @brief DMA FIFO level |
| Kojto | 93:e188a91d3eaa | 299 | * @{ |
| Kojto | 93:e188a91d3eaa | 300 | */ |
| Kojto | 93:e188a91d3eaa | 301 | #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */ |
| Kojto | 93:e188a91d3eaa | 302 | #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ |
| Kojto | 93:e188a91d3eaa | 303 | #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ |
| Kojto | 93:e188a91d3eaa | 304 | #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ |
| Kojto | 93:e188a91d3eaa | 305 | /** |
| Kojto | 93:e188a91d3eaa | 306 | * @} |
| Kojto | 93:e188a91d3eaa | 307 | */ |
| Kojto | 93:e188a91d3eaa | 308 | |
| Kojto | 99:dbbf35b96557 | 309 | /** @defgroup DMA_Memory_burst DMA Memory burst |
| Kojto | 99:dbbf35b96557 | 310 | * @brief DMA memory burst |
| Kojto | 93:e188a91d3eaa | 311 | * @{ |
| Kojto | 93:e188a91d3eaa | 312 | */ |
| Kojto | 93:e188a91d3eaa | 313 | #define DMA_MBURST_SINGLE ((uint32_t)0x00000000) |
| Kojto | 93:e188a91d3eaa | 314 | #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) |
| Kojto | 93:e188a91d3eaa | 315 | #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) |
| Kojto | 93:e188a91d3eaa | 316 | #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) |
| Kojto | 93:e188a91d3eaa | 317 | /** |
| Kojto | 93:e188a91d3eaa | 318 | * @} |
| Kojto | 93:e188a91d3eaa | 319 | */ |
| Kojto | 93:e188a91d3eaa | 320 | |
| Kojto | 99:dbbf35b96557 | 321 | /** @defgroup DMA_Peripheral_burst DMA Peripheral burst |
| Kojto | 99:dbbf35b96557 | 322 | * @brief DMA peripheral burst |
| Kojto | 93:e188a91d3eaa | 323 | * @{ |
| Kojto | 93:e188a91d3eaa | 324 | */ |
| Kojto | 93:e188a91d3eaa | 325 | #define DMA_PBURST_SINGLE ((uint32_t)0x00000000) |
| Kojto | 93:e188a91d3eaa | 326 | #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) |
| Kojto | 93:e188a91d3eaa | 327 | #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) |
| Kojto | 93:e188a91d3eaa | 328 | #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) |
| Kojto | 93:e188a91d3eaa | 329 | /** |
| Kojto | 93:e188a91d3eaa | 330 | * @} |
| Kojto | 93:e188a91d3eaa | 331 | */ |
| Kojto | 93:e188a91d3eaa | 332 | |
| Kojto | 99:dbbf35b96557 | 333 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
| Kojto | 99:dbbf35b96557 | 334 | * @brief DMA interrupts definition |
| Kojto | 93:e188a91d3eaa | 335 | * @{ |
| Kojto | 93:e188a91d3eaa | 336 | */ |
| Kojto | 93:e188a91d3eaa | 337 | #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) |
| Kojto | 93:e188a91d3eaa | 338 | #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) |
| Kojto | 93:e188a91d3eaa | 339 | #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) |
| Kojto | 93:e188a91d3eaa | 340 | #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) |
| Kojto | 93:e188a91d3eaa | 341 | #define DMA_IT_FE ((uint32_t)0x00000080) |
| Kojto | 93:e188a91d3eaa | 342 | /** |
| Kojto | 93:e188a91d3eaa | 343 | * @} |
| Kojto | 93:e188a91d3eaa | 344 | */ |
| Kojto | 93:e188a91d3eaa | 345 | |
| Kojto | 99:dbbf35b96557 | 346 | /** @defgroup DMA_flag_definitions DMA flag definitions |
| Kojto | 99:dbbf35b96557 | 347 | * @brief DMA flag definitions |
| Kojto | 93:e188a91d3eaa | 348 | * @{ |
| Kojto | 93:e188a91d3eaa | 349 | */ |
| Kojto | 93:e188a91d3eaa | 350 | #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001) |
| Kojto | 93:e188a91d3eaa | 351 | #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004) |
| Kojto | 93:e188a91d3eaa | 352 | #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008) |
| Kojto | 93:e188a91d3eaa | 353 | #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010) |
| Kojto | 93:e188a91d3eaa | 354 | #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020) |
| Kojto | 93:e188a91d3eaa | 355 | #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040) |
| Kojto | 93:e188a91d3eaa | 356 | #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100) |
| Kojto | 93:e188a91d3eaa | 357 | #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200) |
| Kojto | 93:e188a91d3eaa | 358 | #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400) |
| Kojto | 93:e188a91d3eaa | 359 | #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800) |
| Kojto | 93:e188a91d3eaa | 360 | #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000) |
| Kojto | 93:e188a91d3eaa | 361 | #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000) |
| Kojto | 93:e188a91d3eaa | 362 | #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000) |
| Kojto | 93:e188a91d3eaa | 363 | #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000) |
| Kojto | 93:e188a91d3eaa | 364 | #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000) |
| Kojto | 93:e188a91d3eaa | 365 | #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000) |
| Kojto | 93:e188a91d3eaa | 366 | #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000) |
| Kojto | 93:e188a91d3eaa | 367 | #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000) |
| Kojto | 93:e188a91d3eaa | 368 | #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000) |
| Kojto | 93:e188a91d3eaa | 369 | #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000) |
| Kojto | 93:e188a91d3eaa | 370 | /** |
| Kojto | 93:e188a91d3eaa | 371 | * @} |
| Kojto | 93:e188a91d3eaa | 372 | */ |
| Kojto | 99:dbbf35b96557 | 373 | |
| Kojto | 93:e188a91d3eaa | 374 | /** |
| Kojto | 93:e188a91d3eaa | 375 | * @} |
| Kojto | 93:e188a91d3eaa | 376 | */ |
| Kojto | 99:dbbf35b96557 | 377 | |
| Kojto | 93:e188a91d3eaa | 378 | /* Exported macro ------------------------------------------------------------*/ |
| Kojto | 93:e188a91d3eaa | 379 | |
| Kojto | 93:e188a91d3eaa | 380 | /** @brief Reset DMA handle state |
| Kojto | 93:e188a91d3eaa | 381 | * @param __HANDLE__: specifies the DMA handle. |
| Kojto | 93:e188a91d3eaa | 382 | * @retval None |
| Kojto | 93:e188a91d3eaa | 383 | */ |
| Kojto | 93:e188a91d3eaa | 384 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| Kojto | 93:e188a91d3eaa | 385 | |
| Kojto | 93:e188a91d3eaa | 386 | /** |
| Kojto | 93:e188a91d3eaa | 387 | * @brief Return the current DMA Stream FIFO filled level. |
| Kojto | 93:e188a91d3eaa | 388 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 389 | * @retval The FIFO filling state. |
| Kojto | 93:e188a91d3eaa | 390 | * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full |
| Kojto | 93:e188a91d3eaa | 391 | * and not empty. |
| Kojto | 93:e188a91d3eaa | 392 | * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. |
| Kojto | 93:e188a91d3eaa | 393 | * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. |
| Kojto | 93:e188a91d3eaa | 394 | * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. |
| Kojto | 93:e188a91d3eaa | 395 | * - DMA_FIFOStatus_Empty: when FIFO is empty |
| Kojto | 93:e188a91d3eaa | 396 | * - DMA_FIFOStatus_Full: when FIFO is full |
| Kojto | 93:e188a91d3eaa | 397 | */ |
| Kojto | 93:e188a91d3eaa | 398 | #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) |
| Kojto | 93:e188a91d3eaa | 399 | |
| Kojto | 93:e188a91d3eaa | 400 | /** |
| Kojto | 93:e188a91d3eaa | 401 | * @brief Enable the specified DMA Stream. |
| Kojto | 93:e188a91d3eaa | 402 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 403 | * @retval None |
| Kojto | 93:e188a91d3eaa | 404 | */ |
| Kojto | 93:e188a91d3eaa | 405 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) |
| Kojto | 93:e188a91d3eaa | 406 | |
| Kojto | 93:e188a91d3eaa | 407 | /** |
| Kojto | 93:e188a91d3eaa | 408 | * @brief Disable the specified DMA Stream. |
| Kojto | 93:e188a91d3eaa | 409 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 410 | * @retval None |
| Kojto | 93:e188a91d3eaa | 411 | */ |
| Kojto | 93:e188a91d3eaa | 412 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) |
| Kojto | 93:e188a91d3eaa | 413 | |
| Kojto | 93:e188a91d3eaa | 414 | /* Interrupt & Flag management */ |
| Kojto | 93:e188a91d3eaa | 415 | |
| Kojto | 93:e188a91d3eaa | 416 | /** |
| Kojto | 93:e188a91d3eaa | 417 | * @brief Return the current DMA Stream transfer complete flag. |
| Kojto | 93:e188a91d3eaa | 418 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 419 | * @retval The specified transfer complete flag index. |
| Kojto | 93:e188a91d3eaa | 420 | */ |
| Kojto | 93:e188a91d3eaa | 421 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| Kojto | 93:e188a91d3eaa | 422 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 423 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 424 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 425 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 426 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 427 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 428 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 429 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 430 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 431 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 432 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 433 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 434 | DMA_FLAG_TCIF3_7) |
| Kojto | 93:e188a91d3eaa | 435 | |
| Kojto | 93:e188a91d3eaa | 436 | /** |
| Kojto | 93:e188a91d3eaa | 437 | * @brief Return the current DMA Stream half transfer complete flag. |
| Kojto | 93:e188a91d3eaa | 438 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 439 | * @retval The specified half transfer complete flag index. |
| Kojto | 93:e188a91d3eaa | 440 | */ |
| Kojto | 93:e188a91d3eaa | 441 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| Kojto | 93:e188a91d3eaa | 442 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 443 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 444 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 445 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 446 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 447 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 448 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 449 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 450 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 451 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 452 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 453 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 454 | DMA_FLAG_HTIF3_7) |
| Kojto | 93:e188a91d3eaa | 455 | |
| Kojto | 93:e188a91d3eaa | 456 | /** |
| Kojto | 93:e188a91d3eaa | 457 | * @brief Return the current DMA Stream transfer error flag. |
| Kojto | 93:e188a91d3eaa | 458 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 459 | * @retval The specified transfer error flag index. |
| Kojto | 93:e188a91d3eaa | 460 | */ |
| Kojto | 93:e188a91d3eaa | 461 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| Kojto | 93:e188a91d3eaa | 462 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 463 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 464 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 465 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 466 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 467 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 468 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 469 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 470 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 471 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 472 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 473 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 474 | DMA_FLAG_TEIF3_7) |
| Kojto | 93:e188a91d3eaa | 475 | |
| Kojto | 93:e188a91d3eaa | 476 | /** |
| Kojto | 93:e188a91d3eaa | 477 | * @brief Return the current DMA Stream FIFO error flag. |
| Kojto | 93:e188a91d3eaa | 478 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 479 | * @retval The specified FIFO error flag index. |
| Kojto | 93:e188a91d3eaa | 480 | */ |
| Kojto | 93:e188a91d3eaa | 481 | #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ |
| Kojto | 93:e188a91d3eaa | 482 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 483 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 484 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 485 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 486 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 487 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 488 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 489 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 490 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 491 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 492 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 493 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 494 | DMA_FLAG_FEIF3_7) |
| Kojto | 93:e188a91d3eaa | 495 | |
| Kojto | 93:e188a91d3eaa | 496 | /** |
| Kojto | 93:e188a91d3eaa | 497 | * @brief Return the current DMA Stream direct mode error flag. |
| Kojto | 93:e188a91d3eaa | 498 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 499 | * @retval The specified direct mode error flag index. |
| Kojto | 93:e188a91d3eaa | 500 | */ |
| Kojto | 93:e188a91d3eaa | 501 | #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ |
| Kojto | 93:e188a91d3eaa | 502 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 503 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 504 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 505 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
| Kojto | 93:e188a91d3eaa | 506 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 507 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 508 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 509 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
| Kojto | 93:e188a91d3eaa | 510 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 511 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 512 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 513 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
| Kojto | 93:e188a91d3eaa | 514 | DMA_FLAG_DMEIF3_7) |
| Kojto | 93:e188a91d3eaa | 515 | |
| Kojto | 93:e188a91d3eaa | 516 | /** |
| Kojto | 93:e188a91d3eaa | 517 | * @brief Get the DMA Stream pending flags. |
| Kojto | 93:e188a91d3eaa | 518 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 519 | * @param __FLAG__: Get the specified flag. |
| Kojto | 93:e188a91d3eaa | 520 | * This parameter can be any combination of the following values: |
| Kojto | 93:e188a91d3eaa | 521 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
| Kojto | 93:e188a91d3eaa | 522 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
| Kojto | 93:e188a91d3eaa | 523 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
| Kojto | 93:e188a91d3eaa | 524 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
| Kojto | 93:e188a91d3eaa | 525 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
| Kojto | 93:e188a91d3eaa | 526 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
| Kojto | 93:e188a91d3eaa | 527 | * @retval The state of FLAG (SET or RESET). |
| Kojto | 93:e188a91d3eaa | 528 | */ |
| Kojto | 93:e188a91d3eaa | 529 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
| Kojto | 93:e188a91d3eaa | 530 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ |
| Kojto | 93:e188a91d3eaa | 531 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ |
| Kojto | 93:e188a91d3eaa | 532 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) |
| Kojto | 93:e188a91d3eaa | 533 | |
| Kojto | 93:e188a91d3eaa | 534 | /** |
| Kojto | 93:e188a91d3eaa | 535 | * @brief Clear the DMA Stream pending flags. |
| Kojto | 93:e188a91d3eaa | 536 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 537 | * @param __FLAG__: specifies the flag to clear. |
| Kojto | 93:e188a91d3eaa | 538 | * This parameter can be any combination of the following values: |
| Kojto | 93:e188a91d3eaa | 539 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
| Kojto | 93:e188a91d3eaa | 540 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
| Kojto | 93:e188a91d3eaa | 541 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
| Kojto | 93:e188a91d3eaa | 542 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
| Kojto | 93:e188a91d3eaa | 543 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
| Kojto | 93:e188a91d3eaa | 544 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
| Kojto | 93:e188a91d3eaa | 545 | * @retval None |
| Kojto | 93:e188a91d3eaa | 546 | */ |
| Kojto | 93:e188a91d3eaa | 547 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| Kojto | 93:e188a91d3eaa | 548 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ |
| Kojto | 93:e188a91d3eaa | 549 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ |
| Kojto | 93:e188a91d3eaa | 550 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) |
| Kojto | 93:e188a91d3eaa | 551 | |
| Kojto | 93:e188a91d3eaa | 552 | /** |
| Kojto | 93:e188a91d3eaa | 553 | * @brief Enable the specified DMA Stream interrupts. |
| Kojto | 93:e188a91d3eaa | 554 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 555 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| Kojto | 93:e188a91d3eaa | 556 | * This parameter can be any combination of the following values: |
| Kojto | 93:e188a91d3eaa | 557 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| Kojto | 93:e188a91d3eaa | 558 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| Kojto | 93:e188a91d3eaa | 559 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| Kojto | 93:e188a91d3eaa | 560 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| Kojto | 93:e188a91d3eaa | 561 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| Kojto | 93:e188a91d3eaa | 562 | * @retval None |
| Kojto | 93:e188a91d3eaa | 563 | */ |
| Kojto | 93:e188a91d3eaa | 564 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| Kojto | 93:e188a91d3eaa | 565 | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) |
| Kojto | 93:e188a91d3eaa | 566 | |
| Kojto | 93:e188a91d3eaa | 567 | /** |
| Kojto | 93:e188a91d3eaa | 568 | * @brief Disable the specified DMA Stream interrupts. |
| Kojto | 93:e188a91d3eaa | 569 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 570 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| Kojto | 93:e188a91d3eaa | 571 | * This parameter can be any combination of the following values: |
| Kojto | 93:e188a91d3eaa | 572 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| Kojto | 93:e188a91d3eaa | 573 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| Kojto | 93:e188a91d3eaa | 574 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| Kojto | 93:e188a91d3eaa | 575 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| Kojto | 93:e188a91d3eaa | 576 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| Kojto | 93:e188a91d3eaa | 577 | * @retval None |
| Kojto | 93:e188a91d3eaa | 578 | */ |
| Kojto | 93:e188a91d3eaa | 579 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| Kojto | 93:e188a91d3eaa | 580 | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) |
| Kojto | 93:e188a91d3eaa | 581 | |
| Kojto | 93:e188a91d3eaa | 582 | /** |
| Kojto | 93:e188a91d3eaa | 583 | * @brief Check whether the specified DMA Stream interrupt has occurred or not. |
| Kojto | 93:e188a91d3eaa | 584 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 585 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| Kojto | 93:e188a91d3eaa | 586 | * This parameter can be one of the following values: |
| Kojto | 93:e188a91d3eaa | 587 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| Kojto | 93:e188a91d3eaa | 588 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| Kojto | 93:e188a91d3eaa | 589 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| Kojto | 93:e188a91d3eaa | 590 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| Kojto | 93:e188a91d3eaa | 591 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| Kojto | 93:e188a91d3eaa | 592 | * @retval The state of DMA_IT. |
| Kojto | 93:e188a91d3eaa | 593 | */ |
| Kojto | 93:e188a91d3eaa | 594 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| Kojto | 93:e188a91d3eaa | 595 | ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ |
| Kojto | 93:e188a91d3eaa | 596 | ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) |
| Kojto | 93:e188a91d3eaa | 597 | |
| Kojto | 93:e188a91d3eaa | 598 | /** |
| Kojto | 93:e188a91d3eaa | 599 | * @brief Writes the number of data units to be transferred on the DMA Stream. |
| Kojto | 93:e188a91d3eaa | 600 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 601 | * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) |
| Kojto | 93:e188a91d3eaa | 602 | * Number of data items depends only on the Peripheral data format. |
| Kojto | 93:e188a91d3eaa | 603 | * |
| Kojto | 93:e188a91d3eaa | 604 | * @note If Peripheral data format is Bytes: number of data units is equal |
| Kojto | 93:e188a91d3eaa | 605 | * to total number of bytes to be transferred. |
| Kojto | 93:e188a91d3eaa | 606 | * |
| Kojto | 93:e188a91d3eaa | 607 | * @note If Peripheral data format is Half-Word: number of data units is |
| Kojto | 93:e188a91d3eaa | 608 | * equal to total number of bytes to be transferred / 2. |
| Kojto | 93:e188a91d3eaa | 609 | * |
| Kojto | 93:e188a91d3eaa | 610 | * @note If Peripheral data format is Word: number of data units is equal |
| Kojto | 93:e188a91d3eaa | 611 | * to total number of bytes to be transferred / 4. |
| Kojto | 93:e188a91d3eaa | 612 | * |
| Kojto | 93:e188a91d3eaa | 613 | * @retval The number of remaining data units in the current DMAy Streamx transfer. |
| Kojto | 93:e188a91d3eaa | 614 | */ |
| Kojto | 93:e188a91d3eaa | 615 | #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) |
| Kojto | 93:e188a91d3eaa | 616 | |
| Kojto | 93:e188a91d3eaa | 617 | /** |
| Kojto | 93:e188a91d3eaa | 618 | * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. |
| Kojto | 93:e188a91d3eaa | 619 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 620 | * |
| Kojto | 93:e188a91d3eaa | 621 | * @retval The number of remaining data units in the current DMA Stream transfer. |
| Kojto | 93:e188a91d3eaa | 622 | */ |
| Kojto | 93:e188a91d3eaa | 623 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) |
| Kojto | 93:e188a91d3eaa | 624 | |
| Kojto | 93:e188a91d3eaa | 625 | |
| Kojto | 93:e188a91d3eaa | 626 | /* Include DMA HAL Extension module */ |
| Kojto | 93:e188a91d3eaa | 627 | #include "stm32f4xx_hal_dma_ex.h" |
| Kojto | 93:e188a91d3eaa | 628 | |
| Kojto | 93:e188a91d3eaa | 629 | /* Exported functions --------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 630 | |
| Kojto | 99:dbbf35b96557 | 631 | /** @defgroup DMA_Exported_Functions DMA Exported Functions |
| Kojto | 99:dbbf35b96557 | 632 | * @brief DMA Exported functions |
| Kojto | 99:dbbf35b96557 | 633 | * @{ |
| Kojto | 99:dbbf35b96557 | 634 | */ |
| Kojto | 99:dbbf35b96557 | 635 | |
| Kojto | 99:dbbf35b96557 | 636 | /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
| Kojto | 99:dbbf35b96557 | 637 | * @brief Initialization and de-initialization functions |
| Kojto | 99:dbbf35b96557 | 638 | * @{ |
| Kojto | 99:dbbf35b96557 | 639 | */ |
| Kojto | 93:e188a91d3eaa | 640 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| Kojto | 93:e188a91d3eaa | 641 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); |
| Kojto | 99:dbbf35b96557 | 642 | /** |
| Kojto | 99:dbbf35b96557 | 643 | * @} |
| Kojto | 99:dbbf35b96557 | 644 | */ |
| Kojto | 93:e188a91d3eaa | 645 | |
| Kojto | 99:dbbf35b96557 | 646 | /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions |
| Kojto | 99:dbbf35b96557 | 647 | * @brief I/O operation functions |
| Kojto | 99:dbbf35b96557 | 648 | * @{ |
| Kojto | 99:dbbf35b96557 | 649 | */ |
| Kojto | 93:e188a91d3eaa | 650 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| Kojto | 93:e188a91d3eaa | 651 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| Kojto | 93:e188a91d3eaa | 652 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| Kojto | 93:e188a91d3eaa | 653 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| Kojto | 93:e188a91d3eaa | 654 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| Kojto | 99:dbbf35b96557 | 655 | /** |
| Kojto | 99:dbbf35b96557 | 656 | * @} |
| Kojto | 99:dbbf35b96557 | 657 | */ |
| Kojto | 93:e188a91d3eaa | 658 | |
| Kojto | 99:dbbf35b96557 | 659 | /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions |
| Kojto | 99:dbbf35b96557 | 660 | * @brief Peripheral State functions |
| Kojto | 99:dbbf35b96557 | 661 | * @{ |
| Kojto | 99:dbbf35b96557 | 662 | */ |
| Kojto | 93:e188a91d3eaa | 663 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| Kojto | 93:e188a91d3eaa | 664 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| Kojto | 99:dbbf35b96557 | 665 | /** |
| Kojto | 99:dbbf35b96557 | 666 | * @} |
| Kojto | 99:dbbf35b96557 | 667 | */ |
| Kojto | 99:dbbf35b96557 | 668 | /** |
| Kojto | 99:dbbf35b96557 | 669 | * @} |
| Kojto | 99:dbbf35b96557 | 670 | */ |
| Kojto | 99:dbbf35b96557 | 671 | /* Private Constants -------------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 672 | /** @defgroup DMA_Private_Constants DMA Private Constants |
| Kojto | 99:dbbf35b96557 | 673 | * @brief DMA private defines and constants |
| Kojto | 99:dbbf35b96557 | 674 | * @{ |
| Kojto | 99:dbbf35b96557 | 675 | */ |
| Kojto | 99:dbbf35b96557 | 676 | /** |
| Kojto | 99:dbbf35b96557 | 677 | * @} |
| Kojto | 99:dbbf35b96557 | 678 | */ |
| Kojto | 99:dbbf35b96557 | 679 | |
| Kojto | 99:dbbf35b96557 | 680 | /* Private macros ------------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 681 | /** @defgroup DMA_Private_Macros DMA Private Macros |
| Kojto | 99:dbbf35b96557 | 682 | * @brief DMA private macros |
| Kojto | 99:dbbf35b96557 | 683 | * @{ |
| Kojto | 99:dbbf35b96557 | 684 | */ |
| Kojto | 99:dbbf35b96557 | 685 | #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ |
| Kojto | 99:dbbf35b96557 | 686 | ((CHANNEL) == DMA_CHANNEL_1) || \ |
| Kojto | 99:dbbf35b96557 | 687 | ((CHANNEL) == DMA_CHANNEL_2) || \ |
| Kojto | 99:dbbf35b96557 | 688 | ((CHANNEL) == DMA_CHANNEL_3) || \ |
| Kojto | 99:dbbf35b96557 | 689 | ((CHANNEL) == DMA_CHANNEL_4) || \ |
| Kojto | 99:dbbf35b96557 | 690 | ((CHANNEL) == DMA_CHANNEL_5) || \ |
| Kojto | 99:dbbf35b96557 | 691 | ((CHANNEL) == DMA_CHANNEL_6) || \ |
| Kojto | 99:dbbf35b96557 | 692 | ((CHANNEL) == DMA_CHANNEL_7)) |
| Kojto | 99:dbbf35b96557 | 693 | |
| Kojto | 99:dbbf35b96557 | 694 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| Kojto | 99:dbbf35b96557 | 695 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| Kojto | 99:dbbf35b96557 | 696 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| Kojto | 99:dbbf35b96557 | 697 | |
| Kojto | 99:dbbf35b96557 | 698 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| Kojto | 99:dbbf35b96557 | 699 | |
| Kojto | 99:dbbf35b96557 | 700 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| Kojto | 99:dbbf35b96557 | 701 | ((STATE) == DMA_PINC_DISABLE)) |
| Kojto | 99:dbbf35b96557 | 702 | |
| Kojto | 99:dbbf35b96557 | 703 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| Kojto | 99:dbbf35b96557 | 704 | ((STATE) == DMA_MINC_DISABLE)) |
| Kojto | 99:dbbf35b96557 | 705 | |
| Kojto | 99:dbbf35b96557 | 706 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| Kojto | 99:dbbf35b96557 | 707 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| Kojto | 99:dbbf35b96557 | 708 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| Kojto | 99:dbbf35b96557 | 709 | |
| Kojto | 99:dbbf35b96557 | 710 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| Kojto | 99:dbbf35b96557 | 711 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| Kojto | 99:dbbf35b96557 | 712 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| Kojto | 99:dbbf35b96557 | 713 | |
| Kojto | 99:dbbf35b96557 | 714 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| Kojto | 99:dbbf35b96557 | 715 | ((MODE) == DMA_CIRCULAR) || \ |
| Kojto | 99:dbbf35b96557 | 716 | ((MODE) == DMA_PFCTRL)) |
| Kojto | 99:dbbf35b96557 | 717 | |
| Kojto | 99:dbbf35b96557 | 718 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| Kojto | 99:dbbf35b96557 | 719 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| Kojto | 99:dbbf35b96557 | 720 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| Kojto | 99:dbbf35b96557 | 721 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| Kojto | 99:dbbf35b96557 | 722 | |
| Kojto | 99:dbbf35b96557 | 723 | #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ |
| Kojto | 99:dbbf35b96557 | 724 | ((STATE) == DMA_FIFOMODE_ENABLE)) |
| Kojto | 99:dbbf35b96557 | 725 | |
| Kojto | 99:dbbf35b96557 | 726 | #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ |
| Kojto | 99:dbbf35b96557 | 727 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ |
| Kojto | 99:dbbf35b96557 | 728 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ |
| Kojto | 99:dbbf35b96557 | 729 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) |
| Kojto | 99:dbbf35b96557 | 730 | |
| Kojto | 99:dbbf35b96557 | 731 | #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ |
| Kojto | 99:dbbf35b96557 | 732 | ((BURST) == DMA_MBURST_INC4) || \ |
| Kojto | 99:dbbf35b96557 | 733 | ((BURST) == DMA_MBURST_INC8) || \ |
| Kojto | 99:dbbf35b96557 | 734 | ((BURST) == DMA_MBURST_INC16)) |
| Kojto | 99:dbbf35b96557 | 735 | |
| Kojto | 99:dbbf35b96557 | 736 | #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ |
| Kojto | 99:dbbf35b96557 | 737 | ((BURST) == DMA_PBURST_INC4) || \ |
| Kojto | 99:dbbf35b96557 | 738 | ((BURST) == DMA_PBURST_INC8) || \ |
| Kojto | 99:dbbf35b96557 | 739 | ((BURST) == DMA_PBURST_INC16)) |
| Kojto | 99:dbbf35b96557 | 740 | /** |
| Kojto | 99:dbbf35b96557 | 741 | * @} |
| Kojto | 99:dbbf35b96557 | 742 | */ |
| Kojto | 99:dbbf35b96557 | 743 | |
| Kojto | 99:dbbf35b96557 | 744 | /* Private functions ---------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 745 | /** @defgroup DMA_Private_Functions DMA Private Functions |
| Kojto | 99:dbbf35b96557 | 746 | * @brief DMA private functions |
| Kojto | 99:dbbf35b96557 | 747 | * @{ |
| Kojto | 99:dbbf35b96557 | 748 | */ |
| Kojto | 99:dbbf35b96557 | 749 | /** |
| Kojto | 99:dbbf35b96557 | 750 | * @} |
| Kojto | 99:dbbf35b96557 | 751 | */ |
| Kojto | 93:e188a91d3eaa | 752 | |
| Kojto | 93:e188a91d3eaa | 753 | /** |
| Kojto | 93:e188a91d3eaa | 754 | * @} |
| Kojto | 93:e188a91d3eaa | 755 | */ |
| Kojto | 93:e188a91d3eaa | 756 | |
| Kojto | 93:e188a91d3eaa | 757 | /** |
| Kojto | 93:e188a91d3eaa | 758 | * @} |
| Kojto | 93:e188a91d3eaa | 759 | */ |
| Kojto | 93:e188a91d3eaa | 760 | |
| Kojto | 93:e188a91d3eaa | 761 | #ifdef __cplusplus |
| Kojto | 93:e188a91d3eaa | 762 | } |
| Kojto | 93:e188a91d3eaa | 763 | #endif |
| Kojto | 93:e188a91d3eaa | 764 | |
| Kojto | 93:e188a91d3eaa | 765 | #endif /* __STM32F4xx_HAL_DMA_H */ |
| Kojto | 93:e188a91d3eaa | 766 | |
| Kojto | 93:e188a91d3eaa | 767 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |