Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_ARCH_MAX/stm32f4xx_ll_fsmc.h@99:dbbf35b96557, 2015-05-13 (annotated)

Committer:
Kojto
Date:
Wed May 13 08:08:21 2015 +0200
Revision:
99:dbbf35b96557
Parent:
92:4fc01daae5a5
Child:
106:ba1f97679dad
Release 99 of the mbed library



Changes:

 - new targets - MAXWSNENV, DISCO_L053C8

 - STM32F4xx - ST Cube driver

 - KSDK mcu - SPI timing fix

 - Nordic - update to softdevice s130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_ll_fsmc.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
Kojto 99:dbbf35b96557 5 * @version V1.3.0
Kojto 99:dbbf35b96557 6 * @date 09-March-2015
bogdanm 89:552587b429a1 7 * @brief Header file of FSMC HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_LL_FSMC_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_LL_FSMC_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
Kojto 99:dbbf35b96557 52
Kojto 99:dbbf35b96557 53 /** @addtogroup FSMC_LL
bogdanm 89:552587b429a1 54 * @{
Kojto 99:dbbf35b96557 55 */
bogdanm 89:552587b429a1 56
Kojto 99:dbbf35b96557 57 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 58 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 59 /** @defgroup FSMC_LL_Private_Types FSMC Private Types
Kojto 99:dbbf35b96557 60 * @{
Kojto 99:dbbf35b96557 61 */
bogdanm 89:552587b429a1 62
bogdanm 89:552587b429a1 63 /**
Kojto 99:dbbf35b96557 64 * @brief FSMC NORSRAM Configuration Structure definition
bogdanm 89:552587b429a1 65 */
bogdanm 89:552587b429a1 66 typedef struct
bogdanm 89:552587b429a1 67 {
bogdanm 89:552587b429a1 68 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm 89:552587b429a1 69 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
bogdanm 89:552587b429a1 70
bogdanm 89:552587b429a1 71 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm 89:552587b429a1 72 multiplexed on the data bus or not.
bogdanm 89:552587b429a1 73 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
bogdanm 89:552587b429a1 74
bogdanm 89:552587b429a1 75 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm 89:552587b429a1 76 the corresponding memory device.
bogdanm 89:552587b429a1 77 This parameter can be a value of @ref FSMC_Memory_Type */
bogdanm 89:552587b429a1 78
bogdanm 89:552587b429a1 79 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 89:552587b429a1 80 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
bogdanm 89:552587b429a1 81
bogdanm 89:552587b429a1 82 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm 89:552587b429a1 83 valid only with synchronous burst Flash memories.
bogdanm 89:552587b429a1 84 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
bogdanm 89:552587b429a1 85
bogdanm 89:552587b429a1 86 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm 89:552587b429a1 87 the Flash memory in burst mode.
bogdanm 89:552587b429a1 88 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
bogdanm 89:552587b429a1 89
bogdanm 89:552587b429a1 90 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm 89:552587b429a1 91 memory, valid only when accessing Flash memories in burst mode.
bogdanm 89:552587b429a1 92 This parameter can be a value of @ref FSMC_Wrap_Mode */
bogdanm 89:552587b429a1 93
bogdanm 89:552587b429a1 94 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm 89:552587b429a1 95 clock cycle before the wait state or during the wait state,
bogdanm 89:552587b429a1 96 valid only when accessing memories in burst mode.
bogdanm 89:552587b429a1 97 This parameter can be a value of @ref FSMC_Wait_Timing */
bogdanm 89:552587b429a1 98
bogdanm 89:552587b429a1 99 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
bogdanm 89:552587b429a1 100 This parameter can be a value of @ref FSMC_Write_Operation */
bogdanm 89:552587b429a1 101
bogdanm 89:552587b429a1 102 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
bogdanm 89:552587b429a1 103 signal, valid for Flash memory access in burst mode.
bogdanm 89:552587b429a1 104 This parameter can be a value of @ref FSMC_Wait_Signal */
bogdanm 89:552587b429a1 105
bogdanm 89:552587b429a1 106 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm 89:552587b429a1 107 This parameter can be a value of @ref FSMC_Extended_Mode */
bogdanm 89:552587b429a1 108
bogdanm 89:552587b429a1 109 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm 89:552587b429a1 110 valid only with asynchronous Flash memories.
bogdanm 89:552587b429a1 111 This parameter can be a value of @ref FSMC_AsynchronousWait */
bogdanm 89:552587b429a1 112
bogdanm 89:552587b429a1 113 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm 89:552587b429a1 114 This parameter can be a value of @ref FSMC_Write_Burst */
bogdanm 89:552587b429a1 115
bogdanm 89:552587b429a1 116 }FSMC_NORSRAM_InitTypeDef;
bogdanm 89:552587b429a1 117
bogdanm 89:552587b429a1 118 /**
Kojto 99:dbbf35b96557 119 * @brief FSMC NORSRAM Timing parameters structure definition
bogdanm 89:552587b429a1 120 */
bogdanm 89:552587b429a1 121 typedef struct
bogdanm 89:552587b429a1 122 {
bogdanm 89:552587b429a1 123 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 124 the duration of the address setup time.
bogdanm 89:552587b429a1 125 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 89:552587b429a1 126 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 89:552587b429a1 127
bogdanm 89:552587b429a1 128 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 129 the duration of the address hold time.
bogdanm 89:552587b429a1 130 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm 89:552587b429a1 131 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 89:552587b429a1 132
bogdanm 89:552587b429a1 133 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 134 the duration of the data setup time.
bogdanm 89:552587b429a1 135 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
bogdanm 89:552587b429a1 136 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm 89:552587b429a1 137 NOR Flash memories. */
bogdanm 89:552587b429a1 138
bogdanm 89:552587b429a1 139 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 140 the duration of the bus turnaround.
bogdanm 89:552587b429a1 141 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 89:552587b429a1 142 @note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm 89:552587b429a1 143
bogdanm 89:552587b429a1 144 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm 89:552587b429a1 145 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
bogdanm 89:552587b429a1 146 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm 89:552587b429a1 147 accesses. */
bogdanm 89:552587b429a1 148
bogdanm 89:552587b429a1 149 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm 89:552587b429a1 150 to the memory before getting the first data.
bogdanm 89:552587b429a1 151 The parameter value depends on the memory type as shown below:
bogdanm 89:552587b429a1 152 - It must be set to 0 in case of a CRAM
bogdanm 89:552587b429a1 153 - It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm 89:552587b429a1 154 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm 89:552587b429a1 155 with synchronous burst mode enable */
bogdanm 89:552587b429a1 156
bogdanm 89:552587b429a1 157 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm 89:552587b429a1 158 This parameter can be a value of @ref FSMC_Access_Mode */
bogdanm 89:552587b429a1 159
bogdanm 89:552587b429a1 160 }FSMC_NORSRAM_TimingTypeDef;
bogdanm 89:552587b429a1 161
bogdanm 89:552587b429a1 162 /**
Kojto 99:dbbf35b96557 163 * @brief FSMC NAND Configuration Structure definition
bogdanm 89:552587b429a1 164 */
bogdanm 89:552587b429a1 165 typedef struct
bogdanm 89:552587b429a1 166 {
bogdanm 89:552587b429a1 167 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm 89:552587b429a1 168 This parameter can be a value of @ref FSMC_NAND_Bank */
bogdanm 89:552587b429a1 169
bogdanm 89:552587b429a1 170 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
bogdanm 89:552587b429a1 171 This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm 89:552587b429a1 172
bogdanm 89:552587b429a1 173 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 89:552587b429a1 174 This parameter can be any value of @ref FSMC_NAND_Data_Width */
bogdanm 89:552587b429a1 175
bogdanm 89:552587b429a1 176 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
bogdanm 89:552587b429a1 177 This parameter can be any value of @ref FSMC_ECC */
bogdanm 89:552587b429a1 178
bogdanm 89:552587b429a1 179 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm 89:552587b429a1 180 This parameter can be any value of @ref FSMC_ECC_Page_Size */
bogdanm 89:552587b429a1 181
bogdanm 89:552587b429a1 182 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 183 delay between CLE low and RE low.
bogdanm 89:552587b429a1 184 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 185
bogdanm 89:552587b429a1 186 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 187 delay between ALE low and RE low.
bogdanm 89:552587b429a1 188 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 189
bogdanm 89:552587b429a1 190 }FSMC_NAND_InitTypeDef;
bogdanm 89:552587b429a1 191
bogdanm 89:552587b429a1 192 /**
Kojto 99:dbbf35b96557 193 * @brief FSMC NAND/PCCARD Timing parameters structure definition
bogdanm 89:552587b429a1 194 */
bogdanm 89:552587b429a1 195 typedef struct
bogdanm 89:552587b429a1 196 {
bogdanm 89:552587b429a1 197 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm 89:552587b429a1 198 the command assertion for NAND-Flash read or write access
bogdanm 89:552587b429a1 199 to common/Attribute or I/O memory space (depending on
bogdanm 89:552587b429a1 200 the memory space timing to be configured).
bogdanm 89:552587b429a1 201 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 202
bogdanm 89:552587b429a1 203 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm 89:552587b429a1 204 command for NAND-Flash read or write access to
bogdanm 89:552587b429a1 205 common/Attribute or I/O memory space (depending on the
bogdanm 89:552587b429a1 206 memory space timing to be configured).
bogdanm 89:552587b429a1 207 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 208
bogdanm 89:552587b429a1 209 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm 89:552587b429a1 210 (and data for write access) after the command de-assertion
bogdanm 89:552587b429a1 211 for NAND-Flash read or write access to common/Attribute
bogdanm 89:552587b429a1 212 or I/O memory space (depending on the memory space timing
bogdanm 89:552587b429a1 213 to be configured).
bogdanm 89:552587b429a1 214 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 215
bogdanm 89:552587b429a1 216 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm 89:552587b429a1 217 data bus is kept in HiZ after the start of a NAND-Flash
bogdanm 89:552587b429a1 218 write access to common/Attribute or I/O memory space (depending
bogdanm 89:552587b429a1 219 on the memory space timing to be configured).
bogdanm 89:552587b429a1 220 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 221
bogdanm 89:552587b429a1 222 }FSMC_NAND_PCC_TimingTypeDef;
bogdanm 89:552587b429a1 223
bogdanm 89:552587b429a1 224 /**
Kojto 99:dbbf35b96557 225 * @brief FSMC NAND Configuration Structure definition
bogdanm 89:552587b429a1 226 */
bogdanm 89:552587b429a1 227 typedef struct
bogdanm 89:552587b429a1 228 {
bogdanm 89:552587b429a1 229 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
bogdanm 89:552587b429a1 230 This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm 89:552587b429a1 231
bogdanm 89:552587b429a1 232 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 233 delay between CLE low and RE low.
bogdanm 89:552587b429a1 234 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 235
bogdanm 89:552587b429a1 236 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 237 delay between ALE low and RE low.
bogdanm 89:552587b429a1 238 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 239
bogdanm 89:552587b429a1 240 }FSMC_PCCARD_InitTypeDef;
Kojto 99:dbbf35b96557 241 /**
Kojto 99:dbbf35b96557 242 * @}
Kojto 99:dbbf35b96557 243 */
bogdanm 89:552587b429a1 244
Kojto 99:dbbf35b96557 245 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 246 /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
Kojto 99:dbbf35b96557 247 * @{
Kojto 99:dbbf35b96557 248 */
bogdanm 89:552587b429a1 249
Kojto 99:dbbf35b96557 250 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
bogdanm 89:552587b429a1 251 * @{
bogdanm 89:552587b429a1 252 */
Kojto 99:dbbf35b96557 253 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
bogdanm 89:552587b429a1 254 * @{
bogdanm 89:552587b429a1 255 */
bogdanm 89:552587b429a1 256 #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 257 #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 258 #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 259 #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
bogdanm 89:552587b429a1 260 /**
bogdanm 89:552587b429a1 261 * @}
bogdanm 89:552587b429a1 262 */
bogdanm 89:552587b429a1 263
Kojto 99:dbbf35b96557 264 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
bogdanm 89:552587b429a1 265 * @{
bogdanm 89:552587b429a1 266 */
bogdanm 89:552587b429a1 267 #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 268 #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 269 /**
bogdanm 89:552587b429a1 270 * @}
bogdanm 89:552587b429a1 271 */
bogdanm 89:552587b429a1 272
Kojto 99:dbbf35b96557 273 /** @defgroup FSMC_Memory_Type FSMC Memory Type
bogdanm 89:552587b429a1 274 * @{
bogdanm 89:552587b429a1 275 */
bogdanm 89:552587b429a1 276 #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 277 #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 278 #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 279 /**
bogdanm 89:552587b429a1 280 * @}
bogdanm 89:552587b429a1 281 */
bogdanm 89:552587b429a1 282
Kojto 99:dbbf35b96557 283 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
bogdanm 89:552587b429a1 284 * @{
bogdanm 89:552587b429a1 285 */
bogdanm 89:552587b429a1 286 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 287 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 288 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 289 /**
bogdanm 89:552587b429a1 290 * @}
bogdanm 89:552587b429a1 291 */
bogdanm 89:552587b429a1 292
Kojto 99:dbbf35b96557 293 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
bogdanm 89:552587b429a1 294 * @{
bogdanm 89:552587b429a1 295 */
bogdanm 89:552587b429a1 296 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 297 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 298 /**
bogdanm 89:552587b429a1 299 * @}
bogdanm 89:552587b429a1 300 */
bogdanm 89:552587b429a1 301
Kojto 99:dbbf35b96557 302 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
bogdanm 89:552587b429a1 303 * @{
bogdanm 89:552587b429a1 304 */
bogdanm 89:552587b429a1 305 #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 306 #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 307 /**
bogdanm 89:552587b429a1 308 * @}
bogdanm 89:552587b429a1 309 */
bogdanm 89:552587b429a1 310
Kojto 99:dbbf35b96557 311 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
bogdanm 89:552587b429a1 312 * @{
bogdanm 89:552587b429a1 313 */
bogdanm 89:552587b429a1 314 #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 315 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 316 /**
bogdanm 89:552587b429a1 317 * @}
bogdanm 89:552587b429a1 318 */
bogdanm 89:552587b429a1 319
Kojto 99:dbbf35b96557 320 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
Kojto 99:dbbf35b96557 321 * @{
Kojto 99:dbbf35b96557 322 */
Kojto 99:dbbf35b96557 323 #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 324 #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
Kojto 99:dbbf35b96557 325 /**
Kojto 99:dbbf35b96557 326 * @}
Kojto 99:dbbf35b96557 327 */
Kojto 99:dbbf35b96557 328
Kojto 99:dbbf35b96557 329 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
bogdanm 89:552587b429a1 330 * @{
bogdanm 89:552587b429a1 331 */
bogdanm 89:552587b429a1 332 #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 333 #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 334 /**
bogdanm 89:552587b429a1 335 * @}
bogdanm 89:552587b429a1 336 */
bogdanm 89:552587b429a1 337
Kojto 99:dbbf35b96557 338 /** @defgroup FSMC_Write_Operation FSMC Write Operation
bogdanm 89:552587b429a1 339 * @{
bogdanm 89:552587b429a1 340 */
bogdanm 89:552587b429a1 341 #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 342 #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 343 /**
bogdanm 89:552587b429a1 344 * @}
bogdanm 89:552587b429a1 345 */
bogdanm 89:552587b429a1 346
Kojto 99:dbbf35b96557 347 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
Kojto 99:dbbf35b96557 348 * @{
Kojto 99:dbbf35b96557 349 */
Kojto 99:dbbf35b96557 350 #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 351 #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
Kojto 99:dbbf35b96557 352 /**
Kojto 99:dbbf35b96557 353 * @}
Kojto 99:dbbf35b96557 354 */
Kojto 99:dbbf35b96557 355
Kojto 99:dbbf35b96557 356 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
Kojto 99:dbbf35b96557 357 * @{
Kojto 99:dbbf35b96557 358 */
Kojto 99:dbbf35b96557 359 #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 360 #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
Kojto 99:dbbf35b96557 361 /**
Kojto 99:dbbf35b96557 362 * @}
Kojto 99:dbbf35b96557 363 */
Kojto 99:dbbf35b96557 364
Kojto 99:dbbf35b96557 365 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
bogdanm 89:552587b429a1 366 * @{
bogdanm 89:552587b429a1 367 */
bogdanm 89:552587b429a1 368 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 369 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 370 /**
bogdanm 89:552587b429a1 371 * @}
bogdanm 89:552587b429a1 372 */
bogdanm 89:552587b429a1 373
Kojto 99:dbbf35b96557 374 /** @defgroup FSMC_Write_Burst FSMC Write Burst
bogdanm 89:552587b429a1 375 * @{
bogdanm 89:552587b429a1 376 */
bogdanm 89:552587b429a1 377 #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 378 #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 379 /**
bogdanm 89:552587b429a1 380 * @}
bogdanm 89:552587b429a1 381 */
bogdanm 89:552587b429a1 382
Kojto 99:dbbf35b96557 383 /** @defgroup FSMC_Continous_Clock FSMC Continous Clock
bogdanm 89:552587b429a1 384 * @{
bogdanm 89:552587b429a1 385 */
Kojto 99:dbbf35b96557 386 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 387 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 388 /**
bogdanm 89:552587b429a1 389 * @}
bogdanm 89:552587b429a1 390 */
bogdanm 89:552587b429a1 391
Kojto 99:dbbf35b96557 392 /** @defgroup FSMC_Access_Mode FSMC Access Mode
bogdanm 89:552587b429a1 393 * @{
bogdanm 89:552587b429a1 394 */
bogdanm 89:552587b429a1 395 #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 396 #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 397 #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 398 #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
bogdanm 89:552587b429a1 399 /**
bogdanm 89:552587b429a1 400 * @}
bogdanm 89:552587b429a1 401 */
bogdanm 89:552587b429a1 402 /**
bogdanm 89:552587b429a1 403 * @}
bogdanm 89:552587b429a1 404 */
bogdanm 89:552587b429a1 405
Kojto 99:dbbf35b96557 406 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
Kojto 99:dbbf35b96557 407 * @{
Kojto 99:dbbf35b96557 408 */
Kojto 99:dbbf35b96557 409 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
Kojto 99:dbbf35b96557 410 * @{
Kojto 99:dbbf35b96557 411 */
Kojto 99:dbbf35b96557 412 #define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
Kojto 99:dbbf35b96557 413 #define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
Kojto 99:dbbf35b96557 414 /**
Kojto 99:dbbf35b96557 415 * @}
Kojto 99:dbbf35b96557 416 */
Kojto 99:dbbf35b96557 417
Kojto 99:dbbf35b96557 418 /** @defgroup FSMC_Wait_feature FSMC Wait feature
bogdanm 89:552587b429a1 419 * @{
bogdanm 89:552587b429a1 420 */
bogdanm 89:552587b429a1 421 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 422 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 423 /**
bogdanm 89:552587b429a1 424 * @}
bogdanm 89:552587b429a1 425 */
bogdanm 89:552587b429a1 426
Kojto 99:dbbf35b96557 427 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
bogdanm 89:552587b429a1 428 * @{
bogdanm 89:552587b429a1 429 */
bogdanm 89:552587b429a1 430 #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 431 #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 432 /**
bogdanm 89:552587b429a1 433 * @}
bogdanm 89:552587b429a1 434 */
bogdanm 89:552587b429a1 435
Kojto 99:dbbf35b96557 436 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
bogdanm 89:552587b429a1 437 * @{
bogdanm 89:552587b429a1 438 */
bogdanm 89:552587b429a1 439 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 440 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 441 /**
bogdanm 89:552587b429a1 442 * @}
bogdanm 89:552587b429a1 443 */
bogdanm 89:552587b429a1 444
Kojto 99:dbbf35b96557 445 /** @defgroup FSMC_ECC FSMC ECC
bogdanm 89:552587b429a1 446 * @{
bogdanm 89:552587b429a1 447 */
bogdanm 89:552587b429a1 448 #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 449 #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 450 /**
bogdanm 89:552587b429a1 451 * @}
bogdanm 89:552587b429a1 452 */
bogdanm 89:552587b429a1 453
Kojto 99:dbbf35b96557 454 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
bogdanm 89:552587b429a1 455 * @{
bogdanm 89:552587b429a1 456 */
bogdanm 89:552587b429a1 457 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 458 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 459 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 460 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
bogdanm 89:552587b429a1 461 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 462 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
bogdanm 89:552587b429a1 463 /**
bogdanm 89:552587b429a1 464 * @}
bogdanm 89:552587b429a1 465 */
bogdanm 89:552587b429a1 466 /**
bogdanm 89:552587b429a1 467 * @}
bogdanm 89:552587b429a1 468 */
bogdanm 89:552587b429a1 469
Kojto 99:dbbf35b96557 470 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
bogdanm 89:552587b429a1 471 * @{
bogdanm 89:552587b429a1 472 */
bogdanm 89:552587b429a1 473 #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 474 #define FSMC_IT_LEVEL ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 475 #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 476 #define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 477 /**
bogdanm 89:552587b429a1 478 * @}
bogdanm 89:552587b429a1 479 */
bogdanm 89:552587b429a1 480
Kojto 99:dbbf35b96557 481 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
bogdanm 89:552587b429a1 482 * @{
bogdanm 89:552587b429a1 483 */
bogdanm 89:552587b429a1 484 #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 485 #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 486 #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 487 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 488 /**
bogdanm 89:552587b429a1 489 * @}
bogdanm 89:552587b429a1 490 */
bogdanm 89:552587b429a1 491
Kojto 99:dbbf35b96557 492 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
Kojto 99:dbbf35b96557 493 * @{
bogdanm 89:552587b429a1 494 */
Kojto 99:dbbf35b96557 495 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
Kojto 99:dbbf35b96557 496 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
Kojto 99:dbbf35b96557 497 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
Kojto 99:dbbf35b96557 498 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
bogdanm 89:552587b429a1 499
Kojto 99:dbbf35b96557 500 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
Kojto 99:dbbf35b96557 501 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
Kojto 99:dbbf35b96557 502 #define FSMC_NAND_DEVICE FSMC_Bank2_3
Kojto 99:dbbf35b96557 503 #define FSMC_PCCARD_DEVICE FSMC_Bank4
bogdanm 89:552587b429a1 504
bogdanm 89:552587b429a1 505 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
bogdanm 89:552587b429a1 506 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
bogdanm 89:552587b429a1 507 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
bogdanm 89:552587b429a1 508 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
bogdanm 89:552587b429a1 509
bogdanm 89:552587b429a1 510 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
bogdanm 89:552587b429a1 511 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
bogdanm 89:552587b429a1 512 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
bogdanm 89:552587b429a1 513 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
bogdanm 89:552587b429a1 514 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
bogdanm 89:552587b429a1 515 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
bogdanm 89:552587b429a1 516
bogdanm 89:552587b429a1 517 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
bogdanm 89:552587b429a1 518 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
bogdanm 89:552587b429a1 519
bogdanm 89:552587b429a1 520 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
bogdanm 89:552587b429a1 521 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
bogdanm 89:552587b429a1 522 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
bogdanm 89:552587b429a1 523
bogdanm 89:552587b429a1 524 #define FMC_NAND_Init FSMC_NAND_Init
bogdanm 89:552587b429a1 525 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
bogdanm 89:552587b429a1 526 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
bogdanm 89:552587b429a1 527 #define FMC_NAND_DeInit FSMC_NAND_DeInit
bogdanm 89:552587b429a1 528 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
bogdanm 89:552587b429a1 529 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
bogdanm 89:552587b429a1 530 #define FMC_NAND_GetECC FSMC_NAND_GetECC
bogdanm 89:552587b429a1 531 #define FMC_PCCARD_Init FSMC_PCCARD_Init
bogdanm 89:552587b429a1 532 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
bogdanm 89:552587b429a1 533 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
bogdanm 89:552587b429a1 534 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
bogdanm 89:552587b429a1 535 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
bogdanm 89:552587b429a1 536
bogdanm 89:552587b429a1 537 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
bogdanm 89:552587b429a1 538 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
bogdanm 89:552587b429a1 539 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
bogdanm 89:552587b429a1 540 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
bogdanm 89:552587b429a1 541 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
bogdanm 89:552587b429a1 542 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
bogdanm 89:552587b429a1 543 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
bogdanm 89:552587b429a1 544 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
bogdanm 89:552587b429a1 545 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
bogdanm 89:552587b429a1 546 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
bogdanm 89:552587b429a1 547 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
bogdanm 89:552587b429a1 548 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
bogdanm 89:552587b429a1 549
bogdanm 89:552587b429a1 550 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
bogdanm 89:552587b429a1 551 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
bogdanm 89:552587b429a1 552 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
bogdanm 89:552587b429a1 553 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
bogdanm 89:552587b429a1 554
bogdanm 89:552587b429a1 555 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
bogdanm 89:552587b429a1 556 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
bogdanm 89:552587b429a1 557 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
bogdanm 89:552587b429a1 558 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
bogdanm 89:552587b429a1 559
bogdanm 89:552587b429a1 560 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
bogdanm 89:552587b429a1 561
bogdanm 92:4fc01daae5a5 562 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
bogdanm 92:4fc01daae5a5 563 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
bogdanm 92:4fc01daae5a5 564 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
bogdanm 92:4fc01daae5a5 565
bogdanm 89:552587b429a1 566 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
bogdanm 89:552587b429a1 567 #define FMC_IT_LEVEL FSMC_IT_LEVEL
bogdanm 89:552587b429a1 568 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
bogdanm 89:552587b429a1 569 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
bogdanm 89:552587b429a1 570
bogdanm 89:552587b429a1 571 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
bogdanm 89:552587b429a1 572 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
bogdanm 89:552587b429a1 573 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
bogdanm 89:552587b429a1 574 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
Kojto 99:dbbf35b96557 575 /**
Kojto 99:dbbf35b96557 576 * @}
Kojto 99:dbbf35b96557 577 */
bogdanm 89:552587b429a1 578
Kojto 99:dbbf35b96557 579 /**
Kojto 99:dbbf35b96557 580 * @}
Kojto 99:dbbf35b96557 581 */
Kojto 99:dbbf35b96557 582
Kojto 99:dbbf35b96557 583 /* Private macro -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 584 /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
Kojto 99:dbbf35b96557 585 * @{
Kojto 99:dbbf35b96557 586 */
Kojto 99:dbbf35b96557 587
Kojto 99:dbbf35b96557 588 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
Kojto 99:dbbf35b96557 589 * @brief macros to handle NOR device enable/disable and read/write operations
Kojto 99:dbbf35b96557 590 * @{
Kojto 99:dbbf35b96557 591 */
Kojto 99:dbbf35b96557 592 /**
Kojto 99:dbbf35b96557 593 * @brief Enable the NORSRAM device access.
Kojto 99:dbbf35b96557 594 * @param __INSTANCE__: FSMC_NORSRAM Instance
Kojto 99:dbbf35b96557 595 * @param __BANK__: FSMC_NORSRAM Bank
Kojto 99:dbbf35b96557 596 * @retval none
Kojto 99:dbbf35b96557 597 */
Kojto 99:dbbf35b96557 598 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
Kojto 99:dbbf35b96557 599
Kojto 99:dbbf35b96557 600 /**
Kojto 99:dbbf35b96557 601 * @brief Disable the NORSRAM device access.
Kojto 99:dbbf35b96557 602 * @param __INSTANCE__: FSMC_NORSRAM Instance
Kojto 99:dbbf35b96557 603 * @param __BANK__: FSMC_NORSRAM Bank
Kojto 99:dbbf35b96557 604 * @retval none
Kojto 99:dbbf35b96557 605 */
Kojto 99:dbbf35b96557 606 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
Kojto 99:dbbf35b96557 607 /**
Kojto 99:dbbf35b96557 608 * @}
Kojto 99:dbbf35b96557 609 */
Kojto 99:dbbf35b96557 610
Kojto 99:dbbf35b96557 611 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
Kojto 99:dbbf35b96557 612 * @brief macros to handle NAND device enable/disable
Kojto 99:dbbf35b96557 613 * @{
Kojto 99:dbbf35b96557 614 */
Kojto 99:dbbf35b96557 615 /**
Kojto 99:dbbf35b96557 616 * @brief Enable the NAND device access.
Kojto 99:dbbf35b96557 617 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 618 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 619 * @retval none
Kojto 99:dbbf35b96557 620 */
Kojto 99:dbbf35b96557 621 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
Kojto 99:dbbf35b96557 622 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
Kojto 99:dbbf35b96557 623
Kojto 99:dbbf35b96557 624 /**
Kojto 99:dbbf35b96557 625 * @brief Disable the NAND device access.
Kojto 99:dbbf35b96557 626 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 627 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 628 * @retval none
Kojto 99:dbbf35b96557 629 */
Kojto 99:dbbf35b96557 630 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
Kojto 99:dbbf35b96557 631 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
Kojto 99:dbbf35b96557 632 /**
Kojto 99:dbbf35b96557 633 * @}
Kojto 99:dbbf35b96557 634 */
Kojto 99:dbbf35b96557 635
Kojto 99:dbbf35b96557 636 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
Kojto 99:dbbf35b96557 637 * @brief macros to handle SRAM read/write operations
Kojto 99:dbbf35b96557 638 * @{
Kojto 99:dbbf35b96557 639 */
Kojto 99:dbbf35b96557 640 /**
Kojto 99:dbbf35b96557 641 * @brief Enable the PCCARD device access.
Kojto 99:dbbf35b96557 642 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 643 * @retval none
Kojto 99:dbbf35b96557 644 */
Kojto 99:dbbf35b96557 645 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
Kojto 99:dbbf35b96557 646
Kojto 99:dbbf35b96557 647 /**
Kojto 99:dbbf35b96557 648 * @brief Disable the PCCARD device access.
Kojto 99:dbbf35b96557 649 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 650 * @retval none
Kojto 99:dbbf35b96557 651 */
Kojto 99:dbbf35b96557 652 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
Kojto 99:dbbf35b96557 653 /**
Kojto 99:dbbf35b96557 654 * @}
Kojto 99:dbbf35b96557 655 */
Kojto 99:dbbf35b96557 656
Kojto 99:dbbf35b96557 657 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
Kojto 99:dbbf35b96557 658 * @brief macros to handle FSMC flags and interrupts
Kojto 99:dbbf35b96557 659 * @{
Kojto 99:dbbf35b96557 660 */
Kojto 99:dbbf35b96557 661 /**
Kojto 99:dbbf35b96557 662 * @brief Enable the NAND device interrupt.
Kojto 99:dbbf35b96557 663 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 664 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 665 * @param __INTERRUPT__: FSMC_NAND interrupt
Kojto 99:dbbf35b96557 666 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 667 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 668 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 669 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 670 * @retval None
Kojto 99:dbbf35b96557 671 */
Kojto 99:dbbf35b96557 672 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
Kojto 99:dbbf35b96557 673 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
Kojto 99:dbbf35b96557 674
Kojto 99:dbbf35b96557 675 /**
Kojto 99:dbbf35b96557 676 * @brief Disable the NAND device interrupt.
Kojto 99:dbbf35b96557 677 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 678 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 679 * @param __INTERRUPT__: FSMC_NAND interrupt
Kojto 99:dbbf35b96557 680 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 681 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 682 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 683 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 684 * @retval None
Kojto 99:dbbf35b96557 685 */
Kojto 99:dbbf35b96557 686 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
Kojto 99:dbbf35b96557 687 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
Kojto 99:dbbf35b96557 688
Kojto 99:dbbf35b96557 689 /**
Kojto 99:dbbf35b96557 690 * @brief Get flag status of the NAND device.
Kojto 99:dbbf35b96557 691 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 692 * @param __BANK__ : FSMC_NAND Bank
Kojto 99:dbbf35b96557 693 * @param __FLAG__ : FSMC_NAND flag
Kojto 99:dbbf35b96557 694 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 695 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 696 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 697 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 698 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 699 * @retval The state of FLAG (SET or RESET).
Kojto 99:dbbf35b96557 700 */
Kojto 99:dbbf35b96557 701 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
Kojto 99:dbbf35b96557 702 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
Kojto 99:dbbf35b96557 703 /**
Kojto 99:dbbf35b96557 704 * @brief Clear flag status of the NAND device.
Kojto 99:dbbf35b96557 705 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 706 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 707 * @param __FLAG__: FSMC_NAND flag
Kojto 99:dbbf35b96557 708 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 709 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 710 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 711 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 712 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 713 * @retval None
Kojto 99:dbbf35b96557 714 */
Kojto 99:dbbf35b96557 715 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto 99:dbbf35b96557 716 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto 99:dbbf35b96557 717 /**
Kojto 99:dbbf35b96557 718 * @brief Enable the PCCARD device interrupt.
Kojto 99:dbbf35b96557 719 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 720 * @param __INTERRUPT__: FSMC_PCCARD interrupt
Kojto 99:dbbf35b96557 721 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 722 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 723 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 724 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 725 * @retval None
Kojto 99:dbbf35b96557 726 */
Kojto 99:dbbf35b96557 727 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
Kojto 99:dbbf35b96557 728
Kojto 99:dbbf35b96557 729 /**
Kojto 99:dbbf35b96557 730 * @brief Disable the PCCARD device interrupt.
Kojto 99:dbbf35b96557 731 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 732 * @param __INTERRUPT__: FSMC_PCCARD interrupt
Kojto 99:dbbf35b96557 733 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 734 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 735 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 736 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 737 * @retval None
Kojto 99:dbbf35b96557 738 */
Kojto 99:dbbf35b96557 739 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
Kojto 99:dbbf35b96557 740
Kojto 99:dbbf35b96557 741 /**
Kojto 99:dbbf35b96557 742 * @brief Get flag status of the PCCARD device.
Kojto 99:dbbf35b96557 743 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 744 * @param __FLAG__: FSMC_PCCARD flag
Kojto 99:dbbf35b96557 745 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 746 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 747 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 748 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 749 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 750 * @retval The state of FLAG (SET or RESET).
Kojto 99:dbbf35b96557 751 */
Kojto 99:dbbf35b96557 752 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
Kojto 99:dbbf35b96557 753
Kojto 99:dbbf35b96557 754 /**
Kojto 99:dbbf35b96557 755 * @brief Clear flag status of the PCCARD device.
Kojto 99:dbbf35b96557 756 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 757 * @param __FLAG__: FSMC_PCCARD flag
Kojto 99:dbbf35b96557 758 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 759 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 760 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 761 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 762 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 763 * @retval None
Kojto 99:dbbf35b96557 764 */
Kojto 99:dbbf35b96557 765 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto 99:dbbf35b96557 766 /**
Kojto 99:dbbf35b96557 767 * @}
Kojto 99:dbbf35b96557 768 */
Kojto 99:dbbf35b96557 769
Kojto 99:dbbf35b96557 770 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto 99:dbbf35b96557 771 * @{
Kojto 99:dbbf35b96557 772 */
Kojto 99:dbbf35b96557 773 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
Kojto 99:dbbf35b96557 774 ((__BANK__) == FSMC_NORSRAM_BANK2) || \
Kojto 99:dbbf35b96557 775 ((__BANK__) == FSMC_NORSRAM_BANK3) || \
Kojto 99:dbbf35b96557 776 ((__BANK__) == FSMC_NORSRAM_BANK4))
Kojto 99:dbbf35b96557 777
Kojto 99:dbbf35b96557 778 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
Kojto 99:dbbf35b96557 779 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
Kojto 99:dbbf35b96557 780
Kojto 99:dbbf35b96557 781 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
Kojto 99:dbbf35b96557 782 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
Kojto 99:dbbf35b96557 783 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
Kojto 99:dbbf35b96557 784
Kojto 99:dbbf35b96557 785 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
Kojto 99:dbbf35b96557 786 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
Kojto 99:dbbf35b96557 787 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto 99:dbbf35b96557 788
Kojto 99:dbbf35b96557 789 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
Kojto 99:dbbf35b96557 790 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
Kojto 99:dbbf35b96557 791 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
Kojto 99:dbbf35b96557 792 ((__MODE__) == FSMC_ACCESS_MODE_D))
Kojto 99:dbbf35b96557 793
Kojto 99:dbbf35b96557 794 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
Kojto 99:dbbf35b96557 795 ((BANK) == FSMC_NAND_BANK3))
Kojto 99:dbbf35b96557 796
Kojto 99:dbbf35b96557 797 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
Kojto 99:dbbf35b96557 798 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto 99:dbbf35b96557 799
Kojto 99:dbbf35b96557 800 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
Kojto 99:dbbf35b96557 801 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto 99:dbbf35b96557 802
Kojto 99:dbbf35b96557 803 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
Kojto 99:dbbf35b96557 804 ((STATE) == FSMC_NAND_ECC_ENABLE))
Kojto 99:dbbf35b96557 805
Kojto 99:dbbf35b96557 806 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
Kojto 99:dbbf35b96557 807 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
Kojto 99:dbbf35b96557 808 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
Kojto 99:dbbf35b96557 809 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
Kojto 99:dbbf35b96557 810 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
Kojto 99:dbbf35b96557 811 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto 99:dbbf35b96557 812
Kojto 99:dbbf35b96557 813 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
Kojto 99:dbbf35b96557 814
Kojto 99:dbbf35b96557 815 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
Kojto 99:dbbf35b96557 816
Kojto 99:dbbf35b96557 817 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
Kojto 99:dbbf35b96557 818
Kojto 99:dbbf35b96557 819 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
Kojto 99:dbbf35b96557 820
Kojto 99:dbbf35b96557 821 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
Kojto 99:dbbf35b96557 822
Kojto 99:dbbf35b96557 823 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
Kojto 99:dbbf35b96557 824
Kojto 99:dbbf35b96557 825 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
Kojto 99:dbbf35b96557 826
Kojto 99:dbbf35b96557 827 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
Kojto 99:dbbf35b96557 828
Kojto 99:dbbf35b96557 829 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
Kojto 99:dbbf35b96557 830
Kojto 99:dbbf35b96557 831 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
Kojto 99:dbbf35b96557 832
Kojto 99:dbbf35b96557 833 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 834 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
Kojto 99:dbbf35b96557 835
Kojto 99:dbbf35b96557 836 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
Kojto 99:dbbf35b96557 837 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto 99:dbbf35b96557 838
Kojto 99:dbbf35b96557 839 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 840 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
Kojto 99:dbbf35b96557 841
Kojto 99:dbbf35b96557 842 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
Kojto 99:dbbf35b96557 843 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
Kojto 99:dbbf35b96557 844
Kojto 99:dbbf35b96557 845 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
Kojto 99:dbbf35b96557 846 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
Kojto 99:dbbf35b96557 847
Kojto 99:dbbf35b96557 848 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
Kojto 99:dbbf35b96557 849 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
Kojto 99:dbbf35b96557 850
Kojto 99:dbbf35b96557 851 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 852 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
Kojto 99:dbbf35b96557 853
Kojto 99:dbbf35b96557 854 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
Kojto 99:dbbf35b96557 855 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto 99:dbbf35b96557 856
Kojto 99:dbbf35b96557 857 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
Kojto 99:dbbf35b96557 858
Kojto 99:dbbf35b96557 859 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
Kojto 99:dbbf35b96557 860 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
Kojto 99:dbbf35b96557 861
Kojto 99:dbbf35b96557 862 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
Kojto 99:dbbf35b96557 863
Kojto 99:dbbf35b96557 864 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
Kojto 99:dbbf35b96557 865
Kojto 99:dbbf35b96557 866 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
Kojto 99:dbbf35b96557 867
Kojto 99:dbbf35b96557 868 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
Kojto 99:dbbf35b96557 869
Kojto 99:dbbf35b96557 870 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
Kojto 99:dbbf35b96557 871 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto 99:dbbf35b96557 872
Kojto 99:dbbf35b96557 873 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
Kojto 99:dbbf35b96557 874
Kojto 99:dbbf35b96557 875 /**
Kojto 99:dbbf35b96557 876 * @}
Kojto 99:dbbf35b96557 877 */
Kojto 99:dbbf35b96557 878 /**
Kojto 99:dbbf35b96557 879 * @}
Kojto 99:dbbf35b96557 880 */
Kojto 99:dbbf35b96557 881
Kojto 99:dbbf35b96557 882 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 883 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
Kojto 99:dbbf35b96557 884 * @{
Kojto 99:dbbf35b96557 885 */
Kojto 99:dbbf35b96557 886
Kojto 99:dbbf35b96557 887 /** @defgroup FSMC_LL_NORSRAM NOR SRAM
Kojto 99:dbbf35b96557 888 * @{
Kojto 99:dbbf35b96557 889 */
Kojto 99:dbbf35b96557 890
Kojto 99:dbbf35b96557 891 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto 99:dbbf35b96557 892 * @{
Kojto 99:dbbf35b96557 893 */
Kojto 99:dbbf35b96557 894 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
Kojto 99:dbbf35b96557 895 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
Kojto 99:dbbf35b96557 896 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
Kojto 99:dbbf35b96557 897 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
Kojto 99:dbbf35b96557 898 /**
Kojto 99:dbbf35b96557 899 * @}
Kojto 99:dbbf35b96557 900 */
Kojto 99:dbbf35b96557 901
Kojto 99:dbbf35b96557 902 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto 99:dbbf35b96557 903 * @{
Kojto 99:dbbf35b96557 904 */
Kojto 99:dbbf35b96557 905 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 906 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 907 /**
Kojto 99:dbbf35b96557 908 * @}
Kojto 99:dbbf35b96557 909 */
Kojto 99:dbbf35b96557 910 /**
Kojto 99:dbbf35b96557 911 * @}
Kojto 99:dbbf35b96557 912 */
Kojto 99:dbbf35b96557 913
Kojto 99:dbbf35b96557 914 /** @defgroup FSMC_LL_NAND NAND
Kojto 99:dbbf35b96557 915 * @{
Kojto 99:dbbf35b96557 916 */
Kojto 99:dbbf35b96557 917 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto 99:dbbf35b96557 918 * @{
Kojto 99:dbbf35b96557 919 */
Kojto 99:dbbf35b96557 920 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
Kojto 99:dbbf35b96557 921 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 99:dbbf35b96557 922 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 99:dbbf35b96557 923 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 924 /**
Kojto 99:dbbf35b96557 925 * @}
Kojto 99:dbbf35b96557 926 */
Kojto 99:dbbf35b96557 927
Kojto 99:dbbf35b96557 928 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto 99:dbbf35b96557 929 * @{
Kojto 99:dbbf35b96557 930 */
Kojto 99:dbbf35b96557 931 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 932 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 933 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
Kojto 99:dbbf35b96557 934 /**
Kojto 99:dbbf35b96557 935 * @}
Kojto 99:dbbf35b96557 936 */
Kojto 99:dbbf35b96557 937 /**
Kojto 99:dbbf35b96557 938 * @}
Kojto 99:dbbf35b96557 939 */
Kojto 99:dbbf35b96557 940
Kojto 99:dbbf35b96557 941 /** @defgroup FSMC_LL_PCCARD PCCARD
Kojto 99:dbbf35b96557 942 * @{
Kojto 99:dbbf35b96557 943 */
Kojto 99:dbbf35b96557 944 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto 99:dbbf35b96557 945 * @{
Kojto 99:dbbf35b96557 946 */
Kojto 99:dbbf35b96557 947 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
Kojto 99:dbbf35b96557 948 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 99:dbbf35b96557 949 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 99:dbbf35b96557 950 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 99:dbbf35b96557 951 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
Kojto 99:dbbf35b96557 952 /**
Kojto 99:dbbf35b96557 953 * @}
Kojto 99:dbbf35b96557 954 */
Kojto 99:dbbf35b96557 955 /**
Kojto 99:dbbf35b96557 956 * @}
Kojto 99:dbbf35b96557 957 */
Kojto 99:dbbf35b96557 958
Kojto 99:dbbf35b96557 959 /**
Kojto 99:dbbf35b96557 960 * @}
Kojto 99:dbbf35b96557 961 */
bogdanm 89:552587b429a1 962 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 963
bogdanm 89:552587b429a1 964 /**
bogdanm 89:552587b429a1 965 * @}
bogdanm 89:552587b429a1 966 */
bogdanm 89:552587b429a1 967
bogdanm 89:552587b429a1 968 /**
bogdanm 89:552587b429a1 969 * @}
bogdanm 89:552587b429a1 970 */
bogdanm 89:552587b429a1 971
bogdanm 89:552587b429a1 972 #ifdef __cplusplus
bogdanm 89:552587b429a1 973 }
bogdanm 89:552587b429a1 974 #endif
bogdanm 89:552587b429a1 975
bogdanm 89:552587b429a1 976 #endif /* __STM32F4xx_LL_FSMC_H */
bogdanm 89:552587b429a1 977
bogdanm 89:552587b429a1 978 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/