Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_ARCH_MAX/stm32f4xx_hal_eth.h@99:dbbf35b96557, 2015-05-13 (annotated)

Committer:
Kojto
Date:
Wed May 13 08:08:21 2015 +0200
Revision:
99:dbbf35b96557
Parent:
92:4fc01daae5a5
Child:
106:ba1f97679dad
Release 99 of the mbed library



Changes:

 - new targets - MAXWSNENV, DISCO_L053C8

 - STM32F4xx - ST Cube driver

 - KSDK mcu - SPI timing fix

 - Nordic - update to softdevice s130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_eth.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
Kojto 99:dbbf35b96557 5 * @version V1.3.0
Kojto 99:dbbf35b96557 6 * @date 09-March-2015
bogdanm 89:552587b429a1 7 * @brief Header file of ETH HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_HAL_ETH_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_HAL_ETH_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 89:552587b429a1 47 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 48 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 49
bogdanm 89:552587b429a1 50 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 51 * @{
bogdanm 89:552587b429a1 52 */
bogdanm 89:552587b429a1 53
bogdanm 89:552587b429a1 54 /** @addtogroup ETH
bogdanm 89:552587b429a1 55 * @{
bogdanm 89:552587b429a1 56 */
Kojto 99:dbbf35b96557 57
Kojto 99:dbbf35b96557 58 /** @addtogroup ETH_Private_Macros
Kojto 99:dbbf35b96557 59 * @{
Kojto 99:dbbf35b96557 60 */
Kojto 99:dbbf35b96557 61 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
Kojto 99:dbbf35b96557 62 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
Kojto 99:dbbf35b96557 63 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
Kojto 99:dbbf35b96557 64 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
Kojto 99:dbbf35b96557 65 ((SPEED) == ETH_SPEED_100M))
Kojto 99:dbbf35b96557 66 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
Kojto 99:dbbf35b96557 67 ((MODE) == ETH_MODE_HALFDUPLEX))
Kojto 99:dbbf35b96557 68 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
Kojto 99:dbbf35b96557 69 ((MODE) == ETH_MODE_HALFDUPLEX))
Kojto 99:dbbf35b96557 70 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
Kojto 99:dbbf35b96557 71 ((MODE) == ETH_RXINTERRUPT_MODE))
Kojto 99:dbbf35b96557 72 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
Kojto 99:dbbf35b96557 73 ((MODE) == ETH_RXINTERRUPT_MODE))
Kojto 99:dbbf35b96557 74 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
Kojto 99:dbbf35b96557 75 ((MODE) == ETH_RXINTERRUPT_MODE))
Kojto 99:dbbf35b96557 76 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
Kojto 99:dbbf35b96557 77 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
Kojto 99:dbbf35b96557 78 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
Kojto 99:dbbf35b96557 79 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
Kojto 99:dbbf35b96557 80 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
Kojto 99:dbbf35b96557 81 ((CMD) == ETH_WATCHDOG_DISABLE))
Kojto 99:dbbf35b96557 82 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
Kojto 99:dbbf35b96557 83 ((CMD) == ETH_JABBER_DISABLE))
Kojto 99:dbbf35b96557 84 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
Kojto 99:dbbf35b96557 85 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
Kojto 99:dbbf35b96557 86 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
Kojto 99:dbbf35b96557 87 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
Kojto 99:dbbf35b96557 88 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
Kojto 99:dbbf35b96557 89 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
Kojto 99:dbbf35b96557 90 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
Kojto 99:dbbf35b96557 91 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
Kojto 99:dbbf35b96557 92 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
Kojto 99:dbbf35b96557 93 ((CMD) == ETH_CARRIERSENCE_DISABLE))
Kojto 99:dbbf35b96557 94 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
Kojto 99:dbbf35b96557 95 ((CMD) == ETH_RECEIVEOWN_DISABLE))
Kojto 99:dbbf35b96557 96 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
Kojto 99:dbbf35b96557 97 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
Kojto 99:dbbf35b96557 98 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
Kojto 99:dbbf35b96557 99 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
Kojto 99:dbbf35b96557 100 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
Kojto 99:dbbf35b96557 101 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
Kojto 99:dbbf35b96557 102 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
Kojto 99:dbbf35b96557 103 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
Kojto 99:dbbf35b96557 104 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
Kojto 99:dbbf35b96557 105 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
Kojto 99:dbbf35b96557 106 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
Kojto 99:dbbf35b96557 107 ((LIMIT) == ETH_BACKOFFLIMIT_1))
Kojto 99:dbbf35b96557 108 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
Kojto 99:dbbf35b96557 109 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
Kojto 99:dbbf35b96557 110 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
Kojto 99:dbbf35b96557 111 ((CMD) == ETH_RECEIVEAll_DISABLE))
Kojto 99:dbbf35b96557 112 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
Kojto 99:dbbf35b96557 113 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
Kojto 99:dbbf35b96557 114 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
Kojto 99:dbbf35b96557 115 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
Kojto 99:dbbf35b96557 116 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
Kojto 99:dbbf35b96557 117 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
Kojto 99:dbbf35b96557 118 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
Kojto 99:dbbf35b96557 119 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
Kojto 99:dbbf35b96557 120 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
Kojto 99:dbbf35b96557 121 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
Kojto 99:dbbf35b96557 122 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
Kojto 99:dbbf35b96557 123 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
Kojto 99:dbbf35b96557 124 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
Kojto 99:dbbf35b96557 125 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
Kojto 99:dbbf35b96557 126 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
Kojto 99:dbbf35b96557 127 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
Kojto 99:dbbf35b96557 128 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
Kojto 99:dbbf35b96557 129 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
Kojto 99:dbbf35b96557 130 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
Kojto 99:dbbf35b96557 131 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
Kojto 99:dbbf35b96557 132 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
Kojto 99:dbbf35b96557 133 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
Kojto 99:dbbf35b96557 134 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
Kojto 99:dbbf35b96557 135 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
Kojto 99:dbbf35b96557 136 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
Kojto 99:dbbf35b96557 137 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
Kojto 99:dbbf35b96557 138 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
Kojto 99:dbbf35b96557 139 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
Kojto 99:dbbf35b96557 140 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
Kojto 99:dbbf35b96557 141 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
Kojto 99:dbbf35b96557 142 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
Kojto 99:dbbf35b96557 143 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
Kojto 99:dbbf35b96557 144 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
Kojto 99:dbbf35b96557 145 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
Kojto 99:dbbf35b96557 146 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
Kojto 99:dbbf35b96557 147 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
Kojto 99:dbbf35b96557 148 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
Kojto 99:dbbf35b96557 149 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
Kojto 99:dbbf35b96557 150 ((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto 99:dbbf35b96557 151 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
Kojto 99:dbbf35b96557 152 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
Kojto 99:dbbf35b96557 153 ((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto 99:dbbf35b96557 154 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
Kojto 99:dbbf35b96557 155 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
Kojto 99:dbbf35b96557 156 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
Kojto 99:dbbf35b96557 157 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
Kojto 99:dbbf35b96557 158 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
Kojto 99:dbbf35b96557 159 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
Kojto 99:dbbf35b96557 160 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
Kojto 99:dbbf35b96557 161 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
Kojto 99:dbbf35b96557 162 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
Kojto 99:dbbf35b96557 163 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
Kojto 99:dbbf35b96557 164 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
Kojto 99:dbbf35b96557 165 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
Kojto 99:dbbf35b96557 166 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
Kojto 99:dbbf35b96557 167 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
Kojto 99:dbbf35b96557 168 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
Kojto 99:dbbf35b96557 169 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
Kojto 99:dbbf35b96557 170 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
Kojto 99:dbbf35b96557 171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
Kojto 99:dbbf35b96557 172 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
Kojto 99:dbbf35b96557 173 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
Kojto 99:dbbf35b96557 174 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
Kojto 99:dbbf35b96557 175 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
Kojto 99:dbbf35b96557 176 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
Kojto 99:dbbf35b96557 177 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
Kojto 99:dbbf35b96557 178 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
Kojto 99:dbbf35b96557 179 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
Kojto 99:dbbf35b96557 180 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
Kojto 99:dbbf35b96557 181 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
Kojto 99:dbbf35b96557 182 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
Kojto 99:dbbf35b96557 183 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
Kojto 99:dbbf35b96557 184 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
Kojto 99:dbbf35b96557 185 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
Kojto 99:dbbf35b96557 186 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
Kojto 99:dbbf35b96557 187 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
Kojto 99:dbbf35b96557 188 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
Kojto 99:dbbf35b96557 189 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
Kojto 99:dbbf35b96557 190 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
Kojto 99:dbbf35b96557 191 ((CMD) == ETH_FIXEDBURST_DISABLE))
Kojto 99:dbbf35b96557 192 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
Kojto 99:dbbf35b96557 193 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
Kojto 99:dbbf35b96557 194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
Kojto 99:dbbf35b96557 195 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
Kojto 99:dbbf35b96557 196 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
Kojto 99:dbbf35b96557 197 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
Kojto 99:dbbf35b96557 198 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
Kojto 99:dbbf35b96557 199 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
Kojto 99:dbbf35b96557 200 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
Kojto 99:dbbf35b96557 201 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
Kojto 99:dbbf35b96557 202 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
Kojto 99:dbbf35b96557 203 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto 99:dbbf35b96557 204 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
Kojto 99:dbbf35b96557 205 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
Kojto 99:dbbf35b96557 206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
Kojto 99:dbbf35b96557 207 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
Kojto 99:dbbf35b96557 208 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
Kojto 99:dbbf35b96557 209 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
Kojto 99:dbbf35b96557 210 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
Kojto 99:dbbf35b96557 211 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
Kojto 99:dbbf35b96557 212 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
Kojto 99:dbbf35b96557 213 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
Kojto 99:dbbf35b96557 214 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
Kojto 99:dbbf35b96557 215 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto 99:dbbf35b96557 216 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
Kojto 99:dbbf35b96557 217 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
Kojto 99:dbbf35b96557 218 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
Kojto 99:dbbf35b96557 219 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
Kojto 99:dbbf35b96557 220 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
Kojto 99:dbbf35b96557 221 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
Kojto 99:dbbf35b96557 222 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
Kojto 99:dbbf35b96557 223 ((FLAG) == ETH_DMATXDESC_IC) || \
Kojto 99:dbbf35b96557 224 ((FLAG) == ETH_DMATXDESC_LS) || \
Kojto 99:dbbf35b96557 225 ((FLAG) == ETH_DMATXDESC_FS) || \
Kojto 99:dbbf35b96557 226 ((FLAG) == ETH_DMATXDESC_DC) || \
Kojto 99:dbbf35b96557 227 ((FLAG) == ETH_DMATXDESC_DP) || \
Kojto 99:dbbf35b96557 228 ((FLAG) == ETH_DMATXDESC_TTSE) || \
Kojto 99:dbbf35b96557 229 ((FLAG) == ETH_DMATXDESC_TER) || \
Kojto 99:dbbf35b96557 230 ((FLAG) == ETH_DMATXDESC_TCH) || \
Kojto 99:dbbf35b96557 231 ((FLAG) == ETH_DMATXDESC_TTSS) || \
Kojto 99:dbbf35b96557 232 ((FLAG) == ETH_DMATXDESC_IHE) || \
Kojto 99:dbbf35b96557 233 ((FLAG) == ETH_DMATXDESC_ES) || \
Kojto 99:dbbf35b96557 234 ((FLAG) == ETH_DMATXDESC_JT) || \
Kojto 99:dbbf35b96557 235 ((FLAG) == ETH_DMATXDESC_FF) || \
Kojto 99:dbbf35b96557 236 ((FLAG) == ETH_DMATXDESC_PCE) || \
Kojto 99:dbbf35b96557 237 ((FLAG) == ETH_DMATXDESC_LCA) || \
Kojto 99:dbbf35b96557 238 ((FLAG) == ETH_DMATXDESC_NC) || \
Kojto 99:dbbf35b96557 239 ((FLAG) == ETH_DMATXDESC_LCO) || \
Kojto 99:dbbf35b96557 240 ((FLAG) == ETH_DMATXDESC_EC) || \
Kojto 99:dbbf35b96557 241 ((FLAG) == ETH_DMATXDESC_VF) || \
Kojto 99:dbbf35b96557 242 ((FLAG) == ETH_DMATXDESC_CC) || \
Kojto 99:dbbf35b96557 243 ((FLAG) == ETH_DMATXDESC_ED) || \
Kojto 99:dbbf35b96557 244 ((FLAG) == ETH_DMATXDESC_UF) || \
Kojto 99:dbbf35b96557 245 ((FLAG) == ETH_DMATXDESC_DB))
Kojto 99:dbbf35b96557 246 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
Kojto 99:dbbf35b96557 247 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
Kojto 99:dbbf35b96557 248 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
Kojto 99:dbbf35b96557 249 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
Kojto 99:dbbf35b96557 250 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
Kojto 99:dbbf35b96557 251 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
Kojto 99:dbbf35b96557 252 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
Kojto 99:dbbf35b96557 253 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
Kojto 99:dbbf35b96557 254 ((FLAG) == ETH_DMARXDESC_AFM) || \
Kojto 99:dbbf35b96557 255 ((FLAG) == ETH_DMARXDESC_ES) || \
Kojto 99:dbbf35b96557 256 ((FLAG) == ETH_DMARXDESC_DE) || \
Kojto 99:dbbf35b96557 257 ((FLAG) == ETH_DMARXDESC_SAF) || \
Kojto 99:dbbf35b96557 258 ((FLAG) == ETH_DMARXDESC_LE) || \
Kojto 99:dbbf35b96557 259 ((FLAG) == ETH_DMARXDESC_OE) || \
Kojto 99:dbbf35b96557 260 ((FLAG) == ETH_DMARXDESC_VLAN) || \
Kojto 99:dbbf35b96557 261 ((FLAG) == ETH_DMARXDESC_FS) || \
Kojto 99:dbbf35b96557 262 ((FLAG) == ETH_DMARXDESC_LS) || \
Kojto 99:dbbf35b96557 263 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
Kojto 99:dbbf35b96557 264 ((FLAG) == ETH_DMARXDESC_LC) || \
Kojto 99:dbbf35b96557 265 ((FLAG) == ETH_DMARXDESC_FT) || \
Kojto 99:dbbf35b96557 266 ((FLAG) == ETH_DMARXDESC_RWT) || \
Kojto 99:dbbf35b96557 267 ((FLAG) == ETH_DMARXDESC_RE) || \
Kojto 99:dbbf35b96557 268 ((FLAG) == ETH_DMARXDESC_DBE) || \
Kojto 99:dbbf35b96557 269 ((FLAG) == ETH_DMARXDESC_CE) || \
Kojto 99:dbbf35b96557 270 ((FLAG) == ETH_DMARXDESC_MAMPCE))
Kojto 99:dbbf35b96557 271 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
Kojto 99:dbbf35b96557 272 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
Kojto 99:dbbf35b96557 273 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
Kojto 99:dbbf35b96557 274 ((FLAG) == ETH_PMT_FLAG_MPR))
Kojto 99:dbbf35b96557 275 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
Kojto 99:dbbf35b96557 276 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
Kojto 99:dbbf35b96557 277 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
Kojto 99:dbbf35b96557 278 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
Kojto 99:dbbf35b96557 279 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
Kojto 99:dbbf35b96557 280 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
Kojto 99:dbbf35b96557 281 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
Kojto 99:dbbf35b96557 282 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
Kojto 99:dbbf35b96557 283 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
Kojto 99:dbbf35b96557 284 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
Kojto 99:dbbf35b96557 285 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
Kojto 99:dbbf35b96557 286 ((FLAG) == ETH_DMA_FLAG_T))
Kojto 99:dbbf35b96557 287 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
Kojto 99:dbbf35b96557 288 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
Kojto 99:dbbf35b96557 289 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
Kojto 99:dbbf35b96557 290 ((IT) == ETH_MAC_IT_PMT))
Kojto 99:dbbf35b96557 291 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
Kojto 99:dbbf35b96557 292 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
Kojto 99:dbbf35b96557 293 ((FLAG) == ETH_MAC_FLAG_PMT))
Kojto 99:dbbf35b96557 294 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
Kojto 99:dbbf35b96557 295 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
Kojto 99:dbbf35b96557 296 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
Kojto 99:dbbf35b96557 297 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
Kojto 99:dbbf35b96557 298 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
Kojto 99:dbbf35b96557 299 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
Kojto 99:dbbf35b96557 300 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
Kojto 99:dbbf35b96557 301 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
Kojto 99:dbbf35b96557 302 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
Kojto 99:dbbf35b96557 303 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
Kojto 99:dbbf35b96557 304 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
Kojto 99:dbbf35b96557 305 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
Kojto 99:dbbf35b96557 306 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
Kojto 99:dbbf35b96557 307 ((IT) != 0x00))
Kojto 99:dbbf35b96557 308 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
Kojto 99:dbbf35b96557 309 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
Kojto 99:dbbf35b96557 310 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
Kojto 99:dbbf35b96557 311 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
Kojto 99:dbbf35b96557 312 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
Kojto 99:dbbf35b96557 313
Kojto 99:dbbf35b96557 314
Kojto 99:dbbf35b96557 315 /**
Kojto 99:dbbf35b96557 316 * @}
Kojto 99:dbbf35b96557 317 */
Kojto 99:dbbf35b96557 318
Kojto 99:dbbf35b96557 319 /** @addtogroup ETH_Private_Defines
Kojto 99:dbbf35b96557 320 * @{
Kojto 99:dbbf35b96557 321 */
Kojto 99:dbbf35b96557 322 /* Delay to wait when writing to some Ethernet registers */
Kojto 99:dbbf35b96557 323 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
Kojto 99:dbbf35b96557 324
Kojto 99:dbbf35b96557 325 /* ETHERNET Errors */
Kojto 99:dbbf35b96557 326 #define ETH_SUCCESS ((uint32_t)0)
Kojto 99:dbbf35b96557 327 #define ETH_ERROR ((uint32_t)1)
Kojto 99:dbbf35b96557 328
Kojto 99:dbbf35b96557 329 /* ETHERNET DMA Tx descriptors Collision Count Shift */
Kojto 99:dbbf35b96557 330 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
Kojto 99:dbbf35b96557 331
Kojto 99:dbbf35b96557 332 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
Kojto 99:dbbf35b96557 333 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
Kojto 99:dbbf35b96557 334
Kojto 99:dbbf35b96557 335 /* ETHERNET DMA Rx descriptors Frame Length Shift */
Kojto 99:dbbf35b96557 336 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
Kojto 99:dbbf35b96557 337
Kojto 99:dbbf35b96557 338 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
Kojto 99:dbbf35b96557 339 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
Kojto 99:dbbf35b96557 340
Kojto 99:dbbf35b96557 341 /* ETHERNET DMA Rx descriptors Frame length Shift */
Kojto 99:dbbf35b96557 342 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
Kojto 99:dbbf35b96557 343
Kojto 99:dbbf35b96557 344 /* ETHERNET MAC address offsets */
Kojto 99:dbbf35b96557 345 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
Kojto 99:dbbf35b96557 346 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
Kojto 99:dbbf35b96557 347
Kojto 99:dbbf35b96557 348 /* ETHERNET MACMIIAR register Mask */
Kojto 99:dbbf35b96557 349 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
Kojto 99:dbbf35b96557 350
Kojto 99:dbbf35b96557 351 /* ETHERNET MACCR register Mask */
Kojto 99:dbbf35b96557 352 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
Kojto 99:dbbf35b96557 353
Kojto 99:dbbf35b96557 354 /* ETHERNET MACFCR register Mask */
Kojto 99:dbbf35b96557 355 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
Kojto 99:dbbf35b96557 356
Kojto 99:dbbf35b96557 357 /* ETHERNET DMAOMR register Mask */
Kojto 99:dbbf35b96557 358 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
Kojto 99:dbbf35b96557 359
Kojto 99:dbbf35b96557 360 /* ETHERNET Remote Wake-up frame register length */
Kojto 99:dbbf35b96557 361 #define ETH_WAKEUP_REGISTER_LENGTH 8
Kojto 99:dbbf35b96557 362
Kojto 99:dbbf35b96557 363 /* ETHERNET Missed frames counter Shift */
Kojto 99:dbbf35b96557 364 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
Kojto 99:dbbf35b96557 365 /**
Kojto 99:dbbf35b96557 366 * @}
Kojto 99:dbbf35b96557 367 */
bogdanm 89:552587b429a1 368
bogdanm 89:552587b429a1 369 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 370 /** @defgroup ETH_Exported_Types ETH Exported Types
Kojto 99:dbbf35b96557 371 * @{
Kojto 99:dbbf35b96557 372 */
bogdanm 89:552587b429a1 373
bogdanm 89:552587b429a1 374 /**
bogdanm 89:552587b429a1 375 * @brief HAL State structures definition
bogdanm 89:552587b429a1 376 */
bogdanm 89:552587b429a1 377 typedef enum
bogdanm 89:552587b429a1 378 {
bogdanm 89:552587b429a1 379 HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
bogdanm 89:552587b429a1 380 HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 89:552587b429a1 381 HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
bogdanm 89:552587b429a1 382 HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
bogdanm 89:552587b429a1 383 HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
bogdanm 89:552587b429a1 384 HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
bogdanm 89:552587b429a1 385 HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
bogdanm 89:552587b429a1 386 HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
bogdanm 89:552587b429a1 387 HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 89:552587b429a1 388 HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
bogdanm 89:552587b429a1 389 }HAL_ETH_StateTypeDef;
bogdanm 89:552587b429a1 390
bogdanm 89:552587b429a1 391 /**
bogdanm 89:552587b429a1 392 * @brief ETH Init Structure definition
bogdanm 89:552587b429a1 393 */
bogdanm 89:552587b429a1 394
bogdanm 89:552587b429a1 395 typedef struct
bogdanm 89:552587b429a1 396 {
bogdanm 89:552587b429a1 397 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
bogdanm 89:552587b429a1 398 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
bogdanm 89:552587b429a1 399 and the mode (half/full-duplex).
bogdanm 89:552587b429a1 400 This parameter can be a value of @ref ETH_AutoNegotiation */
bogdanm 89:552587b429a1 401
bogdanm 89:552587b429a1 402 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
bogdanm 89:552587b429a1 403 This parameter can be a value of @ref ETH_Speed */
bogdanm 89:552587b429a1 404
bogdanm 89:552587b429a1 405 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
bogdanm 89:552587b429a1 406 This parameter can be a value of @ref ETH_Duplex_Mode */
bogdanm 89:552587b429a1 407
bogdanm 89:552587b429a1 408 uint16_t PhyAddress; /*!< Ethernet PHY address.
bogdanm 89:552587b429a1 409 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
bogdanm 89:552587b429a1 410
bogdanm 89:552587b429a1 411 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
bogdanm 89:552587b429a1 412
bogdanm 89:552587b429a1 413 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
bogdanm 89:552587b429a1 414 This parameter can be a value of @ref ETH_Rx_Mode */
bogdanm 89:552587b429a1 415
bogdanm 89:552587b429a1 416 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
bogdanm 89:552587b429a1 417 This parameter can be a value of @ref ETH_Checksum_Mode */
bogdanm 89:552587b429a1 418
bogdanm 89:552587b429a1 419 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
bogdanm 89:552587b429a1 420 This parameter can be a value of @ref ETH_Media_Interface */
bogdanm 89:552587b429a1 421
bogdanm 89:552587b429a1 422 } ETH_InitTypeDef;
bogdanm 89:552587b429a1 423
bogdanm 89:552587b429a1 424
bogdanm 89:552587b429a1 425 /**
bogdanm 89:552587b429a1 426 * @brief ETH MAC Configuration Structure definition
bogdanm 89:552587b429a1 427 */
bogdanm 89:552587b429a1 428
bogdanm 89:552587b429a1 429 typedef struct
bogdanm 89:552587b429a1 430 {
bogdanm 89:552587b429a1 431 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
bogdanm 89:552587b429a1 432 When enabled, the MAC allows no more then 2048 bytes to be received.
bogdanm 89:552587b429a1 433 When disabled, the MAC can receive up to 16384 bytes.
Kojto 99:dbbf35b96557 434 This parameter can be a value of @ref ETH_Watchdog */
bogdanm 89:552587b429a1 435
bogdanm 89:552587b429a1 436 uint32_t Jabber; /*!< Selects or not Jabber timer
bogdanm 89:552587b429a1 437 When enabled, the MAC allows no more then 2048 bytes to be sent.
bogdanm 89:552587b429a1 438 When disabled, the MAC can send up to 16384 bytes.
bogdanm 89:552587b429a1 439 This parameter can be a value of @ref ETH_Jabber */
bogdanm 89:552587b429a1 440
bogdanm 89:552587b429a1 441 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
bogdanm 89:552587b429a1 442 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
bogdanm 89:552587b429a1 443
bogdanm 89:552587b429a1 444 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
bogdanm 89:552587b429a1 445 This parameter can be a value of @ref ETH_Carrier_Sense */
bogdanm 89:552587b429a1 446
bogdanm 89:552587b429a1 447 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
bogdanm 89:552587b429a1 448 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
bogdanm 89:552587b429a1 449 in Half-Duplex mode.
bogdanm 89:552587b429a1 450 This parameter can be a value of @ref ETH_Receive_Own */
bogdanm 89:552587b429a1 451
bogdanm 89:552587b429a1 452 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
bogdanm 89:552587b429a1 453 This parameter can be a value of @ref ETH_Loop_Back_Mode */
bogdanm 89:552587b429a1 454
bogdanm 89:552587b429a1 455 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
bogdanm 89:552587b429a1 456 This parameter can be a value of @ref ETH_Checksum_Offload */
bogdanm 89:552587b429a1 457
bogdanm 89:552587b429a1 458 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
bogdanm 89:552587b429a1 459 when a collision occurs (Half-Duplex mode).
bogdanm 89:552587b429a1 460 This parameter can be a value of @ref ETH_Retry_Transmission */
bogdanm 89:552587b429a1 461
bogdanm 89:552587b429a1 462 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
bogdanm 89:552587b429a1 463 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
bogdanm 89:552587b429a1 464
bogdanm 89:552587b429a1 465 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
bogdanm 89:552587b429a1 466 This parameter can be a value of @ref ETH_Back_Off_Limit */
bogdanm 89:552587b429a1 467
bogdanm 89:552587b429a1 468 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
bogdanm 89:552587b429a1 469 This parameter can be a value of @ref ETH_Deferral_Check */
bogdanm 89:552587b429a1 470
bogdanm 89:552587b429a1 471 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
bogdanm 89:552587b429a1 472 This parameter can be a value of @ref ETH_Receive_All */
bogdanm 89:552587b429a1 473
bogdanm 89:552587b429a1 474 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
bogdanm 89:552587b429a1 475 This parameter can be a value of @ref ETH_Source_Addr_Filter */
bogdanm 89:552587b429a1 476
bogdanm 89:552587b429a1 477 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
bogdanm 89:552587b429a1 478 This parameter can be a value of @ref ETH_Pass_Control_Frames */
bogdanm 89:552587b429a1 479
bogdanm 89:552587b429a1 480 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
bogdanm 89:552587b429a1 481 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
bogdanm 89:552587b429a1 482
bogdanm 89:552587b429a1 483 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
bogdanm 89:552587b429a1 484 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
bogdanm 89:552587b429a1 485
bogdanm 89:552587b429a1 486 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
bogdanm 89:552587b429a1 487 This parameter can be a value of @ref ETH_Promiscuous_Mode */
bogdanm 89:552587b429a1 488
bogdanm 89:552587b429a1 489 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
bogdanm 89:552587b429a1 490 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
bogdanm 89:552587b429a1 491
bogdanm 89:552587b429a1 492 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
bogdanm 89:552587b429a1 493 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
bogdanm 89:552587b429a1 494
bogdanm 89:552587b429a1 495 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
bogdanm 89:552587b429a1 496 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
bogdanm 89:552587b429a1 497
bogdanm 89:552587b429a1 498 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
bogdanm 89:552587b429a1 499 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
bogdanm 89:552587b429a1 500
bogdanm 89:552587b429a1 501 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
bogdanm 89:552587b429a1 502 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
bogdanm 89:552587b429a1 503
bogdanm 89:552587b429a1 504 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
bogdanm 89:552587b429a1 505 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
bogdanm 89:552587b429a1 506
bogdanm 89:552587b429a1 507 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
bogdanm 89:552587b429a1 508 automatic retransmission of PAUSE Frame.
bogdanm 89:552587b429a1 509 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
bogdanm 89:552587b429a1 510
bogdanm 89:552587b429a1 511 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
bogdanm 89:552587b429a1 512 unicast address and unique multicast address).
bogdanm 89:552587b429a1 513 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
bogdanm 89:552587b429a1 514
bogdanm 89:552587b429a1 515 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
bogdanm 89:552587b429a1 516 disable its transmitter for a specified time (Pause Time)
bogdanm 89:552587b429a1 517 This parameter can be a value of @ref ETH_Receive_Flow_Control */
bogdanm 89:552587b429a1 518
bogdanm 89:552587b429a1 519 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
bogdanm 89:552587b429a1 520 or the MAC back-pressure operation (Half-Duplex mode)
bogdanm 89:552587b429a1 521 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
bogdanm 89:552587b429a1 522
bogdanm 89:552587b429a1 523 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
bogdanm 89:552587b429a1 524 comparison and filtering.
bogdanm 89:552587b429a1 525 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
bogdanm 89:552587b429a1 526
bogdanm 89:552587b429a1 527 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
bogdanm 89:552587b429a1 528
bogdanm 89:552587b429a1 529 } ETH_MACInitTypeDef;
bogdanm 89:552587b429a1 530
bogdanm 89:552587b429a1 531
bogdanm 89:552587b429a1 532 /**
bogdanm 89:552587b429a1 533 * @brief ETH DMA Configuration Structure definition
bogdanm 89:552587b429a1 534 */
bogdanm 89:552587b429a1 535
bogdanm 89:552587b429a1 536 typedef struct
bogdanm 89:552587b429a1 537 {
bogdanm 89:552587b429a1 538 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
bogdanm 89:552587b429a1 539 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
bogdanm 89:552587b429a1 540
bogdanm 89:552587b429a1 541 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
bogdanm 89:552587b429a1 542 This parameter can be a value of @ref ETH_Receive_Store_Forward */
bogdanm 89:552587b429a1 543
bogdanm 89:552587b429a1 544 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
bogdanm 89:552587b429a1 545 This parameter can be a value of @ref ETH_Flush_Received_Frame */
bogdanm 89:552587b429a1 546
bogdanm 89:552587b429a1 547 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
bogdanm 89:552587b429a1 548 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
bogdanm 89:552587b429a1 549
bogdanm 89:552587b429a1 550 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
bogdanm 89:552587b429a1 551 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
bogdanm 89:552587b429a1 552
bogdanm 89:552587b429a1 553 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
bogdanm 89:552587b429a1 554 This parameter can be a value of @ref ETH_Forward_Error_Frames */
bogdanm 89:552587b429a1 555
bogdanm 89:552587b429a1 556 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
bogdanm 89:552587b429a1 557 and length less than 64 bytes) including pad-bytes and CRC)
bogdanm 89:552587b429a1 558 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
bogdanm 89:552587b429a1 559
bogdanm 89:552587b429a1 560 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
bogdanm 89:552587b429a1 561 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
bogdanm 89:552587b429a1 562
bogdanm 89:552587b429a1 563 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
bogdanm 89:552587b429a1 564 frame of Transmit data even before obtaining the status for the first frame.
bogdanm 89:552587b429a1 565 This parameter can be a value of @ref ETH_Second_Frame_Operate */
bogdanm 89:552587b429a1 566
bogdanm 89:552587b429a1 567 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
bogdanm 89:552587b429a1 568 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
bogdanm 89:552587b429a1 569
bogdanm 89:552587b429a1 570 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
bogdanm 89:552587b429a1 571 This parameter can be a value of @ref ETH_Fixed_Burst */
bogdanm 89:552587b429a1 572
bogdanm 89:552587b429a1 573 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
bogdanm 89:552587b429a1 574 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
bogdanm 89:552587b429a1 575
bogdanm 89:552587b429a1 576 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
bogdanm 89:552587b429a1 577 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
bogdanm 89:552587b429a1 578
bogdanm 89:552587b429a1 579 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
bogdanm 89:552587b429a1 580 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
bogdanm 89:552587b429a1 581
bogdanm 89:552587b429a1 582 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
bogdanm 89:552587b429a1 583 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
bogdanm 89:552587b429a1 584
bogdanm 89:552587b429a1 585 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
bogdanm 89:552587b429a1 586 This parameter can be a value of @ref ETH_DMA_Arbitration */
bogdanm 89:552587b429a1 587 } ETH_DMAInitTypeDef;
bogdanm 89:552587b429a1 588
bogdanm 89:552587b429a1 589
bogdanm 89:552587b429a1 590 /**
bogdanm 89:552587b429a1 591 * @brief ETH DMA Descriptors data structure definition
bogdanm 89:552587b429a1 592 */
bogdanm 89:552587b429a1 593
bogdanm 89:552587b429a1 594 typedef struct
bogdanm 89:552587b429a1 595 {
bogdanm 89:552587b429a1 596 __IO uint32_t Status; /*!< Status */
bogdanm 89:552587b429a1 597
bogdanm 89:552587b429a1 598 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
bogdanm 89:552587b429a1 599
bogdanm 89:552587b429a1 600 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
bogdanm 89:552587b429a1 601
bogdanm 89:552587b429a1 602 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
bogdanm 89:552587b429a1 603
bogdanm 89:552587b429a1 604 /*!< Enhanced ETHERNET DMA PTP Descriptors */
bogdanm 89:552587b429a1 605 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
bogdanm 89:552587b429a1 606
bogdanm 89:552587b429a1 607 uint32_t Reserved1; /*!< Reserved */
bogdanm 89:552587b429a1 608
bogdanm 89:552587b429a1 609 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
bogdanm 89:552587b429a1 610
bogdanm 89:552587b429a1 611 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
bogdanm 89:552587b429a1 612
bogdanm 89:552587b429a1 613 } ETH_DMADescTypeDef;
bogdanm 89:552587b429a1 614
bogdanm 89:552587b429a1 615
bogdanm 89:552587b429a1 616 /**
bogdanm 89:552587b429a1 617 * @brief Received Frame Informations structure definition
bogdanm 89:552587b429a1 618 */
bogdanm 89:552587b429a1 619 typedef struct
bogdanm 89:552587b429a1 620 {
bogdanm 89:552587b429a1 621 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
bogdanm 89:552587b429a1 622
bogdanm 89:552587b429a1 623 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
bogdanm 89:552587b429a1 624
bogdanm 89:552587b429a1 625 uint32_t SegCount; /*!< Segment count */
bogdanm 89:552587b429a1 626
bogdanm 89:552587b429a1 627 uint32_t length; /*!< Frame length */
bogdanm 89:552587b429a1 628
bogdanm 89:552587b429a1 629 uint32_t buffer; /*!< Frame buffer */
bogdanm 89:552587b429a1 630
bogdanm 89:552587b429a1 631 } ETH_DMARxFrameInfos;
bogdanm 89:552587b429a1 632
bogdanm 89:552587b429a1 633
bogdanm 89:552587b429a1 634 /**
bogdanm 89:552587b429a1 635 * @brief ETH Handle Structure definition
bogdanm 89:552587b429a1 636 */
bogdanm 89:552587b429a1 637
bogdanm 89:552587b429a1 638 typedef struct
bogdanm 89:552587b429a1 639 {
bogdanm 89:552587b429a1 640 ETH_TypeDef *Instance; /*!< Register base address */
bogdanm 89:552587b429a1 641
bogdanm 89:552587b429a1 642 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
bogdanm 89:552587b429a1 643
bogdanm 89:552587b429a1 644 uint32_t LinkStatus; /*!< Ethernet link status */
bogdanm 89:552587b429a1 645
bogdanm 89:552587b429a1 646 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
bogdanm 89:552587b429a1 647
bogdanm 89:552587b429a1 648 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
bogdanm 89:552587b429a1 649
bogdanm 89:552587b429a1 650 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
bogdanm 89:552587b429a1 651
bogdanm 89:552587b429a1 652 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
bogdanm 89:552587b429a1 653
bogdanm 89:552587b429a1 654 HAL_LockTypeDef Lock; /*!< ETH Lock */
bogdanm 89:552587b429a1 655
bogdanm 89:552587b429a1 656 } ETH_HandleTypeDef;
bogdanm 89:552587b429a1 657
Kojto 99:dbbf35b96557 658 /**
Kojto 99:dbbf35b96557 659 * @}
Kojto 99:dbbf35b96557 660 */
bogdanm 89:552587b429a1 661
Kojto 99:dbbf35b96557 662 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 663 /** @defgroup ETH_Exported_Constants ETH Exported Constants
Kojto 99:dbbf35b96557 664 * @{
Kojto 99:dbbf35b96557 665 */
bogdanm 89:552587b429a1 666
Kojto 99:dbbf35b96557 667 /** @defgroup ETH_Buffers_setting ETH Buffers setting
bogdanm 89:552587b429a1 668 * @{
bogdanm 89:552587b429a1 669 */
Kojto 99:dbbf35b96557 670 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
bogdanm 89:552587b429a1 671 #define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
bogdanm 89:552587b429a1 672 #define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
bogdanm 89:552587b429a1 673 #define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
Kojto 99:dbbf35b96557 674 #define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
Kojto 99:dbbf35b96557 675 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
Kojto 99:dbbf35b96557 676 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
Kojto 99:dbbf35b96557 677 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
bogdanm 89:552587b429a1 678
bogdanm 89:552587b429a1 679 /* Ethernet driver receive buffers are organized in a chained linked-list, when
bogdanm 89:552587b429a1 680 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
bogdanm 89:552587b429a1 681 to the driver receive buffers memory.
bogdanm 89:552587b429a1 682
bogdanm 89:552587b429a1 683 Depending on the size of the received ethernet packet and the size of
bogdanm 89:552587b429a1 684 each ethernet driver receive buffer, the received packet can take one or more
bogdanm 89:552587b429a1 685 ethernet driver receive buffer.
bogdanm 89:552587b429a1 686
bogdanm 89:552587b429a1 687 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
bogdanm 89:552587b429a1 688 and the total count of the driver receive buffers ETH_RXBUFNB.
bogdanm 89:552587b429a1 689
bogdanm 89:552587b429a1 690 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
bogdanm 89:552587b429a1 691 example, they can be reconfigured in the application layer to fit the application
bogdanm 89:552587b429a1 692 needs */
bogdanm 89:552587b429a1 693
bogdanm 89:552587b429a1 694 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
bogdanm 89:552587b429a1 695 packet */
bogdanm 89:552587b429a1 696 #ifndef ETH_RX_BUF_SIZE
bogdanm 89:552587b429a1 697 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
bogdanm 89:552587b429a1 698 #endif
bogdanm 89:552587b429a1 699
bogdanm 89:552587b429a1 700 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
bogdanm 89:552587b429a1 701 #ifndef ETH_RXBUFNB
bogdanm 89:552587b429a1 702 #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
bogdanm 89:552587b429a1 703 #endif
bogdanm 89:552587b429a1 704
bogdanm 89:552587b429a1 705
bogdanm 89:552587b429a1 706 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
bogdanm 89:552587b429a1 707 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
bogdanm 89:552587b429a1 708 driver transmit buffers memory to the TxFIFO.
bogdanm 89:552587b429a1 709
bogdanm 89:552587b429a1 710 Depending on the size of the Ethernet packet to be transmitted and the size of
bogdanm 89:552587b429a1 711 each ethernet driver transmit buffer, the packet to be transmitted can take
bogdanm 89:552587b429a1 712 one or more ethernet driver transmit buffer.
bogdanm 89:552587b429a1 713
bogdanm 89:552587b429a1 714 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
bogdanm 89:552587b429a1 715 and the total count of the driver transmit buffers ETH_TXBUFNB.
bogdanm 89:552587b429a1 716
bogdanm 89:552587b429a1 717 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
bogdanm 89:552587b429a1 718 example, they can be reconfigured in the application layer to fit the application
bogdanm 89:552587b429a1 719 needs */
bogdanm 89:552587b429a1 720
bogdanm 89:552587b429a1 721 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
bogdanm 89:552587b429a1 722 packet */
bogdanm 89:552587b429a1 723 #ifndef ETH_TX_BUF_SIZE
bogdanm 89:552587b429a1 724 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
bogdanm 89:552587b429a1 725 #endif
bogdanm 89:552587b429a1 726
bogdanm 89:552587b429a1 727 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
bogdanm 89:552587b429a1 728 #ifndef ETH_TXBUFNB
bogdanm 89:552587b429a1 729 #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
bogdanm 89:552587b429a1 730 #endif
bogdanm 89:552587b429a1 731
Kojto 99:dbbf35b96557 732 /**
Kojto 99:dbbf35b96557 733 * @}
Kojto 99:dbbf35b96557 734 */
Kojto 99:dbbf35b96557 735
Kojto 99:dbbf35b96557 736 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
Kojto 99:dbbf35b96557 737 * @{
Kojto 99:dbbf35b96557 738 */
bogdanm 89:552587b429a1 739
bogdanm 89:552587b429a1 740 /*
Kojto 99:dbbf35b96557 741 DMA Tx Descriptor
bogdanm 89:552587b429a1 742 -----------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 743 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
bogdanm 89:552587b429a1 744 -----------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 745 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
bogdanm 89:552587b429a1 746 -----------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 747 TDES2 | Buffer1 Address [31:0] |
bogdanm 89:552587b429a1 748 -----------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 749 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
bogdanm 89:552587b429a1 750 -----------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 751 */
bogdanm 89:552587b429a1 752
bogdanm 89:552587b429a1 753 /**
bogdanm 89:552587b429a1 754 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
bogdanm 89:552587b429a1 755 */
bogdanm 89:552587b429a1 756 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
bogdanm 89:552587b429a1 757 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
bogdanm 89:552587b429a1 758 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
bogdanm 89:552587b429a1 759 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
bogdanm 89:552587b429a1 760 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
bogdanm 89:552587b429a1 761 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
bogdanm 89:552587b429a1 762 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
bogdanm 89:552587b429a1 763 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
bogdanm 89:552587b429a1 764 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
bogdanm 89:552587b429a1 765 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
bogdanm 89:552587b429a1 766 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
bogdanm 89:552587b429a1 767 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
bogdanm 89:552587b429a1 768 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
bogdanm 89:552587b429a1 769 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
bogdanm 89:552587b429a1 770 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
bogdanm 89:552587b429a1 771 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
bogdanm 89:552587b429a1 772 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
bogdanm 89:552587b429a1 773 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
bogdanm 89:552587b429a1 774 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
bogdanm 89:552587b429a1 775 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
bogdanm 89:552587b429a1 776 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
bogdanm 89:552587b429a1 777 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
bogdanm 89:552587b429a1 778 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
bogdanm 89:552587b429a1 779 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
bogdanm 89:552587b429a1 780 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
bogdanm 89:552587b429a1 781 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
bogdanm 89:552587b429a1 782 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
bogdanm 89:552587b429a1 783 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
bogdanm 89:552587b429a1 784 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
bogdanm 89:552587b429a1 785
bogdanm 89:552587b429a1 786 /**
bogdanm 89:552587b429a1 787 * @brief Bit definition of TDES1 register
bogdanm 89:552587b429a1 788 */
bogdanm 89:552587b429a1 789 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
bogdanm 89:552587b429a1 790 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
bogdanm 89:552587b429a1 791
bogdanm 89:552587b429a1 792 /**
bogdanm 89:552587b429a1 793 * @brief Bit definition of TDES2 register
bogdanm 89:552587b429a1 794 */
bogdanm 89:552587b429a1 795 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
bogdanm 89:552587b429a1 796
bogdanm 89:552587b429a1 797 /**
bogdanm 89:552587b429a1 798 * @brief Bit definition of TDES3 register
bogdanm 89:552587b429a1 799 */
bogdanm 89:552587b429a1 800 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
bogdanm 89:552587b429a1 801
bogdanm 89:552587b429a1 802 /*---------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 803 TDES6 | Transmit Time Stamp Low [31:0] |
bogdanm 89:552587b429a1 804 -----------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 805 TDES7 | Transmit Time Stamp High [31:0] |
bogdanm 89:552587b429a1 806 ----------------------------------------------------------------------------------------------*/
bogdanm 89:552587b429a1 807
bogdanm 89:552587b429a1 808 /* Bit definition of TDES6 register */
bogdanm 89:552587b429a1 809 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
bogdanm 89:552587b429a1 810
bogdanm 89:552587b429a1 811 /* Bit definition of TDES7 register */
bogdanm 89:552587b429a1 812 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
bogdanm 89:552587b429a1 813
bogdanm 89:552587b429a1 814 /**
bogdanm 89:552587b429a1 815 * @}
bogdanm 89:552587b429a1 816 */
Kojto 99:dbbf35b96557 817 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
bogdanm 89:552587b429a1 818 * @{
bogdanm 89:552587b429a1 819 */
bogdanm 89:552587b429a1 820
bogdanm 89:552587b429a1 821 /*
bogdanm 89:552587b429a1 822 DMA Rx Descriptor
bogdanm 89:552587b429a1 823 --------------------------------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 824 RDES0 | OWN(31) | Status [30:0] |
bogdanm 89:552587b429a1 825 ---------------------------------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 826 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
bogdanm 89:552587b429a1 827 ---------------------------------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 828 RDES2 | Buffer1 Address [31:0] |
bogdanm 89:552587b429a1 829 ---------------------------------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 830 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
bogdanm 89:552587b429a1 831 ---------------------------------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 832 */
bogdanm 89:552587b429a1 833
bogdanm 89:552587b429a1 834 /**
bogdanm 89:552587b429a1 835 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
bogdanm 89:552587b429a1 836 */
bogdanm 89:552587b429a1 837 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
bogdanm 89:552587b429a1 838 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
bogdanm 89:552587b429a1 839 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
bogdanm 89:552587b429a1 840 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
bogdanm 89:552587b429a1 841 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
bogdanm 89:552587b429a1 842 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
bogdanm 89:552587b429a1 843 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
bogdanm 89:552587b429a1 844 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
bogdanm 89:552587b429a1 845 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
bogdanm 89:552587b429a1 846 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
bogdanm 89:552587b429a1 847 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
bogdanm 89:552587b429a1 848 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
bogdanm 89:552587b429a1 849 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
bogdanm 89:552587b429a1 850 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
bogdanm 89:552587b429a1 851 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
bogdanm 89:552587b429a1 852 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
bogdanm 89:552587b429a1 853 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
bogdanm 89:552587b429a1 854 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
bogdanm 89:552587b429a1 855 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
bogdanm 89:552587b429a1 856
bogdanm 89:552587b429a1 857 /**
bogdanm 89:552587b429a1 858 * @brief Bit definition of RDES1 register
bogdanm 89:552587b429a1 859 */
bogdanm 89:552587b429a1 860 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
bogdanm 89:552587b429a1 861 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
bogdanm 89:552587b429a1 862 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
bogdanm 89:552587b429a1 863 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
bogdanm 89:552587b429a1 864 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
bogdanm 89:552587b429a1 865
bogdanm 89:552587b429a1 866 /**
bogdanm 89:552587b429a1 867 * @brief Bit definition of RDES2 register
bogdanm 89:552587b429a1 868 */
bogdanm 89:552587b429a1 869 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
bogdanm 89:552587b429a1 870
bogdanm 89:552587b429a1 871 /**
bogdanm 89:552587b429a1 872 * @brief Bit definition of RDES3 register
bogdanm 89:552587b429a1 873 */
bogdanm 89:552587b429a1 874 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
bogdanm 89:552587b429a1 875
bogdanm 89:552587b429a1 876 /*---------------------------------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 877 RDES4 | Reserved[31:15] | Extended Status [14:0] |
bogdanm 89:552587b429a1 878 ---------------------------------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 879 RDES5 | Reserved[31:0] |
bogdanm 89:552587b429a1 880 ---------------------------------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 881 RDES6 | Receive Time Stamp Low [31:0] |
bogdanm 89:552587b429a1 882 ---------------------------------------------------------------------------------------------------------------------
bogdanm 89:552587b429a1 883 RDES7 | Receive Time Stamp High [31:0] |
bogdanm 89:552587b429a1 884 --------------------------------------------------------------------------------------------------------------------*/
bogdanm 89:552587b429a1 885
bogdanm 89:552587b429a1 886 /* Bit definition of RDES4 register */
bogdanm 89:552587b429a1 887 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
bogdanm 89:552587b429a1 888 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
bogdanm 89:552587b429a1 889 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
bogdanm 89:552587b429a1 890 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
bogdanm 89:552587b429a1 891 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
bogdanm 89:552587b429a1 892 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
bogdanm 89:552587b429a1 893 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
bogdanm 89:552587b429a1 894 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
bogdanm 89:552587b429a1 895 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
bogdanm 89:552587b429a1 896 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
bogdanm 89:552587b429a1 897 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
bogdanm 89:552587b429a1 898 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
bogdanm 89:552587b429a1 899 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
bogdanm 89:552587b429a1 900 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
bogdanm 89:552587b429a1 901 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
bogdanm 89:552587b429a1 902 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
bogdanm 89:552587b429a1 903 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
bogdanm 89:552587b429a1 904 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
bogdanm 89:552587b429a1 905 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
bogdanm 89:552587b429a1 906
bogdanm 89:552587b429a1 907 /* Bit definition of RDES6 register */
bogdanm 89:552587b429a1 908 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
bogdanm 89:552587b429a1 909
bogdanm 89:552587b429a1 910 /* Bit definition of RDES7 register */
bogdanm 89:552587b429a1 911 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
Kojto 99:dbbf35b96557 912 /**
Kojto 99:dbbf35b96557 913 * @}
Kojto 99:dbbf35b96557 914 */
Kojto 99:dbbf35b96557 915 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
bogdanm 89:552587b429a1 916 * @{
bogdanm 89:552587b429a1 917 */
bogdanm 89:552587b429a1 918 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 919 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 920
bogdanm 89:552587b429a1 921 /**
bogdanm 89:552587b429a1 922 * @}
bogdanm 89:552587b429a1 923 */
Kojto 99:dbbf35b96557 924 /** @defgroup ETH_Speed ETH Speed
bogdanm 89:552587b429a1 925 * @{
bogdanm 89:552587b429a1 926 */
bogdanm 89:552587b429a1 927 #define ETH_SPEED_10M ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 928 #define ETH_SPEED_100M ((uint32_t)0x00004000)
Kojto 99:dbbf35b96557 929
bogdanm 89:552587b429a1 930 /**
bogdanm 89:552587b429a1 931 * @}
bogdanm 89:552587b429a1 932 */
Kojto 99:dbbf35b96557 933 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
bogdanm 89:552587b429a1 934 * @{
bogdanm 89:552587b429a1 935 */
bogdanm 89:552587b429a1 936 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 937 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 938 /**
bogdanm 89:552587b429a1 939 * @}
bogdanm 89:552587b429a1 940 */
Kojto 99:dbbf35b96557 941 /** @defgroup ETH_Rx_Mode ETH Rx Mode
bogdanm 89:552587b429a1 942 * @{
bogdanm 89:552587b429a1 943 */
bogdanm 89:552587b429a1 944 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 945 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 946 /**
bogdanm 89:552587b429a1 947 * @}
bogdanm 89:552587b429a1 948 */
bogdanm 89:552587b429a1 949
Kojto 99:dbbf35b96557 950 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
bogdanm 89:552587b429a1 951 * @{
bogdanm 89:552587b429a1 952 */
bogdanm 89:552587b429a1 953 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 954 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 955 /**
bogdanm 89:552587b429a1 956 * @}
bogdanm 89:552587b429a1 957 */
bogdanm 89:552587b429a1 958
Kojto 99:dbbf35b96557 959 /** @defgroup ETH_Media_Interface ETH Media Interface
bogdanm 89:552587b429a1 960 * @{
bogdanm 89:552587b429a1 961 */
bogdanm 89:552587b429a1 962 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 963 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
bogdanm 89:552587b429a1 964 /**
bogdanm 89:552587b429a1 965 * @}
bogdanm 89:552587b429a1 966 */
bogdanm 89:552587b429a1 967
Kojto 99:dbbf35b96557 968 /** @defgroup ETH_Watchdog ETH Watchdog
bogdanm 89:552587b429a1 969 * @{
bogdanm 89:552587b429a1 970 */
bogdanm 89:552587b429a1 971 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 972 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 973 /**
bogdanm 89:552587b429a1 974 * @}
bogdanm 89:552587b429a1 975 */
bogdanm 89:552587b429a1 976
Kojto 99:dbbf35b96557 977 /** @defgroup ETH_Jabber ETH Jabber
bogdanm 89:552587b429a1 978 * @{
bogdanm 89:552587b429a1 979 */
bogdanm 89:552587b429a1 980 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 981 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 982 /**
bogdanm 89:552587b429a1 983 * @}
bogdanm 89:552587b429a1 984 */
bogdanm 89:552587b429a1 985
Kojto 99:dbbf35b96557 986 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
bogdanm 89:552587b429a1 987 * @{
bogdanm 89:552587b429a1 988 */
bogdanm 89:552587b429a1 989 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
bogdanm 89:552587b429a1 990 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
bogdanm 89:552587b429a1 991 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
bogdanm 89:552587b429a1 992 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
bogdanm 89:552587b429a1 993 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
bogdanm 89:552587b429a1 994 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
bogdanm 89:552587b429a1 995 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
bogdanm 89:552587b429a1 996 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
bogdanm 89:552587b429a1 997 /**
bogdanm 89:552587b429a1 998 * @}
bogdanm 89:552587b429a1 999 */
bogdanm 89:552587b429a1 1000
Kojto 99:dbbf35b96557 1001 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
bogdanm 89:552587b429a1 1002 * @{
bogdanm 89:552587b429a1 1003 */
bogdanm 89:552587b429a1 1004 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 1005 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 1006 /**
bogdanm 89:552587b429a1 1007 * @}
bogdanm 89:552587b429a1 1008 */
bogdanm 89:552587b429a1 1009
Kojto 99:dbbf35b96557 1010 /** @defgroup ETH_Receive_Own ETH Receive Own
bogdanm 89:552587b429a1 1011 * @{
bogdanm 89:552587b429a1 1012 */
bogdanm 89:552587b429a1 1013 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 1014 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 1015 /**
bogdanm 89:552587b429a1 1016 * @}
bogdanm 89:552587b429a1 1017 */
bogdanm 89:552587b429a1 1018
Kojto 99:dbbf35b96557 1019 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
bogdanm 89:552587b429a1 1020 * @{
bogdanm 89:552587b429a1 1021 */
bogdanm 89:552587b429a1 1022 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 1023 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1024 /**
bogdanm 89:552587b429a1 1025 * @}
bogdanm 89:552587b429a1 1026 */
bogdanm 89:552587b429a1 1027
Kojto 99:dbbf35b96557 1028 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
bogdanm 89:552587b429a1 1029 * @{
bogdanm 89:552587b429a1 1030 */
bogdanm 89:552587b429a1 1031 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 1032 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1033 /**
bogdanm 89:552587b429a1 1034 * @}
bogdanm 89:552587b429a1 1035 */
bogdanm 89:552587b429a1 1036
Kojto 99:dbbf35b96557 1037 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
bogdanm 89:552587b429a1 1038 * @{
bogdanm 89:552587b429a1 1039 */
bogdanm 89:552587b429a1 1040 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1041 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 1042 /**
bogdanm 89:552587b429a1 1043 * @}
bogdanm 89:552587b429a1 1044 */
bogdanm 89:552587b429a1 1045
Kojto 99:dbbf35b96557 1046 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
bogdanm 89:552587b429a1 1047 * @{
bogdanm 89:552587b429a1 1048 */
bogdanm 89:552587b429a1 1049 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 1050 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1051 /**
bogdanm 89:552587b429a1 1052 * @}
bogdanm 89:552587b429a1 1053 */
bogdanm 89:552587b429a1 1054
Kojto 99:dbbf35b96557 1055 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
bogdanm 89:552587b429a1 1056 * @{
bogdanm 89:552587b429a1 1057 */
bogdanm 89:552587b429a1 1058 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1059 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 1060 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 1061 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
bogdanm 89:552587b429a1 1062 /**
bogdanm 89:552587b429a1 1063 * @}
bogdanm 89:552587b429a1 1064 */
bogdanm 89:552587b429a1 1065
Kojto 99:dbbf35b96557 1066 /** @defgroup ETH_Deferral_Check ETH Deferral Check
bogdanm 89:552587b429a1 1067 * @{
bogdanm 89:552587b429a1 1068 */
bogdanm 89:552587b429a1 1069 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 1070 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1071 /**
bogdanm 89:552587b429a1 1072 * @}
bogdanm 89:552587b429a1 1073 */
bogdanm 89:552587b429a1 1074
Kojto 99:dbbf35b96557 1075 /** @defgroup ETH_Receive_All ETH Receive All
bogdanm 89:552587b429a1 1076 * @{
bogdanm 89:552587b429a1 1077 */
bogdanm 89:552587b429a1 1078 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
bogdanm 89:552587b429a1 1079 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1080 /**
bogdanm 89:552587b429a1 1081 * @}
bogdanm 89:552587b429a1 1082 */
bogdanm 89:552587b429a1 1083
Kojto 99:dbbf35b96557 1084 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
bogdanm 89:552587b429a1 1085 * @{
bogdanm 89:552587b429a1 1086 */
bogdanm 89:552587b429a1 1087 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 1088 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
bogdanm 89:552587b429a1 1089 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1090 /**
bogdanm 89:552587b429a1 1091 * @}
bogdanm 89:552587b429a1 1092 */
bogdanm 89:552587b429a1 1093
Kojto 99:dbbf35b96557 1094 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
bogdanm 89:552587b429a1 1095 * @{
bogdanm 89:552587b429a1 1096 */
bogdanm 89:552587b429a1 1097 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
bogdanm 89:552587b429a1 1098 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
bogdanm 89:552587b429a1 1099 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
bogdanm 89:552587b429a1 1100 /**
bogdanm 89:552587b429a1 1101 * @}
bogdanm 89:552587b429a1 1102 */
bogdanm 89:552587b429a1 1103
Kojto 99:dbbf35b96557 1104 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
bogdanm 89:552587b429a1 1105 * @{
bogdanm 89:552587b429a1 1106 */
bogdanm 89:552587b429a1 1107 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1108 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 1109 /**
bogdanm 89:552587b429a1 1110 * @}
bogdanm 89:552587b429a1 1111 */
bogdanm 89:552587b429a1 1112
Kojto 99:dbbf35b96557 1113 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
bogdanm 89:552587b429a1 1114 * @{
bogdanm 89:552587b429a1 1115 */
bogdanm 89:552587b429a1 1116 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1117 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 1118 /**
bogdanm 89:552587b429a1 1119 * @}
bogdanm 89:552587b429a1 1120 */
bogdanm 89:552587b429a1 1121
Kojto 99:dbbf35b96557 1122 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
bogdanm 89:552587b429a1 1123 * @{
bogdanm 89:552587b429a1 1124 */
Kojto 99:dbbf35b96557 1125 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
Kojto 99:dbbf35b96557 1126 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1127 /**
bogdanm 89:552587b429a1 1128 * @}
bogdanm 89:552587b429a1 1129 */
bogdanm 89:552587b429a1 1130
Kojto 99:dbbf35b96557 1131 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
bogdanm 89:552587b429a1 1132 * @{
bogdanm 89:552587b429a1 1133 */
bogdanm 89:552587b429a1 1134 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
bogdanm 89:552587b429a1 1135 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 1136 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1137 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 1138 /**
bogdanm 89:552587b429a1 1139 * @}
bogdanm 89:552587b429a1 1140 */
bogdanm 89:552587b429a1 1141
Kojto 99:dbbf35b96557 1142 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
bogdanm 89:552587b429a1 1143 * @{
bogdanm 89:552587b429a1 1144 */
bogdanm 89:552587b429a1 1145 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
bogdanm 89:552587b429a1 1146 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 1147 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1148 /**
bogdanm 89:552587b429a1 1149 * @}
bogdanm 89:552587b429a1 1150 */
bogdanm 89:552587b429a1 1151
Kojto 99:dbbf35b96557 1152 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
bogdanm 89:552587b429a1 1153 * @{
bogdanm 89:552587b429a1 1154 */
Kojto 99:dbbf35b96557 1155 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 1156 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 1157 /**
bogdanm 89:552587b429a1 1158 * @}
bogdanm 89:552587b429a1 1159 */
bogdanm 89:552587b429a1 1160
Kojto 99:dbbf35b96557 1161 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
bogdanm 89:552587b429a1 1162 * @{
bogdanm 89:552587b429a1 1163 */
bogdanm 89:552587b429a1 1164 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
bogdanm 89:552587b429a1 1165 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
bogdanm 89:552587b429a1 1166 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
bogdanm 89:552587b429a1 1167 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
bogdanm 89:552587b429a1 1168 /**
bogdanm 89:552587b429a1 1169 * @}
bogdanm 89:552587b429a1 1170 */
bogdanm 89:552587b429a1 1171
Kojto 99:dbbf35b96557 1172 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
bogdanm 89:552587b429a1 1173 * @{
bogdanm 89:552587b429a1 1174 */
bogdanm 89:552587b429a1 1175 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 1176 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1177 /**
bogdanm 89:552587b429a1 1178 * @}
bogdanm 89:552587b429a1 1179 */
bogdanm 89:552587b429a1 1180
Kojto 99:dbbf35b96557 1181 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
bogdanm 89:552587b429a1 1182 * @{
bogdanm 89:552587b429a1 1183 */
bogdanm 89:552587b429a1 1184 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 1185 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1186 /**
bogdanm 89:552587b429a1 1187 * @}
bogdanm 89:552587b429a1 1188 */
bogdanm 89:552587b429a1 1189
Kojto 99:dbbf35b96557 1190 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
bogdanm 89:552587b429a1 1191 * @{
bogdanm 89:552587b429a1 1192 */
bogdanm 89:552587b429a1 1193 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 1194 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1195 /**
bogdanm 89:552587b429a1 1196 * @}
bogdanm 89:552587b429a1 1197 */
bogdanm 89:552587b429a1 1198
Kojto 99:dbbf35b96557 1199 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
bogdanm 89:552587b429a1 1200 * @{
bogdanm 89:552587b429a1 1201 */
bogdanm 89:552587b429a1 1202 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 1203 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1204 /**
bogdanm 89:552587b429a1 1205 * @}
bogdanm 89:552587b429a1 1206 */
bogdanm 89:552587b429a1 1207
Kojto 99:dbbf35b96557 1208 /** @defgroup ETH_MAC_addresses ETH MAC addresses
bogdanm 89:552587b429a1 1209 * @{
bogdanm 89:552587b429a1 1210 */
bogdanm 89:552587b429a1 1211 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1212 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 1213 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 1214 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
bogdanm 89:552587b429a1 1215 /**
bogdanm 89:552587b429a1 1216 * @}
bogdanm 89:552587b429a1 1217 */
bogdanm 89:552587b429a1 1218
Kojto 99:dbbf35b96557 1219 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
bogdanm 89:552587b429a1 1220 * @{
bogdanm 89:552587b429a1 1221 */
bogdanm 89:552587b429a1 1222 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1223 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 1224 /**
bogdanm 89:552587b429a1 1225 * @}
bogdanm 89:552587b429a1 1226 */
bogdanm 89:552587b429a1 1227
Kojto 99:dbbf35b96557 1228 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
bogdanm 89:552587b429a1 1229 * @{
bogdanm 89:552587b429a1 1230 */
bogdanm 89:552587b429a1 1231 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
bogdanm 89:552587b429a1 1232 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
bogdanm 89:552587b429a1 1233 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
bogdanm 89:552587b429a1 1234 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
bogdanm 89:552587b429a1 1235 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
bogdanm 89:552587b429a1 1236 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
bogdanm 89:552587b429a1 1237 /**
bogdanm 89:552587b429a1 1238 * @}
bogdanm 89:552587b429a1 1239 */
bogdanm 89:552587b429a1 1240
Kojto 99:dbbf35b96557 1241 /** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
bogdanm 89:552587b429a1 1242 * @{
bogdanm 89:552587b429a1 1243 */
bogdanm 89:552587b429a1 1244 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
bogdanm 89:552587b429a1 1245 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
bogdanm 89:552587b429a1 1246 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
bogdanm 89:552587b429a1 1247 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
bogdanm 89:552587b429a1 1248 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
bogdanm 89:552587b429a1 1249 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
bogdanm 89:552587b429a1 1250 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
bogdanm 89:552587b429a1 1251 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
bogdanm 89:552587b429a1 1252 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
bogdanm 89:552587b429a1 1253 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
bogdanm 89:552587b429a1 1254 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
bogdanm 89:552587b429a1 1255 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
bogdanm 89:552587b429a1 1256 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
bogdanm 89:552587b429a1 1257 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
bogdanm 89:552587b429a1 1258 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
bogdanm 89:552587b429a1 1259 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
bogdanm 89:552587b429a1 1260 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
bogdanm 89:552587b429a1 1261 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
bogdanm 89:552587b429a1 1262 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
bogdanm 89:552587b429a1 1263 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
bogdanm 89:552587b429a1 1264 #define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
bogdanm 89:552587b429a1 1265 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
bogdanm 89:552587b429a1 1266 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
bogdanm 89:552587b429a1 1267 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
bogdanm 89:552587b429a1 1268 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
bogdanm 89:552587b429a1 1269 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
Kojto 99:dbbf35b96557 1270 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
bogdanm 89:552587b429a1 1271 /**
bogdanm 89:552587b429a1 1272 * @}
bogdanm 89:552587b429a1 1273 */
bogdanm 89:552587b429a1 1274
Kojto 99:dbbf35b96557 1275 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
bogdanm 89:552587b429a1 1276 * @{
bogdanm 89:552587b429a1 1277 */
bogdanm 89:552587b429a1 1278 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1279 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 1280 /**
bogdanm 89:552587b429a1 1281 * @}
bogdanm 89:552587b429a1 1282 */
bogdanm 89:552587b429a1 1283
Kojto 99:dbbf35b96557 1284 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
bogdanm 89:552587b429a1 1285 * @{
bogdanm 89:552587b429a1 1286 */
bogdanm 89:552587b429a1 1287 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 1288 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1289 /**
bogdanm 89:552587b429a1 1290 * @}
bogdanm 89:552587b429a1 1291 */
bogdanm 89:552587b429a1 1292
Kojto 99:dbbf35b96557 1293 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
bogdanm 89:552587b429a1 1294 * @{
bogdanm 89:552587b429a1 1295 */
bogdanm 89:552587b429a1 1296 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1297 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 1298 /**
bogdanm 89:552587b429a1 1299 * @}
bogdanm 89:552587b429a1 1300 */
bogdanm 89:552587b429a1 1301
Kojto 99:dbbf35b96557 1302 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
bogdanm 89:552587b429a1 1303 * @{
bogdanm 89:552587b429a1 1304 */
bogdanm 89:552587b429a1 1305 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 1306 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1307 /**
bogdanm 89:552587b429a1 1308 * @}
bogdanm 89:552587b429a1 1309 */
bogdanm 89:552587b429a1 1310
Kojto 99:dbbf35b96557 1311 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
bogdanm 89:552587b429a1 1312 * @{
bogdanm 89:552587b429a1 1313 */
bogdanm 89:552587b429a1 1314 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
bogdanm 89:552587b429a1 1315 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
bogdanm 89:552587b429a1 1316 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
bogdanm 89:552587b429a1 1317 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
bogdanm 89:552587b429a1 1318 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
bogdanm 89:552587b429a1 1319 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
bogdanm 89:552587b429a1 1320 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
bogdanm 89:552587b429a1 1321 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
bogdanm 89:552587b429a1 1322 /**
bogdanm 89:552587b429a1 1323 * @}
bogdanm 89:552587b429a1 1324 */
bogdanm 89:552587b429a1 1325
Kojto 99:dbbf35b96557 1326 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
bogdanm 89:552587b429a1 1327 * @{
bogdanm 89:552587b429a1 1328 */
bogdanm 89:552587b429a1 1329 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 1330 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1331 /**
bogdanm 89:552587b429a1 1332 * @}
bogdanm 89:552587b429a1 1333 */
bogdanm 89:552587b429a1 1334
Kojto 99:dbbf35b96557 1335 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
bogdanm 89:552587b429a1 1336 * @{
bogdanm 89:552587b429a1 1337 */
bogdanm 89:552587b429a1 1338 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 1339 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1340 /**
bogdanm 89:552587b429a1 1341 * @}
bogdanm 89:552587b429a1 1342 */
bogdanm 89:552587b429a1 1343
Kojto 99:dbbf35b96557 1344 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
bogdanm 89:552587b429a1 1345 * @{
bogdanm 89:552587b429a1 1346 */
bogdanm 89:552587b429a1 1347 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
bogdanm 89:552587b429a1 1348 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
bogdanm 89:552587b429a1 1349 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
bogdanm 89:552587b429a1 1350 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
bogdanm 89:552587b429a1 1351 /**
bogdanm 89:552587b429a1 1352 * @}
bogdanm 89:552587b429a1 1353 */
bogdanm 89:552587b429a1 1354
Kojto 99:dbbf35b96557 1355 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
bogdanm 89:552587b429a1 1356 * @{
bogdanm 89:552587b429a1 1357 */
bogdanm 89:552587b429a1 1358 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 1359 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1360 /**
bogdanm 89:552587b429a1 1361 * @}
bogdanm 89:552587b429a1 1362 */
bogdanm 89:552587b429a1 1363
Kojto 99:dbbf35b96557 1364 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
bogdanm 89:552587b429a1 1365 * @{
bogdanm 89:552587b429a1 1366 */
bogdanm 89:552587b429a1 1367 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 1368 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1369 /**
bogdanm 89:552587b429a1 1370 * @}
bogdanm 89:552587b429a1 1371 */
bogdanm 89:552587b429a1 1372
Kojto 99:dbbf35b96557 1373 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
bogdanm 89:552587b429a1 1374 * @{
bogdanm 89:552587b429a1 1375 */
bogdanm 89:552587b429a1 1376 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 1377 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1378 /**
bogdanm 89:552587b429a1 1379 * @}
bogdanm 89:552587b429a1 1380 */
bogdanm 89:552587b429a1 1381
Kojto 99:dbbf35b96557 1382 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
bogdanm 89:552587b429a1 1383 * @{
bogdanm 89:552587b429a1 1384 */
bogdanm 89:552587b429a1 1385 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
bogdanm 89:552587b429a1 1386 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
bogdanm 89:552587b429a1 1387 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
bogdanm 89:552587b429a1 1388 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
bogdanm 89:552587b429a1 1389 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
bogdanm 89:552587b429a1 1390 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
bogdanm 89:552587b429a1 1391 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
bogdanm 89:552587b429a1 1392 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
bogdanm 89:552587b429a1 1393 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
bogdanm 89:552587b429a1 1394 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
bogdanm 89:552587b429a1 1395 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
bogdanm 89:552587b429a1 1396 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
bogdanm 89:552587b429a1 1397 /**
bogdanm 89:552587b429a1 1398 * @}
bogdanm 89:552587b429a1 1399 */
bogdanm 89:552587b429a1 1400
Kojto 99:dbbf35b96557 1401 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
bogdanm 89:552587b429a1 1402 * @{
bogdanm 89:552587b429a1 1403 */
bogdanm 89:552587b429a1 1404 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
bogdanm 89:552587b429a1 1405 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
bogdanm 89:552587b429a1 1406 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
bogdanm 89:552587b429a1 1407 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
bogdanm 89:552587b429a1 1408 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
bogdanm 89:552587b429a1 1409 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
bogdanm 89:552587b429a1 1410 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
bogdanm 89:552587b429a1 1411 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
bogdanm 89:552587b429a1 1412 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
bogdanm 89:552587b429a1 1413 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
bogdanm 89:552587b429a1 1414 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
bogdanm 89:552587b429a1 1415 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
Kojto 99:dbbf35b96557 1416 /**
Kojto 99:dbbf35b96557 1417 * @}
Kojto 99:dbbf35b96557 1418 */
bogdanm 89:552587b429a1 1419
Kojto 99:dbbf35b96557 1420 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
bogdanm 89:552587b429a1 1421 * @{
bogdanm 89:552587b429a1 1422 */
bogdanm 89:552587b429a1 1423 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 1424 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1425 /**
bogdanm 89:552587b429a1 1426 * @}
bogdanm 89:552587b429a1 1427 */
bogdanm 89:552587b429a1 1428
Kojto 99:dbbf35b96557 1429 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
bogdanm 89:552587b429a1 1430 * @{
bogdanm 89:552587b429a1 1431 */
bogdanm 89:552587b429a1 1432 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 1433 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 1434 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 1435 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
bogdanm 89:552587b429a1 1436 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 1437 /**
bogdanm 89:552587b429a1 1438 * @}
bogdanm 89:552587b429a1 1439 */
bogdanm 89:552587b429a1 1440
Kojto 99:dbbf35b96557 1441 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
bogdanm 89:552587b429a1 1442 * @{
bogdanm 89:552587b429a1 1443 */
Kojto 99:dbbf35b96557 1444 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
Kojto 99:dbbf35b96557 1445 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
bogdanm 89:552587b429a1 1446 /**
bogdanm 89:552587b429a1 1447 * @}
bogdanm 89:552587b429a1 1448 */
bogdanm 89:552587b429a1 1449
Kojto 99:dbbf35b96557 1450 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
bogdanm 89:552587b429a1 1451 * @{
bogdanm 89:552587b429a1 1452 */
bogdanm 89:552587b429a1 1453 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
bogdanm 89:552587b429a1 1454 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
bogdanm 89:552587b429a1 1455 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
bogdanm 89:552587b429a1 1456 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
bogdanm 89:552587b429a1 1457 /**
bogdanm 89:552587b429a1 1458 * @}
bogdanm 89:552587b429a1 1459 */
bogdanm 89:552587b429a1 1460
Kojto 99:dbbf35b96557 1461 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
bogdanm 89:552587b429a1 1462 * @{
bogdanm 89:552587b429a1 1463 */
Kojto 99:dbbf35b96557 1464 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
Kojto 99:dbbf35b96557 1465 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
bogdanm 89:552587b429a1 1466 /**
bogdanm 89:552587b429a1 1467 * @}
bogdanm 89:552587b429a1 1468 */
bogdanm 89:552587b429a1 1469
Kojto 99:dbbf35b96557 1470 /** @defgroup ETH_PMT_Flags ETH PMT Flags
bogdanm 89:552587b429a1 1471 * @{
bogdanm 89:552587b429a1 1472 */
bogdanm 89:552587b429a1 1473 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
bogdanm 89:552587b429a1 1474 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
bogdanm 89:552587b429a1 1475 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
bogdanm 89:552587b429a1 1476 /**
bogdanm 89:552587b429a1 1477 * @}
bogdanm 89:552587b429a1 1478 */
bogdanm 89:552587b429a1 1479
Kojto 99:dbbf35b96557 1480 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
bogdanm 89:552587b429a1 1481 * @{
bogdanm 89:552587b429a1 1482 */
bogdanm 89:552587b429a1 1483 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
bogdanm 89:552587b429a1 1484 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
bogdanm 89:552587b429a1 1485 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
bogdanm 89:552587b429a1 1486 /**
bogdanm 89:552587b429a1 1487 * @}
bogdanm 89:552587b429a1 1488 */
bogdanm 89:552587b429a1 1489
Kojto 99:dbbf35b96557 1490 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
bogdanm 89:552587b429a1 1491 * @{
bogdanm 89:552587b429a1 1492 */
bogdanm 89:552587b429a1 1493 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
bogdanm 89:552587b429a1 1494 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
bogdanm 89:552587b429a1 1495 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
bogdanm 89:552587b429a1 1496 /**
bogdanm 89:552587b429a1 1497 * @}
bogdanm 89:552587b429a1 1498 */
bogdanm 89:552587b429a1 1499
Kojto 99:dbbf35b96557 1500 /** @defgroup ETH_MAC_Flags ETH MAC Flags
bogdanm 89:552587b429a1 1501 * @{
bogdanm 89:552587b429a1 1502 */
bogdanm 89:552587b429a1 1503 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
bogdanm 89:552587b429a1 1504 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
bogdanm 89:552587b429a1 1505 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
bogdanm 89:552587b429a1 1506 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
bogdanm 89:552587b429a1 1507 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
bogdanm 89:552587b429a1 1508 /**
bogdanm 89:552587b429a1 1509 * @}
bogdanm 89:552587b429a1 1510 */
bogdanm 89:552587b429a1 1511
Kojto 99:dbbf35b96557 1512 /** @defgroup ETH_DMA_Flags ETH DMA Flags
bogdanm 89:552587b429a1 1513 * @{
bogdanm 89:552587b429a1 1514 */
bogdanm 89:552587b429a1 1515 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
bogdanm 89:552587b429a1 1516 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
bogdanm 89:552587b429a1 1517 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
bogdanm 89:552587b429a1 1518 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
Kojto 99:dbbf35b96557 1519 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */
bogdanm 89:552587b429a1 1520 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
bogdanm 89:552587b429a1 1521 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
bogdanm 89:552587b429a1 1522 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
bogdanm 89:552587b429a1 1523 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
bogdanm 89:552587b429a1 1524 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
bogdanm 89:552587b429a1 1525 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
bogdanm 89:552587b429a1 1526 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
bogdanm 89:552587b429a1 1527 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
bogdanm 89:552587b429a1 1528 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
bogdanm 89:552587b429a1 1529 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
bogdanm 89:552587b429a1 1530 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
bogdanm 89:552587b429a1 1531 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
bogdanm 89:552587b429a1 1532 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
bogdanm 89:552587b429a1 1533 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
bogdanm 89:552587b429a1 1534 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
bogdanm 89:552587b429a1 1535 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
bogdanm 89:552587b429a1 1536 /**
bogdanm 89:552587b429a1 1537 * @}
bogdanm 89:552587b429a1 1538 */
bogdanm 89:552587b429a1 1539
Kojto 99:dbbf35b96557 1540 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
bogdanm 89:552587b429a1 1541 * @{
bogdanm 89:552587b429a1 1542 */
bogdanm 89:552587b429a1 1543 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
bogdanm 89:552587b429a1 1544 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
bogdanm 89:552587b429a1 1545 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
bogdanm 89:552587b429a1 1546 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
bogdanm 89:552587b429a1 1547 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
bogdanm 89:552587b429a1 1548 /**
bogdanm 89:552587b429a1 1549 * @}
bogdanm 89:552587b429a1 1550 */
bogdanm 89:552587b429a1 1551
Kojto 99:dbbf35b96557 1552 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
bogdanm 89:552587b429a1 1553 * @{
bogdanm 89:552587b429a1 1554 */
bogdanm 89:552587b429a1 1555 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
bogdanm 89:552587b429a1 1556 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
bogdanm 89:552587b429a1 1557 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
bogdanm 89:552587b429a1 1558 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
bogdanm 89:552587b429a1 1559 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
bogdanm 89:552587b429a1 1560 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
bogdanm 89:552587b429a1 1561 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
bogdanm 89:552587b429a1 1562 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
bogdanm 89:552587b429a1 1563 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
bogdanm 89:552587b429a1 1564 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
bogdanm 89:552587b429a1 1565 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
bogdanm 89:552587b429a1 1566 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
bogdanm 89:552587b429a1 1567 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
bogdanm 89:552587b429a1 1568 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
bogdanm 89:552587b429a1 1569 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
bogdanm 89:552587b429a1 1570 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
bogdanm 89:552587b429a1 1571 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
bogdanm 89:552587b429a1 1572 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
bogdanm 89:552587b429a1 1573 /**
bogdanm 89:552587b429a1 1574 * @}
bogdanm 89:552587b429a1 1575 */
bogdanm 89:552587b429a1 1576
Kojto 99:dbbf35b96557 1577 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
bogdanm 89:552587b429a1 1578 * @{
bogdanm 89:552587b429a1 1579 */
bogdanm 89:552587b429a1 1580 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
bogdanm 89:552587b429a1 1581 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
bogdanm 89:552587b429a1 1582 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
bogdanm 89:552587b429a1 1583 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
bogdanm 89:552587b429a1 1584 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
bogdanm 89:552587b429a1 1585 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
bogdanm 89:552587b429a1 1586
bogdanm 89:552587b429a1 1587 /**
bogdanm 89:552587b429a1 1588 * @}
bogdanm 89:552587b429a1 1589 */
bogdanm 89:552587b429a1 1590
bogdanm 89:552587b429a1 1591
Kojto 99:dbbf35b96557 1592 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
bogdanm 89:552587b429a1 1593 * @{
bogdanm 89:552587b429a1 1594 */
bogdanm 89:552587b429a1 1595 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
bogdanm 89:552587b429a1 1596 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
bogdanm 89:552587b429a1 1597 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
bogdanm 89:552587b429a1 1598 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
bogdanm 89:552587b429a1 1599 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
bogdanm 89:552587b429a1 1600 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
bogdanm 89:552587b429a1 1601
bogdanm 89:552587b429a1 1602 /**
bogdanm 89:552587b429a1 1603 * @}
bogdanm 89:552587b429a1 1604 */
bogdanm 89:552587b429a1 1605
Kojto 99:dbbf35b96557 1606 /** @defgroup ETH_DMA_overflow ETH DMA overflow
bogdanm 89:552587b429a1 1607 * @{
bogdanm 89:552587b429a1 1608 */
bogdanm 89:552587b429a1 1609 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
bogdanm 89:552587b429a1 1610 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
bogdanm 89:552587b429a1 1611 /**
bogdanm 89:552587b429a1 1612 * @}
bogdanm 89:552587b429a1 1613 */
bogdanm 89:552587b429a1 1614
Kojto 99:dbbf35b96557 1615 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
Kojto 99:dbbf35b96557 1616 * @{
Kojto 99:dbbf35b96557 1617 */
Kojto 99:dbbf35b96557 1618 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
bogdanm 89:552587b429a1 1619
Kojto 99:dbbf35b96557 1620 /**
Kojto 99:dbbf35b96557 1621 * @}
Kojto 99:dbbf35b96557 1622 */
bogdanm 89:552587b429a1 1623
bogdanm 89:552587b429a1 1624 /**
bogdanm 89:552587b429a1 1625 * @}
bogdanm 89:552587b429a1 1626 */
bogdanm 89:552587b429a1 1627
bogdanm 89:552587b429a1 1628 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 1629 /** @defgroup ETH_Exported_Macros ETH Exported Macros
Kojto 99:dbbf35b96557 1630 * @brief macros to handle interrupts and specific clock configurations
Kojto 99:dbbf35b96557 1631 * @{
Kojto 99:dbbf35b96557 1632 */
Kojto 99:dbbf35b96557 1633
bogdanm 89:552587b429a1 1634 /** @brief Reset ETH handle state
bogdanm 89:552587b429a1 1635 * @param __HANDLE__: specifies the ETH handle.
bogdanm 89:552587b429a1 1636 * @retval None
bogdanm 89:552587b429a1 1637 */
bogdanm 89:552587b429a1 1638 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
bogdanm 89:552587b429a1 1639
bogdanm 89:552587b429a1 1640 /**
bogdanm 89:552587b429a1 1641 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
bogdanm 89:552587b429a1 1642 * @param __HANDLE__: ETH Handle
Kojto 99:dbbf35b96557 1643 * @param __FLAG__: specifies the flag of TDES0 to check.
bogdanm 89:552587b429a1 1644 * @retval the ETH_DMATxDescFlag (SET or RESET).
bogdanm 89:552587b429a1 1645 */
bogdanm 89:552587b429a1 1646 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
bogdanm 89:552587b429a1 1647
bogdanm 89:552587b429a1 1648 /**
bogdanm 89:552587b429a1 1649 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
bogdanm 89:552587b429a1 1650 * @param __HANDLE__: ETH Handle
Kojto 99:dbbf35b96557 1651 * @param __FLAG__: specifies the flag of RDES0 to check.
bogdanm 89:552587b429a1 1652 * @retval the ETH_DMATxDescFlag (SET or RESET).
bogdanm 89:552587b429a1 1653 */
bogdanm 89:552587b429a1 1654 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
bogdanm 89:552587b429a1 1655
bogdanm 89:552587b429a1 1656 /**
bogdanm 89:552587b429a1 1657 * @brief Enables the specified DMA Rx Desc receive interrupt.
bogdanm 89:552587b429a1 1658 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1659 * @retval None
bogdanm 89:552587b429a1 1660 */
bogdanm 89:552587b429a1 1661 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
bogdanm 89:552587b429a1 1662
bogdanm 89:552587b429a1 1663 /**
bogdanm 89:552587b429a1 1664 * @brief Disables the specified DMA Rx Desc receive interrupt.
bogdanm 89:552587b429a1 1665 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1666 * @retval None
bogdanm 89:552587b429a1 1667 */
bogdanm 89:552587b429a1 1668 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
bogdanm 89:552587b429a1 1669
bogdanm 89:552587b429a1 1670 /**
bogdanm 89:552587b429a1 1671 * @brief Set the specified DMA Rx Desc Own bit.
bogdanm 89:552587b429a1 1672 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1673 * @retval None
bogdanm 89:552587b429a1 1674 */
bogdanm 89:552587b429a1 1675 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
bogdanm 89:552587b429a1 1676
bogdanm 89:552587b429a1 1677 /**
bogdanm 89:552587b429a1 1678 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
bogdanm 89:552587b429a1 1679 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1680 * @retval The Transmit descriptor collision counter value.
bogdanm 89:552587b429a1 1681 */
bogdanm 89:552587b429a1 1682 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
bogdanm 89:552587b429a1 1683
bogdanm 89:552587b429a1 1684 /**
bogdanm 89:552587b429a1 1685 * @brief Set the specified DMA Tx Desc Own bit.
bogdanm 89:552587b429a1 1686 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1687 * @retval None
bogdanm 89:552587b429a1 1688 */
bogdanm 89:552587b429a1 1689 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
bogdanm 89:552587b429a1 1690
bogdanm 89:552587b429a1 1691 /**
bogdanm 89:552587b429a1 1692 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
bogdanm 89:552587b429a1 1693 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1694 * @retval None
bogdanm 89:552587b429a1 1695 */
bogdanm 89:552587b429a1 1696 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
bogdanm 89:552587b429a1 1697
bogdanm 89:552587b429a1 1698 /**
bogdanm 89:552587b429a1 1699 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
bogdanm 89:552587b429a1 1700 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1701 * @retval None
bogdanm 89:552587b429a1 1702 */
bogdanm 89:552587b429a1 1703 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
bogdanm 89:552587b429a1 1704
bogdanm 89:552587b429a1 1705 /**
bogdanm 89:552587b429a1 1706 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
bogdanm 89:552587b429a1 1707 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1708 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
bogdanm 89:552587b429a1 1709 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1710 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
bogdanm 89:552587b429a1 1711 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
bogdanm 89:552587b429a1 1712 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
bogdanm 89:552587b429a1 1713 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
bogdanm 89:552587b429a1 1714 * @retval None
bogdanm 89:552587b429a1 1715 */
bogdanm 89:552587b429a1 1716 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
bogdanm 89:552587b429a1 1717
bogdanm 89:552587b429a1 1718 /**
bogdanm 89:552587b429a1 1719 * @brief Enables the DMA Tx Desc CRC.
bogdanm 89:552587b429a1 1720 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1721 * @retval None
bogdanm 89:552587b429a1 1722 */
bogdanm 89:552587b429a1 1723 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
bogdanm 89:552587b429a1 1724
bogdanm 89:552587b429a1 1725 /**
bogdanm 89:552587b429a1 1726 * @brief Disables the DMA Tx Desc CRC.
bogdanm 89:552587b429a1 1727 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1728 * @retval None
bogdanm 89:552587b429a1 1729 */
bogdanm 89:552587b429a1 1730 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
bogdanm 89:552587b429a1 1731
bogdanm 89:552587b429a1 1732 /**
bogdanm 89:552587b429a1 1733 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
bogdanm 89:552587b429a1 1734 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1735 * @retval None
bogdanm 89:552587b429a1 1736 */
bogdanm 89:552587b429a1 1737 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
bogdanm 89:552587b429a1 1738
bogdanm 89:552587b429a1 1739 /**
bogdanm 89:552587b429a1 1740 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
bogdanm 89:552587b429a1 1741 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1742 * @retval None
bogdanm 89:552587b429a1 1743 */
bogdanm 89:552587b429a1 1744 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
bogdanm 89:552587b429a1 1745
bogdanm 89:552587b429a1 1746 /**
bogdanm 89:552587b429a1 1747 * @brief Enables the specified ETHERNET MAC interrupts.
bogdanm 89:552587b429a1 1748 * @param __HANDLE__ : ETH Handle
bogdanm 89:552587b429a1 1749 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
bogdanm 89:552587b429a1 1750 * enabled or disabled.
bogdanm 89:552587b429a1 1751 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 1752 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
bogdanm 89:552587b429a1 1753 * @arg ETH_MAC_IT_PMT : PMT interrupt
bogdanm 89:552587b429a1 1754 * @retval None
bogdanm 89:552587b429a1 1755 */
bogdanm 89:552587b429a1 1756 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
bogdanm 89:552587b429a1 1757
bogdanm 89:552587b429a1 1758 /**
bogdanm 89:552587b429a1 1759 * @brief Disables the specified ETHERNET MAC interrupts.
bogdanm 89:552587b429a1 1760 * @param __HANDLE__ : ETH Handle
bogdanm 89:552587b429a1 1761 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
bogdanm 89:552587b429a1 1762 * enabled or disabled.
bogdanm 89:552587b429a1 1763 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 1764 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
bogdanm 89:552587b429a1 1765 * @arg ETH_MAC_IT_PMT : PMT interrupt
bogdanm 89:552587b429a1 1766 * @retval None
bogdanm 89:552587b429a1 1767 */
bogdanm 89:552587b429a1 1768 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
bogdanm 89:552587b429a1 1769
bogdanm 89:552587b429a1 1770 /**
bogdanm 89:552587b429a1 1771 * @brief Initiate a Pause Control Frame (Full-duplex only).
bogdanm 89:552587b429a1 1772 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1773 * @retval None
bogdanm 89:552587b429a1 1774 */
bogdanm 89:552587b429a1 1775 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
bogdanm 89:552587b429a1 1776
bogdanm 89:552587b429a1 1777 /**
bogdanm 89:552587b429a1 1778 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
bogdanm 89:552587b429a1 1779 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1780 * @retval The new state of flow control busy status bit (SET or RESET).
bogdanm 89:552587b429a1 1781 */
bogdanm 89:552587b429a1 1782 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
bogdanm 89:552587b429a1 1783
bogdanm 89:552587b429a1 1784 /**
bogdanm 89:552587b429a1 1785 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
bogdanm 89:552587b429a1 1786 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1787 * @retval None
bogdanm 89:552587b429a1 1788 */
bogdanm 89:552587b429a1 1789 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
bogdanm 89:552587b429a1 1790
bogdanm 89:552587b429a1 1791 /**
bogdanm 89:552587b429a1 1792 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
bogdanm 89:552587b429a1 1793 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1794 * @retval None
bogdanm 89:552587b429a1 1795 */
bogdanm 89:552587b429a1 1796 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
bogdanm 89:552587b429a1 1797
bogdanm 89:552587b429a1 1798 /**
bogdanm 89:552587b429a1 1799 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
bogdanm 89:552587b429a1 1800 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1801 * @param __FLAG__: specifies the flag to check.
bogdanm 89:552587b429a1 1802 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1803 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
bogdanm 89:552587b429a1 1804 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
bogdanm 89:552587b429a1 1805 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
bogdanm 89:552587b429a1 1806 * @arg ETH_MAC_FLAG_MMC : MMC flag
bogdanm 89:552587b429a1 1807 * @arg ETH_MAC_FLAG_PMT : PMT flag
bogdanm 89:552587b429a1 1808 * @retval The state of ETHERNET MAC flag.
bogdanm 89:552587b429a1 1809 */
bogdanm 89:552587b429a1 1810 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
bogdanm 89:552587b429a1 1811
bogdanm 89:552587b429a1 1812 /**
bogdanm 89:552587b429a1 1813 * @brief Enables the specified ETHERNET DMA interrupts.
bogdanm 89:552587b429a1 1814 * @param __HANDLE__ : ETH Handle
bogdanm 89:552587b429a1 1815 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto 99:dbbf35b96557 1816 * enabled @ref ETH_DMA_Interrupts
bogdanm 89:552587b429a1 1817 * @retval None
bogdanm 89:552587b429a1 1818 */
bogdanm 89:552587b429a1 1819 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
bogdanm 89:552587b429a1 1820
bogdanm 89:552587b429a1 1821 /**
bogdanm 89:552587b429a1 1822 * @brief Disables the specified ETHERNET DMA interrupts.
bogdanm 89:552587b429a1 1823 * @param __HANDLE__ : ETH Handle
bogdanm 89:552587b429a1 1824 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto 99:dbbf35b96557 1825 * disabled. @ref ETH_DMA_Interrupts
bogdanm 89:552587b429a1 1826 * @retval None
bogdanm 89:552587b429a1 1827 */
bogdanm 89:552587b429a1 1828 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
bogdanm 89:552587b429a1 1829
bogdanm 89:552587b429a1 1830 /**
bogdanm 89:552587b429a1 1831 * @brief Clears the ETHERNET DMA IT pending bit.
bogdanm 89:552587b429a1 1832 * @param __HANDLE__ : ETH Handle
Kojto 99:dbbf35b96557 1833 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
bogdanm 89:552587b429a1 1834 * @retval None
bogdanm 89:552587b429a1 1835 */
bogdanm 89:552587b429a1 1836 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
bogdanm 89:552587b429a1 1837
bogdanm 89:552587b429a1 1838 /**
bogdanm 89:552587b429a1 1839 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
bogdanm 89:552587b429a1 1840 * @param __HANDLE__: ETH Handle
Kojto 99:dbbf35b96557 1841 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
bogdanm 89:552587b429a1 1842 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
bogdanm 89:552587b429a1 1843 */
bogdanm 89:552587b429a1 1844 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
bogdanm 89:552587b429a1 1845
bogdanm 89:552587b429a1 1846 /**
bogdanm 89:552587b429a1 1847 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
bogdanm 89:552587b429a1 1848 * @param __HANDLE__: ETH Handle
Kojto 99:dbbf35b96557 1849 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
bogdanm 89:552587b429a1 1850 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
bogdanm 89:552587b429a1 1851 */
bogdanm 92:4fc01daae5a5 1852 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
bogdanm 89:552587b429a1 1853
bogdanm 89:552587b429a1 1854 /**
bogdanm 89:552587b429a1 1855 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
bogdanm 89:552587b429a1 1856 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1857 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
bogdanm 89:552587b429a1 1858 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1859 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
bogdanm 89:552587b429a1 1860 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
bogdanm 89:552587b429a1 1861 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
bogdanm 89:552587b429a1 1862 */
bogdanm 89:552587b429a1 1863 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
bogdanm 89:552587b429a1 1864
bogdanm 89:552587b429a1 1865 /**
bogdanm 89:552587b429a1 1866 * @brief Set the DMA Receive status watchdog timer register value
bogdanm 89:552587b429a1 1867 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1868 * @param __VALUE__: DMA Receive status watchdog timer register value
bogdanm 89:552587b429a1 1869 * @retval None
bogdanm 89:552587b429a1 1870 */
bogdanm 89:552587b429a1 1871 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
bogdanm 89:552587b429a1 1872
bogdanm 89:552587b429a1 1873 /**
bogdanm 89:552587b429a1 1874 * @brief Enables any unicast packet filtered by the MAC address
bogdanm 89:552587b429a1 1875 * recognition to be a wake-up frame.
bogdanm 89:552587b429a1 1876 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1877 * @retval None
bogdanm 89:552587b429a1 1878 */
bogdanm 89:552587b429a1 1879 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
bogdanm 89:552587b429a1 1880
bogdanm 89:552587b429a1 1881 /**
bogdanm 89:552587b429a1 1882 * @brief Disables any unicast packet filtered by the MAC address
bogdanm 89:552587b429a1 1883 * recognition to be a wake-up frame.
bogdanm 89:552587b429a1 1884 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1885 * @retval None
bogdanm 89:552587b429a1 1886 */
bogdanm 89:552587b429a1 1887 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
bogdanm 89:552587b429a1 1888
bogdanm 89:552587b429a1 1889 /**
bogdanm 89:552587b429a1 1890 * @brief Enables the MAC Wake-Up Frame Detection.
bogdanm 89:552587b429a1 1891 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1892 * @retval None
bogdanm 89:552587b429a1 1893 */
bogdanm 89:552587b429a1 1894 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
bogdanm 89:552587b429a1 1895
bogdanm 89:552587b429a1 1896 /**
bogdanm 89:552587b429a1 1897 * @brief Disables the MAC Wake-Up Frame Detection.
bogdanm 89:552587b429a1 1898 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1899 * @retval None
bogdanm 89:552587b429a1 1900 */
bogdanm 89:552587b429a1 1901 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
bogdanm 89:552587b429a1 1902
bogdanm 89:552587b429a1 1903 /**
bogdanm 89:552587b429a1 1904 * @brief Enables the MAC Magic Packet Detection.
bogdanm 89:552587b429a1 1905 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1906 * @retval None
bogdanm 89:552587b429a1 1907 */
bogdanm 89:552587b429a1 1908 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
bogdanm 89:552587b429a1 1909
bogdanm 89:552587b429a1 1910 /**
bogdanm 89:552587b429a1 1911 * @brief Disables the MAC Magic Packet Detection.
bogdanm 89:552587b429a1 1912 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1913 * @retval None
bogdanm 89:552587b429a1 1914 */
bogdanm 89:552587b429a1 1915 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
bogdanm 89:552587b429a1 1916
bogdanm 89:552587b429a1 1917 /**
bogdanm 89:552587b429a1 1918 * @brief Enables the MAC Power Down.
bogdanm 89:552587b429a1 1919 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1920 * @retval None
bogdanm 89:552587b429a1 1921 */
bogdanm 89:552587b429a1 1922 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
bogdanm 89:552587b429a1 1923
bogdanm 89:552587b429a1 1924 /**
bogdanm 89:552587b429a1 1925 * @brief Disables the MAC Power Down.
bogdanm 89:552587b429a1 1926 * @param __HANDLE__: ETH Handle
bogdanm 89:552587b429a1 1927 * @retval None
bogdanm 89:552587b429a1 1928 */
bogdanm 89:552587b429a1 1929 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
bogdanm 89:552587b429a1 1930
bogdanm 89:552587b429a1 1931 /**
bogdanm 89:552587b429a1 1932 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
bogdanm 89:552587b429a1 1933 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1934 * @param __FLAG__: specifies the flag to check.
bogdanm 89:552587b429a1 1935 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1936 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
bogdanm 89:552587b429a1 1937 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
bogdanm 89:552587b429a1 1938 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
bogdanm 89:552587b429a1 1939 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
bogdanm 89:552587b429a1 1940 */
bogdanm 89:552587b429a1 1941 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
bogdanm 89:552587b429a1 1942
bogdanm 89:552587b429a1 1943 /**
bogdanm 89:552587b429a1 1944 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
bogdanm 89:552587b429a1 1945 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1946 * @retval None
bogdanm 89:552587b429a1 1947 */
bogdanm 89:552587b429a1 1948 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
bogdanm 89:552587b429a1 1949
bogdanm 89:552587b429a1 1950 /**
bogdanm 89:552587b429a1 1951 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
bogdanm 89:552587b429a1 1952 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1953 * @retval None
bogdanm 89:552587b429a1 1954 */
bogdanm 89:552587b429a1 1955 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
bogdanm 89:552587b429a1 1956 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
bogdanm 89:552587b429a1 1957
bogdanm 89:552587b429a1 1958 /**
bogdanm 89:552587b429a1 1959 * @brief Enables the MMC Counter Freeze.
bogdanm 89:552587b429a1 1960 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1961 * @retval None
bogdanm 89:552587b429a1 1962 */
bogdanm 89:552587b429a1 1963 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
bogdanm 89:552587b429a1 1964
bogdanm 89:552587b429a1 1965 /**
bogdanm 89:552587b429a1 1966 * @brief Disables the MMC Counter Freeze.
bogdanm 89:552587b429a1 1967 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1968 * @retval None
bogdanm 89:552587b429a1 1969 */
bogdanm 89:552587b429a1 1970 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
bogdanm 89:552587b429a1 1971
bogdanm 89:552587b429a1 1972 /**
bogdanm 89:552587b429a1 1973 * @brief Enables the MMC Reset On Read.
bogdanm 89:552587b429a1 1974 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1975 * @retval None
bogdanm 89:552587b429a1 1976 */
bogdanm 89:552587b429a1 1977 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
bogdanm 89:552587b429a1 1978
bogdanm 89:552587b429a1 1979 /**
bogdanm 89:552587b429a1 1980 * @brief Disables the MMC Reset On Read.
bogdanm 89:552587b429a1 1981 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1982 * @retval None
bogdanm 89:552587b429a1 1983 */
bogdanm 89:552587b429a1 1984 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
bogdanm 89:552587b429a1 1985
bogdanm 89:552587b429a1 1986 /**
bogdanm 89:552587b429a1 1987 * @brief Enables the MMC Counter Stop Rollover.
bogdanm 89:552587b429a1 1988 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1989 * @retval None
bogdanm 89:552587b429a1 1990 */
bogdanm 89:552587b429a1 1991 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
bogdanm 89:552587b429a1 1992
bogdanm 89:552587b429a1 1993 /**
bogdanm 89:552587b429a1 1994 * @brief Disables the MMC Counter Stop Rollover.
bogdanm 89:552587b429a1 1995 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 1996 * @retval None
bogdanm 89:552587b429a1 1997 */
bogdanm 89:552587b429a1 1998 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
bogdanm 89:552587b429a1 1999
bogdanm 89:552587b429a1 2000 /**
bogdanm 89:552587b429a1 2001 * @brief Resets the MMC Counters.
bogdanm 89:552587b429a1 2002 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 2003 * @retval None
bogdanm 89:552587b429a1 2004 */
bogdanm 89:552587b429a1 2005 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
bogdanm 89:552587b429a1 2006
bogdanm 89:552587b429a1 2007 /**
bogdanm 89:552587b429a1 2008 * @brief Enables the specified ETHERNET MMC Rx interrupts.
bogdanm 89:552587b429a1 2009 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 2010 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm 89:552587b429a1 2011 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 2012 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
bogdanm 89:552587b429a1 2013 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
bogdanm 89:552587b429a1 2014 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
bogdanm 89:552587b429a1 2015 * @retval None
bogdanm 89:552587b429a1 2016 */
bogdanm 89:552587b429a1 2017 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
bogdanm 89:552587b429a1 2018 /**
bogdanm 89:552587b429a1 2019 * @brief Disables the specified ETHERNET MMC Rx interrupts.
bogdanm 89:552587b429a1 2020 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 2021 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm 89:552587b429a1 2022 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 2023 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
bogdanm 89:552587b429a1 2024 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
bogdanm 89:552587b429a1 2025 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
bogdanm 89:552587b429a1 2026 * @retval None
bogdanm 89:552587b429a1 2027 */
bogdanm 89:552587b429a1 2028 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
bogdanm 89:552587b429a1 2029 /**
bogdanm 89:552587b429a1 2030 * @brief Enables the specified ETHERNET MMC Tx interrupts.
bogdanm 89:552587b429a1 2031 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 2032 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm 89:552587b429a1 2033 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 2034 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
bogdanm 89:552587b429a1 2035 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
bogdanm 89:552587b429a1 2036 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
bogdanm 89:552587b429a1 2037 * @retval None
bogdanm 89:552587b429a1 2038 */
bogdanm 89:552587b429a1 2039 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
bogdanm 89:552587b429a1 2040
bogdanm 89:552587b429a1 2041 /**
bogdanm 89:552587b429a1 2042 * @brief Disables the specified ETHERNET MMC Tx interrupts.
bogdanm 89:552587b429a1 2043 * @param __HANDLE__: ETH Handle.
bogdanm 89:552587b429a1 2044 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm 89:552587b429a1 2045 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 2046 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
bogdanm 89:552587b429a1 2047 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
bogdanm 89:552587b429a1 2048 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
bogdanm 89:552587b429a1 2049 * @retval None
bogdanm 89:552587b429a1 2050 */
Kojto 99:dbbf35b96557 2051 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
Kojto 99:dbbf35b96557 2052
Kojto 99:dbbf35b96557 2053 /**
Kojto 99:dbbf35b96557 2054 * @brief Enables the ETH External interrupt line.
Kojto 99:dbbf35b96557 2055 * @retval None
Kojto 99:dbbf35b96557 2056 */
Kojto 99:dbbf35b96557 2057 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2058
Kojto 99:dbbf35b96557 2059 /**
Kojto 99:dbbf35b96557 2060 * @brief Disables the ETH External interrupt line.
Kojto 99:dbbf35b96557 2061 * @retval None
Kojto 99:dbbf35b96557 2062 */
Kojto 99:dbbf35b96557 2063 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2064
Kojto 99:dbbf35b96557 2065 /**
Kojto 99:dbbf35b96557 2066 * @brief Enable event on ETH External event line.
Kojto 99:dbbf35b96557 2067 * @retval None.
Kojto 99:dbbf35b96557 2068 */
Kojto 99:dbbf35b96557 2069 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2070
Kojto 99:dbbf35b96557 2071 /**
Kojto 99:dbbf35b96557 2072 * @brief Disable event on ETH External event line
Kojto 99:dbbf35b96557 2073 * @retval None.
Kojto 99:dbbf35b96557 2074 */
Kojto 99:dbbf35b96557 2075 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2076
Kojto 99:dbbf35b96557 2077 /**
Kojto 99:dbbf35b96557 2078 * @brief Get flag of the ETH External interrupt line.
Kojto 99:dbbf35b96557 2079 * @retval None
Kojto 99:dbbf35b96557 2080 */
Kojto 99:dbbf35b96557 2081 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2082
Kojto 99:dbbf35b96557 2083 /**
Kojto 99:dbbf35b96557 2084 * @brief Clear flag of the ETH External interrupt line.
Kojto 99:dbbf35b96557 2085 * @retval None
Kojto 99:dbbf35b96557 2086 */
Kojto 99:dbbf35b96557 2087 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
bogdanm 89:552587b429a1 2088
Kojto 99:dbbf35b96557 2089 /**
Kojto 99:dbbf35b96557 2090 * @brief Enables rising edge trigger to the ETH External interrupt line.
Kojto 99:dbbf35b96557 2091 * @retval None
Kojto 99:dbbf35b96557 2092 */
Kojto 99:dbbf35b96557 2093 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
Kojto 99:dbbf35b96557 2094
Kojto 99:dbbf35b96557 2095 /**
Kojto 99:dbbf35b96557 2096 * @brief Disables the rising edge trigger to the ETH External interrupt line.
Kojto 99:dbbf35b96557 2097 * @retval None
Kojto 99:dbbf35b96557 2098 */
Kojto 99:dbbf35b96557 2099 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2100
Kojto 99:dbbf35b96557 2101 /**
Kojto 99:dbbf35b96557 2102 * @brief Enables falling edge trigger to the ETH External interrupt line.
Kojto 99:dbbf35b96557 2103 * @retval None
Kojto 99:dbbf35b96557 2104 */
Kojto 99:dbbf35b96557 2105 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2106
Kojto 99:dbbf35b96557 2107 /**
Kojto 99:dbbf35b96557 2108 * @brief Disables falling edge trigger to the ETH External interrupt line.
Kojto 99:dbbf35b96557 2109 * @retval None
Kojto 99:dbbf35b96557 2110 */
Kojto 99:dbbf35b96557 2111 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2112
Kojto 99:dbbf35b96557 2113 /**
Kojto 99:dbbf35b96557 2114 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
Kojto 99:dbbf35b96557 2115 * @retval None
Kojto 99:dbbf35b96557 2116 */
Kojto 99:dbbf35b96557 2117 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
Kojto 99:dbbf35b96557 2118 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
Kojto 99:dbbf35b96557 2119
Kojto 99:dbbf35b96557 2120 /**
Kojto 99:dbbf35b96557 2121 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
Kojto 99:dbbf35b96557 2122 * @retval None
Kojto 99:dbbf35b96557 2123 */
Kojto 99:dbbf35b96557 2124 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
Kojto 99:dbbf35b96557 2125 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2126
Kojto 99:dbbf35b96557 2127 /**
Kojto 99:dbbf35b96557 2128 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 99:dbbf35b96557 2129 * @retval None.
Kojto 99:dbbf35b96557 2130 */
Kojto 99:dbbf35b96557 2131 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
bogdanm 89:552587b429a1 2132
bogdanm 92:4fc01daae5a5 2133 /**
bogdanm 92:4fc01daae5a5 2134 * @}
bogdanm 92:4fc01daae5a5 2135 */
bogdanm 89:552587b429a1 2136 /* Exported functions --------------------------------------------------------*/
bogdanm 89:552587b429a1 2137
Kojto 99:dbbf35b96557 2138 /** @addtogroup ETH_Exported_Functions
Kojto 99:dbbf35b96557 2139 * @{
Kojto 99:dbbf35b96557 2140 */
Kojto 99:dbbf35b96557 2141
bogdanm 89:552587b429a1 2142 /* Initialization and de-initialization functions ****************************/
Kojto 99:dbbf35b96557 2143
Kojto 99:dbbf35b96557 2144 /** @addtogroup ETH_Exported_Functions_Group1
Kojto 99:dbbf35b96557 2145 * @{
Kojto 99:dbbf35b96557 2146 */
bogdanm 89:552587b429a1 2147 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
bogdanm 89:552587b429a1 2148 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
bogdanm 89:552587b429a1 2149 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
bogdanm 89:552587b429a1 2150 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
bogdanm 89:552587b429a1 2151 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
bogdanm 89:552587b429a1 2152 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
bogdanm 89:552587b429a1 2153
Kojto 99:dbbf35b96557 2154 /**
Kojto 99:dbbf35b96557 2155 * @}
Kojto 99:dbbf35b96557 2156 */
bogdanm 89:552587b429a1 2157 /* IO operation functions ****************************************************/
Kojto 99:dbbf35b96557 2158
Kojto 99:dbbf35b96557 2159 /** @addtogroup ETH_Exported_Functions_Group2
Kojto 99:dbbf35b96557 2160 * @{
Kojto 99:dbbf35b96557 2161 */
bogdanm 89:552587b429a1 2162 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
bogdanm 89:552587b429a1 2163 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
Kojto 99:dbbf35b96557 2164 /* Communication with PHY functions*/
Kojto 99:dbbf35b96557 2165 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
Kojto 99:dbbf35b96557 2166 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
Kojto 99:dbbf35b96557 2167 /* Non-Blocking mode: Interrupt */
bogdanm 89:552587b429a1 2168 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
bogdanm 89:552587b429a1 2169 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
Kojto 99:dbbf35b96557 2170 /* Callback in non blocking modes (Interrupt) */
bogdanm 89:552587b429a1 2171 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
bogdanm 89:552587b429a1 2172 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
bogdanm 89:552587b429a1 2173 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
Kojto 99:dbbf35b96557 2174 /**
Kojto 99:dbbf35b96557 2175 * @}
Kojto 99:dbbf35b96557 2176 */
bogdanm 89:552587b429a1 2177
bogdanm 89:552587b429a1 2178 /* Peripheral Control functions **********************************************/
Kojto 99:dbbf35b96557 2179
Kojto 99:dbbf35b96557 2180 /** @addtogroup ETH_Exported_Functions_Group3
Kojto 99:dbbf35b96557 2181 * @{
Kojto 99:dbbf35b96557 2182 */
Kojto 99:dbbf35b96557 2183
bogdanm 89:552587b429a1 2184 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
bogdanm 89:552587b429a1 2185 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
bogdanm 89:552587b429a1 2186 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
bogdanm 89:552587b429a1 2187 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
bogdanm 89:552587b429a1 2188 /**
bogdanm 89:552587b429a1 2189 * @}
bogdanm 89:552587b429a1 2190 */
bogdanm 89:552587b429a1 2191
Kojto 99:dbbf35b96557 2192 /* Peripheral State functions ************************************************/
Kojto 99:dbbf35b96557 2193
Kojto 99:dbbf35b96557 2194 /** @addtogroup ETH_Exported_Functions_Group4
Kojto 99:dbbf35b96557 2195 * @{
Kojto 99:dbbf35b96557 2196 */
Kojto 99:dbbf35b96557 2197 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
Kojto 99:dbbf35b96557 2198 /**
Kojto 99:dbbf35b96557 2199 * @}
Kojto 99:dbbf35b96557 2200 */
Kojto 99:dbbf35b96557 2201
bogdanm 89:552587b429a1 2202 /**
bogdanm 89:552587b429a1 2203 * @}
Kojto 99:dbbf35b96557 2204 */
Kojto 99:dbbf35b96557 2205
Kojto 99:dbbf35b96557 2206 /**
Kojto 99:dbbf35b96557 2207 * @}
Kojto 99:dbbf35b96557 2208 */
Kojto 99:dbbf35b96557 2209
Kojto 99:dbbf35b96557 2210 /**
Kojto 99:dbbf35b96557 2211 * @}
Kojto 99:dbbf35b96557 2212 */
Kojto 99:dbbf35b96557 2213
Kojto 99:dbbf35b96557 2214 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 2215
bogdanm 89:552587b429a1 2216 #ifdef __cplusplus
bogdanm 89:552587b429a1 2217 }
bogdanm 89:552587b429a1 2218 #endif
bogdanm 89:552587b429a1 2219
bogdanm 89:552587b429a1 2220 #endif /* __STM32F4xx_HAL_ETH_H */
bogdanm 89:552587b429a1 2221
bogdanm 89:552587b429a1 2222
bogdanm 89:552587b429a1 2223 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/