Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_ARM_MPS2_M0/SMM_MPS2.h@102:da0ca467f8b5, 2015-07-08 (annotated)

Committer:
Kojto
Date:
Wed Jul 08 11:22:30 2015 +0100
Revision:
102:da0ca467f8b5
Child:
116:c0f6e94411f5
Release 102 of the mbed library



Changes:

- new platform: MPS2

- K64f - mac address fix

- Freescale Kinetis - Serial NC handling fix

- Asynch constnes fixes

- startup files .s - change extension to .S

- APPNEARME_MICRONFCBOARD rename to MICRONFCBOARD

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 102:da0ca467f8b5 1 /* MPS2 CMSIS Library
Kojto 102:da0ca467f8b5 2 *
Kojto 102:da0ca467f8b5 3 * Copyright (c) 2006-2015 ARM Limited
Kojto 102:da0ca467f8b5 4 * All rights reserved.
Kojto 102:da0ca467f8b5 5 *
Kojto 102:da0ca467f8b5 6 * Redistribution and use in source and binary forms, with or without
Kojto 102:da0ca467f8b5 7 * modification, are permitted provided that the following conditions are met:
Kojto 102:da0ca467f8b5 8 *
Kojto 102:da0ca467f8b5 9 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 102:da0ca467f8b5 10 * this list of conditions and the following disclaimer.
Kojto 102:da0ca467f8b5 11 *
Kojto 102:da0ca467f8b5 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 102:da0ca467f8b5 13 * this list of conditions and the following disclaimer in the documentation
Kojto 102:da0ca467f8b5 14 * and/or other materials provided with the distribution.
Kojto 102:da0ca467f8b5 15 *
Kojto 102:da0ca467f8b5 16 * 3. Neither the name of the copyright holder nor the names of its contributors
Kojto 102:da0ca467f8b5 17 * may be used to endorse or promote products derived from this software without
Kojto 102:da0ca467f8b5 18 * specific prior written permission.
Kojto 102:da0ca467f8b5 19 *
Kojto 102:da0ca467f8b5 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 102:da0ca467f8b5 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 102:da0ca467f8b5 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 102:da0ca467f8b5 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
Kojto 102:da0ca467f8b5 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 102:da0ca467f8b5 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 102:da0ca467f8b5 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 102:da0ca467f8b5 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 102:da0ca467f8b5 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 102:da0ca467f8b5 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 102:da0ca467f8b5 30 * POSSIBILITY OF SUCH DAMAGE.
Kojto 102:da0ca467f8b5 31 *******************************************************************************
Kojto 102:da0ca467f8b5 32 * File: smm_mps2.h
Kojto 102:da0ca467f8b5 33 * Release: Version 1.0
Kojto 102:da0ca467f8b5 34 *******************************************************************************/
Kojto 102:da0ca467f8b5 35
Kojto 102:da0ca467f8b5 36 #ifndef __SMM_MPS2_H
Kojto 102:da0ca467f8b5 37 #define __SMM_MPS2_H
Kojto 102:da0ca467f8b5 38
Kojto 102:da0ca467f8b5 39 #include "peripherallink.h" /* device specific header file */
Kojto 102:da0ca467f8b5 40
Kojto 102:da0ca467f8b5 41 #if defined ( __CC_ARM )
Kojto 102:da0ca467f8b5 42 #pragma anon_unions
Kojto 102:da0ca467f8b5 43 #endif
Kojto 102:da0ca467f8b5 44
Kojto 102:da0ca467f8b5 45 /******************************************************************************/
Kojto 102:da0ca467f8b5 46 /* FPGA System Register declaration */
Kojto 102:da0ca467f8b5 47 /******************************************************************************/
Kojto 102:da0ca467f8b5 48
Kojto 102:da0ca467f8b5 49 typedef struct
Kojto 102:da0ca467f8b5 50 {
Kojto 102:da0ca467f8b5 51 __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
Kojto 102:da0ca467f8b5 52 // [31:2] : Reserved
Kojto 102:da0ca467f8b5 53 // [1:0] : LEDs
Kojto 102:da0ca467f8b5 54 uint32_t RESERVED1[1];
Kojto 102:da0ca467f8b5 55 __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
Kojto 102:da0ca467f8b5 56 // [31:2] : Reserved
Kojto 102:da0ca467f8b5 57 // [1:0] : Buttons
Kojto 102:da0ca467f8b5 58 uint32_t RESERVED2[1];
Kojto 102:da0ca467f8b5 59 __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
Kojto 102:da0ca467f8b5 60 __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
Kojto 102:da0ca467f8b5 61 __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
Kojto 102:da0ca467f8b5 62 // Increments when 32-bit prescale counter reach zero
Kojto 102:da0ca467f8b5 63 uint32_t RESERVED3[1];
Kojto 102:da0ca467f8b5 64 __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
Kojto 102:da0ca467f8b5 65 // Bit[31:0] : reload value for prescale counter
Kojto 102:da0ca467f8b5 66 __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
Kojto 102:da0ca467f8b5 67 // current value of the pre-scaler counter
Kojto 102:da0ca467f8b5 68 // The Cycle Up Counter increment when the prescale down counter reach 0
Kojto 102:da0ca467f8b5 69 // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
Kojto 102:da0ca467f8b5 70 uint32_t RESERVED4[9];
Kojto 102:da0ca467f8b5 71 __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
Kojto 102:da0ca467f8b5 72 // [31:7] : Reserved
Kojto 102:da0ca467f8b5 73 // [6] : CLCD_BL_CTRL
Kojto 102:da0ca467f8b5 74 // [5] : CLCD_RD
Kojto 102:da0ca467f8b5 75 // [4] : CLCD_RS
Kojto 102:da0ca467f8b5 76 // [3] : CLCD_RESET
Kojto 102:da0ca467f8b5 77 // [2] : RESERVED
Kojto 102:da0ca467f8b5 78 // [1] : SPI_nSS
Kojto 102:da0ca467f8b5 79 // [0] : CLCD_CS
Kojto 102:da0ca467f8b5 80 } MPS2_FPGAIO_TypeDef;
Kojto 102:da0ca467f8b5 81
Kojto 102:da0ca467f8b5 82 // MISC register bit definitions
Kojto 102:da0ca467f8b5 83
Kojto 102:da0ca467f8b5 84 #define CLCD_CS_Pos 0
Kojto 102:da0ca467f8b5 85 #define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
Kojto 102:da0ca467f8b5 86 #define SPI_nSS_Pos 1
Kojto 102:da0ca467f8b5 87 #define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
Kojto 102:da0ca467f8b5 88 #define CLCD_RESET_Pos 3
Kojto 102:da0ca467f8b5 89 #define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
Kojto 102:da0ca467f8b5 90 #define CLCD_RS_Pos 4
Kojto 102:da0ca467f8b5 91 #define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
Kojto 102:da0ca467f8b5 92 #define CLCD_RD_Pos 5
Kojto 102:da0ca467f8b5 93 #define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
Kojto 102:da0ca467f8b5 94 #define CLCD_BL_Pos 6
Kojto 102:da0ca467f8b5 95 #define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
Kojto 102:da0ca467f8b5 96
Kojto 102:da0ca467f8b5 97 /******************************************************************************/
Kojto 102:da0ca467f8b5 98 /* SCC Register declaration */
Kojto 102:da0ca467f8b5 99 /******************************************************************************/
Kojto 102:da0ca467f8b5 100
Kojto 102:da0ca467f8b5 101 typedef struct //
Kojto 102:da0ca467f8b5 102 {
Kojto 102:da0ca467f8b5 103 __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
Kojto 102:da0ca467f8b5 104 // [31:1] : Reserved
Kojto 102:da0ca467f8b5 105 // [0] 1 : REMAP BlockRam to ZBT
Kojto 102:da0ca467f8b5 106 __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
Kojto 102:da0ca467f8b5 107 // [31:8] : Reserved
Kojto 102:da0ca467f8b5 108 // [7:0] : MCC LEDs
Kojto 102:da0ca467f8b5 109 uint32_t RESERVED0[1];
Kojto 102:da0ca467f8b5 110 __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
Kojto 102:da0ca467f8b5 111 // [31:8] : Reserved
Kojto 102:da0ca467f8b5 112 // [7:0] : These bits indicate state of the MCC switches
Kojto 102:da0ca467f8b5 113 __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
Kojto 102:da0ca467f8b5 114 // [31:4] : Reserved
Kojto 102:da0ca467f8b5 115 // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
Kojto 102:da0ca467f8b5 116 uint32_t RESERVED1[35];
Kojto 102:da0ca467f8b5 117 __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
Kojto 102:da0ca467f8b5 118 // [31:0] : Data
Kojto 102:da0ca467f8b5 119 __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
Kojto 102:da0ca467f8b5 120 // [31:0] : Data
Kojto 102:da0ca467f8b5 121 __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
Kojto 102:da0ca467f8b5 122 // [31] : Start (generates interrupt on write to this bit)
Kojto 102:da0ca467f8b5 123 // [30] : R/W access
Kojto 102:da0ca467f8b5 124 // [29:26] : Reserved
Kojto 102:da0ca467f8b5 125 // [25:20] : Function value
Kojto 102:da0ca467f8b5 126 // [19:12] : Reserved
Kojto 102:da0ca467f8b5 127 // [11:0] : Device (value of 0/1/2 for supported clocks)
Kojto 102:da0ca467f8b5 128 __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
Kojto 102:da0ca467f8b5 129 // [31:2] : Reserved
Kojto 102:da0ca467f8b5 130 // [1] : Error
Kojto 102:da0ca467f8b5 131 // [0] : Complete
Kojto 102:da0ca467f8b5 132 __IO uint32_t RESERVED2[20];
Kojto 102:da0ca467f8b5 133 __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
Kojto 102:da0ca467f8b5 134 // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
Kojto 102:da0ca467f8b5 135 // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
Kojto 102:da0ca467f8b5 136 // [15:1] : Reserved
Kojto 102:da0ca467f8b5 137 // [0] : This bit indicates if all enabled DLLs are locked
Kojto 102:da0ca467f8b5 138 uint32_t RESERVED3[957];
Kojto 102:da0ca467f8b5 139 __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
Kojto 102:da0ca467f8b5 140 // [31:24] : FPGA build number
Kojto 102:da0ca467f8b5 141 // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
Kojto 102:da0ca467f8b5 142 // [19:11] : Reserved
Kojto 102:da0ca467f8b5 143 // [10] : if “1” SCC_SW register has been implemented
Kojto 102:da0ca467f8b5 144 // [9] : if “1” SCC_LED register has been implemented
Kojto 102:da0ca467f8b5 145 // [8] : if “1” DLL lock register has been implemented
Kojto 102:da0ca467f8b5 146 // [7:0] : number of SCC configuration register
Kojto 102:da0ca467f8b5 147 __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
Kojto 102:da0ca467f8b5 148 // [31:24] : Implementer ID: 0x41 = ARM
Kojto 102:da0ca467f8b5 149 // [23:20] : Application note IP variant number
Kojto 102:da0ca467f8b5 150 // [19:16] : IP Architecture: 0x4 =AHB
Kojto 102:da0ca467f8b5 151 // [15:4] : Primary part number: 386 = AN386
Kojto 102:da0ca467f8b5 152 // [3:0] : Application note IP revision number
Kojto 102:da0ca467f8b5 153 } MPS2_SCC_TypeDef;
Kojto 102:da0ca467f8b5 154
Kojto 102:da0ca467f8b5 155
Kojto 102:da0ca467f8b5 156 /******************************************************************************/
Kojto 102:da0ca467f8b5 157 /* SSP Peripheral declaration */
Kojto 102:da0ca467f8b5 158 /******************************************************************************/
Kojto 102:da0ca467f8b5 159
Kojto 102:da0ca467f8b5 160 typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
Kojto 102:da0ca467f8b5 161 {
Kojto 102:da0ca467f8b5 162 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
Kojto 102:da0ca467f8b5 163 // [31:16] : Reserved
Kojto 102:da0ca467f8b5 164 // [15:8] : Serial clock rate
Kojto 102:da0ca467f8b5 165 // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
Kojto 102:da0ca467f8b5 166 // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
Kojto 102:da0ca467f8b5 167 // [5:4] : Frame format
Kojto 102:da0ca467f8b5 168 // [3:0] : Data Size Select
Kojto 102:da0ca467f8b5 169 __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
Kojto 102:da0ca467f8b5 170 // [31:4] : Reserved
Kojto 102:da0ca467f8b5 171 // [3] : Slave-mode output disable
Kojto 102:da0ca467f8b5 172 // [2] : Master or slave mode select
Kojto 102:da0ca467f8b5 173 // [1] : Synchronous serial port enable
Kojto 102:da0ca467f8b5 174 // [0] : Loop back mode
Kojto 102:da0ca467f8b5 175 __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
Kojto 102:da0ca467f8b5 176 // [31:16] : Reserved
Kojto 102:da0ca467f8b5 177 // [15:0] : Transmit/Receive FIFO
Kojto 102:da0ca467f8b5 178 __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
Kojto 102:da0ca467f8b5 179 // [31:5] : Reserved
Kojto 102:da0ca467f8b5 180 // [4] : PrimeCell SSP busy flag
Kojto 102:da0ca467f8b5 181 // [3] : Receive FIFO full
Kojto 102:da0ca467f8b5 182 // [2] : Receive FIFO not empty
Kojto 102:da0ca467f8b5 183 // [1] : Transmit FIFO not full
Kojto 102:da0ca467f8b5 184 // [0] : Transmit FIFO empty
Kojto 102:da0ca467f8b5 185 __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
Kojto 102:da0ca467f8b5 186 // [31:8] : Reserved
Kojto 102:da0ca467f8b5 187 // [8:0] : Clock prescale divisor
Kojto 102:da0ca467f8b5 188 __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
Kojto 102:da0ca467f8b5 189 // [31:4] : Reserved
Kojto 102:da0ca467f8b5 190 // [3] : Transmit FIFO interrupt mask
Kojto 102:da0ca467f8b5 191 // [2] : Receive FIFO interrupt mask
Kojto 102:da0ca467f8b5 192 // [1] : Receive timeout interrupt mask
Kojto 102:da0ca467f8b5 193 // [0] : Receive overrun interrupt mask
Kojto 102:da0ca467f8b5 194 __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
Kojto 102:da0ca467f8b5 195 // [31:4] : Reserved
Kojto 102:da0ca467f8b5 196 // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
Kojto 102:da0ca467f8b5 197 // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
Kojto 102:da0ca467f8b5 198 // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
Kojto 102:da0ca467f8b5 199 // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
Kojto 102:da0ca467f8b5 200 __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
Kojto 102:da0ca467f8b5 201 // [31:4] : Reserved
Kojto 102:da0ca467f8b5 202 // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
Kojto 102:da0ca467f8b5 203 // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
Kojto 102:da0ca467f8b5 204 // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
Kojto 102:da0ca467f8b5 205 // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
Kojto 102:da0ca467f8b5 206 __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
Kojto 102:da0ca467f8b5 207 // [31:2] : Reserved
Kojto 102:da0ca467f8b5 208 // [1] : Clears the SSPRTINTR interrupt
Kojto 102:da0ca467f8b5 209 // [0] : Clears the SSPRORINTR interrupt
Kojto 102:da0ca467f8b5 210 __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
Kojto 102:da0ca467f8b5 211 // [31:2] : Reserved
Kojto 102:da0ca467f8b5 212 // [1] : Transmit DMA Enable
Kojto 102:da0ca467f8b5 213 // [0] : Receive DMA Enable
Kojto 102:da0ca467f8b5 214 } MPS2_SSP_TypeDef;
Kojto 102:da0ca467f8b5 215
Kojto 102:da0ca467f8b5 216
Kojto 102:da0ca467f8b5 217 // SSP_CR0 Control register 0
Kojto 102:da0ca467f8b5 218 #define SSP_CR0_DSS_Pos 0 // Data Size Select
Kojto 102:da0ca467f8b5 219 #define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
Kojto 102:da0ca467f8b5 220 #define SSP_CR0_FRF_Pos 4 // Frame Format Select
Kojto 102:da0ca467f8b5 221 #define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
Kojto 102:da0ca467f8b5 222 #define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
Kojto 102:da0ca467f8b5 223 #define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
Kojto 102:da0ca467f8b5 224 #define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
Kojto 102:da0ca467f8b5 225 #define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
Kojto 102:da0ca467f8b5 226 #define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
Kojto 102:da0ca467f8b5 227 #define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
Kojto 102:da0ca467f8b5 228
Kojto 102:da0ca467f8b5 229 #define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
Kojto 102:da0ca467f8b5 230 #define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
Kojto 102:da0ca467f8b5 231 #define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
Kojto 102:da0ca467f8b5 232 #define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
Kojto 102:da0ca467f8b5 233
Kojto 102:da0ca467f8b5 234 // SSP_CR1 Control register 1
Kojto 102:da0ca467f8b5 235 #define SSP_CR1_LBM_Pos 0 // Loop Back Mode
Kojto 102:da0ca467f8b5 236 #define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
Kojto 102:da0ca467f8b5 237 #define SSP_CR1_SSE_Pos 1 // Serial port enable
Kojto 102:da0ca467f8b5 238 #define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
Kojto 102:da0ca467f8b5 239 #define SSP_CR1_MS_Pos 2 // Master or Slave mode
Kojto 102:da0ca467f8b5 240 #define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
Kojto 102:da0ca467f8b5 241 #define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
Kojto 102:da0ca467f8b5 242 #define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
Kojto 102:da0ca467f8b5 243
Kojto 102:da0ca467f8b5 244 // SSP_SR Status register
Kojto 102:da0ca467f8b5 245 #define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
Kojto 102:da0ca467f8b5 246 #define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
Kojto 102:da0ca467f8b5 247 #define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
Kojto 102:da0ca467f8b5 248 #define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
Kojto 102:da0ca467f8b5 249 #define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
Kojto 102:da0ca467f8b5 250 #define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
Kojto 102:da0ca467f8b5 251 #define SSP_SR_RFF_Pos 3 // Receive FIFO full
Kojto 102:da0ca467f8b5 252 #define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
Kojto 102:da0ca467f8b5 253 #define SSP_SR_BSY_Pos 4 // Busy
Kojto 102:da0ca467f8b5 254 #define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
Kojto 102:da0ca467f8b5 255
Kojto 102:da0ca467f8b5 256 // SSP_CPSR Clock prescale register
Kojto 102:da0ca467f8b5 257 #define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
Kojto 102:da0ca467f8b5 258 #define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
Kojto 102:da0ca467f8b5 259
Kojto 102:da0ca467f8b5 260 #define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
Kojto 102:da0ca467f8b5 261
Kojto 102:da0ca467f8b5 262 // SSPIMSC Interrupt mask set and clear register
Kojto 102:da0ca467f8b5 263 #define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
Kojto 102:da0ca467f8b5 264 #define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
Kojto 102:da0ca467f8b5 265 #define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
Kojto 102:da0ca467f8b5 266 #define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
Kojto 102:da0ca467f8b5 267 #define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
Kojto 102:da0ca467f8b5 268 #define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
Kojto 102:da0ca467f8b5 269 #define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
Kojto 102:da0ca467f8b5 270 #define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
Kojto 102:da0ca467f8b5 271
Kojto 102:da0ca467f8b5 272 // SSPRIS Raw interrupt status register
Kojto 102:da0ca467f8b5 273 #define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
Kojto 102:da0ca467f8b5 274 #define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
Kojto 102:da0ca467f8b5 275 #define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
Kojto 102:da0ca467f8b5 276 #define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
Kojto 102:da0ca467f8b5 277 #define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
Kojto 102:da0ca467f8b5 278 #define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
Kojto 102:da0ca467f8b5 279 #define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
Kojto 102:da0ca467f8b5 280 #define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
Kojto 102:da0ca467f8b5 281
Kojto 102:da0ca467f8b5 282 // SSPMIS Masked interrupt status register
Kojto 102:da0ca467f8b5 283 #define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
Kojto 102:da0ca467f8b5 284 #define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
Kojto 102:da0ca467f8b5 285 #define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
Kojto 102:da0ca467f8b5 286 #define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
Kojto 102:da0ca467f8b5 287 #define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
Kojto 102:da0ca467f8b5 288 #define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
Kojto 102:da0ca467f8b5 289 #define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
Kojto 102:da0ca467f8b5 290 #define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
Kojto 102:da0ca467f8b5 291
Kojto 102:da0ca467f8b5 292 // SSPICR Interrupt clear register
Kojto 102:da0ca467f8b5 293 #define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
Kojto 102:da0ca467f8b5 294 #define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
Kojto 102:da0ca467f8b5 295 #define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
Kojto 102:da0ca467f8b5 296 #define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
Kojto 102:da0ca467f8b5 297
Kojto 102:da0ca467f8b5 298 // SSPDMACR DMA control register
Kojto 102:da0ca467f8b5 299 #define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
Kojto 102:da0ca467f8b5 300 #define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
Kojto 102:da0ca467f8b5 301 #define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
Kojto 102:da0ca467f8b5 302 #define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
Kojto 102:da0ca467f8b5 303
Kojto 102:da0ca467f8b5 304 /******************************************************************************/
Kojto 102:da0ca467f8b5 305 /* Audio and Touch Screen (I2C) Peripheral declaration */
Kojto 102:da0ca467f8b5 306 /******************************************************************************/
Kojto 102:da0ca467f8b5 307
Kojto 102:da0ca467f8b5 308 typedef struct
Kojto 102:da0ca467f8b5 309 {
Kojto 102:da0ca467f8b5 310 union {
Kojto 102:da0ca467f8b5 311 __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
Kojto 102:da0ca467f8b5 312 __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
Kojto 102:da0ca467f8b5 313 };
Kojto 102:da0ca467f8b5 314 __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
Kojto 102:da0ca467f8b5 315 } MPS2_I2C_TypeDef;
Kojto 102:da0ca467f8b5 316
Kojto 102:da0ca467f8b5 317 #define SDA 1 << 1
Kojto 102:da0ca467f8b5 318 #define SCL 1 << 0
Kojto 102:da0ca467f8b5 319
Kojto 102:da0ca467f8b5 320
Kojto 102:da0ca467f8b5 321 /******************************************************************************/
Kojto 102:da0ca467f8b5 322 /* Audio I2S Peripheral declaration */
Kojto 102:da0ca467f8b5 323 /******************************************************************************/
Kojto 102:da0ca467f8b5 324
Kojto 102:da0ca467f8b5 325 typedef struct
Kojto 102:da0ca467f8b5 326 {
Kojto 102:da0ca467f8b5 327 /*!< Offset: 0x000 CONTROL Register (R/W) */
Kojto 102:da0ca467f8b5 328 __IO uint32_t CONTROL; // <h> CONTROL </h>
Kojto 102:da0ca467f8b5 329 // <o.0> TX Enable
Kojto 102:da0ca467f8b5 330 // <0=> TX disabled
Kojto 102:da0ca467f8b5 331 // <1=> TX enabled
Kojto 102:da0ca467f8b5 332 // <o.1> TX IRQ Enable
Kojto 102:da0ca467f8b5 333 // <0=> TX IRQ disabled
Kojto 102:da0ca467f8b5 334 // <1=> TX IRQ enabled
Kojto 102:da0ca467f8b5 335 // <o.2> RX Enable
Kojto 102:da0ca467f8b5 336 // <0=> RX disabled
Kojto 102:da0ca467f8b5 337 // <1=> RX enabled
Kojto 102:da0ca467f8b5 338 // <o.3> RX IRQ Enable
Kojto 102:da0ca467f8b5 339 // <0=> RX IRQ disabled
Kojto 102:da0ca467f8b5 340 // <1=> RX IRQ enabled
Kojto 102:da0ca467f8b5 341 // <o.10..8> TX Buffer Water Level
Kojto 102:da0ca467f8b5 342 // <0=> / IRQ triggers when any space available
Kojto 102:da0ca467f8b5 343 // <1=> / IRQ triggers when more than 1 space available
Kojto 102:da0ca467f8b5 344 // <2=> / IRQ triggers when more than 2 space available
Kojto 102:da0ca467f8b5 345 // <3=> / IRQ triggers when more than 3 space available
Kojto 102:da0ca467f8b5 346 // <4=> Undefined!
Kojto 102:da0ca467f8b5 347 // <5=> Undefined!
Kojto 102:da0ca467f8b5 348 // <6=> Undefined!
Kojto 102:da0ca467f8b5 349 // <7=> Undefined!
Kojto 102:da0ca467f8b5 350 // <o.14..12> RX Buffer Water Level
Kojto 102:da0ca467f8b5 351 // <0=> Undefined!
Kojto 102:da0ca467f8b5 352 // <1=> / IRQ triggers when less than 1 space available
Kojto 102:da0ca467f8b5 353 // <2=> / IRQ triggers when less than 2 space available
Kojto 102:da0ca467f8b5 354 // <3=> / IRQ triggers when less than 3 space available
Kojto 102:da0ca467f8b5 355 // <4=> / IRQ triggers when less than 4 space available
Kojto 102:da0ca467f8b5 356 // <5=> Undefined!
Kojto 102:da0ca467f8b5 357 // <6=> Undefined!
Kojto 102:da0ca467f8b5 358 // <7=> Undefined!
Kojto 102:da0ca467f8b5 359 // <o.16> FIFO reset
Kojto 102:da0ca467f8b5 360 // <0=> Normal operation
Kojto 102:da0ca467f8b5 361 // <1=> FIFO reset
Kojto 102:da0ca467f8b5 362 // <o.17> Audio Codec reset
Kojto 102:da0ca467f8b5 363 // <0=> Normal operation
Kojto 102:da0ca467f8b5 364 // <1=> Assert audio Codec reset
Kojto 102:da0ca467f8b5 365 /*!< Offset: 0x004 STATUS Register (R/ ) */
Kojto 102:da0ca467f8b5 366 __I uint32_t STATUS; // <h> STATUS </h>
Kojto 102:da0ca467f8b5 367 // <o.0> TX Buffer alert
Kojto 102:da0ca467f8b5 368 // <0=> TX buffer don't need service yet
Kojto 102:da0ca467f8b5 369 // <1=> TX buffer need service
Kojto 102:da0ca467f8b5 370 // <o.1> RX Buffer alert
Kojto 102:da0ca467f8b5 371 // <0=> RX buffer don't need service yet
Kojto 102:da0ca467f8b5 372 // <1=> RX buffer need service
Kojto 102:da0ca467f8b5 373 // <o.2> TX Buffer Empty
Kojto 102:da0ca467f8b5 374 // <0=> TX buffer have data
Kojto 102:da0ca467f8b5 375 // <1=> TX buffer empty
Kojto 102:da0ca467f8b5 376 // <o.3> TX Buffer Full
Kojto 102:da0ca467f8b5 377 // <0=> TX buffer not full
Kojto 102:da0ca467f8b5 378 // <1=> TX buffer full
Kojto 102:da0ca467f8b5 379 // <o.4> RX Buffer Empty
Kojto 102:da0ca467f8b5 380 // <0=> RX buffer have data
Kojto 102:da0ca467f8b5 381 // <1=> RX buffer empty
Kojto 102:da0ca467f8b5 382 // <o.5> RX Buffer Full
Kojto 102:da0ca467f8b5 383 // <0=> RX buffer not full
Kojto 102:da0ca467f8b5 384 // <1=> RX buffer full
Kojto 102:da0ca467f8b5 385 union {
Kojto 102:da0ca467f8b5 386 /*!< Offset: 0x008 Error Status Register (R/ ) */
Kojto 102:da0ca467f8b5 387 __I uint32_t ERROR; // <h> ERROR </h>
Kojto 102:da0ca467f8b5 388 // <o.0> TX error
Kojto 102:da0ca467f8b5 389 // <0=> Okay
Kojto 102:da0ca467f8b5 390 // <1=> TX overrun/underrun
Kojto 102:da0ca467f8b5 391 // <o.1> RX error
Kojto 102:da0ca467f8b5 392 // <0=> Okay
Kojto 102:da0ca467f8b5 393 // <1=> RX overrun/underrun
Kojto 102:da0ca467f8b5 394 /*!< Offset: 0x008 Error Clear Register ( /W) */
Kojto 102:da0ca467f8b5 395 __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
Kojto 102:da0ca467f8b5 396 // <o.0> TX error
Kojto 102:da0ca467f8b5 397 // <0=> Okay
Kojto 102:da0ca467f8b5 398 // <1=> Clear TX error
Kojto 102:da0ca467f8b5 399 // <o.1> RX error
Kojto 102:da0ca467f8b5 400 // <0=> Okay
Kojto 102:da0ca467f8b5 401 // <1=> Clear RX error
Kojto 102:da0ca467f8b5 402 };
Kojto 102:da0ca467f8b5 403 /*!< Offset: 0x00C Divide ratio Register (R/W) */
Kojto 102:da0ca467f8b5 404 __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
Kojto 102:da0ca467f8b5 405 // <o.9..0> TX error (default 0x80)
Kojto 102:da0ca467f8b5 406 /*!< Offset: 0x010 Transmit Buffer ( /W) */
Kojto 102:da0ca467f8b5 407 __O uint32_t TXBUF; // <h> Transmit buffer </h>
Kojto 102:da0ca467f8b5 408 // <o.15..0> Right channel
Kojto 102:da0ca467f8b5 409 // <o.31..16> Left channel
Kojto 102:da0ca467f8b5 410 /*!< Offset: 0x014 Receive Buffer (R/ ) */
Kojto 102:da0ca467f8b5 411 __I uint32_t RXBUF; // <h> Receive buffer </h>
Kojto 102:da0ca467f8b5 412 // <o.15..0> Right channel
Kojto 102:da0ca467f8b5 413 // <o.31..16> Left channel
Kojto 102:da0ca467f8b5 414 uint32_t RESERVED1[186];
Kojto 102:da0ca467f8b5 415 __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
Kojto 102:da0ca467f8b5 416 // <o.0> ITEN
Kojto 102:da0ca467f8b5 417 // <0=> Normal operation
Kojto 102:da0ca467f8b5 418 // <1=> Integration Test mode enable
Kojto 102:da0ca467f8b5 419 __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
Kojto 102:da0ca467f8b5 420 // <o.0> SDIN
Kojto 102:da0ca467f8b5 421 __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
Kojto 102:da0ca467f8b5 422 // <o.0> SDOUT
Kojto 102:da0ca467f8b5 423 // <o.1> SCLK
Kojto 102:da0ca467f8b5 424 // <o.2> LRCK
Kojto 102:da0ca467f8b5 425 // <o.3> IRQOUT
Kojto 102:da0ca467f8b5 426 } MPS2_I2S_TypeDef;
Kojto 102:da0ca467f8b5 427
Kojto 102:da0ca467f8b5 428 #define I2S_CONTROL_TXEN_Pos 0
Kojto 102:da0ca467f8b5 429 #define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
Kojto 102:da0ca467f8b5 430
Kojto 102:da0ca467f8b5 431 #define I2S_CONTROL_TXIRQEN_Pos 1
Kojto 102:da0ca467f8b5 432 #define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
Kojto 102:da0ca467f8b5 433
Kojto 102:da0ca467f8b5 434 #define I2S_CONTROL_RXEN_Pos 2
Kojto 102:da0ca467f8b5 435 #define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
Kojto 102:da0ca467f8b5 436
Kojto 102:da0ca467f8b5 437 #define I2S_CONTROL_RXIRQEN_Pos 3
Kojto 102:da0ca467f8b5 438 #define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
Kojto 102:da0ca467f8b5 439
Kojto 102:da0ca467f8b5 440 #define I2S_CONTROL_TXWLVL_Pos 8
Kojto 102:da0ca467f8b5 441 #define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
Kojto 102:da0ca467f8b5 442
Kojto 102:da0ca467f8b5 443 #define I2S_CONTROL_RXWLVL_Pos 12
Kojto 102:da0ca467f8b5 444 #define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
Kojto 102:da0ca467f8b5 445 /* FIFO reset*/
Kojto 102:da0ca467f8b5 446 #define I2S_CONTROL_FIFORST_Pos 16
Kojto 102:da0ca467f8b5 447 #define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
Kojto 102:da0ca467f8b5 448 /* Codec reset*/
Kojto 102:da0ca467f8b5 449 #define I2S_CONTROL_CODECRST_Pos 17
Kojto 102:da0ca467f8b5 450 #define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
Kojto 102:da0ca467f8b5 451
Kojto 102:da0ca467f8b5 452 #define I2S_STATUS_TXIRQ_Pos 0
Kojto 102:da0ca467f8b5 453 #define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
Kojto 102:da0ca467f8b5 454
Kojto 102:da0ca467f8b5 455 #define I2S_STATUS_RXIRQ_Pos 1
Kojto 102:da0ca467f8b5 456 #define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
Kojto 102:da0ca467f8b5 457
Kojto 102:da0ca467f8b5 458 #define I2S_STATUS_TXEmpty_Pos 2
Kojto 102:da0ca467f8b5 459 #define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
Kojto 102:da0ca467f8b5 460
Kojto 102:da0ca467f8b5 461 #define I2S_STATUS_TXFull_Pos 3
Kojto 102:da0ca467f8b5 462 #define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
Kojto 102:da0ca467f8b5 463
Kojto 102:da0ca467f8b5 464 #define I2S_STATUS_RXEmpty_Pos 4
Kojto 102:da0ca467f8b5 465 #define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
Kojto 102:da0ca467f8b5 466
Kojto 102:da0ca467f8b5 467 #define I2S_STATUS_RXFull_Pos 5
Kojto 102:da0ca467f8b5 468 #define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
Kojto 102:da0ca467f8b5 469
Kojto 102:da0ca467f8b5 470 #define I2S_ERROR_TXERR_Pos 0
Kojto 102:da0ca467f8b5 471 #define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
Kojto 102:da0ca467f8b5 472
Kojto 102:da0ca467f8b5 473 #define I2S_ERROR_RXERR_Pos 1
Kojto 102:da0ca467f8b5 474 #define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
Kojto 102:da0ca467f8b5 475
Kojto 102:da0ca467f8b5 476 /******************************************************************************/
Kojto 102:da0ca467f8b5 477 /* SMSC9220 Register Definitions */
Kojto 102:da0ca467f8b5 478 /******************************************************************************/
Kojto 102:da0ca467f8b5 479
Kojto 102:da0ca467f8b5 480 typedef struct // SMSC LAN9220
Kojto 102:da0ca467f8b5 481 {
Kojto 102:da0ca467f8b5 482 __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
Kojto 102:da0ca467f8b5 483 uint32_t RESERVED1[0x7];
Kojto 102:da0ca467f8b5 484 __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
Kojto 102:da0ca467f8b5 485 uint32_t RESERVED2[0x7];
Kojto 102:da0ca467f8b5 486
Kojto 102:da0ca467f8b5 487 __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
Kojto 102:da0ca467f8b5 488 __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
Kojto 102:da0ca467f8b5 489 __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
Kojto 102:da0ca467f8b5 490 __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
Kojto 102:da0ca467f8b5 491
Kojto 102:da0ca467f8b5 492 __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
Kojto 102:da0ca467f8b5 493 __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
Kojto 102:da0ca467f8b5 494 __IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
Kojto 102:da0ca467f8b5 495 __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
Kojto 102:da0ca467f8b5 496 uint32_t RESERVED3; // Reserved for future use (offset 0x60)
Kojto 102:da0ca467f8b5 497 __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
Kojto 102:da0ca467f8b5 498 __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
Kojto 102:da0ca467f8b5 499 __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
Kojto 102:da0ca467f8b5 500 __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
Kojto 102:da0ca467f8b5 501 __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
Kojto 102:da0ca467f8b5 502 __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
Kojto 102:da0ca467f8b5 503 __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
Kojto 102:da0ca467f8b5 504 __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
Kojto 102:da0ca467f8b5 505 __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
Kojto 102:da0ca467f8b5 506 __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
Kojto 102:da0ca467f8b5 507 __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
Kojto 102:da0ca467f8b5 508 __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
Kojto 102:da0ca467f8b5 509 uint32_t RESERVED4; // Reserved for future use (offset 0x94)
Kojto 102:da0ca467f8b5 510 __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
Kojto 102:da0ca467f8b5 511 __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
Kojto 102:da0ca467f8b5 512 __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
Kojto 102:da0ca467f8b5 513 __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
Kojto 102:da0ca467f8b5 514 __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
Kojto 102:da0ca467f8b5 515 __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
Kojto 102:da0ca467f8b5 516 __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
Kojto 102:da0ca467f8b5 517 __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
Kojto 102:da0ca467f8b5 518
Kojto 102:da0ca467f8b5 519 } SMSC9220_TypeDef;
Kojto 102:da0ca467f8b5 520
Kojto 102:da0ca467f8b5 521 // SMSC9220 MAC Registers Indices
Kojto 102:da0ca467f8b5 522 #define SMSC9220_MAC_CR 0x1
Kojto 102:da0ca467f8b5 523 #define SMSC9220_MAC_ADDRH 0x2
Kojto 102:da0ca467f8b5 524 #define SMSC9220_MAC_ADDRL 0x3
Kojto 102:da0ca467f8b5 525 #define SMSC9220_MAC_HASHH 0x4
Kojto 102:da0ca467f8b5 526 #define SMSC9220_MAC_HASHL 0x5
Kojto 102:da0ca467f8b5 527 #define SMSC9220_MAC_MII_ACC 0x6
Kojto 102:da0ca467f8b5 528 #define SMSC9220_MAC_MII_DATA 0x7
Kojto 102:da0ca467f8b5 529 #define SMSC9220_MAC_FLOW 0x8
Kojto 102:da0ca467f8b5 530 #define SMSC9220_MAC_VLAN1 0x9
Kojto 102:da0ca467f8b5 531 #define SMSC9220_MAC_VLAN2 0xA
Kojto 102:da0ca467f8b5 532 #define SMSC9220_MAC_WUFF 0xB
Kojto 102:da0ca467f8b5 533 #define SMSC9220_MAC_WUCSR 0xC
Kojto 102:da0ca467f8b5 534
Kojto 102:da0ca467f8b5 535 // SMSC9220 PHY Registers Indices
Kojto 102:da0ca467f8b5 536 #define SMSC9220_PHY_BCONTROL 0x0
Kojto 102:da0ca467f8b5 537 #define SMSC9220_PHY_BSTATUS 0x1
Kojto 102:da0ca467f8b5 538 #define SMSC9220_PHY_ID1 0x2
Kojto 102:da0ca467f8b5 539 #define SMSC9220_PHY_ID2 0x3
Kojto 102:da0ca467f8b5 540 #define SMSC9220_PHY_ANEG_ADV 0x4
Kojto 102:da0ca467f8b5 541 #define SMSC9220_PHY_ANEG_LPA 0x5
Kojto 102:da0ca467f8b5 542 #define SMSC9220_PHY_ANEG_EXP 0x6
Kojto 102:da0ca467f8b5 543 #define SMSC9220_PHY_MCONTROL 0x17
Kojto 102:da0ca467f8b5 544 #define SMSC9220_PHY_MSTATUS 0x18
Kojto 102:da0ca467f8b5 545 #define SMSC9220_PHY_CSINDICATE 0x27
Kojto 102:da0ca467f8b5 546 #define SMSC9220_PHY_INTSRC 0x29
Kojto 102:da0ca467f8b5 547 #define SMSC9220_PHY_INTMASK 0x30
Kojto 102:da0ca467f8b5 548 #define SMSC9220_PHY_CS 0x31
Kojto 102:da0ca467f8b5 549
Kojto 102:da0ca467f8b5 550 /******************************************************************************/
Kojto 102:da0ca467f8b5 551 /* Peripheral memory map */
Kojto 102:da0ca467f8b5 552 /******************************************************************************/
Kojto 102:da0ca467f8b5 553
Kojto 102:da0ca467f8b5 554 #define MPS2_SSP1_BASE (0x40020000ul) /* User SSP Base Address */
Kojto 102:da0ca467f8b5 555 #define MPS2_SSP0_BASE (0x40021000ul) /* CLCD SSP Base Address */
Kojto 102:da0ca467f8b5 556 #define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
Kojto 102:da0ca467f8b5 557 #define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
Kojto 102:da0ca467f8b5 558 #define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
Kojto 102:da0ca467f8b5 559 #define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
Kojto 102:da0ca467f8b5 560 #define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
Kojto 102:da0ca467f8b5 561
Kojto 102:da0ca467f8b5 562 #ifdef CORTEX_M7
Kojto 102:da0ca467f8b5 563 #define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
Kojto 102:da0ca467f8b5 564 #else
Kojto 102:da0ca467f8b5 565 #define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
Kojto 102:da0ca467f8b5 566 #endif
Kojto 102:da0ca467f8b5 567
Kojto 102:da0ca467f8b5 568 #define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
Kojto 102:da0ca467f8b5 569 #define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
Kojto 102:da0ca467f8b5 570
Kojto 102:da0ca467f8b5 571 /******************************************************************************/
Kojto 102:da0ca467f8b5 572 /* Peripheral declaration */
Kojto 102:da0ca467f8b5 573 /******************************************************************************/
Kojto 102:da0ca467f8b5 574
Kojto 102:da0ca467f8b5 575 #define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
Kojto 102:da0ca467f8b5 576 #define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
Kojto 102:da0ca467f8b5 577 #define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
Kojto 102:da0ca467f8b5 578 #define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
Kojto 102:da0ca467f8b5 579 #define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
Kojto 102:da0ca467f8b5 580 #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
Kojto 102:da0ca467f8b5 581 #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
Kojto 102:da0ca467f8b5 582 #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
Kojto 102:da0ca467f8b5 583
Kojto 102:da0ca467f8b5 584 /******************************************************************************/
Kojto 102:da0ca467f8b5 585 /* General Function Definitions */
Kojto 102:da0ca467f8b5 586 /******************************************************************************/
Kojto 102:da0ca467f8b5 587
Kojto 102:da0ca467f8b5 588
Kojto 102:da0ca467f8b5 589 /******************************************************************************/
Kojto 102:da0ca467f8b5 590 /* General MACRO Definitions */
Kojto 102:da0ca467f8b5 591 /******************************************************************************/
Kojto 102:da0ca467f8b5 592
Kojto 102:da0ca467f8b5 593
Kojto 102:da0ca467f8b5 594
Kojto 102:da0ca467f8b5 595 #endif /* __SMM_MPS2_H */