Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_NUCLEO_F746ZG/stm32f7xx_hal_rcc.h@116:c0f6e94411f5, 2016-03-15 (annotated)

Committer:
Kojto
Date:
Tue Mar 15 14:34:00 2016 +0000
Revision:
116:c0f6e94411f5
Parent:
115:87f2f5183dfb 
Release 116 of the mbed library



Changes:

- new targets - NUCLEO_L073RZ

- fixes to IOTSS BEID platform

- LPC824, LPC1549 and LPC11U68 - fix PWMOut SCT bugs

- STM32F7 - Cube driver

- STM32F4 - add RTC LSI macro, defined as 0

- STM32F3 - fix multiple ADC clock initialization

- retarget - binary mode fix for GCC

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 115:87f2f5183dfb 1 /**
Kojto 115:87f2f5183dfb 2 ******************************************************************************
Kojto 115:87f2f5183dfb 3 * @file stm32f7xx_hal_rcc.h
Kojto 115:87f2f5183dfb 4 * @author MCD Application Team
Kojto 116:c0f6e94411f5 5 * @version V1.0.4
Kojto 116:c0f6e94411f5 6 * @date 09-December-2015
Kojto 115:87f2f5183dfb 7 * @brief Header file of RCC HAL module.
Kojto 115:87f2f5183dfb 8 ******************************************************************************
Kojto 115:87f2f5183dfb 9 * @attention
Kojto 115:87f2f5183dfb 10 *
Kojto 115:87f2f5183dfb 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 115:87f2f5183dfb 12 *
Kojto 115:87f2f5183dfb 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 115:87f2f5183dfb 14 * are permitted provided that the following conditions are met:
Kojto 115:87f2f5183dfb 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 115:87f2f5183dfb 16 * this list of conditions and the following disclaimer.
Kojto 115:87f2f5183dfb 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 115:87f2f5183dfb 18 * this list of conditions and the following disclaimer in the documentation
Kojto 115:87f2f5183dfb 19 * and/or other materials provided with the distribution.
Kojto 115:87f2f5183dfb 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 115:87f2f5183dfb 21 * may be used to endorse or promote products derived from this software
Kojto 115:87f2f5183dfb 22 * without specific prior written permission.
Kojto 115:87f2f5183dfb 23 *
Kojto 115:87f2f5183dfb 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 115:87f2f5183dfb 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 115:87f2f5183dfb 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 115:87f2f5183dfb 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 115:87f2f5183dfb 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 115:87f2f5183dfb 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 115:87f2f5183dfb 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 115:87f2f5183dfb 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 115:87f2f5183dfb 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 115:87f2f5183dfb 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 115:87f2f5183dfb 34 *
Kojto 115:87f2f5183dfb 35 ******************************************************************************
Kojto 115:87f2f5183dfb 36 */
Kojto 115:87f2f5183dfb 37
Kojto 115:87f2f5183dfb 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 115:87f2f5183dfb 39 #ifndef __STM32F7xx_HAL_RCC_H
Kojto 115:87f2f5183dfb 40 #define __STM32F7xx_HAL_RCC_H
Kojto 115:87f2f5183dfb 41
Kojto 115:87f2f5183dfb 42 #ifdef __cplusplus
Kojto 115:87f2f5183dfb 43 extern "C" {
Kojto 115:87f2f5183dfb 44 #endif
Kojto 115:87f2f5183dfb 45
Kojto 115:87f2f5183dfb 46 /* Includes ------------------------------------------------------------------*/
Kojto 115:87f2f5183dfb 47 #include "stm32f7xx_hal_def.h"
Kojto 115:87f2f5183dfb 48
Kojto 115:87f2f5183dfb 49 /** @addtogroup STM32F7xx_HAL_Driver
Kojto 115:87f2f5183dfb 50 * @{
Kojto 115:87f2f5183dfb 51 */
Kojto 115:87f2f5183dfb 52
Kojto 115:87f2f5183dfb 53 /** @addtogroup RCC
Kojto 115:87f2f5183dfb 54 * @{
Kojto 115:87f2f5183dfb 55 */
Kojto 115:87f2f5183dfb 56
Kojto 115:87f2f5183dfb 57 /* Exported types ------------------------------------------------------------*/
Kojto 115:87f2f5183dfb 58
Kojto 115:87f2f5183dfb 59 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 115:87f2f5183dfb 60 * @{
Kojto 115:87f2f5183dfb 61 */
Kojto 115:87f2f5183dfb 62
Kojto 115:87f2f5183dfb 63 /**
Kojto 115:87f2f5183dfb 64 * @brief RCC PLL configuration structure definition
Kojto 115:87f2f5183dfb 65 */
Kojto 115:87f2f5183dfb 66 typedef struct
Kojto 115:87f2f5183dfb 67 {
Kojto 115:87f2f5183dfb 68 uint32_t PLLState; /*!< The new state of the PLL.
Kojto 115:87f2f5183dfb 69 This parameter can be a value of @ref RCC_PLL_Config */
Kojto 115:87f2f5183dfb 70
Kojto 115:87f2f5183dfb 71 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto 115:87f2f5183dfb 72 This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto 115:87f2f5183dfb 73
Kojto 115:87f2f5183dfb 74 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto 115:87f2f5183dfb 75 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto 115:87f2f5183dfb 76
Kojto 115:87f2f5183dfb 77 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto 116:c0f6e94411f5 78 This parameter must be a number between Min_Data = 100 and Max_Data = 432 */
Kojto 115:87f2f5183dfb 79
Kojto 115:87f2f5183dfb 80 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
Kojto 115:87f2f5183dfb 81 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto 115:87f2f5183dfb 82
Kojto 115:87f2f5183dfb 83 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
Kojto 115:87f2f5183dfb 84 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
Kojto 115:87f2f5183dfb 85
Kojto 115:87f2f5183dfb 86 }RCC_PLLInitTypeDef;
Kojto 115:87f2f5183dfb 87
Kojto 115:87f2f5183dfb 88 /**
Kojto 115:87f2f5183dfb 89 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto 115:87f2f5183dfb 90 */
Kojto 115:87f2f5183dfb 91 typedef struct
Kojto 115:87f2f5183dfb 92 {
Kojto 115:87f2f5183dfb 93 uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto 115:87f2f5183dfb 94 This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto 115:87f2f5183dfb 95
Kojto 115:87f2f5183dfb 96 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 115:87f2f5183dfb 97 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 115:87f2f5183dfb 98
Kojto 115:87f2f5183dfb 99 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 115:87f2f5183dfb 100 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 115:87f2f5183dfb 101
Kojto 115:87f2f5183dfb 102 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 115:87f2f5183dfb 103 This parameter can be a value of @ref RCC_HSI_Config */
Kojto 115:87f2f5183dfb 104
Kojto 115:87f2f5183dfb 105 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 115:87f2f5183dfb 106 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 115:87f2f5183dfb 107
Kojto 115:87f2f5183dfb 108 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 115:87f2f5183dfb 109 This parameter can be a value of @ref RCC_LSI_Config */
Kojto 115:87f2f5183dfb 110
Kojto 115:87f2f5183dfb 111 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
Kojto 115:87f2f5183dfb 112
Kojto 115:87f2f5183dfb 113 }RCC_OscInitTypeDef;
Kojto 115:87f2f5183dfb 114
Kojto 115:87f2f5183dfb 115 /**
Kojto 115:87f2f5183dfb 116 * @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto 115:87f2f5183dfb 117 */
Kojto 115:87f2f5183dfb 118 typedef struct
Kojto 115:87f2f5183dfb 119 {
Kojto 115:87f2f5183dfb 120 uint32_t ClockType; /*!< The clock to be configured.
Kojto 115:87f2f5183dfb 121 This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto 115:87f2f5183dfb 122
Kojto 115:87f2f5183dfb 123 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto 115:87f2f5183dfb 124 This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto 115:87f2f5183dfb 125
Kojto 115:87f2f5183dfb 126 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto 115:87f2f5183dfb 127 This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto 115:87f2f5183dfb 128
Kojto 115:87f2f5183dfb 129 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto 115:87f2f5183dfb 130 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 115:87f2f5183dfb 131
Kojto 115:87f2f5183dfb 132 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto 115:87f2f5183dfb 133 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 115:87f2f5183dfb 134
Kojto 115:87f2f5183dfb 135 }RCC_ClkInitTypeDef;
Kojto 115:87f2f5183dfb 136
Kojto 115:87f2f5183dfb 137 /**
Kojto 115:87f2f5183dfb 138 * @}
Kojto 115:87f2f5183dfb 139 */
Kojto 115:87f2f5183dfb 140
Kojto 115:87f2f5183dfb 141 /* Exported constants --------------------------------------------------------*/
Kojto 115:87f2f5183dfb 142 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 115:87f2f5183dfb 143 * @{
Kojto 115:87f2f5183dfb 144 */
Kojto 115:87f2f5183dfb 145
Kojto 115:87f2f5183dfb 146 /** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto 115:87f2f5183dfb 147 * @{
Kojto 115:87f2f5183dfb 148 */
Kojto 115:87f2f5183dfb 149 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto 115:87f2f5183dfb 150 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto 115:87f2f5183dfb 151 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto 115:87f2f5183dfb 152 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto 115:87f2f5183dfb 153 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto 115:87f2f5183dfb 154 /**
Kojto 115:87f2f5183dfb 155 * @}
Kojto 115:87f2f5183dfb 156 */
Kojto 115:87f2f5183dfb 157
Kojto 115:87f2f5183dfb 158 /** @defgroup RCC_HSE_Config RCC HSE Config
Kojto 115:87f2f5183dfb 159 * @{
Kojto 115:87f2f5183dfb 160 */
Kojto 115:87f2f5183dfb 161 #define RCC_HSE_OFF ((uint32_t)0x00000000)
Kojto 115:87f2f5183dfb 162 #define RCC_HSE_ON RCC_CR_HSEON
Kojto 115:87f2f5183dfb 163 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
Kojto 115:87f2f5183dfb 164 /**
Kojto 115:87f2f5183dfb 165 * @}
Kojto 115:87f2f5183dfb 166 */
Kojto 115:87f2f5183dfb 167
Kojto 115:87f2f5183dfb 168 /** @defgroup RCC_LSE_Config RCC LSE Config
Kojto 115:87f2f5183dfb 169 * @{
Kojto 115:87f2f5183dfb 170 */
Kojto 115:87f2f5183dfb 171 #define RCC_LSE_OFF ((uint32_t)0x00000000)
Kojto 115:87f2f5183dfb 172 #define RCC_LSE_ON RCC_BDCR_LSEON
Kojto 115:87f2f5183dfb 173 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
Kojto 115:87f2f5183dfb 174 /**
Kojto 115:87f2f5183dfb 175 * @}
Kojto 115:87f2f5183dfb 176 */
Kojto 115:87f2f5183dfb 177
Kojto 115:87f2f5183dfb 178 /** @defgroup RCC_HSI_Config RCC HSI Config
Kojto 115:87f2f5183dfb 179 * @{
Kojto 115:87f2f5183dfb 180 */
Kojto 115:87f2f5183dfb 181 #define RCC_HSI_OFF ((uint32_t)0x00000000)
Kojto 115:87f2f5183dfb 182 #define RCC_HSI_ON RCC_CR_HSION
Kojto 115:87f2f5183dfb 183 /**
Kojto 115:87f2f5183dfb 184 * @}
Kojto 115:87f2f5183dfb 185 */
Kojto 115:87f2f5183dfb 186
Kojto 115:87f2f5183dfb 187 /** @defgroup RCC_LSI_Config RCC LSI Config
Kojto 115:87f2f5183dfb 188 * @{
Kojto 115:87f2f5183dfb 189 */
Kojto 115:87f2f5183dfb 190 #define RCC_LSI_OFF ((uint32_t)0x00000000)
Kojto 115:87f2f5183dfb 191 #define RCC_LSI_ON RCC_CSR_LSION
Kojto 115:87f2f5183dfb 192 /**
Kojto 115:87f2f5183dfb 193 * @}
Kojto 115:87f2f5183dfb 194 */
Kojto 115:87f2f5183dfb 195
Kojto 115:87f2f5183dfb 196 /** @defgroup RCC_PLL_Config RCC PLL Config
Kojto 115:87f2f5183dfb 197 * @{
Kojto 115:87f2f5183dfb 198 */
Kojto 115:87f2f5183dfb 199 #define RCC_PLL_NONE ((uint32_t)0x00000000)
Kojto 115:87f2f5183dfb 200 #define RCC_PLL_OFF ((uint32_t)0x00000001)
Kojto 115:87f2f5183dfb 201 #define RCC_PLL_ON ((uint32_t)0x00000002)
Kojto 115:87f2f5183dfb 202 /**
Kojto 115:87f2f5183dfb 203 * @}
Kojto 115:87f2f5183dfb 204 */
Kojto 115:87f2f5183dfb 205
Kojto 115:87f2f5183dfb 206 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
Kojto 115:87f2f5183dfb 207 * @{
Kojto 115:87f2f5183dfb 208 */
Kojto 115:87f2f5183dfb 209 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
Kojto 115:87f2f5183dfb 210 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
Kojto 115:87f2f5183dfb 211 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
Kojto 115:87f2f5183dfb 212 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
Kojto 115:87f2f5183dfb 213 /**
Kojto 115:87f2f5183dfb 214 * @}
Kojto 115:87f2f5183dfb 215 */
Kojto 115:87f2f5183dfb 216
Kojto 115:87f2f5183dfb 217 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Kojto 115:87f2f5183dfb 218 * @{
Kojto 115:87f2f5183dfb 219 */
Kojto 115:87f2f5183dfb 220 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
Kojto 115:87f2f5183dfb 221 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
Kojto 115:87f2f5183dfb 222 /**
Kojto 115:87f2f5183dfb 223 * @}
Kojto 115:87f2f5183dfb 224 */
Kojto 115:87f2f5183dfb 225
Kojto 115:87f2f5183dfb 226 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
Kojto 115:87f2f5183dfb 227 * @{
Kojto 115:87f2f5183dfb 228 */
Kojto 115:87f2f5183dfb 229 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto 115:87f2f5183dfb 230 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto 115:87f2f5183dfb 231 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto 115:87f2f5183dfb 232 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto 115:87f2f5183dfb 233 /**
Kojto 115:87f2f5183dfb 234 * @}
Kojto 115:87f2f5183dfb 235 */
Kojto 115:87f2f5183dfb 236
Kojto 115:87f2f5183dfb 237 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
Kojto 115:87f2f5183dfb 238 * @{
Kojto 115:87f2f5183dfb 239 */
Kojto 115:87f2f5183dfb 240 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto 115:87f2f5183dfb 241 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto 115:87f2f5183dfb 242 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto 115:87f2f5183dfb 243 /**
Kojto 115:87f2f5183dfb 244 * @}
Kojto 115:87f2f5183dfb 245 */
Kojto 115:87f2f5183dfb 246
Kojto 115:87f2f5183dfb 247
Kojto 115:87f2f5183dfb 248 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto 115:87f2f5183dfb 249 * @{
Kojto 115:87f2f5183dfb 250 */
Kojto 115:87f2f5183dfb 251 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 115:87f2f5183dfb 252 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 115:87f2f5183dfb 253 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 115:87f2f5183dfb 254 /**
Kojto 115:87f2f5183dfb 255 * @}
Kojto 115:87f2f5183dfb 256 */
Kojto 115:87f2f5183dfb 257
Kojto 115:87f2f5183dfb 258 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
Kojto 115:87f2f5183dfb 259 * @{
Kojto 115:87f2f5183dfb 260 */
Kojto 115:87f2f5183dfb 261 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto 115:87f2f5183dfb 262 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto 115:87f2f5183dfb 263 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto 115:87f2f5183dfb 264 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto 115:87f2f5183dfb 265 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto 115:87f2f5183dfb 266 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto 115:87f2f5183dfb 267 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto 115:87f2f5183dfb 268 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto 115:87f2f5183dfb 269 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto 115:87f2f5183dfb 270 /**
Kojto 115:87f2f5183dfb 271 * @}
Kojto 115:87f2f5183dfb 272 */
Kojto 115:87f2f5183dfb 273
Kojto 115:87f2f5183dfb 274 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source
Kojto 115:87f2f5183dfb 275 * @{
Kojto 115:87f2f5183dfb 276 */
Kojto 115:87f2f5183dfb 277 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Kojto 115:87f2f5183dfb 278 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Kojto 115:87f2f5183dfb 279 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Kojto 115:87f2f5183dfb 280 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Kojto 115:87f2f5183dfb 281 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Kojto 115:87f2f5183dfb 282 /**
Kojto 115:87f2f5183dfb 283 * @}
Kojto 115:87f2f5183dfb 284 */
Kojto 115:87f2f5183dfb 285
Kojto 115:87f2f5183dfb 286 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
Kojto 115:87f2f5183dfb 287 * @{
Kojto 115:87f2f5183dfb 288 */
Kojto 115:87f2f5183dfb 289 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
Kojto 115:87f2f5183dfb 290 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
Kojto 115:87f2f5183dfb 291 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
Kojto 115:87f2f5183dfb 292 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
Kojto 115:87f2f5183dfb 293 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
Kojto 115:87f2f5183dfb 294 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
Kojto 115:87f2f5183dfb 295 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
Kojto 115:87f2f5183dfb 296 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
Kojto 115:87f2f5183dfb 297 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
Kojto 115:87f2f5183dfb 298 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
Kojto 115:87f2f5183dfb 299 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
Kojto 115:87f2f5183dfb 300 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
Kojto 115:87f2f5183dfb 301 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
Kojto 115:87f2f5183dfb 302 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
Kojto 115:87f2f5183dfb 303 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
Kojto 115:87f2f5183dfb 304 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
Kojto 115:87f2f5183dfb 305 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
Kojto 115:87f2f5183dfb 306 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
Kojto 115:87f2f5183dfb 307 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
Kojto 115:87f2f5183dfb 308 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
Kojto 115:87f2f5183dfb 309 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
Kojto 115:87f2f5183dfb 310 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
Kojto 115:87f2f5183dfb 311 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
Kojto 115:87f2f5183dfb 312 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
Kojto 115:87f2f5183dfb 313 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
Kojto 115:87f2f5183dfb 314 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
Kojto 115:87f2f5183dfb 315 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
Kojto 115:87f2f5183dfb 316 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
Kojto 115:87f2f5183dfb 317 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
Kojto 115:87f2f5183dfb 318 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
Kojto 115:87f2f5183dfb 319 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
Kojto 115:87f2f5183dfb 320 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
Kojto 115:87f2f5183dfb 321 /**
Kojto 115:87f2f5183dfb 322 * @}
Kojto 115:87f2f5183dfb 323 */
Kojto 115:87f2f5183dfb 324
Kojto 115:87f2f5183dfb 325
Kojto 115:87f2f5183dfb 326
Kojto 115:87f2f5183dfb 327 /** @defgroup RCC_MCO_Index RCC MCO Index
Kojto 115:87f2f5183dfb 328 * @{
Kojto 115:87f2f5183dfb 329 */
Kojto 115:87f2f5183dfb 330 #define RCC_MCO1 ((uint32_t)0x00000000)
Kojto 115:87f2f5183dfb 331 #define RCC_MCO2 ((uint32_t)0x00000001)
Kojto 115:87f2f5183dfb 332 /**
Kojto 115:87f2f5183dfb 333 * @}
Kojto 115:87f2f5183dfb 334 */
Kojto 115:87f2f5183dfb 335
Kojto 115:87f2f5183dfb 336 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
Kojto 115:87f2f5183dfb 337 * @{
Kojto 115:87f2f5183dfb 338 */
Kojto 115:87f2f5183dfb 339 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
Kojto 115:87f2f5183dfb 340 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
Kojto 115:87f2f5183dfb 341 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
Kojto 115:87f2f5183dfb 342 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
Kojto 115:87f2f5183dfb 343 /**
Kojto 115:87f2f5183dfb 344 * @}
Kojto 115:87f2f5183dfb 345 */
Kojto 115:87f2f5183dfb 346
Kojto 115:87f2f5183dfb 347 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
Kojto 115:87f2f5183dfb 348 * @{
Kojto 115:87f2f5183dfb 349 */
Kojto 115:87f2f5183dfb 350 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
Kojto 115:87f2f5183dfb 351 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
Kojto 115:87f2f5183dfb 352 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
Kojto 115:87f2f5183dfb 353 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
Kojto 115:87f2f5183dfb 354 /**
Kojto 115:87f2f5183dfb 355 * @}
Kojto 115:87f2f5183dfb 356 */
Kojto 115:87f2f5183dfb 357
Kojto 115:87f2f5183dfb 358 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
Kojto 115:87f2f5183dfb 359 * @{
Kojto 115:87f2f5183dfb 360 */
Kojto 115:87f2f5183dfb 361 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
Kojto 115:87f2f5183dfb 362 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
Kojto 115:87f2f5183dfb 363 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
Kojto 115:87f2f5183dfb 364 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
Kojto 115:87f2f5183dfb 365 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
Kojto 115:87f2f5183dfb 366 /**
Kojto 115:87f2f5183dfb 367 * @}
Kojto 115:87f2f5183dfb 368 */
Kojto 115:87f2f5183dfb 369
Kojto 115:87f2f5183dfb 370 /** @defgroup RCC_Interrupt RCC Interrupt
Kojto 115:87f2f5183dfb 371 * @{
Kojto 115:87f2f5183dfb 372 */
Kojto 115:87f2f5183dfb 373 #define RCC_IT_LSIRDY ((uint8_t)0x01)
Kojto 115:87f2f5183dfb 374 #define RCC_IT_LSERDY ((uint8_t)0x02)
Kojto 115:87f2f5183dfb 375 #define RCC_IT_HSIRDY ((uint8_t)0x04)
Kojto 115:87f2f5183dfb 376 #define RCC_IT_HSERDY ((uint8_t)0x08)
Kojto 115:87f2f5183dfb 377 #define RCC_IT_PLLRDY ((uint8_t)0x10)
Kojto 115:87f2f5183dfb 378 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
Kojto 115:87f2f5183dfb 379 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
Kojto 115:87f2f5183dfb 380 #define RCC_IT_CSS ((uint8_t)0x80)
Kojto 115:87f2f5183dfb 381 /**
Kojto 115:87f2f5183dfb 382 * @}
Kojto 115:87f2f5183dfb 383 */
Kojto 115:87f2f5183dfb 384
Kojto 115:87f2f5183dfb 385 /** @defgroup RCC_Flag RCC Flags
Kojto 115:87f2f5183dfb 386 * Elements values convention: 0XXYYYYYb
Kojto 115:87f2f5183dfb 387 * - YYYYY : Flag position in the register
Kojto 115:87f2f5183dfb 388 * - 0XX : Register index
Kojto 115:87f2f5183dfb 389 * - 01: CR register
Kojto 115:87f2f5183dfb 390 * - 10: BDCR register
Kojto 115:87f2f5183dfb 391 * - 11: CSR register
Kojto 115:87f2f5183dfb 392 * @{
Kojto 115:87f2f5183dfb 393 */
Kojto 115:87f2f5183dfb 394 /* Flags in the CR register */
Kojto 115:87f2f5183dfb 395 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
Kojto 115:87f2f5183dfb 396 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
Kojto 115:87f2f5183dfb 397 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
Kojto 115:87f2f5183dfb 398 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
Kojto 115:87f2f5183dfb 399 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C)
Kojto 115:87f2f5183dfb 400
Kojto 115:87f2f5183dfb 401 /* Flags in the BDCR register */
Kojto 115:87f2f5183dfb 402 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
Kojto 115:87f2f5183dfb 403
Kojto 115:87f2f5183dfb 404 /* Flags in the CSR register */
Kojto 115:87f2f5183dfb 405 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
Kojto 115:87f2f5183dfb 406 #define RCC_FLAG_BORRST ((uint8_t)0x79)
Kojto 115:87f2f5183dfb 407 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
Kojto 115:87f2f5183dfb 408 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
Kojto 115:87f2f5183dfb 409 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
Kojto 115:87f2f5183dfb 410 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
Kojto 115:87f2f5183dfb 411 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
Kojto 115:87f2f5183dfb 412 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
Kojto 115:87f2f5183dfb 413 /**
Kojto 115:87f2f5183dfb 414 * @}
Kojto 115:87f2f5183dfb 415 */
Kojto 115:87f2f5183dfb 416
Kojto 115:87f2f5183dfb 417 /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
Kojto 115:87f2f5183dfb 418 * @{
Kojto 115:87f2f5183dfb 419 */
Kojto 115:87f2f5183dfb 420 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
Kojto 115:87f2f5183dfb 421 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
Kojto 115:87f2f5183dfb 422 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
Kojto 115:87f2f5183dfb 423 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
Kojto 115:87f2f5183dfb 424 /**
Kojto 115:87f2f5183dfb 425 * @}
Kojto 115:87f2f5183dfb 426 */
Kojto 115:87f2f5183dfb 427
Kojto 115:87f2f5183dfb 428 /**
Kojto 115:87f2f5183dfb 429 * @}
Kojto 115:87f2f5183dfb 430 */
Kojto 115:87f2f5183dfb 431
Kojto 115:87f2f5183dfb 432 /* Exported macro ------------------------------------------------------------*/
Kojto 115:87f2f5183dfb 433 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 115:87f2f5183dfb 434 * @{
Kojto 115:87f2f5183dfb 435 */
Kojto 115:87f2f5183dfb 436
Kojto 115:87f2f5183dfb 437 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto 115:87f2f5183dfb 438 * @brief Enable or disable the AHB1 peripheral clock.
Kojto 115:87f2f5183dfb 439 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 440 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 441 * using it.
Kojto 115:87f2f5183dfb 442 * @{
Kojto 115:87f2f5183dfb 443 */
Kojto 115:87f2f5183dfb 444 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto 116:c0f6e94411f5 445 __IO uint32_t tmpreg = 0x00; \
Kojto 115:87f2f5183dfb 446 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto 115:87f2f5183dfb 447 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 448 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto 115:87f2f5183dfb 449 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 450 } while(0)
Kojto 115:87f2f5183dfb 451
Kojto 115:87f2f5183dfb 452 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 116:c0f6e94411f5 453 __IO uint32_t tmpreg = 0x00; \
Kojto 115:87f2f5183dfb 454 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 115:87f2f5183dfb 455 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 456 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 115:87f2f5183dfb 457 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 458 } while(0)
Kojto 115:87f2f5183dfb 459
Kojto 115:87f2f5183dfb 460 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto 115:87f2f5183dfb 461 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Kojto 115:87f2f5183dfb 462
Kojto 115:87f2f5183dfb 463 /**
Kojto 115:87f2f5183dfb 464 * @}
Kojto 115:87f2f5183dfb 465 */
Kojto 115:87f2f5183dfb 466
Kojto 115:87f2f5183dfb 467 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto 115:87f2f5183dfb 468 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 115:87f2f5183dfb 469 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 470 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 471 * using it.
Kojto 115:87f2f5183dfb 472 * @{
Kojto 115:87f2f5183dfb 473 */
Kojto 115:87f2f5183dfb 474 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto 116:c0f6e94411f5 475 __IO uint32_t tmpreg = 0x00; \
Kojto 115:87f2f5183dfb 476 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 115:87f2f5183dfb 477 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 478 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 115:87f2f5183dfb 479 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 480 } while(0)
Kojto 115:87f2f5183dfb 481
Kojto 115:87f2f5183dfb 482 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto 116:c0f6e94411f5 483 __IO uint32_t tmpreg = 0x00; \
Kojto 115:87f2f5183dfb 484 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 115:87f2f5183dfb 485 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 486 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 115:87f2f5183dfb 487 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 488 } while(0)
Kojto 115:87f2f5183dfb 489
Kojto 115:87f2f5183dfb 490 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 115:87f2f5183dfb 491 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto 115:87f2f5183dfb 492 /**
Kojto 115:87f2f5183dfb 493 * @}
Kojto 115:87f2f5183dfb 494 */
Kojto 115:87f2f5183dfb 495
Kojto 115:87f2f5183dfb 496 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto 115:87f2f5183dfb 497 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 115:87f2f5183dfb 498 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 499 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 500 * using it.
Kojto 115:87f2f5183dfb 501 * @{
Kojto 115:87f2f5183dfb 502 */
Kojto 115:87f2f5183dfb 503 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto 116:c0f6e94411f5 504 __IO uint32_t tmpreg = 0x00; \
Kojto 115:87f2f5183dfb 505 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 115:87f2f5183dfb 506 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 507 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 115:87f2f5183dfb 508 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 509 } while(0)
Kojto 115:87f2f5183dfb 510
Kojto 115:87f2f5183dfb 511 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 115:87f2f5183dfb 512
Kojto 115:87f2f5183dfb 513 /**
Kojto 115:87f2f5183dfb 514 * @}
Kojto 115:87f2f5183dfb 515 */
Kojto 115:87f2f5183dfb 516
Kojto 115:87f2f5183dfb 517 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto 115:87f2f5183dfb 518 * @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto 115:87f2f5183dfb 519 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 520 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 521 * using it.
Kojto 115:87f2f5183dfb 522 * @{
Kojto 115:87f2f5183dfb 523 */
Kojto 115:87f2f5183dfb 524 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto 115:87f2f5183dfb 525 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
Kojto 115:87f2f5183dfb 526
Kojto 115:87f2f5183dfb 527 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto 115:87f2f5183dfb 528 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
Kojto 115:87f2f5183dfb 529 /**
Kojto 115:87f2f5183dfb 530 * @}
Kojto 115:87f2f5183dfb 531 */
Kojto 115:87f2f5183dfb 532
Kojto 115:87f2f5183dfb 533 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto 115:87f2f5183dfb 534 * @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto 115:87f2f5183dfb 535 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 536 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 537 * using it.
Kojto 115:87f2f5183dfb 538 * @{
Kojto 115:87f2f5183dfb 539 */
Kojto 115:87f2f5183dfb 540 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
Kojto 115:87f2f5183dfb 541 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
Kojto 115:87f2f5183dfb 542
Kojto 115:87f2f5183dfb 543 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
Kojto 115:87f2f5183dfb 544 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Kojto 115:87f2f5183dfb 545 /**
Kojto 115:87f2f5183dfb 546 * @}
Kojto 115:87f2f5183dfb 547 */
Kojto 115:87f2f5183dfb 548
Kojto 115:87f2f5183dfb 549 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto 115:87f2f5183dfb 550 * @brief EGet the enable or disable status of the APB2 peripheral clock.
Kojto 115:87f2f5183dfb 551 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 552 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 553 * using it.
Kojto 115:87f2f5183dfb 554 * @{
Kojto 115:87f2f5183dfb 555 */
Kojto 115:87f2f5183dfb 556 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
Kojto 115:87f2f5183dfb 557 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
Kojto 115:87f2f5183dfb 558 /**
Kojto 115:87f2f5183dfb 559 * @}
Kojto 115:87f2f5183dfb 560 */
Kojto 115:87f2f5183dfb 561
Kojto 115:87f2f5183dfb 562 /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
Kojto 115:87f2f5183dfb 563 * @brief Force or release AHB peripheral reset.
Kojto 115:87f2f5183dfb 564 * @{
Kojto 115:87f2f5183dfb 565 */
Kojto 115:87f2f5183dfb 566 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Kojto 115:87f2f5183dfb 567 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
Kojto 115:87f2f5183dfb 568 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
Kojto 115:87f2f5183dfb 569
Kojto 115:87f2f5183dfb 570 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
Kojto 115:87f2f5183dfb 571 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto 115:87f2f5183dfb 572 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Kojto 115:87f2f5183dfb 573 /**
Kojto 115:87f2f5183dfb 574 * @}
Kojto 115:87f2f5183dfb 575 */
Kojto 115:87f2f5183dfb 576
Kojto 115:87f2f5183dfb 577 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto 115:87f2f5183dfb 578 * @brief Force or release APB1 peripheral reset.
Kojto 115:87f2f5183dfb 579 * @{
Kojto 115:87f2f5183dfb 580 */
Kojto 115:87f2f5183dfb 581 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto 115:87f2f5183dfb 582 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 115:87f2f5183dfb 583 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
Kojto 115:87f2f5183dfb 584
Kojto 115:87f2f5183dfb 585 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto 115:87f2f5183dfb 586 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 115:87f2f5183dfb 587 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto 115:87f2f5183dfb 588 /**
Kojto 115:87f2f5183dfb 589 * @}
Kojto 115:87f2f5183dfb 590 */
Kojto 115:87f2f5183dfb 591
Kojto 115:87f2f5183dfb 592 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto 115:87f2f5183dfb 593 * @brief Force or release APB2 peripheral reset.
Kojto 115:87f2f5183dfb 594 * @{
Kojto 115:87f2f5183dfb 595 */
Kojto 115:87f2f5183dfb 596 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto 115:87f2f5183dfb 597 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 115:87f2f5183dfb 598
Kojto 115:87f2f5183dfb 599 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto 115:87f2f5183dfb 600 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 115:87f2f5183dfb 601
Kojto 115:87f2f5183dfb 602 /**
Kojto 115:87f2f5183dfb 603 * @}
Kojto 115:87f2f5183dfb 604 */
Kojto 115:87f2f5183dfb 605
Kojto 115:87f2f5183dfb 606 /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
Kojto 115:87f2f5183dfb 607 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 608 * power consumption.
Kojto 115:87f2f5183dfb 609 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 610 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 611 * @{
Kojto 115:87f2f5183dfb 612 */
Kojto 115:87f2f5183dfb 613 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
Kojto 115:87f2f5183dfb 614 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
Kojto 115:87f2f5183dfb 615
Kojto 115:87f2f5183dfb 616 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto 115:87f2f5183dfb 617 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Kojto 115:87f2f5183dfb 618
Kojto 115:87f2f5183dfb 619 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 620 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 621 * power consumption.
Kojto 115:87f2f5183dfb 622 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 623 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 624 */
Kojto 115:87f2f5183dfb 625 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
Kojto 115:87f2f5183dfb 626 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
Kojto 115:87f2f5183dfb 627
Kojto 115:87f2f5183dfb 628 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto 115:87f2f5183dfb 629 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto 115:87f2f5183dfb 630
Kojto 115:87f2f5183dfb 631 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 632 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 633 * power consumption.
Kojto 115:87f2f5183dfb 634 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 635 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 636 */
Kojto 115:87f2f5183dfb 637 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto 115:87f2f5183dfb 638 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto 115:87f2f5183dfb 639
Kojto 115:87f2f5183dfb 640 /**
Kojto 115:87f2f5183dfb 641 * @}
Kojto 115:87f2f5183dfb 642 */
Kojto 115:87f2f5183dfb 643
Kojto 115:87f2f5183dfb 644 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status
Kojto 115:87f2f5183dfb 645 * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 646 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 647 * power consumption.
Kojto 115:87f2f5183dfb 648 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 649 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 650 * @{
Kojto 115:87f2f5183dfb 651 */
Kojto 115:87f2f5183dfb 652 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
Kojto 115:87f2f5183dfb 653 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
Kojto 115:87f2f5183dfb 654
Kojto 115:87f2f5183dfb 655 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
Kojto 115:87f2f5183dfb 656 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
Kojto 115:87f2f5183dfb 657 /**
Kojto 115:87f2f5183dfb 658 * @}
Kojto 115:87f2f5183dfb 659 */
Kojto 115:87f2f5183dfb 660
Kojto 115:87f2f5183dfb 661 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
Kojto 115:87f2f5183dfb 662 * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 663 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 664 * power consumption.
Kojto 115:87f2f5183dfb 665 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 666 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 667 * @{
Kojto 115:87f2f5183dfb 668 */
Kojto 115:87f2f5183dfb 669 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
Kojto 115:87f2f5183dfb 670 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
Kojto 115:87f2f5183dfb 671
Kojto 115:87f2f5183dfb 672 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
Kojto 115:87f2f5183dfb 673 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
Kojto 115:87f2f5183dfb 674 /**
Kojto 115:87f2f5183dfb 675 * @}
Kojto 115:87f2f5183dfb 676 */
Kojto 115:87f2f5183dfb 677
Kojto 115:87f2f5183dfb 678 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
Kojto 115:87f2f5183dfb 679 * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 680 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 681 * power consumption.
Kojto 115:87f2f5183dfb 682 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 683 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 684 * @{
Kojto 115:87f2f5183dfb 685 */
Kojto 115:87f2f5183dfb 686 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
Kojto 115:87f2f5183dfb 687 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
Kojto 115:87f2f5183dfb 688 /**
Kojto 115:87f2f5183dfb 689 * @}
Kojto 115:87f2f5183dfb 690 */
Kojto 115:87f2f5183dfb 691
Kojto 115:87f2f5183dfb 692 /** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto 115:87f2f5183dfb 693 * @{
Kojto 115:87f2f5183dfb 694 */
Kojto 115:87f2f5183dfb 695
Kojto 115:87f2f5183dfb 696 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto 115:87f2f5183dfb 697 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 115:87f2f5183dfb 698 * It is used (enabled by hardware) as system clock source after startup
Kojto 115:87f2f5183dfb 699 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto 115:87f2f5183dfb 700 * of the HSE used directly or indirectly as system clock (if the Clock
Kojto 115:87f2f5183dfb 701 * Security System CSS is enabled).
Kojto 115:87f2f5183dfb 702 * @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto 115:87f2f5183dfb 703 * you have to select another source of the system clock then stop the HSI.
Kojto 115:87f2f5183dfb 704 * @note After enabling the HSI, the application software should wait on HSIRDY
Kojto 115:87f2f5183dfb 705 * flag to be set indicating that HSI clock is stable and can be used as
Kojto 115:87f2f5183dfb 706 * system clock source.
Kojto 115:87f2f5183dfb 707 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto 115:87f2f5183dfb 708 * clock cycles.
Kojto 115:87f2f5183dfb 709 */
Kojto 115:87f2f5183dfb 710 #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
Kojto 115:87f2f5183dfb 711 #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
Kojto 115:87f2f5183dfb 712
Kojto 115:87f2f5183dfb 713 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto 115:87f2f5183dfb 714 * @note The calibration is used to compensate for the variations in voltage
Kojto 115:87f2f5183dfb 715 * and temperature that influence the frequency of the internal HSI RC.
Kojto 115:87f2f5183dfb 716 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value.
Kojto 115:87f2f5183dfb 717 * This parameter must be a number between 0 and 0x1F.
Kojto 115:87f2f5183dfb 718 */
Kojto 115:87f2f5183dfb 719 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
Kojto 115:87f2f5183dfb 720 RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto 115:87f2f5183dfb 721 /**
Kojto 115:87f2f5183dfb 722 * @}
Kojto 115:87f2f5183dfb 723 */
Kojto 115:87f2f5183dfb 724
Kojto 115:87f2f5183dfb 725 /** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto 115:87f2f5183dfb 726 * @{
Kojto 115:87f2f5183dfb 727 */
Kojto 115:87f2f5183dfb 728
Kojto 115:87f2f5183dfb 729 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto 115:87f2f5183dfb 730 * @note After enabling the LSI, the application software should wait on
Kojto 115:87f2f5183dfb 731 * LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto 115:87f2f5183dfb 732 * be used to clock the IWDG and/or the RTC.
Kojto 115:87f2f5183dfb 733 * @note LSI can not be disabled if the IWDG is running.
Kojto 115:87f2f5183dfb 734 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto 115:87f2f5183dfb 735 * clock cycles.
Kojto 115:87f2f5183dfb 736 */
Kojto 115:87f2f5183dfb 737 #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))
Kojto 115:87f2f5183dfb 738 #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
Kojto 115:87f2f5183dfb 739 /**
Kojto 115:87f2f5183dfb 740 * @}
Kojto 115:87f2f5183dfb 741 */
Kojto 115:87f2f5183dfb 742
Kojto 115:87f2f5183dfb 743 /** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto 115:87f2f5183dfb 744 * @{
Kojto 115:87f2f5183dfb 745 */
Kojto 115:87f2f5183dfb 746 /**
Kojto 115:87f2f5183dfb 747 * @brief Macro to configure the External High Speed oscillator (__HSE__).
Kojto 115:87f2f5183dfb 748 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto 115:87f2f5183dfb 749 * software should wait on HSERDY flag to be set indicating that HSE clock
Kojto 115:87f2f5183dfb 750 * is stable and can be used to clock the PLL and/or system clock.
Kojto 115:87f2f5183dfb 751 * @note HSE state can not be changed if it is used directly or through the
Kojto 115:87f2f5183dfb 752 * PLL as system clock. In this case, you have to select another source
Kojto 115:87f2f5183dfb 753 * of the system clock then change the HSE state (ex. disable it).
Kojto 115:87f2f5183dfb 754 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto 115:87f2f5183dfb 755 * @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto 115:87f2f5183dfb 756 * was previously enabled you have to enable it again after calling this
Kojto 115:87f2f5183dfb 757 * function.
Kojto 115:87f2f5183dfb 758 * @param __STATE__: specifies the new state of the HSE.
Kojto 115:87f2f5183dfb 759 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 760 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto 115:87f2f5183dfb 761 * 6 HSE oscillator clock cycles.
Kojto 115:87f2f5183dfb 762 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
Kojto 115:87f2f5183dfb 763 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
Kojto 115:87f2f5183dfb 764 */
Kojto 115:87f2f5183dfb 765 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto 115:87f2f5183dfb 766 do { \
Kojto 115:87f2f5183dfb 767 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 115:87f2f5183dfb 768 if((__STATE__) == RCC_HSE_ON) \
Kojto 115:87f2f5183dfb 769 { \
Kojto 115:87f2f5183dfb 770 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 115:87f2f5183dfb 771 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 115:87f2f5183dfb 772 } \
Kojto 115:87f2f5183dfb 773 else if((__STATE__) == RCC_HSE_BYPASS) \
Kojto 115:87f2f5183dfb 774 { \
Kojto 115:87f2f5183dfb 775 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 115:87f2f5183dfb 776 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 115:87f2f5183dfb 777 } \
Kojto 115:87f2f5183dfb 778 else \
Kojto 115:87f2f5183dfb 779 { \
Kojto 115:87f2f5183dfb 780 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 115:87f2f5183dfb 781 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 115:87f2f5183dfb 782 } \
Kojto 115:87f2f5183dfb 783 } while(0)
Kojto 115:87f2f5183dfb 784 /**
Kojto 115:87f2f5183dfb 785 * @}
Kojto 115:87f2f5183dfb 786 */
Kojto 115:87f2f5183dfb 787
Kojto 115:87f2f5183dfb 788 /** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto 115:87f2f5183dfb 789 * @{
Kojto 115:87f2f5183dfb 790 */
Kojto 115:87f2f5183dfb 791
Kojto 115:87f2f5183dfb 792 /**
Kojto 115:87f2f5183dfb 793 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 115:87f2f5183dfb 794 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto 115:87f2f5183dfb 795 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Kojto 115:87f2f5183dfb 796 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 115:87f2f5183dfb 797 * this domain after reset, you have to enable write access using
Kojto 115:87f2f5183dfb 798 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 115:87f2f5183dfb 799 * (to be done once after reset).
Kojto 115:87f2f5183dfb 800 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto 115:87f2f5183dfb 801 * software should wait on LSERDY flag to be set indicating that LSE clock
Kojto 115:87f2f5183dfb 802 * is stable and can be used to clock the RTC.
Kojto 115:87f2f5183dfb 803 * @param __STATE__: specifies the new state of the LSE.
Kojto 115:87f2f5183dfb 804 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 805 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto 115:87f2f5183dfb 806 * 6 LSE oscillator clock cycles.
Kojto 115:87f2f5183dfb 807 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto 115:87f2f5183dfb 808 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Kojto 115:87f2f5183dfb 809 */
Kojto 115:87f2f5183dfb 810 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto 115:87f2f5183dfb 811 do { \
Kojto 115:87f2f5183dfb 812 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 115:87f2f5183dfb 813 if((__STATE__) == RCC_LSE_ON) \
Kojto 115:87f2f5183dfb 814 { \
Kojto 115:87f2f5183dfb 815 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 115:87f2f5183dfb 816 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 115:87f2f5183dfb 817 } \
Kojto 115:87f2f5183dfb 818 else if((__STATE__) == RCC_LSE_BYPASS) \
Kojto 115:87f2f5183dfb 819 { \
Kojto 115:87f2f5183dfb 820 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 115:87f2f5183dfb 821 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 115:87f2f5183dfb 822 } \
Kojto 115:87f2f5183dfb 823 else \
Kojto 115:87f2f5183dfb 824 { \
Kojto 115:87f2f5183dfb 825 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 115:87f2f5183dfb 826 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 115:87f2f5183dfb 827 } \
Kojto 115:87f2f5183dfb 828 } while(0)
Kojto 115:87f2f5183dfb 829 /**
Kojto 115:87f2f5183dfb 830 * @}
Kojto 115:87f2f5183dfb 831 */
Kojto 115:87f2f5183dfb 832
Kojto 115:87f2f5183dfb 833 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
Kojto 115:87f2f5183dfb 834 * @{
Kojto 115:87f2f5183dfb 835 */
Kojto 115:87f2f5183dfb 836
Kojto 115:87f2f5183dfb 837 /** @brief Macros to enable or disable the RTC clock.
Kojto 115:87f2f5183dfb 838 * @note These macros must be used only after the RTC clock source was selected.
Kojto 115:87f2f5183dfb 839 */
Kojto 115:87f2f5183dfb 840 #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))
Kojto 115:87f2f5183dfb 841 #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
Kojto 115:87f2f5183dfb 842
Kojto 115:87f2f5183dfb 843 /** @brief Macros to configure the RTC clock (RTCCLK).
Kojto 115:87f2f5183dfb 844 * @note As the RTC clock configuration bits are in the Backup domain and write
Kojto 115:87f2f5183dfb 845 * access is denied to this domain after reset, you have to enable write
Kojto 115:87f2f5183dfb 846 * access using the Power Backup Access macro before to configure
Kojto 115:87f2f5183dfb 847 * the RTC clock source (to be done once after reset).
Kojto 115:87f2f5183dfb 848 * @note Once the RTC clock is configured it can't be changed unless the
Kojto 115:87f2f5183dfb 849 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Kojto 115:87f2f5183dfb 850 * a Power On Reset (POR).
Kojto 115:87f2f5183dfb 851 * @param __RTCCLKSource__: specifies the RTC clock source.
Kojto 115:87f2f5183dfb 852 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 853 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
Kojto 115:87f2f5183dfb 854 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
Kojto 115:87f2f5183dfb 855 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
Kojto 115:87f2f5183dfb 856 * as RTC clock, where x:[2,31]
Kojto 115:87f2f5183dfb 857 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto 115:87f2f5183dfb 858 * work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto 115:87f2f5183dfb 859 * However, when the HSE clock is used as RTC clock source, the RTC
Kojto 115:87f2f5183dfb 860 * cannot be used in STOP and STANDBY modes.
Kojto 115:87f2f5183dfb 861 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto 115:87f2f5183dfb 862 * RTC clock source).
Kojto 115:87f2f5183dfb 863 */
Kojto 115:87f2f5183dfb 864 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
Kojto 115:87f2f5183dfb 865 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
Kojto 115:87f2f5183dfb 866
Kojto 115:87f2f5183dfb 867 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Kojto 115:87f2f5183dfb 868 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
Kojto 115:87f2f5183dfb 869 } while (0)
Kojto 115:87f2f5183dfb 870
Kojto 115:87f2f5183dfb 871 /** @brief Macros to force or release the Backup domain reset.
Kojto 115:87f2f5183dfb 872 * @note This function resets the RTC peripheral (including the backup registers)
Kojto 115:87f2f5183dfb 873 * and the RTC clock source selection in RCC_CSR register.
Kojto 115:87f2f5183dfb 874 * @note The BKPSRAM is not affected by this reset.
Kojto 115:87f2f5183dfb 875 */
Kojto 115:87f2f5183dfb 876 #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))
Kojto 115:87f2f5183dfb 877 #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
Kojto 115:87f2f5183dfb 878 /**
Kojto 115:87f2f5183dfb 879 * @}
Kojto 115:87f2f5183dfb 880 */
Kojto 115:87f2f5183dfb 881
Kojto 115:87f2f5183dfb 882 /** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto 115:87f2f5183dfb 883 * @{
Kojto 115:87f2f5183dfb 884 */
Kojto 115:87f2f5183dfb 885
Kojto 115:87f2f5183dfb 886 /** @brief Macros to enable or disable the main PLL.
Kojto 115:87f2f5183dfb 887 * @note After enabling the main PLL, the application software should wait on
Kojto 115:87f2f5183dfb 888 * PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto 115:87f2f5183dfb 889 * be used as system clock source.
Kojto 115:87f2f5183dfb 890 * @note The main PLL can not be disabled if it is used as system clock source
Kojto 115:87f2f5183dfb 891 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto 115:87f2f5183dfb 892 */
Kojto 115:87f2f5183dfb 893 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Kojto 115:87f2f5183dfb 894 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
Kojto 115:87f2f5183dfb 895
Kojto 115:87f2f5183dfb 896
Kojto 115:87f2f5183dfb 897 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto 115:87f2f5183dfb 898 * @note This function must be used only when the main PLL is disabled.
Kojto 115:87f2f5183dfb 899 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto 115:87f2f5183dfb 900 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 901 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 115:87f2f5183dfb 902 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 115:87f2f5183dfb 903 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto 115:87f2f5183dfb 904 * @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto 115:87f2f5183dfb 905 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 115:87f2f5183dfb 906 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 115:87f2f5183dfb 907 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 115:87f2f5183dfb 908 * of 2 MHz to limit PLL jitter.
Kojto 115:87f2f5183dfb 909 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto 116:c0f6e94411f5 910 * This parameter must be a number between Min_Data = 100 and Max_Data = 432.
Kojto 115:87f2f5183dfb 911 * @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto 116:c0f6e94411f5 912 * output frequency is between 100 and 432 MHz.
Kojto 115:87f2f5183dfb 913 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto 115:87f2f5183dfb 914 * This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto 115:87f2f5183dfb 915 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
Kojto 115:87f2f5183dfb 916 * the System clock frequency.
Kojto 115:87f2f5183dfb 917 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
Kojto 115:87f2f5183dfb 918 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 115:87f2f5183dfb 919 * @note If the USB OTG FS is used in your application, you have to set the
Kojto 115:87f2f5183dfb 920 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto 115:87f2f5183dfb 921 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
Kojto 115:87f2f5183dfb 922 * correctly.
Kojto 115:87f2f5183dfb 923 */
Kojto 115:87f2f5183dfb 924 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
Kojto 115:87f2f5183dfb 925 (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
Kojto 115:87f2f5183dfb 926 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
Kojto 115:87f2f5183dfb 927 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
Kojto 115:87f2f5183dfb 928
Kojto 115:87f2f5183dfb 929 /** @brief Macro to configure the PLL clock source.
Kojto 115:87f2f5183dfb 930 * @note This function must be used only when the main PLL is disabled.
Kojto 115:87f2f5183dfb 931 * @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto 115:87f2f5183dfb 932 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 933 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 115:87f2f5183dfb 934 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 115:87f2f5183dfb 935 *
Kojto 115:87f2f5183dfb 936 */
Kojto 115:87f2f5183dfb 937 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto 115:87f2f5183dfb 938
Kojto 115:87f2f5183dfb 939 /** @brief Macro to configure the PLL multiplication factor.
Kojto 115:87f2f5183dfb 940 * @note This function must be used only when the main PLL is disabled.
Kojto 115:87f2f5183dfb 941 * @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto 115:87f2f5183dfb 942 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 115:87f2f5183dfb 943 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 115:87f2f5183dfb 944 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 115:87f2f5183dfb 945 * of 2 MHz to limit PLL jitter.
Kojto 115:87f2f5183dfb 946 *
Kojto 115:87f2f5183dfb 947 */
Kojto 115:87f2f5183dfb 948 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Kojto 115:87f2f5183dfb 949 /**
Kojto 115:87f2f5183dfb 950 * @}
Kojto 115:87f2f5183dfb 951 */
Kojto 115:87f2f5183dfb 952
Kojto 115:87f2f5183dfb 953 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
Kojto 115:87f2f5183dfb 954 * @{
Kojto 115:87f2f5183dfb 955 */
Kojto 115:87f2f5183dfb 956
Kojto 115:87f2f5183dfb 957 /** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto 115:87f2f5183dfb 958 * @note This function must be called before enabling the I2S APB clock.
Kojto 115:87f2f5183dfb 959 * @param __SOURCE__: specifies the I2S clock source.
Kojto 115:87f2f5183dfb 960 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 961 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
Kojto 115:87f2f5183dfb 962 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto 115:87f2f5183dfb 963 * used as I2S clock source.
Kojto 115:87f2f5183dfb 964 */
Kojto 115:87f2f5183dfb 965 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
Kojto 116:c0f6e94411f5 966 RCC->CFGR |= (__SOURCE__); \
Kojto 116:c0f6e94411f5 967 }while(0)
Kojto 115:87f2f5183dfb 968
Kojto 115:87f2f5183dfb 969 /** @brief Macros to enable or disable the PLLI2S.
Kojto 115:87f2f5183dfb 970 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
Kojto 115:87f2f5183dfb 971 */
Kojto 115:87f2f5183dfb 972 #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
Kojto 115:87f2f5183dfb 973 #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
Kojto 115:87f2f5183dfb 974 /**
Kojto 115:87f2f5183dfb 975 * @}
Kojto 115:87f2f5183dfb 976 */
Kojto 115:87f2f5183dfb 977
Kojto 115:87f2f5183dfb 978 /** @defgroup RCC_Get_Clock_source Get Clock source
Kojto 115:87f2f5183dfb 979 * @{
Kojto 115:87f2f5183dfb 980 */
Kojto 115:87f2f5183dfb 981 /**
Kojto 115:87f2f5183dfb 982 * @brief Macro to configure the system clock source.
Kojto 115:87f2f5183dfb 983 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto 115:87f2f5183dfb 984 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 985 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto 115:87f2f5183dfb 986 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto 115:87f2f5183dfb 987 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto 115:87f2f5183dfb 988 */
Kojto 115:87f2f5183dfb 989 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Kojto 115:87f2f5183dfb 990
Kojto 115:87f2f5183dfb 991 /** @brief Macro to get the clock source used as system clock.
Kojto 115:87f2f5183dfb 992 * @retval The clock source used as system clock. The returned value can be one
Kojto 115:87f2f5183dfb 993 * of the following:
Kojto 115:87f2f5183dfb 994 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto 115:87f2f5183dfb 995 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto 115:87f2f5183dfb 996 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto 115:87f2f5183dfb 997 */
Kojto 115:87f2f5183dfb 998 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto 115:87f2f5183dfb 999
Kojto 115:87f2f5183dfb 1000 /**
Kojto 115:87f2f5183dfb 1001 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
Kojto 115:87f2f5183dfb 1002 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 115:87f2f5183dfb 1003 * this domain after reset, you have to enable write access using
Kojto 115:87f2f5183dfb 1004 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 115:87f2f5183dfb 1005 * (to be done once after reset).
Kojto 115:87f2f5183dfb 1006 * @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.
Kojto 115:87f2f5183dfb 1007 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 1008 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
Kojto 115:87f2f5183dfb 1009 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
Kojto 115:87f2f5183dfb 1010 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
Kojto 115:87f2f5183dfb 1011 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
Kojto 115:87f2f5183dfb 1012 * @retval None
Kojto 115:87f2f5183dfb 1013 */
Kojto 115:87f2f5183dfb 1014 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
Kojto 115:87f2f5183dfb 1015 (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
Kojto 115:87f2f5183dfb 1016
Kojto 115:87f2f5183dfb 1017 /** @brief Macro to get the oscillator used as PLL clock source.
Kojto 115:87f2f5183dfb 1018 * @retval The oscillator used as PLL clock source. The returned value can be one
Kojto 115:87f2f5183dfb 1019 * of the following:
Kojto 115:87f2f5183dfb 1020 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto 115:87f2f5183dfb 1021 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto 115:87f2f5183dfb 1022 */
Kojto 115:87f2f5183dfb 1023 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto 115:87f2f5183dfb 1024 /**
Kojto 115:87f2f5183dfb 1025 * @}
Kojto 115:87f2f5183dfb 1026 */
Kojto 116:c0f6e94411f5 1027
Kojto 116:c0f6e94411f5 1028 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto 116:c0f6e94411f5 1029 * @{
Kojto 116:c0f6e94411f5 1030 */
Kojto 116:c0f6e94411f5 1031
Kojto 116:c0f6e94411f5 1032 /** @brief Macro to configure the MCO1 clock.
Kojto 116:c0f6e94411f5 1033 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 116:c0f6e94411f5 1034 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1035 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
Kojto 116:c0f6e94411f5 1036 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
Kojto 116:c0f6e94411f5 1037 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
Kojto 116:c0f6e94411f5 1038 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
Kojto 116:c0f6e94411f5 1039 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 116:c0f6e94411f5 1040 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1041 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto 116:c0f6e94411f5 1042 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto 116:c0f6e94411f5 1043 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto 116:c0f6e94411f5 1044 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto 116:c0f6e94411f5 1045 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto 116:c0f6e94411f5 1046 */
Kojto 115:87f2f5183dfb 1047
Kojto 116:c0f6e94411f5 1048 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 116:c0f6e94411f5 1049 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Kojto 116:c0f6e94411f5 1050
Kojto 116:c0f6e94411f5 1051 /** @brief Macro to configure the MCO2 clock.
Kojto 116:c0f6e94411f5 1052 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 116:c0f6e94411f5 1053 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1054 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
Kojto 116:c0f6e94411f5 1055 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
Kojto 116:c0f6e94411f5 1056 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
Kojto 116:c0f6e94411f5 1057 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
Kojto 116:c0f6e94411f5 1058 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 116:c0f6e94411f5 1059 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1060 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto 116:c0f6e94411f5 1061 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto 116:c0f6e94411f5 1062 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto 116:c0f6e94411f5 1063 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto 116:c0f6e94411f5 1064 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto 116:c0f6e94411f5 1065 */
Kojto 116:c0f6e94411f5 1066
Kojto 116:c0f6e94411f5 1067 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 116:c0f6e94411f5 1068 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
Kojto 116:c0f6e94411f5 1069 /**
Kojto 116:c0f6e94411f5 1070 * @}
Kojto 116:c0f6e94411f5 1071 */
Kojto 116:c0f6e94411f5 1072
Kojto 115:87f2f5183dfb 1073 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto 115:87f2f5183dfb 1074 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 115:87f2f5183dfb 1075 * @{
Kojto 115:87f2f5183dfb 1076 */
Kojto 115:87f2f5183dfb 1077
Kojto 115:87f2f5183dfb 1078 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto 115:87f2f5183dfb 1079 * the selected interrupts).
Kojto 115:87f2f5183dfb 1080 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto 115:87f2f5183dfb 1081 * This parameter can be any combination of the following values:
Kojto 115:87f2f5183dfb 1082 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 115:87f2f5183dfb 1083 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 115:87f2f5183dfb 1084 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 115:87f2f5183dfb 1085 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 115:87f2f5183dfb 1086 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 115:87f2f5183dfb 1087 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 115:87f2f5183dfb 1088 */
Kojto 115:87f2f5183dfb 1089 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Kojto 115:87f2f5183dfb 1090
Kojto 115:87f2f5183dfb 1091 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto 115:87f2f5183dfb 1092 * the selected interrupts).
Kojto 115:87f2f5183dfb 1093 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto 115:87f2f5183dfb 1094 * This parameter can be any combination of the following values:
Kojto 115:87f2f5183dfb 1095 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 115:87f2f5183dfb 1096 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 115:87f2f5183dfb 1097 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 115:87f2f5183dfb 1098 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 115:87f2f5183dfb 1099 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 115:87f2f5183dfb 1100 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 115:87f2f5183dfb 1101 */
Kojto 115:87f2f5183dfb 1102 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto 115:87f2f5183dfb 1103
Kojto 115:87f2f5183dfb 1104 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto 115:87f2f5183dfb 1105 * bits to clear the selected interrupt pending bits.
Kojto 115:87f2f5183dfb 1106 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto 115:87f2f5183dfb 1107 * This parameter can be any combination of the following values:
Kojto 115:87f2f5183dfb 1108 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 115:87f2f5183dfb 1109 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 115:87f2f5183dfb 1110 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 115:87f2f5183dfb 1111 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 115:87f2f5183dfb 1112 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 115:87f2f5183dfb 1113 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 115:87f2f5183dfb 1114 * @arg RCC_IT_CSS: Clock Security System interrupt
Kojto 115:87f2f5183dfb 1115 */
Kojto 115:87f2f5183dfb 1116 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Kojto 115:87f2f5183dfb 1117
Kojto 115:87f2f5183dfb 1118 /** @brief Check the RCC's interrupt has occurred or not.
Kojto 115:87f2f5183dfb 1119 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto 115:87f2f5183dfb 1120 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 1121 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 115:87f2f5183dfb 1122 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 115:87f2f5183dfb 1123 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 115:87f2f5183dfb 1124 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 115:87f2f5183dfb 1125 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 115:87f2f5183dfb 1126 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 115:87f2f5183dfb 1127 * @arg RCC_IT_CSS: Clock Security System interrupt
Kojto 115:87f2f5183dfb 1128 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto 115:87f2f5183dfb 1129 */
Kojto 115:87f2f5183dfb 1130 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto 115:87f2f5183dfb 1131
Kojto 115:87f2f5183dfb 1132 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
Kojto 115:87f2f5183dfb 1133 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
Kojto 115:87f2f5183dfb 1134 */
Kojto 115:87f2f5183dfb 1135 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Kojto 115:87f2f5183dfb 1136
Kojto 115:87f2f5183dfb 1137 /** @brief Check RCC flag is set or not.
Kojto 115:87f2f5183dfb 1138 * @param __FLAG__: specifies the flag to check.
Kojto 115:87f2f5183dfb 1139 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 1140 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto 115:87f2f5183dfb 1141 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto 115:87f2f5183dfb 1142 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Kojto 115:87f2f5183dfb 1143 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
Kojto 115:87f2f5183dfb 1144 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto 115:87f2f5183dfb 1145 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Kojto 115:87f2f5183dfb 1146 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
Kojto 115:87f2f5183dfb 1147 * @arg RCC_FLAG_PINRST: Pin reset.
Kojto 115:87f2f5183dfb 1148 * @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto 115:87f2f5183dfb 1149 * @arg RCC_FLAG_SFTRST: Software reset.
Kojto 115:87f2f5183dfb 1150 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto 115:87f2f5183dfb 1151 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto 115:87f2f5183dfb 1152 * @arg RCC_FLAG_LPWRRST: Low Power reset.
Kojto 115:87f2f5183dfb 1153 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 115:87f2f5183dfb 1154 */
Kojto 115:87f2f5183dfb 1155 #define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto 115:87f2f5183dfb 1156 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
Kojto 115:87f2f5183dfb 1157
Kojto 115:87f2f5183dfb 1158 /**
Kojto 115:87f2f5183dfb 1159 * @}
Kojto 115:87f2f5183dfb 1160 */
Kojto 115:87f2f5183dfb 1161
Kojto 115:87f2f5183dfb 1162 /**
Kojto 115:87f2f5183dfb 1163 * @}
Kojto 115:87f2f5183dfb 1164 */
Kojto 115:87f2f5183dfb 1165
Kojto 115:87f2f5183dfb 1166 /* Include RCC HAL Extension module */
Kojto 115:87f2f5183dfb 1167 #include "stm32f7xx_hal_rcc_ex.h"
Kojto 115:87f2f5183dfb 1168
Kojto 115:87f2f5183dfb 1169 /* Exported functions --------------------------------------------------------*/
Kojto 115:87f2f5183dfb 1170 /** @addtogroup RCC_Exported_Functions
Kojto 115:87f2f5183dfb 1171 * @{
Kojto 115:87f2f5183dfb 1172 */
Kojto 115:87f2f5183dfb 1173
Kojto 115:87f2f5183dfb 1174 /** @addtogroup RCC_Exported_Functions_Group1
Kojto 115:87f2f5183dfb 1175 * @{
Kojto 115:87f2f5183dfb 1176 */
Kojto 115:87f2f5183dfb 1177 /* Initialization and de-initialization functions ******************************/
Kojto 115:87f2f5183dfb 1178 void HAL_RCC_DeInit(void);
Kojto 115:87f2f5183dfb 1179 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 115:87f2f5183dfb 1180 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 115:87f2f5183dfb 1181 /**
Kojto 115:87f2f5183dfb 1182 * @}
Kojto 115:87f2f5183dfb 1183 */
Kojto 115:87f2f5183dfb 1184
Kojto 115:87f2f5183dfb 1185 /** @addtogroup RCC_Exported_Functions_Group2
Kojto 115:87f2f5183dfb 1186 * @{
Kojto 115:87f2f5183dfb 1187 */
Kojto 115:87f2f5183dfb 1188 /* Peripheral Control functions ************************************************/
Kojto 115:87f2f5183dfb 1189 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto 115:87f2f5183dfb 1190 void HAL_RCC_EnableCSS(void);
Kojto 115:87f2f5183dfb 1191 void HAL_RCC_DisableCSS(void);
Kojto 115:87f2f5183dfb 1192 uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto 115:87f2f5183dfb 1193 uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto 115:87f2f5183dfb 1194 uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto 115:87f2f5183dfb 1195 uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto 115:87f2f5183dfb 1196 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 115:87f2f5183dfb 1197 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
Kojto 115:87f2f5183dfb 1198
Kojto 115:87f2f5183dfb 1199 /* CSS NMI IRQ handler */
Kojto 115:87f2f5183dfb 1200 void HAL_RCC_NMI_IRQHandler(void);
Kojto 115:87f2f5183dfb 1201
Kojto 115:87f2f5183dfb 1202 /* User Callbacks in non blocking mode (IT mode) */
Kojto 115:87f2f5183dfb 1203 void HAL_RCC_CSSCallback(void);
Kojto 115:87f2f5183dfb 1204 /**
Kojto 115:87f2f5183dfb 1205 * @}
Kojto 115:87f2f5183dfb 1206 */
Kojto 115:87f2f5183dfb 1207
Kojto 115:87f2f5183dfb 1208 /**
Kojto 115:87f2f5183dfb 1209 * @}
Kojto 115:87f2f5183dfb 1210 */
Kojto 115:87f2f5183dfb 1211
Kojto 115:87f2f5183dfb 1212 /* Private types -------------------------------------------------------------*/
Kojto 115:87f2f5183dfb 1213 /* Private variables ---------------------------------------------------------*/
Kojto 115:87f2f5183dfb 1214 /* Private constants ---------------------------------------------------------*/
Kojto 115:87f2f5183dfb 1215 /** @defgroup RCC_Private_Constants RCC Private Constants
Kojto 115:87f2f5183dfb 1216 * @{
Kojto 115:87f2f5183dfb 1217 */
Kojto 115:87f2f5183dfb 1218 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto 115:87f2f5183dfb 1219 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 115:87f2f5183dfb 1220 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 115:87f2f5183dfb 1221 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 115:87f2f5183dfb 1222 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
Kojto 115:87f2f5183dfb 1223
Kojto 115:87f2f5183dfb 1224 /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
Kojto 115:87f2f5183dfb 1225 * @brief RCC registers bit address alias
Kojto 115:87f2f5183dfb 1226 * @{
Kojto 115:87f2f5183dfb 1227 */
Kojto 115:87f2f5183dfb 1228 /* CIR register byte 2 (Bits[15:8]) base address */
Kojto 115:87f2f5183dfb 1229 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
Kojto 115:87f2f5183dfb 1230
Kojto 115:87f2f5183dfb 1231 /* CIR register byte 3 (Bits[23:16]) base address */
Kojto 115:87f2f5183dfb 1232 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
Kojto 115:87f2f5183dfb 1233
Kojto 115:87f2f5183dfb 1234 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto 115:87f2f5183dfb 1235 #define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
Kojto 115:87f2f5183dfb 1236 /**
Kojto 115:87f2f5183dfb 1237 * @}
Kojto 115:87f2f5183dfb 1238 */
Kojto 115:87f2f5183dfb 1239 /**
Kojto 115:87f2f5183dfb 1240 * @}
Kojto 115:87f2f5183dfb 1241 */
Kojto 115:87f2f5183dfb 1242
Kojto 115:87f2f5183dfb 1243 /* Private macros ------------------------------------------------------------*/
Kojto 115:87f2f5183dfb 1244 /** @addtogroup RCC_Private_Macros RCC Private Macros
Kojto 115:87f2f5183dfb 1245 * @{
Kojto 115:87f2f5183dfb 1246 */
Kojto 115:87f2f5183dfb 1247
Kojto 115:87f2f5183dfb 1248 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto 115:87f2f5183dfb 1249 * @{
Kojto 115:87f2f5183dfb 1250 */
Kojto 115:87f2f5183dfb 1251 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
Kojto 115:87f2f5183dfb 1252
Kojto 115:87f2f5183dfb 1253 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
Kojto 115:87f2f5183dfb 1254 ((HSE) == RCC_HSE_BYPASS))
Kojto 115:87f2f5183dfb 1255
Kojto 115:87f2f5183dfb 1256 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
Kojto 115:87f2f5183dfb 1257 ((LSE) == RCC_LSE_BYPASS))
Kojto 115:87f2f5183dfb 1258
Kojto 115:87f2f5183dfb 1259 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
Kojto 115:87f2f5183dfb 1260
Kojto 115:87f2f5183dfb 1261 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
Kojto 115:87f2f5183dfb 1262
Kojto 115:87f2f5183dfb 1263 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
Kojto 115:87f2f5183dfb 1264
Kojto 115:87f2f5183dfb 1265 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 115:87f2f5183dfb 1266 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 115:87f2f5183dfb 1267
Kojto 115:87f2f5183dfb 1268 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 115:87f2f5183dfb 1269 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 115:87f2f5183dfb 1270 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto 115:87f2f5183dfb 1271 #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
Kojto 115:87f2f5183dfb 1272
Kojto 116:c0f6e94411f5 1273 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
Kojto 115:87f2f5183dfb 1274
Kojto 115:87f2f5183dfb 1275 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
Kojto 115:87f2f5183dfb 1276 ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
Kojto 115:87f2f5183dfb 1277 #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto 115:87f2f5183dfb 1278
Kojto 115:87f2f5183dfb 1279 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
Kojto 115:87f2f5183dfb 1280 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
Kojto 115:87f2f5183dfb 1281 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
Kojto 115:87f2f5183dfb 1282 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
Kojto 115:87f2f5183dfb 1283 ((HCLK) == RCC_SYSCLK_DIV512))
Kojto 115:87f2f5183dfb 1284
Kojto 115:87f2f5183dfb 1285 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
Kojto 115:87f2f5183dfb 1286
Kojto 115:87f2f5183dfb 1287 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
Kojto 115:87f2f5183dfb 1288 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
Kojto 115:87f2f5183dfb 1289 ((PCLK) == RCC_HCLK_DIV16))
Kojto 115:87f2f5183dfb 1290
Kojto 115:87f2f5183dfb 1291 #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
Kojto 115:87f2f5183dfb 1292
Kojto 115:87f2f5183dfb 1293
Kojto 115:87f2f5183dfb 1294 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
Kojto 115:87f2f5183dfb 1295 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Kojto 115:87f2f5183dfb 1296
Kojto 115:87f2f5183dfb 1297 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
Kojto 115:87f2f5183dfb 1298 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto 115:87f2f5183dfb 1299
Kojto 115:87f2f5183dfb 1300 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
Kojto 115:87f2f5183dfb 1301 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
Kojto 115:87f2f5183dfb 1302 ((DIV) == RCC_MCODIV_5))
Kojto 115:87f2f5183dfb 1303 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
Kojto 115:87f2f5183dfb 1304
Kojto 115:87f2f5183dfb 1305 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
Kojto 115:87f2f5183dfb 1306 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
Kojto 115:87f2f5183dfb 1307 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
Kojto 115:87f2f5183dfb 1308 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
Kojto 115:87f2f5183dfb 1309 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
Kojto 115:87f2f5183dfb 1310 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
Kojto 115:87f2f5183dfb 1311 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
Kojto 115:87f2f5183dfb 1312 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
Kojto 115:87f2f5183dfb 1313 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
Kojto 115:87f2f5183dfb 1314 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
Kojto 115:87f2f5183dfb 1315 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
Kojto 115:87f2f5183dfb 1316 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
Kojto 115:87f2f5183dfb 1317 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
Kojto 115:87f2f5183dfb 1318 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
Kojto 115:87f2f5183dfb 1319 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
Kojto 115:87f2f5183dfb 1320 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
Kojto 115:87f2f5183dfb 1321
Kojto 115:87f2f5183dfb 1322
Kojto 115:87f2f5183dfb 1323 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \
Kojto 116:c0f6e94411f5 1324 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \
Kojto 116:c0f6e94411f5 1325 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
Kojto 116:c0f6e94411f5 1326 ((DRIVE) == RCC_LSEDRIVE_HIGH))
Kojto 115:87f2f5183dfb 1327 /**
Kojto 115:87f2f5183dfb 1328 * @}
Kojto 115:87f2f5183dfb 1329 */
Kojto 115:87f2f5183dfb 1330
Kojto 115:87f2f5183dfb 1331 /**
Kojto 115:87f2f5183dfb 1332 * @}
Kojto 115:87f2f5183dfb 1333 */
Kojto 115:87f2f5183dfb 1334
Kojto 115:87f2f5183dfb 1335 /**
Kojto 115:87f2f5183dfb 1336 * @}
Kojto 115:87f2f5183dfb 1337 */
Kojto 115:87f2f5183dfb 1338
Kojto 115:87f2f5183dfb 1339 /**
Kojto 115:87f2f5183dfb 1340 * @}
Kojto 115:87f2f5183dfb 1341 */
Kojto 115:87f2f5183dfb 1342
Kojto 115:87f2f5183dfb 1343 #ifdef __cplusplus
Kojto 115:87f2f5183dfb 1344 }
Kojto 115:87f2f5183dfb 1345 #endif
Kojto 115:87f2f5183dfb 1346
Kojto 115:87f2f5183dfb 1347 #endif /* __STM32F7xx_HAL_RCC_H */
Kojto 115:87f2f5183dfb 1348
Kojto 115:87f2f5183dfb 1349 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/