Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_NUCLEO_F446RE/core_caFunc.h@106:ba1f97679dad, 2015-09-02 (annotated)

Committer:
Kojto
Date:
Wed Sep 02 14:17:43 2015 +0100
Revision:
106:ba1f97679dad
Child:
108:34e6b704fe68
Release 106  of the mbed library



Changes:

- new platform - Nucleo F446RE

- STM32F4 Cube driver update v2.3.2

- ST cmsis driver v2.3.2

- nordic bugfix gcc linker start address

- lpc11u68 - bugfix for serial ports

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 106:ba1f97679dad 1 /**************************************************************************//**
Kojto 106:ba1f97679dad 2 * @file core_caFunc.h
Kojto 106:ba1f97679dad 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 106:ba1f97679dad 4 * @version V3.10
Kojto 106:ba1f97679dad 5 * @date 9 May 2013
Kojto 106:ba1f97679dad 6 *
Kojto 106:ba1f97679dad 7 * @note
Kojto 106:ba1f97679dad 8 *
Kojto 106:ba1f97679dad 9 ******************************************************************************/
Kojto 106:ba1f97679dad 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
Kojto 106:ba1f97679dad 11
Kojto 106:ba1f97679dad 12 All rights reserved.
Kojto 106:ba1f97679dad 13 Redistribution and use in source and binary forms, with or without
Kojto 106:ba1f97679dad 14 modification, are permitted provided that the following conditions are met:
Kojto 106:ba1f97679dad 15 - Redistributions of source code must retain the above copyright
Kojto 106:ba1f97679dad 16 notice, this list of conditions and the following disclaimer.
Kojto 106:ba1f97679dad 17 - Redistributions in binary form must reproduce the above copyright
Kojto 106:ba1f97679dad 18 notice, this list of conditions and the following disclaimer in the
Kojto 106:ba1f97679dad 19 documentation and/or other materials provided with the distribution.
Kojto 106:ba1f97679dad 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 106:ba1f97679dad 21 to endorse or promote products derived from this software without
Kojto 106:ba1f97679dad 22 specific prior written permission.
Kojto 106:ba1f97679dad 23 *
Kojto 106:ba1f97679dad 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 106:ba1f97679dad 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 106:ba1f97679dad 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 106:ba1f97679dad 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 106:ba1f97679dad 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 106:ba1f97679dad 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 106:ba1f97679dad 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 106:ba1f97679dad 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 106:ba1f97679dad 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 106:ba1f97679dad 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 106:ba1f97679dad 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 106:ba1f97679dad 35 ---------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 36
Kojto 106:ba1f97679dad 37
Kojto 106:ba1f97679dad 38 #ifndef __CORE_CAFUNC_H__
Kojto 106:ba1f97679dad 39 #define __CORE_CAFUNC_H__
Kojto 106:ba1f97679dad 40
Kojto 106:ba1f97679dad 41
Kojto 106:ba1f97679dad 42 /* ########################### Core Function Access ########################### */
Kojto 106:ba1f97679dad 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 106:ba1f97679dad 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 106:ba1f97679dad 45 @{
Kojto 106:ba1f97679dad 46 */
Kojto 106:ba1f97679dad 47
Kojto 106:ba1f97679dad 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 106:ba1f97679dad 49 /* ARM armcc specific functions */
Kojto 106:ba1f97679dad 50
Kojto 106:ba1f97679dad 51 #if (__ARMCC_VERSION < 400677)
Kojto 106:ba1f97679dad 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 106:ba1f97679dad 53 #endif
Kojto 106:ba1f97679dad 54
Kojto 106:ba1f97679dad 55 #define MODE_USR 0x10
Kojto 106:ba1f97679dad 56 #define MODE_FIQ 0x11
Kojto 106:ba1f97679dad 57 #define MODE_IRQ 0x12
Kojto 106:ba1f97679dad 58 #define MODE_SVC 0x13
Kojto 106:ba1f97679dad 59 #define MODE_MON 0x16
Kojto 106:ba1f97679dad 60 #define MODE_ABT 0x17
Kojto 106:ba1f97679dad 61 #define MODE_HYP 0x1A
Kojto 106:ba1f97679dad 62 #define MODE_UND 0x1B
Kojto 106:ba1f97679dad 63 #define MODE_SYS 0x1F
Kojto 106:ba1f97679dad 64
Kojto 106:ba1f97679dad 65 /** \brief Get APSR Register
Kojto 106:ba1f97679dad 66
Kojto 106:ba1f97679dad 67 This function returns the content of the APSR Register.
Kojto 106:ba1f97679dad 68
Kojto 106:ba1f97679dad 69 \return APSR Register value
Kojto 106:ba1f97679dad 70 */
Kojto 106:ba1f97679dad 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 106:ba1f97679dad 72 {
Kojto 106:ba1f97679dad 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 106:ba1f97679dad 74 return(__regAPSR);
Kojto 106:ba1f97679dad 75 }
Kojto 106:ba1f97679dad 76
Kojto 106:ba1f97679dad 77
Kojto 106:ba1f97679dad 78 /** \brief Get CPSR Register
Kojto 106:ba1f97679dad 79
Kojto 106:ba1f97679dad 80 This function returns the content of the CPSR Register.
Kojto 106:ba1f97679dad 81
Kojto 106:ba1f97679dad 82 \return CPSR Register value
Kojto 106:ba1f97679dad 83 */
Kojto 106:ba1f97679dad 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 106:ba1f97679dad 85 {
Kojto 106:ba1f97679dad 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 106:ba1f97679dad 87 return(__regCPSR);
Kojto 106:ba1f97679dad 88 }
Kojto 106:ba1f97679dad 89
Kojto 106:ba1f97679dad 90 /** \brief Set Stack Pointer
Kojto 106:ba1f97679dad 91
Kojto 106:ba1f97679dad 92 This function assigns the given value to the current stack pointer.
Kojto 106:ba1f97679dad 93
Kojto 106:ba1f97679dad 94 \param [in] topOfStack Stack Pointer value to set
Kojto 106:ba1f97679dad 95 */
Kojto 106:ba1f97679dad 96 register uint32_t __regSP __ASM("sp");
Kojto 106:ba1f97679dad 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 106:ba1f97679dad 98 {
Kojto 106:ba1f97679dad 99 __regSP = topOfStack;
Kojto 106:ba1f97679dad 100 }
Kojto 106:ba1f97679dad 101
Kojto 106:ba1f97679dad 102
Kojto 106:ba1f97679dad 103 /** \brief Get link register
Kojto 106:ba1f97679dad 104
Kojto 106:ba1f97679dad 105 This function returns the value of the link register
Kojto 106:ba1f97679dad 106
Kojto 106:ba1f97679dad 107 \return Value of link register
Kojto 106:ba1f97679dad 108 */
Kojto 106:ba1f97679dad 109 register uint32_t __reglr __ASM("lr");
Kojto 106:ba1f97679dad 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 106:ba1f97679dad 111 {
Kojto 106:ba1f97679dad 112 return(__reglr);
Kojto 106:ba1f97679dad 113 }
Kojto 106:ba1f97679dad 114
Kojto 106:ba1f97679dad 115 /** \brief Set link register
Kojto 106:ba1f97679dad 116
Kojto 106:ba1f97679dad 117 This function sets the value of the link register
Kojto 106:ba1f97679dad 118
Kojto 106:ba1f97679dad 119 \param [in] lr LR value to set
Kojto 106:ba1f97679dad 120 */
Kojto 106:ba1f97679dad 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 106:ba1f97679dad 122 {
Kojto 106:ba1f97679dad 123 __reglr = lr;
Kojto 106:ba1f97679dad 124 }
Kojto 106:ba1f97679dad 125
Kojto 106:ba1f97679dad 126 /** \brief Set Process Stack Pointer
Kojto 106:ba1f97679dad 127
Kojto 106:ba1f97679dad 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 106:ba1f97679dad 129
Kojto 106:ba1f97679dad 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 106:ba1f97679dad 131 */
Kojto 106:ba1f97679dad 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 106:ba1f97679dad 133 {
Kojto 106:ba1f97679dad 134 ARM
Kojto 106:ba1f97679dad 135 PRESERVE8
Kojto 106:ba1f97679dad 136
Kojto 106:ba1f97679dad 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 106:ba1f97679dad 138 MRS R1, CPSR
Kojto 106:ba1f97679dad 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 106:ba1f97679dad 140 MOV SP, R0
Kojto 106:ba1f97679dad 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 106:ba1f97679dad 142 ISB
Kojto 106:ba1f97679dad 143 BX LR
Kojto 106:ba1f97679dad 144
Kojto 106:ba1f97679dad 145 }
Kojto 106:ba1f97679dad 146
Kojto 106:ba1f97679dad 147 /** \brief Set User Mode
Kojto 106:ba1f97679dad 148
Kojto 106:ba1f97679dad 149 This function changes the processor state to User Mode
Kojto 106:ba1f97679dad 150
Kojto 106:ba1f97679dad 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 106:ba1f97679dad 152 */
Kojto 106:ba1f97679dad 153 __STATIC_ASM void __set_CPS_USR(void)
Kojto 106:ba1f97679dad 154 {
Kojto 106:ba1f97679dad 155 ARM
Kojto 106:ba1f97679dad 156
Kojto 106:ba1f97679dad 157 CPS #MODE_USR
Kojto 106:ba1f97679dad 158 BX LR
Kojto 106:ba1f97679dad 159 }
Kojto 106:ba1f97679dad 160
Kojto 106:ba1f97679dad 161
Kojto 106:ba1f97679dad 162 /** \brief Enable FIQ
Kojto 106:ba1f97679dad 163
Kojto 106:ba1f97679dad 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 106:ba1f97679dad 165 Can only be executed in Privileged modes.
Kojto 106:ba1f97679dad 166 */
Kojto 106:ba1f97679dad 167 #define __enable_fault_irq __enable_fiq
Kojto 106:ba1f97679dad 168
Kojto 106:ba1f97679dad 169
Kojto 106:ba1f97679dad 170 /** \brief Disable FIQ
Kojto 106:ba1f97679dad 171
Kojto 106:ba1f97679dad 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 106:ba1f97679dad 173 Can only be executed in Privileged modes.
Kojto 106:ba1f97679dad 174 */
Kojto 106:ba1f97679dad 175 #define __disable_fault_irq __disable_fiq
Kojto 106:ba1f97679dad 176
Kojto 106:ba1f97679dad 177
Kojto 106:ba1f97679dad 178 /** \brief Get FPSCR
Kojto 106:ba1f97679dad 179
Kojto 106:ba1f97679dad 180 This function returns the current value of the Floating Point Status/Control register.
Kojto 106:ba1f97679dad 181
Kojto 106:ba1f97679dad 182 \return Floating Point Status/Control register value
Kojto 106:ba1f97679dad 183 */
Kojto 106:ba1f97679dad 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 106:ba1f97679dad 185 {
Kojto 106:ba1f97679dad 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 106:ba1f97679dad 187 register uint32_t __regfpscr __ASM("fpscr");
Kojto 106:ba1f97679dad 188 return(__regfpscr);
Kojto 106:ba1f97679dad 189 #else
Kojto 106:ba1f97679dad 190 return(0);
Kojto 106:ba1f97679dad 191 #endif
Kojto 106:ba1f97679dad 192 }
Kojto 106:ba1f97679dad 193
Kojto 106:ba1f97679dad 194
Kojto 106:ba1f97679dad 195 /** \brief Set FPSCR
Kojto 106:ba1f97679dad 196
Kojto 106:ba1f97679dad 197 This function assigns the given value to the Floating Point Status/Control register.
Kojto 106:ba1f97679dad 198
Kojto 106:ba1f97679dad 199 \param [in] fpscr Floating Point Status/Control value to set
Kojto 106:ba1f97679dad 200 */
Kojto 106:ba1f97679dad 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 106:ba1f97679dad 202 {
Kojto 106:ba1f97679dad 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 106:ba1f97679dad 204 register uint32_t __regfpscr __ASM("fpscr");
Kojto 106:ba1f97679dad 205 __regfpscr = (fpscr);
Kojto 106:ba1f97679dad 206 #endif
Kojto 106:ba1f97679dad 207 }
Kojto 106:ba1f97679dad 208
Kojto 106:ba1f97679dad 209 /** \brief Get FPEXC
Kojto 106:ba1f97679dad 210
Kojto 106:ba1f97679dad 211 This function returns the current value of the Floating Point Exception Control register.
Kojto 106:ba1f97679dad 212
Kojto 106:ba1f97679dad 213 \return Floating Point Exception Control register value
Kojto 106:ba1f97679dad 214 */
Kojto 106:ba1f97679dad 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 106:ba1f97679dad 216 {
Kojto 106:ba1f97679dad 217 #if (__FPU_PRESENT == 1)
Kojto 106:ba1f97679dad 218 register uint32_t __regfpexc __ASM("fpexc");
Kojto 106:ba1f97679dad 219 return(__regfpexc);
Kojto 106:ba1f97679dad 220 #else
Kojto 106:ba1f97679dad 221 return(0);
Kojto 106:ba1f97679dad 222 #endif
Kojto 106:ba1f97679dad 223 }
Kojto 106:ba1f97679dad 224
Kojto 106:ba1f97679dad 225
Kojto 106:ba1f97679dad 226 /** \brief Set FPEXC
Kojto 106:ba1f97679dad 227
Kojto 106:ba1f97679dad 228 This function assigns the given value to the Floating Point Exception Control register.
Kojto 106:ba1f97679dad 229
Kojto 106:ba1f97679dad 230 \param [in] fpscr Floating Point Exception Control value to set
Kojto 106:ba1f97679dad 231 */
Kojto 106:ba1f97679dad 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 106:ba1f97679dad 233 {
Kojto 106:ba1f97679dad 234 #if (__FPU_PRESENT == 1)
Kojto 106:ba1f97679dad 235 register uint32_t __regfpexc __ASM("fpexc");
Kojto 106:ba1f97679dad 236 __regfpexc = (fpexc);
Kojto 106:ba1f97679dad 237 #endif
Kojto 106:ba1f97679dad 238 }
Kojto 106:ba1f97679dad 239
Kojto 106:ba1f97679dad 240 /** \brief Get CPACR
Kojto 106:ba1f97679dad 241
Kojto 106:ba1f97679dad 242 This function returns the current value of the Coprocessor Access Control register.
Kojto 106:ba1f97679dad 243
Kojto 106:ba1f97679dad 244 \return Coprocessor Access Control register value
Kojto 106:ba1f97679dad 245 */
Kojto 106:ba1f97679dad 246 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 106:ba1f97679dad 247 {
Kojto 106:ba1f97679dad 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 106:ba1f97679dad 249 return __regCPACR;
Kojto 106:ba1f97679dad 250 }
Kojto 106:ba1f97679dad 251
Kojto 106:ba1f97679dad 252 /** \brief Set CPACR
Kojto 106:ba1f97679dad 253
Kojto 106:ba1f97679dad 254 This function assigns the given value to the Coprocessor Access Control register.
Kojto 106:ba1f97679dad 255
Kojto 106:ba1f97679dad 256 \param [in] cpacr Coporcessor Acccess Control value to set
Kojto 106:ba1f97679dad 257 */
Kojto 106:ba1f97679dad 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 106:ba1f97679dad 259 {
Kojto 106:ba1f97679dad 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 106:ba1f97679dad 261 __regCPACR = cpacr;
Kojto 106:ba1f97679dad 262 __ISB();
Kojto 106:ba1f97679dad 263 }
Kojto 106:ba1f97679dad 264
Kojto 106:ba1f97679dad 265 /** \brief Get CBAR
Kojto 106:ba1f97679dad 266
Kojto 106:ba1f97679dad 267 This function returns the value of the Configuration Base Address register.
Kojto 106:ba1f97679dad 268
Kojto 106:ba1f97679dad 269 \return Configuration Base Address register value
Kojto 106:ba1f97679dad 270 */
Kojto 106:ba1f97679dad 271 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 106:ba1f97679dad 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 106:ba1f97679dad 273 return(__regCBAR);
Kojto 106:ba1f97679dad 274 }
Kojto 106:ba1f97679dad 275
Kojto 106:ba1f97679dad 276 /** \brief Get TTBR0
Kojto 106:ba1f97679dad 277
Kojto 106:ba1f97679dad 278 This function returns the value of the Configuration Base Address register.
Kojto 106:ba1f97679dad 279
Kojto 106:ba1f97679dad 280 \return Translation Table Base Register 0 value
Kojto 106:ba1f97679dad 281 */
Kojto 106:ba1f97679dad 282 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 106:ba1f97679dad 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 106:ba1f97679dad 284 return(__regTTBR0);
Kojto 106:ba1f97679dad 285 }
Kojto 106:ba1f97679dad 286
Kojto 106:ba1f97679dad 287 /** \brief Set TTBR0
Kojto 106:ba1f97679dad 288
Kojto 106:ba1f97679dad 289 This function assigns the given value to the Coprocessor Access Control register.
Kojto 106:ba1f97679dad 290
Kojto 106:ba1f97679dad 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 106:ba1f97679dad 292 */
Kojto 106:ba1f97679dad 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 106:ba1f97679dad 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 106:ba1f97679dad 295 __regTTBR0 = ttbr0;
Kojto 106:ba1f97679dad 296 __ISB();
Kojto 106:ba1f97679dad 297 }
Kojto 106:ba1f97679dad 298
Kojto 106:ba1f97679dad 299 /** \brief Get DACR
Kojto 106:ba1f97679dad 300
Kojto 106:ba1f97679dad 301 This function returns the value of the Domain Access Control Register.
Kojto 106:ba1f97679dad 302
Kojto 106:ba1f97679dad 303 \return Domain Access Control Register value
Kojto 106:ba1f97679dad 304 */
Kojto 106:ba1f97679dad 305 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 106:ba1f97679dad 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 106:ba1f97679dad 307 return(__regDACR);
Kojto 106:ba1f97679dad 308 }
Kojto 106:ba1f97679dad 309
Kojto 106:ba1f97679dad 310 /** \brief Set DACR
Kojto 106:ba1f97679dad 311
Kojto 106:ba1f97679dad 312 This function assigns the given value to the Coprocessor Access Control register.
Kojto 106:ba1f97679dad 313
Kojto 106:ba1f97679dad 314 \param [in] dacr Domain Access Control Register value to set
Kojto 106:ba1f97679dad 315 */
Kojto 106:ba1f97679dad 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 106:ba1f97679dad 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 106:ba1f97679dad 318 __regDACR = dacr;
Kojto 106:ba1f97679dad 319 __ISB();
Kojto 106:ba1f97679dad 320 }
Kojto 106:ba1f97679dad 321
Kojto 106:ba1f97679dad 322 /******************************** Cache and BTAC enable ****************************************************/
Kojto 106:ba1f97679dad 323
Kojto 106:ba1f97679dad 324 /** \brief Set SCTLR
Kojto 106:ba1f97679dad 325
Kojto 106:ba1f97679dad 326 This function assigns the given value to the System Control Register.
Kojto 106:ba1f97679dad 327
Kojto 106:ba1f97679dad 328 \param [in] sctlr System Control Register, value to set
Kojto 106:ba1f97679dad 329 */
Kojto 106:ba1f97679dad 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 106:ba1f97679dad 331 {
Kojto 106:ba1f97679dad 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 106:ba1f97679dad 333 __regSCTLR = sctlr;
Kojto 106:ba1f97679dad 334 }
Kojto 106:ba1f97679dad 335
Kojto 106:ba1f97679dad 336 /** \brief Get SCTLR
Kojto 106:ba1f97679dad 337
Kojto 106:ba1f97679dad 338 This function returns the value of the System Control Register.
Kojto 106:ba1f97679dad 339
Kojto 106:ba1f97679dad 340 \return System Control Register value
Kojto 106:ba1f97679dad 341 */
Kojto 106:ba1f97679dad 342 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 106:ba1f97679dad 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 106:ba1f97679dad 344 return(__regSCTLR);
Kojto 106:ba1f97679dad 345 }
Kojto 106:ba1f97679dad 346
Kojto 106:ba1f97679dad 347 /** \brief Enable Caches
Kojto 106:ba1f97679dad 348
Kojto 106:ba1f97679dad 349 Enable Caches
Kojto 106:ba1f97679dad 350 */
Kojto 106:ba1f97679dad 351 __STATIC_INLINE void __enable_caches(void) {
Kojto 106:ba1f97679dad 352 // Set I bit 12 to enable I Cache
Kojto 106:ba1f97679dad 353 // Set C bit 2 to enable D Cache
Kojto 106:ba1f97679dad 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 106:ba1f97679dad 355 }
Kojto 106:ba1f97679dad 356
Kojto 106:ba1f97679dad 357 /** \brief Disable Caches
Kojto 106:ba1f97679dad 358
Kojto 106:ba1f97679dad 359 Disable Caches
Kojto 106:ba1f97679dad 360 */
Kojto 106:ba1f97679dad 361 __STATIC_INLINE void __disable_caches(void) {
Kojto 106:ba1f97679dad 362 // Clear I bit 12 to disable I Cache
Kojto 106:ba1f97679dad 363 // Clear C bit 2 to disable D Cache
Kojto 106:ba1f97679dad 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 106:ba1f97679dad 365 __ISB();
Kojto 106:ba1f97679dad 366 }
Kojto 106:ba1f97679dad 367
Kojto 106:ba1f97679dad 368 /** \brief Enable BTAC
Kojto 106:ba1f97679dad 369
Kojto 106:ba1f97679dad 370 Enable BTAC
Kojto 106:ba1f97679dad 371 */
Kojto 106:ba1f97679dad 372 __STATIC_INLINE void __enable_btac(void) {
Kojto 106:ba1f97679dad 373 // Set Z bit 11 to enable branch prediction
Kojto 106:ba1f97679dad 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 106:ba1f97679dad 375 __ISB();
Kojto 106:ba1f97679dad 376 }
Kojto 106:ba1f97679dad 377
Kojto 106:ba1f97679dad 378 /** \brief Disable BTAC
Kojto 106:ba1f97679dad 379
Kojto 106:ba1f97679dad 380 Disable BTAC
Kojto 106:ba1f97679dad 381 */
Kojto 106:ba1f97679dad 382 __STATIC_INLINE void __disable_btac(void) {
Kojto 106:ba1f97679dad 383 // Clear Z bit 11 to disable branch prediction
Kojto 106:ba1f97679dad 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 106:ba1f97679dad 385 }
Kojto 106:ba1f97679dad 386
Kojto 106:ba1f97679dad 387
Kojto 106:ba1f97679dad 388 /** \brief Enable MMU
Kojto 106:ba1f97679dad 389
Kojto 106:ba1f97679dad 390 Enable MMU
Kojto 106:ba1f97679dad 391 */
Kojto 106:ba1f97679dad 392 __STATIC_INLINE void __enable_mmu(void) {
Kojto 106:ba1f97679dad 393 // Set M bit 0 to enable the MMU
Kojto 106:ba1f97679dad 394 // Set AFE bit to enable simplified access permissions model
Kojto 106:ba1f97679dad 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 106:ba1f97679dad 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 106:ba1f97679dad 397 __ISB();
Kojto 106:ba1f97679dad 398 }
Kojto 106:ba1f97679dad 399
Kojto 106:ba1f97679dad 400 /** \brief Enable MMU
Kojto 106:ba1f97679dad 401
Kojto 106:ba1f97679dad 402 Enable MMU
Kojto 106:ba1f97679dad 403 */
Kojto 106:ba1f97679dad 404 __STATIC_INLINE void __disable_mmu(void) {
Kojto 106:ba1f97679dad 405 // Clear M bit 0 to disable the MMU
Kojto 106:ba1f97679dad 406 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 106:ba1f97679dad 407 __ISB();
Kojto 106:ba1f97679dad 408 }
Kojto 106:ba1f97679dad 409
Kojto 106:ba1f97679dad 410 /******************************** TLB maintenance operations ************************************************/
Kojto 106:ba1f97679dad 411 /** \brief Invalidate the whole tlb
Kojto 106:ba1f97679dad 412
Kojto 106:ba1f97679dad 413 TLBIALL. Invalidate the whole tlb
Kojto 106:ba1f97679dad 414 */
Kojto 106:ba1f97679dad 415
Kojto 106:ba1f97679dad 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 106:ba1f97679dad 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 106:ba1f97679dad 418 __TLBIALL = 0;
Kojto 106:ba1f97679dad 419 __DSB();
Kojto 106:ba1f97679dad 420 __ISB();
Kojto 106:ba1f97679dad 421 }
Kojto 106:ba1f97679dad 422
Kojto 106:ba1f97679dad 423 /******************************** BTB maintenance operations ************************************************/
Kojto 106:ba1f97679dad 424 /** \brief Invalidate entire branch predictor array
Kojto 106:ba1f97679dad 425
Kojto 106:ba1f97679dad 426 BPIALL. Branch Predictor Invalidate All.
Kojto 106:ba1f97679dad 427 */
Kojto 106:ba1f97679dad 428
Kojto 106:ba1f97679dad 429 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 106:ba1f97679dad 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 106:ba1f97679dad 431 __BPIALL = 0;
Kojto 106:ba1f97679dad 432 __DSB(); //ensure completion of the invalidation
Kojto 106:ba1f97679dad 433 __ISB(); //ensure instruction fetch path sees new state
Kojto 106:ba1f97679dad 434 }
Kojto 106:ba1f97679dad 435
Kojto 106:ba1f97679dad 436
Kojto 106:ba1f97679dad 437 /******************************** L1 cache operations ******************************************************/
Kojto 106:ba1f97679dad 438
Kojto 106:ba1f97679dad 439 /** \brief Invalidate the whole I$
Kojto 106:ba1f97679dad 440
Kojto 106:ba1f97679dad 441 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 106:ba1f97679dad 442 */
Kojto 106:ba1f97679dad 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 106:ba1f97679dad 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 106:ba1f97679dad 445 __ICIALLU = 0;
Kojto 106:ba1f97679dad 446 __DSB(); //ensure completion of the invalidation
Kojto 106:ba1f97679dad 447 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 106:ba1f97679dad 448 }
Kojto 106:ba1f97679dad 449
Kojto 106:ba1f97679dad 450 /** \brief Clean D$ by MVA
Kojto 106:ba1f97679dad 451
Kojto 106:ba1f97679dad 452 DCCMVAC. Data cache clean by MVA to PoC
Kojto 106:ba1f97679dad 453 */
Kojto 106:ba1f97679dad 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 106:ba1f97679dad 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 106:ba1f97679dad 456 __DCCMVAC = (uint32_t)va;
Kojto 106:ba1f97679dad 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 106:ba1f97679dad 458 }
Kojto 106:ba1f97679dad 459
Kojto 106:ba1f97679dad 460 /** \brief Invalidate D$ by MVA
Kojto 106:ba1f97679dad 461
Kojto 106:ba1f97679dad 462 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 106:ba1f97679dad 463 */
Kojto 106:ba1f97679dad 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 106:ba1f97679dad 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 106:ba1f97679dad 466 __DCIMVAC = (uint32_t)va;
Kojto 106:ba1f97679dad 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 106:ba1f97679dad 468 }
Kojto 106:ba1f97679dad 469
Kojto 106:ba1f97679dad 470 /** \brief Clean and Invalidate D$ by MVA
Kojto 106:ba1f97679dad 471
Kojto 106:ba1f97679dad 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 106:ba1f97679dad 473 */
Kojto 106:ba1f97679dad 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 106:ba1f97679dad 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 106:ba1f97679dad 476 __DCCIMVAC = (uint32_t)va;
Kojto 106:ba1f97679dad 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 106:ba1f97679dad 478 }
Kojto 106:ba1f97679dad 479
Kojto 106:ba1f97679dad 480 /** \brief
Kojto 106:ba1f97679dad 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 106:ba1f97679dad 482 */
Kojto 106:ba1f97679dad 483 #pragma push
Kojto 106:ba1f97679dad 484 #pragma arm
Kojto 106:ba1f97679dad 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 106:ba1f97679dad 486 ARM
Kojto 106:ba1f97679dad 487
Kojto 106:ba1f97679dad 488 PUSH {R4-R11}
Kojto 106:ba1f97679dad 489
Kojto 106:ba1f97679dad 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 106:ba1f97679dad 491 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 106:ba1f97679dad 492 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 106:ba1f97679dad 493 BEQ Finished // If 0, no need to clean
Kojto 106:ba1f97679dad 494
Kojto 106:ba1f97679dad 495 MOV R10, #0 // R10 holds current cache level << 1
Kojto 106:ba1f97679dad 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 106:ba1f97679dad 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 106:ba1f97679dad 498 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 106:ba1f97679dad 499 CMP R1, #2
Kojto 106:ba1f97679dad 500 BLT Skip // No cache or only instruction cache at this level
Kojto 106:ba1f97679dad 501
Kojto 106:ba1f97679dad 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 106:ba1f97679dad 503 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 106:ba1f97679dad 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 106:ba1f97679dad 505 AND R2, R1, #7 // Extract the line length field
Kojto 106:ba1f97679dad 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 106:ba1f97679dad 507 LDR R4, =0x3FF
Kojto 106:ba1f97679dad 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 106:ba1f97679dad 509 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 106:ba1f97679dad 510 LDR R7, =0x7FFF
Kojto 106:ba1f97679dad 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 106:ba1f97679dad 512
Kojto 106:ba1f97679dad 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 106:ba1f97679dad 514
Kojto 106:ba1f97679dad 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 106:ba1f97679dad 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 106:ba1f97679dad 517 CMP R0, #0
Kojto 106:ba1f97679dad 518 BNE Dccsw
Kojto 106:ba1f97679dad 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 106:ba1f97679dad 520 B cont
Kojto 106:ba1f97679dad 521 Dccsw CMP R0, #1
Kojto 106:ba1f97679dad 522 BNE Dccisw
Kojto 106:ba1f97679dad 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 106:ba1f97679dad 524 B cont
Kojto 106:ba1f97679dad 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
Kojto 106:ba1f97679dad 526 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 106:ba1f97679dad 527 BGE Loop3
Kojto 106:ba1f97679dad 528 SUBS R7, R7, #1 // Decrement the Set number
Kojto 106:ba1f97679dad 529 BGE Loop2
Kojto 106:ba1f97679dad 530 Skip ADD R10, R10, #2 // increment the cache number
Kojto 106:ba1f97679dad 531 CMP R3, R10
Kojto 106:ba1f97679dad 532 BGT Loop1
Kojto 106:ba1f97679dad 533
Kojto 106:ba1f97679dad 534 Finished
Kojto 106:ba1f97679dad 535 DSB
Kojto 106:ba1f97679dad 536 POP {R4-R11}
Kojto 106:ba1f97679dad 537 BX lr
Kojto 106:ba1f97679dad 538
Kojto 106:ba1f97679dad 539 }
Kojto 106:ba1f97679dad 540 #pragma pop
Kojto 106:ba1f97679dad 541
Kojto 106:ba1f97679dad 542 /** \brief __v7_all_cache - helper function
Kojto 106:ba1f97679dad 543
Kojto 106:ba1f97679dad 544 */
Kojto 106:ba1f97679dad 545
Kojto 106:ba1f97679dad 546 /** \brief Invalidate the whole D$
Kojto 106:ba1f97679dad 547
Kojto 106:ba1f97679dad 548 DCISW. Invalidate by Set/Way
Kojto 106:ba1f97679dad 549 */
Kojto 106:ba1f97679dad 550
Kojto 106:ba1f97679dad 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 106:ba1f97679dad 552 __v7_all_cache(0);
Kojto 106:ba1f97679dad 553 }
Kojto 106:ba1f97679dad 554
Kojto 106:ba1f97679dad 555 /** \brief Clean the whole D$
Kojto 106:ba1f97679dad 556
Kojto 106:ba1f97679dad 557 DCCSW. Clean by Set/Way
Kojto 106:ba1f97679dad 558 */
Kojto 106:ba1f97679dad 559
Kojto 106:ba1f97679dad 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 106:ba1f97679dad 561 __v7_all_cache(1);
Kojto 106:ba1f97679dad 562 }
Kojto 106:ba1f97679dad 563
Kojto 106:ba1f97679dad 564 /** \brief Clean and invalidate the whole D$
Kojto 106:ba1f97679dad 565
Kojto 106:ba1f97679dad 566 DCCISW. Clean and Invalidate by Set/Way
Kojto 106:ba1f97679dad 567 */
Kojto 106:ba1f97679dad 568
Kojto 106:ba1f97679dad 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 106:ba1f97679dad 570 __v7_all_cache(2);
Kojto 106:ba1f97679dad 571 }
Kojto 106:ba1f97679dad 572
Kojto 106:ba1f97679dad 573 #include "core_ca_mmu.h"
Kojto 106:ba1f97679dad 574
Kojto 106:ba1f97679dad 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 106:ba1f97679dad 576
Kojto 106:ba1f97679dad 577 #error IAR Compiler support not implemented for Cortex-A
Kojto 106:ba1f97679dad 578
Kojto 106:ba1f97679dad 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 106:ba1f97679dad 580
Kojto 106:ba1f97679dad 581 /* GNU gcc specific functions */
Kojto 106:ba1f97679dad 582
Kojto 106:ba1f97679dad 583 #define MODE_USR 0x10
Kojto 106:ba1f97679dad 584 #define MODE_FIQ 0x11
Kojto 106:ba1f97679dad 585 #define MODE_IRQ 0x12
Kojto 106:ba1f97679dad 586 #define MODE_SVC 0x13
Kojto 106:ba1f97679dad 587 #define MODE_MON 0x16
Kojto 106:ba1f97679dad 588 #define MODE_ABT 0x17
Kojto 106:ba1f97679dad 589 #define MODE_HYP 0x1A
Kojto 106:ba1f97679dad 590 #define MODE_UND 0x1B
Kojto 106:ba1f97679dad 591 #define MODE_SYS 0x1F
Kojto 106:ba1f97679dad 592
Kojto 106:ba1f97679dad 593
Kojto 106:ba1f97679dad 594 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 106:ba1f97679dad 595 {
Kojto 106:ba1f97679dad 596 __ASM volatile ("cpsie i");
Kojto 106:ba1f97679dad 597 }
Kojto 106:ba1f97679dad 598
Kojto 106:ba1f97679dad 599 /** \brief Disable IRQ Interrupts
Kojto 106:ba1f97679dad 600
Kojto 106:ba1f97679dad 601 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 106:ba1f97679dad 602 Can only be executed in Privileged modes.
Kojto 106:ba1f97679dad 603 */
Kojto 106:ba1f97679dad 604 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 106:ba1f97679dad 605 {
Kojto 106:ba1f97679dad 606 uint32_t result;
Kojto 106:ba1f97679dad 607
Kojto 106:ba1f97679dad 608 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 106:ba1f97679dad 609 __ASM volatile ("cpsid i");
Kojto 106:ba1f97679dad 610 return(result & 0x80);
Kojto 106:ba1f97679dad 611 }
Kojto 106:ba1f97679dad 612
Kojto 106:ba1f97679dad 613
Kojto 106:ba1f97679dad 614 /** \brief Get APSR Register
Kojto 106:ba1f97679dad 615
Kojto 106:ba1f97679dad 616 This function returns the content of the APSR Register.
Kojto 106:ba1f97679dad 617
Kojto 106:ba1f97679dad 618 \return APSR Register value
Kojto 106:ba1f97679dad 619 */
Kojto 106:ba1f97679dad 620 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 106:ba1f97679dad 621 {
Kojto 106:ba1f97679dad 622 #if 1
Kojto 106:ba1f97679dad 623 uint32_t result;
Kojto 106:ba1f97679dad 624
Kojto 106:ba1f97679dad 625 __ASM volatile ("mrs %0, apsr" : "=r" (result) );
Kojto 106:ba1f97679dad 626 return (result);
Kojto 106:ba1f97679dad 627 #else
Kojto 106:ba1f97679dad 628 register uint32_t __regAPSR __ASM("apsr");
Kojto 106:ba1f97679dad 629 return(__regAPSR);
Kojto 106:ba1f97679dad 630 #endif
Kojto 106:ba1f97679dad 631 }
Kojto 106:ba1f97679dad 632
Kojto 106:ba1f97679dad 633
Kojto 106:ba1f97679dad 634 /** \brief Get CPSR Register
Kojto 106:ba1f97679dad 635
Kojto 106:ba1f97679dad 636 This function returns the content of the CPSR Register.
Kojto 106:ba1f97679dad 637
Kojto 106:ba1f97679dad 638 \return CPSR Register value
Kojto 106:ba1f97679dad 639 */
Kojto 106:ba1f97679dad 640 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 106:ba1f97679dad 641 {
Kojto 106:ba1f97679dad 642 #if 1
Kojto 106:ba1f97679dad 643 register uint32_t __regCPSR;
Kojto 106:ba1f97679dad 644 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 106:ba1f97679dad 645 #else
Kojto 106:ba1f97679dad 646 register uint32_t __regCPSR __ASM("cpsr");
Kojto 106:ba1f97679dad 647 #endif
Kojto 106:ba1f97679dad 648 return(__regCPSR);
Kojto 106:ba1f97679dad 649 }
Kojto 106:ba1f97679dad 650
Kojto 106:ba1f97679dad 651 #if 0
Kojto 106:ba1f97679dad 652 /** \brief Set Stack Pointer
Kojto 106:ba1f97679dad 653
Kojto 106:ba1f97679dad 654 This function assigns the given value to the current stack pointer.
Kojto 106:ba1f97679dad 655
Kojto 106:ba1f97679dad 656 \param [in] topOfStack Stack Pointer value to set
Kojto 106:ba1f97679dad 657 */
Kojto 106:ba1f97679dad 658 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 106:ba1f97679dad 659 {
Kojto 106:ba1f97679dad 660 register uint32_t __regSP __ASM("sp");
Kojto 106:ba1f97679dad 661 __regSP = topOfStack;
Kojto 106:ba1f97679dad 662 }
Kojto 106:ba1f97679dad 663 #endif
Kojto 106:ba1f97679dad 664
Kojto 106:ba1f97679dad 665 /** \brief Get link register
Kojto 106:ba1f97679dad 666
Kojto 106:ba1f97679dad 667 This function returns the value of the link register
Kojto 106:ba1f97679dad 668
Kojto 106:ba1f97679dad 669 \return Value of link register
Kojto 106:ba1f97679dad 670 */
Kojto 106:ba1f97679dad 671 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 106:ba1f97679dad 672 {
Kojto 106:ba1f97679dad 673 register uint32_t __reglr __ASM("lr");
Kojto 106:ba1f97679dad 674 return(__reglr);
Kojto 106:ba1f97679dad 675 }
Kojto 106:ba1f97679dad 676
Kojto 106:ba1f97679dad 677 #if 0
Kojto 106:ba1f97679dad 678 /** \brief Set link register
Kojto 106:ba1f97679dad 679
Kojto 106:ba1f97679dad 680 This function sets the value of the link register
Kojto 106:ba1f97679dad 681
Kojto 106:ba1f97679dad 682 \param [in] lr LR value to set
Kojto 106:ba1f97679dad 683 */
Kojto 106:ba1f97679dad 684 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 106:ba1f97679dad 685 {
Kojto 106:ba1f97679dad 686 register uint32_t __reglr __ASM("lr");
Kojto 106:ba1f97679dad 687 __reglr = lr;
Kojto 106:ba1f97679dad 688 }
Kojto 106:ba1f97679dad 689 #endif
Kojto 106:ba1f97679dad 690
Kojto 106:ba1f97679dad 691 /** \brief Set Process Stack Pointer
Kojto 106:ba1f97679dad 692
Kojto 106:ba1f97679dad 693 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 106:ba1f97679dad 694
Kojto 106:ba1f97679dad 695 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 106:ba1f97679dad 696 */
Kojto 106:ba1f97679dad 697 extern void __set_PSP(uint32_t topOfProcStack);
Kojto 106:ba1f97679dad 698
Kojto 106:ba1f97679dad 699 /** \brief Set User Mode
Kojto 106:ba1f97679dad 700
Kojto 106:ba1f97679dad 701 This function changes the processor state to User Mode
Kojto 106:ba1f97679dad 702
Kojto 106:ba1f97679dad 703 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 106:ba1f97679dad 704 */
Kojto 106:ba1f97679dad 705 extern void __set_CPS_USR(void);
Kojto 106:ba1f97679dad 706
Kojto 106:ba1f97679dad 707 /** \brief Enable FIQ
Kojto 106:ba1f97679dad 708
Kojto 106:ba1f97679dad 709 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 106:ba1f97679dad 710 Can only be executed in Privileged modes.
Kojto 106:ba1f97679dad 711 */
Kojto 106:ba1f97679dad 712 #define __enable_fault_irq __enable_fiq
Kojto 106:ba1f97679dad 713
Kojto 106:ba1f97679dad 714
Kojto 106:ba1f97679dad 715 /** \brief Disable FIQ
Kojto 106:ba1f97679dad 716
Kojto 106:ba1f97679dad 717 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 106:ba1f97679dad 718 Can only be executed in Privileged modes.
Kojto 106:ba1f97679dad 719 */
Kojto 106:ba1f97679dad 720 #define __disable_fault_irq __disable_fiq
Kojto 106:ba1f97679dad 721
Kojto 106:ba1f97679dad 722
Kojto 106:ba1f97679dad 723 /** \brief Get FPSCR
Kojto 106:ba1f97679dad 724
Kojto 106:ba1f97679dad 725 This function returns the current value of the Floating Point Status/Control register.
Kojto 106:ba1f97679dad 726
Kojto 106:ba1f97679dad 727 \return Floating Point Status/Control register value
Kojto 106:ba1f97679dad 728 */
Kojto 106:ba1f97679dad 729 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 106:ba1f97679dad 730 {
Kojto 106:ba1f97679dad 731 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 106:ba1f97679dad 732 #if 1
Kojto 106:ba1f97679dad 733 uint32_t result;
Kojto 106:ba1f97679dad 734
Kojto 106:ba1f97679dad 735 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 106:ba1f97679dad 736 return (result);
Kojto 106:ba1f97679dad 737 #else
Kojto 106:ba1f97679dad 738 register uint32_t __regfpscr __ASM("fpscr");
Kojto 106:ba1f97679dad 739 return(__regfpscr);
Kojto 106:ba1f97679dad 740 #endif
Kojto 106:ba1f97679dad 741 #else
Kojto 106:ba1f97679dad 742 return(0);
Kojto 106:ba1f97679dad 743 #endif
Kojto 106:ba1f97679dad 744 }
Kojto 106:ba1f97679dad 745
Kojto 106:ba1f97679dad 746
Kojto 106:ba1f97679dad 747 /** \brief Set FPSCR
Kojto 106:ba1f97679dad 748
Kojto 106:ba1f97679dad 749 This function assigns the given value to the Floating Point Status/Control register.
Kojto 106:ba1f97679dad 750
Kojto 106:ba1f97679dad 751 \param [in] fpscr Floating Point Status/Control value to set
Kojto 106:ba1f97679dad 752 */
Kojto 106:ba1f97679dad 753 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 106:ba1f97679dad 754 {
Kojto 106:ba1f97679dad 755 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 106:ba1f97679dad 756 #if 1
Kojto 106:ba1f97679dad 757 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 106:ba1f97679dad 758 #else
Kojto 106:ba1f97679dad 759 register uint32_t __regfpscr __ASM("fpscr");
Kojto 106:ba1f97679dad 760 __regfpscr = (fpscr);
Kojto 106:ba1f97679dad 761 #endif
Kojto 106:ba1f97679dad 762 #endif
Kojto 106:ba1f97679dad 763 }
Kojto 106:ba1f97679dad 764
Kojto 106:ba1f97679dad 765 /** \brief Get FPEXC
Kojto 106:ba1f97679dad 766
Kojto 106:ba1f97679dad 767 This function returns the current value of the Floating Point Exception Control register.
Kojto 106:ba1f97679dad 768
Kojto 106:ba1f97679dad 769 \return Floating Point Exception Control register value
Kojto 106:ba1f97679dad 770 */
Kojto 106:ba1f97679dad 771 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 106:ba1f97679dad 772 {
Kojto 106:ba1f97679dad 773 #if (__FPU_PRESENT == 1)
Kojto 106:ba1f97679dad 774 #if 1
Kojto 106:ba1f97679dad 775 uint32_t result;
Kojto 106:ba1f97679dad 776
Kojto 106:ba1f97679dad 777 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 106:ba1f97679dad 778 return (result);
Kojto 106:ba1f97679dad 779 #else
Kojto 106:ba1f97679dad 780 register uint32_t __regfpexc __ASM("fpexc");
Kojto 106:ba1f97679dad 781 return(__regfpexc);
Kojto 106:ba1f97679dad 782 #endif
Kojto 106:ba1f97679dad 783 #else
Kojto 106:ba1f97679dad 784 return(0);
Kojto 106:ba1f97679dad 785 #endif
Kojto 106:ba1f97679dad 786 }
Kojto 106:ba1f97679dad 787
Kojto 106:ba1f97679dad 788
Kojto 106:ba1f97679dad 789 /** \brief Set FPEXC
Kojto 106:ba1f97679dad 790
Kojto 106:ba1f97679dad 791 This function assigns the given value to the Floating Point Exception Control register.
Kojto 106:ba1f97679dad 792
Kojto 106:ba1f97679dad 793 \param [in] fpscr Floating Point Exception Control value to set
Kojto 106:ba1f97679dad 794 */
Kojto 106:ba1f97679dad 795 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 106:ba1f97679dad 796 {
Kojto 106:ba1f97679dad 797 #if (__FPU_PRESENT == 1)
Kojto 106:ba1f97679dad 798 #if 1
Kojto 106:ba1f97679dad 799 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 106:ba1f97679dad 800 #else
Kojto 106:ba1f97679dad 801 register uint32_t __regfpexc __ASM("fpexc");
Kojto 106:ba1f97679dad 802 __regfpexc = (fpexc);
Kojto 106:ba1f97679dad 803 #endif
Kojto 106:ba1f97679dad 804 #endif
Kojto 106:ba1f97679dad 805 }
Kojto 106:ba1f97679dad 806
Kojto 106:ba1f97679dad 807 /** \brief Get CPACR
Kojto 106:ba1f97679dad 808
Kojto 106:ba1f97679dad 809 This function returns the current value of the Coprocessor Access Control register.
Kojto 106:ba1f97679dad 810
Kojto 106:ba1f97679dad 811 \return Coprocessor Access Control register value
Kojto 106:ba1f97679dad 812 */
Kojto 106:ba1f97679dad 813 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 106:ba1f97679dad 814 {
Kojto 106:ba1f97679dad 815 #if 1
Kojto 106:ba1f97679dad 816 register uint32_t __regCPACR;
Kojto 106:ba1f97679dad 817 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 106:ba1f97679dad 818 #else
Kojto 106:ba1f97679dad 819 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 106:ba1f97679dad 820 #endif
Kojto 106:ba1f97679dad 821 return __regCPACR;
Kojto 106:ba1f97679dad 822 }
Kojto 106:ba1f97679dad 823
Kojto 106:ba1f97679dad 824 /** \brief Set CPACR
Kojto 106:ba1f97679dad 825
Kojto 106:ba1f97679dad 826 This function assigns the given value to the Coprocessor Access Control register.
Kojto 106:ba1f97679dad 827
Kojto 106:ba1f97679dad 828 \param [in] cpacr Coporcessor Acccess Control value to set
Kojto 106:ba1f97679dad 829 */
Kojto 106:ba1f97679dad 830 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 106:ba1f97679dad 831 {
Kojto 106:ba1f97679dad 832 #if 1
Kojto 106:ba1f97679dad 833 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 106:ba1f97679dad 834 #else
Kojto 106:ba1f97679dad 835 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 106:ba1f97679dad 836 __regCPACR = cpacr;
Kojto 106:ba1f97679dad 837 #endif
Kojto 106:ba1f97679dad 838 __ISB();
Kojto 106:ba1f97679dad 839 }
Kojto 106:ba1f97679dad 840
Kojto 106:ba1f97679dad 841 /** \brief Get CBAR
Kojto 106:ba1f97679dad 842
Kojto 106:ba1f97679dad 843 This function returns the value of the Configuration Base Address register.
Kojto 106:ba1f97679dad 844
Kojto 106:ba1f97679dad 845 \return Configuration Base Address register value
Kojto 106:ba1f97679dad 846 */
Kojto 106:ba1f97679dad 847 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 106:ba1f97679dad 848 #if 1
Kojto 106:ba1f97679dad 849 register uint32_t __regCBAR;
Kojto 106:ba1f97679dad 850 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 106:ba1f97679dad 851 #else
Kojto 106:ba1f97679dad 852 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 106:ba1f97679dad 853 #endif
Kojto 106:ba1f97679dad 854 return(__regCBAR);
Kojto 106:ba1f97679dad 855 }
Kojto 106:ba1f97679dad 856
Kojto 106:ba1f97679dad 857 /** \brief Get TTBR0
Kojto 106:ba1f97679dad 858
Kojto 106:ba1f97679dad 859 This function returns the value of the Configuration Base Address register.
Kojto 106:ba1f97679dad 860
Kojto 106:ba1f97679dad 861 \return Translation Table Base Register 0 value
Kojto 106:ba1f97679dad 862 */
Kojto 106:ba1f97679dad 863 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 106:ba1f97679dad 864 #if 1
Kojto 106:ba1f97679dad 865 register uint32_t __regTTBR0;
Kojto 106:ba1f97679dad 866 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 106:ba1f97679dad 867 #else
Kojto 106:ba1f97679dad 868 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 106:ba1f97679dad 869 #endif
Kojto 106:ba1f97679dad 870 return(__regTTBR0);
Kojto 106:ba1f97679dad 871 }
Kojto 106:ba1f97679dad 872
Kojto 106:ba1f97679dad 873 /** \brief Set TTBR0
Kojto 106:ba1f97679dad 874
Kojto 106:ba1f97679dad 875 This function assigns the given value to the Coprocessor Access Control register.
Kojto 106:ba1f97679dad 876
Kojto 106:ba1f97679dad 877 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 106:ba1f97679dad 878 */
Kojto 106:ba1f97679dad 879 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 106:ba1f97679dad 880 #if 1
Kojto 106:ba1f97679dad 881 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 106:ba1f97679dad 882 #else
Kojto 106:ba1f97679dad 883 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 106:ba1f97679dad 884 __regTTBR0 = ttbr0;
Kojto 106:ba1f97679dad 885 #endif
Kojto 106:ba1f97679dad 886 __ISB();
Kojto 106:ba1f97679dad 887 }
Kojto 106:ba1f97679dad 888
Kojto 106:ba1f97679dad 889 /** \brief Get DACR
Kojto 106:ba1f97679dad 890
Kojto 106:ba1f97679dad 891 This function returns the value of the Domain Access Control Register.
Kojto 106:ba1f97679dad 892
Kojto 106:ba1f97679dad 893 \return Domain Access Control Register value
Kojto 106:ba1f97679dad 894 */
Kojto 106:ba1f97679dad 895 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 106:ba1f97679dad 896 #if 1
Kojto 106:ba1f97679dad 897 register uint32_t __regDACR;
Kojto 106:ba1f97679dad 898 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 106:ba1f97679dad 899 #else
Kojto 106:ba1f97679dad 900 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 106:ba1f97679dad 901 #endif
Kojto 106:ba1f97679dad 902 return(__regDACR);
Kojto 106:ba1f97679dad 903 }
Kojto 106:ba1f97679dad 904
Kojto 106:ba1f97679dad 905 /** \brief Set DACR
Kojto 106:ba1f97679dad 906
Kojto 106:ba1f97679dad 907 This function assigns the given value to the Coprocessor Access Control register.
Kojto 106:ba1f97679dad 908
Kojto 106:ba1f97679dad 909 \param [in] dacr Domain Access Control Register value to set
Kojto 106:ba1f97679dad 910 */
Kojto 106:ba1f97679dad 911 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 106:ba1f97679dad 912 #if 1
Kojto 106:ba1f97679dad 913 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 106:ba1f97679dad 914 #else
Kojto 106:ba1f97679dad 915 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 106:ba1f97679dad 916 __regDACR = dacr;
Kojto 106:ba1f97679dad 917 #endif
Kojto 106:ba1f97679dad 918 __ISB();
Kojto 106:ba1f97679dad 919 }
Kojto 106:ba1f97679dad 920
Kojto 106:ba1f97679dad 921 /******************************** Cache and BTAC enable ****************************************************/
Kojto 106:ba1f97679dad 922
Kojto 106:ba1f97679dad 923 /** \brief Set SCTLR
Kojto 106:ba1f97679dad 924
Kojto 106:ba1f97679dad 925 This function assigns the given value to the System Control Register.
Kojto 106:ba1f97679dad 926
Kojto 106:ba1f97679dad 927 \param [in] sctlr System Control Register, value to set
Kojto 106:ba1f97679dad 928 */
Kojto 106:ba1f97679dad 929 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 106:ba1f97679dad 930 {
Kojto 106:ba1f97679dad 931 #if 1
Kojto 106:ba1f97679dad 932 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 106:ba1f97679dad 933 #else
Kojto 106:ba1f97679dad 934 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 106:ba1f97679dad 935 __regSCTLR = sctlr;
Kojto 106:ba1f97679dad 936 #endif
Kojto 106:ba1f97679dad 937 }
Kojto 106:ba1f97679dad 938
Kojto 106:ba1f97679dad 939 /** \brief Get SCTLR
Kojto 106:ba1f97679dad 940
Kojto 106:ba1f97679dad 941 This function returns the value of the System Control Register.
Kojto 106:ba1f97679dad 942
Kojto 106:ba1f97679dad 943 \return System Control Register value
Kojto 106:ba1f97679dad 944 */
Kojto 106:ba1f97679dad 945 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 106:ba1f97679dad 946 #if 1
Kojto 106:ba1f97679dad 947 register uint32_t __regSCTLR;
Kojto 106:ba1f97679dad 948 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 106:ba1f97679dad 949 #else
Kojto 106:ba1f97679dad 950 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 106:ba1f97679dad 951 #endif
Kojto 106:ba1f97679dad 952 return(__regSCTLR);
Kojto 106:ba1f97679dad 953 }
Kojto 106:ba1f97679dad 954
Kojto 106:ba1f97679dad 955 /** \brief Enable Caches
Kojto 106:ba1f97679dad 956
Kojto 106:ba1f97679dad 957 Enable Caches
Kojto 106:ba1f97679dad 958 */
Kojto 106:ba1f97679dad 959 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 106:ba1f97679dad 960 // Set I bit 12 to enable I Cache
Kojto 106:ba1f97679dad 961 // Set C bit 2 to enable D Cache
Kojto 106:ba1f97679dad 962 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 106:ba1f97679dad 963 }
Kojto 106:ba1f97679dad 964
Kojto 106:ba1f97679dad 965 /** \brief Disable Caches
Kojto 106:ba1f97679dad 966
Kojto 106:ba1f97679dad 967 Disable Caches
Kojto 106:ba1f97679dad 968 */
Kojto 106:ba1f97679dad 969 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 106:ba1f97679dad 970 // Clear I bit 12 to disable I Cache
Kojto 106:ba1f97679dad 971 // Clear C bit 2 to disable D Cache
Kojto 106:ba1f97679dad 972 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 106:ba1f97679dad 973 __ISB();
Kojto 106:ba1f97679dad 974 }
Kojto 106:ba1f97679dad 975
Kojto 106:ba1f97679dad 976 /** \brief Enable BTAC
Kojto 106:ba1f97679dad 977
Kojto 106:ba1f97679dad 978 Enable BTAC
Kojto 106:ba1f97679dad 979 */
Kojto 106:ba1f97679dad 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 106:ba1f97679dad 981 // Set Z bit 11 to enable branch prediction
Kojto 106:ba1f97679dad 982 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 106:ba1f97679dad 983 __ISB();
Kojto 106:ba1f97679dad 984 }
Kojto 106:ba1f97679dad 985
Kojto 106:ba1f97679dad 986 /** \brief Disable BTAC
Kojto 106:ba1f97679dad 987
Kojto 106:ba1f97679dad 988 Disable BTAC
Kojto 106:ba1f97679dad 989 */
Kojto 106:ba1f97679dad 990 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 106:ba1f97679dad 991 // Clear Z bit 11 to disable branch prediction
Kojto 106:ba1f97679dad 992 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 106:ba1f97679dad 993 }
Kojto 106:ba1f97679dad 994
Kojto 106:ba1f97679dad 995
Kojto 106:ba1f97679dad 996 /** \brief Enable MMU
Kojto 106:ba1f97679dad 997
Kojto 106:ba1f97679dad 998 Enable MMU
Kojto 106:ba1f97679dad 999 */
Kojto 106:ba1f97679dad 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 106:ba1f97679dad 1001 // Set M bit 0 to enable the MMU
Kojto 106:ba1f97679dad 1002 // Set AFE bit to enable simplified access permissions model
Kojto 106:ba1f97679dad 1003 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 106:ba1f97679dad 1004 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 106:ba1f97679dad 1005 __ISB();
Kojto 106:ba1f97679dad 1006 }
Kojto 106:ba1f97679dad 1007
Kojto 106:ba1f97679dad 1008 /** \brief Enable MMU
Kojto 106:ba1f97679dad 1009
Kojto 106:ba1f97679dad 1010 Enable MMU
Kojto 106:ba1f97679dad 1011 */
Kojto 106:ba1f97679dad 1012 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 106:ba1f97679dad 1013 // Clear M bit 0 to disable the MMU
Kojto 106:ba1f97679dad 1014 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 106:ba1f97679dad 1015 __ISB();
Kojto 106:ba1f97679dad 1016 }
Kojto 106:ba1f97679dad 1017
Kojto 106:ba1f97679dad 1018 /******************************** TLB maintenance operations ************************************************/
Kojto 106:ba1f97679dad 1019 /** \brief Invalidate the whole tlb
Kojto 106:ba1f97679dad 1020
Kojto 106:ba1f97679dad 1021 TLBIALL. Invalidate the whole tlb
Kojto 106:ba1f97679dad 1022 */
Kojto 106:ba1f97679dad 1023
Kojto 106:ba1f97679dad 1024 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 106:ba1f97679dad 1025 #if 1
Kojto 106:ba1f97679dad 1026 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 106:ba1f97679dad 1027 #else
Kojto 106:ba1f97679dad 1028 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 106:ba1f97679dad 1029 __TLBIALL = 0;
Kojto 106:ba1f97679dad 1030 #endif
Kojto 106:ba1f97679dad 1031 __DSB();
Kojto 106:ba1f97679dad 1032 __ISB();
Kojto 106:ba1f97679dad 1033 }
Kojto 106:ba1f97679dad 1034
Kojto 106:ba1f97679dad 1035 /******************************** BTB maintenance operations ************************************************/
Kojto 106:ba1f97679dad 1036 /** \brief Invalidate entire branch predictor array
Kojto 106:ba1f97679dad 1037
Kojto 106:ba1f97679dad 1038 BPIALL. Branch Predictor Invalidate All.
Kojto 106:ba1f97679dad 1039 */
Kojto 106:ba1f97679dad 1040
Kojto 106:ba1f97679dad 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 106:ba1f97679dad 1042 #if 1
Kojto 106:ba1f97679dad 1043 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 106:ba1f97679dad 1044 #else
Kojto 106:ba1f97679dad 1045 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 106:ba1f97679dad 1046 __BPIALL = 0;
Kojto 106:ba1f97679dad 1047 #endif
Kojto 106:ba1f97679dad 1048 __DSB(); //ensure completion of the invalidation
Kojto 106:ba1f97679dad 1049 __ISB(); //ensure instruction fetch path sees new state
Kojto 106:ba1f97679dad 1050 }
Kojto 106:ba1f97679dad 1051
Kojto 106:ba1f97679dad 1052
Kojto 106:ba1f97679dad 1053 /******************************** L1 cache operations ******************************************************/
Kojto 106:ba1f97679dad 1054
Kojto 106:ba1f97679dad 1055 /** \brief Invalidate the whole I$
Kojto 106:ba1f97679dad 1056
Kojto 106:ba1f97679dad 1057 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 106:ba1f97679dad 1058 */
Kojto 106:ba1f97679dad 1059 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 106:ba1f97679dad 1060 #if 1
Kojto 106:ba1f97679dad 1061 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 106:ba1f97679dad 1062 #else
Kojto 106:ba1f97679dad 1063 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 106:ba1f97679dad 1064 __ICIALLU = 0;
Kojto 106:ba1f97679dad 1065 #endif
Kojto 106:ba1f97679dad 1066 __DSB(); //ensure completion of the invalidation
Kojto 106:ba1f97679dad 1067 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 106:ba1f97679dad 1068 }
Kojto 106:ba1f97679dad 1069
Kojto 106:ba1f97679dad 1070 /** \brief Clean D$ by MVA
Kojto 106:ba1f97679dad 1071
Kojto 106:ba1f97679dad 1072 DCCMVAC. Data cache clean by MVA to PoC
Kojto 106:ba1f97679dad 1073 */
Kojto 106:ba1f97679dad 1074 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 106:ba1f97679dad 1075 #if 1
Kojto 106:ba1f97679dad 1076 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 106:ba1f97679dad 1077 #else
Kojto 106:ba1f97679dad 1078 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 106:ba1f97679dad 1079 __DCCMVAC = (uint32_t)va;
Kojto 106:ba1f97679dad 1080 #endif
Kojto 106:ba1f97679dad 1081 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 106:ba1f97679dad 1082 }
Kojto 106:ba1f97679dad 1083
Kojto 106:ba1f97679dad 1084 /** \brief Invalidate D$ by MVA
Kojto 106:ba1f97679dad 1085
Kojto 106:ba1f97679dad 1086 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 106:ba1f97679dad 1087 */
Kojto 106:ba1f97679dad 1088 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 106:ba1f97679dad 1089 #if 1
Kojto 106:ba1f97679dad 1090 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 106:ba1f97679dad 1091 #else
Kojto 106:ba1f97679dad 1092 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 106:ba1f97679dad 1093 __DCIMVAC = (uint32_t)va;
Kojto 106:ba1f97679dad 1094 #endif
Kojto 106:ba1f97679dad 1095 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 106:ba1f97679dad 1096 }
Kojto 106:ba1f97679dad 1097
Kojto 106:ba1f97679dad 1098 /** \brief Clean and Invalidate D$ by MVA
Kojto 106:ba1f97679dad 1099
Kojto 106:ba1f97679dad 1100 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 106:ba1f97679dad 1101 */
Kojto 106:ba1f97679dad 1102 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 106:ba1f97679dad 1103 #if 1
Kojto 106:ba1f97679dad 1104 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 106:ba1f97679dad 1105 #else
Kojto 106:ba1f97679dad 1106 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 106:ba1f97679dad 1107 __DCCIMVAC = (uint32_t)va;
Kojto 106:ba1f97679dad 1108 #endif
Kojto 106:ba1f97679dad 1109 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 106:ba1f97679dad 1110 }
Kojto 106:ba1f97679dad 1111
Kojto 106:ba1f97679dad 1112 /** \brief
Kojto 106:ba1f97679dad 1113 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 106:ba1f97679dad 1114 */
Kojto 106:ba1f97679dad 1115
Kojto 106:ba1f97679dad 1116 /** \brief __v7_all_cache - helper function
Kojto 106:ba1f97679dad 1117
Kojto 106:ba1f97679dad 1118 */
Kojto 106:ba1f97679dad 1119
Kojto 106:ba1f97679dad 1120 extern void __v7_all_cache(uint32_t op);
Kojto 106:ba1f97679dad 1121
Kojto 106:ba1f97679dad 1122
Kojto 106:ba1f97679dad 1123 /** \brief Invalidate the whole D$
Kojto 106:ba1f97679dad 1124
Kojto 106:ba1f97679dad 1125 DCISW. Invalidate by Set/Way
Kojto 106:ba1f97679dad 1126 */
Kojto 106:ba1f97679dad 1127
Kojto 106:ba1f97679dad 1128 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 106:ba1f97679dad 1129 __v7_all_cache(0);
Kojto 106:ba1f97679dad 1130 }
Kojto 106:ba1f97679dad 1131
Kojto 106:ba1f97679dad 1132 /** \brief Clean the whole D$
Kojto 106:ba1f97679dad 1133
Kojto 106:ba1f97679dad 1134 DCCSW. Clean by Set/Way
Kojto 106:ba1f97679dad 1135 */
Kojto 106:ba1f97679dad 1136
Kojto 106:ba1f97679dad 1137 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 106:ba1f97679dad 1138 __v7_all_cache(1);
Kojto 106:ba1f97679dad 1139 }
Kojto 106:ba1f97679dad 1140
Kojto 106:ba1f97679dad 1141 /** \brief Clean and invalidate the whole D$
Kojto 106:ba1f97679dad 1142
Kojto 106:ba1f97679dad 1143 DCCISW. Clean and Invalidate by Set/Way
Kojto 106:ba1f97679dad 1144 */
Kojto 106:ba1f97679dad 1145
Kojto 106:ba1f97679dad 1146 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 106:ba1f97679dad 1147 __v7_all_cache(2);
Kojto 106:ba1f97679dad 1148 }
Kojto 106:ba1f97679dad 1149
Kojto 106:ba1f97679dad 1150 #include "core_ca_mmu.h"
Kojto 106:ba1f97679dad 1151
Kojto 106:ba1f97679dad 1152 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 106:ba1f97679dad 1153
Kojto 106:ba1f97679dad 1154 #error TASKING Compiler support not implemented for Cortex-A
Kojto 106:ba1f97679dad 1155
Kojto 106:ba1f97679dad 1156 #endif
Kojto 106:ba1f97679dad 1157
Kojto 106:ba1f97679dad 1158 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 106:ba1f97679dad 1159
Kojto 106:ba1f97679dad 1160
Kojto 106:ba1f97679dad 1161 #endif /* __CORE_CAFUNC_H__ */