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TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h@106:ba1f97679dad, 2015-09-02 (annotated)

Committer:: Kojto
Date:: Wed Sep 02 14:17:43 2015 +0100
Revision:: 106:ba1f97679dad
Parent:: 99:dbbf35b96557
Child:: 110:165afa46840b

Release 106  of the mbed library



Changes:

- new platform - Nucleo F446RE

- STM32F4 Cube driver update v2.3.2

- ST cmsis driver v2.3.2

- nordic bugfix gcc linker start address

- lpc11u68 - bugfix for serial ports

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_ll_fmc.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
Kojto	106:ba1f97679dad	5	* @version V1.3.2
Kojto	106:ba1f97679dad	6	* @date 26-June-2015
emilmont	77:869cf507173a	7	* @brief Header file of FMC HAL module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
Kojto	99:dbbf35b96557	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_LL_FMC_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_LL_FMC_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	47	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	48
emilmont	77:869cf507173a	49	/** @addtogroup STM32F4xx_HAL_Driver
emilmont	77:869cf507173a	50	* @{
emilmont	77:869cf507173a	51	*/
Kojto	99:dbbf35b96557	52
Kojto	99:dbbf35b96557	53	/** @addtogroup FMC_LL
emilmont	77:869cf507173a	54	* @{
emilmont	77:869cf507173a	55	*/
Kojto	99:dbbf35b96557	56	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
Kojto	99:dbbf35b96557	57	/* Private types -------------------------------------------------------------*/
Kojto	99:dbbf35b96557	58	/** @defgroup FMC_LL_Private_Types FMC Private Types
Kojto	99:dbbf35b96557	59	* @{
Kojto	99:dbbf35b96557	60	*/
emilmont	77:869cf507173a	61
emilmont	77:869cf507173a	62	/**
Kojto	99:dbbf35b96557	63	* @brief FMC NORSRAM Configuration Structure definition
emilmont	77:869cf507173a	64	*/
emilmont	77:869cf507173a	65	typedef struct
emilmont	77:869cf507173a	66	{
emilmont	77:869cf507173a	67	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm	85:024bf7f99721	68	This parameter can be a value of @ref FMC_NORSRAM_Bank */
bogdanm	85:024bf7f99721	69
emilmont	77:869cf507173a	70	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
emilmont	77:869cf507173a	71	multiplexed on the data bus or not.
emilmont	77:869cf507173a	72	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
bogdanm	85:024bf7f99721	73
emilmont	77:869cf507173a	74	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
emilmont	77:869cf507173a	75	the corresponding memory device.
emilmont	77:869cf507173a	76	This parameter can be a value of @ref FMC_Memory_Type */
bogdanm	85:024bf7f99721	77
emilmont	77:869cf507173a	78	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
emilmont	77:869cf507173a	79	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
bogdanm	85:024bf7f99721	80
emilmont	77:869cf507173a	81	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
emilmont	77:869cf507173a	82	valid only with synchronous burst Flash memories.
emilmont	77:869cf507173a	83	This parameter can be a value of @ref FMC_Burst_Access_Mode */
bogdanm	85:024bf7f99721	84
emilmont	77:869cf507173a	85	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
emilmont	77:869cf507173a	86	the Flash memory in burst mode.
emilmont	77:869cf507173a	87	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
bogdanm	85:024bf7f99721	88
emilmont	77:869cf507173a	89	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
emilmont	77:869cf507173a	90	memory, valid only when accessing Flash memories in burst mode.
Kojto	99:dbbf35b96557	91	This parameter can be a value of @ref FMC_Wrap_Mode
Kojto	99:dbbf35b96557	92	This mode is not available for the STM32F446xx devices */
bogdanm	85:024bf7f99721	93
emilmont	77:869cf507173a	94	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
emilmont	77:869cf507173a	95	clock cycle before the wait state or during the wait state,
emilmont	77:869cf507173a	96	valid only when accessing memories in burst mode.
emilmont	77:869cf507173a	97	This parameter can be a value of @ref FMC_Wait_Timing */
bogdanm	85:024bf7f99721	98
emilmont	77:869cf507173a	99	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
emilmont	77:869cf507173a	100	This parameter can be a value of @ref FMC_Write_Operation */
bogdanm	85:024bf7f99721	101
emilmont	77:869cf507173a	102	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
emilmont	77:869cf507173a	103	signal, valid for Flash memory access in burst mode.
emilmont	77:869cf507173a	104	This parameter can be a value of @ref FMC_Wait_Signal */
bogdanm	85:024bf7f99721	105
emilmont	77:869cf507173a	106	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
emilmont	77:869cf507173a	107	This parameter can be a value of @ref FMC_Extended_Mode */
bogdanm	85:024bf7f99721	108
emilmont	77:869cf507173a	109	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
emilmont	77:869cf507173a	110	valid only with asynchronous Flash memories.
emilmont	77:869cf507173a	111	This parameter can be a value of @ref FMC_AsynchronousWait */
bogdanm	85:024bf7f99721	112
emilmont	77:869cf507173a	113	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm	85:024bf7f99721	114	This parameter can be a value of @ref FMC_Write_Burst */
bogdanm	85:024bf7f99721	115
emilmont	77:869cf507173a	116	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
emilmont	77:869cf507173a	117	This parameter is only enabled through the FMC_BCR1 register, and don't care
emilmont	77:869cf507173a	118	through FMC_BCR2..4 registers.
bogdanm	85:024bf7f99721	119	This parameter can be a value of @ref FMC_Continous_Clock */
emilmont	77:869cf507173a	120
Kojto	99:dbbf35b96557	121	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto	99:dbbf35b96557	122	This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto	99:dbbf35b96557	123	through FMC_BCR2..4 registers.
Kojto	99:dbbf35b96557	124	This parameter can be a value of @ref FMC_Write_FIFO
Kojto	99:dbbf35b96557	125	This mode is available only for the STM32F446xx devices */
Kojto	99:dbbf35b96557	126
Kojto	99:dbbf35b96557	127	uint32_t PageSize; /*!< Specifies the memory page size.
Kojto	99:dbbf35b96557	128	This parameter can be a value of @ref FMC_Page_Size
Kojto	99:dbbf35b96557	129	This mode is available only for the STM32F446xx devices */
Kojto	99:dbbf35b96557	130
emilmont	77:869cf507173a	131	}FMC_NORSRAM_InitTypeDef;
emilmont	77:869cf507173a	132
emilmont	77:869cf507173a	133	/**
Kojto	99:dbbf35b96557	134	* @brief FMC NORSRAM Timing parameters structure definition
emilmont	77:869cf507173a	135	*/
emilmont	77:869cf507173a	136	typedef struct
emilmont	77:869cf507173a	137	{
emilmont	77:869cf507173a	138	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	139	the duration of the address setup time.
emilmont	77:869cf507173a	140	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
emilmont	77:869cf507173a	141	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	85:024bf7f99721	142
emilmont	77:869cf507173a	143	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	144	the duration of the address hold time.
emilmont	77:869cf507173a	145	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
emilmont	77:869cf507173a	146	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	85:024bf7f99721	147
emilmont	77:869cf507173a	148	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	149	the duration of the data setup time.
emilmont	77:869cf507173a	150	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
emilmont	77:869cf507173a	151	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
emilmont	77:869cf507173a	152	NOR Flash memories. */
bogdanm	85:024bf7f99721	153
emilmont	77:869cf507173a	154	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	155	the duration of the bus turnaround.
emilmont	77:869cf507173a	156	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
emilmont	77:869cf507173a	157	@note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm	85:024bf7f99721	158
emilmont	77:869cf507173a	159	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
emilmont	77:869cf507173a	160	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
emilmont	77:869cf507173a	161	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
emilmont	77:869cf507173a	162	accesses. */
bogdanm	85:024bf7f99721	163
emilmont	77:869cf507173a	164	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
emilmont	77:869cf507173a	165	to the memory before getting the first data.
emilmont	77:869cf507173a	166	The parameter value depends on the memory type as shown below:
emilmont	77:869cf507173a	167	- It must be set to 0 in case of a CRAM
emilmont	77:869cf507173a	168	- It is don't care in asynchronous NOR, SRAM or ROM accesses
emilmont	77:869cf507173a	169	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
emilmont	77:869cf507173a	170	with synchronous burst mode enable */
bogdanm	85:024bf7f99721	171
emilmont	77:869cf507173a	172	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
emilmont	77:869cf507173a	173	This parameter can be a value of @ref FMC_Access_Mode */
emilmont	77:869cf507173a	174	}FMC_NORSRAM_TimingTypeDef;
emilmont	77:869cf507173a	175
emilmont	77:869cf507173a	176	/**
Kojto	99:dbbf35b96557	177	* @brief FMC NAND Configuration Structure definition
emilmont	77:869cf507173a	178	*/
emilmont	77:869cf507173a	179	typedef struct
emilmont	77:869cf507173a	180	{
emilmont	77:869cf507173a	181	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm	85:024bf7f99721	182	This parameter can be a value of @ref FMC_NAND_Bank */
bogdanm	85:024bf7f99721	183
emilmont	77:869cf507173a	184	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
emilmont	77:869cf507173a	185	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	85:024bf7f99721	186
emilmont	77:869cf507173a	187	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
emilmont	77:869cf507173a	188	This parameter can be any value of @ref FMC_NAND_Data_Width */
bogdanm	85:024bf7f99721	189
emilmont	77:869cf507173a	190	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
emilmont	77:869cf507173a	191	This parameter can be any value of @ref FMC_ECC */
bogdanm	85:024bf7f99721	192
emilmont	77:869cf507173a	193	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
emilmont	77:869cf507173a	194	This parameter can be any value of @ref FMC_ECC_Page_Size */
bogdanm	85:024bf7f99721	195
emilmont	77:869cf507173a	196	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	197	delay between CLE low and RE low.
emilmont	77:869cf507173a	198	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	199
emilmont	77:869cf507173a	200	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	201	delay between ALE low and RE low.
emilmont	77:869cf507173a	202	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	203	}FMC_NAND_InitTypeDef;
emilmont	77:869cf507173a	204
emilmont	77:869cf507173a	205	/**
Kojto	99:dbbf35b96557	206	* @brief FMC NAND/PCCARD Timing parameters structure definition
emilmont	77:869cf507173a	207	*/
emilmont	77:869cf507173a	208	typedef struct
emilmont	77:869cf507173a	209	{
emilmont	77:869cf507173a	210	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
emilmont	77:869cf507173a	211	the command assertion for NAND-Flash read or write access
emilmont	77:869cf507173a	212	to common/Attribute or I/O memory space (depending on
emilmont	77:869cf507173a	213	the memory space timing to be configured).
emilmont	77:869cf507173a	214	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	215
emilmont	77:869cf507173a	216	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
emilmont	77:869cf507173a	217	command for NAND-Flash read or write access to
emilmont	77:869cf507173a	218	common/Attribute or I/O memory space (depending on the
emilmont	77:869cf507173a	219	memory space timing to be configured).
emilmont	77:869cf507173a	220	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	221
emilmont	77:869cf507173a	222	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
emilmont	77:869cf507173a	223	(and data for write access) after the command de-assertion
emilmont	77:869cf507173a	224	for NAND-Flash read or write access to common/Attribute
emilmont	77:869cf507173a	225	or I/O memory space (depending on the memory space timing
emilmont	77:869cf507173a	226	to be configured).
emilmont	77:869cf507173a	227	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	228
emilmont	77:869cf507173a	229	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
emilmont	77:869cf507173a	230	data bus is kept in HiZ after the start of a NAND-Flash
emilmont	77:869cf507173a	231	write access to common/Attribute or I/O memory space (depending
emilmont	77:869cf507173a	232	on the memory space timing to be configured).
emilmont	77:869cf507173a	233	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
emilmont	77:869cf507173a	234	}FMC_NAND_PCC_TimingTypeDef;
emilmont	77:869cf507173a	235
emilmont	77:869cf507173a	236	/**
Kojto	99:dbbf35b96557	237	* @brief FMC NAND Configuration Structure definition
emilmont	77:869cf507173a	238	*/
emilmont	77:869cf507173a	239	typedef struct
emilmont	77:869cf507173a	240	{
emilmont	77:869cf507173a	241	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
emilmont	77:869cf507173a	242	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	85:024bf7f99721	243
emilmont	77:869cf507173a	244	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	245	delay between CLE low and RE low.
emilmont	77:869cf507173a	246	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	247
emilmont	77:869cf507173a	248	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	249	delay between ALE low and RE low.
emilmont	77:869cf507173a	250	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	251	}FMC_PCCARD_InitTypeDef;
emilmont	77:869cf507173a	252
emilmont	77:869cf507173a	253	/**
Kojto	99:dbbf35b96557	254	* @brief FMC SDRAM Configuration Structure definition
emilmont	77:869cf507173a	255	*/
emilmont	77:869cf507173a	256	typedef struct
emilmont	77:869cf507173a	257	{
emilmont	77:869cf507173a	258	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
bogdanm	85:024bf7f99721	259	This parameter can be a value of @ref FMC_SDRAM_Bank */
bogdanm	85:024bf7f99721	260
emilmont	77:869cf507173a	261	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
emilmont	77:869cf507173a	262	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
bogdanm	85:024bf7f99721	263
emilmont	77:869cf507173a	264	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
emilmont	77:869cf507173a	265	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
bogdanm	85:024bf7f99721	266
emilmont	77:869cf507173a	267	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
emilmont	77:869cf507173a	268	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
bogdanm	85:024bf7f99721	269
emilmont	77:869cf507173a	270	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
emilmont	77:869cf507173a	271	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
bogdanm	85:024bf7f99721	272
emilmont	77:869cf507173a	273	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
emilmont	77:869cf507173a	274	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
bogdanm	85:024bf7f99721	275
emilmont	77:869cf507173a	276	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
emilmont	77:869cf507173a	277	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
bogdanm	85:024bf7f99721	278
emilmont	77:869cf507173a	279	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
emilmont	77:869cf507173a	280	to disable the clock before changing frequency.
emilmont	77:869cf507173a	281	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
bogdanm	85:024bf7f99721	282
emilmont	77:869cf507173a	283	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
emilmont	77:869cf507173a	284	commands during the CAS latency and stores data in the Read FIFO.
emilmont	77:869cf507173a	285	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
bogdanm	85:024bf7f99721	286
emilmont	77:869cf507173a	287	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
emilmont	77:869cf507173a	288	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
emilmont	77:869cf507173a	289	}FMC_SDRAM_InitTypeDef;
emilmont	77:869cf507173a	290
emilmont	77:869cf507173a	291	/**
Kojto	99:dbbf35b96557	292	* @brief FMC SDRAM Timing parameters structure definition
emilmont	77:869cf507173a	293	*/
emilmont	77:869cf507173a	294	typedef struct
emilmont	77:869cf507173a	295	{
emilmont	77:869cf507173a	296	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
emilmont	77:869cf507173a	297	an active or Refresh command in number of memory clock cycles.
emilmont	77:869cf507173a	298	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	299
emilmont	77:869cf507173a	300	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
emilmont	77:869cf507173a	301	issuing the Activate command in number of memory clock cycles.
emilmont	77:869cf507173a	302	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	303
emilmont	77:869cf507173a	304	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
emilmont	77:869cf507173a	305	cycles.
emilmont	77:869cf507173a	306	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	307
emilmont	77:869cf507173a	308	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
emilmont	77:869cf507173a	309	and the delay between two consecutive Refresh commands in number of
emilmont	77:869cf507173a	310	memory clock cycles.
emilmont	77:869cf507173a	311	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	312
emilmont	77:869cf507173a	313	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
emilmont	77:869cf507173a	314	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	315
emilmont	77:869cf507173a	316	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
emilmont	77:869cf507173a	317	in number of memory clock cycles.
emilmont	77:869cf507173a	318	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	319
emilmont	77:869cf507173a	320	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
emilmont	77:869cf507173a	321	command in number of memory clock cycles.
emilmont	77:869cf507173a	322	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	323	}FMC_SDRAM_TimingTypeDef;
emilmont	77:869cf507173a	324
emilmont	77:869cf507173a	325	/**
Kojto	99:dbbf35b96557	326	* @brief SDRAM command parameters structure definition
emilmont	77:869cf507173a	327	*/
emilmont	77:869cf507173a	328	typedef struct
emilmont	77:869cf507173a	329	{
emilmont	77:869cf507173a	330	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
bogdanm	85:024bf7f99721	331	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
bogdanm	85:024bf7f99721	332
emilmont	77:869cf507173a	333	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
bogdanm	85:024bf7f99721	334	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
bogdanm	85:024bf7f99721	335
emilmont	77:869cf507173a	336	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
emilmont	77:869cf507173a	337	in auto refresh mode.
bogdanm	85:024bf7f99721	338	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	339	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
emilmont	77:869cf507173a	340	}FMC_SDRAM_CommandTypeDef;
Kojto	99:dbbf35b96557	341	/**
Kojto	99:dbbf35b96557	342	* @}
Kojto	99:dbbf35b96557	343	*/
emilmont	77:869cf507173a	344
Kojto	99:dbbf35b96557	345	/* Private constants ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	346	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
emilmont	77:869cf507173a	347	* @{
bogdanm	85:024bf7f99721	348	*/
bogdanm	85:024bf7f99721	349
Kojto	99:dbbf35b96557	350	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
Kojto	99:dbbf35b96557	351	* @{
Kojto	99:dbbf35b96557	352	*/
Kojto	99:dbbf35b96557	353	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
emilmont	77:869cf507173a	354	* @{
emilmont	77:869cf507173a	355	*/
emilmont	77:869cf507173a	356	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	357	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	358	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	359	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
emilmont	77:869cf507173a	360	/**
emilmont	77:869cf507173a	361	* @}
emilmont	77:869cf507173a	362	*/
emilmont	77:869cf507173a	363
Kojto	99:dbbf35b96557	364	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
emilmont	77:869cf507173a	365	* @{
emilmont	77:869cf507173a	366	*/
emilmont	77:869cf507173a	367	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	368	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
emilmont	77:869cf507173a	369	/**
emilmont	77:869cf507173a	370	* @}
emilmont	77:869cf507173a	371	*/
emilmont	77:869cf507173a	372
Kojto	99:dbbf35b96557	373	/** @defgroup FMC_Memory_Type FMC Memory Type
emilmont	77:869cf507173a	374	* @{
emilmont	77:869cf507173a	375	*/
emilmont	77:869cf507173a	376	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
emilmont	77:869cf507173a	377	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
emilmont	77:869cf507173a	378	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
emilmont	77:869cf507173a	379	/**
emilmont	77:869cf507173a	380	* @}
emilmont	77:869cf507173a	381	*/
emilmont	77:869cf507173a	382
Kojto	99:dbbf35b96557	383	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
emilmont	77:869cf507173a	384	* @{
emilmont	77:869cf507173a	385	*/
emilmont	77:869cf507173a	386	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	387	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	388	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	389	/**
emilmont	77:869cf507173a	390	* @}
emilmont	77:869cf507173a	391	*/
emilmont	77:869cf507173a	392
Kojto	99:dbbf35b96557	393	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
emilmont	77:869cf507173a	394	* @{
emilmont	77:869cf507173a	395	*/
emilmont	77:869cf507173a	396	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
emilmont	77:869cf507173a	397	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	398	/**
emilmont	77:869cf507173a	399	* @}
emilmont	77:869cf507173a	400	*/
emilmont	77:869cf507173a	401
Kojto	99:dbbf35b96557	402	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
emilmont	77:869cf507173a	403	* @{
emilmont	77:869cf507173a	404	*/
emilmont	77:869cf507173a	405	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	406	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
emilmont	77:869cf507173a	407	/**
emilmont	77:869cf507173a	408	* @}
emilmont	77:869cf507173a	409	*/
emilmont	77:869cf507173a	410
Kojto	99:dbbf35b96557	411	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
emilmont	77:869cf507173a	412	* @{
emilmont	77:869cf507173a	413	*/
emilmont	77:869cf507173a	414	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
emilmont	77:869cf507173a	415	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
emilmont	77:869cf507173a	416	/**
emilmont	77:869cf507173a	417	* @}
emilmont	77:869cf507173a	418	*/
emilmont	77:869cf507173a	419
Kojto	99:dbbf35b96557	420	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
emilmont	77:869cf507173a	421	* @{
emilmont	77:869cf507173a	422	*/
Kojto	99:dbbf35b96557	423	/** @note This mode is not available for the STM32F446xx devices
Kojto	99:dbbf35b96557	424	*/
Kojto	99:dbbf35b96557	425	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	426	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
emilmont	77:869cf507173a	427	/**
emilmont	77:869cf507173a	428	* @}
emilmont	77:869cf507173a	429	*/
emilmont	77:869cf507173a	430
Kojto	99:dbbf35b96557	431	/** @defgroup FMC_Wait_Timing FMC Wait Timing
Kojto	99:dbbf35b96557	432	* @{
Kojto	99:dbbf35b96557	433	*/
Kojto	99:dbbf35b96557	434	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	435	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
Kojto	99:dbbf35b96557	436	/**
Kojto	99:dbbf35b96557	437	* @}
Kojto	99:dbbf35b96557	438	*/
Kojto	99:dbbf35b96557	439
Kojto	99:dbbf35b96557	440	/** @defgroup FMC_Write_Operation FMC Write Operation
emilmont	77:869cf507173a	441	* @{
emilmont	77:869cf507173a	442	*/
emilmont	77:869cf507173a	443	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	444	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
emilmont	77:869cf507173a	445	/**
emilmont	77:869cf507173a	446	* @}
emilmont	77:869cf507173a	447	*/
emilmont	77:869cf507173a	448
Kojto	99:dbbf35b96557	449	/** @defgroup FMC_Wait_Signal FMC Wait Signal
emilmont	77:869cf507173a	450	* @{
emilmont	77:869cf507173a	451	*/
emilmont	77:869cf507173a	452	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	453	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
emilmont	77:869cf507173a	454	/**
emilmont	77:869cf507173a	455	* @}
emilmont	77:869cf507173a	456	*/
emilmont	77:869cf507173a	457
Kojto	99:dbbf35b96557	458	/** @defgroup FMC_Extended_Mode FMC Extended Mode
Kojto	99:dbbf35b96557	459	* @{
Kojto	99:dbbf35b96557	460	*/
Kojto	99:dbbf35b96557	461	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	462	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
Kojto	99:dbbf35b96557	463	/**
Kojto	99:dbbf35b96557	464	* @}
Kojto	99:dbbf35b96557	465	*/
Kojto	99:dbbf35b96557	466
Kojto	99:dbbf35b96557	467	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
emilmont	77:869cf507173a	468	* @{
emilmont	77:869cf507173a	469	*/
emilmont	77:869cf507173a	470	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	471	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
emilmont	77:869cf507173a	472	/**
emilmont	77:869cf507173a	473	* @}
emilmont	77:869cf507173a	474	*/
emilmont	77:869cf507173a	475
Kojto	99:dbbf35b96557	476	/** @defgroup FMC_Page_Size FMC Page Size
Kojto	99:dbbf35b96557	477	* @note These values are available only for the STM32F446xx devices.
Kojto	99:dbbf35b96557	478	* @{
Kojto	99:dbbf35b96557	479	*/
Kojto	99:dbbf35b96557	480	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	481	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
Kojto	99:dbbf35b96557	482	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
Kojto	99:dbbf35b96557	483	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
Kojto	99:dbbf35b96557	484	/**
Kojto	99:dbbf35b96557	485	* @}
Kojto	99:dbbf35b96557	486	*/
Kojto	99:dbbf35b96557	487
Kojto	99:dbbf35b96557	488	/** @defgroup FMC_Write_FIFO FMC Write FIFO
Kojto	99:dbbf35b96557	489	* @note These values are available only for the STM32F446xx devices.
Kojto	99:dbbf35b96557	490	* @{
Kojto	99:dbbf35b96557	491	*/
Kojto	99:dbbf35b96557	492	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	493	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
Kojto	99:dbbf35b96557	494	/**
Kojto	99:dbbf35b96557	495	* @}
Kojto	99:dbbf35b96557	496	*/
Kojto	99:dbbf35b96557	497
Kojto	99:dbbf35b96557	498	/** @defgroup FMC_Write_Burst FMC Write Burst
emilmont	77:869cf507173a	499	* @{
emilmont	77:869cf507173a	500	*/
emilmont	77:869cf507173a	501	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	502	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
emilmont	77:869cf507173a	503	/**
emilmont	77:869cf507173a	504	* @}
emilmont	77:869cf507173a	505	*/
emilmont	77:869cf507173a	506
Kojto	99:dbbf35b96557	507	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
emilmont	77:869cf507173a	508	* @{
emilmont	77:869cf507173a	509	*/
Kojto	99:dbbf35b96557	510	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	511	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
emilmont	77:869cf507173a	512	/**
emilmont	77:869cf507173a	513	* @}
emilmont	77:869cf507173a	514	*/
Kojto	99:dbbf35b96557	515
Kojto	99:dbbf35b96557	516	/** @defgroup FMC_Access_Mode FMC Access Mode
emilmont	77:869cf507173a	517	* @{
emilmont	77:869cf507173a	518	*/
emilmont	77:869cf507173a	519	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
emilmont	77:869cf507173a	520	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
emilmont	77:869cf507173a	521	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
emilmont	77:869cf507173a	522	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
emilmont	77:869cf507173a	523	/**
emilmont	77:869cf507173a	524	* @}
emilmont	77:869cf507173a	525	*/
emilmont	77:869cf507173a	526
emilmont	77:869cf507173a	527	/**
emilmont	77:869cf507173a	528	* @}
Kojto	99:dbbf35b96557	529	*/
emilmont	77:869cf507173a	530
Kojto	99:dbbf35b96557	531	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
emilmont	77:869cf507173a	532	* @{
emilmont	77:869cf507173a	533	*/
Kojto	99:dbbf35b96557	534	/** @defgroup FMC_NAND_Bank FMC NAND Bank
emilmont	77:869cf507173a	535	* @{
Kojto	99:dbbf35b96557	536	*/
emilmont	77:869cf507173a	537	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
Kojto	99:dbbf35b96557	538	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	539	/**
emilmont	77:869cf507173a	540	* @}
emilmont	77:869cf507173a	541	*/
emilmont	77:869cf507173a	542
Kojto	99:dbbf35b96557	543	/** @defgroup FMC_Wait_feature FMC Wait feature
emilmont	77:869cf507173a	544	* @{
emilmont	77:869cf507173a	545	*/
emilmont	77:869cf507173a	546	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	547	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
emilmont	77:869cf507173a	548	/**
emilmont	77:869cf507173a	549	* @}
emilmont	77:869cf507173a	550	*/
emilmont	77:869cf507173a	551
Kojto	99:dbbf35b96557	552	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
emilmont	77:869cf507173a	553	* @{
emilmont	77:869cf507173a	554	*/
emilmont	77:869cf507173a	555	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
emilmont	77:869cf507173a	556	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
emilmont	77:869cf507173a	557	/**
emilmont	77:869cf507173a	558	* @}
emilmont	77:869cf507173a	559	*/
emilmont	77:869cf507173a	560
Kojto	99:dbbf35b96557	561	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
emilmont	77:869cf507173a	562	* @{
emilmont	77:869cf507173a	563	*/
emilmont	77:869cf507173a	564	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	565	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	566	/**
emilmont	77:869cf507173a	567	* @}
emilmont	77:869cf507173a	568	*/
emilmont	77:869cf507173a	569
Kojto	99:dbbf35b96557	570	/** @defgroup FMC_ECC FMC ECC
emilmont	77:869cf507173a	571	* @{
emilmont	77:869cf507173a	572	*/
emilmont	77:869cf507173a	573	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	574	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
emilmont	77:869cf507173a	575	/**
emilmont	77:869cf507173a	576	* @}
emilmont	77:869cf507173a	577	*/
emilmont	77:869cf507173a	578
Kojto	99:dbbf35b96557	579	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
emilmont	77:869cf507173a	580	* @{
emilmont	77:869cf507173a	581	*/
emilmont	77:869cf507173a	582	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	583	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
emilmont	77:869cf507173a	584	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
emilmont	77:869cf507173a	585	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
emilmont	77:869cf507173a	586	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
emilmont	77:869cf507173a	587	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
emilmont	77:869cf507173a	588	/**
emilmont	77:869cf507173a	589	* @}
emilmont	77:869cf507173a	590	*/
Kojto	99:dbbf35b96557	591
emilmont	77:869cf507173a	592	/**
emilmont	77:869cf507173a	593	* @}
Kojto	99:dbbf35b96557	594	*/
emilmont	77:869cf507173a	595
Kojto	99:dbbf35b96557	596	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
emilmont	77:869cf507173a	597	* @{
emilmont	77:869cf507173a	598	*/
Kojto	99:dbbf35b96557	599	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
emilmont	77:869cf507173a	600	* @{
emilmont	77:869cf507173a	601	*/
Kojto	99:dbbf35b96557	602	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	603	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	604	/**
emilmont	77:869cf507173a	605	* @}
emilmont	77:869cf507173a	606	*/
emilmont	77:869cf507173a	607
Kojto	99:dbbf35b96557	608	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
emilmont	77:869cf507173a	609	* @{
emilmont	77:869cf507173a	610	*/
emilmont	77:869cf507173a	611	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	612	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	613	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	614	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
emilmont	77:869cf507173a	615	/**
emilmont	77:869cf507173a	616	* @}
emilmont	77:869cf507173a	617	*/
emilmont	77:869cf507173a	618
Kojto	99:dbbf35b96557	619	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
emilmont	77:869cf507173a	620	* @{
emilmont	77:869cf507173a	621	*/
emilmont	77:869cf507173a	622	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	623	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	624	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	625	/**
emilmont	77:869cf507173a	626	* @}
emilmont	77:869cf507173a	627	*/
emilmont	77:869cf507173a	628
Kojto	99:dbbf35b96557	629	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
emilmont	77:869cf507173a	630	* @{
emilmont	77:869cf507173a	631	*/
emilmont	77:869cf507173a	632	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	633	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	634	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	635	/**
emilmont	77:869cf507173a	636	* @}
emilmont	77:869cf507173a	637	*/
emilmont	77:869cf507173a	638
Kojto	99:dbbf35b96557	639	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
emilmont	77:869cf507173a	640	* @{
emilmont	77:869cf507173a	641	*/
emilmont	77:869cf507173a	642	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	643	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	644	/**
emilmont	77:869cf507173a	645	* @}
emilmont	77:869cf507173a	646	*/
emilmont	77:869cf507173a	647
Kojto	99:dbbf35b96557	648	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
emilmont	77:869cf507173a	649	* @{
emilmont	77:869cf507173a	650	*/
emilmont	77:869cf507173a	651	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	652	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	653	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
emilmont	77:869cf507173a	654	/**
emilmont	77:869cf507173a	655	* @}
emilmont	77:869cf507173a	656	*/
emilmont	77:869cf507173a	657
Kojto	99:dbbf35b96557	658	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
emilmont	77:869cf507173a	659	* @{
emilmont	77:869cf507173a	660	*/
emilmont	77:869cf507173a	661	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	662	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
emilmont	77:869cf507173a	663
emilmont	77:869cf507173a	664	/**
emilmont	77:869cf507173a	665	* @}
emilmont	77:869cf507173a	666	*/
emilmont	77:869cf507173a	667
Kojto	99:dbbf35b96557	668	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
emilmont	77:869cf507173a	669	* @{
emilmont	77:869cf507173a	670	*/
emilmont	77:869cf507173a	671	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	672	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	673	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
emilmont	77:869cf507173a	674	/**
emilmont	77:869cf507173a	675	* @}
emilmont	77:869cf507173a	676	*/
emilmont	77:869cf507173a	677
Kojto	99:dbbf35b96557	678	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
emilmont	77:869cf507173a	679	* @{
emilmont	77:869cf507173a	680	*/
emilmont	77:869cf507173a	681	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	682	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
emilmont	77:869cf507173a	683	/**
emilmont	77:869cf507173a	684	* @}
emilmont	77:869cf507173a	685	*/
emilmont	77:869cf507173a	686
Kojto	99:dbbf35b96557	687	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
emilmont	77:869cf507173a	688	* @{
emilmont	77:869cf507173a	689	*/
emilmont	77:869cf507173a	690	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	691	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	692	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	693	/**
emilmont	77:869cf507173a	694	* @}
emilmont	77:869cf507173a	695	*/
emilmont	77:869cf507173a	696
Kojto	99:dbbf35b96557	697	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
emilmont	77:869cf507173a	698	* @{
emilmont	77:869cf507173a	699	*/
emilmont	77:869cf507173a	700	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	701	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
emilmont	77:869cf507173a	702	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
emilmont	77:869cf507173a	703	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
emilmont	77:869cf507173a	704	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
emilmont	77:869cf507173a	705	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
emilmont	77:869cf507173a	706	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
emilmont	77:869cf507173a	707	/**
emilmont	77:869cf507173a	708	* @}
emilmont	77:869cf507173a	709	*/
emilmont	77:869cf507173a	710
Kojto	99:dbbf35b96557	711	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
emilmont	77:869cf507173a	712	* @{
emilmont	77:869cf507173a	713	*/
emilmont	77:869cf507173a	714	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
emilmont	77:869cf507173a	715	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
emilmont	77:869cf507173a	716	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
emilmont	77:869cf507173a	717	/**
emilmont	77:869cf507173a	718	* @}
emilmont	77:869cf507173a	719	*/
emilmont	77:869cf507173a	720
Kojto	99:dbbf35b96557	721	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
emilmont	77:869cf507173a	722	* @{
emilmont	77:869cf507173a	723	*/
emilmont	77:869cf507173a	724	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	725	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
emilmont	77:869cf507173a	726	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
emilmont	77:869cf507173a	727	/**
emilmont	77:869cf507173a	728	* @}
emilmont	77:869cf507173a	729	*/
Kojto	99:dbbf35b96557	730
emilmont	77:869cf507173a	731	/**
emilmont	77:869cf507173a	732	* @}
emilmont	77:869cf507173a	733	*/
emilmont	77:869cf507173a	734
Kojto	99:dbbf35b96557	735	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
emilmont	77:869cf507173a	736	* @{
emilmont	77:869cf507173a	737	*/
emilmont	77:869cf507173a	738	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
emilmont	77:869cf507173a	739	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
emilmont	77:869cf507173a	740	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
emilmont	77:869cf507173a	741	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
emilmont	77:869cf507173a	742	/**
emilmont	77:869cf507173a	743	* @}
emilmont	77:869cf507173a	744	*/
emilmont	77:869cf507173a	745
Kojto	99:dbbf35b96557	746	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
emilmont	77:869cf507173a	747	* @{
emilmont	77:869cf507173a	748	*/
emilmont	77:869cf507173a	749	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
emilmont	77:869cf507173a	750	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
emilmont	77:869cf507173a	751	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
emilmont	77:869cf507173a	752	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
emilmont	77:869cf507173a	753	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
emilmont	77:869cf507173a	754	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
emilmont	77:869cf507173a	755	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
emilmont	77:869cf507173a	756	/**
emilmont	77:869cf507173a	757	* @}
emilmont	77:869cf507173a	758	*/
emilmont	77:869cf507173a	759
Kojto	99:dbbf35b96557	760	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
Kojto	99:dbbf35b96557	761	* @{
Kojto	99:dbbf35b96557	762	*/
Kojto	99:dbbf35b96557	763	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	764	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
Kojto	99:dbbf35b96557	765	#else
Kojto	99:dbbf35b96557	766	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
Kojto	99:dbbf35b96557	767	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
Kojto	99:dbbf35b96557	768	#endif /* defined(STM32F446xx) */
Kojto	99:dbbf35b96557	769	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
Kojto	99:dbbf35b96557	770	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
Kojto	99:dbbf35b96557	771	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
Kojto	99:dbbf35b96557	772
emilmont	77:869cf507173a	773
Kojto	99:dbbf35b96557	774	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	775	#define FMC_NAND_DEVICE FMC_Bank3
Kojto	99:dbbf35b96557	776	#else
Kojto	99:dbbf35b96557	777	#define FMC_NAND_DEVICE FMC_Bank2_3
Kojto	99:dbbf35b96557	778	#define FMC_PCCARD_DEVICE FMC_Bank4
Kojto	99:dbbf35b96557	779	#endif /* defined(STM32F446xx) */
Kojto	99:dbbf35b96557	780	#define FMC_NORSRAM_DEVICE FMC_Bank1
Kojto	99:dbbf35b96557	781	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
Kojto	99:dbbf35b96557	782	#define FMC_SDRAM_DEVICE FMC_Bank5_6
Kojto	99:dbbf35b96557	783	/**
Kojto	99:dbbf35b96557	784	* @}
Kojto	99:dbbf35b96557	785	*/
Kojto	99:dbbf35b96557	786
Kojto	99:dbbf35b96557	787	/**
Kojto	99:dbbf35b96557	788	* @}
Kojto	99:dbbf35b96557	789	*/
Kojto	99:dbbf35b96557	790
Kojto	99:dbbf35b96557	791	/* Private macro -------------------------------------------------------------*/
Kojto	99:dbbf35b96557	792	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
Kojto	99:dbbf35b96557	793	* @{
Kojto	99:dbbf35b96557	794	*/
Kojto	99:dbbf35b96557	795
Kojto	99:dbbf35b96557	796	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
emilmont	77:869cf507173a	797	* @brief macros to handle NOR device enable/disable and read/write operations
emilmont	77:869cf507173a	798	* @{
emilmont	77:869cf507173a	799	*/
emilmont	77:869cf507173a	800	/**
emilmont	77:869cf507173a	801	* @brief Enable the NORSRAM device access.
emilmont	77:869cf507173a	802	* @param __INSTANCE__: FMC_NORSRAM Instance
emilmont	77:869cf507173a	803	* @param __BANK__: FMC_NORSRAM Bank
emilmont	77:869cf507173a	804	* @retval None
emilmont	77:869cf507173a	805	*/
emilmont	77:869cf507173a	806	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
emilmont	77:869cf507173a	807
emilmont	77:869cf507173a	808	/**
emilmont	77:869cf507173a	809	* @brief Disable the NORSRAM device access.
emilmont	77:869cf507173a	810	* @param __INSTANCE__: FMC_NORSRAM Instance
emilmont	77:869cf507173a	811	* @param __BANK__: FMC_NORSRAM Bank
emilmont	77:869cf507173a	812	* @retval None
emilmont	77:869cf507173a	813	*/
emilmont	77:869cf507173a	814	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
emilmont	77:869cf507173a	815	/**
emilmont	77:869cf507173a	816	* @}
emilmont	77:869cf507173a	817	*/
emilmont	77:869cf507173a	818
Kojto	99:dbbf35b96557	819	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
emilmont	77:869cf507173a	820	* @brief macros to handle NAND device enable/disable
emilmont	77:869cf507173a	821	* @{
emilmont	77:869cf507173a	822	*/
Kojto	99:dbbf35b96557	823	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	824	/**
Kojto	99:dbbf35b96557	825	* @brief Enable the NAND device access.
Kojto	99:dbbf35b96557	826	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	827	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	828	* @retval None
Kojto	99:dbbf35b96557	829	*/
Kojto	99:dbbf35b96557	830	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
Kojto	99:dbbf35b96557	831
Kojto	99:dbbf35b96557	832	/**
Kojto	99:dbbf35b96557	833	* @brief Disable the NAND device access.
Kojto	99:dbbf35b96557	834	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	835	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	836	* @retval None
Kojto	99:dbbf35b96557	837	*/
Kojto	99:dbbf35b96557	838	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
Kojto	99:dbbf35b96557	839	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
emilmont	77:869cf507173a	840	/**
emilmont	77:869cf507173a	841	* @brief Enable the NAND device access.
emilmont	77:869cf507173a	842	* @param __INSTANCE__: FMC_NAND Instance
emilmont	77:869cf507173a	843	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	844	* @retval None
emilmont	77:869cf507173a	845	*/
emilmont	77:869cf507173a	846	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
bogdanm	85:024bf7f99721	847	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
emilmont	77:869cf507173a	848
emilmont	77:869cf507173a	849	/**
emilmont	77:869cf507173a	850	* @brief Disable the NAND device access.
emilmont	77:869cf507173a	851	* @param __INSTANCE__: FMC_NAND Instance
emilmont	77:869cf507173a	852	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	853	* @retval None
bogdanm	85:024bf7f99721	854	*/
emilmont	77:869cf507173a	855	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
bogdanm	85:024bf7f99721	856	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
Kojto	99:dbbf35b96557	857
Kojto	99:dbbf35b96557	858	#endif /* defined(STM32F446xx)*/
emilmont	77:869cf507173a	859	/**
emilmont	77:869cf507173a	860	* @}
emilmont	77:869cf507173a	861	*/
Kojto	99:dbbf35b96557	862	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	863	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
emilmont	77:869cf507173a	864	* @brief macros to handle SRAM read/write operations
emilmont	77:869cf507173a	865	* @{
emilmont	77:869cf507173a	866	*/
emilmont	77:869cf507173a	867	/**
emilmont	77:869cf507173a	868	* @brief Enable the PCCARD device access.
emilmont	77:869cf507173a	869	* @param __INSTANCE__: FMC_PCCARD Instance
emilmont	77:869cf507173a	870	* @retval None
emilmont	77:869cf507173a	871	*/
emilmont	77:869cf507173a	872	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
emilmont	77:869cf507173a	873
emilmont	77:869cf507173a	874	/**
emilmont	77:869cf507173a	875	* @brief Disable the PCCARD device access.
emilmont	77:869cf507173a	876	* @param __INSTANCE__: FMC_PCCARD Instance
emilmont	77:869cf507173a	877	* @retval None
emilmont	77:869cf507173a	878	*/
emilmont	77:869cf507173a	879	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
emilmont	77:869cf507173a	880	/**
emilmont	77:869cf507173a	881	* @}
emilmont	77:869cf507173a	882	*/
Kojto	99:dbbf35b96557	883	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	99:dbbf35b96557	884
Kojto	99:dbbf35b96557	885	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
Kojto	99:dbbf35b96557	886	* @brief macros to handle FMC flags and interrupts
emilmont	77:869cf507173a	887	* @{
emilmont	77:869cf507173a	888	*/
Kojto	99:dbbf35b96557	889	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	890	/**
Kojto	99:dbbf35b96557	891	* @brief Enable the NAND device interrupt.
Kojto	99:dbbf35b96557	892	* @param __INSTANCE__: FMC_NAND instance
Kojto	99:dbbf35b96557	893	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	894	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	99:dbbf35b96557	895	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	896	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	99:dbbf35b96557	897	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	99:dbbf35b96557	898	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	99:dbbf35b96557	899	* @retval None
Kojto	99:dbbf35b96557	900	*/
Kojto	99:dbbf35b96557	901	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
emilmont	77:869cf507173a	902
emilmont	77:869cf507173a	903	/**
Kojto	99:dbbf35b96557	904	* @brief Disable the NAND device interrupt.
Kojto	99:dbbf35b96557	905	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	906	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	907	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	99:dbbf35b96557	908	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	909	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	99:dbbf35b96557	910	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	99:dbbf35b96557	911	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	99:dbbf35b96557	912	* @retval None
Kojto	99:dbbf35b96557	913	*/
Kojto	99:dbbf35b96557	914	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
Kojto	99:dbbf35b96557	915
Kojto	99:dbbf35b96557	916	/**
Kojto	99:dbbf35b96557	917	* @brief Get flag status of the NAND device.
Kojto	99:dbbf35b96557	918	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	919	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	920	* @param __FLAG__: FMC_NAND flag
Kojto	99:dbbf35b96557	921	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	922	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	99:dbbf35b96557	923	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	99:dbbf35b96557	924	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	99:dbbf35b96557	925	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	99:dbbf35b96557	926	* @retval The state of FLAG (SET or RESET).
Kojto	99:dbbf35b96557	927	*/
Kojto	99:dbbf35b96557	928	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
Kojto	99:dbbf35b96557	929	/**
Kojto	99:dbbf35b96557	930	* @brief Clear flag status of the NAND device.
Kojto	99:dbbf35b96557	931	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	932	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	933	* @param __FLAG__: FMC_NAND flag
Kojto	99:dbbf35b96557	934	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	935	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	99:dbbf35b96557	936	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	99:dbbf35b96557	937	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	99:dbbf35b96557	938	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	99:dbbf35b96557	939	* @retval None
Kojto	99:dbbf35b96557	940	*/
Kojto	99:dbbf35b96557	941	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
Kojto	99:dbbf35b96557	942	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	99:dbbf35b96557	943	/**
emilmont	77:869cf507173a	944	* @brief Enable the NAND device interrupt.
emilmont	77:869cf507173a	945	* @param __INSTANCE__: FMC_NAND instance
emilmont	77:869cf507173a	946	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	947	* @param __INTERRUPT__: FMC_NAND interrupt
emilmont	77:869cf507173a	948	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	949	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	950	* @arg FMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	951	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	952	* @retval None
emilmont	77:869cf507173a	953	*/
emilmont	77:869cf507173a	954	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
emilmont	77:869cf507173a	955	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
emilmont	77:869cf507173a	956
emilmont	77:869cf507173a	957	/**
emilmont	77:869cf507173a	958	* @brief Disable the NAND device interrupt.
Kojto	99:dbbf35b96557	959	* @param __INSTANCE__: FMC_NAND Instance
emilmont	77:869cf507173a	960	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	961	* @param __INTERRUPT__: FMC_NAND interrupt
emilmont	77:869cf507173a	962	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	963	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	964	* @arg FMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	965	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	966	* @retval None
emilmont	77:869cf507173a	967	*/
emilmont	77:869cf507173a	968	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
emilmont	77:869cf507173a	969	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
emilmont	77:869cf507173a	970
emilmont	77:869cf507173a	971	/**
emilmont	77:869cf507173a	972	* @brief Get flag status of the NAND device.
Kojto	99:dbbf35b96557	973	* @param __INSTANCE__: FMC_NAND Instance
emilmont	77:869cf507173a	974	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	975	* @param __FLAG__: FMC_NAND flag
emilmont	77:869cf507173a	976	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	977	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	978	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	979	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	980	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	981	* @retval The state of FLAG (SET or RESET).
emilmont	77:869cf507173a	982	*/
emilmont	77:869cf507173a	983	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
emilmont	77:869cf507173a	984	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
emilmont	77:869cf507173a	985	/**
emilmont	77:869cf507173a	986	* @brief Clear flag status of the NAND device.
Kojto	99:dbbf35b96557	987	* @param __INSTANCE__: FMC_NAND Instance
emilmont	77:869cf507173a	988	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	989	* @param __FLAG__: FMC_NAND flag
emilmont	77:869cf507173a	990	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	991	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	992	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	993	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	994	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	995	* @retval None
emilmont	77:869cf507173a	996	*/
emilmont	77:869cf507173a	997	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto	99:dbbf35b96557	998	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto	99:dbbf35b96557	999	#endif /* defined(STM32F446xx) */
Kojto	99:dbbf35b96557	1000
Kojto	99:dbbf35b96557	1001	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
emilmont	77:869cf507173a	1002	/**
emilmont	77:869cf507173a	1003	* @brief Enable the PCCARD device interrupt.
emilmont	77:869cf507173a	1004	* @param __INSTANCE__: FMC_PCCARD instance
emilmont	77:869cf507173a	1005	* @param __INTERRUPT__: FMC_PCCARD interrupt
emilmont	77:869cf507173a	1006	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1007	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	1008	* @arg FMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	1009	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	1010	* @retval None
emilmont	77:869cf507173a	1011	*/
emilmont	77:869cf507173a	1012	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
emilmont	77:869cf507173a	1013
emilmont	77:869cf507173a	1014	/**
emilmont	77:869cf507173a	1015	* @brief Disable the PCCARD device interrupt.
emilmont	77:869cf507173a	1016	* @param __INSTANCE__: FMC_PCCARD instance
emilmont	77:869cf507173a	1017	* @param __INTERRUPT__: FMC_PCCARD interrupt
emilmont	77:869cf507173a	1018	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1019	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	1020	* @arg FMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	1021	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	1022	* @retval None
emilmont	77:869cf507173a	1023	*/
emilmont	77:869cf507173a	1024	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	1025
emilmont	77:869cf507173a	1026	/**
emilmont	77:869cf507173a	1027	* @brief Get flag status of the PCCARD device.
emilmont	77:869cf507173a	1028	* @param __INSTANCE__: FMC_PCCARD instance
emilmont	77:869cf507173a	1029	* @param __FLAG__: FMC_PCCARD flag
emilmont	77:869cf507173a	1030	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1031	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	1032	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	1033	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	1034	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	1035	* @retval The state of FLAG (SET or RESET).
emilmont	77:869cf507173a	1036	*/
emilmont	77:869cf507173a	1037	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
emilmont	77:869cf507173a	1038
emilmont	77:869cf507173a	1039	/**
emilmont	77:869cf507173a	1040	* @brief Clear flag status of the PCCARD device.
emilmont	77:869cf507173a	1041	* @param __INSTANCE__: FMC_PCCARD instance
emilmont	77:869cf507173a	1042	* @param __FLAG__: FMC_PCCARD flag
emilmont	77:869cf507173a	1043	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1044	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	1045	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	1046	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	1047	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	1048	* @retval None
emilmont	77:869cf507173a	1049	*/
emilmont	77:869cf507173a	1050	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto	99:dbbf35b96557	1051	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	99:dbbf35b96557	1052
emilmont	77:869cf507173a	1053	/**
emilmont	77:869cf507173a	1054	* @brief Enable the SDRAM device interrupt.
emilmont	77:869cf507173a	1055	* @param __INSTANCE__: FMC_SDRAM instance
emilmont	77:869cf507173a	1056	* @param __INTERRUPT__: FMC_SDRAM interrupt
emilmont	77:869cf507173a	1057	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1058	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
emilmont	77:869cf507173a	1059	* @retval None
emilmont	77:869cf507173a	1060	*/
emilmont	77:869cf507173a	1061	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
emilmont	77:869cf507173a	1062
emilmont	77:869cf507173a	1063	/**
emilmont	77:869cf507173a	1064	* @brief Disable the SDRAM device interrupt.
emilmont	77:869cf507173a	1065	* @param __INSTANCE__: FMC_SDRAM instance
emilmont	77:869cf507173a	1066	* @param __INTERRUPT__: FMC_SDRAM interrupt
emilmont	77:869cf507173a	1067	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1068	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
emilmont	77:869cf507173a	1069	* @retval None
emilmont	77:869cf507173a	1070	*/
emilmont	77:869cf507173a	1071	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	1072
emilmont	77:869cf507173a	1073	/**
emilmont	77:869cf507173a	1074	* @brief Get flag status of the SDRAM device.
emilmont	77:869cf507173a	1075	* @param __INSTANCE__: FMC_SDRAM instance
emilmont	77:869cf507173a	1076	* @param __FLAG__: FMC_SDRAM flag
emilmont	77:869cf507173a	1077	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1078	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
emilmont	77:869cf507173a	1079	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
emilmont	77:869cf507173a	1080	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
emilmont	77:869cf507173a	1081	* @retval The state of FLAG (SET or RESET).
emilmont	77:869cf507173a	1082	*/
emilmont	77:869cf507173a	1083	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
emilmont	77:869cf507173a	1084
emilmont	77:869cf507173a	1085	/**
emilmont	77:869cf507173a	1086	* @brief Clear flag status of the SDRAM device.
emilmont	77:869cf507173a	1087	* @param __INSTANCE__: FMC_SDRAM instance
emilmont	77:869cf507173a	1088	* @param __FLAG__: FMC_SDRAM flag
emilmont	77:869cf507173a	1089	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1090	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
emilmont	77:869cf507173a	1091	* @retval None
emilmont	77:869cf507173a	1092	*/
emilmont	77:869cf507173a	1093	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
emilmont	77:869cf507173a	1094	/**
emilmont	77:869cf507173a	1095	* @}
Kojto	99:dbbf35b96557	1096	*/
Kojto	99:dbbf35b96557	1097
Kojto	99:dbbf35b96557	1098	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto	99:dbbf35b96557	1099	* @{
Kojto	99:dbbf35b96557	1100	*/
Kojto	99:dbbf35b96557	1101	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
Kojto	99:dbbf35b96557	1102	((BANK) == FMC_NORSRAM_BANK2) \|\| \
Kojto	99:dbbf35b96557	1103	((BANK) == FMC_NORSRAM_BANK3) \|\| \
Kojto	99:dbbf35b96557	1104	((BANK) == FMC_NORSRAM_BANK4))
Kojto	99:dbbf35b96557	1105
Kojto	99:dbbf35b96557	1106	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1107	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
Kojto	99:dbbf35b96557	1108
Kojto	99:dbbf35b96557	1109	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
Kojto	99:dbbf35b96557	1110	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
Kojto	99:dbbf35b96557	1111	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
Kojto	99:dbbf35b96557	1112
Kojto	99:dbbf35b96557	1113	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	99:dbbf35b96557	1114	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	99:dbbf35b96557	1115	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto	99:dbbf35b96557	1116
Kojto	99:dbbf35b96557	1117	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
Kojto	99:dbbf35b96557	1118	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
Kojto	99:dbbf35b96557	1119	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
Kojto	99:dbbf35b96557	1120	((__MODE__) == FMC_ACCESS_MODE_D))
Kojto	99:dbbf35b96557	1121
Kojto	99:dbbf35b96557	1122	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
Kojto	99:dbbf35b96557	1123	((BANK) == FMC_NAND_BANK3))
Kojto	99:dbbf35b96557	1124
Kojto	99:dbbf35b96557	1125	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1126	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto	99:dbbf35b96557	1127
Kojto	99:dbbf35b96557	1128	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
Kojto	99:dbbf35b96557	1129	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto	99:dbbf35b96557	1130
Kojto	99:dbbf35b96557	1131	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1132	((STATE) == FMC_NAND_ECC_ENABLE))
Kojto	99:dbbf35b96557	1133
Kojto	99:dbbf35b96557	1134	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
Kojto	99:dbbf35b96557	1135	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
Kojto	99:dbbf35b96557	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
Kojto	99:dbbf35b96557	1137	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
Kojto	99:dbbf35b96557	1138	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
Kojto	99:dbbf35b96557	1139	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto	99:dbbf35b96557	1140
Kojto	99:dbbf35b96557	1141	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
Kojto	99:dbbf35b96557	1142
Kojto	99:dbbf35b96557	1143	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
Kojto	99:dbbf35b96557	1144
Kojto	99:dbbf35b96557	1145	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
Kojto	99:dbbf35b96557	1146
Kojto	99:dbbf35b96557	1147	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
Kojto	99:dbbf35b96557	1148
Kojto	99:dbbf35b96557	1149	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
Kojto	99:dbbf35b96557	1150
Kojto	99:dbbf35b96557	1151	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
Kojto	99:dbbf35b96557	1152
Kojto	99:dbbf35b96557	1153	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
Kojto	99:dbbf35b96557	1154
Kojto	99:dbbf35b96557	1155	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
Kojto	99:dbbf35b96557	1156
Kojto	99:dbbf35b96557	1157	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
Kojto	99:dbbf35b96557	1158
Kojto	99:dbbf35b96557	1159	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
Kojto	99:dbbf35b96557	1160
Kojto	99:dbbf35b96557	1161	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1162	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
Kojto	99:dbbf35b96557	1163
Kojto	99:dbbf35b96557	1164	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
Kojto	99:dbbf35b96557	1165	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto	99:dbbf35b96557	1166
Kojto	99:dbbf35b96557	1167	#if !defined (STM32F446xx)
Kojto	99:dbbf35b96557	1168	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1169	((__MODE__) == FMC_WRAP_MODE_ENABLE))
Kojto	99:dbbf35b96557	1170	#endif /* !defined (STM32F446xx) */
Kojto	99:dbbf35b96557	1171
Kojto	99:dbbf35b96557	1172	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
Kojto	99:dbbf35b96557	1173	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
Kojto	99:dbbf35b96557	1174
Kojto	99:dbbf35b96557	1175	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1176	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
Kojto	99:dbbf35b96557	1177
Kojto	99:dbbf35b96557	1178	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1179	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
Kojto	99:dbbf35b96557	1180
Kojto	99:dbbf35b96557	1181	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1182	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
Kojto	99:dbbf35b96557	1183
Kojto	99:dbbf35b96557	1184	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1185	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto	99:dbbf35b96557	1186
Kojto	99:dbbf35b96557	1187	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1188	((__BURST__) == FMC_WRITE_BURST_ENABLE))
Kojto	99:dbbf35b96557	1189
Kojto	99:dbbf35b96557	1190	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
Kojto	99:dbbf35b96557	1191	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto	99:dbbf35b96557	1192
Kojto	99:dbbf35b96557	1193	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
Kojto	99:dbbf35b96557	1194
Kojto	99:dbbf35b96557	1195	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
Kojto	99:dbbf35b96557	1196
Kojto	99:dbbf35b96557	1197	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
Kojto	99:dbbf35b96557	1198
Kojto	99:dbbf35b96557	1199	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
Kojto	99:dbbf35b96557	1200
Kojto	99:dbbf35b96557	1201	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
Kojto	99:dbbf35b96557	1202
Kojto	99:dbbf35b96557	1203	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
Kojto	99:dbbf35b96557	1204
Kojto	99:dbbf35b96557	1205	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
Kojto	99:dbbf35b96557	1206	((BANK) == FMC_SDRAM_BANK2))
Kojto	99:dbbf35b96557	1207
Kojto	99:dbbf35b96557	1208	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
Kojto	99:dbbf35b96557	1209	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
Kojto	99:dbbf35b96557	1210	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
Kojto	99:dbbf35b96557	1211	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
Kojto	99:dbbf35b96557	1212
Kojto	99:dbbf35b96557	1213	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
Kojto	99:dbbf35b96557	1214	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
Kojto	99:dbbf35b96557	1215	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
Kojto	99:dbbf35b96557	1216
Kojto	99:dbbf35b96557	1217	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	99:dbbf35b96557	1218	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	99:dbbf35b96557	1219	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
Kojto	99:dbbf35b96557	1220
Kojto	99:dbbf35b96557	1221	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
Kojto	99:dbbf35b96557	1222	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
Kojto	99:dbbf35b96557	1223
Kojto	99:dbbf35b96557	1224
Kojto	99:dbbf35b96557	1225	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
Kojto	99:dbbf35b96557	1226	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
Kojto	99:dbbf35b96557	1227	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
Kojto	99:dbbf35b96557	1228
Kojto	99:dbbf35b96557	1229	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1230	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
Kojto	99:dbbf35b96557	1231	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
Kojto	99:dbbf35b96557	1232
Kojto	99:dbbf35b96557	1233	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1234	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
Kojto	99:dbbf35b96557	1235
Kojto	99:dbbf35b96557	1236
Kojto	99:dbbf35b96557	1237	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
Kojto	99:dbbf35b96557	1238	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
Kojto	99:dbbf35b96557	1239	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
Kojto	99:dbbf35b96557	1240
Kojto	99:dbbf35b96557	1241	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	99:dbbf35b96557	1242
Kojto	99:dbbf35b96557	1243	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	99:dbbf35b96557	1244
Kojto	99:dbbf35b96557	1245	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto	99:dbbf35b96557	1246
Kojto	99:dbbf35b96557	1247	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	99:dbbf35b96557	1248
Kojto	99:dbbf35b96557	1249	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto	99:dbbf35b96557	1250
Kojto	99:dbbf35b96557	1251	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	99:dbbf35b96557	1252
Kojto	99:dbbf35b96557	1253	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	99:dbbf35b96557	1254
Kojto	99:dbbf35b96557	1255	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
Kojto	99:dbbf35b96557	1256	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
Kojto	99:dbbf35b96557	1257	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
Kojto	99:dbbf35b96557	1258	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
Kojto	99:dbbf35b96557	1259	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
Kojto	99:dbbf35b96557	1260	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
Kojto	99:dbbf35b96557	1261	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
Kojto	99:dbbf35b96557	1262
Kojto	99:dbbf35b96557	1263	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
Kojto	99:dbbf35b96557	1264	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
Kojto	99:dbbf35b96557	1265	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
Kojto	99:dbbf35b96557	1266
Kojto	99:dbbf35b96557	1267	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
Kojto	99:dbbf35b96557	1268
Kojto	99:dbbf35b96557	1269	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
Kojto	99:dbbf35b96557	1270
Kojto	99:dbbf35b96557	1271	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
Kojto	99:dbbf35b96557	1272
Kojto	99:dbbf35b96557	1273	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
Kojto	99:dbbf35b96557	1274
Kojto	99:dbbf35b96557	1275	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1276	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
Kojto	99:dbbf35b96557	1277
Kojto	99:dbbf35b96557	1278	#if defined (STM32F446xx)
Kojto	99:dbbf35b96557	1279	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
Kojto	99:dbbf35b96557	1280	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
Kojto	99:dbbf35b96557	1281	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
Kojto	99:dbbf35b96557	1282	((SIZE) == FMC_PAGE_SIZE_1024))
Kojto	99:dbbf35b96557	1283
Kojto	99:dbbf35b96557	1284	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1285	((FIFO) == FMC_WRITE_FIFO_ENABLE))
Kojto	99:dbbf35b96557	1286	#endif /* defined (STM32F446xx) */
Kojto	99:dbbf35b96557	1287
Kojto	99:dbbf35b96557	1288	/**
Kojto	99:dbbf35b96557	1289	* @}
Kojto	99:dbbf35b96557	1290	*/
Kojto	99:dbbf35b96557	1291
Kojto	99:dbbf35b96557	1292	/**
Kojto	99:dbbf35b96557	1293	* @}
emilmont	77:869cf507173a	1294	*/
emilmont	77:869cf507173a	1295
Kojto	99:dbbf35b96557	1296	/* Private functions ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	1297	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
Kojto	99:dbbf35b96557	1298	* @{
Kojto	99:dbbf35b96557	1299	*/
emilmont	77:869cf507173a	1300
Kojto	99:dbbf35b96557	1301	/** @defgroup FMC_LL_NORSRAM NOR SRAM
Kojto	99:dbbf35b96557	1302	* @{
Kojto	99:dbbf35b96557	1303	*/
Kojto	99:dbbf35b96557	1304	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto	99:dbbf35b96557	1305	* @{
Kojto	99:dbbf35b96557	1306	*/
emilmont	77:869cf507173a	1307	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
emilmont	77:869cf507173a	1308	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	1309	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
emilmont	77:869cf507173a	1310	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
Kojto	99:dbbf35b96557	1311	/**
Kojto	99:dbbf35b96557	1312	* @}
Kojto	99:dbbf35b96557	1313	*/
emilmont	77:869cf507173a	1314
Kojto	99:dbbf35b96557	1315	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto	99:dbbf35b96557	1316	* @{
Kojto	99:dbbf35b96557	1317	*/
emilmont	77:869cf507173a	1318	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1319	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto	99:dbbf35b96557	1320	/**
Kojto	99:dbbf35b96557	1321	* @}
Kojto	99:dbbf35b96557	1322	*/
Kojto	99:dbbf35b96557	1323	/**
Kojto	99:dbbf35b96557	1324	* @}
Kojto	99:dbbf35b96557	1325	*/
emilmont	77:869cf507173a	1326
Kojto	99:dbbf35b96557	1327	/** @defgroup FMC_LL_NAND NAND
Kojto	99:dbbf35b96557	1328	* @{
Kojto	99:dbbf35b96557	1329	*/
Kojto	99:dbbf35b96557	1330	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto	99:dbbf35b96557	1331	* @{
Kojto	99:dbbf35b96557	1332	*/
emilmont	77:869cf507173a	1333	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
emilmont	77:869cf507173a	1334	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	1335	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	1336	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	99:dbbf35b96557	1337	/**
Kojto	99:dbbf35b96557	1338	* @}
Kojto	99:dbbf35b96557	1339	*/
emilmont	77:869cf507173a	1340
Kojto	99:dbbf35b96557	1341	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto	99:dbbf35b96557	1342	* @{
Kojto	99:dbbf35b96557	1343	*/
emilmont	77:869cf507173a	1344	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1345	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1346	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
emilmont	77:869cf507173a	1347
Kojto	99:dbbf35b96557	1348	/**
Kojto	99:dbbf35b96557	1349	* @}
Kojto	99:dbbf35b96557	1350	*/
Kojto	99:dbbf35b96557	1351	/**
Kojto	99:dbbf35b96557	1352	* @}
Kojto	99:dbbf35b96557	1353	*/
Kojto	99:dbbf35b96557	1354	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	1355	/** @defgroup FMC_LL_PCCARD PCCARD
Kojto	99:dbbf35b96557	1356	* @{
Kojto	99:dbbf35b96557	1357	*/
Kojto	99:dbbf35b96557	1358	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto	99:dbbf35b96557	1359	* @{
Kojto	99:dbbf35b96557	1360	*/
emilmont	77:869cf507173a	1361	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
emilmont	77:869cf507173a	1362	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
emilmont	77:869cf507173a	1363	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
emilmont	77:869cf507173a	1364	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
emilmont	77:869cf507173a	1365	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
Kojto	99:dbbf35b96557	1366	/**
Kojto	99:dbbf35b96557	1367	* @}
Kojto	99:dbbf35b96557	1368	*/
Kojto	99:dbbf35b96557	1369	/**
Kojto	99:dbbf35b96557	1370	* @}
Kojto	99:dbbf35b96557	1371	*/
Kojto	99:dbbf35b96557	1372	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
emilmont	77:869cf507173a	1373
Kojto	99:dbbf35b96557	1374	/** @defgroup FMC_LL_SDRAM SDRAM
Kojto	99:dbbf35b96557	1375	* @{
Kojto	99:dbbf35b96557	1376	*/
Kojto	99:dbbf35b96557	1377	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
Kojto	99:dbbf35b96557	1378	* @{
Kojto	99:dbbf35b96557	1379	*/
emilmont	77:869cf507173a	1380	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
emilmont	77:869cf507173a	1381	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	1382	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	99:dbbf35b96557	1383	/**
Kojto	99:dbbf35b96557	1384	* @}
Kojto	99:dbbf35b96557	1385	*/
emilmont	77:869cf507173a	1386
Kojto	99:dbbf35b96557	1387	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
Kojto	99:dbbf35b96557	1388	* @{
Kojto	99:dbbf35b96557	1389	*/
emilmont	77:869cf507173a	1390	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1391	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1392	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
emilmont	77:869cf507173a	1393	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
emilmont	77:869cf507173a	1394	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
emilmont	77:869cf507173a	1395	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1396	/**
emilmont	77:869cf507173a	1397	* @}
Kojto	99:dbbf35b96557	1398	*/
Kojto	99:dbbf35b96557	1399	/**
Kojto	99:dbbf35b96557	1400	* @}
Kojto	99:dbbf35b96557	1401	*/
emilmont	77:869cf507173a	1402
emilmont	77:869cf507173a	1403	/**
emilmont	77:869cf507173a	1404	* @}
emilmont	77:869cf507173a	1405	*/
Kojto	99:dbbf35b96557	1406
Kojto	99:dbbf35b96557	1407	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
Kojto	99:dbbf35b96557	1408	/**
Kojto	99:dbbf35b96557	1409	* @}
Kojto	99:dbbf35b96557	1410	*/
Kojto	99:dbbf35b96557	1411
Kojto	99:dbbf35b96557	1412	/**
Kojto	99:dbbf35b96557	1413	* @}
Kojto	99:dbbf35b96557	1414	*/
emilmont	77:869cf507173a	1415	#ifdef __cplusplus
emilmont	77:869cf507173a	1416	}
emilmont	77:869cf507173a	1417	#endif
emilmont	77:869cf507173a	1418
emilmont	77:869cf507173a	1419	#endif /* __STM32F4xx_LL_FMC_H */
emilmont	77:869cf507173a	1420
emilmont	77:869cf507173a	1421	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h@106:ba1f97679dad, 2015-09-02 (annotated)

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