Elijah Orr
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TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h@106:ba1f97679dad, 2015-09-02 (annotated)
- Committer:
- Kojto
- Date:
- Wed Sep 02 14:17:43 2015 +0100
- Revision:
- 106:ba1f97679dad
- Parent:
- 99:dbbf35b96557
- Child:
- 110:165afa46840b
Release 106 of the mbed library
Changes:
- new platform - Nucleo F446RE
- STM32F4 Cube driver update v2.3.2
- ST cmsis driver v2.3.2
- nordic bugfix gcc linker start address
- lpc11u68 - bugfix for serial ports
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 77:869cf507173a | 1 | /** |
| emilmont | 77:869cf507173a | 2 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 3 | * @file stm32f4xx_hal_pwr.h |
| emilmont | 77:869cf507173a | 4 | * @author MCD Application Team |
| Kojto | 106:ba1f97679dad | 5 | * @version V1.3.2 |
| Kojto | 106:ba1f97679dad | 6 | * @date 26-June-2015 |
| emilmont | 77:869cf507173a | 7 | * @brief Header file of PWR HAL module. |
| emilmont | 77:869cf507173a | 8 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 9 | * @attention |
| emilmont | 77:869cf507173a | 10 | * |
| Kojto | 99:dbbf35b96557 | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| emilmont | 77:869cf507173a | 12 | * |
| emilmont | 77:869cf507173a | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| emilmont | 77:869cf507173a | 14 | * are permitted provided that the following conditions are met: |
| emilmont | 77:869cf507173a | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| emilmont | 77:869cf507173a | 16 | * this list of conditions and the following disclaimer. |
| emilmont | 77:869cf507173a | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| emilmont | 77:869cf507173a | 18 | * this list of conditions and the following disclaimer in the documentation |
| emilmont | 77:869cf507173a | 19 | * and/or other materials provided with the distribution. |
| emilmont | 77:869cf507173a | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| emilmont | 77:869cf507173a | 21 | * may be used to endorse or promote products derived from this software |
| emilmont | 77:869cf507173a | 22 | * without specific prior written permission. |
| emilmont | 77:869cf507173a | 23 | * |
| emilmont | 77:869cf507173a | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| emilmont | 77:869cf507173a | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| emilmont | 77:869cf507173a | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| emilmont | 77:869cf507173a | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| emilmont | 77:869cf507173a | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| emilmont | 77:869cf507173a | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| emilmont | 77:869cf507173a | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| emilmont | 77:869cf507173a | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| emilmont | 77:869cf507173a | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| emilmont | 77:869cf507173a | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| emilmont | 77:869cf507173a | 34 | * |
| emilmont | 77:869cf507173a | 35 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 36 | */ |
| emilmont | 77:869cf507173a | 37 | |
| emilmont | 77:869cf507173a | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| emilmont | 77:869cf507173a | 39 | #ifndef __STM32F4xx_HAL_PWR_H |
| emilmont | 77:869cf507173a | 40 | #define __STM32F4xx_HAL_PWR_H |
| emilmont | 77:869cf507173a | 41 | |
| emilmont | 77:869cf507173a | 42 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 43 | extern "C" { |
| emilmont | 77:869cf507173a | 44 | #endif |
| emilmont | 77:869cf507173a | 45 | |
| emilmont | 77:869cf507173a | 46 | /* Includes ------------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 47 | #include "stm32f4xx_hal_def.h" |
| emilmont | 77:869cf507173a | 48 | |
| emilmont | 77:869cf507173a | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| emilmont | 77:869cf507173a | 50 | * @{ |
| emilmont | 77:869cf507173a | 51 | */ |
| emilmont | 77:869cf507173a | 52 | |
| emilmont | 77:869cf507173a | 53 | /** @addtogroup PWR |
| emilmont | 77:869cf507173a | 54 | * @{ |
| emilmont | 77:869cf507173a | 55 | */ |
| emilmont | 77:869cf507173a | 56 | |
| emilmont | 77:869cf507173a | 57 | /* Exported types ------------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 58 | |
| Kojto | 99:dbbf35b96557 | 59 | /** @defgroup PWR_Exported_Types PWR Exported Types |
| Kojto | 99:dbbf35b96557 | 60 | * @{ |
| Kojto | 99:dbbf35b96557 | 61 | */ |
| Kojto | 99:dbbf35b96557 | 62 | |
| emilmont | 77:869cf507173a | 63 | /** |
| emilmont | 77:869cf507173a | 64 | * @brief PWR PVD configuration structure definition |
| emilmont | 77:869cf507173a | 65 | */ |
| emilmont | 77:869cf507173a | 66 | typedef struct |
| emilmont | 77:869cf507173a | 67 | { |
| bogdanm | 85:024bf7f99721 | 68 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. |
| emilmont | 77:869cf507173a | 69 | This parameter can be a value of @ref PWR_PVD_detection_level */ |
| emilmont | 77:869cf507173a | 70 | |
| emilmont | 77:869cf507173a | 71 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| emilmont | 77:869cf507173a | 72 | This parameter can be a value of @ref PWR_PVD_Mode */ |
| emilmont | 77:869cf507173a | 73 | }PWR_PVDTypeDef; |
| emilmont | 77:869cf507173a | 74 | |
| emilmont | 77:869cf507173a | 75 | /** |
| emilmont | 77:869cf507173a | 76 | * @} |
| emilmont | 77:869cf507173a | 77 | */ |
| emilmont | 77:869cf507173a | 78 | |
| Kojto | 99:dbbf35b96557 | 79 | /* Exported constants --------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 80 | /** @defgroup PWR_Exported_Constants PWR Exported Constants |
| Kojto | 99:dbbf35b96557 | 81 | * @{ |
| Kojto | 99:dbbf35b96557 | 82 | */ |
| Kojto | 99:dbbf35b96557 | 83 | |
| Kojto | 99:dbbf35b96557 | 84 | /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins |
| Kojto | 99:dbbf35b96557 | 85 | * @{ |
| Kojto | 99:dbbf35b96557 | 86 | */ |
| Kojto | 99:dbbf35b96557 | 87 | #define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100) |
| Kojto | 99:dbbf35b96557 | 88 | #define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080) |
| Kojto | 99:dbbf35b96557 | 89 | /** |
| Kojto | 99:dbbf35b96557 | 90 | * @} |
| Kojto | 99:dbbf35b96557 | 91 | */ |
| Kojto | 99:dbbf35b96557 | 92 | |
| Kojto | 99:dbbf35b96557 | 93 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level |
| emilmont | 77:869cf507173a | 94 | * @{ |
| emilmont | 77:869cf507173a | 95 | */ |
| emilmont | 77:869cf507173a | 96 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 |
| emilmont | 77:869cf507173a | 97 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 |
| emilmont | 77:869cf507173a | 98 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 |
| emilmont | 77:869cf507173a | 99 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 |
| emilmont | 77:869cf507173a | 100 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 |
| emilmont | 77:869cf507173a | 101 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 |
| emilmont | 77:869cf507173a | 102 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 |
| Kojto | 99:dbbf35b96557 | 103 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage |
| Kojto | 99:dbbf35b96557 | 104 | (Compare internally to VREFINT) */ |
| emilmont | 77:869cf507173a | 105 | /** |
| emilmont | 77:869cf507173a | 106 | * @} |
| emilmont | 77:869cf507173a | 107 | */ |
| emilmont | 77:869cf507173a | 108 | |
| Kojto | 99:dbbf35b96557 | 109 | /** @defgroup PWR_PVD_Mode PWR PVD Mode |
| emilmont | 77:869cf507173a | 110 | * @{ |
| emilmont | 77:869cf507173a | 111 | */ |
| Kojto | 99:dbbf35b96557 | 112 | #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ |
| Kojto | 99:dbbf35b96557 | 113 | #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ |
| Kojto | 99:dbbf35b96557 | 114 | #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ |
| Kojto | 99:dbbf35b96557 | 115 | #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| Kojto | 99:dbbf35b96557 | 116 | #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ |
| Kojto | 99:dbbf35b96557 | 117 | #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ |
| Kojto | 99:dbbf35b96557 | 118 | #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ |
| emilmont | 77:869cf507173a | 119 | /** |
| emilmont | 77:869cf507173a | 120 | * @} |
| Kojto | 99:dbbf35b96557 | 121 | */ |
| emilmont | 77:869cf507173a | 122 | |
| Kojto | 99:dbbf35b96557 | 123 | |
| Kojto | 99:dbbf35b96557 | 124 | /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode |
| emilmont | 77:869cf507173a | 125 | * @{ |
| emilmont | 77:869cf507173a | 126 | */ |
| emilmont | 77:869cf507173a | 127 | #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 128 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS |
| emilmont | 77:869cf507173a | 129 | /** |
| emilmont | 77:869cf507173a | 130 | * @} |
| emilmont | 77:869cf507173a | 131 | */ |
| emilmont | 77:869cf507173a | 132 | |
| Kojto | 99:dbbf35b96557 | 133 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry |
| emilmont | 77:869cf507173a | 134 | * @{ |
| emilmont | 77:869cf507173a | 135 | */ |
| emilmont | 77:869cf507173a | 136 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) |
| emilmont | 77:869cf507173a | 137 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) |
| emilmont | 77:869cf507173a | 138 | /** |
| emilmont | 77:869cf507173a | 139 | * @} |
| emilmont | 77:869cf507173a | 140 | */ |
| emilmont | 77:869cf507173a | 141 | |
| Kojto | 99:dbbf35b96557 | 142 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry |
| emilmont | 77:869cf507173a | 143 | * @{ |
| emilmont | 77:869cf507173a | 144 | */ |
| emilmont | 77:869cf507173a | 145 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) |
| emilmont | 77:869cf507173a | 146 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) |
| emilmont | 77:869cf507173a | 147 | /** |
| emilmont | 77:869cf507173a | 148 | * @} |
| emilmont | 77:869cf507173a | 149 | */ |
| emilmont | 77:869cf507173a | 150 | |
| Kojto | 99:dbbf35b96557 | 151 | /** @defgroup PWR_Flag PWR Flag |
| emilmont | 77:869cf507173a | 152 | * @{ |
| emilmont | 77:869cf507173a | 153 | */ |
| emilmont | 77:869cf507173a | 154 | #define PWR_FLAG_WU PWR_CSR_WUF |
| emilmont | 77:869cf507173a | 155 | #define PWR_FLAG_SB PWR_CSR_SBF |
| emilmont | 77:869cf507173a | 156 | #define PWR_FLAG_PVDO PWR_CSR_PVDO |
| emilmont | 77:869cf507173a | 157 | #define PWR_FLAG_BRR PWR_CSR_BRR |
| emilmont | 77:869cf507173a | 158 | #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY |
| emilmont | 77:869cf507173a | 159 | /** |
| emilmont | 77:869cf507173a | 160 | * @} |
| emilmont | 77:869cf507173a | 161 | */ |
| emilmont | 77:869cf507173a | 162 | |
| emilmont | 77:869cf507173a | 163 | /** |
| emilmont | 77:869cf507173a | 164 | * @} |
| emilmont | 77:869cf507173a | 165 | */ |
| emilmont | 77:869cf507173a | 166 | |
| emilmont | 77:869cf507173a | 167 | /* Exported macro ------------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 168 | /** @defgroup PWR_Exported_Macro PWR Exported Macro |
| Kojto | 99:dbbf35b96557 | 169 | * @{ |
| Kojto | 99:dbbf35b96557 | 170 | */ |
| emilmont | 77:869cf507173a | 171 | |
| Kojto | 106:ba1f97679dad | 172 | #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) |
| Kojto | 99:dbbf35b96557 | 173 | /** @brief macros configure the main internal regulator output voltage. |
| Kojto | 99:dbbf35b96557 | 174 | * @param __REGULATOR__: specifies the regulator output voltage to achieve |
| Kojto | 99:dbbf35b96557 | 175 | * a tradeoff between performance and power consumption when the device does |
| Kojto | 99:dbbf35b96557 | 176 | * not operate at the maximum frequency (refer to the datasheets for more details). |
| Kojto | 99:dbbf35b96557 | 177 | * This parameter can be one of the following values: |
| Kojto | 99:dbbf35b96557 | 178 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode |
| Kojto | 99:dbbf35b96557 | 179 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode |
| Kojto | 99:dbbf35b96557 | 180 | * @retval None |
| Kojto | 99:dbbf35b96557 | 181 | */ |
| Kojto | 99:dbbf35b96557 | 182 | #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ |
| Kojto | 99:dbbf35b96557 | 183 | __IO uint32_t tmpreg; \ |
| Kojto | 99:dbbf35b96557 | 184 | MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ |
| Kojto | 99:dbbf35b96557 | 185 | /* Delay after an RCC peripheral clock enabling */ \ |
| Kojto | 99:dbbf35b96557 | 186 | tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ |
| Kojto | 99:dbbf35b96557 | 187 | UNUSED(tmpreg); \ |
| Kojto | 99:dbbf35b96557 | 188 | } while(0) |
| Kojto | 99:dbbf35b96557 | 189 | #else |
| emilmont | 77:869cf507173a | 190 | /** @brief macros configure the main internal regulator output voltage. |
| emilmont | 77:869cf507173a | 191 | * @param __REGULATOR__: specifies the regulator output voltage to achieve |
| emilmont | 77:869cf507173a | 192 | * a tradeoff between performance and power consumption when the device does |
| emilmont | 77:869cf507173a | 193 | * not operate at the maximum frequency (refer to the datasheets for more details). |
| emilmont | 77:869cf507173a | 194 | * This parameter can be one of the following values: |
| emilmont | 77:869cf507173a | 195 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode |
| emilmont | 77:869cf507173a | 196 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode |
| emilmont | 77:869cf507173a | 197 | * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode |
| emilmont | 77:869cf507173a | 198 | * @retval None |
| emilmont | 77:869cf507173a | 199 | */ |
| Kojto | 99:dbbf35b96557 | 200 | #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ |
| Kojto | 99:dbbf35b96557 | 201 | __IO uint32_t tmpreg; \ |
| Kojto | 99:dbbf35b96557 | 202 | MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ |
| Kojto | 99:dbbf35b96557 | 203 | /* Delay after an RCC peripheral clock enabling */ \ |
| Kojto | 99:dbbf35b96557 | 204 | tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ |
| Kojto | 99:dbbf35b96557 | 205 | UNUSED(tmpreg); \ |
| Kojto | 99:dbbf35b96557 | 206 | } while(0) |
| Kojto | 99:dbbf35b96557 | 207 | #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ |
| emilmont | 77:869cf507173a | 208 | |
| emilmont | 77:869cf507173a | 209 | /** @brief Check PWR flag is set or not. |
| emilmont | 77:869cf507173a | 210 | * @param __FLAG__: specifies the flag to check. |
| emilmont | 77:869cf507173a | 211 | * This parameter can be one of the following values: |
| emilmont | 77:869cf507173a | 212 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event |
| emilmont | 77:869cf507173a | 213 | * was received from the WKUP pin or from the RTC alarm (Alarm A |
| emilmont | 77:869cf507173a | 214 | * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. |
| emilmont | 77:869cf507173a | 215 | * An additional wakeup event is detected if the WKUP pin is enabled |
| emilmont | 77:869cf507173a | 216 | * (by setting the EWUP bit) when the WKUP pin level is already high. |
| emilmont | 77:869cf507173a | 217 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was |
| emilmont | 77:869cf507173a | 218 | * resumed from StandBy mode. |
| emilmont | 77:869cf507173a | 219 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled |
| emilmont | 77:869cf507173a | 220 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode |
| emilmont | 77:869cf507173a | 221 | * For this reason, this bit is equal to 0 after Standby or reset |
| emilmont | 77:869cf507173a | 222 | * until the PVDE bit is set. |
| emilmont | 77:869cf507173a | 223 | * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset |
| emilmont | 77:869cf507173a | 224 | * when the device wakes up from Standby mode or by a system reset |
| emilmont | 77:869cf507173a | 225 | * or power reset. |
| emilmont | 77:869cf507173a | 226 | * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage |
| emilmont | 77:869cf507173a | 227 | * scaling output selection is ready. |
| emilmont | 77:869cf507173a | 228 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| emilmont | 77:869cf507173a | 229 | */ |
| emilmont | 77:869cf507173a | 230 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) |
| emilmont | 77:869cf507173a | 231 | |
| emilmont | 77:869cf507173a | 232 | /** @brief Clear the PWR's pending flags. |
| emilmont | 77:869cf507173a | 233 | * @param __FLAG__: specifies the flag to clear. |
| emilmont | 77:869cf507173a | 234 | * This parameter can be one of the following values: |
| emilmont | 77:869cf507173a | 235 | * @arg PWR_FLAG_WU: Wake Up flag |
| emilmont | 77:869cf507173a | 236 | * @arg PWR_FLAG_SB: StandBy flag |
| emilmont | 77:869cf507173a | 237 | */ |
| emilmont | 77:869cf507173a | 238 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2) |
| emilmont | 77:869cf507173a | 239 | |
| Kojto | 99:dbbf35b96557 | 240 | /** |
| Kojto | 99:dbbf35b96557 | 241 | * @brief Enable the PVD Exti Line 16. |
| Kojto | 99:dbbf35b96557 | 242 | * @retval None. |
| Kojto | 99:dbbf35b96557 | 243 | */ |
| Kojto | 99:dbbf35b96557 | 244 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) |
| Kojto | 99:dbbf35b96557 | 245 | |
| Kojto | 99:dbbf35b96557 | 246 | /** |
| Kojto | 99:dbbf35b96557 | 247 | * @brief Disable the PVD EXTI Line 16. |
| Kojto | 99:dbbf35b96557 | 248 | * @retval None. |
| Kojto | 99:dbbf35b96557 | 249 | */ |
| Kojto | 99:dbbf35b96557 | 250 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) |
| Kojto | 99:dbbf35b96557 | 251 | |
| emilmont | 77:869cf507173a | 252 | /** |
| Kojto | 99:dbbf35b96557 | 253 | * @brief Enable event on PVD Exti Line 16. |
| Kojto | 99:dbbf35b96557 | 254 | * @retval None. |
| Kojto | 99:dbbf35b96557 | 255 | */ |
| Kojto | 99:dbbf35b96557 | 256 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) |
| Kojto | 99:dbbf35b96557 | 257 | |
| Kojto | 99:dbbf35b96557 | 258 | /** |
| Kojto | 99:dbbf35b96557 | 259 | * @brief Disable event on PVD Exti Line 16. |
| Kojto | 99:dbbf35b96557 | 260 | * @retval None. |
| Kojto | 99:dbbf35b96557 | 261 | */ |
| Kojto | 99:dbbf35b96557 | 262 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) |
| Kojto | 99:dbbf35b96557 | 263 | |
| Kojto | 99:dbbf35b96557 | 264 | /** |
| Kojto | 99:dbbf35b96557 | 265 | * @brief Enable the PVD Extended Interrupt Rising Trigger. |
| emilmont | 77:869cf507173a | 266 | * @retval None. |
| emilmont | 77:869cf507173a | 267 | */ |
| Kojto | 99:dbbf35b96557 | 268 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| Kojto | 99:dbbf35b96557 | 269 | |
| Kojto | 99:dbbf35b96557 | 270 | /** |
| Kojto | 99:dbbf35b96557 | 271 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
| Kojto | 99:dbbf35b96557 | 272 | * @retval None. |
| Kojto | 99:dbbf35b96557 | 273 | */ |
| Kojto | 99:dbbf35b96557 | 274 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| Kojto | 99:dbbf35b96557 | 275 | |
| Kojto | 99:dbbf35b96557 | 276 | /** |
| Kojto | 99:dbbf35b96557 | 277 | * @brief Enable the PVD Extended Interrupt Falling Trigger. |
| Kojto | 99:dbbf35b96557 | 278 | * @retval None. |
| Kojto | 99:dbbf35b96557 | 279 | */ |
| Kojto | 99:dbbf35b96557 | 280 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| Kojto | 99:dbbf35b96557 | 281 | |
| emilmont | 77:869cf507173a | 282 | |
| emilmont | 77:869cf507173a | 283 | /** |
| Kojto | 99:dbbf35b96557 | 284 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
| emilmont | 77:869cf507173a | 285 | * @retval None. |
| emilmont | 77:869cf507173a | 286 | */ |
| Kojto | 99:dbbf35b96557 | 287 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| Kojto | 99:dbbf35b96557 | 288 | |
| Kojto | 99:dbbf35b96557 | 289 | |
| Kojto | 99:dbbf35b96557 | 290 | /** |
| Kojto | 99:dbbf35b96557 | 291 | * @brief PVD EXTI line configuration: set rising & falling edge trigger. |
| Kojto | 99:dbbf35b96557 | 292 | * @retval None. |
| Kojto | 99:dbbf35b96557 | 293 | */ |
| Kojto | 99:dbbf35b96557 | 294 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
| Kojto | 99:dbbf35b96557 | 295 | |
| Kojto | 99:dbbf35b96557 | 296 | /** |
| Kojto | 99:dbbf35b96557 | 297 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
| Kojto | 99:dbbf35b96557 | 298 | * This parameter can be: |
| Kojto | 99:dbbf35b96557 | 299 | * @retval None. |
| Kojto | 99:dbbf35b96557 | 300 | */ |
| Kojto | 99:dbbf35b96557 | 301 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); |
| emilmont | 77:869cf507173a | 302 | |
| emilmont | 77:869cf507173a | 303 | /** |
| emilmont | 77:869cf507173a | 304 | * @brief checks whether the specified PVD Exti interrupt flag is set or not. |
| emilmont | 77:869cf507173a | 305 | * @retval EXTI PVD Line Status. |
| emilmont | 77:869cf507173a | 306 | */ |
| Kojto | 99:dbbf35b96557 | 307 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
| emilmont | 77:869cf507173a | 308 | |
| emilmont | 77:869cf507173a | 309 | /** |
| emilmont | 77:869cf507173a | 310 | * @brief Clear the PVD Exti flag. |
| emilmont | 77:869cf507173a | 311 | * @retval None. |
| emilmont | 77:869cf507173a | 312 | */ |
| Kojto | 99:dbbf35b96557 | 313 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
| emilmont | 77:869cf507173a | 314 | |
| Kojto | 90:cb3d968589d8 | 315 | /** |
| Kojto | 99:dbbf35b96557 | 316 | * @brief Generates a Software interrupt on PVD EXTI line. |
| Kojto | 90:cb3d968589d8 | 317 | * @retval None |
| Kojto | 90:cb3d968589d8 | 318 | */ |
| Kojto | 99:dbbf35b96557 | 319 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) |
| Kojto | 99:dbbf35b96557 | 320 | |
| Kojto | 99:dbbf35b96557 | 321 | /** |
| Kojto | 99:dbbf35b96557 | 322 | * @} |
| Kojto | 99:dbbf35b96557 | 323 | */ |
| emilmont | 77:869cf507173a | 324 | |
| emilmont | 77:869cf507173a | 325 | /* Include PWR HAL Extension module */ |
| emilmont | 77:869cf507173a | 326 | #include "stm32f4xx_hal_pwr_ex.h" |
| emilmont | 77:869cf507173a | 327 | |
| emilmont | 77:869cf507173a | 328 | /* Exported functions --------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 329 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions |
| Kojto | 99:dbbf35b96557 | 330 | * @{ |
| Kojto | 99:dbbf35b96557 | 331 | */ |
| Kojto | 99:dbbf35b96557 | 332 | |
| Kojto | 99:dbbf35b96557 | 333 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
| Kojto | 99:dbbf35b96557 | 334 | * @{ |
| Kojto | 99:dbbf35b96557 | 335 | */ |
| Kojto | 90:cb3d968589d8 | 336 | /* Initialization and de-initialization functions *****************************/ |
| Kojto | 90:cb3d968589d8 | 337 | void HAL_PWR_DeInit(void); |
| Kojto | 90:cb3d968589d8 | 338 | void HAL_PWR_EnableBkUpAccess(void); |
| Kojto | 90:cb3d968589d8 | 339 | void HAL_PWR_DisableBkUpAccess(void); |
| Kojto | 99:dbbf35b96557 | 340 | /** |
| Kojto | 99:dbbf35b96557 | 341 | * @} |
| Kojto | 99:dbbf35b96557 | 342 | */ |
| Kojto | 90:cb3d968589d8 | 343 | |
| Kojto | 99:dbbf35b96557 | 344 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions |
| Kojto | 99:dbbf35b96557 | 345 | * @{ |
| Kojto | 99:dbbf35b96557 | 346 | */ |
| Kojto | 90:cb3d968589d8 | 347 | /* Peripheral Control functions **********************************************/ |
| Kojto | 90:cb3d968589d8 | 348 | /* PVD configuration */ |
| Kojto | 99:dbbf35b96557 | 349 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
| Kojto | 90:cb3d968589d8 | 350 | void HAL_PWR_EnablePVD(void); |
| Kojto | 90:cb3d968589d8 | 351 | void HAL_PWR_DisablePVD(void); |
| emilmont | 77:869cf507173a | 352 | |
| Kojto | 90:cb3d968589d8 | 353 | /* WakeUp pins configuration */ |
| Kojto | 90:cb3d968589d8 | 354 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); |
| Kojto | 90:cb3d968589d8 | 355 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
| emilmont | 77:869cf507173a | 356 | |
| Kojto | 90:cb3d968589d8 | 357 | /* Low Power modes entry */ |
| Kojto | 90:cb3d968589d8 | 358 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
| Kojto | 90:cb3d968589d8 | 359 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
| Kojto | 90:cb3d968589d8 | 360 | void HAL_PWR_EnterSTANDBYMode(void); |
| emilmont | 77:869cf507173a | 361 | |
| Kojto | 99:dbbf35b96557 | 362 | /* Power PVD IRQ Handler */ |
| Kojto | 90:cb3d968589d8 | 363 | void HAL_PWR_PVD_IRQHandler(void); |
| bogdanm | 81:7d30d6019079 | 364 | void HAL_PWR_PVDCallback(void); |
| emilmont | 77:869cf507173a | 365 | |
| Kojto | 99:dbbf35b96557 | 366 | /* Cortex System Control functions *******************************************/ |
| Kojto | 99:dbbf35b96557 | 367 | void HAL_PWR_EnableSleepOnExit(void); |
| Kojto | 99:dbbf35b96557 | 368 | void HAL_PWR_DisableSleepOnExit(void); |
| Kojto | 99:dbbf35b96557 | 369 | void HAL_PWR_EnableSEVOnPend(void); |
| Kojto | 99:dbbf35b96557 | 370 | void HAL_PWR_DisableSEVOnPend(void); |
| Kojto | 99:dbbf35b96557 | 371 | /** |
| Kojto | 99:dbbf35b96557 | 372 | * @} |
| Kojto | 99:dbbf35b96557 | 373 | */ |
| Kojto | 99:dbbf35b96557 | 374 | |
| Kojto | 99:dbbf35b96557 | 375 | /** |
| Kojto | 99:dbbf35b96557 | 376 | * @} |
| Kojto | 99:dbbf35b96557 | 377 | */ |
| Kojto | 99:dbbf35b96557 | 378 | |
| Kojto | 99:dbbf35b96557 | 379 | /* Private types -------------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 380 | /* Private variables ---------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 381 | /* Private constants ---------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 382 | /** @defgroup PWR_Private_Constants PWR Private Constants |
| Kojto | 99:dbbf35b96557 | 383 | * @{ |
| Kojto | 99:dbbf35b96557 | 384 | */ |
| Kojto | 99:dbbf35b96557 | 385 | |
| Kojto | 99:dbbf35b96557 | 386 | /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line |
| Kojto | 99:dbbf35b96557 | 387 | * @{ |
| Kojto | 99:dbbf35b96557 | 388 | */ |
| Kojto | 99:dbbf35b96557 | 389 | #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
| Kojto | 99:dbbf35b96557 | 390 | /** |
| Kojto | 99:dbbf35b96557 | 391 | * @} |
| Kojto | 99:dbbf35b96557 | 392 | */ |
| Kojto | 99:dbbf35b96557 | 393 | |
| Kojto | 99:dbbf35b96557 | 394 | /** @defgroup PWR_register_alias_address PWR Register alias address |
| Kojto | 99:dbbf35b96557 | 395 | * @{ |
| Kojto | 99:dbbf35b96557 | 396 | */ |
| Kojto | 99:dbbf35b96557 | 397 | /* ------------- PWR registers bit address in the alias region ---------------*/ |
| Kojto | 99:dbbf35b96557 | 398 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) |
| Kojto | 99:dbbf35b96557 | 399 | #define PWR_CR_OFFSET 0x00 |
| Kojto | 99:dbbf35b96557 | 400 | #define PWR_CSR_OFFSET 0x04 |
| Kojto | 99:dbbf35b96557 | 401 | #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) |
| Kojto | 99:dbbf35b96557 | 402 | #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) |
| Kojto | 99:dbbf35b96557 | 403 | /** |
| Kojto | 99:dbbf35b96557 | 404 | * @} |
| Kojto | 99:dbbf35b96557 | 405 | */ |
| Kojto | 99:dbbf35b96557 | 406 | |
| Kojto | 99:dbbf35b96557 | 407 | /** @defgroup PWR_CR_register_alias PWR CR Register alias address |
| Kojto | 99:dbbf35b96557 | 408 | * @{ |
| Kojto | 99:dbbf35b96557 | 409 | */ |
| Kojto | 99:dbbf35b96557 | 410 | /* --- CR Register ---*/ |
| Kojto | 99:dbbf35b96557 | 411 | /* Alias word address of DBP bit */ |
| Kojto | 99:dbbf35b96557 | 412 | #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) |
| Kojto | 99:dbbf35b96557 | 413 | #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)) |
| Kojto | 99:dbbf35b96557 | 414 | |
| Kojto | 99:dbbf35b96557 | 415 | /* Alias word address of PVDE bit */ |
| Kojto | 99:dbbf35b96557 | 416 | #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) |
| Kojto | 99:dbbf35b96557 | 417 | #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)) |
| Kojto | 99:dbbf35b96557 | 418 | |
| Kojto | 99:dbbf35b96557 | 419 | /* Alias word address of PMODE bit */ |
| Kojto | 99:dbbf35b96557 | 420 | #define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE) |
| Kojto | 99:dbbf35b96557 | 421 | #define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PMODE_BIT_NUMBER * 4)) |
| Kojto | 99:dbbf35b96557 | 422 | /** |
| Kojto | 99:dbbf35b96557 | 423 | * @} |
| Kojto | 99:dbbf35b96557 | 424 | */ |
| Kojto | 99:dbbf35b96557 | 425 | |
| Kojto | 99:dbbf35b96557 | 426 | /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address |
| Kojto | 99:dbbf35b96557 | 427 | * @{ |
| Kojto | 99:dbbf35b96557 | 428 | */ |
| Kojto | 99:dbbf35b96557 | 429 | /* --- CSR Register ---*/ |
| Kojto | 99:dbbf35b96557 | 430 | /* Alias word address of EWUP bit */ |
| Kojto | 99:dbbf35b96557 | 431 | #define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP) |
| Kojto | 99:dbbf35b96557 | 432 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (EWUP_BIT_NUMBER * 4)) |
| Kojto | 99:dbbf35b96557 | 433 | /** |
| Kojto | 99:dbbf35b96557 | 434 | * @} |
| Kojto | 99:dbbf35b96557 | 435 | */ |
| Kojto | 99:dbbf35b96557 | 436 | |
| Kojto | 99:dbbf35b96557 | 437 | /** |
| Kojto | 99:dbbf35b96557 | 438 | * @} |
| Kojto | 99:dbbf35b96557 | 439 | */ |
| Kojto | 99:dbbf35b96557 | 440 | /* Private macros ------------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 441 | /** @defgroup PWR_Private_Macros PWR Private Macros |
| Kojto | 99:dbbf35b96557 | 442 | * @{ |
| Kojto | 99:dbbf35b96557 | 443 | */ |
| Kojto | 99:dbbf35b96557 | 444 | |
| Kojto | 99:dbbf35b96557 | 445 | /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters |
| Kojto | 99:dbbf35b96557 | 446 | * @{ |
| Kojto | 99:dbbf35b96557 | 447 | */ |
| Kojto | 99:dbbf35b96557 | 448 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2)) |
| Kojto | 99:dbbf35b96557 | 449 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
| Kojto | 99:dbbf35b96557 | 450 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
| Kojto | 99:dbbf35b96557 | 451 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
| Kojto | 99:dbbf35b96557 | 452 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
| Kojto | 99:dbbf35b96557 | 453 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
| Kojto | 99:dbbf35b96557 | 454 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ |
| Kojto | 99:dbbf35b96557 | 455 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ |
| Kojto | 99:dbbf35b96557 | 456 | ((MODE) == PWR_PVD_MODE_NORMAL)) |
| Kojto | 99:dbbf35b96557 | 457 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
| Kojto | 99:dbbf35b96557 | 458 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
| Kojto | 99:dbbf35b96557 | 459 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
| Kojto | 99:dbbf35b96557 | 460 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) |
| Kojto | 99:dbbf35b96557 | 461 | /** |
| Kojto | 99:dbbf35b96557 | 462 | * @} |
| Kojto | 99:dbbf35b96557 | 463 | */ |
| Kojto | 99:dbbf35b96557 | 464 | |
| Kojto | 99:dbbf35b96557 | 465 | /** |
| Kojto | 99:dbbf35b96557 | 466 | * @} |
| Kojto | 99:dbbf35b96557 | 467 | */ |
| emilmont | 77:869cf507173a | 468 | |
| emilmont | 77:869cf507173a | 469 | /** |
| emilmont | 77:869cf507173a | 470 | * @} |
| emilmont | 77:869cf507173a | 471 | */ |
| emilmont | 77:869cf507173a | 472 | |
| emilmont | 77:869cf507173a | 473 | /** |
| emilmont | 77:869cf507173a | 474 | * @} |
| emilmont | 77:869cf507173a | 475 | */ |
| emilmont | 77:869cf507173a | 476 | |
| emilmont | 77:869cf507173a | 477 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 478 | } |
| emilmont | 77:869cf507173a | 479 | #endif |
| emilmont | 77:869cf507173a | 480 | |
| emilmont | 77:869cf507173a | 481 | |
| emilmont | 77:869cf507173a | 482 | #endif /* __STM32F4xx_HAL_PWR_H */ |
| emilmont | 77:869cf507173a | 483 | |
| emilmont | 77:869cf507173a | 484 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |