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LPC2368/core_arm7.h@40:976df7c37ad5, 2012-06-12 (annotated)
- Committer:
- emilmont
- Date:
- Tue Jun 12 18:23:44 2012 +0100
- Revision:
- 40:976df7c37ad5
- Child:
- 44:24d45a770a51
First build for the new build system
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
emilmont | 40:976df7c37ad5 | 1 | /* mbed Microcontroller Library |
emilmont | 40:976df7c37ad5 | 2 | * Copyright (C) 2008-2009 ARM Limited. All rights reserved. |
emilmont | 40:976df7c37ad5 | 3 | * |
emilmont | 40:976df7c37ad5 | 4 | * ARM7 version of CMSIS-like functionality - not advised for use outside mbed! |
emilmont | 40:976df7c37ad5 | 5 | * based on core_cm3.h, V1.20 |
emilmont | 40:976df7c37ad5 | 6 | */ |
emilmont | 40:976df7c37ad5 | 7 | |
emilmont | 40:976df7c37ad5 | 8 | #ifndef __ARM7_CORE_H__ |
emilmont | 40:976df7c37ad5 | 9 | #define __ARM7_CORE_H__ |
emilmont | 40:976df7c37ad5 | 10 | |
emilmont | 40:976df7c37ad5 | 11 | #ifdef __cplusplus |
emilmont | 40:976df7c37ad5 | 12 | extern "C" { |
emilmont | 40:976df7c37ad5 | 13 | #endif |
emilmont | 40:976df7c37ad5 | 14 | |
emilmont | 40:976df7c37ad5 | 15 | #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ |
emilmont | 40:976df7c37ad5 | 16 | #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ |
emilmont | 40:976df7c37ad5 | 17 | #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ |
emilmont | 40:976df7c37ad5 | 18 | |
emilmont | 40:976df7c37ad5 | 19 | #define __CORTEX_M (0x03) /*!< Cortex core */ |
emilmont | 40:976df7c37ad5 | 20 | |
emilmont | 40:976df7c37ad5 | 21 | /** |
emilmont | 40:976df7c37ad5 | 22 | * Lint configuration \n |
emilmont | 40:976df7c37ad5 | 23 | * ----------------------- \n |
emilmont | 40:976df7c37ad5 | 24 | * |
emilmont | 40:976df7c37ad5 | 25 | * The following Lint messages will be suppressed and not shown: \n |
emilmont | 40:976df7c37ad5 | 26 | * \n |
emilmont | 40:976df7c37ad5 | 27 | * --- Error 10: --- \n |
emilmont | 40:976df7c37ad5 | 28 | * register uint32_t __regBasePri __asm("basepri"); \n |
emilmont | 40:976df7c37ad5 | 29 | * Error 10: Expecting ';' \n |
emilmont | 40:976df7c37ad5 | 30 | * \n |
emilmont | 40:976df7c37ad5 | 31 | * --- Error 530: --- \n |
emilmont | 40:976df7c37ad5 | 32 | * return(__regBasePri); \n |
emilmont | 40:976df7c37ad5 | 33 | * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n |
emilmont | 40:976df7c37ad5 | 34 | * \n |
emilmont | 40:976df7c37ad5 | 35 | * --- Error 550: --- \n |
emilmont | 40:976df7c37ad5 | 36 | * __regBasePri = (basePri & 0x1ff); \n |
emilmont | 40:976df7c37ad5 | 37 | * } \n |
emilmont | 40:976df7c37ad5 | 38 | * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n |
emilmont | 40:976df7c37ad5 | 39 | * \n |
emilmont | 40:976df7c37ad5 | 40 | * --- Error 754: --- \n |
emilmont | 40:976df7c37ad5 | 41 | * uint32_t RESERVED0[24]; \n |
emilmont | 40:976df7c37ad5 | 42 | * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n |
emilmont | 40:976df7c37ad5 | 43 | * \n |
emilmont | 40:976df7c37ad5 | 44 | * --- Error 750: --- \n |
emilmont | 40:976df7c37ad5 | 45 | * #define __CM3_CORE_H__ \n |
emilmont | 40:976df7c37ad5 | 46 | * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n |
emilmont | 40:976df7c37ad5 | 47 | * \n |
emilmont | 40:976df7c37ad5 | 48 | * --- Error 528: --- \n |
emilmont | 40:976df7c37ad5 | 49 | * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n |
emilmont | 40:976df7c37ad5 | 50 | * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n |
emilmont | 40:976df7c37ad5 | 51 | * \n |
emilmont | 40:976df7c37ad5 | 52 | * --- Error 751: --- \n |
emilmont | 40:976df7c37ad5 | 53 | * } InterruptType_Type; \n |
emilmont | 40:976df7c37ad5 | 54 | * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n |
emilmont | 40:976df7c37ad5 | 55 | * \n |
emilmont | 40:976df7c37ad5 | 56 | * \n |
emilmont | 40:976df7c37ad5 | 57 | * Note: To re-enable a Message, insert a space before 'lint' * \n |
emilmont | 40:976df7c37ad5 | 58 | * |
emilmont | 40:976df7c37ad5 | 59 | */ |
emilmont | 40:976df7c37ad5 | 60 | |
emilmont | 40:976df7c37ad5 | 61 | /*lint -save */ |
emilmont | 40:976df7c37ad5 | 62 | /*lint -e10 */ |
emilmont | 40:976df7c37ad5 | 63 | /*lint -e530 */ |
emilmont | 40:976df7c37ad5 | 64 | /*lint -e550 */ |
emilmont | 40:976df7c37ad5 | 65 | /*lint -e754 */ |
emilmont | 40:976df7c37ad5 | 66 | /*lint -e750 */ |
emilmont | 40:976df7c37ad5 | 67 | /*lint -e528 */ |
emilmont | 40:976df7c37ad5 | 68 | /*lint -e751 */ |
emilmont | 40:976df7c37ad5 | 69 | |
emilmont | 40:976df7c37ad5 | 70 | #include <stdint.h> /* Include standard types */ |
emilmont | 40:976df7c37ad5 | 71 | |
emilmont | 40:976df7c37ad5 | 72 | #if defined ( __CC_ARM ) |
emilmont | 40:976df7c37ad5 | 73 | /** |
emilmont | 40:976df7c37ad5 | 74 | * @brief Return the Main Stack Pointer (current ARM7 stack) |
emilmont | 40:976df7c37ad5 | 75 | * |
emilmont | 40:976df7c37ad5 | 76 | * @param none |
emilmont | 40:976df7c37ad5 | 77 | * @return uint32_t Main Stack Pointer |
emilmont | 40:976df7c37ad5 | 78 | * |
emilmont | 40:976df7c37ad5 | 79 | * Return the current value of the MSP (main stack pointer) |
emilmont | 40:976df7c37ad5 | 80 | * Cortex processor register |
emilmont | 40:976df7c37ad5 | 81 | */ |
emilmont | 40:976df7c37ad5 | 82 | extern uint32_t __get_MSP(void); |
emilmont | 40:976df7c37ad5 | 83 | #endif |
emilmont | 40:976df7c37ad5 | 84 | |
emilmont | 40:976df7c37ad5 | 85 | |
emilmont | 40:976df7c37ad5 | 86 | #if defined (__ICCARM__) |
emilmont | 40:976df7c37ad5 | 87 | #include <intrinsics.h> /* IAR Intrinsics */ |
emilmont | 40:976df7c37ad5 | 88 | #endif |
emilmont | 40:976df7c37ad5 | 89 | |
emilmont | 40:976df7c37ad5 | 90 | |
emilmont | 40:976df7c37ad5 | 91 | #ifndef __NVIC_PRIO_BITS |
emilmont | 40:976df7c37ad5 | 92 | #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ |
emilmont | 40:976df7c37ad5 | 93 | #endif |
emilmont | 40:976df7c37ad5 | 94 | |
emilmont | 40:976df7c37ad5 | 95 | typedef struct |
emilmont | 40:976df7c37ad5 | 96 | { |
emilmont | 40:976df7c37ad5 | 97 | uint32_t IRQStatus; |
emilmont | 40:976df7c37ad5 | 98 | uint32_t FIQStatus; |
emilmont | 40:976df7c37ad5 | 99 | uint32_t RawIntr; |
emilmont | 40:976df7c37ad5 | 100 | uint32_t IntSelect; |
emilmont | 40:976df7c37ad5 | 101 | uint32_t IntEnable; |
emilmont | 40:976df7c37ad5 | 102 | uint32_t IntEnClr; |
emilmont | 40:976df7c37ad5 | 103 | uint32_t SoftInt; |
emilmont | 40:976df7c37ad5 | 104 | uint32_t SoftIntClr; |
emilmont | 40:976df7c37ad5 | 105 | uint32_t Protection; |
emilmont | 40:976df7c37ad5 | 106 | uint32_t SWPriorityMask; |
emilmont | 40:976df7c37ad5 | 107 | uint32_t RESERVED0[54]; |
emilmont | 40:976df7c37ad5 | 108 | uint32_t VectAddr[32]; |
emilmont | 40:976df7c37ad5 | 109 | uint32_t RESERVED1[32]; |
emilmont | 40:976df7c37ad5 | 110 | uint32_t VectPriority[32]; |
emilmont | 40:976df7c37ad5 | 111 | uint32_t RESERVED2[800]; |
emilmont | 40:976df7c37ad5 | 112 | uint32_t Address; |
emilmont | 40:976df7c37ad5 | 113 | } NVIC_TypeDef; |
emilmont | 40:976df7c37ad5 | 114 | |
emilmont | 40:976df7c37ad5 | 115 | #define NVIC_BASE (0xFFFFF000) |
emilmont | 40:976df7c37ad5 | 116 | #define NVIC (( NVIC_TypeDef *) NVIC_BASE) |
emilmont | 40:976df7c37ad5 | 117 | |
emilmont | 40:976df7c37ad5 | 118 | |
emilmont | 40:976df7c37ad5 | 119 | |
emilmont | 40:976df7c37ad5 | 120 | /** |
emilmont | 40:976df7c37ad5 | 121 | * IO definitions |
emilmont | 40:976df7c37ad5 | 122 | * |
emilmont | 40:976df7c37ad5 | 123 | * define access restrictions to peripheral registers |
emilmont | 40:976df7c37ad5 | 124 | */ |
emilmont | 40:976df7c37ad5 | 125 | |
emilmont | 40:976df7c37ad5 | 126 | #ifdef __cplusplus |
emilmont | 40:976df7c37ad5 | 127 | #define __I volatile /*!< defines 'read only' permissions */ |
emilmont | 40:976df7c37ad5 | 128 | #else |
emilmont | 40:976df7c37ad5 | 129 | #define __I volatile const /*!< defines 'read only' permissions */ |
emilmont | 40:976df7c37ad5 | 130 | #endif |
emilmont | 40:976df7c37ad5 | 131 | #define __O volatile /*!< defines 'write only' permissions */ |
emilmont | 40:976df7c37ad5 | 132 | #define __IO volatile /*!< defines 'read / write' permissions */ |
emilmont | 40:976df7c37ad5 | 133 | |
emilmont | 40:976df7c37ad5 | 134 | |
emilmont | 40:976df7c37ad5 | 135 | |
emilmont | 40:976df7c37ad5 | 136 | |
emilmont | 40:976df7c37ad5 | 137 | |
emilmont | 40:976df7c37ad5 | 138 | #if defined ( __CC_ARM ) |
emilmont | 40:976df7c37ad5 | 139 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
emilmont | 40:976df7c37ad5 | 140 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
emilmont | 40:976df7c37ad5 | 141 | |
emilmont | 40:976df7c37ad5 | 142 | #elif defined ( __ICCARM__ ) |
emilmont | 40:976df7c37ad5 | 143 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
emilmont | 40:976df7c37ad5 | 144 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ |
emilmont | 40:976df7c37ad5 | 145 | |
emilmont | 40:976df7c37ad5 | 146 | #elif defined ( __GNUC__ ) |
emilmont | 40:976df7c37ad5 | 147 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
emilmont | 40:976df7c37ad5 | 148 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
emilmont | 40:976df7c37ad5 | 149 | |
emilmont | 40:976df7c37ad5 | 150 | #elif defined ( __TASKING__ ) |
emilmont | 40:976df7c37ad5 | 151 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
emilmont | 40:976df7c37ad5 | 152 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
emilmont | 40:976df7c37ad5 | 153 | |
emilmont | 40:976df7c37ad5 | 154 | #endif |
emilmont | 40:976df7c37ad5 | 155 | |
emilmont | 40:976df7c37ad5 | 156 | |
emilmont | 40:976df7c37ad5 | 157 | /* ################### Compiler specific Intrinsics ########################### */ |
emilmont | 40:976df7c37ad5 | 158 | |
emilmont | 40:976df7c37ad5 | 159 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
emilmont | 40:976df7c37ad5 | 160 | /* ARM armcc specific functions */ |
emilmont | 40:976df7c37ad5 | 161 | |
emilmont | 40:976df7c37ad5 | 162 | #define __enable_fault_irq __enable_fiq |
emilmont | 40:976df7c37ad5 | 163 | #define __disable_fault_irq __disable_fiq |
emilmont | 40:976df7c37ad5 | 164 | |
emilmont | 40:976df7c37ad5 | 165 | #define __NOP __nop |
emilmont | 40:976df7c37ad5 | 166 | //#define __WFI __wfi |
emilmont | 40:976df7c37ad5 | 167 | //#define __WFE __wfe |
emilmont | 40:976df7c37ad5 | 168 | //#define __SEV __sev |
emilmont | 40:976df7c37ad5 | 169 | //#define __ISB() __isb(0) |
emilmont | 40:976df7c37ad5 | 170 | //#define __DSB() __dsb(0) |
emilmont | 40:976df7c37ad5 | 171 | //#define __DMB() __dmb(0) |
emilmont | 40:976df7c37ad5 | 172 | //#define __REV __rev |
emilmont | 40:976df7c37ad5 | 173 | //#define __RBIT __rbit |
emilmont | 40:976df7c37ad5 | 174 | #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) |
emilmont | 40:976df7c37ad5 | 175 | #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) |
emilmont | 40:976df7c37ad5 | 176 | #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) |
emilmont | 40:976df7c37ad5 | 177 | #define __STREXB(value, ptr) __strex(value, ptr) |
emilmont | 40:976df7c37ad5 | 178 | #define __STREXH(value, ptr) __strex(value, ptr) |
emilmont | 40:976df7c37ad5 | 179 | #define __STREXW(value, ptr) __strex(value, ptr) |
emilmont | 40:976df7c37ad5 | 180 | |
emilmont | 40:976df7c37ad5 | 181 | |
emilmont | 40:976df7c37ad5 | 182 | #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ |
emilmont | 40:976df7c37ad5 | 183 | |
emilmont | 40:976df7c37ad5 | 184 | #define __enable_irq __enable_interrupt /*!< global Interrupt enable */ |
emilmont | 40:976df7c37ad5 | 185 | #define __disable_irq __disable_interrupt /*!< global Interrupt disable */ |
emilmont | 40:976df7c37ad5 | 186 | #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ |
emilmont | 40:976df7c37ad5 | 187 | |
emilmont | 40:976df7c37ad5 | 188 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
emilmont | 40:976df7c37ad5 | 189 | |
emilmont | 40:976df7c37ad5 | 190 | static __INLINE void __enable_irq() { |
emilmont | 40:976df7c37ad5 | 191 | unsigned long temp; |
emilmont | 40:976df7c37ad5 | 192 | __asm__ __volatile__("mrs %0, cpsr\n" |
emilmont | 40:976df7c37ad5 | 193 | "bic %0, %0, #0x80\n" |
emilmont | 40:976df7c37ad5 | 194 | "msr cpsr_c, %0" |
emilmont | 40:976df7c37ad5 | 195 | : "=r" (temp) |
emilmont | 40:976df7c37ad5 | 196 | : |
emilmont | 40:976df7c37ad5 | 197 | : "memory"); |
emilmont | 40:976df7c37ad5 | 198 | } |
emilmont | 40:976df7c37ad5 | 199 | |
emilmont | 40:976df7c37ad5 | 200 | static __INLINE void __disable_irq() { |
emilmont | 40:976df7c37ad5 | 201 | unsigned long old,temp; |
emilmont | 40:976df7c37ad5 | 202 | __asm__ __volatile__("mrs %0, cpsr\n" |
emilmont | 40:976df7c37ad5 | 203 | "orr %1, %0, #0xc0\n" |
emilmont | 40:976df7c37ad5 | 204 | "msr cpsr_c, %1" |
emilmont | 40:976df7c37ad5 | 205 | : "=r" (old), "=r" (temp) |
emilmont | 40:976df7c37ad5 | 206 | : |
emilmont | 40:976df7c37ad5 | 207 | : "memory"); |
emilmont | 40:976df7c37ad5 | 208 | // return (old & 0x80) == 0; |
emilmont | 40:976df7c37ad5 | 209 | } |
emilmont | 40:976df7c37ad5 | 210 | |
emilmont | 40:976df7c37ad5 | 211 | static __INLINE void __NOP() { __ASM volatile ("nop"); } |
emilmont | 40:976df7c37ad5 | 212 | |
emilmont | 40:976df7c37ad5 | 213 | #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ |
emilmont | 40:976df7c37ad5 | 214 | /* TASKING carm specific functions */ |
emilmont | 40:976df7c37ad5 | 215 | |
emilmont | 40:976df7c37ad5 | 216 | /* |
emilmont | 40:976df7c37ad5 | 217 | * The CMSIS functions have been implemented as intrinsics in the compiler. |
emilmont | 40:976df7c37ad5 | 218 | * Please use "carm -?i" to get an up to date list of all instrinsics, |
emilmont | 40:976df7c37ad5 | 219 | * Including the CMSIS ones. |
emilmont | 40:976df7c37ad5 | 220 | */ |
emilmont | 40:976df7c37ad5 | 221 | |
emilmont | 40:976df7c37ad5 | 222 | #endif |
emilmont | 40:976df7c37ad5 | 223 | |
emilmont | 40:976df7c37ad5 | 224 | |
emilmont | 40:976df7c37ad5 | 225 | /** |
emilmont | 40:976df7c37ad5 | 226 | * @brief Enable Interrupt in NVIC Interrupt Controller |
emilmont | 40:976df7c37ad5 | 227 | * |
emilmont | 40:976df7c37ad5 | 228 | * @param IRQn_Type IRQn specifies the interrupt number |
emilmont | 40:976df7c37ad5 | 229 | * @return none |
emilmont | 40:976df7c37ad5 | 230 | * |
emilmont | 40:976df7c37ad5 | 231 | * Enable a device specific interupt in the NVIC interrupt controller. |
emilmont | 40:976df7c37ad5 | 232 | * The interrupt number cannot be a negative value. |
emilmont | 40:976df7c37ad5 | 233 | */ |
emilmont | 40:976df7c37ad5 | 234 | static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
emilmont | 40:976df7c37ad5 | 235 | { |
emilmont | 40:976df7c37ad5 | 236 | NVIC->IntEnable = 1 << (uint32_t)IRQn; |
emilmont | 40:976df7c37ad5 | 237 | } |
emilmont | 40:976df7c37ad5 | 238 | |
emilmont | 40:976df7c37ad5 | 239 | |
emilmont | 40:976df7c37ad5 | 240 | /** |
emilmont | 40:976df7c37ad5 | 241 | * @brief Disable the interrupt line for external interrupt specified |
emilmont | 40:976df7c37ad5 | 242 | * |
emilmont | 40:976df7c37ad5 | 243 | * @param IRQn_Type IRQn is the positive number of the external interrupt |
emilmont | 40:976df7c37ad5 | 244 | * @return none |
emilmont | 40:976df7c37ad5 | 245 | * |
emilmont | 40:976df7c37ad5 | 246 | * Disable a device specific interupt in the NVIC interrupt controller. |
emilmont | 40:976df7c37ad5 | 247 | * The interrupt number cannot be a negative value. |
emilmont | 40:976df7c37ad5 | 248 | */ |
emilmont | 40:976df7c37ad5 | 249 | static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
emilmont | 40:976df7c37ad5 | 250 | { |
emilmont | 40:976df7c37ad5 | 251 | NVIC->IntEnClr = 1 << (uint32_t)IRQn; |
emilmont | 40:976df7c37ad5 | 252 | } |
emilmont | 40:976df7c37ad5 | 253 | |
emilmont | 40:976df7c37ad5 | 254 | |
emilmont | 40:976df7c37ad5 | 255 | #ifdef __cplusplus |
emilmont | 40:976df7c37ad5 | 256 | } |
emilmont | 40:976df7c37ad5 | 257 | #endif |
emilmont | 40:976df7c37ad5 | 258 | |
emilmont | 40:976df7c37ad5 | 259 | #endif /* __ARM7_CORE_H__ */ |
emilmont | 40:976df7c37ad5 | 260 | |
emilmont | 40:976df7c37ad5 | 261 | /*lint -restore */ |