Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.
Dependents: 1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB
Fork of mbed by
TARGET_EFM32ZG_STK3200/efm32zg_rtc.h@98:8ab26030e058, 2015-04-29 (annotated)
- Committer:
- Kojto
- Date:
- Wed Apr 29 10:16:23 2015 +0100
- Revision:
- 98:8ab26030e058
- Child:
- 113:f141b2784e32
Release 98 of the mbed library
Changes:
- Silabs new targets (Giant, Zero, Happy, Leopard, Wonder Geckos)
- Asynchronous SPI, I2C, Serial
- LowPower classes
- Nordic - nordic SDK v8.0 update
- Teensy - gcc arm fix for startup
- Nucleo F411 - usb freq fix
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 98:8ab26030e058 | 1 | /**************************************************************************//** |
Kojto | 98:8ab26030e058 | 2 | * @file efm32zg_rtc.h |
Kojto | 98:8ab26030e058 | 3 | * @brief EFM32ZG_RTC register and bit field definitions |
Kojto | 98:8ab26030e058 | 4 | * @version 3.20.6 |
Kojto | 98:8ab26030e058 | 5 | ****************************************************************************** |
Kojto | 98:8ab26030e058 | 6 | * @section License |
Kojto | 98:8ab26030e058 | 7 | * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> |
Kojto | 98:8ab26030e058 | 8 | ****************************************************************************** |
Kojto | 98:8ab26030e058 | 9 | * |
Kojto | 98:8ab26030e058 | 10 | * Permission is granted to anyone to use this software for any purpose, |
Kojto | 98:8ab26030e058 | 11 | * including commercial applications, and to alter it and redistribute it |
Kojto | 98:8ab26030e058 | 12 | * freely, subject to the following restrictions: |
Kojto | 98:8ab26030e058 | 13 | * |
Kojto | 98:8ab26030e058 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
Kojto | 98:8ab26030e058 | 15 | * claim that you wrote the original software.@n |
Kojto | 98:8ab26030e058 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
Kojto | 98:8ab26030e058 | 17 | * misrepresented as being the original software.@n |
Kojto | 98:8ab26030e058 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
Kojto | 98:8ab26030e058 | 19 | * |
Kojto | 98:8ab26030e058 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
Kojto | 98:8ab26030e058 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
Kojto | 98:8ab26030e058 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
Kojto | 98:8ab26030e058 | 23 | * kind, including, but not limited to, any implied warranties of |
Kojto | 98:8ab26030e058 | 24 | * merchantability or fitness for any particular purpose or warranties against |
Kojto | 98:8ab26030e058 | 25 | * infringement of any proprietary rights of a third party. |
Kojto | 98:8ab26030e058 | 26 | * |
Kojto | 98:8ab26030e058 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
Kojto | 98:8ab26030e058 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
Kojto | 98:8ab26030e058 | 29 | * any third party, arising from your use of this Software. |
Kojto | 98:8ab26030e058 | 30 | * |
Kojto | 98:8ab26030e058 | 31 | *****************************************************************************/ |
Kojto | 98:8ab26030e058 | 32 | /**************************************************************************//** |
Kojto | 98:8ab26030e058 | 33 | * @defgroup EFM32ZG_RTC |
Kojto | 98:8ab26030e058 | 34 | * @{ |
Kojto | 98:8ab26030e058 | 35 | * @brief EFM32ZG_RTC Register Declaration |
Kojto | 98:8ab26030e058 | 36 | *****************************************************************************/ |
Kojto | 98:8ab26030e058 | 37 | typedef struct |
Kojto | 98:8ab26030e058 | 38 | { |
Kojto | 98:8ab26030e058 | 39 | __IO uint32_t CTRL; /**< Control Register */ |
Kojto | 98:8ab26030e058 | 40 | __IO uint32_t CNT; /**< Counter Value Register */ |
Kojto | 98:8ab26030e058 | 41 | __IO uint32_t COMP0; /**< Compare Value Register 0 */ |
Kojto | 98:8ab26030e058 | 42 | __IO uint32_t COMP1; /**< Compare Value Register 1 */ |
Kojto | 98:8ab26030e058 | 43 | __I uint32_t IF; /**< Interrupt Flag Register */ |
Kojto | 98:8ab26030e058 | 44 | __IO uint32_t IFS; /**< Interrupt Flag Set Register */ |
Kojto | 98:8ab26030e058 | 45 | __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ |
Kojto | 98:8ab26030e058 | 46 | __IO uint32_t IEN; /**< Interrupt Enable Register */ |
Kojto | 98:8ab26030e058 | 47 | |
Kojto | 98:8ab26030e058 | 48 | __IO uint32_t FREEZE; /**< Freeze Register */ |
Kojto | 98:8ab26030e058 | 49 | __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
Kojto | 98:8ab26030e058 | 50 | } RTC_TypeDef; /** @} */ |
Kojto | 98:8ab26030e058 | 51 | |
Kojto | 98:8ab26030e058 | 52 | /**************************************************************************//** |
Kojto | 98:8ab26030e058 | 53 | * @defgroup EFM32ZG_RTC_BitFields |
Kojto | 98:8ab26030e058 | 54 | * @{ |
Kojto | 98:8ab26030e058 | 55 | *****************************************************************************/ |
Kojto | 98:8ab26030e058 | 56 | |
Kojto | 98:8ab26030e058 | 57 | /* Bit fields for RTC CTRL */ |
Kojto | 98:8ab26030e058 | 58 | #define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 59 | #define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 60 | #define RTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */ |
Kojto | 98:8ab26030e058 | 61 | #define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */ |
Kojto | 98:8ab26030e058 | 62 | #define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */ |
Kojto | 98:8ab26030e058 | 63 | #define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 64 | #define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 65 | #define RTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ |
Kojto | 98:8ab26030e058 | 66 | #define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */ |
Kojto | 98:8ab26030e058 | 67 | #define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */ |
Kojto | 98:8ab26030e058 | 68 | #define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 69 | #define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 70 | #define RTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */ |
Kojto | 98:8ab26030e058 | 71 | #define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */ |
Kojto | 98:8ab26030e058 | 72 | #define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */ |
Kojto | 98:8ab26030e058 | 73 | #define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 74 | #define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 75 | #define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 76 | #define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 77 | #define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 78 | #define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 79 | |
Kojto | 98:8ab26030e058 | 80 | /* Bit fields for RTC CNT */ |
Kojto | 98:8ab26030e058 | 81 | #define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */ |
Kojto | 98:8ab26030e058 | 82 | #define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */ |
Kojto | 98:8ab26030e058 | 83 | #define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */ |
Kojto | 98:8ab26030e058 | 84 | #define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */ |
Kojto | 98:8ab26030e058 | 85 | #define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */ |
Kojto | 98:8ab26030e058 | 86 | #define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */ |
Kojto | 98:8ab26030e058 | 87 | |
Kojto | 98:8ab26030e058 | 88 | /* Bit fields for RTC COMP0 */ |
Kojto | 98:8ab26030e058 | 89 | #define _RTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 90 | #define _RTC_COMP0_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 91 | #define _RTC_COMP0_COMP0_SHIFT 0 /**< Shift value for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 92 | #define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 93 | #define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 94 | #define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 95 | |
Kojto | 98:8ab26030e058 | 96 | /* Bit fields for RTC COMP1 */ |
Kojto | 98:8ab26030e058 | 97 | #define _RTC_COMP1_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 98 | #define _RTC_COMP1_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 99 | #define _RTC_COMP1_COMP1_SHIFT 0 /**< Shift value for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 100 | #define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 101 | #define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 102 | #define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 103 | |
Kojto | 98:8ab26030e058 | 104 | /* Bit fields for RTC IF */ |
Kojto | 98:8ab26030e058 | 105 | #define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */ |
Kojto | 98:8ab26030e058 | 106 | #define _RTC_IF_MASK 0x00000007UL /**< Mask for RTC_IF */ |
Kojto | 98:8ab26030e058 | 107 | #define RTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ |
Kojto | 98:8ab26030e058 | 108 | #define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */ |
Kojto | 98:8ab26030e058 | 109 | #define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ |
Kojto | 98:8ab26030e058 | 110 | #define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ |
Kojto | 98:8ab26030e058 | 111 | #define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IF */ |
Kojto | 98:8ab26030e058 | 112 | #define RTC_IF_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Flag */ |
Kojto | 98:8ab26030e058 | 113 | #define _RTC_IF_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 114 | #define _RTC_IF_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 115 | #define _RTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ |
Kojto | 98:8ab26030e058 | 116 | #define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */ |
Kojto | 98:8ab26030e058 | 117 | #define RTC_IF_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Flag */ |
Kojto | 98:8ab26030e058 | 118 | #define _RTC_IF_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 119 | #define _RTC_IF_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 120 | #define _RTC_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ |
Kojto | 98:8ab26030e058 | 121 | #define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IF */ |
Kojto | 98:8ab26030e058 | 122 | |
Kojto | 98:8ab26030e058 | 123 | /* Bit fields for RTC IFS */ |
Kojto | 98:8ab26030e058 | 124 | #define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */ |
Kojto | 98:8ab26030e058 | 125 | #define _RTC_IFS_MASK 0x00000007UL /**< Mask for RTC_IFS */ |
Kojto | 98:8ab26030e058 | 126 | #define RTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */ |
Kojto | 98:8ab26030e058 | 127 | #define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */ |
Kojto | 98:8ab26030e058 | 128 | #define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ |
Kojto | 98:8ab26030e058 | 129 | #define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ |
Kojto | 98:8ab26030e058 | 130 | #define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFS */ |
Kojto | 98:8ab26030e058 | 131 | #define RTC_IFS_COMP0 (0x1UL << 1) /**< Set Compare match 0 Interrupt Flag */ |
Kojto | 98:8ab26030e058 | 132 | #define _RTC_IFS_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 133 | #define _RTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 134 | #define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ |
Kojto | 98:8ab26030e058 | 135 | #define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */ |
Kojto | 98:8ab26030e058 | 136 | #define RTC_IFS_COMP1 (0x1UL << 2) /**< Set Compare match 1 Interrupt Flag */ |
Kojto | 98:8ab26030e058 | 137 | #define _RTC_IFS_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 138 | #define _RTC_IFS_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 139 | #define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ |
Kojto | 98:8ab26030e058 | 140 | #define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFS */ |
Kojto | 98:8ab26030e058 | 141 | |
Kojto | 98:8ab26030e058 | 142 | /* Bit fields for RTC IFC */ |
Kojto | 98:8ab26030e058 | 143 | #define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */ |
Kojto | 98:8ab26030e058 | 144 | #define _RTC_IFC_MASK 0x00000007UL /**< Mask for RTC_IFC */ |
Kojto | 98:8ab26030e058 | 145 | #define RTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */ |
Kojto | 98:8ab26030e058 | 146 | #define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */ |
Kojto | 98:8ab26030e058 | 147 | #define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ |
Kojto | 98:8ab26030e058 | 148 | #define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ |
Kojto | 98:8ab26030e058 | 149 | #define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFC */ |
Kojto | 98:8ab26030e058 | 150 | #define RTC_IFC_COMP0 (0x1UL << 1) /**< Clear Compare match 0 Interrupt Flag */ |
Kojto | 98:8ab26030e058 | 151 | #define _RTC_IFC_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 152 | #define _RTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 153 | #define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ |
Kojto | 98:8ab26030e058 | 154 | #define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */ |
Kojto | 98:8ab26030e058 | 155 | #define RTC_IFC_COMP1 (0x1UL << 2) /**< Clear Compare match 1 Interrupt Flag */ |
Kojto | 98:8ab26030e058 | 156 | #define _RTC_IFC_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 157 | #define _RTC_IFC_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 158 | #define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ |
Kojto | 98:8ab26030e058 | 159 | #define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFC */ |
Kojto | 98:8ab26030e058 | 160 | |
Kojto | 98:8ab26030e058 | 161 | /* Bit fields for RTC IEN */ |
Kojto | 98:8ab26030e058 | 162 | #define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */ |
Kojto | 98:8ab26030e058 | 163 | #define _RTC_IEN_MASK 0x00000007UL /**< Mask for RTC_IEN */ |
Kojto | 98:8ab26030e058 | 164 | #define RTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ |
Kojto | 98:8ab26030e058 | 165 | #define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */ |
Kojto | 98:8ab26030e058 | 166 | #define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ |
Kojto | 98:8ab26030e058 | 167 | #define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ |
Kojto | 98:8ab26030e058 | 168 | #define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IEN */ |
Kojto | 98:8ab26030e058 | 169 | #define RTC_IEN_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Enable */ |
Kojto | 98:8ab26030e058 | 170 | #define _RTC_IEN_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 171 | #define _RTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 172 | #define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ |
Kojto | 98:8ab26030e058 | 173 | #define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */ |
Kojto | 98:8ab26030e058 | 174 | #define RTC_IEN_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Enable */ |
Kojto | 98:8ab26030e058 | 175 | #define _RTC_IEN_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 176 | #define _RTC_IEN_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 177 | #define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ |
Kojto | 98:8ab26030e058 | 178 | #define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IEN */ |
Kojto | 98:8ab26030e058 | 179 | |
Kojto | 98:8ab26030e058 | 180 | /* Bit fields for RTC FREEZE */ |
Kojto | 98:8ab26030e058 | 181 | #define _RTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for RTC_FREEZE */ |
Kojto | 98:8ab26030e058 | 182 | #define _RTC_FREEZE_MASK 0x00000001UL /**< Mask for RTC_FREEZE */ |
Kojto | 98:8ab26030e058 | 183 | #define RTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ |
Kojto | 98:8ab26030e058 | 184 | #define _RTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for RTC_REGFREEZE */ |
Kojto | 98:8ab26030e058 | 185 | #define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for RTC_REGFREEZE */ |
Kojto | 98:8ab26030e058 | 186 | #define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_FREEZE */ |
Kojto | 98:8ab26030e058 | 187 | #define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for RTC_FREEZE */ |
Kojto | 98:8ab26030e058 | 188 | #define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for RTC_FREEZE */ |
Kojto | 98:8ab26030e058 | 189 | #define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */ |
Kojto | 98:8ab26030e058 | 190 | #define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for RTC_FREEZE */ |
Kojto | 98:8ab26030e058 | 191 | #define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for RTC_FREEZE */ |
Kojto | 98:8ab26030e058 | 192 | |
Kojto | 98:8ab26030e058 | 193 | /* Bit fields for RTC SYNCBUSY */ |
Kojto | 98:8ab26030e058 | 194 | #define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTC_SYNCBUSY */ |
Kojto | 98:8ab26030e058 | 195 | #define _RTC_SYNCBUSY_MASK 0x00000007UL /**< Mask for RTC_SYNCBUSY */ |
Kojto | 98:8ab26030e058 | 196 | #define RTC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ |
Kojto | 98:8ab26030e058 | 197 | #define _RTC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 198 | #define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for RTC_CTRL */ |
Kojto | 98:8ab26030e058 | 199 | #define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ |
Kojto | 98:8ab26030e058 | 200 | #define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ |
Kojto | 98:8ab26030e058 | 201 | #define RTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< COMP0 Register Busy */ |
Kojto | 98:8ab26030e058 | 202 | #define _RTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 203 | #define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ |
Kojto | 98:8ab26030e058 | 204 | #define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ |
Kojto | 98:8ab26030e058 | 205 | #define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ |
Kojto | 98:8ab26030e058 | 206 | #define RTC_SYNCBUSY_COMP1 (0x1UL << 2) /**< COMP1 Register Busy */ |
Kojto | 98:8ab26030e058 | 207 | #define _RTC_SYNCBUSY_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 208 | #define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ |
Kojto | 98:8ab26030e058 | 209 | #define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ |
Kojto | 98:8ab26030e058 | 210 | #define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ |
Kojto | 98:8ab26030e058 | 211 | |
Kojto | 98:8ab26030e058 | 212 | /** @} End of group EFM32ZG_RTC */ |
Kojto | 98:8ab26030e058 | 213 | |
Kojto | 98:8ab26030e058 | 214 |