Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_EFM32ZG_STK3200/efm32zg_cmu.h@98:8ab26030e058, 2015-04-29 (annotated)

Committer:
Kojto
Date:
Wed Apr 29 10:16:23 2015 +0100
Revision:
98:8ab26030e058
Child:
113:f141b2784e32
Release 98 of the mbed library



Changes:

 - Silabs new targets (Giant, Zero, Happy, Leopard, Wonder Geckos)

 - Asynchronous SPI, I2C, Serial

 - LowPower classes

 - Nordic - nordic SDK v8.0 update

 - Teensy - gcc arm fix for startup

 - Nucleo F411 - usb freq fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 98:8ab26030e058 1 /**************************************************************************//**
Kojto 98:8ab26030e058 2 * @file efm32zg_cmu.h
Kojto 98:8ab26030e058 3 * @brief EFM32ZG_CMU register and bit field definitions
Kojto 98:8ab26030e058 4 * @version 3.20.6
Kojto 98:8ab26030e058 5 ******************************************************************************
Kojto 98:8ab26030e058 6 * @section License
Kojto 98:8ab26030e058 7 * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
Kojto 98:8ab26030e058 8 ******************************************************************************
Kojto 98:8ab26030e058 9 *
Kojto 98:8ab26030e058 10 * Permission is granted to anyone to use this software for any purpose,
Kojto 98:8ab26030e058 11 * including commercial applications, and to alter it and redistribute it
Kojto 98:8ab26030e058 12 * freely, subject to the following restrictions:
Kojto 98:8ab26030e058 13 *
Kojto 98:8ab26030e058 14 * 1. The origin of this software must not be misrepresented; you must not
Kojto 98:8ab26030e058 15 * claim that you wrote the original software.@n
Kojto 98:8ab26030e058 16 * 2. Altered source versions must be plainly marked as such, and must not be
Kojto 98:8ab26030e058 17 * misrepresented as being the original software.@n
Kojto 98:8ab26030e058 18 * 3. This notice may not be removed or altered from any source distribution.
Kojto 98:8ab26030e058 19 *
Kojto 98:8ab26030e058 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
Kojto 98:8ab26030e058 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
Kojto 98:8ab26030e058 22 * providing the Software "AS IS", with no express or implied warranties of any
Kojto 98:8ab26030e058 23 * kind, including, but not limited to, any implied warranties of
Kojto 98:8ab26030e058 24 * merchantability or fitness for any particular purpose or warranties against
Kojto 98:8ab26030e058 25 * infringement of any proprietary rights of a third party.
Kojto 98:8ab26030e058 26 *
Kojto 98:8ab26030e058 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
Kojto 98:8ab26030e058 28 * incidental, or special damages, or any other relief, or for any claim by
Kojto 98:8ab26030e058 29 * any third party, arising from your use of this Software.
Kojto 98:8ab26030e058 30 *
Kojto 98:8ab26030e058 31 *****************************************************************************/
Kojto 98:8ab26030e058 32 /**************************************************************************//**
Kojto 98:8ab26030e058 33 * @defgroup EFM32ZG_CMU
Kojto 98:8ab26030e058 34 * @{
Kojto 98:8ab26030e058 35 * @brief EFM32ZG_CMU Register Declaration
Kojto 98:8ab26030e058 36 *****************************************************************************/
Kojto 98:8ab26030e058 37 typedef struct
Kojto 98:8ab26030e058 38 {
Kojto 98:8ab26030e058 39 __IO uint32_t CTRL; /**< CMU Control Register */
Kojto 98:8ab26030e058 40 __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
Kojto 98:8ab26030e058 41 __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
Kojto 98:8ab26030e058 42 __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */
Kojto 98:8ab26030e058 43 __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */
Kojto 98:8ab26030e058 44 __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
Kojto 98:8ab26030e058 45 __IO uint32_t CALCTRL; /**< Calibration Control Register */
Kojto 98:8ab26030e058 46 __IO uint32_t CALCNT; /**< Calibration Counter Register */
Kojto 98:8ab26030e058 47 __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
Kojto 98:8ab26030e058 48 __IO uint32_t CMD; /**< Command Register */
Kojto 98:8ab26030e058 49 __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
Kojto 98:8ab26030e058 50 __I uint32_t STATUS; /**< Status Register */
Kojto 98:8ab26030e058 51 __I uint32_t IF; /**< Interrupt Flag Register */
Kojto 98:8ab26030e058 52 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
Kojto 98:8ab26030e058 53 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
Kojto 98:8ab26030e058 54 __IO uint32_t IEN; /**< Interrupt Enable Register */
Kojto 98:8ab26030e058 55 __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
Kojto 98:8ab26030e058 56 __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
Kojto 98:8ab26030e058 57 uint32_t RESERVED0[2]; /**< Reserved for future use **/
Kojto 98:8ab26030e058 58 __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
Kojto 98:8ab26030e058 59 __IO uint32_t FREEZE; /**< Freeze Register */
Kojto 98:8ab26030e058 60 __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
Kojto 98:8ab26030e058 61 uint32_t RESERVED1[1]; /**< Reserved for future use **/
Kojto 98:8ab26030e058 62 __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
Kojto 98:8ab26030e058 63 uint32_t RESERVED2[1]; /**< Reserved for future use **/
Kojto 98:8ab26030e058 64 __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
Kojto 98:8ab26030e058 65 uint32_t RESERVED3[1]; /**< Reserved for future use **/
Kojto 98:8ab26030e058 66 __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
Kojto 98:8ab26030e058 67 uint32_t RESERVED4[1]; /**< Reserved for future use **/
Kojto 98:8ab26030e058 68 __IO uint32_t PCNTCTRL; /**< PCNT Control Register */
Kojto 98:8ab26030e058 69
Kojto 98:8ab26030e058 70 uint32_t RESERVED5[1]; /**< Reserved for future use **/
Kojto 98:8ab26030e058 71 __IO uint32_t ROUTE; /**< I/O Routing Register */
Kojto 98:8ab26030e058 72 __IO uint32_t LOCK; /**< Configuration Lock Register */
Kojto 98:8ab26030e058 73 } CMU_TypeDef; /** @} */
Kojto 98:8ab26030e058 74
Kojto 98:8ab26030e058 75 /**************************************************************************//**
Kojto 98:8ab26030e058 76 * @defgroup EFM32ZG_CMU_BitFields
Kojto 98:8ab26030e058 77 * @{
Kojto 98:8ab26030e058 78 *****************************************************************************/
Kojto 98:8ab26030e058 79
Kojto 98:8ab26030e058 80 /* Bit fields for CMU CTRL */
Kojto 98:8ab26030e058 81 #define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */
Kojto 98:8ab26030e058 82 #define _CMU_CTRL_MASK 0x03FE3EEFUL /**< Mask for CMU_CTRL */
Kojto 98:8ab26030e058 83 #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
Kojto 98:8ab26030e058 84 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
Kojto 98:8ab26030e058 85 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 86 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
Kojto 98:8ab26030e058 87 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 88 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 89 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 90 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */
Kojto 98:8ab26030e058 91 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 92 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 93 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */
Kojto 98:8ab26030e058 94 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */
Kojto 98:8ab26030e058 95 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 96 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 97 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 98 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 99 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 100 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 101 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 102 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 103 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 104 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 105 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */
Kojto 98:8ab26030e058 106 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */
Kojto 98:8ab26030e058 107 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 108 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 109 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */
Kojto 98:8ab26030e058 110 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */
Kojto 98:8ab26030e058 111 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */
Kojto 98:8ab26030e058 112 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 113 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 114 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */
Kojto 98:8ab26030e058 115 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */
Kojto 98:8ab26030e058 116 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 117 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 118 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 119 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 120 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 121 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 122 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 123 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 124 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 125 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 126 #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */
Kojto 98:8ab26030e058 127 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */
Kojto 98:8ab26030e058 128 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 129 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
Kojto 98:8ab26030e058 130 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 131 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 132 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 133 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */
Kojto 98:8ab26030e058 134 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 135 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 136 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */
Kojto 98:8ab26030e058 137 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */
Kojto 98:8ab26030e058 138 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */
Kojto 98:8ab26030e058 139 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 140 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 141 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 142 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 143 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 144 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 145 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */
Kojto 98:8ab26030e058 146 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */
Kojto 98:8ab26030e058 147 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */
Kojto 98:8ab26030e058 148 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 149 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 150 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */
Kojto 98:8ab26030e058 151 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */
Kojto 98:8ab26030e058 152 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 153 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 154 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 155 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 156 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 157 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 158 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 159 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 160 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 161 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 162 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */
Kojto 98:8ab26030e058 163 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */
Kojto 98:8ab26030e058 164 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 165 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 166 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */
Kojto 98:8ab26030e058 167 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */
Kojto 98:8ab26030e058 168 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */
Kojto 98:8ab26030e058 169 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */
Kojto 98:8ab26030e058 170 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */
Kojto 98:8ab26030e058 171 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 172 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 173 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 174 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 175 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */
Kojto 98:8ab26030e058 176 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */
Kojto 98:8ab26030e058 177 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */
Kojto 98:8ab26030e058 178 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */
Kojto 98:8ab26030e058 179 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */
Kojto 98:8ab26030e058 180 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 181 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 182 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */
Kojto 98:8ab26030e058 183 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x3800000UL /**< Bit mask for CMU_CLKOUTSEL1 */
Kojto 98:8ab26030e058 184 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 185 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 186 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */
Kojto 98:8ab26030e058 187 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */
Kojto 98:8ab26030e058 188 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */
Kojto 98:8ab26030e058 189 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */
Kojto 98:8ab26030e058 190 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */
Kojto 98:8ab26030e058 191 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */
Kojto 98:8ab26030e058 192 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */
Kojto 98:8ab26030e058 193 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 194 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 195 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */
Kojto 98:8ab26030e058 196 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */
Kojto 98:8ab26030e058 197 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */
Kojto 98:8ab26030e058 198 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */
Kojto 98:8ab26030e058 199 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */
Kojto 98:8ab26030e058 200 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */
Kojto 98:8ab26030e058 201 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
Kojto 98:8ab26030e058 202
Kojto 98:8ab26030e058 203 /* Bit fields for CMU HFCORECLKDIV */
Kojto 98:8ab26030e058 204 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 205 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 206 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 207 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 208 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 209 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 210 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 211 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 212 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 213 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 214 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 215 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 216 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 217 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 218 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 219 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 220 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 221 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 222 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 223 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 224 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 225 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 226 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 227 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 228 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 229 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 230 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */
Kojto 98:8ab26030e058 231 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */
Kojto 98:8ab26030e058 232 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */
Kojto 98:8ab26030e058 233 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 234 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 235 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 236 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 237 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 238 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 239
Kojto 98:8ab26030e058 240 /* Bit fields for CMU HFPERCLKDIV */
Kojto 98:8ab26030e058 241 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 242 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 243 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 244 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 245 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 246 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 247 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 248 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 249 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 250 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 251 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 252 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 253 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 254 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 255 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 256 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 257 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 258 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 259 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 260 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 261 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 262 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 263 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 264 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 265 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 266 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 267 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */
Kojto 98:8ab26030e058 268 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */
Kojto 98:8ab26030e058 269 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */
Kojto 98:8ab26030e058 270 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 271 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 272
Kojto 98:8ab26030e058 273 /* Bit fields for CMU HFRCOCTRL */
Kojto 98:8ab26030e058 274 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 275 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 276 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
Kojto 98:8ab26030e058 277 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
Kojto 98:8ab26030e058 278 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 279 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 280 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
Kojto 98:8ab26030e058 281 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
Kojto 98:8ab26030e058 282 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 283 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 284 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 285 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 286 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 287 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 288 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 289 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 290 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 291 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 292 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 293 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 294 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */
Kojto 98:8ab26030e058 295 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */
Kojto 98:8ab26030e058 296 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 297 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 298
Kojto 98:8ab26030e058 299 /* Bit fields for CMU LFRCOCTRL */
Kojto 98:8ab26030e058 300 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */
Kojto 98:8ab26030e058 301 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */
Kojto 98:8ab26030e058 302 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
Kojto 98:8ab26030e058 303 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
Kojto 98:8ab26030e058 304 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
Kojto 98:8ab26030e058 305 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
Kojto 98:8ab26030e058 306
Kojto 98:8ab26030e058 307 /* Bit fields for CMU AUXHFRCOCTRL */
Kojto 98:8ab26030e058 308 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 309 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 310 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
Kojto 98:8ab26030e058 311 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
Kojto 98:8ab26030e058 312 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 313 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 314 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
Kojto 98:8ab26030e058 315 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
Kojto 98:8ab26030e058 316 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 317 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 318 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 319 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 320 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 321 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 322 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 323 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 324 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 325 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 326 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 327 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 328
Kojto 98:8ab26030e058 329 /* Bit fields for CMU CALCTRL */
Kojto 98:8ab26030e058 330 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
Kojto 98:8ab26030e058 331 #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */
Kojto 98:8ab26030e058 332 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
Kojto 98:8ab26030e058 333 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */
Kojto 98:8ab26030e058 334 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
Kojto 98:8ab26030e058 335 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 336 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 337 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 338 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 339 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 340 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
Kojto 98:8ab26030e058 341 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 342 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 343 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 344 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 345 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 346 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */
Kojto 98:8ab26030e058 347 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */
Kojto 98:8ab26030e058 348 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
Kojto 98:8ab26030e058 349 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
Kojto 98:8ab26030e058 350 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 351 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 352 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 353 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 354 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 355 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */
Kojto 98:8ab26030e058 356 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */
Kojto 98:8ab26030e058 357 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 358 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 359 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 360 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 361 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 362 #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */
Kojto 98:8ab26030e058 363 #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */
Kojto 98:8ab26030e058 364 #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */
Kojto 98:8ab26030e058 365 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
Kojto 98:8ab26030e058 366 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */
Kojto 98:8ab26030e058 367
Kojto 98:8ab26030e058 368 /* Bit fields for CMU CALCNT */
Kojto 98:8ab26030e058 369 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
Kojto 98:8ab26030e058 370 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
Kojto 98:8ab26030e058 371 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
Kojto 98:8ab26030e058 372 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
Kojto 98:8ab26030e058 373 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
Kojto 98:8ab26030e058 374 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
Kojto 98:8ab26030e058 375
Kojto 98:8ab26030e058 376 /* Bit fields for CMU OSCENCMD */
Kojto 98:8ab26030e058 377 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
Kojto 98:8ab26030e058 378 #define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */
Kojto 98:8ab26030e058 379 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
Kojto 98:8ab26030e058 380 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
Kojto 98:8ab26030e058 381 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
Kojto 98:8ab26030e058 382 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 383 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 384 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
Kojto 98:8ab26030e058 385 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
Kojto 98:8ab26030e058 386 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
Kojto 98:8ab26030e058 387 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 388 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 389 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
Kojto 98:8ab26030e058 390 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
Kojto 98:8ab26030e058 391 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
Kojto 98:8ab26030e058 392 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 393 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 394 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
Kojto 98:8ab26030e058 395 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
Kojto 98:8ab26030e058 396 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
Kojto 98:8ab26030e058 397 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 398 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 399 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
Kojto 98:8ab26030e058 400 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
Kojto 98:8ab26030e058 401 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
Kojto 98:8ab26030e058 402 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 403 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 404 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
Kojto 98:8ab26030e058 405 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
Kojto 98:8ab26030e058 406 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
Kojto 98:8ab26030e058 407 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 408 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 409 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
Kojto 98:8ab26030e058 410 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
Kojto 98:8ab26030e058 411 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
Kojto 98:8ab26030e058 412 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 413 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 414 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
Kojto 98:8ab26030e058 415 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
Kojto 98:8ab26030e058 416 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
Kojto 98:8ab26030e058 417 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 418 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 419 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
Kojto 98:8ab26030e058 420 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
Kojto 98:8ab26030e058 421 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
Kojto 98:8ab26030e058 422 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 423 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 424 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
Kojto 98:8ab26030e058 425 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
Kojto 98:8ab26030e058 426 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
Kojto 98:8ab26030e058 427 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 428 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 429
Kojto 98:8ab26030e058 430 /* Bit fields for CMU CMD */
Kojto 98:8ab26030e058 431 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
Kojto 98:8ab26030e058 432 #define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */
Kojto 98:8ab26030e058 433 #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */
Kojto 98:8ab26030e058 434 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */
Kojto 98:8ab26030e058 435 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 436 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */
Kojto 98:8ab26030e058 437 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */
Kojto 98:8ab26030e058 438 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
Kojto 98:8ab26030e058 439 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */
Kojto 98:8ab26030e058 440 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 441 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */
Kojto 98:8ab26030e058 442 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */
Kojto 98:8ab26030e058 443 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */
Kojto 98:8ab26030e058 444 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */
Kojto 98:8ab26030e058 445 #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */
Kojto 98:8ab26030e058 446 #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */
Kojto 98:8ab26030e058 447 #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */
Kojto 98:8ab26030e058 448 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 449 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 450 #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */
Kojto 98:8ab26030e058 451 #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */
Kojto 98:8ab26030e058 452 #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */
Kojto 98:8ab26030e058 453 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 454 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 455
Kojto 98:8ab26030e058 456 /* Bit fields for CMU LFCLKSEL */
Kojto 98:8ab26030e058 457 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 458 #define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 459 #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
Kojto 98:8ab26030e058 460 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */
Kojto 98:8ab26030e058 461 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 462 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 463 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 464 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 465 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 466 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 467 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 468 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 469 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 470 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 471 #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */
Kojto 98:8ab26030e058 472 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */
Kojto 98:8ab26030e058 473 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 474 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 475 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 476 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 477 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 478 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 479 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 480 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 481 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 482 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 483 #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */
Kojto 98:8ab26030e058 484 #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */
Kojto 98:8ab26030e058 485 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */
Kojto 98:8ab26030e058 486 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 487 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 488 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 489 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 490 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 491 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 492 #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */
Kojto 98:8ab26030e058 493 #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */
Kojto 98:8ab26030e058 494 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */
Kojto 98:8ab26030e058 495 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 496 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 497 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 498 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 499 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 500 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 501
Kojto 98:8ab26030e058 502 /* Bit fields for CMU STATUS */
Kojto 98:8ab26030e058 503 #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */
Kojto 98:8ab26030e058 504 #define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */
Kojto 98:8ab26030e058 505 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
Kojto 98:8ab26030e058 506 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
Kojto 98:8ab26030e058 507 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
Kojto 98:8ab26030e058 508 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 509 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 510 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
Kojto 98:8ab26030e058 511 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
Kojto 98:8ab26030e058 512 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
Kojto 98:8ab26030e058 513 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 514 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 515 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
Kojto 98:8ab26030e058 516 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
Kojto 98:8ab26030e058 517 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
Kojto 98:8ab26030e058 518 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 519 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 520 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
Kojto 98:8ab26030e058 521 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
Kojto 98:8ab26030e058 522 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
Kojto 98:8ab26030e058 523 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 524 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 525 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
Kojto 98:8ab26030e058 526 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
Kojto 98:8ab26030e058 527 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
Kojto 98:8ab26030e058 528 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 529 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 530 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
Kojto 98:8ab26030e058 531 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 532 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 533 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 534 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 535 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
Kojto 98:8ab26030e058 536 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
Kojto 98:8ab26030e058 537 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
Kojto 98:8ab26030e058 538 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 539 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 540 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
Kojto 98:8ab26030e058 541 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
Kojto 98:8ab26030e058 542 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
Kojto 98:8ab26030e058 543 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 544 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 545 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
Kojto 98:8ab26030e058 546 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
Kojto 98:8ab26030e058 547 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
Kojto 98:8ab26030e058 548 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 549 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 550 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
Kojto 98:8ab26030e058 551 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
Kojto 98:8ab26030e058 552 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
Kojto 98:8ab26030e058 553 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 554 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 555 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */
Kojto 98:8ab26030e058 556 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */
Kojto 98:8ab26030e058 557 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */
Kojto 98:8ab26030e058 558 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 559 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 560 #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */
Kojto 98:8ab26030e058 561 #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */
Kojto 98:8ab26030e058 562 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */
Kojto 98:8ab26030e058 563 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 564 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 565 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */
Kojto 98:8ab26030e058 566 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */
Kojto 98:8ab26030e058 567 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */
Kojto 98:8ab26030e058 568 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 569 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 570 #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */
Kojto 98:8ab26030e058 571 #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */
Kojto 98:8ab26030e058 572 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */
Kojto 98:8ab26030e058 573 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 574 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 575 #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */
Kojto 98:8ab26030e058 576 #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */
Kojto 98:8ab26030e058 577 #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */
Kojto 98:8ab26030e058 578 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 579 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 580
Kojto 98:8ab26030e058 581 /* Bit fields for CMU IF */
Kojto 98:8ab26030e058 582 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
Kojto 98:8ab26030e058 583 #define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */
Kojto 98:8ab26030e058 584 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
Kojto 98:8ab26030e058 585 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
Kojto 98:8ab26030e058 586 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
Kojto 98:8ab26030e058 587 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 588 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 589 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
Kojto 98:8ab26030e058 590 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
Kojto 98:8ab26030e058 591 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
Kojto 98:8ab26030e058 592 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 593 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 594 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
Kojto 98:8ab26030e058 595 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
Kojto 98:8ab26030e058 596 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
Kojto 98:8ab26030e058 597 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 598 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 599 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
Kojto 98:8ab26030e058 600 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
Kojto 98:8ab26030e058 601 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
Kojto 98:8ab26030e058 602 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 603 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 604 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
Kojto 98:8ab26030e058 605 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 606 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 607 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 608 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 609 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
Kojto 98:8ab26030e058 610 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
Kojto 98:8ab26030e058 611 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
Kojto 98:8ab26030e058 612 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 613 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 614 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
Kojto 98:8ab26030e058 615 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
Kojto 98:8ab26030e058 616 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
Kojto 98:8ab26030e058 617 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 618 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 619
Kojto 98:8ab26030e058 620 /* Bit fields for CMU IFS */
Kojto 98:8ab26030e058 621 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
Kojto 98:8ab26030e058 622 #define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */
Kojto 98:8ab26030e058 623 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */
Kojto 98:8ab26030e058 624 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
Kojto 98:8ab26030e058 625 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
Kojto 98:8ab26030e058 626 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 627 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 628 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */
Kojto 98:8ab26030e058 629 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
Kojto 98:8ab26030e058 630 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
Kojto 98:8ab26030e058 631 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 632 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 633 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */
Kojto 98:8ab26030e058 634 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
Kojto 98:8ab26030e058 635 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
Kojto 98:8ab26030e058 636 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 637 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 638 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */
Kojto 98:8ab26030e058 639 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
Kojto 98:8ab26030e058 640 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
Kojto 98:8ab26030e058 641 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 642 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 643 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */
Kojto 98:8ab26030e058 644 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 645 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 646 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 647 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 648 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */
Kojto 98:8ab26030e058 649 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
Kojto 98:8ab26030e058 650 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
Kojto 98:8ab26030e058 651 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 652 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 653 #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */
Kojto 98:8ab26030e058 654 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
Kojto 98:8ab26030e058 655 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
Kojto 98:8ab26030e058 656 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 657 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 658
Kojto 98:8ab26030e058 659 /* Bit fields for CMU IFC */
Kojto 98:8ab26030e058 660 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
Kojto 98:8ab26030e058 661 #define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */
Kojto 98:8ab26030e058 662 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */
Kojto 98:8ab26030e058 663 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
Kojto 98:8ab26030e058 664 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
Kojto 98:8ab26030e058 665 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 666 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 667 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */
Kojto 98:8ab26030e058 668 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
Kojto 98:8ab26030e058 669 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
Kojto 98:8ab26030e058 670 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 671 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 672 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */
Kojto 98:8ab26030e058 673 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
Kojto 98:8ab26030e058 674 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
Kojto 98:8ab26030e058 675 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 676 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 677 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */
Kojto 98:8ab26030e058 678 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
Kojto 98:8ab26030e058 679 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
Kojto 98:8ab26030e058 680 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 681 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 682 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */
Kojto 98:8ab26030e058 683 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 684 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 685 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 686 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 687 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */
Kojto 98:8ab26030e058 688 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
Kojto 98:8ab26030e058 689 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
Kojto 98:8ab26030e058 690 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 691 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 692 #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */
Kojto 98:8ab26030e058 693 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
Kojto 98:8ab26030e058 694 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
Kojto 98:8ab26030e058 695 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 696 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 697
Kojto 98:8ab26030e058 698 /* Bit fields for CMU IEN */
Kojto 98:8ab26030e058 699 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
Kojto 98:8ab26030e058 700 #define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */
Kojto 98:8ab26030e058 701 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */
Kojto 98:8ab26030e058 702 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
Kojto 98:8ab26030e058 703 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
Kojto 98:8ab26030e058 704 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 705 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 706 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */
Kojto 98:8ab26030e058 707 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
Kojto 98:8ab26030e058 708 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
Kojto 98:8ab26030e058 709 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 710 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 711 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */
Kojto 98:8ab26030e058 712 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
Kojto 98:8ab26030e058 713 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
Kojto 98:8ab26030e058 714 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 715 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 716 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */
Kojto 98:8ab26030e058 717 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
Kojto 98:8ab26030e058 718 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
Kojto 98:8ab26030e058 719 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 720 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 721 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */
Kojto 98:8ab26030e058 722 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 723 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 724 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 725 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 726 #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */
Kojto 98:8ab26030e058 727 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
Kojto 98:8ab26030e058 728 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
Kojto 98:8ab26030e058 729 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 730 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 731 #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */
Kojto 98:8ab26030e058 732 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
Kojto 98:8ab26030e058 733 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
Kojto 98:8ab26030e058 734 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 735 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 736
Kojto 98:8ab26030e058 737 /* Bit fields for CMU HFCORECLKEN0 */
Kojto 98:8ab26030e058 738 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 739 #define _CMU_HFCORECLKEN0_MASK 0x00000007UL /**< Mask for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 740 #define CMU_HFCORECLKEN0_AES (0x1UL << 0) /**< Advanced Encryption Standard Accelerator Clock Enable */
Kojto 98:8ab26030e058 741 #define _CMU_HFCORECLKEN0_AES_SHIFT 0 /**< Shift value for CMU_AES */
Kojto 98:8ab26030e058 742 #define _CMU_HFCORECLKEN0_AES_MASK 0x1UL /**< Bit mask for CMU_AES */
Kojto 98:8ab26030e058 743 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 744 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 745 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1) /**< Direct Memory Access Controller Clock Enable */
Kojto 98:8ab26030e058 746 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1 /**< Shift value for CMU_DMA */
Kojto 98:8ab26030e058 747 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL /**< Bit mask for CMU_DMA */
Kojto 98:8ab26030e058 748 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 749 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 750 #define CMU_HFCORECLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */
Kojto 98:8ab26030e058 751 #define _CMU_HFCORECLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */
Kojto 98:8ab26030e058 752 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */
Kojto 98:8ab26030e058 753 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 754 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 755
Kojto 98:8ab26030e058 756 /* Bit fields for CMU HFPERCLKEN0 */
Kojto 98:8ab26030e058 757 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 758 #define _CMU_HFPERCLKEN0_MASK 0x00000DDFUL /**< Mask for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 759 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */
Kojto 98:8ab26030e058 760 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */
Kojto 98:8ab26030e058 761 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */
Kojto 98:8ab26030e058 762 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 763 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 764 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */
Kojto 98:8ab26030e058 765 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */
Kojto 98:8ab26030e058 766 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */
Kojto 98:8ab26030e058 767 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 768 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 769 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 2) /**< Analog Comparator 0 Clock Enable */
Kojto 98:8ab26030e058 770 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 2 /**< Shift value for CMU_ACMP0 */
Kojto 98:8ab26030e058 771 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x4UL /**< Bit mask for CMU_ACMP0 */
Kojto 98:8ab26030e058 772 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 773 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 774 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 3) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
Kojto 98:8ab26030e058 775 #define _CMU_HFPERCLKEN0_USART1_SHIFT 3 /**< Shift value for CMU_USART1 */
Kojto 98:8ab26030e058 776 #define _CMU_HFPERCLKEN0_USART1_MASK 0x8UL /**< Bit mask for CMU_USART1 */
Kojto 98:8ab26030e058 777 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 778 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 779 #define CMU_HFPERCLKEN0_PRS (0x1UL << 4) /**< Peripheral Reflex System Clock Enable */
Kojto 98:8ab26030e058 780 #define _CMU_HFPERCLKEN0_PRS_SHIFT 4 /**< Shift value for CMU_PRS */
Kojto 98:8ab26030e058 781 #define _CMU_HFPERCLKEN0_PRS_MASK 0x10UL /**< Bit mask for CMU_PRS */
Kojto 98:8ab26030e058 782 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 783 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 784 #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 6) /**< Current Digital to Analog Converter 0 Clock Enable */
Kojto 98:8ab26030e058 785 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 6 /**< Shift value for CMU_IDAC0 */
Kojto 98:8ab26030e058 786 #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x40UL /**< Bit mask for CMU_IDAC0 */
Kojto 98:8ab26030e058 787 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 788 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 789 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 7) /**< General purpose Input/Output Clock Enable */
Kojto 98:8ab26030e058 790 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 7 /**< Shift value for CMU_GPIO */
Kojto 98:8ab26030e058 791 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x80UL /**< Bit mask for CMU_GPIO */
Kojto 98:8ab26030e058 792 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 793 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 794 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 8) /**< Voltage Comparator Clock Enable */
Kojto 98:8ab26030e058 795 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 8 /**< Shift value for CMU_VCMP */
Kojto 98:8ab26030e058 796 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x100UL /**< Bit mask for CMU_VCMP */
Kojto 98:8ab26030e058 797 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 798 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 799 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 10) /**< Analog to Digital Converter 0 Clock Enable */
Kojto 98:8ab26030e058 800 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 10 /**< Shift value for CMU_ADC0 */
Kojto 98:8ab26030e058 801 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x400UL /**< Bit mask for CMU_ADC0 */
Kojto 98:8ab26030e058 802 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 803 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 804 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */
Kojto 98:8ab26030e058 805 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */
Kojto 98:8ab26030e058 806 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */
Kojto 98:8ab26030e058 807 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 808 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 809
Kojto 98:8ab26030e058 810 /* Bit fields for CMU SYNCBUSY */
Kojto 98:8ab26030e058 811 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 812 #define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 813 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
Kojto 98:8ab26030e058 814 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 815 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 816 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 817 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 818 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
Kojto 98:8ab26030e058 819 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 820 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 821 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 822 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 823 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
Kojto 98:8ab26030e058 824 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 825 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 826 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 827 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 828 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
Kojto 98:8ab26030e058 829 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 830 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 831 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 832 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 833
Kojto 98:8ab26030e058 834 /* Bit fields for CMU FREEZE */
Kojto 98:8ab26030e058 835 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
Kojto 98:8ab26030e058 836 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
Kojto 98:8ab26030e058 837 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
Kojto 98:8ab26030e058 838 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
Kojto 98:8ab26030e058 839 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
Kojto 98:8ab26030e058 840 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
Kojto 98:8ab26030e058 841 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
Kojto 98:8ab26030e058 842 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
Kojto 98:8ab26030e058 843 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
Kojto 98:8ab26030e058 844 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
Kojto 98:8ab26030e058 845 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
Kojto 98:8ab26030e058 846
Kojto 98:8ab26030e058 847 /* Bit fields for CMU LFACLKEN0 */
Kojto 98:8ab26030e058 848 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 849 #define _CMU_LFACLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 850 #define CMU_LFACLKEN0_RTC (0x1UL << 0) /**< Real-Time Counter Clock Enable */
Kojto 98:8ab26030e058 851 #define _CMU_LFACLKEN0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */
Kojto 98:8ab26030e058 852 #define _CMU_LFACLKEN0_RTC_MASK 0x1UL /**< Bit mask for CMU_RTC */
Kojto 98:8ab26030e058 853 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 854 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 855
Kojto 98:8ab26030e058 856 /* Bit fields for CMU LFBCLKEN0 */
Kojto 98:8ab26030e058 857 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 858 #define _CMU_LFBCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 859 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */
Kojto 98:8ab26030e058 860 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
Kojto 98:8ab26030e058 861 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */
Kojto 98:8ab26030e058 862 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 863 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 864
Kojto 98:8ab26030e058 865 /* Bit fields for CMU LFAPRESC0 */
Kojto 98:8ab26030e058 866 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 867 #define _CMU_LFAPRESC0_MASK 0x0000000FUL /**< Mask for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 868 #define _CMU_LFAPRESC0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */
Kojto 98:8ab26030e058 869 #define _CMU_LFAPRESC0_RTC_MASK 0xFUL /**< Bit mask for CMU_RTC */
Kojto 98:8ab26030e058 870 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 871 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 872 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 873 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 874 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 875 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 876 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 877 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 878 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 879 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 880 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 881 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 882 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 883 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 884 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 885 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 886 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 887 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 888 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 889 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 890 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 891 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 892 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 893 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 894 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 895 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 896 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 897 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 898 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 899 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 900 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 901 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 902
Kojto 98:8ab26030e058 903 /* Bit fields for CMU LFBPRESC0 */
Kojto 98:8ab26030e058 904 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 905 #define _CMU_LFBPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 906 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
Kojto 98:8ab26030e058 907 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */
Kojto 98:8ab26030e058 908 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 909 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 910 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 911 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 912 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 913 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 914 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 915 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 916
Kojto 98:8ab26030e058 917 /* Bit fields for CMU PCNTCTRL */
Kojto 98:8ab26030e058 918 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 919 #define _CMU_PCNTCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 920 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
Kojto 98:8ab26030e058 921 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
Kojto 98:8ab26030e058 922 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
Kojto 98:8ab26030e058 923 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 924 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 925 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
Kojto 98:8ab26030e058 926 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
Kojto 98:8ab26030e058 927 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
Kojto 98:8ab26030e058 928 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 929 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 930 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 931 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 932 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 933 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 934
Kojto 98:8ab26030e058 935 /* Bit fields for CMU ROUTE */
Kojto 98:8ab26030e058 936 #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */
Kojto 98:8ab26030e058 937 #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */
Kojto 98:8ab26030e058 938 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
Kojto 98:8ab26030e058 939 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
Kojto 98:8ab26030e058 940 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
Kojto 98:8ab26030e058 941 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
Kojto 98:8ab26030e058 942 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */
Kojto 98:8ab26030e058 943 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
Kojto 98:8ab26030e058 944 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
Kojto 98:8ab26030e058 945 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
Kojto 98:8ab26030e058 946 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
Kojto 98:8ab26030e058 947 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */
Kojto 98:8ab26030e058 948 #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */
Kojto 98:8ab26030e058 949 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */
Kojto 98:8ab26030e058 950 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */
Kojto 98:8ab26030e058 951 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
Kojto 98:8ab26030e058 952 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */
Kojto 98:8ab26030e058 953 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */
Kojto 98:8ab26030e058 954 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */
Kojto 98:8ab26030e058 955 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */
Kojto 98:8ab26030e058 956 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */
Kojto 98:8ab26030e058 957 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */
Kojto 98:8ab26030e058 958
Kojto 98:8ab26030e058 959 /* Bit fields for CMU LOCK */
Kojto 98:8ab26030e058 960 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
Kojto 98:8ab26030e058 961 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
Kojto 98:8ab26030e058 962 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
Kojto 98:8ab26030e058 963 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
Kojto 98:8ab26030e058 964 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
Kojto 98:8ab26030e058 965 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
Kojto 98:8ab26030e058 966 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
Kojto 98:8ab26030e058 967 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
Kojto 98:8ab26030e058 968 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
Kojto 98:8ab26030e058 969 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
Kojto 98:8ab26030e058 970 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
Kojto 98:8ab26030e058 971 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
Kojto 98:8ab26030e058 972 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
Kojto 98:8ab26030e058 973 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
Kojto 98:8ab26030e058 974
Kojto 98:8ab26030e058 975 /** @} End of group EFM32ZG_CMU */
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