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TARGET_NUCLEO_F746ZG/stm32f746xx.h@115:87f2f5183dfb, 2016-03-02 (annotated)

Committer:: Kojto
Date:: Wed Mar 02 09:58:28 2016 +0100
Revision:: 115:87f2f5183dfb
Child:: 116:c0f6e94411f5

Release 115 of the mbed library



Changes:

- new targets - NUCLEO_F746ZG

- Bugfix - STM32F7 + STM32L4 - RTC init fix

- Bugfix - STM32L4 Set NVIC_RAM_VECTOR_ADDRESS to 0x10000000

- B96B_F446VE - CAN addition

- Changed target name from NZ32SC151 to NZ32_SC151

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	115:87f2f5183dfb	1	/**
Kojto	115:87f2f5183dfb	2	******************************************************************************
Kojto	115:87f2f5183dfb	3	* @file stm32f746xx.h
Kojto	115:87f2f5183dfb	4	* @author MCD Application Team
Kojto	115:87f2f5183dfb	5	* @version V1.0.1
Kojto	115:87f2f5183dfb	6	* @date 25-June-2015
Kojto	115:87f2f5183dfb	7	* @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File.
Kojto	115:87f2f5183dfb	8	*
Kojto	115:87f2f5183dfb	9	* This file contains:
Kojto	115:87f2f5183dfb	10	* - Data structures and the address mapping for all peripherals
Kojto	115:87f2f5183dfb	11	* - Peripheral's registers declarations and bits definition
Kojto	115:87f2f5183dfb	12	* - Macros to access peripherals registers hardware
Kojto	115:87f2f5183dfb	13	*
Kojto	115:87f2f5183dfb	14	******************************************************************************
Kojto	115:87f2f5183dfb	15	* @attention
Kojto	115:87f2f5183dfb	16	*
Kojto	115:87f2f5183dfb	17	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	115:87f2f5183dfb	18	*
Kojto	115:87f2f5183dfb	19	* Redistribution and use in source and binary forms, with or without modification,
Kojto	115:87f2f5183dfb	20	* are permitted provided that the following conditions are met:
Kojto	115:87f2f5183dfb	21	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	115:87f2f5183dfb	22	* this list of conditions and the following disclaimer.
Kojto	115:87f2f5183dfb	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	115:87f2f5183dfb	24	* this list of conditions and the following disclaimer in the documentation
Kojto	115:87f2f5183dfb	25	* and/or other materials provided with the distribution.
Kojto	115:87f2f5183dfb	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	115:87f2f5183dfb	27	* may be used to endorse or promote products derived from this software
Kojto	115:87f2f5183dfb	28	* without specific prior written permission.
Kojto	115:87f2f5183dfb	29	*
Kojto	115:87f2f5183dfb	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	115:87f2f5183dfb	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	115:87f2f5183dfb	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	115:87f2f5183dfb	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	115:87f2f5183dfb	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	115:87f2f5183dfb	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	115:87f2f5183dfb	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	115:87f2f5183dfb	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	115:87f2f5183dfb	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	115:87f2f5183dfb	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	115:87f2f5183dfb	40	*
Kojto	115:87f2f5183dfb	41	******************************************************************************
Kojto	115:87f2f5183dfb	42	*/
Kojto	115:87f2f5183dfb	43
Kojto	115:87f2f5183dfb	44	/** @addtogroup CMSIS_Device
Kojto	115:87f2f5183dfb	45	* @{
Kojto	115:87f2f5183dfb	46	*/
Kojto	115:87f2f5183dfb	47
Kojto	115:87f2f5183dfb	48	/** @addtogroup stm32f746xx
Kojto	115:87f2f5183dfb	49	* @{
Kojto	115:87f2f5183dfb	50	*/
Kojto	115:87f2f5183dfb	51
Kojto	115:87f2f5183dfb	52	#ifndef __STM32F746xx_H
Kojto	115:87f2f5183dfb	53	#define __STM32F746xx_H
Kojto	115:87f2f5183dfb	54
Kojto	115:87f2f5183dfb	55	#ifdef __cplusplus
Kojto	115:87f2f5183dfb	56	extern "C" {
Kojto	115:87f2f5183dfb	57	#endif /* __cplusplus */
Kojto	115:87f2f5183dfb	58
Kojto	115:87f2f5183dfb	59	/** @addtogroup Configuration_section_for_CMSIS
Kojto	115:87f2f5183dfb	60	* @{
Kojto	115:87f2f5183dfb	61	*/
Kojto	115:87f2f5183dfb	62
Kojto	115:87f2f5183dfb	63	/**
Kojto	115:87f2f5183dfb	64	* @brief STM32F7xx Interrupt Number Definition, according to the selected device
Kojto	115:87f2f5183dfb	65	* in @ref Library_configuration_section
Kojto	115:87f2f5183dfb	66	*/
Kojto	115:87f2f5183dfb	67	typedef enum IRQn
Kojto	115:87f2f5183dfb	68	{
Kojto	115:87f2f5183dfb	69	/**** Cortex-M7 Processor Exceptions Numbers **************************************************************/
Kojto	115:87f2f5183dfb	70	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
Kojto	115:87f2f5183dfb	71	MemoryManagement_IRQn = -12, /!< 4 Cortex-M7 Memory Management Interrupt /
Kojto	115:87f2f5183dfb	72	BusFault_IRQn = -11, /!< 5 Cortex-M7 Bus Fault Interrupt /
Kojto	115:87f2f5183dfb	73	UsageFault_IRQn = -10, /!< 6 Cortex-M7 Usage Fault Interrupt /
Kojto	115:87f2f5183dfb	74	SVCall_IRQn = -5, /!< 11 Cortex-M7 SV Call Interrupt /
Kojto	115:87f2f5183dfb	75	DebugMonitor_IRQn = -4, /!< 12 Cortex-M7 Debug Monitor Interrupt /
Kojto	115:87f2f5183dfb	76	PendSV_IRQn = -2, /!< 14 Cortex-M7 Pend SV Interrupt /
Kojto	115:87f2f5183dfb	77	SysTick_IRQn = -1, /!< 15 Cortex-M7 System Tick Interrupt /
Kojto	115:87f2f5183dfb	78	/**** STM32 specific Interrupt Numbers ********************************************************************/
Kojto	115:87f2f5183dfb	79	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
Kojto	115:87f2f5183dfb	80	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
Kojto	115:87f2f5183dfb	81	TAMP_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts through the EXTI line /
Kojto	115:87f2f5183dfb	82	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI line /
Kojto	115:87f2f5183dfb	83	FLASH_IRQn = 4, /!< FLASH global Interrupt /
Kojto	115:87f2f5183dfb	84	RCC_IRQn = 5, /!< RCC global Interrupt /
Kojto	115:87f2f5183dfb	85	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
Kojto	115:87f2f5183dfb	86	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
Kojto	115:87f2f5183dfb	87	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
Kojto	115:87f2f5183dfb	88	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
Kojto	115:87f2f5183dfb	89	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
Kojto	115:87f2f5183dfb	90	DMA1_Stream0_IRQn = 11, /!< DMA1 Stream 0 global Interrupt /
Kojto	115:87f2f5183dfb	91	DMA1_Stream1_IRQn = 12, /!< DMA1 Stream 1 global Interrupt /
Kojto	115:87f2f5183dfb	92	DMA1_Stream2_IRQn = 13, /!< DMA1 Stream 2 global Interrupt /
Kojto	115:87f2f5183dfb	93	DMA1_Stream3_IRQn = 14, /!< DMA1 Stream 3 global Interrupt /
Kojto	115:87f2f5183dfb	94	DMA1_Stream4_IRQn = 15, /!< DMA1 Stream 4 global Interrupt /
Kojto	115:87f2f5183dfb	95	DMA1_Stream5_IRQn = 16, /!< DMA1 Stream 5 global Interrupt /
Kojto	115:87f2f5183dfb	96	DMA1_Stream6_IRQn = 17, /!< DMA1 Stream 6 global Interrupt /
Kojto	115:87f2f5183dfb	97	ADC_IRQn = 18, /!< ADC1, ADC2 and ADC3 global Interrupts /
Kojto	115:87f2f5183dfb	98	CAN1_TX_IRQn = 19, /!< CAN1 TX Interrupt /
Kojto	115:87f2f5183dfb	99	CAN1_RX0_IRQn = 20, /!< CAN1 RX0 Interrupt /
Kojto	115:87f2f5183dfb	100	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
Kojto	115:87f2f5183dfb	101	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
Kojto	115:87f2f5183dfb	102	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
Kojto	115:87f2f5183dfb	103	TIM1_BRK_TIM9_IRQn = 24, /!< TIM1 Break interrupt and TIM9 global interrupt /
Kojto	115:87f2f5183dfb	104	TIM1_UP_TIM10_IRQn = 25, /!< TIM1 Update Interrupt and TIM10 global interrupt /
Kojto	115:87f2f5183dfb	105	TIM1_TRG_COM_TIM11_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt /
Kojto	115:87f2f5183dfb	106	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
Kojto	115:87f2f5183dfb	107	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
Kojto	115:87f2f5183dfb	108	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
Kojto	115:87f2f5183dfb	109	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
Kojto	115:87f2f5183dfb	110	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
Kojto	115:87f2f5183dfb	111	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
Kojto	115:87f2f5183dfb	112	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
Kojto	115:87f2f5183dfb	113	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
Kojto	115:87f2f5183dfb	114	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
Kojto	115:87f2f5183dfb	115	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
Kojto	115:87f2f5183dfb	116	USART1_IRQn = 37, /!< USART1 global Interrupt /
Kojto	115:87f2f5183dfb	117	USART2_IRQn = 38, /!< USART2 global Interrupt /
Kojto	115:87f2f5183dfb	118	USART3_IRQn = 39, /!< USART3 global Interrupt /
Kojto	115:87f2f5183dfb	119	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
Kojto	115:87f2f5183dfb	120	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
Kojto	115:87f2f5183dfb	121	OTG_FS_WKUP_IRQn = 42, /!< USB OTG FS Wakeup through EXTI line interrupt /
Kojto	115:87f2f5183dfb	122	TIM8_BRK_TIM12_IRQn = 43, /!< TIM8 Break Interrupt and TIM12 global interrupt /
Kojto	115:87f2f5183dfb	123	TIM8_UP_TIM13_IRQn = 44, /!< TIM8 Update Interrupt and TIM13 global interrupt /
Kojto	115:87f2f5183dfb	124	TIM8_TRG_COM_TIM14_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt /
Kojto	115:87f2f5183dfb	125	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare Interrupt /
Kojto	115:87f2f5183dfb	126	DMA1_Stream7_IRQn = 47, /!< DMA1 Stream7 Interrupt /
Kojto	115:87f2f5183dfb	127	FMC_IRQn = 48, /!< FMC global Interrupt /
Kojto	115:87f2f5183dfb	128	SDMMC1_IRQn = 49, /!< SDMMC1 global Interrupt /
Kojto	115:87f2f5183dfb	129	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
Kojto	115:87f2f5183dfb	130	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
Kojto	115:87f2f5183dfb	131	UART4_IRQn = 52, /!< UART4 global Interrupt /
Kojto	115:87f2f5183dfb	132	UART5_IRQn = 53, /!< UART5 global Interrupt /
Kojto	115:87f2f5183dfb	133	TIM6_DAC_IRQn = 54, /!< TIM6 global and DAC1&2 underrun error interrupts /
Kojto	115:87f2f5183dfb	134	TIM7_IRQn = 55, /!< TIM7 global interrupt /
Kojto	115:87f2f5183dfb	135	DMA2_Stream0_IRQn = 56, /!< DMA2 Stream 0 global Interrupt /
Kojto	115:87f2f5183dfb	136	DMA2_Stream1_IRQn = 57, /!< DMA2 Stream 1 global Interrupt /
Kojto	115:87f2f5183dfb	137	DMA2_Stream2_IRQn = 58, /!< DMA2 Stream 2 global Interrupt /
Kojto	115:87f2f5183dfb	138	DMA2_Stream3_IRQn = 59, /!< DMA2 Stream 3 global Interrupt /
Kojto	115:87f2f5183dfb	139	DMA2_Stream4_IRQn = 60, /!< DMA2 Stream 4 global Interrupt /
Kojto	115:87f2f5183dfb	140	ETH_IRQn = 61, /!< Ethernet global Interrupt /
Kojto	115:87f2f5183dfb	141	ETH_WKUP_IRQn = 62, /!< Ethernet Wakeup through EXTI line Interrupt /
Kojto	115:87f2f5183dfb	142	CAN2_TX_IRQn = 63, /!< CAN2 TX Interrupt /
Kojto	115:87f2f5183dfb	143	CAN2_RX0_IRQn = 64, /!< CAN2 RX0 Interrupt /
Kojto	115:87f2f5183dfb	144	CAN2_RX1_IRQn = 65, /!< CAN2 RX1 Interrupt /
Kojto	115:87f2f5183dfb	145	CAN2_SCE_IRQn = 66, /!< CAN2 SCE Interrupt /
Kojto	115:87f2f5183dfb	146	OTG_FS_IRQn = 67, /!< USB OTG FS global Interrupt /
Kojto	115:87f2f5183dfb	147	DMA2_Stream5_IRQn = 68, /!< DMA2 Stream 5 global interrupt /
Kojto	115:87f2f5183dfb	148	DMA2_Stream6_IRQn = 69, /!< DMA2 Stream 6 global interrupt /
Kojto	115:87f2f5183dfb	149	DMA2_Stream7_IRQn = 70, /!< DMA2 Stream 7 global interrupt /
Kojto	115:87f2f5183dfb	150	USART6_IRQn = 71, /!< USART6 global interrupt /
Kojto	115:87f2f5183dfb	151	I2C3_EV_IRQn = 72, /!< I2C3 event interrupt /
Kojto	115:87f2f5183dfb	152	I2C3_ER_IRQn = 73, /!< I2C3 error interrupt /
Kojto	115:87f2f5183dfb	153	OTG_HS_EP1_OUT_IRQn = 74, /!< USB OTG HS End Point 1 Out global interrupt /
Kojto	115:87f2f5183dfb	154	OTG_HS_EP1_IN_IRQn = 75, /!< USB OTG HS End Point 1 In global interrupt /
Kojto	115:87f2f5183dfb	155	OTG_HS_WKUP_IRQn = 76, /!< USB OTG HS Wakeup through EXTI interrupt /
Kojto	115:87f2f5183dfb	156	OTG_HS_IRQn = 77, /!< USB OTG HS global interrupt /
Kojto	115:87f2f5183dfb	157	DCMI_IRQn = 78, /!< DCMI global interrupt /
Kojto	115:87f2f5183dfb	158	RNG_IRQn = 80, /!< RNG global interrupt /
Kojto	115:87f2f5183dfb	159	FPU_IRQn = 81, /!< FPU global interrupt /
Kojto	115:87f2f5183dfb	160	UART7_IRQn = 82, /!< UART7 global interrupt /
Kojto	115:87f2f5183dfb	161	UART8_IRQn = 83, /!< UART8 global interrupt /
Kojto	115:87f2f5183dfb	162	SPI4_IRQn = 84, /!< SPI4 global Interrupt /
Kojto	115:87f2f5183dfb	163	SPI5_IRQn = 85, /!< SPI5 global Interrupt /
Kojto	115:87f2f5183dfb	164	SPI6_IRQn = 86, /!< SPI6 global Interrupt /
Kojto	115:87f2f5183dfb	165	SAI1_IRQn = 87, /!< SAI1 global Interrupt /
Kojto	115:87f2f5183dfb	166	LTDC_IRQn = 88, /!< LTDC global Interrupt /
Kojto	115:87f2f5183dfb	167	LTDC_ER_IRQn = 89, /!< LTDC Error global Interrupt /
Kojto	115:87f2f5183dfb	168	DMA2D_IRQn = 90, /!< DMA2D global Interrupt /
Kojto	115:87f2f5183dfb	169	SAI2_IRQn = 91, /!< SAI2 global Interrupt /
Kojto	115:87f2f5183dfb	170	QUADSPI_IRQn = 92, /!< Quad SPI global interrupt /
Kojto	115:87f2f5183dfb	171	LPTIM1_IRQn = 93, /!< LP TIM1 interrupt /
Kojto	115:87f2f5183dfb	172	CEC_IRQn = 94, /!< HDMI-CEC global Interrupt /
Kojto	115:87f2f5183dfb	173	I2C4_EV_IRQn = 95, /!< I2C4 Event Interrupt /
Kojto	115:87f2f5183dfb	174	I2C4_ER_IRQn = 96, /!< I2C4 Error Interrupt /
Kojto	115:87f2f5183dfb	175	SPDIF_RX_IRQn = 97 /!< SPDIF-RX global Interrupt /
Kojto	115:87f2f5183dfb	176	} IRQn_Type;
Kojto	115:87f2f5183dfb	177
Kojto	115:87f2f5183dfb	178	/**
Kojto	115:87f2f5183dfb	179	* @}
Kojto	115:87f2f5183dfb	180	*/
Kojto	115:87f2f5183dfb	181
Kojto	115:87f2f5183dfb	182	/**
Kojto	115:87f2f5183dfb	183	* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
Kojto	115:87f2f5183dfb	184	*/
Kojto	115:87f2f5183dfb	185	#define __CM7_REV 0x0000 /!< Cortex-M7 revision r0p1 /
Kojto	115:87f2f5183dfb	186	#define __MPU_PRESENT 1 /!< CM7 provides an MPU /
Kojto	115:87f2f5183dfb	187	#define __NVIC_PRIO_BITS 4 /!< CM7 uses 4 Bits for the Priority Levels /
Kojto	115:87f2f5183dfb	188	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
Kojto	115:87f2f5183dfb	189	#define __FPU_PRESENT 1 /!< FPU present /
Kojto	115:87f2f5183dfb	190	#define __ICACHE_PRESENT 1 /!< CM7 instruction cache present /
Kojto	115:87f2f5183dfb	191	#define __DCACHE_PRESENT 1 /!< CM7 data cache present /
Kojto	115:87f2f5183dfb	192	#include "core_cm7.h" /!< Cortex-M7 processor and core peripherals /
Kojto	115:87f2f5183dfb	193
Kojto	115:87f2f5183dfb	194
Kojto	115:87f2f5183dfb	195	#include "system_stm32f7xx.h"
Kojto	115:87f2f5183dfb	196	#include <stdint.h>
Kojto	115:87f2f5183dfb	197
Kojto	115:87f2f5183dfb	198	/** @addtogroup Peripheral_registers_structures
Kojto	115:87f2f5183dfb	199	* @{
Kojto	115:87f2f5183dfb	200	*/
Kojto	115:87f2f5183dfb	201
Kojto	115:87f2f5183dfb	202	/**
Kojto	115:87f2f5183dfb	203	* @brief Analog to Digital Converter
Kojto	115:87f2f5183dfb	204	*/
Kojto	115:87f2f5183dfb	205
Kojto	115:87f2f5183dfb	206	typedef struct
Kojto	115:87f2f5183dfb	207	{
Kojto	115:87f2f5183dfb	208	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	209	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	210	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	211	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	212	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	213	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	214	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	215	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	216	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	217	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
Kojto	115:87f2f5183dfb	218	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
Kojto	115:87f2f5183dfb	219	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
Kojto	115:87f2f5183dfb	220	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
Kojto	115:87f2f5183dfb	221	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
Kojto	115:87f2f5183dfb	222	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
Kojto	115:87f2f5183dfb	223	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
Kojto	115:87f2f5183dfb	224	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
Kojto	115:87f2f5183dfb	225	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
Kojto	115:87f2f5183dfb	226	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
Kojto	115:87f2f5183dfb	227	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
Kojto	115:87f2f5183dfb	228	} ADC_TypeDef;
Kojto	115:87f2f5183dfb	229
Kojto	115:87f2f5183dfb	230	typedef struct
Kojto	115:87f2f5183dfb	231	{
Kojto	115:87f2f5183dfb	232	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
Kojto	115:87f2f5183dfb	233	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
Kojto	115:87f2f5183dfb	234	__IO uint32_t CDR; /*!< ADC common regular data register for dual
Kojto	115:87f2f5183dfb	235	AND triple modes, Address offset: ADC1 base address + 0x308 */
Kojto	115:87f2f5183dfb	236	} ADC_Common_TypeDef;
Kojto	115:87f2f5183dfb	237
Kojto	115:87f2f5183dfb	238
Kojto	115:87f2f5183dfb	239	/**
Kojto	115:87f2f5183dfb	240	* @brief Controller Area Network TxMailBox
Kojto	115:87f2f5183dfb	241	*/
Kojto	115:87f2f5183dfb	242
Kojto	115:87f2f5183dfb	243	typedef struct
Kojto	115:87f2f5183dfb	244	{
Kojto	115:87f2f5183dfb	245	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
Kojto	115:87f2f5183dfb	246	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
Kojto	115:87f2f5183dfb	247	__IO uint32_t TDLR; /!< CAN mailbox data low register /
Kojto	115:87f2f5183dfb	248	__IO uint32_t TDHR; /!< CAN mailbox data high register /
Kojto	115:87f2f5183dfb	249	} CAN_TxMailBox_TypeDef;
Kojto	115:87f2f5183dfb	250
Kojto	115:87f2f5183dfb	251	/**
Kojto	115:87f2f5183dfb	252	* @brief Controller Area Network FIFOMailBox
Kojto	115:87f2f5183dfb	253	*/
Kojto	115:87f2f5183dfb	254
Kojto	115:87f2f5183dfb	255	typedef struct
Kojto	115:87f2f5183dfb	256	{
Kojto	115:87f2f5183dfb	257	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
Kojto	115:87f2f5183dfb	258	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
Kojto	115:87f2f5183dfb	259	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
Kojto	115:87f2f5183dfb	260	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
Kojto	115:87f2f5183dfb	261	} CAN_FIFOMailBox_TypeDef;
Kojto	115:87f2f5183dfb	262
Kojto	115:87f2f5183dfb	263	/**
Kojto	115:87f2f5183dfb	264	* @brief Controller Area Network FilterRegister
Kojto	115:87f2f5183dfb	265	*/
Kojto	115:87f2f5183dfb	266
Kojto	115:87f2f5183dfb	267	typedef struct
Kojto	115:87f2f5183dfb	268	{
Kojto	115:87f2f5183dfb	269	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
Kojto	115:87f2f5183dfb	270	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
Kojto	115:87f2f5183dfb	271	} CAN_FilterRegister_TypeDef;
Kojto	115:87f2f5183dfb	272
Kojto	115:87f2f5183dfb	273	/**
Kojto	115:87f2f5183dfb	274	* @brief Controller Area Network
Kojto	115:87f2f5183dfb	275	*/
Kojto	115:87f2f5183dfb	276
Kojto	115:87f2f5183dfb	277	typedef struct
Kojto	115:87f2f5183dfb	278	{
Kojto	115:87f2f5183dfb	279	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	280	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	281	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	282	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	283	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	284	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	285	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	286	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	287	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
Kojto	115:87f2f5183dfb	288	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
Kojto	115:87f2f5183dfb	289	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
Kojto	115:87f2f5183dfb	290	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
Kojto	115:87f2f5183dfb	291	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
Kojto	115:87f2f5183dfb	292	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
Kojto	115:87f2f5183dfb	293	uint32_t RESERVED2; /!< Reserved, 0x208 /
Kojto	115:87f2f5183dfb	294	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
Kojto	115:87f2f5183dfb	295	uint32_t RESERVED3; /!< Reserved, 0x210 /
Kojto	115:87f2f5183dfb	296	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
Kojto	115:87f2f5183dfb	297	uint32_t RESERVED4; /!< Reserved, 0x218 /
Kojto	115:87f2f5183dfb	298	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
Kojto	115:87f2f5183dfb	299	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
Kojto	115:87f2f5183dfb	300	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
Kojto	115:87f2f5183dfb	301	} CAN_TypeDef;
Kojto	115:87f2f5183dfb	302
Kojto	115:87f2f5183dfb	303	/**
Kojto	115:87f2f5183dfb	304	* @brief HDMI-CEC
Kojto	115:87f2f5183dfb	305	*/
Kojto	115:87f2f5183dfb	306
Kojto	115:87f2f5183dfb	307	typedef struct
Kojto	115:87f2f5183dfb	308	{
Kojto	115:87f2f5183dfb	309	__IO uint32_t CR; /!< CEC control register, Address offset:0x00 /
Kojto	115:87f2f5183dfb	310	__IO uint32_t CFGR; /!< CEC configuration register, Address offset:0x04 /
Kojto	115:87f2f5183dfb	311	__IO uint32_t TXDR; /!< CEC Tx data register , Address offset:0x08 /
Kojto	115:87f2f5183dfb	312	__IO uint32_t RXDR; /!< CEC Rx Data Register, Address offset:0x0C /
Kojto	115:87f2f5183dfb	313	__IO uint32_t ISR; /!< CEC Interrupt and Status Register, Address offset:0x10 /
Kojto	115:87f2f5183dfb	314	__IO uint32_t IER; /!< CEC interrupt enable register, Address offset:0x14 /
Kojto	115:87f2f5183dfb	315	}CEC_TypeDef;
Kojto	115:87f2f5183dfb	316
Kojto	115:87f2f5183dfb	317
Kojto	115:87f2f5183dfb	318	/**
Kojto	115:87f2f5183dfb	319	* @brief CRC calculation unit
Kojto	115:87f2f5183dfb	320	*/
Kojto	115:87f2f5183dfb	321
Kojto	115:87f2f5183dfb	322	typedef struct
Kojto	115:87f2f5183dfb	323	{
Kojto	115:87f2f5183dfb	324	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	325	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	326	uint8_t RESERVED0; /!< Reserved, 0x05 /
Kojto	115:87f2f5183dfb	327	uint16_t RESERVED1; /!< Reserved, 0x06 /
Kojto	115:87f2f5183dfb	328	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	329	uint32_t RESERVED2; /!< Reserved, 0x0C /
Kojto	115:87f2f5183dfb	330	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	331	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	332	} CRC_TypeDef;
Kojto	115:87f2f5183dfb	333
Kojto	115:87f2f5183dfb	334	/**
Kojto	115:87f2f5183dfb	335	* @brief Digital to Analog Converter
Kojto	115:87f2f5183dfb	336	*/
Kojto	115:87f2f5183dfb	337
Kojto	115:87f2f5183dfb	338	typedef struct
Kojto	115:87f2f5183dfb	339	{
Kojto	115:87f2f5183dfb	340	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	341	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	342	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	343	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	344	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	345	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	346	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	347	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	348	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	349	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
Kojto	115:87f2f5183dfb	350	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
Kojto	115:87f2f5183dfb	351	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
Kojto	115:87f2f5183dfb	352	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
Kojto	115:87f2f5183dfb	353	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
Kojto	115:87f2f5183dfb	354	} DAC_TypeDef;
Kojto	115:87f2f5183dfb	355
Kojto	115:87f2f5183dfb	356	/**
Kojto	115:87f2f5183dfb	357	* @brief Debug MCU
Kojto	115:87f2f5183dfb	358	*/
Kojto	115:87f2f5183dfb	359
Kojto	115:87f2f5183dfb	360	typedef struct
Kojto	115:87f2f5183dfb	361	{
Kojto	115:87f2f5183dfb	362	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	363	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	364	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	365	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	366	}DBGMCU_TypeDef;
Kojto	115:87f2f5183dfb	367
Kojto	115:87f2f5183dfb	368	/**
Kojto	115:87f2f5183dfb	369	* @brief DCMI
Kojto	115:87f2f5183dfb	370	*/
Kojto	115:87f2f5183dfb	371
Kojto	115:87f2f5183dfb	372	typedef struct
Kojto	115:87f2f5183dfb	373	{
Kojto	115:87f2f5183dfb	374	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	375	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	376	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	377	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	378	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	379	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	380	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	381	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	382	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	383	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
Kojto	115:87f2f5183dfb	384	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
Kojto	115:87f2f5183dfb	385	} DCMI_TypeDef;
Kojto	115:87f2f5183dfb	386
Kojto	115:87f2f5183dfb	387	/**
Kojto	115:87f2f5183dfb	388	* @brief DMA Controller
Kojto	115:87f2f5183dfb	389	*/
Kojto	115:87f2f5183dfb	390
Kojto	115:87f2f5183dfb	391	typedef struct
Kojto	115:87f2f5183dfb	392	{
Kojto	115:87f2f5183dfb	393	__IO uint32_t CR; /!< DMA stream x configuration register /
Kojto	115:87f2f5183dfb	394	__IO uint32_t NDTR; /!< DMA stream x number of data register /
Kojto	115:87f2f5183dfb	395	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
Kojto	115:87f2f5183dfb	396	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
Kojto	115:87f2f5183dfb	397	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
Kojto	115:87f2f5183dfb	398	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
Kojto	115:87f2f5183dfb	399	} DMA_Stream_TypeDef;
Kojto	115:87f2f5183dfb	400
Kojto	115:87f2f5183dfb	401	typedef struct
Kojto	115:87f2f5183dfb	402	{
Kojto	115:87f2f5183dfb	403	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	404	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	405	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	406	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	407	} DMA_TypeDef;
Kojto	115:87f2f5183dfb	408
Kojto	115:87f2f5183dfb	409
Kojto	115:87f2f5183dfb	410	/**
Kojto	115:87f2f5183dfb	411	* @brief DMA2D Controller
Kojto	115:87f2f5183dfb	412	*/
Kojto	115:87f2f5183dfb	413
Kojto	115:87f2f5183dfb	414	typedef struct
Kojto	115:87f2f5183dfb	415	{
Kojto	115:87f2f5183dfb	416	__IO uint32_t CR; /!< DMA2D Control Register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	417	__IO uint32_t ISR; /!< DMA2D Interrupt Status Register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	418	__IO uint32_t IFCR; /!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	419	__IO uint32_t FGMAR; /!< DMA2D Foreground Memory Address Register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	420	__IO uint32_t FGOR; /!< DMA2D Foreground Offset Register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	421	__IO uint32_t BGMAR; /!< DMA2D Background Memory Address Register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	422	__IO uint32_t BGOR; /!< DMA2D Background Offset Register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	423	__IO uint32_t FGPFCCR; /!< DMA2D Foreground PFC Control Register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	424	__IO uint32_t FGCOLR; /!< DMA2D Foreground Color Register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	425	__IO uint32_t BGPFCCR; /!< DMA2D Background PFC Control Register, Address offset: 0x24 /
Kojto	115:87f2f5183dfb	426	__IO uint32_t BGCOLR; /!< DMA2D Background Color Register, Address offset: 0x28 /
Kojto	115:87f2f5183dfb	427	__IO uint32_t FGCMAR; /!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C /
Kojto	115:87f2f5183dfb	428	__IO uint32_t BGCMAR; /!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 /
Kojto	115:87f2f5183dfb	429	__IO uint32_t OPFCCR; /!< DMA2D Output PFC Control Register, Address offset: 0x34 /
Kojto	115:87f2f5183dfb	430	__IO uint32_t OCOLR; /!< DMA2D Output Color Register, Address offset: 0x38 /
Kojto	115:87f2f5183dfb	431	__IO uint32_t OMAR; /!< DMA2D Output Memory Address Register, Address offset: 0x3C /
Kojto	115:87f2f5183dfb	432	__IO uint32_t OOR; /!< DMA2D Output Offset Register, Address offset: 0x40 /
Kojto	115:87f2f5183dfb	433	__IO uint32_t NLR; /!< DMA2D Number of Line Register, Address offset: 0x44 /
Kojto	115:87f2f5183dfb	434	__IO uint32_t LWR; /!< DMA2D Line Watermark Register, Address offset: 0x48 /
Kojto	115:87f2f5183dfb	435	__IO uint32_t AMTCR; /!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C /
Kojto	115:87f2f5183dfb	436	uint32_t RESERVED[236]; /!< Reserved, 0x50-0x3FF /
Kojto	115:87f2f5183dfb	437	__IO uint32_t FGCLUT[256]; /!< DMA2D Foreground CLUT, Address offset:400-7FF /
Kojto	115:87f2f5183dfb	438	__IO uint32_t BGCLUT[256]; /!< DMA2D Background CLUT, Address offset:800-BFF /
Kojto	115:87f2f5183dfb	439	} DMA2D_TypeDef;
Kojto	115:87f2f5183dfb	440
Kojto	115:87f2f5183dfb	441
Kojto	115:87f2f5183dfb	442	/**
Kojto	115:87f2f5183dfb	443	* @brief Ethernet MAC
Kojto	115:87f2f5183dfb	444	*/
Kojto	115:87f2f5183dfb	445
Kojto	115:87f2f5183dfb	446	typedef struct
Kojto	115:87f2f5183dfb	447	{
Kojto	115:87f2f5183dfb	448	__IO uint32_t MACCR;
Kojto	115:87f2f5183dfb	449	__IO uint32_t MACFFR;
Kojto	115:87f2f5183dfb	450	__IO uint32_t MACHTHR;
Kojto	115:87f2f5183dfb	451	__IO uint32_t MACHTLR;
Kojto	115:87f2f5183dfb	452	__IO uint32_t MACMIIAR;
Kojto	115:87f2f5183dfb	453	__IO uint32_t MACMIIDR;
Kojto	115:87f2f5183dfb	454	__IO uint32_t MACFCR;
Kojto	115:87f2f5183dfb	455	__IO uint32_t MACVLANTR; /* 8 */
Kojto	115:87f2f5183dfb	456	uint32_t RESERVED0[2];
Kojto	115:87f2f5183dfb	457	__IO uint32_t MACRWUFFR; /* 11 */
Kojto	115:87f2f5183dfb	458	__IO uint32_t MACPMTCSR;
Kojto	115:87f2f5183dfb	459	uint32_t RESERVED1[2];
Kojto	115:87f2f5183dfb	460	__IO uint32_t MACSR; /* 15 */
Kojto	115:87f2f5183dfb	461	__IO uint32_t MACIMR;
Kojto	115:87f2f5183dfb	462	__IO uint32_t MACA0HR;
Kojto	115:87f2f5183dfb	463	__IO uint32_t MACA0LR;
Kojto	115:87f2f5183dfb	464	__IO uint32_t MACA1HR;
Kojto	115:87f2f5183dfb	465	__IO uint32_t MACA1LR;
Kojto	115:87f2f5183dfb	466	__IO uint32_t MACA2HR;
Kojto	115:87f2f5183dfb	467	__IO uint32_t MACA2LR;
Kojto	115:87f2f5183dfb	468	__IO uint32_t MACA3HR;
Kojto	115:87f2f5183dfb	469	__IO uint32_t MACA3LR; /* 24 */
Kojto	115:87f2f5183dfb	470	uint32_t RESERVED2[40];
Kojto	115:87f2f5183dfb	471	__IO uint32_t MMCCR; /* 65 */
Kojto	115:87f2f5183dfb	472	__IO uint32_t MMCRIR;
Kojto	115:87f2f5183dfb	473	__IO uint32_t MMCTIR;
Kojto	115:87f2f5183dfb	474	__IO uint32_t MMCRIMR;
Kojto	115:87f2f5183dfb	475	__IO uint32_t MMCTIMR; /* 69 */
Kojto	115:87f2f5183dfb	476	uint32_t RESERVED3[14];
Kojto	115:87f2f5183dfb	477	__IO uint32_t MMCTGFSCCR; /* 84 */
Kojto	115:87f2f5183dfb	478	__IO uint32_t MMCTGFMSCCR;
Kojto	115:87f2f5183dfb	479	uint32_t RESERVED4[5];
Kojto	115:87f2f5183dfb	480	__IO uint32_t MMCTGFCR;
Kojto	115:87f2f5183dfb	481	uint32_t RESERVED5[10];
Kojto	115:87f2f5183dfb	482	__IO uint32_t MMCRFCECR;
Kojto	115:87f2f5183dfb	483	__IO uint32_t MMCRFAECR;
Kojto	115:87f2f5183dfb	484	uint32_t RESERVED6[10];
Kojto	115:87f2f5183dfb	485	__IO uint32_t MMCRGUFCR;
Kojto	115:87f2f5183dfb	486	uint32_t RESERVED7[334];
Kojto	115:87f2f5183dfb	487	__IO uint32_t PTPTSCR;
Kojto	115:87f2f5183dfb	488	__IO uint32_t PTPSSIR;
Kojto	115:87f2f5183dfb	489	__IO uint32_t PTPTSHR;
Kojto	115:87f2f5183dfb	490	__IO uint32_t PTPTSLR;
Kojto	115:87f2f5183dfb	491	__IO uint32_t PTPTSHUR;
Kojto	115:87f2f5183dfb	492	__IO uint32_t PTPTSLUR;
Kojto	115:87f2f5183dfb	493	__IO uint32_t PTPTSAR;
Kojto	115:87f2f5183dfb	494	__IO uint32_t PTPTTHR;
Kojto	115:87f2f5183dfb	495	__IO uint32_t PTPTTLR;
Kojto	115:87f2f5183dfb	496	__IO uint32_t RESERVED8;
Kojto	115:87f2f5183dfb	497	__IO uint32_t PTPTSSR;
Kojto	115:87f2f5183dfb	498	uint32_t RESERVED9[565];
Kojto	115:87f2f5183dfb	499	__IO uint32_t DMABMR;
Kojto	115:87f2f5183dfb	500	__IO uint32_t DMATPDR;
Kojto	115:87f2f5183dfb	501	__IO uint32_t DMARPDR;
Kojto	115:87f2f5183dfb	502	__IO uint32_t DMARDLAR;
Kojto	115:87f2f5183dfb	503	__IO uint32_t DMATDLAR;
Kojto	115:87f2f5183dfb	504	__IO uint32_t DMASR;
Kojto	115:87f2f5183dfb	505	__IO uint32_t DMAOMR;
Kojto	115:87f2f5183dfb	506	__IO uint32_t DMAIER;
Kojto	115:87f2f5183dfb	507	__IO uint32_t DMAMFBOCR;
Kojto	115:87f2f5183dfb	508	__IO uint32_t DMARSWTR;
Kojto	115:87f2f5183dfb	509	uint32_t RESERVED10[8];
Kojto	115:87f2f5183dfb	510	__IO uint32_t DMACHTDR;
Kojto	115:87f2f5183dfb	511	__IO uint32_t DMACHRDR;
Kojto	115:87f2f5183dfb	512	__IO uint32_t DMACHTBAR;
Kojto	115:87f2f5183dfb	513	__IO uint32_t DMACHRBAR;
Kojto	115:87f2f5183dfb	514	} ETH_TypeDef;
Kojto	115:87f2f5183dfb	515
Kojto	115:87f2f5183dfb	516	/**
Kojto	115:87f2f5183dfb	517	* @brief External Interrupt/Event Controller
Kojto	115:87f2f5183dfb	518	*/
Kojto	115:87f2f5183dfb	519
Kojto	115:87f2f5183dfb	520	typedef struct
Kojto	115:87f2f5183dfb	521	{
Kojto	115:87f2f5183dfb	522	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	523	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	524	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	525	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	526	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	527	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	528	} EXTI_TypeDef;
Kojto	115:87f2f5183dfb	529
Kojto	115:87f2f5183dfb	530	/**
Kojto	115:87f2f5183dfb	531	* @brief FLASH Registers
Kojto	115:87f2f5183dfb	532	*/
Kojto	115:87f2f5183dfb	533
Kojto	115:87f2f5183dfb	534	typedef struct
Kojto	115:87f2f5183dfb	535	{
Kojto	115:87f2f5183dfb	536	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	537	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	538	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	539	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	540	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	541	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
Kojto	115:87f2f5183dfb	542	__IO uint32_t OPTCR1; /!< FLASH option control register 1 , Address offset: 0x18 /
Kojto	115:87f2f5183dfb	543	} FLASH_TypeDef;
Kojto	115:87f2f5183dfb	544
Kojto	115:87f2f5183dfb	545
Kojto	115:87f2f5183dfb	546
Kojto	115:87f2f5183dfb	547	/**
Kojto	115:87f2f5183dfb	548	* @brief Flexible Memory Controller
Kojto	115:87f2f5183dfb	549	*/
Kojto	115:87f2f5183dfb	550
Kojto	115:87f2f5183dfb	551	typedef struct
Kojto	115:87f2f5183dfb	552	{
Kojto	115:87f2f5183dfb	553	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
Kojto	115:87f2f5183dfb	554	} FMC_Bank1_TypeDef;
Kojto	115:87f2f5183dfb	555
Kojto	115:87f2f5183dfb	556	/**
Kojto	115:87f2f5183dfb	557	* @brief Flexible Memory Controller Bank1E
Kojto	115:87f2f5183dfb	558	*/
Kojto	115:87f2f5183dfb	559
Kojto	115:87f2f5183dfb	560	typedef struct
Kojto	115:87f2f5183dfb	561	{
Kojto	115:87f2f5183dfb	562	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
Kojto	115:87f2f5183dfb	563	} FMC_Bank1E_TypeDef;
Kojto	115:87f2f5183dfb	564
Kojto	115:87f2f5183dfb	565	/**
Kojto	115:87f2f5183dfb	566	* @brief Flexible Memory Controller Bank3
Kojto	115:87f2f5183dfb	567	*/
Kojto	115:87f2f5183dfb	568
Kojto	115:87f2f5183dfb	569	typedef struct
Kojto	115:87f2f5183dfb	570	{
Kojto	115:87f2f5183dfb	571	__IO uint32_t PCR; /!< NAND Flash control register, Address offset: 0x80 /
Kojto	115:87f2f5183dfb	572	__IO uint32_t SR; /!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 /
Kojto	115:87f2f5183dfb	573	__IO uint32_t PMEM; /!< NAND Flash Common memory space timing register, Address offset: 0x88 /
Kojto	115:87f2f5183dfb	574	__IO uint32_t PATT; /!< NAND Flash Attribute memory space timing register, Address offset: 0x8C /
Kojto	115:87f2f5183dfb	575	uint32_t RESERVED0; /!< Reserved, 0x90 /
Kojto	115:87f2f5183dfb	576	__IO uint32_t ECCR; /!< NAND Flash ECC result registers, Address offset: 0x94 /
Kojto	115:87f2f5183dfb	577	} FMC_Bank3_TypeDef;
Kojto	115:87f2f5183dfb	578
Kojto	115:87f2f5183dfb	579	/**
Kojto	115:87f2f5183dfb	580	* @brief Flexible Memory Controller Bank5_6
Kojto	115:87f2f5183dfb	581	*/
Kojto	115:87f2f5183dfb	582
Kojto	115:87f2f5183dfb	583	typedef struct
Kojto	115:87f2f5183dfb	584	{
Kojto	115:87f2f5183dfb	585	__IO uint32_t SDCR[2]; /!< SDRAM Control registers , Address offset: 0x140-0x144 /
Kojto	115:87f2f5183dfb	586	__IO uint32_t SDTR[2]; /!< SDRAM Timing registers , Address offset: 0x148-0x14C /
Kojto	115:87f2f5183dfb	587	__IO uint32_t SDCMR; /!< SDRAM Command Mode register, Address offset: 0x150 /
Kojto	115:87f2f5183dfb	588	__IO uint32_t SDRTR; /!< SDRAM Refresh Timer register, Address offset: 0x154 /
Kojto	115:87f2f5183dfb	589	__IO uint32_t SDSR; /!< SDRAM Status register, Address offset: 0x158 /
Kojto	115:87f2f5183dfb	590	} FMC_Bank5_6_TypeDef;
Kojto	115:87f2f5183dfb	591
Kojto	115:87f2f5183dfb	592
Kojto	115:87f2f5183dfb	593	/**
Kojto	115:87f2f5183dfb	594	* @brief General Purpose I/O
Kojto	115:87f2f5183dfb	595	*/
Kojto	115:87f2f5183dfb	596
Kojto	115:87f2f5183dfb	597	typedef struct
Kojto	115:87f2f5183dfb	598	{
Kojto	115:87f2f5183dfb	599	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	600	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	601	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	602	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	603	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	604	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	605	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	606	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	607	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
Kojto	115:87f2f5183dfb	608	} GPIO_TypeDef;
Kojto	115:87f2f5183dfb	609
Kojto	115:87f2f5183dfb	610	/**
Kojto	115:87f2f5183dfb	611	* @brief System configuration controller
Kojto	115:87f2f5183dfb	612	*/
Kojto	115:87f2f5183dfb	613
Kojto	115:87f2f5183dfb	614	typedef struct
Kojto	115:87f2f5183dfb	615	{
Kojto	115:87f2f5183dfb	616	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	617	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	618	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
Kojto	115:87f2f5183dfb	619	uint32_t RESERVED[2]; /!< Reserved, 0x18-0x1C /
Kojto	115:87f2f5183dfb	620	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	621	} SYSCFG_TypeDef;
Kojto	115:87f2f5183dfb	622
Kojto	115:87f2f5183dfb	623	/**
Kojto	115:87f2f5183dfb	624	* @brief Inter-integrated Circuit Interface
Kojto	115:87f2f5183dfb	625	*/
Kojto	115:87f2f5183dfb	626
Kojto	115:87f2f5183dfb	627	typedef struct
Kojto	115:87f2f5183dfb	628	{
Kojto	115:87f2f5183dfb	629	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	630	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	631	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	632	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	633	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	634	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	635	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	636	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	637	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	638	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
Kojto	115:87f2f5183dfb	639	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
Kojto	115:87f2f5183dfb	640	} I2C_TypeDef;
Kojto	115:87f2f5183dfb	641
Kojto	115:87f2f5183dfb	642	/**
Kojto	115:87f2f5183dfb	643	* @brief Independent WATCHDOG
Kojto	115:87f2f5183dfb	644	*/
Kojto	115:87f2f5183dfb	645
Kojto	115:87f2f5183dfb	646	typedef struct
Kojto	115:87f2f5183dfb	647	{
Kojto	115:87f2f5183dfb	648	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	649	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	650	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	651	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	652	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	653	} IWDG_TypeDef;
Kojto	115:87f2f5183dfb	654
Kojto	115:87f2f5183dfb	655
Kojto	115:87f2f5183dfb	656	/**
Kojto	115:87f2f5183dfb	657	* @brief LCD-TFT Display Controller
Kojto	115:87f2f5183dfb	658	*/
Kojto	115:87f2f5183dfb	659
Kojto	115:87f2f5183dfb	660	typedef struct
Kojto	115:87f2f5183dfb	661	{
Kojto	115:87f2f5183dfb	662	uint32_t RESERVED0[2]; /!< Reserved, 0x00-0x04 /
Kojto	115:87f2f5183dfb	663	__IO uint32_t SSCR; /!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	664	__IO uint32_t BPCR; /!< LTDC Back Porch Configuration Register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	665	__IO uint32_t AWCR; /!< LTDC Active Width Configuration Register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	666	__IO uint32_t TWCR; /!< LTDC Total Width Configuration Register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	667	__IO uint32_t GCR; /!< LTDC Global Control Register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	668	uint32_t RESERVED1[2]; /!< Reserved, 0x1C-0x20 /
Kojto	115:87f2f5183dfb	669	__IO uint32_t SRCR; /!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 /
Kojto	115:87f2f5183dfb	670	uint32_t RESERVED2[1]; /!< Reserved, 0x28 /
Kojto	115:87f2f5183dfb	671	__IO uint32_t BCCR; /!< LTDC Background Color Configuration Register, Address offset: 0x2C /
Kojto	115:87f2f5183dfb	672	uint32_t RESERVED3[1]; /!< Reserved, 0x30 /
Kojto	115:87f2f5183dfb	673	__IO uint32_t IER; /!< LTDC Interrupt Enable Register, Address offset: 0x34 /
Kojto	115:87f2f5183dfb	674	__IO uint32_t ISR; /!< LTDC Interrupt Status Register, Address offset: 0x38 /
Kojto	115:87f2f5183dfb	675	__IO uint32_t ICR; /!< LTDC Interrupt Clear Register, Address offset: 0x3C /
Kojto	115:87f2f5183dfb	676	__IO uint32_t LIPCR; /!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 /
Kojto	115:87f2f5183dfb	677	__IO uint32_t CPSR; /!< LTDC Current Position Status Register, Address offset: 0x44 /
Kojto	115:87f2f5183dfb	678	__IO uint32_t CDSR; /!< LTDC Current Display Status Register, Address offset: 0x48 /
Kojto	115:87f2f5183dfb	679	} LTDC_TypeDef;
Kojto	115:87f2f5183dfb	680
Kojto	115:87f2f5183dfb	681	/**
Kojto	115:87f2f5183dfb	682	* @brief LCD-TFT Display layer x Controller
Kojto	115:87f2f5183dfb	683	*/
Kojto	115:87f2f5183dfb	684
Kojto	115:87f2f5183dfb	685	typedef struct
Kojto	115:87f2f5183dfb	686	{
Kojto	115:87f2f5183dfb	687	__IO uint32_t CR; /!< LTDC Layerx Control Register Address offset: 0x84 /
Kojto	115:87f2f5183dfb	688	__IO uint32_t WHPCR; /!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 /
Kojto	115:87f2f5183dfb	689	__IO uint32_t WVPCR; /!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C /
Kojto	115:87f2f5183dfb	690	__IO uint32_t CKCR; /!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 /
Kojto	115:87f2f5183dfb	691	__IO uint32_t PFCR; /!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 /
Kojto	115:87f2f5183dfb	692	__IO uint32_t CACR; /!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 /
Kojto	115:87f2f5183dfb	693	__IO uint32_t DCCR; /!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C /
Kojto	115:87f2f5183dfb	694	__IO uint32_t BFCR; /!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 /
Kojto	115:87f2f5183dfb	695	uint32_t RESERVED0[2]; /!< Reserved /
Kojto	115:87f2f5183dfb	696	__IO uint32_t CFBAR; /!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC /
Kojto	115:87f2f5183dfb	697	__IO uint32_t CFBLR; /!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 /
Kojto	115:87f2f5183dfb	698	__IO uint32_t CFBLNR; /!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 /
Kojto	115:87f2f5183dfb	699	uint32_t RESERVED1[3]; /!< Reserved /
Kojto	115:87f2f5183dfb	700	__IO uint32_t CLUTWR; /!< LTDC Layerx CLUT Write Register Address offset: 0x144 /
Kojto	115:87f2f5183dfb	701
Kojto	115:87f2f5183dfb	702	} LTDC_Layer_TypeDef;
Kojto	115:87f2f5183dfb	703
Kojto	115:87f2f5183dfb	704
Kojto	115:87f2f5183dfb	705	/**
Kojto	115:87f2f5183dfb	706	* @brief Power Control
Kojto	115:87f2f5183dfb	707	*/
Kojto	115:87f2f5183dfb	708
Kojto	115:87f2f5183dfb	709	typedef struct
Kojto	115:87f2f5183dfb	710	{
Kojto	115:87f2f5183dfb	711	__IO uint32_t CR1; /!< PWR power control register 1, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	712	__IO uint32_t CSR1; /!< PWR power control/status register 2, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	713	__IO uint32_t CR2; /!< PWR power control register 2, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	714	__IO uint32_t CSR2; /!< PWR power control/status register 2, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	715	} PWR_TypeDef;
Kojto	115:87f2f5183dfb	716
Kojto	115:87f2f5183dfb	717
Kojto	115:87f2f5183dfb	718	/**
Kojto	115:87f2f5183dfb	719	* @brief Reset and Clock Control
Kojto	115:87f2f5183dfb	720	*/
Kojto	115:87f2f5183dfb	721
Kojto	115:87f2f5183dfb	722	typedef struct
Kojto	115:87f2f5183dfb	723	{
Kojto	115:87f2f5183dfb	724	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	725	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	726	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	727	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	728	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	729	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	730	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	731	uint32_t RESERVED0; /!< Reserved, 0x1C /
Kojto	115:87f2f5183dfb	732	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	733	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
Kojto	115:87f2f5183dfb	734	uint32_t RESERVED1[2]; /!< Reserved, 0x28-0x2C /
Kojto	115:87f2f5183dfb	735	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
Kojto	115:87f2f5183dfb	736	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
Kojto	115:87f2f5183dfb	737	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
Kojto	115:87f2f5183dfb	738	uint32_t RESERVED2; /!< Reserved, 0x3C /
Kojto	115:87f2f5183dfb	739	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
Kojto	115:87f2f5183dfb	740	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
Kojto	115:87f2f5183dfb	741	uint32_t RESERVED3[2]; /!< Reserved, 0x48-0x4C /
Kojto	115:87f2f5183dfb	742	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
Kojto	115:87f2f5183dfb	743	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
Kojto	115:87f2f5183dfb	744	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
Kojto	115:87f2f5183dfb	745	uint32_t RESERVED4; /!< Reserved, 0x5C /
Kojto	115:87f2f5183dfb	746	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
Kojto	115:87f2f5183dfb	747	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
Kojto	115:87f2f5183dfb	748	uint32_t RESERVED5[2]; /!< Reserved, 0x68-0x6C /
Kojto	115:87f2f5183dfb	749	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
Kojto	115:87f2f5183dfb	750	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
Kojto	115:87f2f5183dfb	751	uint32_t RESERVED6[2]; /!< Reserved, 0x78-0x7C /
Kojto	115:87f2f5183dfb	752	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
Kojto	115:87f2f5183dfb	753	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
Kojto	115:87f2f5183dfb	754	__IO uint32_t PLLSAICFGR; /!< RCC PLLSAI configuration register, Address offset: 0x88 /
Kojto	115:87f2f5183dfb	755	__IO uint32_t DCKCFGR1; /!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C /
Kojto	115:87f2f5183dfb	756	__IO uint32_t DCKCFGR2; /!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 /
Kojto	115:87f2f5183dfb	757
Kojto	115:87f2f5183dfb	758	} RCC_TypeDef;
Kojto	115:87f2f5183dfb	759
Kojto	115:87f2f5183dfb	760	/**
Kojto	115:87f2f5183dfb	761	* @brief Real-Time Clock
Kojto	115:87f2f5183dfb	762	*/
Kojto	115:87f2f5183dfb	763
Kojto	115:87f2f5183dfb	764	typedef struct
Kojto	115:87f2f5183dfb	765	{
Kojto	115:87f2f5183dfb	766	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	767	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	768	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	769	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	770	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	771	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	772	uint32_t reserved; /!< Reserved /
Kojto	115:87f2f5183dfb	773	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	774	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	775	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
Kojto	115:87f2f5183dfb	776	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
Kojto	115:87f2f5183dfb	777	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
Kojto	115:87f2f5183dfb	778	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
Kojto	115:87f2f5183dfb	779	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
Kojto	115:87f2f5183dfb	780	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
Kojto	115:87f2f5183dfb	781	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
Kojto	115:87f2f5183dfb	782	__IO uint32_t TAMPCR; /!< RTC tamper configuration register, Address offset: 0x40 /
Kojto	115:87f2f5183dfb	783	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
Kojto	115:87f2f5183dfb	784	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
Kojto	115:87f2f5183dfb	785	__IO uint32_t OR; /!< RTC option register, Address offset: 0x4C /
Kojto	115:87f2f5183dfb	786	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
Kojto	115:87f2f5183dfb	787	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
Kojto	115:87f2f5183dfb	788	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
Kojto	115:87f2f5183dfb	789	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
Kojto	115:87f2f5183dfb	790	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
Kojto	115:87f2f5183dfb	791	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
Kojto	115:87f2f5183dfb	792	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
Kojto	115:87f2f5183dfb	793	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
Kojto	115:87f2f5183dfb	794	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
Kojto	115:87f2f5183dfb	795	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
Kojto	115:87f2f5183dfb	796	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
Kojto	115:87f2f5183dfb	797	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
Kojto	115:87f2f5183dfb	798	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
Kojto	115:87f2f5183dfb	799	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
Kojto	115:87f2f5183dfb	800	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
Kojto	115:87f2f5183dfb	801	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
Kojto	115:87f2f5183dfb	802	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
Kojto	115:87f2f5183dfb	803	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
Kojto	115:87f2f5183dfb	804	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
Kojto	115:87f2f5183dfb	805	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
Kojto	115:87f2f5183dfb	806	__IO uint32_t BKP20R; /!< RTC backup register 20, Address offset: 0xA0 /
Kojto	115:87f2f5183dfb	807	__IO uint32_t BKP21R; /!< RTC backup register 21, Address offset: 0xA4 /
Kojto	115:87f2f5183dfb	808	__IO uint32_t BKP22R; /!< RTC backup register 22, Address offset: 0xA8 /
Kojto	115:87f2f5183dfb	809	__IO uint32_t BKP23R; /!< RTC backup register 23, Address offset: 0xAC /
Kojto	115:87f2f5183dfb	810	__IO uint32_t BKP24R; /!< RTC backup register 24, Address offset: 0xB0 /
Kojto	115:87f2f5183dfb	811	__IO uint32_t BKP25R; /!< RTC backup register 25, Address offset: 0xB4 /
Kojto	115:87f2f5183dfb	812	__IO uint32_t BKP26R; /!< RTC backup register 26, Address offset: 0xB8 /
Kojto	115:87f2f5183dfb	813	__IO uint32_t BKP27R; /!< RTC backup register 27, Address offset: 0xBC /
Kojto	115:87f2f5183dfb	814	__IO uint32_t BKP28R; /!< RTC backup register 28, Address offset: 0xC0 /
Kojto	115:87f2f5183dfb	815	__IO uint32_t BKP29R; /!< RTC backup register 29, Address offset: 0xC4 /
Kojto	115:87f2f5183dfb	816	__IO uint32_t BKP30R; /!< RTC backup register 30, Address offset: 0xC8 /
Kojto	115:87f2f5183dfb	817	__IO uint32_t BKP31R; /!< RTC backup register 31, Address offset: 0xCC /
Kojto	115:87f2f5183dfb	818	} RTC_TypeDef;
Kojto	115:87f2f5183dfb	819
Kojto	115:87f2f5183dfb	820
Kojto	115:87f2f5183dfb	821	/**
Kojto	115:87f2f5183dfb	822	* @brief Serial Audio Interface
Kojto	115:87f2f5183dfb	823	*/
Kojto	115:87f2f5183dfb	824
Kojto	115:87f2f5183dfb	825	typedef struct
Kojto	115:87f2f5183dfb	826	{
Kojto	115:87f2f5183dfb	827	__IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	828	} SAI_TypeDef;
Kojto	115:87f2f5183dfb	829
Kojto	115:87f2f5183dfb	830	typedef struct
Kojto	115:87f2f5183dfb	831	{
Kojto	115:87f2f5183dfb	832	__IO uint32_t CR1; /!< SAI block x configuration register 1, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	833	__IO uint32_t CR2; /!< SAI block x configuration register 2, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	834	__IO uint32_t FRCR; /!< SAI block x frame configuration register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	835	__IO uint32_t SLOTR; /!< SAI block x slot register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	836	__IO uint32_t IMR; /!< SAI block x interrupt mask register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	837	__IO uint32_t SR; /!< SAI block x status register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	838	__IO uint32_t CLRFR; /!< SAI block x clear flag register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	839	__IO uint32_t DR; /!< SAI block x data register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	840	} SAI_Block_TypeDef;
Kojto	115:87f2f5183dfb	841
Kojto	115:87f2f5183dfb	842	/**
Kojto	115:87f2f5183dfb	843	* @brief SPDIF-RX Interface
Kojto	115:87f2f5183dfb	844	*/
Kojto	115:87f2f5183dfb	845
Kojto	115:87f2f5183dfb	846	typedef struct
Kojto	115:87f2f5183dfb	847	{
Kojto	115:87f2f5183dfb	848	__IO uint32_t CR; /!< Control register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	849	__IO uint32_t IMR; /!< Interrupt mask register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	850	__IO uint32_t SR; /!< Status register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	851	__IO uint32_t IFCR; /!< Interrupt Flag Clear register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	852	__IO uint32_t DR; /!< Data input register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	853	__IO uint32_t CSR; /!< Channel Status register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	854	__IO uint32_t DIR; /!< Debug Information register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	855	} SPDIFRX_TypeDef;
Kojto	115:87f2f5183dfb	856
Kojto	115:87f2f5183dfb	857
Kojto	115:87f2f5183dfb	858	/**
Kojto	115:87f2f5183dfb	859	* @brief SD host Interface
Kojto	115:87f2f5183dfb	860	*/
Kojto	115:87f2f5183dfb	861
Kojto	115:87f2f5183dfb	862	typedef struct
Kojto	115:87f2f5183dfb	863	{
Kojto	115:87f2f5183dfb	864	__IO uint32_t POWER; /!< SDMMC power control register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	865	__IO uint32_t CLKCR; /!< SDMMClock control register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	866	__IO uint32_t ARG; /!< SDMMC argument register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	867	__IO uint32_t CMD; /!< SDMMC command register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	868	__I uint32_t RESPCMD; /!< SDMMC command response register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	869	__I uint32_t RESP1; /!< SDMMC response 1 register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	870	__I uint32_t RESP2; /!< SDMMC response 2 register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	871	__I uint32_t RESP3; /!< SDMMC response 3 register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	872	__I uint32_t RESP4; /!< SDMMC response 4 register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	873	__IO uint32_t DTIMER; /!< SDMMC data timer register, Address offset: 0x24 /
Kojto	115:87f2f5183dfb	874	__IO uint32_t DLEN; /!< SDMMC data length register, Address offset: 0x28 /
Kojto	115:87f2f5183dfb	875	__IO uint32_t DCTRL; /!< SDMMC data control register, Address offset: 0x2C /
Kojto	115:87f2f5183dfb	876	__I uint32_t DCOUNT; /!< SDMMC data counter register, Address offset: 0x30 /
Kojto	115:87f2f5183dfb	877	__I uint32_t STA; /!< SDMMC status register, Address offset: 0x34 /
Kojto	115:87f2f5183dfb	878	__IO uint32_t ICR; /!< SDMMC interrupt clear register, Address offset: 0x38 /
Kojto	115:87f2f5183dfb	879	__IO uint32_t MASK; /!< SDMMC mask register, Address offset: 0x3C /
Kojto	115:87f2f5183dfb	880	uint32_t RESERVED0[2]; /!< Reserved, 0x40-0x44 /
Kojto	115:87f2f5183dfb	881	__I uint32_t FIFOCNT; /!< SDMMC FIFO counter register, Address offset: 0x48 /
Kojto	115:87f2f5183dfb	882	uint32_t RESERVED1[13]; /!< Reserved, 0x4C-0x7C /
Kojto	115:87f2f5183dfb	883	__IO uint32_t FIFO; /!< SDMMC data FIFO register, Address offset: 0x80 /
Kojto	115:87f2f5183dfb	884	} SDMMC_TypeDef;
Kojto	115:87f2f5183dfb	885
Kojto	115:87f2f5183dfb	886	/**
Kojto	115:87f2f5183dfb	887	* @brief Serial Peripheral Interface
Kojto	115:87f2f5183dfb	888	*/
Kojto	115:87f2f5183dfb	889
Kojto	115:87f2f5183dfb	890	typedef struct
Kojto	115:87f2f5183dfb	891	{
Kojto	115:87f2f5183dfb	892	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
Kojto	115:87f2f5183dfb	893	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	894	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	895	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	896	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
Kojto	115:87f2f5183dfb	897	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
Kojto	115:87f2f5183dfb	898	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
Kojto	115:87f2f5183dfb	899	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	900	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	901	} SPI_TypeDef;
Kojto	115:87f2f5183dfb	902
Kojto	115:87f2f5183dfb	903	/**
Kojto	115:87f2f5183dfb	904	* @brief QUAD Serial Peripheral Interface
Kojto	115:87f2f5183dfb	905	*/
Kojto	115:87f2f5183dfb	906
Kojto	115:87f2f5183dfb	907	typedef struct
Kojto	115:87f2f5183dfb	908	{
Kojto	115:87f2f5183dfb	909	__IO uint32_t CR; /!< QUADSPI Control register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	910	__IO uint32_t DCR; /!< QUADSPI Device Configuration register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	911	__IO uint32_t SR; /!< QUADSPI Status register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	912	__IO uint32_t FCR; /!< QUADSPI Flag Clear register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	913	__IO uint32_t DLR; /!< QUADSPI Data Length register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	914	__IO uint32_t CCR; /!< QUADSPI Communication Configuration register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	915	__IO uint32_t AR; /!< QUADSPI Address register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	916	__IO uint32_t ABR; /!< QUADSPI Alternate Bytes register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	917	__IO uint32_t DR; /!< QUADSPI Data register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	918	__IO uint32_t PSMKR; /!< QUADSPI Polling Status Mask register, Address offset: 0x24 /
Kojto	115:87f2f5183dfb	919	__IO uint32_t PSMAR; /!< QUADSPI Polling Status Match register, Address offset: 0x28 /
Kojto	115:87f2f5183dfb	920	__IO uint32_t PIR; /!< QUADSPI Polling Interval register, Address offset: 0x2C /
Kojto	115:87f2f5183dfb	921	__IO uint32_t LPTR; /!< QUADSPI Low Power Timeout register, Address offset: 0x30 /
Kojto	115:87f2f5183dfb	922	} QUADSPI_TypeDef;
Kojto	115:87f2f5183dfb	923
Kojto	115:87f2f5183dfb	924	/**
Kojto	115:87f2f5183dfb	925	* @brief TIM
Kojto	115:87f2f5183dfb	926	*/
Kojto	115:87f2f5183dfb	927
Kojto	115:87f2f5183dfb	928	typedef struct
Kojto	115:87f2f5183dfb	929	{
Kojto	115:87f2f5183dfb	930	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	931	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	932	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	933	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	934	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	935	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	936	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	937	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	938	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	939	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
Kojto	115:87f2f5183dfb	940	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
Kojto	115:87f2f5183dfb	941	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
Kojto	115:87f2f5183dfb	942	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
Kojto	115:87f2f5183dfb	943	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
Kojto	115:87f2f5183dfb	944	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
Kojto	115:87f2f5183dfb	945	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
Kojto	115:87f2f5183dfb	946	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
Kojto	115:87f2f5183dfb	947	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
Kojto	115:87f2f5183dfb	948	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
Kojto	115:87f2f5183dfb	949	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
Kojto	115:87f2f5183dfb	950	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
Kojto	115:87f2f5183dfb	951	__IO uint32_t CCMR3; /!< TIM capture/compare mode register 3, Address offset: 0x54 /
Kojto	115:87f2f5183dfb	952	__IO uint32_t CCR5; /!< TIM capture/compare mode register5, Address offset: 0x58 /
Kojto	115:87f2f5183dfb	953	__IO uint32_t CCR6; /!< TIM capture/compare mode register6, Address offset: 0x5C /
Kojto	115:87f2f5183dfb	954
Kojto	115:87f2f5183dfb	955	} TIM_TypeDef;
Kojto	115:87f2f5183dfb	956
Kojto	115:87f2f5183dfb	957	/**
Kojto	115:87f2f5183dfb	958	* @brief LPTIMIMER
Kojto	115:87f2f5183dfb	959	*/
Kojto	115:87f2f5183dfb	960	typedef struct
Kojto	115:87f2f5183dfb	961	{
Kojto	115:87f2f5183dfb	962	__IO uint32_t ISR; /!< LPTIM Interrupt and Status register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	963	__IO uint32_t ICR; /!< LPTIM Interrupt Clear register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	964	__IO uint32_t IER; /!< LPTIM Interrupt Enable register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	965	__IO uint32_t CFGR; /!< LPTIM Configuration register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	966	__IO uint32_t CR; /!< LPTIM Control register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	967	__IO uint32_t CMP; /!< LPTIM Compare register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	968	__IO uint32_t ARR; /!< LPTIM Autoreload register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	969	__IO uint32_t CNT; /!< LPTIM Counter register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	970	__IO uint32_t OR; /!< LPTIM Option register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	971	} LPTIM_TypeDef;
Kojto	115:87f2f5183dfb	972
Kojto	115:87f2f5183dfb	973
Kojto	115:87f2f5183dfb	974	/**
Kojto	115:87f2f5183dfb	975	* @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto	115:87f2f5183dfb	976	*/
Kojto	115:87f2f5183dfb	977
Kojto	115:87f2f5183dfb	978	typedef struct
Kojto	115:87f2f5183dfb	979	{
Kojto	115:87f2f5183dfb	980	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	981	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	982	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	983	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
Kojto	115:87f2f5183dfb	984	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
Kojto	115:87f2f5183dfb	985	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
Kojto	115:87f2f5183dfb	986	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
Kojto	115:87f2f5183dfb	987	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
Kojto	115:87f2f5183dfb	988	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
Kojto	115:87f2f5183dfb	989	__IO uint32_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
Kojto	115:87f2f5183dfb	990	__IO uint32_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
Kojto	115:87f2f5183dfb	991	} USART_TypeDef;
Kojto	115:87f2f5183dfb	992
Kojto	115:87f2f5183dfb	993
Kojto	115:87f2f5183dfb	994	/**
Kojto	115:87f2f5183dfb	995	* @brief Window WATCHDOG
Kojto	115:87f2f5183dfb	996	*/
Kojto	115:87f2f5183dfb	997
Kojto	115:87f2f5183dfb	998	typedef struct
Kojto	115:87f2f5183dfb	999	{
Kojto	115:87f2f5183dfb	1000	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	1001	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	1002	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	1003	} WWDG_TypeDef;
Kojto	115:87f2f5183dfb	1004
Kojto	115:87f2f5183dfb	1005	/**
Kojto	115:87f2f5183dfb	1006	* @brief RNG
Kojto	115:87f2f5183dfb	1007	*/
Kojto	115:87f2f5183dfb	1008
Kojto	115:87f2f5183dfb	1009	typedef struct
Kojto	115:87f2f5183dfb	1010	{
Kojto	115:87f2f5183dfb	1011	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
Kojto	115:87f2f5183dfb	1012	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
Kojto	115:87f2f5183dfb	1013	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
Kojto	115:87f2f5183dfb	1014	} RNG_TypeDef;
Kojto	115:87f2f5183dfb	1015
Kojto	115:87f2f5183dfb	1016	/**
Kojto	115:87f2f5183dfb	1017	* @}
Kojto	115:87f2f5183dfb	1018	*/
Kojto	115:87f2f5183dfb	1019
Kojto	115:87f2f5183dfb	1020	/**
Kojto	115:87f2f5183dfb	1021	* @brief USB_OTG_Core_Registers
Kojto	115:87f2f5183dfb	1022	*/
Kojto	115:87f2f5183dfb	1023	typedef struct
Kojto	115:87f2f5183dfb	1024	{
Kojto	115:87f2f5183dfb	1025	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
Kojto	115:87f2f5183dfb	1026	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
Kojto	115:87f2f5183dfb	1027	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
Kojto	115:87f2f5183dfb	1028	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
Kojto	115:87f2f5183dfb	1029	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
Kojto	115:87f2f5183dfb	1030	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
Kojto	115:87f2f5183dfb	1031	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
Kojto	115:87f2f5183dfb	1032	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
Kojto	115:87f2f5183dfb	1033	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
Kojto	115:87f2f5183dfb	1034	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
Kojto	115:87f2f5183dfb	1035	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
Kojto	115:87f2f5183dfb	1036	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
Kojto	115:87f2f5183dfb	1037	uint32_t Reserved30[2]; /!< Reserved 030h /
Kojto	115:87f2f5183dfb	1038	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
Kojto	115:87f2f5183dfb	1039	__IO uint32_t CID; /!< User ID Register 03Ch /
Kojto	115:87f2f5183dfb	1040	uint32_t Reserved5[3]; /!< Reserved 040h-048h /
Kojto	115:87f2f5183dfb	1041	__IO uint32_t GHWCFG3; /!< User HW config3 04Ch /
Kojto	115:87f2f5183dfb	1042	uint32_t Reserved6; /!< Reserved 050h /
Kojto	115:87f2f5183dfb	1043	__IO uint32_t GLPMCFG; /!< LPM Register 054h /
Kojto	115:87f2f5183dfb	1044	__IO uint32_t GPWRDN; /!< Power Down Register 058h /
Kojto	115:87f2f5183dfb	1045	__IO uint32_t GDFIFOCFG; /!< DFIFO Software Config Register 05Ch /
Kojto	115:87f2f5183dfb	1046	__IO uint32_t GADPCTL; /!< ADP Timer, Control and Status Register 60Ch /
Kojto	115:87f2f5183dfb	1047	uint32_t Reserved43[39]; /!< Reserved 058h-0FFh /
Kojto	115:87f2f5183dfb	1048	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
Kojto	115:87f2f5183dfb	1049	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
Kojto	115:87f2f5183dfb	1050	} USB_OTG_GlobalTypeDef;
Kojto	115:87f2f5183dfb	1051
Kojto	115:87f2f5183dfb	1052
Kojto	115:87f2f5183dfb	1053	/**
Kojto	115:87f2f5183dfb	1054	* @brief USB_OTG_device_Registers
Kojto	115:87f2f5183dfb	1055	*/
Kojto	115:87f2f5183dfb	1056	typedef struct
Kojto	115:87f2f5183dfb	1057	{
Kojto	115:87f2f5183dfb	1058	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
Kojto	115:87f2f5183dfb	1059	__IO uint32_t DCTL; /!< dev Control Register 804h /
Kojto	115:87f2f5183dfb	1060	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
Kojto	115:87f2f5183dfb	1061	uint32_t Reserved0C; /!< Reserved 80Ch /
Kojto	115:87f2f5183dfb	1062	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
Kojto	115:87f2f5183dfb	1063	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
Kojto	115:87f2f5183dfb	1064	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
Kojto	115:87f2f5183dfb	1065	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
Kojto	115:87f2f5183dfb	1066	uint32_t Reserved20; /!< Reserved 820h /
Kojto	115:87f2f5183dfb	1067	uint32_t Reserved9; /!< Reserved 824h /
Kojto	115:87f2f5183dfb	1068	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
Kojto	115:87f2f5183dfb	1069	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
Kojto	115:87f2f5183dfb	1070	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
Kojto	115:87f2f5183dfb	1071	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
Kojto	115:87f2f5183dfb	1072	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
Kojto	115:87f2f5183dfb	1073	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
Kojto	115:87f2f5183dfb	1074	uint32_t Reserved40; /!< dedicated EP mask 840h /
Kojto	115:87f2f5183dfb	1075	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
Kojto	115:87f2f5183dfb	1076	uint32_t Reserved44[15]; /!< Reserved 844-87Ch /
Kojto	115:87f2f5183dfb	1077	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
Kojto	115:87f2f5183dfb	1078	} USB_OTG_DeviceTypeDef;
Kojto	115:87f2f5183dfb	1079
Kojto	115:87f2f5183dfb	1080
Kojto	115:87f2f5183dfb	1081	/**
Kojto	115:87f2f5183dfb	1082	* @brief USB_OTG_IN_Endpoint-Specific_Register
Kojto	115:87f2f5183dfb	1083	*/
Kojto	115:87f2f5183dfb	1084	typedef struct
Kojto	115:87f2f5183dfb	1085	{
Kojto	115:87f2f5183dfb	1086	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
Kojto	115:87f2f5183dfb	1087	uint32_t Reserved04; /!< Reserved 900h + (ep_num 20h) + 04h */
Kojto	115:87f2f5183dfb	1088	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
Kojto	115:87f2f5183dfb	1089	uint32_t Reserved0C; /!< Reserved 900h + (ep_num 20h) + 0Ch */
Kojto	115:87f2f5183dfb	1090	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
Kojto	115:87f2f5183dfb	1091	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
Kojto	115:87f2f5183dfb	1092	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
Kojto	115:87f2f5183dfb	1093	uint32_t Reserved18; /!< Reserved 900h+(ep_num20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
Kojto	115:87f2f5183dfb	1094	} USB_OTG_INEndpointTypeDef;
Kojto	115:87f2f5183dfb	1095
Kojto	115:87f2f5183dfb	1096
Kojto	115:87f2f5183dfb	1097	/**
Kojto	115:87f2f5183dfb	1098	* @brief USB_OTG_OUT_Endpoint-Specific_Registers
Kojto	115:87f2f5183dfb	1099	*/
Kojto	115:87f2f5183dfb	1100	typedef struct
Kojto	115:87f2f5183dfb	1101	{
Kojto	115:87f2f5183dfb	1102	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
Kojto	115:87f2f5183dfb	1103	uint32_t Reserved04; /!< Reserved B00h + (ep_num 20h) + 04h */
Kojto	115:87f2f5183dfb	1104	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
Kojto	115:87f2f5183dfb	1105	uint32_t Reserved0C; /!< Reserved B00h + (ep_num 20h) + 0Ch */
Kojto	115:87f2f5183dfb	1106	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
Kojto	115:87f2f5183dfb	1107	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
Kojto	115:87f2f5183dfb	1108	uint32_t Reserved18[2]; /!< Reserved B00h + (ep_num 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
Kojto	115:87f2f5183dfb	1109	} USB_OTG_OUTEndpointTypeDef;
Kojto	115:87f2f5183dfb	1110
Kojto	115:87f2f5183dfb	1111
Kojto	115:87f2f5183dfb	1112	/**
Kojto	115:87f2f5183dfb	1113	* @brief USB_OTG_Host_Mode_Register_Structures
Kojto	115:87f2f5183dfb	1114	*/
Kojto	115:87f2f5183dfb	1115	typedef struct
Kojto	115:87f2f5183dfb	1116	{
Kojto	115:87f2f5183dfb	1117	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
Kojto	115:87f2f5183dfb	1118	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
Kojto	115:87f2f5183dfb	1119	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
Kojto	115:87f2f5183dfb	1120	uint32_t Reserved40C; /!< Reserved 40Ch /
Kojto	115:87f2f5183dfb	1121	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
Kojto	115:87f2f5183dfb	1122	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
Kojto	115:87f2f5183dfb	1123	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
Kojto	115:87f2f5183dfb	1124	} USB_OTG_HostTypeDef;
Kojto	115:87f2f5183dfb	1125
Kojto	115:87f2f5183dfb	1126	/**
Kojto	115:87f2f5183dfb	1127	* @brief USB_OTG_Host_Channel_Specific_Registers
Kojto	115:87f2f5183dfb	1128	*/
Kojto	115:87f2f5183dfb	1129	typedef struct
Kojto	115:87f2f5183dfb	1130	{
Kojto	115:87f2f5183dfb	1131	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
Kojto	115:87f2f5183dfb	1132	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
Kojto	115:87f2f5183dfb	1133	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
Kojto	115:87f2f5183dfb	1134	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
Kojto	115:87f2f5183dfb	1135	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
Kojto	115:87f2f5183dfb	1136	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
Kojto	115:87f2f5183dfb	1137	uint32_t Reserved[2]; /!< Reserved /
Kojto	115:87f2f5183dfb	1138	} USB_OTG_HostChannelTypeDef;
Kojto	115:87f2f5183dfb	1139	/**
Kojto	115:87f2f5183dfb	1140	* @}
Kojto	115:87f2f5183dfb	1141	*/
Kojto	115:87f2f5183dfb	1142
Kojto	115:87f2f5183dfb	1143
Kojto	115:87f2f5183dfb	1144	/** @addtogroup Peripheral_memory_map
Kojto	115:87f2f5183dfb	1145	* @{
Kojto	115:87f2f5183dfb	1146	*/
Kojto	115:87f2f5183dfb	1147	#define RAMITCM_BASE ((uint32_t)0x00000000) /!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM /
Kojto	115:87f2f5183dfb	1148	#define FLASHITCM_BASE ((uint32_t)0x00200000) /!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM /
Kojto	115:87f2f5183dfb	1149	#define FLASHAXI_BASE ((uint32_t)0x08000000) /!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI /
Kojto	115:87f2f5183dfb	1150	#define RAMDTCM_BASE ((uint32_t)0x20000000) /!< Base address of : 64KB system data RAM accessible over DTCM /
Kojto	115:87f2f5183dfb	1151	#define SRAM1_BASE ((uint32_t)0x20010000) /!< Base address of : 240KB RAM1 accessible over AXI/AHB /
Kojto	115:87f2f5183dfb	1152	#define SRAM2_BASE ((uint32_t)0x2004C000) /!< Base address of : 16KB RAM2 accessible over AXI/AHB /
Kojto	115:87f2f5183dfb	1153	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Base address of : AHB/ABP Peripherals /
Kojto	115:87f2f5183dfb	1154	#define BKPSRAM_BASE ((uint32_t)0x40024000) /!< Base address of : Backup SRAM(4 KB) /
Kojto	115:87f2f5183dfb	1155	#define QSPI_BASE ((uint32_t)0x90000000) /!< Base address of : QSPI memories accessible over AXI /
Kojto	115:87f2f5183dfb	1156	#define FMC_R_BASE ((uint32_t)0xA0000000) /!< Base address of : FMC Control registers /
Kojto	115:87f2f5183dfb	1157	#define QSPI_R_BASE ((uint32_t)0xA0001000) /!< Base address of : QSPI Control registers /
Kojto	115:87f2f5183dfb	1158	#define FLASH_END ((uint32_t)0x080FFFFF) /!< FLASH end address /
Kojto	115:87f2f5183dfb	1159
Kojto	115:87f2f5183dfb	1160	/* Legacy define */
Kojto	115:87f2f5183dfb	1161	#define FLASH_BASE FLASHAXI_BASE
Kojto	115:87f2f5183dfb	1162
Kojto	115:87f2f5183dfb	1163	/!< Peripheral memory map /
Kojto	115:87f2f5183dfb	1164	#define APB1PERIPH_BASE PERIPH_BASE
Kojto	115:87f2f5183dfb	1165	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
Kojto	115:87f2f5183dfb	1166	#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto	115:87f2f5183dfb	1167	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
Kojto	115:87f2f5183dfb	1168
Kojto	115:87f2f5183dfb	1169	/!< APB1 peripherals /
Kojto	115:87f2f5183dfb	1170	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
Kojto	115:87f2f5183dfb	1171	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
Kojto	115:87f2f5183dfb	1172	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
Kojto	115:87f2f5183dfb	1173	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
Kojto	115:87f2f5183dfb	1174	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
Kojto	115:87f2f5183dfb	1175	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
Kojto	115:87f2f5183dfb	1176	#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
Kojto	115:87f2f5183dfb	1177	#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
Kojto	115:87f2f5183dfb	1178	#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
Kojto	115:87f2f5183dfb	1179	#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
Kojto	115:87f2f5183dfb	1180	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
Kojto	115:87f2f5183dfb	1181	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
Kojto	115:87f2f5183dfb	1182	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
Kojto	115:87f2f5183dfb	1183	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
Kojto	115:87f2f5183dfb	1184	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
Kojto	115:87f2f5183dfb	1185	#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
Kojto	115:87f2f5183dfb	1186	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
Kojto	115:87f2f5183dfb	1187	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
Kojto	115:87f2f5183dfb	1188	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
Kojto	115:87f2f5183dfb	1189	#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
Kojto	115:87f2f5183dfb	1190	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
Kojto	115:87f2f5183dfb	1191	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
Kojto	115:87f2f5183dfb	1192	#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
Kojto	115:87f2f5183dfb	1193	#define I2C4_BASE (APB1PERIPH_BASE + 0x6000)
Kojto	115:87f2f5183dfb	1194	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
Kojto	115:87f2f5183dfb	1195	#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
Kojto	115:87f2f5183dfb	1196	#define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
Kojto	115:87f2f5183dfb	1197	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
Kojto	115:87f2f5183dfb	1198	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
Kojto	115:87f2f5183dfb	1199	#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
Kojto	115:87f2f5183dfb	1200	#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
Kojto	115:87f2f5183dfb	1201
Kojto	115:87f2f5183dfb	1202	/!< APB2 peripherals /
Kojto	115:87f2f5183dfb	1203	#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
Kojto	115:87f2f5183dfb	1204	#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
Kojto	115:87f2f5183dfb	1205	#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
Kojto	115:87f2f5183dfb	1206	#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
Kojto	115:87f2f5183dfb	1207	#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
Kojto	115:87f2f5183dfb	1208	#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
Kojto	115:87f2f5183dfb	1209	#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
Kojto	115:87f2f5183dfb	1210	#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
Kojto	115:87f2f5183dfb	1211	#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00)
Kojto	115:87f2f5183dfb	1212	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
Kojto	115:87f2f5183dfb	1213	#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
Kojto	115:87f2f5183dfb	1214	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
Kojto	115:87f2f5183dfb	1215	#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
Kojto	115:87f2f5183dfb	1216	#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
Kojto	115:87f2f5183dfb	1217	#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
Kojto	115:87f2f5183dfb	1218	#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
Kojto	115:87f2f5183dfb	1219	#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
Kojto	115:87f2f5183dfb	1220	#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
Kojto	115:87f2f5183dfb	1221	#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
Kojto	115:87f2f5183dfb	1222	#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
Kojto	115:87f2f5183dfb	1223	#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
Kojto	115:87f2f5183dfb	1224	#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
Kojto	115:87f2f5183dfb	1225	#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
Kojto	115:87f2f5183dfb	1226	#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
Kojto	115:87f2f5183dfb	1227	#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
Kojto	115:87f2f5183dfb	1228	#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
Kojto	115:87f2f5183dfb	1229	#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
Kojto	115:87f2f5183dfb	1230	/!< AHB1 peripherals /
Kojto	115:87f2f5183dfb	1231	#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
Kojto	115:87f2f5183dfb	1232	#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
Kojto	115:87f2f5183dfb	1233	#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
Kojto	115:87f2f5183dfb	1234	#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
Kojto	115:87f2f5183dfb	1235	#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
Kojto	115:87f2f5183dfb	1236	#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
Kojto	115:87f2f5183dfb	1237	#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
Kojto	115:87f2f5183dfb	1238	#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
Kojto	115:87f2f5183dfb	1239	#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
Kojto	115:87f2f5183dfb	1240	#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
Kojto	115:87f2f5183dfb	1241	#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
Kojto	115:87f2f5183dfb	1242	#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
Kojto	115:87f2f5183dfb	1243	#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
Kojto	115:87f2f5183dfb	1244	#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
Kojto	115:87f2f5183dfb	1245	#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
Kojto	115:87f2f5183dfb	1246	#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
Kojto	115:87f2f5183dfb	1247	#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
Kojto	115:87f2f5183dfb	1248	#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
Kojto	115:87f2f5183dfb	1249	#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
Kojto	115:87f2f5183dfb	1250	#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
Kojto	115:87f2f5183dfb	1251	#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
Kojto	115:87f2f5183dfb	1252	#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
Kojto	115:87f2f5183dfb	1253	#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
Kojto	115:87f2f5183dfb	1254	#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
Kojto	115:87f2f5183dfb	1255	#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
Kojto	115:87f2f5183dfb	1256	#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
Kojto	115:87f2f5183dfb	1257	#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
Kojto	115:87f2f5183dfb	1258	#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
Kojto	115:87f2f5183dfb	1259	#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
Kojto	115:87f2f5183dfb	1260	#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
Kojto	115:87f2f5183dfb	1261	#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
Kojto	115:87f2f5183dfb	1262	#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
Kojto	115:87f2f5183dfb	1263	#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
Kojto	115:87f2f5183dfb	1264	#define ETH_MAC_BASE (ETH_BASE)
Kojto	115:87f2f5183dfb	1265	#define ETH_MMC_BASE (ETH_BASE + 0x0100)
Kojto	115:87f2f5183dfb	1266	#define ETH_PTP_BASE (ETH_BASE + 0x0700)
Kojto	115:87f2f5183dfb	1267	#define ETH_DMA_BASE (ETH_BASE + 0x1000)
Kojto	115:87f2f5183dfb	1268	#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
Kojto	115:87f2f5183dfb	1269	/!< AHB2 peripherals /
Kojto	115:87f2f5183dfb	1270	#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
Kojto	115:87f2f5183dfb	1271	#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
Kojto	115:87f2f5183dfb	1272	/!< FMC Bankx registers base address /
Kojto	115:87f2f5183dfb	1273	#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
Kojto	115:87f2f5183dfb	1274	#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
Kojto	115:87f2f5183dfb	1275	#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
Kojto	115:87f2f5183dfb	1276	#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
Kojto	115:87f2f5183dfb	1277
Kojto	115:87f2f5183dfb	1278	/* Debug MCU registers base address */
Kojto	115:87f2f5183dfb	1279	#define DBGMCU_BASE ((uint32_t )0xE0042000)
Kojto	115:87f2f5183dfb	1280
Kojto	115:87f2f5183dfb	1281	/!< USB registers base address /
Kojto	115:87f2f5183dfb	1282	#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
Kojto	115:87f2f5183dfb	1283	#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
Kojto	115:87f2f5183dfb	1284
Kojto	115:87f2f5183dfb	1285	#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
Kojto	115:87f2f5183dfb	1286	#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
Kojto	115:87f2f5183dfb	1287	#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
Kojto	115:87f2f5183dfb	1288	#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
Kojto	115:87f2f5183dfb	1289	#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
Kojto	115:87f2f5183dfb	1290	#define USB_OTG_HOST_BASE ((uint32_t )0x400)
Kojto	115:87f2f5183dfb	1291	#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
Kojto	115:87f2f5183dfb	1292	#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
Kojto	115:87f2f5183dfb	1293	#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
Kojto	115:87f2f5183dfb	1294	#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
Kojto	115:87f2f5183dfb	1295	#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
Kojto	115:87f2f5183dfb	1296	#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
Kojto	115:87f2f5183dfb	1297
Kojto	115:87f2f5183dfb	1298	/**
Kojto	115:87f2f5183dfb	1299	* @}
Kojto	115:87f2f5183dfb	1300	*/
Kojto	115:87f2f5183dfb	1301
Kojto	115:87f2f5183dfb	1302	/** @addtogroup Peripheral_declaration
Kojto	115:87f2f5183dfb	1303	* @{
Kojto	115:87f2f5183dfb	1304	*/
Kojto	115:87f2f5183dfb	1305	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto	115:87f2f5183dfb	1306	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto	115:87f2f5183dfb	1307	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto	115:87f2f5183dfb	1308	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto	115:87f2f5183dfb	1309	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto	115:87f2f5183dfb	1310	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto	115:87f2f5183dfb	1311	#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
Kojto	115:87f2f5183dfb	1312	#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
Kojto	115:87f2f5183dfb	1313	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto	115:87f2f5183dfb	1314	#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
Kojto	115:87f2f5183dfb	1315	#define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto	115:87f2f5183dfb	1316	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto	115:87f2f5183dfb	1317	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto	115:87f2f5183dfb	1318	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto	115:87f2f5183dfb	1319	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto	115:87f2f5183dfb	1320	#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
Kojto	115:87f2f5183dfb	1321	#define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto	115:87f2f5183dfb	1322	#define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto	115:87f2f5183dfb	1323	#define UART4 ((USART_TypeDef *) UART4_BASE)
Kojto	115:87f2f5183dfb	1324	#define UART5 ((USART_TypeDef *) UART5_BASE)
Kojto	115:87f2f5183dfb	1325	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto	115:87f2f5183dfb	1326	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto	115:87f2f5183dfb	1327	#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
Kojto	115:87f2f5183dfb	1328	#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
Kojto	115:87f2f5183dfb	1329	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
Kojto	115:87f2f5183dfb	1330	#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
Kojto	115:87f2f5183dfb	1331	#define CEC ((CEC_TypeDef *) CEC_BASE)
Kojto	115:87f2f5183dfb	1332	#define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto	115:87f2f5183dfb	1333	#define DAC ((DAC_TypeDef *) DAC_BASE)
Kojto	115:87f2f5183dfb	1334	#define UART7 ((USART_TypeDef *) UART7_BASE)
Kojto	115:87f2f5183dfb	1335	#define UART8 ((USART_TypeDef *) UART8_BASE)
Kojto	115:87f2f5183dfb	1336	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto	115:87f2f5183dfb	1337	#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
Kojto	115:87f2f5183dfb	1338	#define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto	115:87f2f5183dfb	1339	#define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto	115:87f2f5183dfb	1340	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto	115:87f2f5183dfb	1341	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto	115:87f2f5183dfb	1342	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
Kojto	115:87f2f5183dfb	1343	#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
Kojto	115:87f2f5183dfb	1344	#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
Kojto	115:87f2f5183dfb	1345	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto	115:87f2f5183dfb	1346	#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
Kojto	115:87f2f5183dfb	1347	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto	115:87f2f5183dfb	1348	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto	115:87f2f5183dfb	1349	#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto	115:87f2f5183dfb	1350	#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto	115:87f2f5183dfb	1351	#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto	115:87f2f5183dfb	1352	#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
Kojto	115:87f2f5183dfb	1353	#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
Kojto	115:87f2f5183dfb	1354	#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
Kojto	115:87f2f5183dfb	1355	#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
Kojto	115:87f2f5183dfb	1356	#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
Kojto	115:87f2f5183dfb	1357	#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
Kojto	115:87f2f5183dfb	1358	#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
Kojto	115:87f2f5183dfb	1359	#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
Kojto	115:87f2f5183dfb	1360	#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
Kojto	115:87f2f5183dfb	1361	#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
Kojto	115:87f2f5183dfb	1362	#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
Kojto	115:87f2f5183dfb	1363	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto	115:87f2f5183dfb	1364	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto	115:87f2f5183dfb	1365	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto	115:87f2f5183dfb	1366	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto	115:87f2f5183dfb	1367	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto	115:87f2f5183dfb	1368	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto	115:87f2f5183dfb	1369	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
Kojto	115:87f2f5183dfb	1370	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto	115:87f2f5183dfb	1371	#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
Kojto	115:87f2f5183dfb	1372	#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
Kojto	115:87f2f5183dfb	1373	#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
Kojto	115:87f2f5183dfb	1374	#define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto	115:87f2f5183dfb	1375	#define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto	115:87f2f5183dfb	1376	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto	115:87f2f5183dfb	1377	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto	115:87f2f5183dfb	1378	#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Kojto	115:87f2f5183dfb	1379	#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
Kojto	115:87f2f5183dfb	1380	#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
Kojto	115:87f2f5183dfb	1381	#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
Kojto	115:87f2f5183dfb	1382	#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
Kojto	115:87f2f5183dfb	1383	#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
Kojto	115:87f2f5183dfb	1384	#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
Kojto	115:87f2f5183dfb	1385	#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
Kojto	115:87f2f5183dfb	1386	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto	115:87f2f5183dfb	1387	#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
Kojto	115:87f2f5183dfb	1388	#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
Kojto	115:87f2f5183dfb	1389	#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
Kojto	115:87f2f5183dfb	1390	#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
Kojto	115:87f2f5183dfb	1391	#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
Kojto	115:87f2f5183dfb	1392	#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
Kojto	115:87f2f5183dfb	1393	#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
Kojto	115:87f2f5183dfb	1394	#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
Kojto	115:87f2f5183dfb	1395	#define ETH ((ETH_TypeDef *) ETH_BASE)
Kojto	115:87f2f5183dfb	1396	#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
Kojto	115:87f2f5183dfb	1397	#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
Kojto	115:87f2f5183dfb	1398	#define RNG ((RNG_TypeDef *) RNG_BASE)
Kojto	115:87f2f5183dfb	1399	#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
Kojto	115:87f2f5183dfb	1400	#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
Kojto	115:87f2f5183dfb	1401	#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
Kojto	115:87f2f5183dfb	1402	#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
Kojto	115:87f2f5183dfb	1403	#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
Kojto	115:87f2f5183dfb	1404	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto	115:87f2f5183dfb	1405	#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
Kojto	115:87f2f5183dfb	1406	#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
Kojto	115:87f2f5183dfb	1407
Kojto	115:87f2f5183dfb	1408	/**
Kojto	115:87f2f5183dfb	1409	* @}
Kojto	115:87f2f5183dfb	1410	*/
Kojto	115:87f2f5183dfb	1411
Kojto	115:87f2f5183dfb	1412	/** @addtogroup Exported_constants
Kojto	115:87f2f5183dfb	1413	* @{
Kojto	115:87f2f5183dfb	1414	*/
Kojto	115:87f2f5183dfb	1415
Kojto	115:87f2f5183dfb	1416	/** @addtogroup Peripheral_Registers_Bits_Definition
Kojto	115:87f2f5183dfb	1417	* @{
Kojto	115:87f2f5183dfb	1418	*/
Kojto	115:87f2f5183dfb	1419
Kojto	115:87f2f5183dfb	1420	/******************************************************************************/
Kojto	115:87f2f5183dfb	1421	/* Peripheral Registers_Bits_Definition */
Kojto	115:87f2f5183dfb	1422	/******************************************************************************/
Kojto	115:87f2f5183dfb	1423
Kojto	115:87f2f5183dfb	1424	/******************************************************************************/
Kojto	115:87f2f5183dfb	1425	/* */
Kojto	115:87f2f5183dfb	1426	/* Analog to Digital Converter */
Kojto	115:87f2f5183dfb	1427	/* */
Kojto	115:87f2f5183dfb	1428	/******************************************************************************/
Kojto	115:87f2f5183dfb	1429	/****************** Bit definition for ADC_SR register ******************/
Kojto	115:87f2f5183dfb	1430	#define ADC_SR_AWD ((uint32_t)0x00000001) /!<Analog watchdog flag /
Kojto	115:87f2f5183dfb	1431	#define ADC_SR_EOC ((uint32_t)0x00000002) /!<End of conversion /
Kojto	115:87f2f5183dfb	1432	#define ADC_SR_JEOC ((uint32_t)0x00000004) /!<Injected channel end of conversion /
Kojto	115:87f2f5183dfb	1433	#define ADC_SR_JSTRT ((uint32_t)0x00000008) /!<Injected channel Start flag /
Kojto	115:87f2f5183dfb	1434	#define ADC_SR_STRT ((uint32_t)0x00000010) /!<Regular channel Start flag /
Kojto	115:87f2f5183dfb	1435	#define ADC_SR_OVR ((uint32_t)0x00000020) /!<Overrun flag /
Kojto	115:87f2f5183dfb	1436
Kojto	115:87f2f5183dfb	1437	/***************** Bit definition for ADC_CR1 register ******************/
Kojto	115:87f2f5183dfb	1438	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!<AWDCH[4:0] bits (Analog watchdog channel select bits) /
Kojto	115:87f2f5183dfb	1439	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1440	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1441	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1442	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1443	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1444	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!<Interrupt enable for EOC /
Kojto	115:87f2f5183dfb	1445	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!<AAnalog Watchdog interrupt enable /
Kojto	115:87f2f5183dfb	1446	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!<Interrupt enable for injected channels /
Kojto	115:87f2f5183dfb	1447	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!<Scan mode /
Kojto	115:87f2f5183dfb	1448	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!<Enable the watchdog on a single channel in scan mode /
Kojto	115:87f2f5183dfb	1449	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!<Automatic injected group conversion /
Kojto	115:87f2f5183dfb	1450	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!<Discontinuous mode on regular channels /
Kojto	115:87f2f5183dfb	1451	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!<Discontinuous mode on injected channels /
Kojto	115:87f2f5183dfb	1452	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!<DISCNUM[2:0] bits (Discontinuous mode channel count) /
Kojto	115:87f2f5183dfb	1453	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1454	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1455	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1456	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!<Analog watchdog enable on injected channels /
Kojto	115:87f2f5183dfb	1457	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!<Analog watchdog enable on regular channels /
Kojto	115:87f2f5183dfb	1458	#define ADC_CR1_RES ((uint32_t)0x03000000) /!<RES[2:0] bits (Resolution) /
Kojto	115:87f2f5183dfb	1459	#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1460	#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1461	#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /!<overrun interrupt enable /
Kojto	115:87f2f5183dfb	1462
Kojto	115:87f2f5183dfb	1463	/***************** Bit definition for ADC_CR2 register ******************/
Kojto	115:87f2f5183dfb	1464	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!<A/D Converter ON / OFF /
Kojto	115:87f2f5183dfb	1465	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!<Continuous Conversion /
Kojto	115:87f2f5183dfb	1466	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!<Direct Memory access mode /
Kojto	115:87f2f5183dfb	1467	#define ADC_CR2_DDS ((uint32_t)0x00000200) /!<DMA disable selection (Single ADC) /
Kojto	115:87f2f5183dfb	1468	#define ADC_CR2_EOCS ((uint32_t)0x00000400) /!<End of conversion selection /
Kojto	115:87f2f5183dfb	1469	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!<Data Alignment /
Kojto	115:87f2f5183dfb	1470	#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /!<JEXTSEL[3:0] bits (External event select for injected group) /
Kojto	115:87f2f5183dfb	1471	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1472	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1473	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1474	#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1475	#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) /
Kojto	115:87f2f5183dfb	1476	#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1477	#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1478	#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /!<Start Conversion of injected channels /
Kojto	115:87f2f5183dfb	1479	#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /!<EXTSEL[3:0] bits (External Event Select for regular group) /
Kojto	115:87f2f5183dfb	1480	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1481	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1482	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1483	#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1484	#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) /
Kojto	115:87f2f5183dfb	1485	#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1486	#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1487	#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /!<Start Conversion of regular channels /
Kojto	115:87f2f5183dfb	1488
Kojto	115:87f2f5183dfb	1489	/**************** Bit definition for ADC_SMPR1 register *****************/
Kojto	115:87f2f5183dfb	1490	#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /!<SMP10[2:0] bits (Channel 10 Sample time selection) /
Kojto	115:87f2f5183dfb	1491	#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1492	#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1493	#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1494	#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /!<SMP11[2:0] bits (Channel 11 Sample time selection) /
Kojto	115:87f2f5183dfb	1495	#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1496	#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1497	#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1498	#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /!<SMP12[2:0] bits (Channel 12 Sample time selection) /
Kojto	115:87f2f5183dfb	1499	#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1500	#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1501	#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1502	#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /!<SMP13[2:0] bits (Channel 13 Sample time selection) /
Kojto	115:87f2f5183dfb	1503	#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1504	#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1505	#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1506	#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /!<SMP14[2:0] bits (Channel 14 Sample time selection) /
Kojto	115:87f2f5183dfb	1507	#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1508	#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1509	#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1510	#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /!<SMP15[2:0] bits (Channel 15 Sample time selection) /
Kojto	115:87f2f5183dfb	1511	#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1512	#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1513	#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1514	#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /!<SMP16[2:0] bits (Channel 16 Sample time selection) /
Kojto	115:87f2f5183dfb	1515	#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1516	#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1517	#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1518	#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /!<SMP17[2:0] bits (Channel 17 Sample time selection) /
Kojto	115:87f2f5183dfb	1519	#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1520	#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1521	#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1522	#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /!<SMP18[2:0] bits (Channel 18 Sample time selection) /
Kojto	115:87f2f5183dfb	1523	#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1524	#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1525	#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1526
Kojto	115:87f2f5183dfb	1527	/**************** Bit definition for ADC_SMPR2 register *****************/
Kojto	115:87f2f5183dfb	1528	#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /!<SMP0[2:0] bits (Channel 0 Sample time selection) /
Kojto	115:87f2f5183dfb	1529	#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1530	#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1531	#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1532	#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /!<SMP1[2:0] bits (Channel 1 Sample time selection) /
Kojto	115:87f2f5183dfb	1533	#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1534	#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1535	#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1536	#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /!<SMP2[2:0] bits (Channel 2 Sample time selection) /
Kojto	115:87f2f5183dfb	1537	#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1538	#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1539	#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1540	#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /!<SMP3[2:0] bits (Channel 3 Sample time selection) /
Kojto	115:87f2f5183dfb	1541	#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1542	#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1543	#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1544	#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /!<SMP4[2:0] bits (Channel 4 Sample time selection) /
Kojto	115:87f2f5183dfb	1545	#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1546	#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1547	#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1548	#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /!<SMP5[2:0] bits (Channel 5 Sample time selection) /
Kojto	115:87f2f5183dfb	1549	#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1550	#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1551	#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1552	#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /!<SMP6[2:0] bits (Channel 6 Sample time selection) /
Kojto	115:87f2f5183dfb	1553	#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1554	#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1555	#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1556	#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /!<SMP7[2:0] bits (Channel 7 Sample time selection) /
Kojto	115:87f2f5183dfb	1557	#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1558	#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1559	#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1560	#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /!<SMP8[2:0] bits (Channel 8 Sample time selection) /
Kojto	115:87f2f5183dfb	1561	#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1562	#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1563	#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1564	#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /!<SMP9[2:0] bits (Channel 9 Sample time selection) /
Kojto	115:87f2f5183dfb	1565	#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1566	#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1567	#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1568
Kojto	115:87f2f5183dfb	1569	/**************** Bit definition for ADC_JOFR1 register *****************/
Kojto	115:87f2f5183dfb	1570	#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /!<Data offset for injected channel 1 /
Kojto	115:87f2f5183dfb	1571
Kojto	115:87f2f5183dfb	1572	/**************** Bit definition for ADC_JOFR2 register *****************/
Kojto	115:87f2f5183dfb	1573	#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /!<Data offset for injected channel 2 /
Kojto	115:87f2f5183dfb	1574
Kojto	115:87f2f5183dfb	1575	/**************** Bit definition for ADC_JOFR3 register *****************/
Kojto	115:87f2f5183dfb	1576	#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /!<Data offset for injected channel 3 /
Kojto	115:87f2f5183dfb	1577
Kojto	115:87f2f5183dfb	1578	/**************** Bit definition for ADC_JOFR4 register *****************/
Kojto	115:87f2f5183dfb	1579	#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /!<Data offset for injected channel 4 /
Kojto	115:87f2f5183dfb	1580
Kojto	115:87f2f5183dfb	1581	/***************** Bit definition for ADC_HTR register ******************/
Kojto	115:87f2f5183dfb	1582	#define ADC_HTR_HT ((uint32_t)0x0FFF) /!<Analog watchdog high threshold /
Kojto	115:87f2f5183dfb	1583
Kojto	115:87f2f5183dfb	1584	/***************** Bit definition for ADC_LTR register ******************/
Kojto	115:87f2f5183dfb	1585	#define ADC_LTR_LT ((uint32_t)0x0FFF) /!<Analog watchdog low threshold /
Kojto	115:87f2f5183dfb	1586
Kojto	115:87f2f5183dfb	1587	/***************** Bit definition for ADC_SQR1 register *****************/
Kojto	115:87f2f5183dfb	1588	#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /!<SQ13[4:0] bits (13th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1589	#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1590	#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1591	#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1592	#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1593	#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1594	#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /!<SQ14[4:0] bits (14th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1595	#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1596	#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1597	#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1598	#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1599	#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1600	#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /!<SQ15[4:0] bits (15th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1601	#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1602	#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1603	#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1604	#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1605	#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1606	#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /!<SQ16[4:0] bits (16th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1607	#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1608	#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1609	#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1610	#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1611	#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1612	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!<L[3:0] bits (Regular channel sequence length) /
Kojto	115:87f2f5183dfb	1613	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1614	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1615	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1616	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1617
Kojto	115:87f2f5183dfb	1618	/***************** Bit definition for ADC_SQR2 register *****************/
Kojto	115:87f2f5183dfb	1619	#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /!<SQ7[4:0] bits (7th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1620	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1621	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1622	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1623	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1624	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1625	#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /!<SQ8[4:0] bits (8th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1626	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1627	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1628	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1629	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1630	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1631	#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /!<SQ9[4:0] bits (9th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1632	#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1633	#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1634	#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1635	#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1636	#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1637	#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /!<SQ10[4:0] bits (10th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1638	#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1639	#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1640	#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1641	#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1642	#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1643	#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /!<SQ11[4:0] bits (11th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1644	#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1645	#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1646	#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1647	#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1648	#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1649	#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /!<SQ12[4:0] bits (12th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1650	#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1651	#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1652	#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1653	#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1654	#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1655
Kojto	115:87f2f5183dfb	1656	/***************** Bit definition for ADC_SQR3 register *****************/
Kojto	115:87f2f5183dfb	1657	#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /!<SQ1[4:0] bits (1st conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1658	#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1659	#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1660	#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1661	#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1662	#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1663	#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /!<SQ2[4:0] bits (2nd conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1664	#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1665	#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1666	#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1667	#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1668	#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1669	#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /!<SQ3[4:0] bits (3rd conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1670	#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1671	#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1672	#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1673	#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1674	#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1675	#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /!<SQ4[4:0] bits (4th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1676	#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1677	#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1678	#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1679	#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1680	#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1681	#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /!<SQ5[4:0] bits (5th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1682	#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1683	#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1684	#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1685	#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1686	#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1687	#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /!<SQ6[4:0] bits (6th conversion in regular sequence) /
Kojto	115:87f2f5183dfb	1688	#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1689	#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1690	#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1691	#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1692	#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1693
Kojto	115:87f2f5183dfb	1694	/***************** Bit definition for ADC_JSQR register *****************/
Kojto	115:87f2f5183dfb	1695	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!<JSQ1[4:0] bits (1st conversion in injected sequence) /
Kojto	115:87f2f5183dfb	1696	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1697	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1698	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1699	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1700	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1701	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!<JSQ2[4:0] bits (2nd conversion in injected sequence) /
Kojto	115:87f2f5183dfb	1702	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1703	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1704	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1705	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1706	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1707	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!<JSQ3[4:0] bits (3rd conversion in injected sequence) /
Kojto	115:87f2f5183dfb	1708	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1709	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1710	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1711	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1712	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1713	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!<JSQ4[4:0] bits (4th conversion in injected sequence) /
Kojto	115:87f2f5183dfb	1714	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1715	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1716	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1717	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1718	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1719	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!<JL[1:0] bits (Injected Sequence length) /
Kojto	115:87f2f5183dfb	1720	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1721	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1722
Kojto	115:87f2f5183dfb	1723	/***************** Bit definition for ADC_JDR1 register *****************/
Kojto	115:87f2f5183dfb	1724	#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /!<Injected data /
Kojto	115:87f2f5183dfb	1725
Kojto	115:87f2f5183dfb	1726	/***************** Bit definition for ADC_JDR2 register *****************/
Kojto	115:87f2f5183dfb	1727	#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /!<Injected data /
Kojto	115:87f2f5183dfb	1728
Kojto	115:87f2f5183dfb	1729	/***************** Bit definition for ADC_JDR3 register *****************/
Kojto	115:87f2f5183dfb	1730	#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /!<Injected data /
Kojto	115:87f2f5183dfb	1731
Kojto	115:87f2f5183dfb	1732	/***************** Bit definition for ADC_JDR4 register *****************/
Kojto	115:87f2f5183dfb	1733	#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /!<Injected data /
Kojto	115:87f2f5183dfb	1734
Kojto	115:87f2f5183dfb	1735	/****************** Bit definition for ADC_DR register ******************/
Kojto	115:87f2f5183dfb	1736	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!<Regular data /
Kojto	115:87f2f5183dfb	1737	#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /!<ADC2 data /
Kojto	115:87f2f5183dfb	1738
Kojto	115:87f2f5183dfb	1739	/***************** Bit definition for ADC_CSR register ******************/
Kojto	115:87f2f5183dfb	1740	#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /!<ADC1 Analog watchdog flag /
Kojto	115:87f2f5183dfb	1741	#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /!<ADC1 End of conversion /
Kojto	115:87f2f5183dfb	1742	#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /!<ADC1 Injected channel end of conversion /
Kojto	115:87f2f5183dfb	1743	#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /!<ADC1 Injected channel Start flag /
Kojto	115:87f2f5183dfb	1744	#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /!<ADC1 Regular channel Start flag /
Kojto	115:87f2f5183dfb	1745	#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /!<ADC1 DMA overrun flag /
Kojto	115:87f2f5183dfb	1746	#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /!<ADC2 Analog watchdog flag /
Kojto	115:87f2f5183dfb	1747	#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /!<ADC2 End of conversion /
Kojto	115:87f2f5183dfb	1748	#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /!<ADC2 Injected channel end of conversion /
Kojto	115:87f2f5183dfb	1749	#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /!<ADC2 Injected channel Start flag /
Kojto	115:87f2f5183dfb	1750	#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /!<ADC2 Regular channel Start flag /
Kojto	115:87f2f5183dfb	1751	#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /!<ADC2 DMA overrun flag /
Kojto	115:87f2f5183dfb	1752	#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /!<ADC3 Analog watchdog flag /
Kojto	115:87f2f5183dfb	1753	#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /!<ADC3 End of conversion /
Kojto	115:87f2f5183dfb	1754	#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /!<ADC3 Injected channel end of conversion /
Kojto	115:87f2f5183dfb	1755	#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /!<ADC3 Injected channel Start flag /
Kojto	115:87f2f5183dfb	1756	#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /!<ADC3 Regular channel Start flag /
Kojto	115:87f2f5183dfb	1757	#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /!<ADC3 DMA overrun flag /
Kojto	115:87f2f5183dfb	1758
Kojto	115:87f2f5183dfb	1759	/***************** Bit definition for ADC_CCR register ******************/
Kojto	115:87f2f5183dfb	1760	#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /!<MULTI[4:0] bits (Multi-ADC mode selection) /
Kojto	115:87f2f5183dfb	1761	#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1762	#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1763	#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1764	#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1765	#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	1766	#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /!<DELAY[3:0] bits (Delay between 2 sampling phases) /
Kojto	115:87f2f5183dfb	1767	#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1768	#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1769	#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1770	#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1771	#define ADC_CCR_DDS ((uint32_t)0x00002000) /!<DMA disable selection (Multi-ADC mode) /
Kojto	115:87f2f5183dfb	1772	#define ADC_CCR_DMA ((uint32_t)0x0000C000) /!<DMA[1:0] bits (Direct Memory Access mode for multimode) /
Kojto	115:87f2f5183dfb	1773	#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1774	#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1775	#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /!<ADCPRE[1:0] bits (ADC prescaler) /
Kojto	115:87f2f5183dfb	1776	#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1777	#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1778	#define ADC_CCR_VBATE ((uint32_t)0x00400000) /!<VBAT Enable /
Kojto	115:87f2f5183dfb	1779	#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /!<Temperature Sensor and VREFINT Enable /
Kojto	115:87f2f5183dfb	1780
Kojto	115:87f2f5183dfb	1781	/***************** Bit definition for ADC_CDR register ******************/
Kojto	115:87f2f5183dfb	1782	#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /!<1st data of a pair of regular conversions /
Kojto	115:87f2f5183dfb	1783	#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /!<2nd data of a pair of regular conversions /
Kojto	115:87f2f5183dfb	1784
Kojto	115:87f2f5183dfb	1785	/******************************************************************************/
Kojto	115:87f2f5183dfb	1786	/* */
Kojto	115:87f2f5183dfb	1787	/* Controller Area Network */
Kojto	115:87f2f5183dfb	1788	/* */
Kojto	115:87f2f5183dfb	1789	/******************************************************************************/
Kojto	115:87f2f5183dfb	1790	/!<CAN control and status registers /
Kojto	115:87f2f5183dfb	1791	/***************** Bit definition for CAN_MCR register ******************/
Kojto	115:87f2f5183dfb	1792	#define CAN_MCR_INRQ ((uint32_t)0x00000001) /!<Initialization Request /
Kojto	115:87f2f5183dfb	1793	#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /!<Sleep Mode Request /
Kojto	115:87f2f5183dfb	1794	#define CAN_MCR_TXFP ((uint32_t)0x00000004) /!<Transmit FIFO Priority /
Kojto	115:87f2f5183dfb	1795	#define CAN_MCR_RFLM ((uint32_t)0x00000008) /!<Receive FIFO Locked Mode /
Kojto	115:87f2f5183dfb	1796	#define CAN_MCR_NART ((uint32_t)0x00000010) /!<No Automatic Retransmission /
Kojto	115:87f2f5183dfb	1797	#define CAN_MCR_AWUM ((uint32_t)0x00000020) /!<Automatic Wakeup Mode /
Kojto	115:87f2f5183dfb	1798	#define CAN_MCR_ABOM ((uint32_t)0x00000040) /!<Automatic Bus-Off Management /
Kojto	115:87f2f5183dfb	1799	#define CAN_MCR_TTCM ((uint32_t)0x00000080) /!<Time Triggered Communication Mode /
Kojto	115:87f2f5183dfb	1800	#define CAN_MCR_RESET ((uint32_t)0x00008000) /!<bxCAN software master reset /
Kojto	115:87f2f5183dfb	1801
Kojto	115:87f2f5183dfb	1802	/***************** Bit definition for CAN_MSR register ******************/
Kojto	115:87f2f5183dfb	1803	#define CAN_MSR_INAK ((uint32_t)0x00000001) /!<Initialization Acknowledge /
Kojto	115:87f2f5183dfb	1804	#define CAN_MSR_SLAK ((uint32_t)0x00000002) /!<Sleep Acknowledge /
Kojto	115:87f2f5183dfb	1805	#define CAN_MSR_ERRI ((uint32_t)0x00000004) /!<Error Interrupt /
Kojto	115:87f2f5183dfb	1806	#define CAN_MSR_WKUI ((uint32_t)0x00000008) /!<Wakeup Interrupt /
Kojto	115:87f2f5183dfb	1807	#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /!<Sleep Acknowledge Interrupt /
Kojto	115:87f2f5183dfb	1808	#define CAN_MSR_TXM ((uint32_t)0x00000100) /!<Transmit Mode /
Kojto	115:87f2f5183dfb	1809	#define CAN_MSR_RXM ((uint32_t)0x00000200) /!<Receive Mode /
Kojto	115:87f2f5183dfb	1810	#define CAN_MSR_SAMP ((uint32_t)0x00000400) /!<Last Sample Point /
Kojto	115:87f2f5183dfb	1811	#define CAN_MSR_RX ((uint32_t)0x00000800) /!<CAN Rx Signal /
Kojto	115:87f2f5183dfb	1812
Kojto	115:87f2f5183dfb	1813	/***************** Bit definition for CAN_TSR register ******************/
Kojto	115:87f2f5183dfb	1814	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!<Request Completed Mailbox0 /
Kojto	115:87f2f5183dfb	1815	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!<Transmission OK of Mailbox0 /
Kojto	115:87f2f5183dfb	1816	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!<Arbitration Lost for Mailbox0 /
Kojto	115:87f2f5183dfb	1817	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!<Transmission Error of Mailbox0 /
Kojto	115:87f2f5183dfb	1818	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!<Abort Request for Mailbox0 /
Kojto	115:87f2f5183dfb	1819	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!<Request Completed Mailbox1 /
Kojto	115:87f2f5183dfb	1820	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!<Transmission OK of Mailbox1 /
Kojto	115:87f2f5183dfb	1821	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!<Arbitration Lost for Mailbox1 /
Kojto	115:87f2f5183dfb	1822	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!<Transmission Error of Mailbox1 /
Kojto	115:87f2f5183dfb	1823	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!<Abort Request for Mailbox 1 /
Kojto	115:87f2f5183dfb	1824	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!<Request Completed Mailbox2 /
Kojto	115:87f2f5183dfb	1825	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!<Transmission OK of Mailbox 2 /
Kojto	115:87f2f5183dfb	1826	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!<Arbitration Lost for mailbox 2 /
Kojto	115:87f2f5183dfb	1827	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!<Transmission Error of Mailbox 2 /
Kojto	115:87f2f5183dfb	1828	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!<Abort Request for Mailbox 2 /
Kojto	115:87f2f5183dfb	1829	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!<Mailbox Code /
Kojto	115:87f2f5183dfb	1830
Kojto	115:87f2f5183dfb	1831	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!<TME[2:0] bits /
Kojto	115:87f2f5183dfb	1832	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!<Transmit Mailbox 0 Empty /
Kojto	115:87f2f5183dfb	1833	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!<Transmit Mailbox 1 Empty /
Kojto	115:87f2f5183dfb	1834	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!<Transmit Mailbox 2 Empty /
Kojto	115:87f2f5183dfb	1835
Kojto	115:87f2f5183dfb	1836	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!<LOW[2:0] bits /
Kojto	115:87f2f5183dfb	1837	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!<Lowest Priority Flag for Mailbox 0 /
Kojto	115:87f2f5183dfb	1838	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!<Lowest Priority Flag for Mailbox 1 /
Kojto	115:87f2f5183dfb	1839	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!<Lowest Priority Flag for Mailbox 2 /
Kojto	115:87f2f5183dfb	1840
Kojto	115:87f2f5183dfb	1841	/***************** Bit definition for CAN_RF0R register *****************/
Kojto	115:87f2f5183dfb	1842	#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /!<FIFO 0 Message Pending /
Kojto	115:87f2f5183dfb	1843	#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /!<FIFO 0 Full /
Kojto	115:87f2f5183dfb	1844	#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /!<FIFO 0 Overrun /
Kojto	115:87f2f5183dfb	1845	#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /!<Release FIFO 0 Output Mailbox /
Kojto	115:87f2f5183dfb	1846
Kojto	115:87f2f5183dfb	1847	/***************** Bit definition for CAN_RF1R register *****************/
Kojto	115:87f2f5183dfb	1848	#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /!<FIFO 1 Message Pending /
Kojto	115:87f2f5183dfb	1849	#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /!<FIFO 1 Full /
Kojto	115:87f2f5183dfb	1850	#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /!<FIFO 1 Overrun /
Kojto	115:87f2f5183dfb	1851	#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /!<Release FIFO 1 Output Mailbox /
Kojto	115:87f2f5183dfb	1852
Kojto	115:87f2f5183dfb	1853	/****************** Bit definition for CAN_IER register *****************/
Kojto	115:87f2f5183dfb	1854	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!<Transmit Mailbox Empty Interrupt Enable /
Kojto	115:87f2f5183dfb	1855	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!<FIFO Message Pending Interrupt Enable /
Kojto	115:87f2f5183dfb	1856	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!<FIFO Full Interrupt Enable /
Kojto	115:87f2f5183dfb	1857	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!<FIFO Overrun Interrupt Enable /
Kojto	115:87f2f5183dfb	1858	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!<FIFO Message Pending Interrupt Enable /
Kojto	115:87f2f5183dfb	1859	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!<FIFO Full Interrupt Enable /
Kojto	115:87f2f5183dfb	1860	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!<FIFO Overrun Interrupt Enable /
Kojto	115:87f2f5183dfb	1861	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!<Error Warning Interrupt Enable /
Kojto	115:87f2f5183dfb	1862	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!<Error Passive Interrupt Enable /
Kojto	115:87f2f5183dfb	1863	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!<Bus-Off Interrupt Enable /
Kojto	115:87f2f5183dfb	1864	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!<Last Error Code Interrupt Enable /
Kojto	115:87f2f5183dfb	1865	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!<Error Interrupt Enable /
Kojto	115:87f2f5183dfb	1866	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!<Wakeup Interrupt Enable /
Kojto	115:87f2f5183dfb	1867	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!<Sleep Interrupt Enable /
Kojto	115:87f2f5183dfb	1868
Kojto	115:87f2f5183dfb	1869	/****************** Bit definition for CAN_ESR register *****************/
Kojto	115:87f2f5183dfb	1870	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!<Error Warning Flag /
Kojto	115:87f2f5183dfb	1871	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!<Error Passive Flag /
Kojto	115:87f2f5183dfb	1872	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!<Bus-Off Flag /
Kojto	115:87f2f5183dfb	1873
Kojto	115:87f2f5183dfb	1874	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!<LEC[2:0] bits (Last Error Code) /
Kojto	115:87f2f5183dfb	1875	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1876	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1877	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1878
Kojto	115:87f2f5183dfb	1879	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!<Least significant byte of the 9-bit Transmit Error Counter /
Kojto	115:87f2f5183dfb	1880	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!<Receive Error Counter /
Kojto	115:87f2f5183dfb	1881
Kojto	115:87f2f5183dfb	1882	/***************** Bit definition for CAN_BTR register ******************/
Kojto	115:87f2f5183dfb	1883	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
Kojto	115:87f2f5183dfb	1884	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
Kojto	115:87f2f5183dfb	1885	#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1886	#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1887	#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1888	#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	1889	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
Kojto	115:87f2f5183dfb	1890	#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1891	#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1892	#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	1893	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
Kojto	115:87f2f5183dfb	1894	#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	1895	#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	1896	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
Kojto	115:87f2f5183dfb	1897	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
Kojto	115:87f2f5183dfb	1898
Kojto	115:87f2f5183dfb	1899	/!<Mailbox registers /
Kojto	115:87f2f5183dfb	1900	/**************** Bit definition for CAN_TI0R register ******************/
Kojto	115:87f2f5183dfb	1901	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
Kojto	115:87f2f5183dfb	1902	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
Kojto	115:87f2f5183dfb	1903	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
Kojto	115:87f2f5183dfb	1904	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
Kojto	115:87f2f5183dfb	1905	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
Kojto	115:87f2f5183dfb	1906
Kojto	115:87f2f5183dfb	1907	/**************** Bit definition for CAN_TDT0R register *****************/
Kojto	115:87f2f5183dfb	1908	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
Kojto	115:87f2f5183dfb	1909	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
Kojto	115:87f2f5183dfb	1910	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
Kojto	115:87f2f5183dfb	1911
Kojto	115:87f2f5183dfb	1912	/**************** Bit definition for CAN_TDL0R register *****************/
Kojto	115:87f2f5183dfb	1913	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
Kojto	115:87f2f5183dfb	1914	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
Kojto	115:87f2f5183dfb	1915	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
Kojto	115:87f2f5183dfb	1916	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
Kojto	115:87f2f5183dfb	1917
Kojto	115:87f2f5183dfb	1918	/**************** Bit definition for CAN_TDH0R register *****************/
Kojto	115:87f2f5183dfb	1919	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
Kojto	115:87f2f5183dfb	1920	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
Kojto	115:87f2f5183dfb	1921	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
Kojto	115:87f2f5183dfb	1922	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
Kojto	115:87f2f5183dfb	1923
Kojto	115:87f2f5183dfb	1924	/***************** Bit definition for CAN_TI1R register *****************/
Kojto	115:87f2f5183dfb	1925	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
Kojto	115:87f2f5183dfb	1926	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
Kojto	115:87f2f5183dfb	1927	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
Kojto	115:87f2f5183dfb	1928	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
Kojto	115:87f2f5183dfb	1929	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
Kojto	115:87f2f5183dfb	1930
Kojto	115:87f2f5183dfb	1931	/***************** Bit definition for CAN_TDT1R register ****************/
Kojto	115:87f2f5183dfb	1932	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
Kojto	115:87f2f5183dfb	1933	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
Kojto	115:87f2f5183dfb	1934	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
Kojto	115:87f2f5183dfb	1935
Kojto	115:87f2f5183dfb	1936	/***************** Bit definition for CAN_TDL1R register ****************/
Kojto	115:87f2f5183dfb	1937	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
Kojto	115:87f2f5183dfb	1938	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
Kojto	115:87f2f5183dfb	1939	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
Kojto	115:87f2f5183dfb	1940	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
Kojto	115:87f2f5183dfb	1941
Kojto	115:87f2f5183dfb	1942	/***************** Bit definition for CAN_TDH1R register ****************/
Kojto	115:87f2f5183dfb	1943	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
Kojto	115:87f2f5183dfb	1944	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
Kojto	115:87f2f5183dfb	1945	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
Kojto	115:87f2f5183dfb	1946	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
Kojto	115:87f2f5183dfb	1947
Kojto	115:87f2f5183dfb	1948	/***************** Bit definition for CAN_TI2R register *****************/
Kojto	115:87f2f5183dfb	1949	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
Kojto	115:87f2f5183dfb	1950	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
Kojto	115:87f2f5183dfb	1951	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
Kojto	115:87f2f5183dfb	1952	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
Kojto	115:87f2f5183dfb	1953	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
Kojto	115:87f2f5183dfb	1954
Kojto	115:87f2f5183dfb	1955	/***************** Bit definition for CAN_TDT2R register ****************/
Kojto	115:87f2f5183dfb	1956	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
Kojto	115:87f2f5183dfb	1957	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
Kojto	115:87f2f5183dfb	1958	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
Kojto	115:87f2f5183dfb	1959
Kojto	115:87f2f5183dfb	1960	/***************** Bit definition for CAN_TDL2R register ****************/
Kojto	115:87f2f5183dfb	1961	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
Kojto	115:87f2f5183dfb	1962	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
Kojto	115:87f2f5183dfb	1963	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
Kojto	115:87f2f5183dfb	1964	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
Kojto	115:87f2f5183dfb	1965
Kojto	115:87f2f5183dfb	1966	/***************** Bit definition for CAN_TDH2R register ****************/
Kojto	115:87f2f5183dfb	1967	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
Kojto	115:87f2f5183dfb	1968	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
Kojto	115:87f2f5183dfb	1969	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
Kojto	115:87f2f5183dfb	1970	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
Kojto	115:87f2f5183dfb	1971
Kojto	115:87f2f5183dfb	1972	/***************** Bit definition for CAN_RI0R register *****************/
Kojto	115:87f2f5183dfb	1973	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
Kojto	115:87f2f5183dfb	1974	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
Kojto	115:87f2f5183dfb	1975	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
Kojto	115:87f2f5183dfb	1976	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
Kojto	115:87f2f5183dfb	1977
Kojto	115:87f2f5183dfb	1978	/***************** Bit definition for CAN_RDT0R register ****************/
Kojto	115:87f2f5183dfb	1979	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
Kojto	115:87f2f5183dfb	1980	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
Kojto	115:87f2f5183dfb	1981	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
Kojto	115:87f2f5183dfb	1982
Kojto	115:87f2f5183dfb	1983	/***************** Bit definition for CAN_RDL0R register ****************/
Kojto	115:87f2f5183dfb	1984	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
Kojto	115:87f2f5183dfb	1985	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
Kojto	115:87f2f5183dfb	1986	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
Kojto	115:87f2f5183dfb	1987	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
Kojto	115:87f2f5183dfb	1988
Kojto	115:87f2f5183dfb	1989	/***************** Bit definition for CAN_RDH0R register ****************/
Kojto	115:87f2f5183dfb	1990	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
Kojto	115:87f2f5183dfb	1991	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
Kojto	115:87f2f5183dfb	1992	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
Kojto	115:87f2f5183dfb	1993	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
Kojto	115:87f2f5183dfb	1994
Kojto	115:87f2f5183dfb	1995	/***************** Bit definition for CAN_RI1R register *****************/
Kojto	115:87f2f5183dfb	1996	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
Kojto	115:87f2f5183dfb	1997	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
Kojto	115:87f2f5183dfb	1998	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
Kojto	115:87f2f5183dfb	1999	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
Kojto	115:87f2f5183dfb	2000
Kojto	115:87f2f5183dfb	2001	/***************** Bit definition for CAN_RDT1R register ****************/
Kojto	115:87f2f5183dfb	2002	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
Kojto	115:87f2f5183dfb	2003	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
Kojto	115:87f2f5183dfb	2004	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
Kojto	115:87f2f5183dfb	2005
Kojto	115:87f2f5183dfb	2006	/***************** Bit definition for CAN_RDL1R register ****************/
Kojto	115:87f2f5183dfb	2007	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
Kojto	115:87f2f5183dfb	2008	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
Kojto	115:87f2f5183dfb	2009	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
Kojto	115:87f2f5183dfb	2010	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
Kojto	115:87f2f5183dfb	2011
Kojto	115:87f2f5183dfb	2012	/***************** Bit definition for CAN_RDH1R register ****************/
Kojto	115:87f2f5183dfb	2013	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
Kojto	115:87f2f5183dfb	2014	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
Kojto	115:87f2f5183dfb	2015	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
Kojto	115:87f2f5183dfb	2016	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
Kojto	115:87f2f5183dfb	2017
Kojto	115:87f2f5183dfb	2018	/!<CAN filter registers /
Kojto	115:87f2f5183dfb	2019	/***************** Bit definition for CAN_FMR register ******************/
Kojto	115:87f2f5183dfb	2020	#define CAN_FMR_FINIT ((uint8_t)0x01) /!<Filter Init Mode /
Kojto	115:87f2f5183dfb	2021	#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /!<CAN2 start bank /
Kojto	115:87f2f5183dfb	2022
Kojto	115:87f2f5183dfb	2023	/***************** Bit definition for CAN_FM1R register *****************/
Kojto	115:87f2f5183dfb	2024	#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /!<Filter Mode /
Kojto	115:87f2f5183dfb	2025	#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /!<Filter Init Mode bit 0 /
Kojto	115:87f2f5183dfb	2026	#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /!<Filter Init Mode bit 1 /
Kojto	115:87f2f5183dfb	2027	#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /!<Filter Init Mode bit 2 /
Kojto	115:87f2f5183dfb	2028	#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /!<Filter Init Mode bit 3 /
Kojto	115:87f2f5183dfb	2029	#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /!<Filter Init Mode bit 4 /
Kojto	115:87f2f5183dfb	2030	#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /!<Filter Init Mode bit 5 /
Kojto	115:87f2f5183dfb	2031	#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /!<Filter Init Mode bit 6 /
Kojto	115:87f2f5183dfb	2032	#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /!<Filter Init Mode bit 7 /
Kojto	115:87f2f5183dfb	2033	#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /!<Filter Init Mode bit 8 /
Kojto	115:87f2f5183dfb	2034	#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /!<Filter Init Mode bit 9 /
Kojto	115:87f2f5183dfb	2035	#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /!<Filter Init Mode bit 10 /
Kojto	115:87f2f5183dfb	2036	#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /!<Filter Init Mode bit 11 /
Kojto	115:87f2f5183dfb	2037	#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /!<Filter Init Mode bit 12 /
Kojto	115:87f2f5183dfb	2038	#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /!<Filter Init Mode bit 13 /
Kojto	115:87f2f5183dfb	2039
Kojto	115:87f2f5183dfb	2040	/***************** Bit definition for CAN_FS1R register *****************/
Kojto	115:87f2f5183dfb	2041	#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /!<Filter Scale Configuration /
Kojto	115:87f2f5183dfb	2042	#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /!<Filter Scale Configuration bit 0 /
Kojto	115:87f2f5183dfb	2043	#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /!<Filter Scale Configuration bit 1 /
Kojto	115:87f2f5183dfb	2044	#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /!<Filter Scale Configuration bit 2 /
Kojto	115:87f2f5183dfb	2045	#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /!<Filter Scale Configuration bit 3 /
Kojto	115:87f2f5183dfb	2046	#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /!<Filter Scale Configuration bit 4 /
Kojto	115:87f2f5183dfb	2047	#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /!<Filter Scale Configuration bit 5 /
Kojto	115:87f2f5183dfb	2048	#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /!<Filter Scale Configuration bit 6 /
Kojto	115:87f2f5183dfb	2049	#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /!<Filter Scale Configuration bit 7 /
Kojto	115:87f2f5183dfb	2050	#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /!<Filter Scale Configuration bit 8 /
Kojto	115:87f2f5183dfb	2051	#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /!<Filter Scale Configuration bit 9 /
Kojto	115:87f2f5183dfb	2052	#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /!<Filter Scale Configuration bit 10 /
Kojto	115:87f2f5183dfb	2053	#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /!<Filter Scale Configuration bit 11 /
Kojto	115:87f2f5183dfb	2054	#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /!<Filter Scale Configuration bit 12 /
Kojto	115:87f2f5183dfb	2055	#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /!<Filter Scale Configuration bit 13 /
Kojto	115:87f2f5183dfb	2056
Kojto	115:87f2f5183dfb	2057	/**************** Bit definition for CAN_FFA1R register *****************/
Kojto	115:87f2f5183dfb	2058	#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /!<Filter FIFO Assignment /
Kojto	115:87f2f5183dfb	2059	#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /!<Filter FIFO Assignment for Filter 0 /
Kojto	115:87f2f5183dfb	2060	#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /!<Filter FIFO Assignment for Filter 1 /
Kojto	115:87f2f5183dfb	2061	#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /!<Filter FIFO Assignment for Filter 2 /
Kojto	115:87f2f5183dfb	2062	#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /!<Filter FIFO Assignment for Filter 3 /
Kojto	115:87f2f5183dfb	2063	#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /!<Filter FIFO Assignment for Filter 4 /
Kojto	115:87f2f5183dfb	2064	#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /!<Filter FIFO Assignment for Filter 5 /
Kojto	115:87f2f5183dfb	2065	#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /!<Filter FIFO Assignment for Filter 6 /
Kojto	115:87f2f5183dfb	2066	#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /!<Filter FIFO Assignment for Filter 7 /
Kojto	115:87f2f5183dfb	2067	#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /!<Filter FIFO Assignment for Filter 8 /
Kojto	115:87f2f5183dfb	2068	#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /!<Filter FIFO Assignment for Filter 9 /
Kojto	115:87f2f5183dfb	2069	#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /!<Filter FIFO Assignment for Filter 10 /
Kojto	115:87f2f5183dfb	2070	#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /!<Filter FIFO Assignment for Filter 11 /
Kojto	115:87f2f5183dfb	2071	#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /!<Filter FIFO Assignment for Filter 12 /
Kojto	115:87f2f5183dfb	2072	#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /!<Filter FIFO Assignment for Filter 13 /
Kojto	115:87f2f5183dfb	2073
Kojto	115:87f2f5183dfb	2074	/***************** Bit definition for CAN_FA1R register *****************/
Kojto	115:87f2f5183dfb	2075	#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /!<Filter Active /
Kojto	115:87f2f5183dfb	2076	#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /!<Filter 0 Active /
Kojto	115:87f2f5183dfb	2077	#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /!<Filter 1 Active /
Kojto	115:87f2f5183dfb	2078	#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /!<Filter 2 Active /
Kojto	115:87f2f5183dfb	2079	#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /!<Filter 3 Active /
Kojto	115:87f2f5183dfb	2080	#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /!<Filter 4 Active /
Kojto	115:87f2f5183dfb	2081	#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /!<Filter 5 Active /
Kojto	115:87f2f5183dfb	2082	#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /!<Filter 6 Active /
Kojto	115:87f2f5183dfb	2083	#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /!<Filter 7 Active /
Kojto	115:87f2f5183dfb	2084	#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /!<Filter 8 Active /
Kojto	115:87f2f5183dfb	2085	#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /!<Filter 9 Active /
Kojto	115:87f2f5183dfb	2086	#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /!<Filter 10 Active /
Kojto	115:87f2f5183dfb	2087	#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /!<Filter 11 Active /
Kojto	115:87f2f5183dfb	2088	#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /!<Filter 12 Active /
Kojto	115:87f2f5183dfb	2089	#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /!<Filter 13 Active /
Kojto	115:87f2f5183dfb	2090
Kojto	115:87f2f5183dfb	2091	/***************** Bit definition for CAN_F0R1 register *****************/
Kojto	115:87f2f5183dfb	2092	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2093	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2094	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2095	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2096	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2097	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2098	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2099	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2100	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2101	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2102	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2103	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2104	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2105	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2106	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2107	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2108	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2109	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2110	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2111	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2112	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2113	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2114	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2115	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2116	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2117	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2118	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2119	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2120	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2121	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2122	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2123	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2124
Kojto	115:87f2f5183dfb	2125	/***************** Bit definition for CAN_F1R1 register *****************/
Kojto	115:87f2f5183dfb	2126	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2127	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2128	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2129	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2130	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2131	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2132	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2133	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2134	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2135	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2136	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2137	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2138	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2139	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2140	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2141	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2142	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2143	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2144	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2145	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2146	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2147	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2148	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2149	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2150	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2151	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2152	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2153	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2154	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2155	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2156	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2157	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2158
Kojto	115:87f2f5183dfb	2159	/***************** Bit definition for CAN_F2R1 register *****************/
Kojto	115:87f2f5183dfb	2160	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2161	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2162	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2163	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2164	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2165	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2166	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2167	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2168	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2169	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2170	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2171	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2172	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2173	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2174	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2175	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2176	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2177	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2178	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2179	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2180	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2181	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2182	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2183	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2184	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2185	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2186	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2187	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2188	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2189	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2190	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2191	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2192
Kojto	115:87f2f5183dfb	2193	/***************** Bit definition for CAN_F3R1 register *****************/
Kojto	115:87f2f5183dfb	2194	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2195	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2196	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2197	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2198	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2199	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2200	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2201	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2202	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2203	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2204	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2205	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2206	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2207	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2208	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2209	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2210	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2211	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2212	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2213	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2214	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2215	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2216	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2217	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2218	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2219	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2220	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2221	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2222	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2223	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2224	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2225	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2226
Kojto	115:87f2f5183dfb	2227	/***************** Bit definition for CAN_F4R1 register *****************/
Kojto	115:87f2f5183dfb	2228	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2229	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2230	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2231	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2232	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2233	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2234	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2235	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2236	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2237	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2238	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2239	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2240	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2241	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2242	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2243	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2244	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2245	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2246	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2247	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2248	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2249	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2250	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2251	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2252	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2253	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2254	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2255	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2256	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2257	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2258	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2259	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2260
Kojto	115:87f2f5183dfb	2261	/***************** Bit definition for CAN_F5R1 register *****************/
Kojto	115:87f2f5183dfb	2262	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2263	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2264	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2265	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2266	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2267	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2268	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2269	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2270	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2271	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2272	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2273	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2274	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2275	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2276	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2277	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2278	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2279	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2280	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2281	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2282	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2283	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2284	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2285	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2286	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2287	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2288	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2289	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2290	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2291	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2292	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2293	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2294
Kojto	115:87f2f5183dfb	2295	/***************** Bit definition for CAN_F6R1 register *****************/
Kojto	115:87f2f5183dfb	2296	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2297	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2298	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2299	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2300	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2301	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2302	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2303	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2304	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2305	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2306	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2307	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2308	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2309	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2310	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2311	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2312	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2313	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2314	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2315	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2316	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2317	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2318	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2319	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2320	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2321	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2322	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2323	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2324	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2325	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2326	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2327	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2328
Kojto	115:87f2f5183dfb	2329	/***************** Bit definition for CAN_F7R1 register *****************/
Kojto	115:87f2f5183dfb	2330	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2331	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2332	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2333	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2334	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2335	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2336	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2337	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2338	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2339	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2340	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2341	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2342	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2343	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2344	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2345	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2346	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2347	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2348	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2349	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2350	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2351	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2352	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2353	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2354	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2355	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2356	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2357	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2358	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2359	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2360	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2361	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2362
Kojto	115:87f2f5183dfb	2363	/***************** Bit definition for CAN_F8R1 register *****************/
Kojto	115:87f2f5183dfb	2364	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2365	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2366	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2367	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2368	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2369	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2370	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2371	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2372	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2373	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2374	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2375	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2376	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2377	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2378	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2379	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2380	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2381	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2382	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2383	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2384	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2385	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2386	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2387	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2388	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2389	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2390	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2391	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2392	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2393	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2394	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2395	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2396
Kojto	115:87f2f5183dfb	2397	/***************** Bit definition for CAN_F9R1 register *****************/
Kojto	115:87f2f5183dfb	2398	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2399	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2400	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2401	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2402	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2403	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2404	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2405	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2406	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2407	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2408	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2409	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2410	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2411	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2412	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2413	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2414	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2415	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2416	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2417	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2418	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2419	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2420	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2421	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2422	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2423	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2424	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2425	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2426	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2427	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2428	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2429	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2430
Kojto	115:87f2f5183dfb	2431	/***************** Bit definition for CAN_F10R1 register ****************/
Kojto	115:87f2f5183dfb	2432	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2433	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2434	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2435	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2436	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2437	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2438	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2439	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2440	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2441	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2442	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2443	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2444	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2445	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2446	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2447	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2448	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2449	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2450	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2451	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2452	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2453	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2454	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2455	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2456	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2457	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2458	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2459	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2460	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2461	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2462	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2463	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2464
Kojto	115:87f2f5183dfb	2465	/***************** Bit definition for CAN_F11R1 register ****************/
Kojto	115:87f2f5183dfb	2466	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2467	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2468	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2469	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2470	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2471	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2472	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2473	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2474	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2475	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2476	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2477	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2478	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2479	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2480	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2481	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2482	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2483	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2484	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2485	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2486	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2487	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2488	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2489	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2490	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2491	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2492	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2493	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2494	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2495	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2496	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2497	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2498
Kojto	115:87f2f5183dfb	2499	/***************** Bit definition for CAN_F12R1 register ****************/
Kojto	115:87f2f5183dfb	2500	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2501	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2502	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2503	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2504	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2505	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2506	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2507	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2508	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2509	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2510	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2511	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2512	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2513	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2514	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2515	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2516	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2517	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2518	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2519	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2520	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2521	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2522	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2523	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2524	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2525	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2526	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2527	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2528	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2529	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2530	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2531	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2532
Kojto	115:87f2f5183dfb	2533	/***************** Bit definition for CAN_F13R1 register ****************/
Kojto	115:87f2f5183dfb	2534	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2535	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2536	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2537	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2538	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2539	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2540	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2541	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2542	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2543	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2544	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2545	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2546	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2547	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2548	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2549	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2550	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2551	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2552	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2553	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2554	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2555	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2556	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2557	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2558	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2559	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2560	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2561	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2562	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2563	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2564	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2565	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2566
Kojto	115:87f2f5183dfb	2567	/***************** Bit definition for CAN_F0R2 register *****************/
Kojto	115:87f2f5183dfb	2568	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2569	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2570	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2571	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2572	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2573	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2574	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2575	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2576	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2577	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2578	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2579	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2580	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2581	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2582	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2583	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2584	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2585	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2586	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2587	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2588	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2589	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2590	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2591	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2592	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2593	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2594	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2595	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2596	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2597	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2598	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2599	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2600
Kojto	115:87f2f5183dfb	2601	/***************** Bit definition for CAN_F1R2 register *****************/
Kojto	115:87f2f5183dfb	2602	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2603	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2604	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2605	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2606	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2607	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2608	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2609	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2610	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2611	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2612	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2613	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2614	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2615	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2616	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2617	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2618	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2619	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2620	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2621	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2622	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2623	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2624	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2625	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2626	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2627	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2628	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2629	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2630	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2631	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2632	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2633	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2634
Kojto	115:87f2f5183dfb	2635	/***************** Bit definition for CAN_F2R2 register *****************/
Kojto	115:87f2f5183dfb	2636	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2637	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2638	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2639	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2640	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2641	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2642	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2643	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2644	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2645	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2646	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2647	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2648	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2649	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2650	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2651	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2652	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2653	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2654	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2655	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2656	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2657	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2658	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2659	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2660	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2661	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2662	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2663	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2664	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2665	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2666	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2667	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2668
Kojto	115:87f2f5183dfb	2669	/***************** Bit definition for CAN_F3R2 register *****************/
Kojto	115:87f2f5183dfb	2670	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2671	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2672	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2673	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2674	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2675	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2676	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2677	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2678	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2679	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2680	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2681	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2682	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2683	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2684	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2685	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2686	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2687	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2688	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2689	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2690	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2691	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2692	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2693	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2694	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2695	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2696	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2697	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2698	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2699	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2700	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2701	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2702
Kojto	115:87f2f5183dfb	2703	/***************** Bit definition for CAN_F4R2 register *****************/
Kojto	115:87f2f5183dfb	2704	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2705	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2706	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2707	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2708	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2709	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2710	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2711	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2712	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2713	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2714	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2715	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2716	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2717	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2718	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2719	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2720	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2721	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2722	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2723	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2724	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2725	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2726	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2727	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2728	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2729	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2730	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2731	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2732	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2733	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2734	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2735	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2736
Kojto	115:87f2f5183dfb	2737	/***************** Bit definition for CAN_F5R2 register *****************/
Kojto	115:87f2f5183dfb	2738	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2739	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2740	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2741	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2742	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2743	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2744	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2745	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2746	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2747	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2748	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2749	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2750	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2751	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2752	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2753	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2754	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2755	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2756	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2757	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2758	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2759	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2760	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2761	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2762	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2763	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2764	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2765	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2766	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2767	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2768	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2769	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2770
Kojto	115:87f2f5183dfb	2771	/***************** Bit definition for CAN_F6R2 register *****************/
Kojto	115:87f2f5183dfb	2772	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2773	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2774	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2775	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2776	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2777	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2778	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2779	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2780	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2781	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2782	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2783	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2784	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2785	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2786	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2787	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2788	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2789	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2790	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2791	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2792	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2793	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2794	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2795	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2796	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2797	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2798	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2799	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2800	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2801	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2802	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2803	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2804
Kojto	115:87f2f5183dfb	2805	/***************** Bit definition for CAN_F7R2 register *****************/
Kojto	115:87f2f5183dfb	2806	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2807	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2808	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2809	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2810	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2811	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2812	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2813	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2814	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2815	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2816	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2817	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2818	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2819	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2820	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2821	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2822	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2823	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2824	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2825	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2826	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2827	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2828	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2829	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2830	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2831	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2832	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2833	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2834	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2835	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2836	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2837	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2838
Kojto	115:87f2f5183dfb	2839	/***************** Bit definition for CAN_F8R2 register *****************/
Kojto	115:87f2f5183dfb	2840	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2841	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2842	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2843	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2844	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2845	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2846	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2847	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2848	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2849	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2850	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2851	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2852	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2853	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2854	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2855	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2856	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2857	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2858	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2859	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2860	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2861	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2862	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2863	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2864	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2865	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2866	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2867	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2868	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2869	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2870	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2871	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2872
Kojto	115:87f2f5183dfb	2873	/***************** Bit definition for CAN_F9R2 register *****************/
Kojto	115:87f2f5183dfb	2874	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2875	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2876	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2877	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2878	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2879	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2880	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2881	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2882	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2883	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2884	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2885	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2886	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2887	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2888	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2889	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2890	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2891	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2892	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2893	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2894	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2895	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2896	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2897	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2898	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2899	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2900	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2901	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2902	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2903	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2904	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2905	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2906
Kojto	115:87f2f5183dfb	2907	/***************** Bit definition for CAN_F10R2 register ****************/
Kojto	115:87f2f5183dfb	2908	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2909	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2910	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2911	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2912	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2913	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2914	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2915	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2916	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2917	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2918	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2919	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2920	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2921	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2922	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2923	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2924	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2925	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2926	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2927	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2928	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2929	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2930	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2931	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2932	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2933	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2934	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2935	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2936	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2937	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2938	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2939	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2940
Kojto	115:87f2f5183dfb	2941	/***************** Bit definition for CAN_F11R2 register ****************/
Kojto	115:87f2f5183dfb	2942	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2943	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2944	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2945	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2946	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2947	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2948	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2949	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2950	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2951	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2952	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2953	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2954	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2955	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2956	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2957	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2958	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2959	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2960	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2961	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2962	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2963	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2964	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2965	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	2966	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	2967	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	2968	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	2969	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	2970	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	2971	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	2972	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	2973	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	2974
Kojto	115:87f2f5183dfb	2975	/***************** Bit definition for CAN_F12R2 register ****************/
Kojto	115:87f2f5183dfb	2976	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	2977	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	2978	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	2979	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	2980	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	2981	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	2982	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	2983	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	2984	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	2985	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	2986	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	2987	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	2988	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	2989	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	2990	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	2991	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	2992	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	2993	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	2994	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	2995	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	2996	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	2997	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	2998	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	2999	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	3000	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	3001	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	3002	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	3003	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	3004	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	3005	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	3006	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	3007	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	3008
Kojto	115:87f2f5183dfb	3009	/***************** Bit definition for CAN_F13R2 register ****************/
Kojto	115:87f2f5183dfb	3010	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
Kojto	115:87f2f5183dfb	3011	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
Kojto	115:87f2f5183dfb	3012	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
Kojto	115:87f2f5183dfb	3013	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
Kojto	115:87f2f5183dfb	3014	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
Kojto	115:87f2f5183dfb	3015	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
Kojto	115:87f2f5183dfb	3016	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
Kojto	115:87f2f5183dfb	3017	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
Kojto	115:87f2f5183dfb	3018	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
Kojto	115:87f2f5183dfb	3019	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
Kojto	115:87f2f5183dfb	3020	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
Kojto	115:87f2f5183dfb	3021	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
Kojto	115:87f2f5183dfb	3022	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
Kojto	115:87f2f5183dfb	3023	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
Kojto	115:87f2f5183dfb	3024	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
Kojto	115:87f2f5183dfb	3025	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
Kojto	115:87f2f5183dfb	3026	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
Kojto	115:87f2f5183dfb	3027	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
Kojto	115:87f2f5183dfb	3028	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
Kojto	115:87f2f5183dfb	3029	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
Kojto	115:87f2f5183dfb	3030	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
Kojto	115:87f2f5183dfb	3031	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
Kojto	115:87f2f5183dfb	3032	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
Kojto	115:87f2f5183dfb	3033	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
Kojto	115:87f2f5183dfb	3034	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
Kojto	115:87f2f5183dfb	3035	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
Kojto	115:87f2f5183dfb	3036	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
Kojto	115:87f2f5183dfb	3037	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
Kojto	115:87f2f5183dfb	3038	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
Kojto	115:87f2f5183dfb	3039	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
Kojto	115:87f2f5183dfb	3040	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
Kojto	115:87f2f5183dfb	3041	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
Kojto	115:87f2f5183dfb	3042
Kojto	115:87f2f5183dfb	3043	/******************************************************************************/
Kojto	115:87f2f5183dfb	3044	/* */
Kojto	115:87f2f5183dfb	3045	/* HDMI-CEC (CEC) */
Kojto	115:87f2f5183dfb	3046	/* */
Kojto	115:87f2f5183dfb	3047	/******************************************************************************/
Kojto	115:87f2f5183dfb	3048
Kojto	115:87f2f5183dfb	3049	/***************** Bit definition for CEC_CR register *******************/
Kojto	115:87f2f5183dfb	3050	#define CEC_CR_CECEN ((uint32_t)0x00000001) /!< CEC Enable /
Kojto	115:87f2f5183dfb	3051	#define CEC_CR_TXSOM ((uint32_t)0x00000002) /!< CEC Tx Start Of Message /
Kojto	115:87f2f5183dfb	3052	#define CEC_CR_TXEOM ((uint32_t)0x00000004) /!< CEC Tx End Of Message /
Kojto	115:87f2f5183dfb	3053
Kojto	115:87f2f5183dfb	3054	/***************** Bit definition for CEC_CFGR register *****************/
Kojto	115:87f2f5183dfb	3055	#define CEC_CFGR_SFT ((uint32_t)0x00000007) /!< CEC Signal Free Time /
Kojto	115:87f2f5183dfb	3056	#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /!< CEC Tolerance /
Kojto	115:87f2f5183dfb	3057	#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /!< CEC Rx Stop /
Kojto	115:87f2f5183dfb	3058	#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /!< CEC Bit Rising Error generation /
Kojto	115:87f2f5183dfb	3059	#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /!< CEC Long Period Error generation /
Kojto	115:87f2f5183dfb	3060	#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /!< CEC Broadcast no Error generation /
Kojto	115:87f2f5183dfb	3061	#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /!< CEC Signal Free Time optional /
Kojto	115:87f2f5183dfb	3062	#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /!< CEC Own Address /
Kojto	115:87f2f5183dfb	3063	#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /!< CEC Listen mode /
Kojto	115:87f2f5183dfb	3064
Kojto	115:87f2f5183dfb	3065	/***************** Bit definition for CEC_TXDR register *****************/
Kojto	115:87f2f5183dfb	3066	#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /!< CEC Tx Data /
Kojto	115:87f2f5183dfb	3067
Kojto	115:87f2f5183dfb	3068	/***************** Bit definition for CEC_RXDR register *****************/
Kojto	115:87f2f5183dfb	3069	#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /!< CEC Rx Data /
Kojto	115:87f2f5183dfb	3070
Kojto	115:87f2f5183dfb	3071	/***************** Bit definition for CEC_ISR register ******************/
Kojto	115:87f2f5183dfb	3072	#define CEC_ISR_RXBR ((uint32_t)0x00000001) /!< CEC Rx-Byte Received /
Kojto	115:87f2f5183dfb	3073	#define CEC_ISR_RXEND ((uint32_t)0x00000002) /!< CEC End Of Reception /
Kojto	115:87f2f5183dfb	3074	#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /!< CEC Rx-Overrun /
Kojto	115:87f2f5183dfb	3075	#define CEC_ISR_BRE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error /
Kojto	115:87f2f5183dfb	3076	#define CEC_ISR_SBPE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error /
Kojto	115:87f2f5183dfb	3077	#define CEC_ISR_LBPE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error /
Kojto	115:87f2f5183dfb	3078	#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge /
Kojto	115:87f2f5183dfb	3079	#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /!< CEC Arbitration Lost /
Kojto	115:87f2f5183dfb	3080	#define CEC_ISR_TXBR ((uint32_t)0x00000100) /!< CEC Tx Byte Request /
Kojto	115:87f2f5183dfb	3081	#define CEC_ISR_TXEND ((uint32_t)0x00000200) /!< CEC End of Transmission /
Kojto	115:87f2f5183dfb	3082	#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun /
Kojto	115:87f2f5183dfb	3083	#define CEC_ISR_TXERR ((uint32_t)0x00000800) /!< CEC Tx-Error /
Kojto	115:87f2f5183dfb	3084	#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge /
Kojto	115:87f2f5183dfb	3085
Kojto	115:87f2f5183dfb	3086	/***************** Bit definition for CEC_IER register ******************/
Kojto	115:87f2f5183dfb	3087	#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /!< CEC Rx-Byte Received IT Enable /
Kojto	115:87f2f5183dfb	3088	#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /!< CEC End Of Reception IT Enable /
Kojto	115:87f2f5183dfb	3089	#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /!< CEC Rx-Overrun IT Enable /
Kojto	115:87f2f5183dfb	3090	#define CEC_IER_BREIE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error IT Enable /
Kojto	115:87f2f5183dfb	3091	#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error IT Enable/
Kojto	115:87f2f5183dfb	3092	#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error IT Enable /
Kojto	115:87f2f5183dfb	3093	#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge IT Enable /
Kojto	115:87f2f5183dfb	3094	#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /!< CEC Arbitration Lost IT Enable /
Kojto	115:87f2f5183dfb	3095	#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /!< CEC Tx Byte Request IT Enable /
Kojto	115:87f2f5183dfb	3096	#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /!< CEC End of Transmission IT Enable /
Kojto	115:87f2f5183dfb	3097	#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun IT Enable /
Kojto	115:87f2f5183dfb	3098	#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /!< CEC Tx-Error IT Enable /
Kojto	115:87f2f5183dfb	3099	#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge IT Enable /
Kojto	115:87f2f5183dfb	3100
Kojto	115:87f2f5183dfb	3101	/******************************************************************************/
Kojto	115:87f2f5183dfb	3102	/* */
Kojto	115:87f2f5183dfb	3103	/* CRC calculation unit */
Kojto	115:87f2f5183dfb	3104	/* */
Kojto	115:87f2f5183dfb	3105	/******************************************************************************/
Kojto	115:87f2f5183dfb	3106	/***************** Bit definition for CRC_DR register *******************/
Kojto	115:87f2f5183dfb	3107	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
Kojto	115:87f2f5183dfb	3108
Kojto	115:87f2f5183dfb	3109	/***************** Bit definition for CRC_IDR register ******************/
Kojto	115:87f2f5183dfb	3110	#define CRC_IDR_IDR ((uint32_t)0x000000FF) /!< General-purpose 8-bit data register bits /
Kojto	115:87f2f5183dfb	3111
Kojto	115:87f2f5183dfb	3112	/****************** Bit definition for CRC_CR register ******************/
Kojto	115:87f2f5183dfb	3113	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
Kojto	115:87f2f5183dfb	3114	#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /!< Polynomial size bits /
Kojto	115:87f2f5183dfb	3115	#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /!< Polynomial size bit 0 /
Kojto	115:87f2f5183dfb	3116	#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /!< Polynomial size bit 1 /
Kojto	115:87f2f5183dfb	3117	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
Kojto	115:87f2f5183dfb	3118	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< Bit 0 /
Kojto	115:87f2f5183dfb	3119	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< Bit 1 /
Kojto	115:87f2f5183dfb	3120	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
Kojto	115:87f2f5183dfb	3121
Kojto	115:87f2f5183dfb	3122	/***************** Bit definition for CRC_INIT register *****************/
Kojto	115:87f2f5183dfb	3123	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
Kojto	115:87f2f5183dfb	3124
Kojto	115:87f2f5183dfb	3125	/***************** Bit definition for CRC_POL register ******************/
Kojto	115:87f2f5183dfb	3126	#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /!< Coefficients of the polynomial /
Kojto	115:87f2f5183dfb	3127
Kojto	115:87f2f5183dfb	3128	/******************************************************************************/
Kojto	115:87f2f5183dfb	3129	/* */
Kojto	115:87f2f5183dfb	3130	/* Digital to Analog Converter */
Kojto	115:87f2f5183dfb	3131	/* */
Kojto	115:87f2f5183dfb	3132	/******************************************************************************/
Kojto	115:87f2f5183dfb	3133	/****************** Bit definition for DAC_CR register ******************/
Kojto	115:87f2f5183dfb	3134	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!<DAC channel1 enable /
Kojto	115:87f2f5183dfb	3135	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!<DAC channel1 output buffer disable /
Kojto	115:87f2f5183dfb	3136	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!<DAC channel1 Trigger enable /
Kojto	115:87f2f5183dfb	3137
Kojto	115:87f2f5183dfb	3138	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
Kojto	115:87f2f5183dfb	3139	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3140	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3141	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3142
Kojto	115:87f2f5183dfb	3143	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
Kojto	115:87f2f5183dfb	3144	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3145	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3146
Kojto	115:87f2f5183dfb	3147	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
Kojto	115:87f2f5183dfb	3148	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3149	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3150	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3151	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	3152
Kojto	115:87f2f5183dfb	3153	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!<DAC channel1 DMA enable /
Kojto	115:87f2f5183dfb	3154	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!<DAC channel2 enable /
Kojto	115:87f2f5183dfb	3155	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!<DAC channel2 output buffer disable /
Kojto	115:87f2f5183dfb	3156	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!<DAC channel2 Trigger enable /
Kojto	115:87f2f5183dfb	3157
Kojto	115:87f2f5183dfb	3158	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
Kojto	115:87f2f5183dfb	3159	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3160	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3161	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3162
Kojto	115:87f2f5183dfb	3163	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
Kojto	115:87f2f5183dfb	3164	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3165	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3166
Kojto	115:87f2f5183dfb	3167	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
Kojto	115:87f2f5183dfb	3168	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3169	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3170	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3171	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	3172
Kojto	115:87f2f5183dfb	3173	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!<DAC channel2 DMA enabled /
Kojto	115:87f2f5183dfb	3174
Kojto	115:87f2f5183dfb	3175	/*************** Bit definition for DAC_SWTRIGR register ****************/
Kojto	115:87f2f5183dfb	3176	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /!<DAC channel1 software trigger /
Kojto	115:87f2f5183dfb	3177	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /!<DAC channel2 software trigger /
Kojto	115:87f2f5183dfb	3178
Kojto	115:87f2f5183dfb	3179	/*************** Bit definition for DAC_DHR12R1 register ****************/
Kojto	115:87f2f5183dfb	3180	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /!<DAC channel1 12-bit Right aligned data /
Kojto	115:87f2f5183dfb	3181
Kojto	115:87f2f5183dfb	3182	/*************** Bit definition for DAC_DHR12L1 register ****************/
Kojto	115:87f2f5183dfb	3183	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /!<DAC channel1 12-bit Left aligned data /
Kojto	115:87f2f5183dfb	3184
Kojto	115:87f2f5183dfb	3185	/**************** Bit definition for DAC_DHR8R1 register ****************/
Kojto	115:87f2f5183dfb	3186	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /!<DAC channel1 8-bit Right aligned data /
Kojto	115:87f2f5183dfb	3187
Kojto	115:87f2f5183dfb	3188	/*************** Bit definition for DAC_DHR12R2 register ****************/
Kojto	115:87f2f5183dfb	3189	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /!<DAC channel2 12-bit Right aligned data /
Kojto	115:87f2f5183dfb	3190
Kojto	115:87f2f5183dfb	3191	/*************** Bit definition for DAC_DHR12L2 register ****************/
Kojto	115:87f2f5183dfb	3192	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /!<DAC channel2 12-bit Left aligned data /
Kojto	115:87f2f5183dfb	3193
Kojto	115:87f2f5183dfb	3194	/**************** Bit definition for DAC_DHR8R2 register ****************/
Kojto	115:87f2f5183dfb	3195	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /!<DAC channel2 8-bit Right aligned data /
Kojto	115:87f2f5183dfb	3196
Kojto	115:87f2f5183dfb	3197	/*************** Bit definition for DAC_DHR12RD register ****************/
Kojto	115:87f2f5183dfb	3198	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
Kojto	115:87f2f5183dfb	3199	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!<DAC channel2 12-bit Right aligned data /
Kojto	115:87f2f5183dfb	3200
Kojto	115:87f2f5183dfb	3201	/*************** Bit definition for DAC_DHR12LD register ****************/
Kojto	115:87f2f5183dfb	3202	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
Kojto	115:87f2f5183dfb	3203	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!<DAC channel2 12-bit Left aligned data /
Kojto	115:87f2f5183dfb	3204
Kojto	115:87f2f5183dfb	3205	/**************** Bit definition for DAC_DHR8RD register ****************/
Kojto	115:87f2f5183dfb	3206	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /!<DAC channel1 8-bit Right aligned data /
Kojto	115:87f2f5183dfb	3207	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /!<DAC channel2 8-bit Right aligned data /
Kojto	115:87f2f5183dfb	3208
Kojto	115:87f2f5183dfb	3209	/***************** Bit definition for DAC_DOR1 register *****************/
Kojto	115:87f2f5183dfb	3210	#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /!<DAC channel1 data output /
Kojto	115:87f2f5183dfb	3211
Kojto	115:87f2f5183dfb	3212	/***************** Bit definition for DAC_DOR2 register *****************/
Kojto	115:87f2f5183dfb	3213	#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /!<DAC channel2 data output /
Kojto	115:87f2f5183dfb	3214
Kojto	115:87f2f5183dfb	3215	/****************** Bit definition for DAC_SR register ******************/
Kojto	115:87f2f5183dfb	3216	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!<DAC channel1 DMA underrun flag /
Kojto	115:87f2f5183dfb	3217	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun flag /
Kojto	115:87f2f5183dfb	3218
Kojto	115:87f2f5183dfb	3219	/******************************************************************************/
Kojto	115:87f2f5183dfb	3220	/* */
Kojto	115:87f2f5183dfb	3221	/* Debug MCU */
Kojto	115:87f2f5183dfb	3222	/* */
Kojto	115:87f2f5183dfb	3223	/******************************************************************************/
Kojto	115:87f2f5183dfb	3224
Kojto	115:87f2f5183dfb	3225	/******************************************************************************/
Kojto	115:87f2f5183dfb	3226	/* */
Kojto	115:87f2f5183dfb	3227	/* DCMI */
Kojto	115:87f2f5183dfb	3228	/* */
Kojto	115:87f2f5183dfb	3229	/******************************************************************************/
Kojto	115:87f2f5183dfb	3230	/****************** Bits definition for DCMI_CR register ****************/
Kojto	115:87f2f5183dfb	3231	#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3232	#define DCMI_CR_CM ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3233	#define DCMI_CR_CROP ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3234	#define DCMI_CR_JPEG ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3235	#define DCMI_CR_ESS ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3236	#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	3237	#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	3238	#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	3239	#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	3240	#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	3241	#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	3242	#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	3243	#define DCMI_CR_CRE ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	3244	#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	3245	#define DCMI_CR_BSM ((uint32_t)0x00030000)
Kojto	115:87f2f5183dfb	3246	#define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	3247	#define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	3248	#define DCMI_CR_OEBS ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	3249	#define DCMI_CR_LSM ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	3250	#define DCMI_CR_OELS ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	3251
Kojto	115:87f2f5183dfb	3252	/****************** Bits definition for DCMI_SR register ****************/
Kojto	115:87f2f5183dfb	3253	#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3254	#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3255	#define DCMI_SR_FNE ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3256
Kojto	115:87f2f5183dfb	3257	/****************** Bits definition for DCMI_RISR register **************/
Kojto	115:87f2f5183dfb	3258	#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3259	#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3260	#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3261	#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3262	#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3263
Kojto	115:87f2f5183dfb	3264	/****************** Bits definition for DCMI_IER register ***************/
Kojto	115:87f2f5183dfb	3265	#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3266	#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3267	#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3268	#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3269	#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3270
Kojto	115:87f2f5183dfb	3271	/****************** Bits definition for DCMI_MISR register **************/
Kojto	115:87f2f5183dfb	3272	#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3273	#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3274	#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3275	#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3276	#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3277
Kojto	115:87f2f5183dfb	3278	/****************** Bits definition for DCMI_ICR register ***************/
Kojto	115:87f2f5183dfb	3279	#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3280	#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3281	#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3282	#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3283	#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3284
Kojto	115:87f2f5183dfb	3285	/******************************************************************************/
Kojto	115:87f2f5183dfb	3286	/* */
Kojto	115:87f2f5183dfb	3287	/* DMA Controller */
Kojto	115:87f2f5183dfb	3288	/* */
Kojto	115:87f2f5183dfb	3289	/******************************************************************************/
Kojto	115:87f2f5183dfb	3290	/****************** Bits definition for DMA_SxCR register ***************/
Kojto	115:87f2f5183dfb	3291	#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
Kojto	115:87f2f5183dfb	3292	#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	3293	#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	3294	#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	3295	#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
Kojto	115:87f2f5183dfb	3296	#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	3297	#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	3298	#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
Kojto	115:87f2f5183dfb	3299	#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	3300	#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	3301	#define DMA_SxCR_ACK ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	3302	#define DMA_SxCR_CT ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	3303	#define DMA_SxCR_DBM ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	3304	#define DMA_SxCR_PL ((uint32_t)0x00030000)
Kojto	115:87f2f5183dfb	3305	#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	3306	#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	3307	#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	3308	#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
Kojto	115:87f2f5183dfb	3309	#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	3310	#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	3311	#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
Kojto	115:87f2f5183dfb	3312	#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	3313	#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	3314	#define DMA_SxCR_MINC ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	3315	#define DMA_SxCR_PINC ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	3316	#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	3317	#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
Kojto	115:87f2f5183dfb	3318	#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	3319	#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	3320	#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	3321	#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3322	#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3323	#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3324	#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3325	#define DMA_SxCR_EN ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3326
Kojto	115:87f2f5183dfb	3327	/****************** Bits definition for DMA_SxCNDTR register ************/
Kojto	115:87f2f5183dfb	3328	#define DMA_SxNDT ((uint32_t)0x0000FFFF)
Kojto	115:87f2f5183dfb	3329	#define DMA_SxNDT_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3330	#define DMA_SxNDT_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3331	#define DMA_SxNDT_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3332	#define DMA_SxNDT_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3333	#define DMA_SxNDT_4 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3334	#define DMA_SxNDT_5 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	3335	#define DMA_SxNDT_6 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	3336	#define DMA_SxNDT_7 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	3337	#define DMA_SxNDT_8 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	3338	#define DMA_SxNDT_9 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	3339	#define DMA_SxNDT_10 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	3340	#define DMA_SxNDT_11 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	3341	#define DMA_SxNDT_12 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	3342	#define DMA_SxNDT_13 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	3343	#define DMA_SxNDT_14 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	3344	#define DMA_SxNDT_15 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	3345
Kojto	115:87f2f5183dfb	3346	/****************** Bits definition for DMA_SxFCR register **************/
Kojto	115:87f2f5183dfb	3347	#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	3348	#define DMA_SxFCR_FS ((uint32_t)0x00000038)
Kojto	115:87f2f5183dfb	3349	#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3350	#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3351	#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	3352	#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3353	#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
Kojto	115:87f2f5183dfb	3354	#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3355	#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3356
Kojto	115:87f2f5183dfb	3357	/****************** Bits definition for DMA_LISR register ***************/
Kojto	115:87f2f5183dfb	3358	#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	3359	#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	3360	#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	3361	#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	3362	#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	3363	#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	3364	#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	3365	#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	3366	#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	3367	#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	3368	#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	3369	#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	3370	#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	3371	#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	3372	#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	3373	#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	3374	#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3375	#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3376	#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3377	#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3378
Kojto	115:87f2f5183dfb	3379	/****************** Bits definition for DMA_HISR register ***************/
Kojto	115:87f2f5183dfb	3380	#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	3381	#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	3382	#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	3383	#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	3384	#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	3385	#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	3386	#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	3387	#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	3388	#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	3389	#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	3390	#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	3391	#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	3392	#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	3393	#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	3394	#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	3395	#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	3396	#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3397	#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3398	#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3399	#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3400
Kojto	115:87f2f5183dfb	3401	/****************** Bits definition for DMA_LIFCR register **************/
Kojto	115:87f2f5183dfb	3402	#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	3403	#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	3404	#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	3405	#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	3406	#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	3407	#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	3408	#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	3409	#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	3410	#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	3411	#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	3412	#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	3413	#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	3414	#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	3415	#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	3416	#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	3417	#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	3418	#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3419	#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3420	#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3421	#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3422
Kojto	115:87f2f5183dfb	3423	/****************** Bits definition for DMA_HIFCR register **************/
Kojto	115:87f2f5183dfb	3424	#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	3425	#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	3426	#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	3427	#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	3428	#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	3429	#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	3430	#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	3431	#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	3432	#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	3433	#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	3434	#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	3435	#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	3436	#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	3437	#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	3438	#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	3439	#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	3440	#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3441	#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3442	#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3443	#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3444
Kojto	115:87f2f5183dfb	3445	/******************************************************************************/
Kojto	115:87f2f5183dfb	3446	/* */
Kojto	115:87f2f5183dfb	3447	/* AHB Master DMA2D Controller (DMA2D) */
Kojto	115:87f2f5183dfb	3448	/* */
Kojto	115:87f2f5183dfb	3449	/******************************************************************************/
Kojto	115:87f2f5183dfb	3450
Kojto	115:87f2f5183dfb	3451	/****************** Bit definition for DMA2D_CR register ****************/
Kojto	115:87f2f5183dfb	3452
Kojto	115:87f2f5183dfb	3453	#define DMA2D_CR_START ((uint32_t)0x00000001) /!< Start transfer /
Kojto	115:87f2f5183dfb	3454	#define DMA2D_CR_SUSP ((uint32_t)0x00000002) /!< Suspend transfer /
Kojto	115:87f2f5183dfb	3455	#define DMA2D_CR_ABORT ((uint32_t)0x00000004) /!< Abort transfer /
Kojto	115:87f2f5183dfb	3456	#define DMA2D_CR_TEIE ((uint32_t)0x00000100) /!< Transfer Error Interrupt Enable /
Kojto	115:87f2f5183dfb	3457	#define DMA2D_CR_TCIE ((uint32_t)0x00000200) /!< Transfer Complete Interrupt Enable /
Kojto	115:87f2f5183dfb	3458	#define DMA2D_CR_TWIE ((uint32_t)0x00000400) /!< Transfer Watermark Interrupt Enable /
Kojto	115:87f2f5183dfb	3459	#define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /!< CLUT Access Error Interrupt Enable /
Kojto	115:87f2f5183dfb	3460	#define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /!< CLUT Transfer Complete Interrupt Enable /
Kojto	115:87f2f5183dfb	3461	#define DMA2D_CR_CEIE ((uint32_t)0x00002000) /!< Configuration Error Interrupt Enable /
Kojto	115:87f2f5183dfb	3462	#define DMA2D_CR_MODE ((uint32_t)0x00030000) /!< DMA2D Mode /
Kojto	115:87f2f5183dfb	3463
Kojto	115:87f2f5183dfb	3464	/****************** Bit definition for DMA2D_ISR register ***************/
Kojto	115:87f2f5183dfb	3465
Kojto	115:87f2f5183dfb	3466	#define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /!< Transfer Error Interrupt Flag /
Kojto	115:87f2f5183dfb	3467	#define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /!< Transfer Complete Interrupt Flag /
Kojto	115:87f2f5183dfb	3468	#define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /!< Transfer Watermark Interrupt Flag /
Kojto	115:87f2f5183dfb	3469	#define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /!< CLUT Access Error Interrupt Flag /
Kojto	115:87f2f5183dfb	3470	#define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /!< CLUT Transfer Complete Interrupt Flag /
Kojto	115:87f2f5183dfb	3471	#define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /!< Configuration Error Interrupt Flag /
Kojto	115:87f2f5183dfb	3472
Kojto	115:87f2f5183dfb	3473	/****************** Bit definition for DMA2D_IFSR register **************/
Kojto	115:87f2f5183dfb	3474
Kojto	115:87f2f5183dfb	3475	#define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /!< Clears Transfer Error Interrupt Flag /
Kojto	115:87f2f5183dfb	3476	#define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /!< Clears Transfer Complete Interrupt Flag /
Kojto	115:87f2f5183dfb	3477	#define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /!< Clears Transfer Watermark Interrupt Flag /
Kojto	115:87f2f5183dfb	3478	#define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /!< Clears CLUT Access Error Interrupt Flag /
Kojto	115:87f2f5183dfb	3479	#define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /!< Clears CLUT Transfer Complete Interrupt Flag /
Kojto	115:87f2f5183dfb	3480	#define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /!< Clears Configuration Error Interrupt Flag /
Kojto	115:87f2f5183dfb	3481
Kojto	115:87f2f5183dfb	3482	/****************** Bit definition for DMA2D_FGMAR register *************/
Kojto	115:87f2f5183dfb	3483
Kojto	115:87f2f5183dfb	3484	#define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	115:87f2f5183dfb	3485
Kojto	115:87f2f5183dfb	3486	/****************** Bit definition for DMA2D_FGOR register **************/
Kojto	115:87f2f5183dfb	3487
Kojto	115:87f2f5183dfb	3488	#define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /!< Line Offset /
Kojto	115:87f2f5183dfb	3489
Kojto	115:87f2f5183dfb	3490	/****************** Bit definition for DMA2D_BGMAR register *************/
Kojto	115:87f2f5183dfb	3491
Kojto	115:87f2f5183dfb	3492	#define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	115:87f2f5183dfb	3493
Kojto	115:87f2f5183dfb	3494	/****************** Bit definition for DMA2D_BGOR register **************/
Kojto	115:87f2f5183dfb	3495
Kojto	115:87f2f5183dfb	3496	#define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /!< Line Offset /
Kojto	115:87f2f5183dfb	3497
Kojto	115:87f2f5183dfb	3498	/****************** Bit definition for DMA2D_FGPFCCR register ***********/
Kojto	115:87f2f5183dfb	3499
Kojto	115:87f2f5183dfb	3500	#define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /!< Color mode /
Kojto	115:87f2f5183dfb	3501	#define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /!< CLUT Color mode /
Kojto	115:87f2f5183dfb	3502	#define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /!< Start /
Kojto	115:87f2f5183dfb	3503	#define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /!< CLUT size /
Kojto	115:87f2f5183dfb	3504	#define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /!< Alpha mode /
Kojto	115:87f2f5183dfb	3505	#define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /!< Alpha value /
Kojto	115:87f2f5183dfb	3506
Kojto	115:87f2f5183dfb	3507	/****************** Bit definition for DMA2D_FGCOLR register ************/
Kojto	115:87f2f5183dfb	3508
Kojto	115:87f2f5183dfb	3509	#define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /!< Blue Value /
Kojto	115:87f2f5183dfb	3510	#define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /!< Green Value /
Kojto	115:87f2f5183dfb	3511	#define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /!< Red Value /
Kojto	115:87f2f5183dfb	3512
Kojto	115:87f2f5183dfb	3513	/****************** Bit definition for DMA2D_BGPFCCR register ***********/
Kojto	115:87f2f5183dfb	3514
Kojto	115:87f2f5183dfb	3515	#define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /!< Color mode /
Kojto	115:87f2f5183dfb	3516	#define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /!< CLUT Color mode /
Kojto	115:87f2f5183dfb	3517	#define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /!< Start /
Kojto	115:87f2f5183dfb	3518	#define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /!< CLUT size /
Kojto	115:87f2f5183dfb	3519	#define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /!< Alpha Mode /
Kojto	115:87f2f5183dfb	3520	#define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /!< Alpha value /
Kojto	115:87f2f5183dfb	3521
Kojto	115:87f2f5183dfb	3522	/****************** Bit definition for DMA2D_BGCOLR register ************/
Kojto	115:87f2f5183dfb	3523
Kojto	115:87f2f5183dfb	3524	#define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /!< Blue Value /
Kojto	115:87f2f5183dfb	3525	#define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /!< Green Value /
Kojto	115:87f2f5183dfb	3526	#define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /!< Red Value /
Kojto	115:87f2f5183dfb	3527
Kojto	115:87f2f5183dfb	3528	/****************** Bit definition for DMA2D_FGCMAR register ************/
Kojto	115:87f2f5183dfb	3529
Kojto	115:87f2f5183dfb	3530	#define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	115:87f2f5183dfb	3531
Kojto	115:87f2f5183dfb	3532	/****************** Bit definition for DMA2D_BGCMAR register ************/
Kojto	115:87f2f5183dfb	3533
Kojto	115:87f2f5183dfb	3534	#define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	115:87f2f5183dfb	3535
Kojto	115:87f2f5183dfb	3536	/****************** Bit definition for DMA2D_OPFCCR register ************/
Kojto	115:87f2f5183dfb	3537
Kojto	115:87f2f5183dfb	3538	#define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /!< Color mode /
Kojto	115:87f2f5183dfb	3539
Kojto	115:87f2f5183dfb	3540	/****************** Bit definition for DMA2D_OCOLR register *************/
Kojto	115:87f2f5183dfb	3541
Kojto	115:87f2f5183dfb	3542	/!<Mode_ARGB8888/RGB888 /
Kojto	115:87f2f5183dfb	3543
Kojto	115:87f2f5183dfb	3544	#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /!< BLUE Value /
Kojto	115:87f2f5183dfb	3545	#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /!< GREEN Value /
Kojto	115:87f2f5183dfb	3546	#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /!< Red Value /
Kojto	115:87f2f5183dfb	3547	#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /!< Alpha Channel Value /
Kojto	115:87f2f5183dfb	3548
Kojto	115:87f2f5183dfb	3549	/!<Mode_RGB565 /
Kojto	115:87f2f5183dfb	3550	#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /!< BLUE Value /
Kojto	115:87f2f5183dfb	3551	#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /!< GREEN Value /
Kojto	115:87f2f5183dfb	3552	#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /!< Red Value /
Kojto	115:87f2f5183dfb	3553
Kojto	115:87f2f5183dfb	3554	/!<Mode_ARGB1555 /
Kojto	115:87f2f5183dfb	3555	#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /!< BLUE Value /
Kojto	115:87f2f5183dfb	3556	#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /!< GREEN Value /
Kojto	115:87f2f5183dfb	3557	#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /!< Red Value /
Kojto	115:87f2f5183dfb	3558	#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /!< Alpha Channel Value /
Kojto	115:87f2f5183dfb	3559
Kojto	115:87f2f5183dfb	3560	/!<Mode_ARGB4444 /
Kojto	115:87f2f5183dfb	3561	#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /!< BLUE Value /
Kojto	115:87f2f5183dfb	3562	#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /!< GREEN Value /
Kojto	115:87f2f5183dfb	3563	#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /!< Red Value /
Kojto	115:87f2f5183dfb	3564	#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /!< Alpha Channel Value /
Kojto	115:87f2f5183dfb	3565
Kojto	115:87f2f5183dfb	3566	/****************** Bit definition for DMA2D_OMAR register **************/
Kojto	115:87f2f5183dfb	3567
Kojto	115:87f2f5183dfb	3568	#define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	115:87f2f5183dfb	3569
Kojto	115:87f2f5183dfb	3570	/****************** Bit definition for DMA2D_OOR register ***************/
Kojto	115:87f2f5183dfb	3571
Kojto	115:87f2f5183dfb	3572	#define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /!< Line Offset /
Kojto	115:87f2f5183dfb	3573
Kojto	115:87f2f5183dfb	3574	/****************** Bit definition for DMA2D_NLR register ***************/
Kojto	115:87f2f5183dfb	3575
Kojto	115:87f2f5183dfb	3576	#define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /!< Number of Lines /
Kojto	115:87f2f5183dfb	3577	#define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /!< Pixel per Lines /
Kojto	115:87f2f5183dfb	3578
Kojto	115:87f2f5183dfb	3579	/****************** Bit definition for DMA2D_LWR register ***************/
Kojto	115:87f2f5183dfb	3580
Kojto	115:87f2f5183dfb	3581	#define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /!< Line Watermark /
Kojto	115:87f2f5183dfb	3582
Kojto	115:87f2f5183dfb	3583	/****************** Bit definition for DMA2D_AMTCR register *************/
Kojto	115:87f2f5183dfb	3584
Kojto	115:87f2f5183dfb	3585	#define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /!< Enable /
Kojto	115:87f2f5183dfb	3586	#define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /!< Dead Time /
Kojto	115:87f2f5183dfb	3587
Kojto	115:87f2f5183dfb	3588
Kojto	115:87f2f5183dfb	3589
Kojto	115:87f2f5183dfb	3590	/****************** Bit definition for DMA2D_FGCLUT register ************/
Kojto	115:87f2f5183dfb	3591
Kojto	115:87f2f5183dfb	3592	/****************** Bit definition for DMA2D_BGCLUT register ************/
Kojto	115:87f2f5183dfb	3593
Kojto	115:87f2f5183dfb	3594
Kojto	115:87f2f5183dfb	3595	/******************************************************************************/
Kojto	115:87f2f5183dfb	3596	/* */
Kojto	115:87f2f5183dfb	3597	/* External Interrupt/Event Controller */
Kojto	115:87f2f5183dfb	3598	/* */
Kojto	115:87f2f5183dfb	3599	/******************************************************************************/
Kojto	115:87f2f5183dfb	3600	/***************** Bit definition for EXTI_IMR register *****************/
Kojto	115:87f2f5183dfb	3601	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
Kojto	115:87f2f5183dfb	3602	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
Kojto	115:87f2f5183dfb	3603	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
Kojto	115:87f2f5183dfb	3604	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
Kojto	115:87f2f5183dfb	3605	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
Kojto	115:87f2f5183dfb	3606	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
Kojto	115:87f2f5183dfb	3607	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
Kojto	115:87f2f5183dfb	3608	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
Kojto	115:87f2f5183dfb	3609	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
Kojto	115:87f2f5183dfb	3610	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
Kojto	115:87f2f5183dfb	3611	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
Kojto	115:87f2f5183dfb	3612	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
Kojto	115:87f2f5183dfb	3613	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
Kojto	115:87f2f5183dfb	3614	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
Kojto	115:87f2f5183dfb	3615	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
Kojto	115:87f2f5183dfb	3616	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
Kojto	115:87f2f5183dfb	3617	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
Kojto	115:87f2f5183dfb	3618	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
Kojto	115:87f2f5183dfb	3619	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
Kojto	115:87f2f5183dfb	3620	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
Kojto	115:87f2f5183dfb	3621	#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /!< Interrupt Mask on line 20 /
Kojto	115:87f2f5183dfb	3622	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
Kojto	115:87f2f5183dfb	3623	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
Kojto	115:87f2f5183dfb	3624	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
Kojto	115:87f2f5183dfb	3625
Kojto	115:87f2f5183dfb	3626	/***************** Bit definition for EXTI_EMR register *****************/
Kojto	115:87f2f5183dfb	3627	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
Kojto	115:87f2f5183dfb	3628	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
Kojto	115:87f2f5183dfb	3629	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
Kojto	115:87f2f5183dfb	3630	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
Kojto	115:87f2f5183dfb	3631	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
Kojto	115:87f2f5183dfb	3632	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
Kojto	115:87f2f5183dfb	3633	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
Kojto	115:87f2f5183dfb	3634	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
Kojto	115:87f2f5183dfb	3635	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
Kojto	115:87f2f5183dfb	3636	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
Kojto	115:87f2f5183dfb	3637	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
Kojto	115:87f2f5183dfb	3638	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
Kojto	115:87f2f5183dfb	3639	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
Kojto	115:87f2f5183dfb	3640	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
Kojto	115:87f2f5183dfb	3641	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
Kojto	115:87f2f5183dfb	3642	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
Kojto	115:87f2f5183dfb	3643	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
Kojto	115:87f2f5183dfb	3644	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
Kojto	115:87f2f5183dfb	3645	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
Kojto	115:87f2f5183dfb	3646	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
Kojto	115:87f2f5183dfb	3647	#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /!< Event Mask on line 20 /
Kojto	115:87f2f5183dfb	3648	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
Kojto	115:87f2f5183dfb	3649	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
Kojto	115:87f2f5183dfb	3650	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
Kojto	115:87f2f5183dfb	3651
Kojto	115:87f2f5183dfb	3652	/**************** Bit definition for EXTI_RTSR register *****************/
Kojto	115:87f2f5183dfb	3653	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
Kojto	115:87f2f5183dfb	3654	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
Kojto	115:87f2f5183dfb	3655	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
Kojto	115:87f2f5183dfb	3656	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
Kojto	115:87f2f5183dfb	3657	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
Kojto	115:87f2f5183dfb	3658	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
Kojto	115:87f2f5183dfb	3659	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
Kojto	115:87f2f5183dfb	3660	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
Kojto	115:87f2f5183dfb	3661	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
Kojto	115:87f2f5183dfb	3662	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
Kojto	115:87f2f5183dfb	3663	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
Kojto	115:87f2f5183dfb	3664	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
Kojto	115:87f2f5183dfb	3665	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
Kojto	115:87f2f5183dfb	3666	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
Kojto	115:87f2f5183dfb	3667	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
Kojto	115:87f2f5183dfb	3668	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
Kojto	115:87f2f5183dfb	3669	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
Kojto	115:87f2f5183dfb	3670	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
Kojto	115:87f2f5183dfb	3671	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
Kojto	115:87f2f5183dfb	3672	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
Kojto	115:87f2f5183dfb	3673	#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /!< Rising trigger event configuration bit of line 20 /
Kojto	115:87f2f5183dfb	3674	#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /!< Rising trigger event configuration bit of line 21 /
Kojto	115:87f2f5183dfb	3675	#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /!< Rising trigger event configuration bit of line 22 /
Kojto	115:87f2f5183dfb	3676	#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /!< Rising trigger event configuration bit of line 23 /
Kojto	115:87f2f5183dfb	3677
Kojto	115:87f2f5183dfb	3678	/**************** Bit definition for EXTI_FTSR register *****************/
Kojto	115:87f2f5183dfb	3679	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
Kojto	115:87f2f5183dfb	3680	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
Kojto	115:87f2f5183dfb	3681	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
Kojto	115:87f2f5183dfb	3682	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
Kojto	115:87f2f5183dfb	3683	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
Kojto	115:87f2f5183dfb	3684	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
Kojto	115:87f2f5183dfb	3685	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
Kojto	115:87f2f5183dfb	3686	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
Kojto	115:87f2f5183dfb	3687	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
Kojto	115:87f2f5183dfb	3688	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
Kojto	115:87f2f5183dfb	3689	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
Kojto	115:87f2f5183dfb	3690	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
Kojto	115:87f2f5183dfb	3691	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
Kojto	115:87f2f5183dfb	3692	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
Kojto	115:87f2f5183dfb	3693	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
Kojto	115:87f2f5183dfb	3694	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
Kojto	115:87f2f5183dfb	3695	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
Kojto	115:87f2f5183dfb	3696	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
Kojto	115:87f2f5183dfb	3697	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
Kojto	115:87f2f5183dfb	3698	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
Kojto	115:87f2f5183dfb	3699	#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /!< Falling trigger event configuration bit of line 20 /
Kojto	115:87f2f5183dfb	3700	#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /!< Falling trigger event configuration bit of line 21 /
Kojto	115:87f2f5183dfb	3701	#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /!< Falling trigger event configuration bit of line 22 /
Kojto	115:87f2f5183dfb	3702	#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /!< Falling trigger event configuration bit of line 23 /
Kojto	115:87f2f5183dfb	3703
Kojto	115:87f2f5183dfb	3704	/**************** Bit definition for EXTI_SWIER register ****************/
Kojto	115:87f2f5183dfb	3705	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
Kojto	115:87f2f5183dfb	3706	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
Kojto	115:87f2f5183dfb	3707	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
Kojto	115:87f2f5183dfb	3708	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
Kojto	115:87f2f5183dfb	3709	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
Kojto	115:87f2f5183dfb	3710	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
Kojto	115:87f2f5183dfb	3711	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
Kojto	115:87f2f5183dfb	3712	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
Kojto	115:87f2f5183dfb	3713	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
Kojto	115:87f2f5183dfb	3714	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
Kojto	115:87f2f5183dfb	3715	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
Kojto	115:87f2f5183dfb	3716	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
Kojto	115:87f2f5183dfb	3717	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
Kojto	115:87f2f5183dfb	3718	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
Kojto	115:87f2f5183dfb	3719	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
Kojto	115:87f2f5183dfb	3720	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
Kojto	115:87f2f5183dfb	3721	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
Kojto	115:87f2f5183dfb	3722	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
Kojto	115:87f2f5183dfb	3723	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
Kojto	115:87f2f5183dfb	3724	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
Kojto	115:87f2f5183dfb	3725	#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /!< Software Interrupt on line 20 /
Kojto	115:87f2f5183dfb	3726	#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /!< Software Interrupt on line 21 /
Kojto	115:87f2f5183dfb	3727	#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /!< Software Interrupt on line 22 /
Kojto	115:87f2f5183dfb	3728	#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /!< Software Interrupt on line 23 /
Kojto	115:87f2f5183dfb	3729
Kojto	115:87f2f5183dfb	3730	/***************** Bit definition for EXTI_PR register ******************/
Kojto	115:87f2f5183dfb	3731	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
Kojto	115:87f2f5183dfb	3732	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
Kojto	115:87f2f5183dfb	3733	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
Kojto	115:87f2f5183dfb	3734	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
Kojto	115:87f2f5183dfb	3735	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
Kojto	115:87f2f5183dfb	3736	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
Kojto	115:87f2f5183dfb	3737	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
Kojto	115:87f2f5183dfb	3738	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
Kojto	115:87f2f5183dfb	3739	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
Kojto	115:87f2f5183dfb	3740	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
Kojto	115:87f2f5183dfb	3741	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
Kojto	115:87f2f5183dfb	3742	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
Kojto	115:87f2f5183dfb	3743	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
Kojto	115:87f2f5183dfb	3744	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
Kojto	115:87f2f5183dfb	3745	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
Kojto	115:87f2f5183dfb	3746	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
Kojto	115:87f2f5183dfb	3747	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
Kojto	115:87f2f5183dfb	3748	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
Kojto	115:87f2f5183dfb	3749	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
Kojto	115:87f2f5183dfb	3750	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
Kojto	115:87f2f5183dfb	3751	#define EXTI_PR_PR20 ((uint32_t)0x00100000) /!< Pending bit for line 20 /
Kojto	115:87f2f5183dfb	3752	#define EXTI_PR_PR21 ((uint32_t)0x00200000) /!< Pending bit for line 21 /
Kojto	115:87f2f5183dfb	3753	#define EXTI_PR_PR22 ((uint32_t)0x00400000) /!< Pending bit for line 22 /
Kojto	115:87f2f5183dfb	3754	#define EXTI_PR_PR23 ((uint32_t)0x00800000) /!< Pending bit for line 23 /
Kojto	115:87f2f5183dfb	3755
Kojto	115:87f2f5183dfb	3756	/******************************************************************************/
Kojto	115:87f2f5183dfb	3757	/* */
Kojto	115:87f2f5183dfb	3758	/* FLASH */
Kojto	115:87f2f5183dfb	3759	/* */
Kojto	115:87f2f5183dfb	3760	/******************************************************************************/
Kojto	115:87f2f5183dfb	3761	/***************** Bits definition for FLASH_ACR register ***************/
Kojto	115:87f2f5183dfb	3762	#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
Kojto	115:87f2f5183dfb	3763	#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	3764	#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3765	#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3766	#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
Kojto	115:87f2f5183dfb	3767	#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3768	#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
Kojto	115:87f2f5183dfb	3769	#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
Kojto	115:87f2f5183dfb	3770	#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
Kojto	115:87f2f5183dfb	3771	#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3772	#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
Kojto	115:87f2f5183dfb	3773	#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
Kojto	115:87f2f5183dfb	3774	#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
Kojto	115:87f2f5183dfb	3775	#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
Kojto	115:87f2f5183dfb	3776	#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
Kojto	115:87f2f5183dfb	3777	#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
Kojto	115:87f2f5183dfb	3778	#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
Kojto	115:87f2f5183dfb	3779	#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	3780	#define FLASH_ACR_ARTEN ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	3781	#define FLASH_ACR_ARTRST ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	3782
Kojto	115:87f2f5183dfb	3783	/***************** Bits definition for FLASH_SR register ****************/
Kojto	115:87f2f5183dfb	3784	#define FLASH_SR_EOP ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3785	#define FLASH_SR_OPERR ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3786	#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3787	#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	3788	#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	3789	#define FLASH_SR_ERSERR ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	3790	#define FLASH_SR_BSY ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	3791
Kojto	115:87f2f5183dfb	3792	/***************** Bits definition for FLASH_CR register ****************/
Kojto	115:87f2f5183dfb	3793	#define FLASH_CR_PG ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3794	#define FLASH_CR_SER ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3795	#define FLASH_CR_MER ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3796	#define FLASH_CR_SNB ((uint32_t)0x00000078)
Kojto	115:87f2f5183dfb	3797	#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3798	#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3799	#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	3800	#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	3801	#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
Kojto	115:87f2f5183dfb	3802	#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	3803	#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	3804	#define FLASH_CR_STRT ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	3805	#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	3806	#define FLASH_CR_ERRIE ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	3807	#define FLASH_CR_LOCK ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	3808
Kojto	115:87f2f5183dfb	3809	/***************** Bits definition for FLASH_OPTCR register *************/
Kojto	115:87f2f5183dfb	3810	#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	3811	#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	3812	#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
Kojto	115:87f2f5183dfb	3813	#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	3814	#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	3815	#define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	3816	#define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	3817	#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	3818	#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	3819	#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
Kojto	115:87f2f5183dfb	3820	#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	3821	#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	3822	#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	3823	#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	3824	#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	3825	#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	3826	#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	3827	#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	3828	#define FLASH_OPTCR_nWRP ((uint32_t)0x00FF0000)
Kojto	115:87f2f5183dfb	3829	#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	3830	#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	3831	#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	3832	#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	3833	#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	3834	#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	3835	#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	3836	#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	3837	#define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	3838	#define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	3839
Kojto	115:87f2f5183dfb	3840	/***************** Bits definition for FLASH_OPTCR1 register *************/
Kojto	115:87f2f5183dfb	3841	#define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)
Kojto	115:87f2f5183dfb	3842	#define FLASH_OPTCR1_BOOT_ADD1 ((uint32_t)0xFFFF0000)
Kojto	115:87f2f5183dfb	3843
Kojto	115:87f2f5183dfb	3844
Kojto	115:87f2f5183dfb	3845
Kojto	115:87f2f5183dfb	3846	/******************************************************************************/
Kojto	115:87f2f5183dfb	3847	/* */
Kojto	115:87f2f5183dfb	3848	/* Flexible Memory Controller */
Kojto	115:87f2f5183dfb	3849	/* */
Kojto	115:87f2f5183dfb	3850	/******************************************************************************/
Kojto	115:87f2f5183dfb	3851	/**************** Bit definition for FMC_BCR1 register *****************/
Kojto	115:87f2f5183dfb	3852	#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
Kojto	115:87f2f5183dfb	3853	#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
Kojto	115:87f2f5183dfb	3854
Kojto	115:87f2f5183dfb	3855	#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
Kojto	115:87f2f5183dfb	3856	#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3857	#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3858
Kojto	115:87f2f5183dfb	3859	#define FMC_BCR1_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
Kojto	115:87f2f5183dfb	3860	#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3861	#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3862
Kojto	115:87f2f5183dfb	3863	#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
Kojto	115:87f2f5183dfb	3864	#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
Kojto	115:87f2f5183dfb	3865	#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
Kojto	115:87f2f5183dfb	3866	#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
Kojto	115:87f2f5183dfb	3867	#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
Kojto	115:87f2f5183dfb	3868	#define FMC_BCR1_WREN ((uint32_t)0x00001000) /!<Write enable bit /
Kojto	115:87f2f5183dfb	3869	#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
Kojto	115:87f2f5183dfb	3870	#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
Kojto	115:87f2f5183dfb	3871	#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
Kojto	115:87f2f5183dfb	3872	#define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /!<CRAM page size /
Kojto	115:87f2f5183dfb	3873	#define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3874	#define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3875	#define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3876	#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
Kojto	115:87f2f5183dfb	3877	#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /!<Continous clock enable /
Kojto	115:87f2f5183dfb	3878	#define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /!<Write FIFO Disable /
Kojto	115:87f2f5183dfb	3879
Kojto	115:87f2f5183dfb	3880	/**************** Bit definition for FMC_BCR2 register *****************/
Kojto	115:87f2f5183dfb	3881	#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
Kojto	115:87f2f5183dfb	3882	#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
Kojto	115:87f2f5183dfb	3883
Kojto	115:87f2f5183dfb	3884	#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
Kojto	115:87f2f5183dfb	3885	#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3886	#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3887
Kojto	115:87f2f5183dfb	3888	#define FMC_BCR2_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
Kojto	115:87f2f5183dfb	3889	#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3890	#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3891
Kojto	115:87f2f5183dfb	3892	#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
Kojto	115:87f2f5183dfb	3893	#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
Kojto	115:87f2f5183dfb	3894	#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
Kojto	115:87f2f5183dfb	3895	#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
Kojto	115:87f2f5183dfb	3896	#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
Kojto	115:87f2f5183dfb	3897	#define FMC_BCR2_WREN ((uint32_t)0x00001000) /!<Write enable bit /
Kojto	115:87f2f5183dfb	3898	#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
Kojto	115:87f2f5183dfb	3899	#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
Kojto	115:87f2f5183dfb	3900	#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
Kojto	115:87f2f5183dfb	3901	#define FMC_BCR2_CPSIZE ((uint32_t)0x00070000) /!<CRAM page size /
Kojto	115:87f2f5183dfb	3902	#define FMC_BCR2_CPSIZE_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3903	#define FMC_BCR2_CPSIZE_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3904	#define FMC_BCR2_CPSIZE_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3905	#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
Kojto	115:87f2f5183dfb	3906
Kojto	115:87f2f5183dfb	3907	/**************** Bit definition for FMC_BCR3 register *****************/
Kojto	115:87f2f5183dfb	3908	#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
Kojto	115:87f2f5183dfb	3909	#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
Kojto	115:87f2f5183dfb	3910
Kojto	115:87f2f5183dfb	3911	#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
Kojto	115:87f2f5183dfb	3912	#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3913	#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3914
Kojto	115:87f2f5183dfb	3915	#define FMC_BCR3_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
Kojto	115:87f2f5183dfb	3916	#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3917	#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3918
Kojto	115:87f2f5183dfb	3919	#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
Kojto	115:87f2f5183dfb	3920	#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
Kojto	115:87f2f5183dfb	3921	#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
Kojto	115:87f2f5183dfb	3922	#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
Kojto	115:87f2f5183dfb	3923	#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
Kojto	115:87f2f5183dfb	3924	#define FMC_BCR3_WREN ((uint32_t)0x00001000) /!<Write enable bit /
Kojto	115:87f2f5183dfb	3925	#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
Kojto	115:87f2f5183dfb	3926	#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
Kojto	115:87f2f5183dfb	3927	#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
Kojto	115:87f2f5183dfb	3928	#define FMC_BCR3_CPSIZE ((uint32_t)0x00070000) /!<CRAM page size /
Kojto	115:87f2f5183dfb	3929	#define FMC_BCR3_CPSIZE_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3930	#define FMC_BCR3_CPSIZE_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3931	#define FMC_BCR3_CPSIZE_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3932	#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
Kojto	115:87f2f5183dfb	3933
Kojto	115:87f2f5183dfb	3934	/**************** Bit definition for FMC_BCR4 register *****************/
Kojto	115:87f2f5183dfb	3935	#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
Kojto	115:87f2f5183dfb	3936	#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
Kojto	115:87f2f5183dfb	3937
Kojto	115:87f2f5183dfb	3938	#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
Kojto	115:87f2f5183dfb	3939	#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3940	#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3941
Kojto	115:87f2f5183dfb	3942	#define FMC_BCR4_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
Kojto	115:87f2f5183dfb	3943	#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3944	#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3945
Kojto	115:87f2f5183dfb	3946	#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
Kojto	115:87f2f5183dfb	3947	#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
Kojto	115:87f2f5183dfb	3948	#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
Kojto	115:87f2f5183dfb	3949	#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
Kojto	115:87f2f5183dfb	3950	#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
Kojto	115:87f2f5183dfb	3951	#define FMC_BCR4_WREN ((uint32_t)0x00001000) /!<Write enable bit /
Kojto	115:87f2f5183dfb	3952	#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
Kojto	115:87f2f5183dfb	3953	#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
Kojto	115:87f2f5183dfb	3954	#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
Kojto	115:87f2f5183dfb	3955	#define FMC_BCR4_CPSIZE ((uint32_t)0x00070000) /!<CRAM page size /
Kojto	115:87f2f5183dfb	3956	#define FMC_BCR4_CPSIZE_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3957	#define FMC_BCR4_CPSIZE_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3958	#define FMC_BCR4_CPSIZE_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3959	#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
Kojto	115:87f2f5183dfb	3960
Kojto	115:87f2f5183dfb	3961	/**************** Bit definition for FMC_BTR1 register ****************/
Kojto	115:87f2f5183dfb	3962	#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	115:87f2f5183dfb	3963	#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3964	#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3965	#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3966	#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	3967
Kojto	115:87f2f5183dfb	3968	#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	115:87f2f5183dfb	3969	#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3970	#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3971	#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3972	#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	3973
Kojto	115:87f2f5183dfb	3974	#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	115:87f2f5183dfb	3975	#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3976	#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3977	#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3978	#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	3979	#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	3980	#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	3981	#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	3982	#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	3983
Kojto	115:87f2f5183dfb	3984	#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	115:87f2f5183dfb	3985	#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3986	#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3987	#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3988	#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	3989
Kojto	115:87f2f5183dfb	3990	#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
Kojto	115:87f2f5183dfb	3991	#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3992	#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3993	#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	3994	#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	3995
Kojto	115:87f2f5183dfb	3996	#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
Kojto	115:87f2f5183dfb	3997	#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	3998	#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	3999	#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4000	#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4001
Kojto	115:87f2f5183dfb	4002	#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
Kojto	115:87f2f5183dfb	4003	#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4004	#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4005
Kojto	115:87f2f5183dfb	4006	/**************** Bit definition for FMC_BTR2 register *****************/
Kojto	115:87f2f5183dfb	4007	#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	115:87f2f5183dfb	4008	#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4009	#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4010	#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4011	#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4012
Kojto	115:87f2f5183dfb	4013	#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	115:87f2f5183dfb	4014	#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4015	#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4016	#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4017	#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4018
Kojto	115:87f2f5183dfb	4019	#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	115:87f2f5183dfb	4020	#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4021	#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4022	#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4023	#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4024	#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4025	#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4026	#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4027	#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4028
Kojto	115:87f2f5183dfb	4029	#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	115:87f2f5183dfb	4030	#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4031	#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4032	#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4033	#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4034
Kojto	115:87f2f5183dfb	4035	#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
Kojto	115:87f2f5183dfb	4036	#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4037	#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4038	#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4039	#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4040
Kojto	115:87f2f5183dfb	4041	#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
Kojto	115:87f2f5183dfb	4042	#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4043	#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4044	#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4045	#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4046
Kojto	115:87f2f5183dfb	4047	#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
Kojto	115:87f2f5183dfb	4048	#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4049	#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4050
Kojto	115:87f2f5183dfb	4051	/***************** Bit definition for FMC_BTR3 register *****************/
Kojto	115:87f2f5183dfb	4052	#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	115:87f2f5183dfb	4053	#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4054	#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4055	#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4056	#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4057
Kojto	115:87f2f5183dfb	4058	#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	115:87f2f5183dfb	4059	#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4060	#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4061	#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4062	#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4063
Kojto	115:87f2f5183dfb	4064	#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	115:87f2f5183dfb	4065	#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4066	#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4067	#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4068	#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4069	#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4070	#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4071	#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4072	#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4073
Kojto	115:87f2f5183dfb	4074	#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	115:87f2f5183dfb	4075	#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4076	#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4077	#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4078	#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4079
Kojto	115:87f2f5183dfb	4080	#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
Kojto	115:87f2f5183dfb	4081	#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4082	#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4083	#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4084	#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4085
Kojto	115:87f2f5183dfb	4086	#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
Kojto	115:87f2f5183dfb	4087	#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4088	#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4089	#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4090	#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4091
Kojto	115:87f2f5183dfb	4092	#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
Kojto	115:87f2f5183dfb	4093	#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4094	#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4095
Kojto	115:87f2f5183dfb	4096	/**************** Bit definition for FMC_BTR4 register *****************/
Kojto	115:87f2f5183dfb	4097	#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	115:87f2f5183dfb	4098	#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4099	#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4100	#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4101	#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4102
Kojto	115:87f2f5183dfb	4103	#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	115:87f2f5183dfb	4104	#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4105	#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4106	#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4107	#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4108
Kojto	115:87f2f5183dfb	4109	#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	115:87f2f5183dfb	4110	#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4111	#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4112	#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4113	#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4114	#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4115	#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4116	#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4117	#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4118
Kojto	115:87f2f5183dfb	4119	#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	115:87f2f5183dfb	4120	#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4121	#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4122	#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4123	#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4124
Kojto	115:87f2f5183dfb	4125	#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
Kojto	115:87f2f5183dfb	4126	#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4127	#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4128	#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4129	#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4130
Kojto	115:87f2f5183dfb	4131	#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
Kojto	115:87f2f5183dfb	4132	#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4133	#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4134	#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4135	#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4136
Kojto	115:87f2f5183dfb	4137	#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
Kojto	115:87f2f5183dfb	4138	#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4139	#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4140
Kojto	115:87f2f5183dfb	4141	/**************** Bit definition for FMC_BWTR1 register ****************/
Kojto	115:87f2f5183dfb	4142	#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	115:87f2f5183dfb	4143	#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4144	#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4145	#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4146	#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4147
Kojto	115:87f2f5183dfb	4148	#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	115:87f2f5183dfb	4149	#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4150	#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4151	#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4152	#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4153
Kojto	115:87f2f5183dfb	4154	#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	115:87f2f5183dfb	4155	#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4156	#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4157	#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4158	#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4159	#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4160	#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4161	#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4162	#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4163
Kojto	115:87f2f5183dfb	4164	#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	115:87f2f5183dfb	4165	#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4166	#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4167	#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4168	#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4169
Kojto	115:87f2f5183dfb	4170	#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
Kojto	115:87f2f5183dfb	4171	#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4172	#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4173
Kojto	115:87f2f5183dfb	4174	/**************** Bit definition for FMC_BWTR2 register ****************/
Kojto	115:87f2f5183dfb	4175	#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	115:87f2f5183dfb	4176	#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4177	#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4178	#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4179	#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4180
Kojto	115:87f2f5183dfb	4181	#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	115:87f2f5183dfb	4182	#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4183	#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4184	#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4185	#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4186
Kojto	115:87f2f5183dfb	4187	#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	115:87f2f5183dfb	4188	#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4189	#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4190	#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4191	#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4192	#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4193	#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4194	#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4195	#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4196
Kojto	115:87f2f5183dfb	4197	#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	115:87f2f5183dfb	4198	#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4199	#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4200	#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4201	#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4202
Kojto	115:87f2f5183dfb	4203	#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
Kojto	115:87f2f5183dfb	4204	#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4205	#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4206
Kojto	115:87f2f5183dfb	4207	/**************** Bit definition for FMC_BWTR3 register ****************/
Kojto	115:87f2f5183dfb	4208	#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	115:87f2f5183dfb	4209	#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4210	#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4211	#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4212	#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4213
Kojto	115:87f2f5183dfb	4214	#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	115:87f2f5183dfb	4215	#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4216	#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4217	#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4218	#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4219
Kojto	115:87f2f5183dfb	4220	#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	115:87f2f5183dfb	4221	#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4222	#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4223	#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4224	#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4225	#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4226	#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4227	#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4228	#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4229
Kojto	115:87f2f5183dfb	4230	#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	115:87f2f5183dfb	4231	#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4232	#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4233	#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4234	#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4235
Kojto	115:87f2f5183dfb	4236	#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
Kojto	115:87f2f5183dfb	4237	#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4238	#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4239
Kojto	115:87f2f5183dfb	4240	/**************** Bit definition for FMC_BWTR4 register ****************/
Kojto	115:87f2f5183dfb	4241	#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	115:87f2f5183dfb	4242	#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4243	#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4244	#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4245	#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4246
Kojto	115:87f2f5183dfb	4247	#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	115:87f2f5183dfb	4248	#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4249	#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4250	#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4251	#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4252
Kojto	115:87f2f5183dfb	4253	#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	115:87f2f5183dfb	4254	#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4255	#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4256	#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4257	#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4258	#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4259	#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4260	#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4261	#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4262
Kojto	115:87f2f5183dfb	4263	#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	115:87f2f5183dfb	4264	#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4265	#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4266	#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4267	#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4268
Kojto	115:87f2f5183dfb	4269	#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
Kojto	115:87f2f5183dfb	4270	#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4271	#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4272
Kojto	115:87f2f5183dfb	4273	/**************** Bit definition for FMC_PCR register *****************/
Kojto	115:87f2f5183dfb	4274	#define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /!<Wait feature enable bit /
Kojto	115:87f2f5183dfb	4275	#define FMC_PCR_PBKEN ((uint32_t)0x00000004) /!<PC Card/NAND Flash memory bank enable bit /
Kojto	115:87f2f5183dfb	4276	#define FMC_PCR_PTYP ((uint32_t)0x00000008) /!<Memory type /
Kojto	115:87f2f5183dfb	4277
Kojto	115:87f2f5183dfb	4278	#define FMC_PCR_PWID ((uint32_t)0x00000030) /!<PWID[1:0] bits (NAND Flash databus width) /
Kojto	115:87f2f5183dfb	4279	#define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4280	#define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4281
Kojto	115:87f2f5183dfb	4282	#define FMC_PCR_ECCEN ((uint32_t)0x00000040) /!<ECC computation logic enable bit /
Kojto	115:87f2f5183dfb	4283
Kojto	115:87f2f5183dfb	4284	#define FMC_PCR_TCLR ((uint32_t)0x00001E00) /!<TCLR[3:0] bits (CLE to RE delay) /
Kojto	115:87f2f5183dfb	4285	#define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4286	#define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4287	#define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4288	#define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4289
Kojto	115:87f2f5183dfb	4290	#define FMC_PCR_TAR ((uint32_t)0x0001E000) /!<TAR[3:0] bits (ALE to RE delay) /
Kojto	115:87f2f5183dfb	4291	#define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4292	#define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4293	#define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4294	#define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4295
Kojto	115:87f2f5183dfb	4296	#define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /!<ECCPS[2:0] bits (ECC page size) /
Kojto	115:87f2f5183dfb	4297	#define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4298	#define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4299	#define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4300
Kojto	115:87f2f5183dfb	4301	/***************** Bit definition for FMC_SR register *****************/
Kojto	115:87f2f5183dfb	4302	#define FMC_SR_IRS ((uint32_t)0x01) /!<Interrupt Rising Edge status /
Kojto	115:87f2f5183dfb	4303	#define FMC_SR_ILS ((uint32_t)0x02) /!<Interrupt Level status /
Kojto	115:87f2f5183dfb	4304	#define FMC_SR_IFS ((uint32_t)0x04) /!<Interrupt Falling Edge status /
Kojto	115:87f2f5183dfb	4305	#define FMC_SR_IREN ((uint32_t)0x08) /!<Interrupt Rising Edge detection Enable bit /
Kojto	115:87f2f5183dfb	4306	#define FMC_SR_ILEN ((uint32_t)0x10) /!<Interrupt Level detection Enable bit /
Kojto	115:87f2f5183dfb	4307	#define FMC_SR_IFEN ((uint32_t)0x20) /!<Interrupt Falling Edge detection Enable bit /
Kojto	115:87f2f5183dfb	4308	#define FMC_SR_FEMPT ((uint32_t)0x40) /!<FIFO empty /
Kojto	115:87f2f5183dfb	4309
Kojto	115:87f2f5183dfb	4310	/**************** Bit definition for FMC_PMEM register ****************/
Kojto	115:87f2f5183dfb	4311	#define FMC_PMEM_MEMSET3 ((uint32_t)0x000000FF) /!<MEMSET3[7:0] bits (Common memory 3 setup time) /
Kojto	115:87f2f5183dfb	4312	#define FMC_PMEM_MEMSET3_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4313	#define FMC_PMEM_MEMSET3_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4314	#define FMC_PMEM_MEMSET3_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4315	#define FMC_PMEM_MEMSET3_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4316	#define FMC_PMEM_MEMSET3_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4317	#define FMC_PMEM_MEMSET3_5 ((uint32_t)0x00000020) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4318	#define FMC_PMEM_MEMSET3_6 ((uint32_t)0x00000040) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4319	#define FMC_PMEM_MEMSET3_7 ((uint32_t)0x00000080) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4320
Kojto	115:87f2f5183dfb	4321	#define FMC_PMEM_MEMWAIT3 ((uint32_t)0x0000FF00) /!<MEMWAIT3[7:0] bits (Common memory 3 wait time) /
Kojto	115:87f2f5183dfb	4322	#define FMC_PMEM_MEMWAIT3_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4323	#define FMC_PMEM_MEMWAIT3_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4324	#define FMC_PMEM_MEMWAIT3_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4325	#define FMC_PMEM_MEMWAIT3_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4326	#define FMC_PMEM_MEMWAIT3_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4327	#define FMC_PMEM_MEMWAIT3_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4328	#define FMC_PMEM_MEMWAIT3_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4329	#define FMC_PMEM_MEMWAIT3_7 ((uint32_t)0x00008000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4330
Kojto	115:87f2f5183dfb	4331	#define FMC_PMEM_MEMHOLD3 ((uint32_t)0x00FF0000) /!<MEMHOLD3[7:0] bits (Common memory 3 hold time) /
Kojto	115:87f2f5183dfb	4332	#define FMC_PMEM_MEMHOLD3_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4333	#define FMC_PMEM_MEMHOLD3_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4334	#define FMC_PMEM_MEMHOLD3_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4335	#define FMC_PMEM_MEMHOLD3_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4336	#define FMC_PMEM_MEMHOLD3_4 ((uint32_t)0x00100000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4337	#define FMC_PMEM_MEMHOLD3_5 ((uint32_t)0x00200000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4338	#define FMC_PMEM_MEMHOLD3_6 ((uint32_t)0x00400000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4339	#define FMC_PMEM_MEMHOLD3_7 ((uint32_t)0x00800000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4340
Kojto	115:87f2f5183dfb	4341	#define FMC_PMEM_MEMHIZ3 ((uint32_t)0xFF000000) /!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) /
Kojto	115:87f2f5183dfb	4342	#define FMC_PMEM_MEMHIZ3_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4343	#define FMC_PMEM_MEMHIZ3_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4344	#define FMC_PMEM_MEMHIZ3_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4345	#define FMC_PMEM_MEMHIZ3_3 ((uint32_t)0x08000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4346	#define FMC_PMEM_MEMHIZ3_4 ((uint32_t)0x10000000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4347	#define FMC_PMEM_MEMHIZ3_5 ((uint32_t)0x20000000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4348	#define FMC_PMEM_MEMHIZ3_6 ((uint32_t)0x40000000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4349	#define FMC_PMEM_MEMHIZ3_7 ((uint32_t)0x80000000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4350
Kojto	115:87f2f5183dfb	4351	/**************** Bit definition for FMC_PATT register ****************/
Kojto	115:87f2f5183dfb	4352	#define FMC_PATT_ATTSET3 ((uint32_t)0x000000FF) /!<ATTSET3[7:0] bits (Attribute memory 3 setup time) /
Kojto	115:87f2f5183dfb	4353	#define FMC_PATT_ATTSET3_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4354	#define FMC_PATT_ATTSET3_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4355	#define FMC_PATT_ATTSET3_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4356	#define FMC_PATT_ATTSET3_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4357	#define FMC_PATT_ATTSET3_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4358	#define FMC_PATT_ATTSET3_5 ((uint32_t)0x00000020) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4359	#define FMC_PATT_ATTSET3_6 ((uint32_t)0x00000040) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4360	#define FMC_PATT_ATTSET3_7 ((uint32_t)0x00000080) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4361
Kojto	115:87f2f5183dfb	4362	#define FMC_PATT_ATTWAIT3 ((uint32_t)0x0000FF00) /!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) /
Kojto	115:87f2f5183dfb	4363	#define FMC_PATT_ATTWAIT3_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4364	#define FMC_PATT_ATTWAIT3_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4365	#define FMC_PATT_ATTWAIT3_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4366	#define FMC_PATT_ATTWAIT3_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4367	#define FMC_PATT_ATTWAIT3_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4368	#define FMC_PATT_ATTWAIT3_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4369	#define FMC_PATT_ATTWAIT3_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4370	#define FMC_PATT_ATTWAIT3_7 ((uint32_t)0x00008000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4371
Kojto	115:87f2f5183dfb	4372	#define FMC_PATT_ATTHOLD3 ((uint32_t)0x00FF0000) /!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) /
Kojto	115:87f2f5183dfb	4373	#define FMC_PATT_ATTHOLD3_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4374	#define FMC_PATT_ATTHOLD3_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4375	#define FMC_PATT_ATTHOLD3_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4376	#define FMC_PATT_ATTHOLD3_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4377	#define FMC_PATT_ATTHOLD3_4 ((uint32_t)0x00100000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4378	#define FMC_PATT_ATTHOLD3_5 ((uint32_t)0x00200000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4379	#define FMC_PATT_ATTHOLD3_6 ((uint32_t)0x00400000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4380	#define FMC_PATT_ATTHOLD3_7 ((uint32_t)0x00800000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4381
Kojto	115:87f2f5183dfb	4382	#define FMC_PATT_ATTHIZ3 ((uint32_t)0xFF000000) /!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) /
Kojto	115:87f2f5183dfb	4383	#define FMC_PATT_ATTHIZ3_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4384	#define FMC_PATT_ATTHIZ3_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4385	#define FMC_PATT_ATTHIZ3_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4386	#define FMC_PATT_ATTHIZ3_3 ((uint32_t)0x08000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4387	#define FMC_PATT_ATTHIZ3_4 ((uint32_t)0x10000000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	4388	#define FMC_PATT_ATTHIZ3_5 ((uint32_t)0x20000000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	4389	#define FMC_PATT_ATTHIZ3_6 ((uint32_t)0x40000000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	4390	#define FMC_PATT_ATTHIZ3_7 ((uint32_t)0x80000000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	4391
Kojto	115:87f2f5183dfb	4392	/**************** Bit definition for FMC_ECCR register ****************/
Kojto	115:87f2f5183dfb	4393	#define FMC_ECCR_ECC3 ((uint32_t)0xFFFFFFFF) /!<ECC result /
Kojto	115:87f2f5183dfb	4394
Kojto	115:87f2f5183dfb	4395	/**************** Bit definition for FMC_SDCR1 register ****************/
Kojto	115:87f2f5183dfb	4396	#define FMC_SDCR1_NC ((uint32_t)0x00000003) /!<NC[1:0] bits (Number of column bits) /
Kojto	115:87f2f5183dfb	4397	#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4398	#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4399
Kojto	115:87f2f5183dfb	4400	#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /!<NR[1:0] bits (Number of row bits) /
Kojto	115:87f2f5183dfb	4401	#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4402	#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4403
Kojto	115:87f2f5183dfb	4404	#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /!<NR[1:0] bits (Number of row bits) /
Kojto	115:87f2f5183dfb	4405	#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4406	#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4407
Kojto	115:87f2f5183dfb	4408	#define FMC_SDCR1_NB ((uint32_t)0x00000040) /!<Number of internal bank /
Kojto	115:87f2f5183dfb	4409
Kojto	115:87f2f5183dfb	4410	#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /!<CAS[1:0] bits (CAS latency) /
Kojto	115:87f2f5183dfb	4411	#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4412	#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4413
Kojto	115:87f2f5183dfb	4414	#define FMC_SDCR1_WP ((uint32_t)0x00000200) /!<Write protection /
Kojto	115:87f2f5183dfb	4415
Kojto	115:87f2f5183dfb	4416	#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /!<SDRAM clock configuration /
Kojto	115:87f2f5183dfb	4417	#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4418	#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4419
Kojto	115:87f2f5183dfb	4420	#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /!<Read burst /
Kojto	115:87f2f5183dfb	4421
Kojto	115:87f2f5183dfb	4422	#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /!<Write protection /
Kojto	115:87f2f5183dfb	4423	#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4424	#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4425
Kojto	115:87f2f5183dfb	4426	/**************** Bit definition for FMC_SDCR2 register ****************/
Kojto	115:87f2f5183dfb	4427	#define FMC_SDCR2_NC ((uint32_t)0x00000003) /!<NC[1:0] bits (Number of column bits) /
Kojto	115:87f2f5183dfb	4428	#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4429	#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4430
Kojto	115:87f2f5183dfb	4431	#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /!<NR[1:0] bits (Number of row bits) /
Kojto	115:87f2f5183dfb	4432	#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4433	#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4434
Kojto	115:87f2f5183dfb	4435	#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /!<NR[1:0] bits (Number of row bits) /
Kojto	115:87f2f5183dfb	4436	#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4437	#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4438
Kojto	115:87f2f5183dfb	4439	#define FMC_SDCR2_NB ((uint32_t)0x00000040) /!<Number of internal bank /
Kojto	115:87f2f5183dfb	4440
Kojto	115:87f2f5183dfb	4441	#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /!<CAS[1:0] bits (CAS latency) /
Kojto	115:87f2f5183dfb	4442	#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4443	#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4444
Kojto	115:87f2f5183dfb	4445	#define FMC_SDCR2_WP ((uint32_t)0x00000200) /!<Write protection /
Kojto	115:87f2f5183dfb	4446
Kojto	115:87f2f5183dfb	4447	#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /!<SDCLK[1:0] (SDRAM clock configuration) /
Kojto	115:87f2f5183dfb	4448	#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4449	#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4450
Kojto	115:87f2f5183dfb	4451	#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /!<Read burst /
Kojto	115:87f2f5183dfb	4452
Kojto	115:87f2f5183dfb	4453	#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /!<RPIPE[1:0](Read pipe) /
Kojto	115:87f2f5183dfb	4454	#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4455	#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4456
Kojto	115:87f2f5183dfb	4457	/**************** Bit definition for FMC_SDTR1 register ****************/
Kojto	115:87f2f5183dfb	4458	#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /!<TMRD[3:0] bits (Load mode register to active) /
Kojto	115:87f2f5183dfb	4459	#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4460	#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4461	#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4462	#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4463
Kojto	115:87f2f5183dfb	4464	#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /!<TXSR[3:0] bits (Exit self refresh) /
Kojto	115:87f2f5183dfb	4465	#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4466	#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4467	#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4468	#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4469
Kojto	115:87f2f5183dfb	4470	#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /!<TRAS[3:0] bits (Self refresh time) /
Kojto	115:87f2f5183dfb	4471	#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4472	#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4473	#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4474	#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4475
Kojto	115:87f2f5183dfb	4476	#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /!<TRC[2:0] bits (Row cycle delay) /
Kojto	115:87f2f5183dfb	4477	#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4478	#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4479	#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4480
Kojto	115:87f2f5183dfb	4481	#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /!<TRC[2:0] bits (Write recovery delay) /
Kojto	115:87f2f5183dfb	4482	#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4483	#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4484	#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4485
Kojto	115:87f2f5183dfb	4486	#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /!<TRP[2:0] bits (Row precharge delay) /
Kojto	115:87f2f5183dfb	4487	#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4488	#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4489	#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4490
Kojto	115:87f2f5183dfb	4491	#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /!<TRP[2:0] bits (Row to column delay) /
Kojto	115:87f2f5183dfb	4492	#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4493	#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4494	#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4495
Kojto	115:87f2f5183dfb	4496	/**************** Bit definition for FMC_SDTR2 register ****************/
Kojto	115:87f2f5183dfb	4497	#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /!<TMRD[3:0] bits (Load mode register to active) /
Kojto	115:87f2f5183dfb	4498	#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4499	#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4500	#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4501	#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4502
Kojto	115:87f2f5183dfb	4503	#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /!<TXSR[3:0] bits (Exit self refresh) /
Kojto	115:87f2f5183dfb	4504	#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4505	#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4506	#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4507	#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4508
Kojto	115:87f2f5183dfb	4509	#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /!<TRAS[3:0] bits (Self refresh time) /
Kojto	115:87f2f5183dfb	4510	#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4511	#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4512	#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4513	#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4514
Kojto	115:87f2f5183dfb	4515	#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /!<TRC[2:0] bits (Row cycle delay) /
Kojto	115:87f2f5183dfb	4516	#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4517	#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4518	#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4519
Kojto	115:87f2f5183dfb	4520	#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /!<TRC[2:0] bits (Write recovery delay) /
Kojto	115:87f2f5183dfb	4521	#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4522	#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4523	#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4524
Kojto	115:87f2f5183dfb	4525	#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /!<TRP[2:0] bits (Row precharge delay) /
Kojto	115:87f2f5183dfb	4526	#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4527	#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4528	#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4529
Kojto	115:87f2f5183dfb	4530	#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /!<TRP[2:0] bits (Row to column delay) /
Kojto	115:87f2f5183dfb	4531	#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4532	#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4533	#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4534
Kojto	115:87f2f5183dfb	4535	/**************** Bit definition for FMC_SDCMR register ****************/
Kojto	115:87f2f5183dfb	4536	#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /!<MODE[2:0] bits (Command mode) /
Kojto	115:87f2f5183dfb	4537	#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4538	#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4539	#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4540
Kojto	115:87f2f5183dfb	4541	#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /!<Command target 2 /
Kojto	115:87f2f5183dfb	4542
Kojto	115:87f2f5183dfb	4543	#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /!<Command target 1 /
Kojto	115:87f2f5183dfb	4544
Kojto	115:87f2f5183dfb	4545	#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /!<NRFS[3:0] bits (Number of auto-refresh) /
Kojto	115:87f2f5183dfb	4546	#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4547	#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4548	#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /!<Bit 2 /
Kojto	115:87f2f5183dfb	4549	#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /!<Bit 3 /
Kojto	115:87f2f5183dfb	4550
Kojto	115:87f2f5183dfb	4551	#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /!<MRD[12:0] bits (Mode register definition) /
Kojto	115:87f2f5183dfb	4552
Kojto	115:87f2f5183dfb	4553	/**************** Bit definition for FMC_SDRTR register ****************/
Kojto	115:87f2f5183dfb	4554	#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /!<Clear refresh error flag /
Kojto	115:87f2f5183dfb	4555
Kojto	115:87f2f5183dfb	4556	#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /!<COUNT[12:0] bits (Refresh timer count) /
Kojto	115:87f2f5183dfb	4557
Kojto	115:87f2f5183dfb	4558	#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /!<RES interupt enable /
Kojto	115:87f2f5183dfb	4559
Kojto	115:87f2f5183dfb	4560	/**************** Bit definition for FMC_SDSR register ****************/
Kojto	115:87f2f5183dfb	4561	#define FMC_SDSR_RE ((uint32_t)0x00000001) /!<Refresh error flag /
Kojto	115:87f2f5183dfb	4562
Kojto	115:87f2f5183dfb	4563	#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /!<MODES1[1:0]bits (Status mode for bank 1) /
Kojto	115:87f2f5183dfb	4564	#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4565	#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4566
Kojto	115:87f2f5183dfb	4567	#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /!<MODES2[1:0]bits (Status mode for bank 2) /
Kojto	115:87f2f5183dfb	4568	#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /!<Bit 0 /
Kojto	115:87f2f5183dfb	4569	#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /!<Bit 1 /
Kojto	115:87f2f5183dfb	4570
Kojto	115:87f2f5183dfb	4571	#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /!<Busy status /
Kojto	115:87f2f5183dfb	4572
Kojto	115:87f2f5183dfb	4573	/******************************************************************************/
Kojto	115:87f2f5183dfb	4574	/* */
Kojto	115:87f2f5183dfb	4575	/* General Purpose I/O */
Kojto	115:87f2f5183dfb	4576	/* */
Kojto	115:87f2f5183dfb	4577	/******************************************************************************/
Kojto	115:87f2f5183dfb	4578	/**************** Bits definition for GPIO_MODER register ***************/
Kojto	115:87f2f5183dfb	4579	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto	115:87f2f5183dfb	4580	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	4581	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	4582
Kojto	115:87f2f5183dfb	4583	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto	115:87f2f5183dfb	4584	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	4585	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	4586
Kojto	115:87f2f5183dfb	4587	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto	115:87f2f5183dfb	4588	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	4589	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	4590
Kojto	115:87f2f5183dfb	4591	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto	115:87f2f5183dfb	4592	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	4593	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	4594
Kojto	115:87f2f5183dfb	4595	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto	115:87f2f5183dfb	4596	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	4597	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	4598
Kojto	115:87f2f5183dfb	4599	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto	115:87f2f5183dfb	4600	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	4601	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	4602
Kojto	115:87f2f5183dfb	4603	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto	115:87f2f5183dfb	4604	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	4605	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	4606
Kojto	115:87f2f5183dfb	4607	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto	115:87f2f5183dfb	4608	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	4609	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	4610
Kojto	115:87f2f5183dfb	4611	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto	115:87f2f5183dfb	4612	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	4613	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	4614
Kojto	115:87f2f5183dfb	4615	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto	115:87f2f5183dfb	4616	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	4617	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	4618
Kojto	115:87f2f5183dfb	4619	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto	115:87f2f5183dfb	4620	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	4621	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	4622
Kojto	115:87f2f5183dfb	4623	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto	115:87f2f5183dfb	4624	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	4625	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	4626
Kojto	115:87f2f5183dfb	4627	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto	115:87f2f5183dfb	4628	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	4629	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	4630
Kojto	115:87f2f5183dfb	4631	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto	115:87f2f5183dfb	4632	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	4633	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	4634
Kojto	115:87f2f5183dfb	4635	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto	115:87f2f5183dfb	4636	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	4637	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	4638
Kojto	115:87f2f5183dfb	4639	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto	115:87f2f5183dfb	4640	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	4641	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	4642
Kojto	115:87f2f5183dfb	4643	/**************** Bits definition for GPIO_OTYPER register **************/
Kojto	115:87f2f5183dfb	4644	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	4645	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	4646	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	4647	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	4648	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	4649	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	4650	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	4651	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	4652	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	4653	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	4654	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	4655	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	4656	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	4657	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	4658	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	4659	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	4660
Kojto	115:87f2f5183dfb	4661	/**************** Bits definition for GPIO_OSPEEDR register *************/
Kojto	115:87f2f5183dfb	4662	#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
Kojto	115:87f2f5183dfb	4663	#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	4664	#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	4665
Kojto	115:87f2f5183dfb	4666	#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto	115:87f2f5183dfb	4667	#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	4668	#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	4669
Kojto	115:87f2f5183dfb	4670	#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
Kojto	115:87f2f5183dfb	4671	#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	4672	#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	4673
Kojto	115:87f2f5183dfb	4674	#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto	115:87f2f5183dfb	4675	#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	4676	#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	4677
Kojto	115:87f2f5183dfb	4678	#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
Kojto	115:87f2f5183dfb	4679	#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	4680	#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	4681
Kojto	115:87f2f5183dfb	4682	#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto	115:87f2f5183dfb	4683	#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	4684	#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	4685
Kojto	115:87f2f5183dfb	4686	#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
Kojto	115:87f2f5183dfb	4687	#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	4688	#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	4689
Kojto	115:87f2f5183dfb	4690	#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto	115:87f2f5183dfb	4691	#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	4692	#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	4693
Kojto	115:87f2f5183dfb	4694	#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
Kojto	115:87f2f5183dfb	4695	#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	4696	#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	4697
Kojto	115:87f2f5183dfb	4698	#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto	115:87f2f5183dfb	4699	#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	4700	#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	4701
Kojto	115:87f2f5183dfb	4702	#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
Kojto	115:87f2f5183dfb	4703	#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	4704	#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	4705
Kojto	115:87f2f5183dfb	4706	#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto	115:87f2f5183dfb	4707	#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	4708	#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	4709
Kojto	115:87f2f5183dfb	4710	#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
Kojto	115:87f2f5183dfb	4711	#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	4712	#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	4713
Kojto	115:87f2f5183dfb	4714	#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto	115:87f2f5183dfb	4715	#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	4716	#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	4717
Kojto	115:87f2f5183dfb	4718	#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
Kojto	115:87f2f5183dfb	4719	#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	4720	#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	4721
Kojto	115:87f2f5183dfb	4722	#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto	115:87f2f5183dfb	4723	#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	4724	#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	4725
Kojto	115:87f2f5183dfb	4726	/**************** Bits definition for GPIO_PUPDR register ***************/
Kojto	115:87f2f5183dfb	4727	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto	115:87f2f5183dfb	4728	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	4729	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	4730
Kojto	115:87f2f5183dfb	4731	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto	115:87f2f5183dfb	4732	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	4733	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	4734
Kojto	115:87f2f5183dfb	4735	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto	115:87f2f5183dfb	4736	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	4737	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	4738
Kojto	115:87f2f5183dfb	4739	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto	115:87f2f5183dfb	4740	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	4741	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	4742
Kojto	115:87f2f5183dfb	4743	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto	115:87f2f5183dfb	4744	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	4745	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	4746
Kojto	115:87f2f5183dfb	4747	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto	115:87f2f5183dfb	4748	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	4749	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	4750
Kojto	115:87f2f5183dfb	4751	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto	115:87f2f5183dfb	4752	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	4753	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	4754
Kojto	115:87f2f5183dfb	4755	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto	115:87f2f5183dfb	4756	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	4757	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	4758
Kojto	115:87f2f5183dfb	4759	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto	115:87f2f5183dfb	4760	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	4761	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	4762
Kojto	115:87f2f5183dfb	4763	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto	115:87f2f5183dfb	4764	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	4765	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	4766
Kojto	115:87f2f5183dfb	4767	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto	115:87f2f5183dfb	4768	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	4769	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	4770
Kojto	115:87f2f5183dfb	4771	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto	115:87f2f5183dfb	4772	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	4773	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	4774
Kojto	115:87f2f5183dfb	4775	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto	115:87f2f5183dfb	4776	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	4777	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	4778
Kojto	115:87f2f5183dfb	4779	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto	115:87f2f5183dfb	4780	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	4781	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	4782
Kojto	115:87f2f5183dfb	4783	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto	115:87f2f5183dfb	4784	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	4785	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	4786
Kojto	115:87f2f5183dfb	4787	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto	115:87f2f5183dfb	4788	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	4789	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	4790
Kojto	115:87f2f5183dfb	4791	/**************** Bits definition for GPIO_IDR register *****************/
Kojto	115:87f2f5183dfb	4792	#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	4793	#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	4794	#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	4795	#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	4796	#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	4797	#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	4798	#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	4799	#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	4800	#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	4801	#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	4802	#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	4803	#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	4804	#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	4805	#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	4806	#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	4807	#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	4808
Kojto	115:87f2f5183dfb	4809	/**************** Bits definition for GPIO_ODR register *****************/
Kojto	115:87f2f5183dfb	4810	#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	4811	#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	4812	#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	4813	#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	4814	#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	4815	#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	4816	#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	4817	#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	4818	#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	4819	#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	4820	#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	4821	#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	4822	#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	4823	#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	4824	#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	4825	#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	4826
Kojto	115:87f2f5183dfb	4827	/**************** Bits definition for GPIO_BSRR register ****************/
Kojto	115:87f2f5183dfb	4828	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	4829	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	4830	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	4831	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	4832	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	4833	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	4834	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	4835	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	4836	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	4837	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	4838	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	4839	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	4840	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	4841	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	4842	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	4843	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	4844	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	4845	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	4846	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	4847	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	4848	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	4849	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	4850	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	4851	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	4852	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	4853	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	4854	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	4855	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	4856	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	4857	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	4858	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	4859	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	4860
Kojto	115:87f2f5183dfb	4861	/**************** Bit definition for GPIO_LCKR register *******************/
Kojto	115:87f2f5183dfb	4862	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	4863	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	4864	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	4865	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	4866	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	4867	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	4868	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	4869	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	4870	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	4871	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	4872	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	4873	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	4874	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	4875	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	4876	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	4877	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	4878	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	4879
Kojto	115:87f2f5183dfb	4880	/******************************************************************************/
Kojto	115:87f2f5183dfb	4881	/* */
Kojto	115:87f2f5183dfb	4882	/* Inter-integrated Circuit Interface (I2C) */
Kojto	115:87f2f5183dfb	4883	/* */
Kojto	115:87f2f5183dfb	4884	/******************************************************************************/
Kojto	115:87f2f5183dfb	4885	/***************** Bit definition for I2C_CR1 register *****************/
Kojto	115:87f2f5183dfb	4886	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
Kojto	115:87f2f5183dfb	4887	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
Kojto	115:87f2f5183dfb	4888	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
Kojto	115:87f2f5183dfb	4889	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
Kojto	115:87f2f5183dfb	4890	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
Kojto	115:87f2f5183dfb	4891	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
Kojto	115:87f2f5183dfb	4892	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
Kojto	115:87f2f5183dfb	4893	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
Kojto	115:87f2f5183dfb	4894	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
Kojto	115:87f2f5183dfb	4895	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
Kojto	115:87f2f5183dfb	4896	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
Kojto	115:87f2f5183dfb	4897	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
Kojto	115:87f2f5183dfb	4898	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
Kojto	115:87f2f5183dfb	4899	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
Kojto	115:87f2f5183dfb	4900	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
Kojto	115:87f2f5183dfb	4901	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
Kojto	115:87f2f5183dfb	4902	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
Kojto	115:87f2f5183dfb	4903	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
Kojto	115:87f2f5183dfb	4904	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
Kojto	115:87f2f5183dfb	4905	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
Kojto	115:87f2f5183dfb	4906	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
Kojto	115:87f2f5183dfb	4907
Kojto	115:87f2f5183dfb	4908	/**************** Bit definition for I2C_CR2 register ******************/
Kojto	115:87f2f5183dfb	4909	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
Kojto	115:87f2f5183dfb	4910	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
Kojto	115:87f2f5183dfb	4911	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
Kojto	115:87f2f5183dfb	4912	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
Kojto	115:87f2f5183dfb	4913	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
Kojto	115:87f2f5183dfb	4914	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
Kojto	115:87f2f5183dfb	4915	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
Kojto	115:87f2f5183dfb	4916	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
Kojto	115:87f2f5183dfb	4917	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
Kojto	115:87f2f5183dfb	4918	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
Kojto	115:87f2f5183dfb	4919	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
Kojto	115:87f2f5183dfb	4920
Kojto	115:87f2f5183dfb	4921	/***************** Bit definition for I2C_OAR1 register ****************/
Kojto	115:87f2f5183dfb	4922	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
Kojto	115:87f2f5183dfb	4923	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
Kojto	115:87f2f5183dfb	4924	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
Kojto	115:87f2f5183dfb	4925
Kojto	115:87f2f5183dfb	4926	/***************** Bit definition for I2C_OAR2 register ****************/
Kojto	115:87f2f5183dfb	4927	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
Kojto	115:87f2f5183dfb	4928	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
Kojto	115:87f2f5183dfb	4929	#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /!< No mask /
Kojto	115:87f2f5183dfb	4930	#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /!< OA2[1] is masked, Only OA2[7:2] are compared /
Kojto	115:87f2f5183dfb	4931	#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /!< OA2[2:1] is masked, Only OA2[7:3] are compared /
Kojto	115:87f2f5183dfb	4932	#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /!< OA2[3:1] is masked, Only OA2[7:4] are compared /
Kojto	115:87f2f5183dfb	4933	#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /!< OA2[4:1] is masked, Only OA2[7:5] are compared /
Kojto	115:87f2f5183dfb	4934	#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /!< OA2[5:1] is masked, Only OA2[7:6] are compared /
Kojto	115:87f2f5183dfb	4935	#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /!< OA2[6:1] is masked, Only OA2[7] are compared /
Kojto	115:87f2f5183dfb	4936	#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /!< OA2[7:1] is masked, No comparison is done /
Kojto	115:87f2f5183dfb	4937	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
Kojto	115:87f2f5183dfb	4938
Kojto	115:87f2f5183dfb	4939	/***************** Bit definition for I2C_TIMINGR register *****************/
Kojto	115:87f2f5183dfb	4940	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
Kojto	115:87f2f5183dfb	4941	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
Kojto	115:87f2f5183dfb	4942	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
Kojto	115:87f2f5183dfb	4943	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
Kojto	115:87f2f5183dfb	4944	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
Kojto	115:87f2f5183dfb	4945
Kojto	115:87f2f5183dfb	4946	/***************** Bit definition for I2C_TIMEOUTR register *****************/
Kojto	115:87f2f5183dfb	4947	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
Kojto	115:87f2f5183dfb	4948	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
Kojto	115:87f2f5183dfb	4949	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
Kojto	115:87f2f5183dfb	4950	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B /
Kojto	115:87f2f5183dfb	4951	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
Kojto	115:87f2f5183dfb	4952
Kojto	115:87f2f5183dfb	4953	/**************** Bit definition for I2C_ISR register *******************/
Kojto	115:87f2f5183dfb	4954	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
Kojto	115:87f2f5183dfb	4955	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
Kojto	115:87f2f5183dfb	4956	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
Kojto	115:87f2f5183dfb	4957	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode) /
Kojto	115:87f2f5183dfb	4958	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
Kojto	115:87f2f5183dfb	4959	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
Kojto	115:87f2f5183dfb	4960	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
Kojto	115:87f2f5183dfb	4961	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
Kojto	115:87f2f5183dfb	4962	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
Kojto	115:87f2f5183dfb	4963	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
Kojto	115:87f2f5183dfb	4964	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
Kojto	115:87f2f5183dfb	4965	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
Kojto	115:87f2f5183dfb	4966	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
Kojto	115:87f2f5183dfb	4967	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
Kojto	115:87f2f5183dfb	4968	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
Kojto	115:87f2f5183dfb	4969	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
Kojto	115:87f2f5183dfb	4970	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
Kojto	115:87f2f5183dfb	4971
Kojto	115:87f2f5183dfb	4972	/**************** Bit definition for I2C_ICR register *******************/
Kojto	115:87f2f5183dfb	4973	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
Kojto	115:87f2f5183dfb	4974	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
Kojto	115:87f2f5183dfb	4975	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
Kojto	115:87f2f5183dfb	4976	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
Kojto	115:87f2f5183dfb	4977	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
Kojto	115:87f2f5183dfb	4978	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
Kojto	115:87f2f5183dfb	4979	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
Kojto	115:87f2f5183dfb	4980	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
Kojto	115:87f2f5183dfb	4981	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
Kojto	115:87f2f5183dfb	4982
Kojto	115:87f2f5183dfb	4983	/**************** Bit definition for I2C_PECR register *******************/
Kojto	115:87f2f5183dfb	4984	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
Kojto	115:87f2f5183dfb	4985
Kojto	115:87f2f5183dfb	4986	/**************** Bit definition for I2C_RXDR register *******************/
Kojto	115:87f2f5183dfb	4987	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
Kojto	115:87f2f5183dfb	4988
Kojto	115:87f2f5183dfb	4989	/**************** Bit definition for I2C_TXDR register *******************/
Kojto	115:87f2f5183dfb	4990	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
Kojto	115:87f2f5183dfb	4991
Kojto	115:87f2f5183dfb	4992
Kojto	115:87f2f5183dfb	4993	/******************************************************************************/
Kojto	115:87f2f5183dfb	4994	/* */
Kojto	115:87f2f5183dfb	4995	/* Independent WATCHDOG */
Kojto	115:87f2f5183dfb	4996	/* */
Kojto	115:87f2f5183dfb	4997	/******************************************************************************/
Kojto	115:87f2f5183dfb	4998	/***************** Bit definition for IWDG_KR register ******************/
Kojto	115:87f2f5183dfb	4999	#define IWDG_KR_KEY ((uint32_t)0xFFFF) /!<Key value (write only, read 0000h) /
Kojto	115:87f2f5183dfb	5000
Kojto	115:87f2f5183dfb	5001	/***************** Bit definition for IWDG_PR register ******************/
Kojto	115:87f2f5183dfb	5002	#define IWDG_PR_PR ((uint32_t)0x07) /!<PR[2:0] (Prescaler divider) /
Kojto	115:87f2f5183dfb	5003	#define IWDG_PR_PR_0 ((uint32_t)0x01) /!<Bit 0 /
Kojto	115:87f2f5183dfb	5004	#define IWDG_PR_PR_1 ((uint32_t)0x02) /!<Bit 1 /
Kojto	115:87f2f5183dfb	5005	#define IWDG_PR_PR_2 ((uint32_t)0x04) /!<Bit 2 /
Kojto	115:87f2f5183dfb	5006
Kojto	115:87f2f5183dfb	5007	/***************** Bit definition for IWDG_RLR register *****************/
Kojto	115:87f2f5183dfb	5008	#define IWDG_RLR_RL ((uint32_t)0x0FFF) /!<Watchdog counter reload value /
Kojto	115:87f2f5183dfb	5009
Kojto	115:87f2f5183dfb	5010	/***************** Bit definition for IWDG_SR register ******************/
Kojto	115:87f2f5183dfb	5011	#define IWDG_SR_PVU ((uint32_t)0x01) /!< Watchdog prescaler value update /
Kojto	115:87f2f5183dfb	5012	#define IWDG_SR_RVU ((uint32_t)0x02) /!< Watchdog counter reload value update /
Kojto	115:87f2f5183dfb	5013	#define IWDG_SR_WVU ((uint32_t)0x04) /!< Watchdog counter window value update /
Kojto	115:87f2f5183dfb	5014
Kojto	115:87f2f5183dfb	5015	/***************** Bit definition for IWDG_KR register ******************/
Kojto	115:87f2f5183dfb	5016	#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /!< Watchdog counter window value /
Kojto	115:87f2f5183dfb	5017
Kojto	115:87f2f5183dfb	5018	/******************************************************************************/
Kojto	115:87f2f5183dfb	5019	/* */
Kojto	115:87f2f5183dfb	5020	/* LCD-TFT Display Controller (LTDC) */
Kojto	115:87f2f5183dfb	5021	/* */
Kojto	115:87f2f5183dfb	5022	/******************************************************************************/
Kojto	115:87f2f5183dfb	5023
Kojto	115:87f2f5183dfb	5024	/****************** Bit definition for LTDC_SSCR register ***************/
Kojto	115:87f2f5183dfb	5025
Kojto	115:87f2f5183dfb	5026	#define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /!< Vertical Synchronization Height /
Kojto	115:87f2f5183dfb	5027	#define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /!< Horizontal Synchronization Width /
Kojto	115:87f2f5183dfb	5028
Kojto	115:87f2f5183dfb	5029	/****************** Bit definition for LTDC_BPCR register ***************/
Kojto	115:87f2f5183dfb	5030
Kojto	115:87f2f5183dfb	5031	#define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /!< Accumulated Vertical Back Porch /
Kojto	115:87f2f5183dfb	5032	#define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /!< Accumulated Horizontal Back Porch /
Kojto	115:87f2f5183dfb	5033
Kojto	115:87f2f5183dfb	5034	/****************** Bit definition for LTDC_AWCR register ***************/
Kojto	115:87f2f5183dfb	5035
Kojto	115:87f2f5183dfb	5036	#define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /!< Accumulated Active heigh /
Kojto	115:87f2f5183dfb	5037	#define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /!< Accumulated Active Width /
Kojto	115:87f2f5183dfb	5038
Kojto	115:87f2f5183dfb	5039	/****************** Bit definition for LTDC_TWCR register ***************/
Kojto	115:87f2f5183dfb	5040
Kojto	115:87f2f5183dfb	5041	#define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /!< Total Heigh /
Kojto	115:87f2f5183dfb	5042	#define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /!< Total Width /
Kojto	115:87f2f5183dfb	5043
Kojto	115:87f2f5183dfb	5044	/****************** Bit definition for LTDC_GCR register ****************/
Kojto	115:87f2f5183dfb	5045
Kojto	115:87f2f5183dfb	5046	#define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /!< LCD-TFT controller enable bit /
Kojto	115:87f2f5183dfb	5047	#define LTDC_GCR_DBW ((uint32_t)0x00000070) /!< Dither Blue Width /
Kojto	115:87f2f5183dfb	5048	#define LTDC_GCR_DGW ((uint32_t)0x00000700) /!< Dither Green Width /
Kojto	115:87f2f5183dfb	5049	#define LTDC_GCR_DRW ((uint32_t)0x00007000) /!< Dither Red Width /
Kojto	115:87f2f5183dfb	5050	#define LTDC_GCR_DTEN ((uint32_t)0x00010000) /!< Dither Enable /
Kojto	115:87f2f5183dfb	5051	#define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /!< Pixel Clock Polarity /
Kojto	115:87f2f5183dfb	5052	#define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /!< Data Enable Polarity /
Kojto	115:87f2f5183dfb	5053	#define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /!< Vertical Synchronization Polarity /
Kojto	115:87f2f5183dfb	5054	#define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /!< Horizontal Synchronization Polarity /
Kojto	115:87f2f5183dfb	5055
Kojto	115:87f2f5183dfb	5056	/****************** Bit definition for LTDC_SRCR register ***************/
Kojto	115:87f2f5183dfb	5057
Kojto	115:87f2f5183dfb	5058	#define LTDC_SRCR_IMR ((uint32_t)0x00000001) /!< Immediate Reload /
Kojto	115:87f2f5183dfb	5059	#define LTDC_SRCR_VBR ((uint32_t)0x00000002) /!< Vertical Blanking Reload /
Kojto	115:87f2f5183dfb	5060
Kojto	115:87f2f5183dfb	5061	/****************** Bit definition for LTDC_BCCR register ***************/
Kojto	115:87f2f5183dfb	5062
Kojto	115:87f2f5183dfb	5063	#define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /!< Background Blue value /
Kojto	115:87f2f5183dfb	5064	#define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /!< Background Green value /
Kojto	115:87f2f5183dfb	5065	#define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /!< Background Red value /
Kojto	115:87f2f5183dfb	5066
Kojto	115:87f2f5183dfb	5067	/****************** Bit definition for LTDC_IER register ****************/
Kojto	115:87f2f5183dfb	5068
Kojto	115:87f2f5183dfb	5069	#define LTDC_IER_LIE ((uint32_t)0x00000001) /!< Line Interrupt Enable /
Kojto	115:87f2f5183dfb	5070	#define LTDC_IER_FUIE ((uint32_t)0x00000002) /!< FIFO Underrun Interrupt Enable /
Kojto	115:87f2f5183dfb	5071	#define LTDC_IER_TERRIE ((uint32_t)0x00000004) /!< Transfer Error Interrupt Enable /
Kojto	115:87f2f5183dfb	5072	#define LTDC_IER_RRIE ((uint32_t)0x00000008) /!< Register Reload interrupt enable /
Kojto	115:87f2f5183dfb	5073
Kojto	115:87f2f5183dfb	5074	/****************** Bit definition for LTDC_ISR register ****************/
Kojto	115:87f2f5183dfb	5075
Kojto	115:87f2f5183dfb	5076	#define LTDC_ISR_LIF ((uint32_t)0x00000001) /!< Line Interrupt Flag /
Kojto	115:87f2f5183dfb	5077	#define LTDC_ISR_FUIF ((uint32_t)0x00000002) /!< FIFO Underrun Interrupt Flag /
Kojto	115:87f2f5183dfb	5078	#define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /!< Transfer Error Interrupt Flag /
Kojto	115:87f2f5183dfb	5079	#define LTDC_ISR_RRIF ((uint32_t)0x00000008) /!< Register Reload interrupt Flag /
Kojto	115:87f2f5183dfb	5080
Kojto	115:87f2f5183dfb	5081	/****************** Bit definition for LTDC_ICR register ****************/
Kojto	115:87f2f5183dfb	5082
Kojto	115:87f2f5183dfb	5083	#define LTDC_ICR_CLIF ((uint32_t)0x00000001) /!< Clears the Line Interrupt Flag /
Kojto	115:87f2f5183dfb	5084	#define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /!< Clears the FIFO Underrun Interrupt Flag /
Kojto	115:87f2f5183dfb	5085	#define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /!< Clears the Transfer Error Interrupt Flag /
Kojto	115:87f2f5183dfb	5086	#define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /!< Clears Register Reload interrupt Flag /
Kojto	115:87f2f5183dfb	5087
Kojto	115:87f2f5183dfb	5088	/****************** Bit definition for LTDC_LIPCR register **************/
Kojto	115:87f2f5183dfb	5089
Kojto	115:87f2f5183dfb	5090	#define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /!< Line Interrupt Position /
Kojto	115:87f2f5183dfb	5091
Kojto	115:87f2f5183dfb	5092	/****************** Bit definition for LTDC_CPSR register ***************/
Kojto	115:87f2f5183dfb	5093
Kojto	115:87f2f5183dfb	5094	#define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /!< Current Y Position /
Kojto	115:87f2f5183dfb	5095	#define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /!< Current X Position /
Kojto	115:87f2f5183dfb	5096
Kojto	115:87f2f5183dfb	5097	/****************** Bit definition for LTDC_CDSR register ***************/
Kojto	115:87f2f5183dfb	5098
Kojto	115:87f2f5183dfb	5099	#define LTDC_CDSR_VDES ((uint32_t)0x00000001) /!< Vertical Data Enable Status /
Kojto	115:87f2f5183dfb	5100	#define LTDC_CDSR_HDES ((uint32_t)0x00000002) /!< Horizontal Data Enable Status /
Kojto	115:87f2f5183dfb	5101	#define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /!< Vertical Synchronization Status /
Kojto	115:87f2f5183dfb	5102	#define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /!< Horizontal Synchronization Status /
Kojto	115:87f2f5183dfb	5103
Kojto	115:87f2f5183dfb	5104	/****************** Bit definition for LTDC_LxCR register ***************/
Kojto	115:87f2f5183dfb	5105
Kojto	115:87f2f5183dfb	5106	#define LTDC_LxCR_LEN ((uint32_t)0x00000001) /!< Layer Enable /
Kojto	115:87f2f5183dfb	5107	#define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /!< Color Keying Enable /
Kojto	115:87f2f5183dfb	5108	#define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /!< Color Lockup Table Enable /
Kojto	115:87f2f5183dfb	5109
Kojto	115:87f2f5183dfb	5110	/****************** Bit definition for LTDC_LxWHPCR register ************/
Kojto	115:87f2f5183dfb	5111
Kojto	115:87f2f5183dfb	5112	#define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /!< Window Horizontal Start Position /
Kojto	115:87f2f5183dfb	5113	#define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /!< Window Horizontal Stop Position /
Kojto	115:87f2f5183dfb	5114
Kojto	115:87f2f5183dfb	5115	/****************** Bit definition for LTDC_LxWVPCR register ************/
Kojto	115:87f2f5183dfb	5116
Kojto	115:87f2f5183dfb	5117	#define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /!< Window Vertical Start Position /
Kojto	115:87f2f5183dfb	5118	#define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /!< Window Vertical Stop Position /
Kojto	115:87f2f5183dfb	5119
Kojto	115:87f2f5183dfb	5120	/****************** Bit definition for LTDC_LxCKCR register *************/
Kojto	115:87f2f5183dfb	5121
Kojto	115:87f2f5183dfb	5122	#define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /!< Color Key Blue value /
Kojto	115:87f2f5183dfb	5123	#define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /!< Color Key Green value /
Kojto	115:87f2f5183dfb	5124	#define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /!< Color Key Red value /
Kojto	115:87f2f5183dfb	5125
Kojto	115:87f2f5183dfb	5126	/****************** Bit definition for LTDC_LxPFCR register *************/
Kojto	115:87f2f5183dfb	5127
Kojto	115:87f2f5183dfb	5128	#define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /!< Pixel Format /
Kojto	115:87f2f5183dfb	5129
Kojto	115:87f2f5183dfb	5130	/****************** Bit definition for LTDC_LxCACR register *************/
Kojto	115:87f2f5183dfb	5131
Kojto	115:87f2f5183dfb	5132	#define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /!< Constant Alpha /
Kojto	115:87f2f5183dfb	5133
Kojto	115:87f2f5183dfb	5134	/****************** Bit definition for LTDC_LxDCCR register *************/
Kojto	115:87f2f5183dfb	5135
Kojto	115:87f2f5183dfb	5136	#define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /!< Default Color Blue /
Kojto	115:87f2f5183dfb	5137	#define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /!< Default Color Green /
Kojto	115:87f2f5183dfb	5138	#define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /!< Default Color Red /
Kojto	115:87f2f5183dfb	5139	#define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /!< Default Color Alpha /
Kojto	115:87f2f5183dfb	5140
Kojto	115:87f2f5183dfb	5141	/****************** Bit definition for LTDC_LxBFCR register *************/
Kojto	115:87f2f5183dfb	5142
Kojto	115:87f2f5183dfb	5143	#define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /!< Blending Factor 2 /
Kojto	115:87f2f5183dfb	5144	#define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /!< Blending Factor 1 /
Kojto	115:87f2f5183dfb	5145
Kojto	115:87f2f5183dfb	5146	/****************** Bit definition for LTDC_LxCFBAR register ************/
Kojto	115:87f2f5183dfb	5147
Kojto	115:87f2f5183dfb	5148	#define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /!< Color Frame Buffer Start Address /
Kojto	115:87f2f5183dfb	5149
Kojto	115:87f2f5183dfb	5150	/****************** Bit definition for LTDC_LxCFBLR register ************/
Kojto	115:87f2f5183dfb	5151
Kojto	115:87f2f5183dfb	5152	#define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /!< Color Frame Buffer Line Length /
Kojto	115:87f2f5183dfb	5153	#define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /!< Color Frame Buffer Pitch in bytes /
Kojto	115:87f2f5183dfb	5154
Kojto	115:87f2f5183dfb	5155	/****************** Bit definition for LTDC_LxCFBLNR register ***********/
Kojto	115:87f2f5183dfb	5156
Kojto	115:87f2f5183dfb	5157	#define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /!< Frame Buffer Line Number /
Kojto	115:87f2f5183dfb	5158
Kojto	115:87f2f5183dfb	5159	/****************** Bit definition for LTDC_LxCLUTWR register ***********/
Kojto	115:87f2f5183dfb	5160
Kojto	115:87f2f5183dfb	5161	#define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /!< Blue value /
Kojto	115:87f2f5183dfb	5162	#define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /!< Green value /
Kojto	115:87f2f5183dfb	5163	#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /!< Red value /
Kojto	115:87f2f5183dfb	5164	#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /!< CLUT address /
Kojto	115:87f2f5183dfb	5165
Kojto	115:87f2f5183dfb	5166
Kojto	115:87f2f5183dfb	5167	/******************************************************************************/
Kojto	115:87f2f5183dfb	5168	/* */
Kojto	115:87f2f5183dfb	5169	/* Power Control */
Kojto	115:87f2f5183dfb	5170	/* */
Kojto	115:87f2f5183dfb	5171	/******************************************************************************/
Kojto	115:87f2f5183dfb	5172	/****************** Bit definition for PWR_CR1 register ******************/
Kojto	115:87f2f5183dfb	5173	#define PWR_CR1_LPDS ((uint32_t)0x00000001) /!< Low-Power Deepsleep /
Kojto	115:87f2f5183dfb	5174	#define PWR_CR1_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
Kojto	115:87f2f5183dfb	5175	#define PWR_CR1_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
Kojto	115:87f2f5183dfb	5176	#define PWR_CR1_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
Kojto	115:87f2f5183dfb	5177
Kojto	115:87f2f5183dfb	5178	#define PWR_CR1_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
Kojto	115:87f2f5183dfb	5179	#define PWR_CR1_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5180	#define PWR_CR1_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5181	#define PWR_CR1_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
Kojto	115:87f2f5183dfb	5182
Kojto	115:87f2f5183dfb	5183	/!< PVD level configuration /
Kojto	115:87f2f5183dfb	5184	#define PWR_CR1_PLS_LEV0 ((uint32_t)0x00000000) /!< PVD level 0 /
Kojto	115:87f2f5183dfb	5185	#define PWR_CR1_PLS_LEV1 ((uint32_t)0x00000020) /!< PVD level 1 /
Kojto	115:87f2f5183dfb	5186	#define PWR_CR1_PLS_LEV2 ((uint32_t)0x00000040) /!< PVD level 2 /
Kojto	115:87f2f5183dfb	5187	#define PWR_CR1_PLS_LEV3 ((uint32_t)0x00000060) /!< PVD level 3 /
Kojto	115:87f2f5183dfb	5188	#define PWR_CR1_PLS_LEV4 ((uint32_t)0x00000080) /!< PVD level 4 /
Kojto	115:87f2f5183dfb	5189	#define PWR_CR1_PLS_LEV5 ((uint32_t)0x000000A0) /!< PVD level 5 /
Kojto	115:87f2f5183dfb	5190	#define PWR_CR1_PLS_LEV6 ((uint32_t)0x000000C0) /!< PVD level 6 /
Kojto	115:87f2f5183dfb	5191	#define PWR_CR1_PLS_LEV7 ((uint32_t)0x000000E0) /!< PVD level 7 /
Kojto	115:87f2f5183dfb	5192
Kojto	115:87f2f5183dfb	5193	#define PWR_CR1_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
Kojto	115:87f2f5183dfb	5194	#define PWR_CR1_FPDS ((uint32_t)0x00000200) /!< Flash power down in Stop mode /
Kojto	115:87f2f5183dfb	5195
Kojto	115:87f2f5183dfb	5196	#define PWR_CR1_LPUDS ((uint32_t)0x00000400) /!< Low-power regulator in deepsleep under-drive mode /
Kojto	115:87f2f5183dfb	5197	#define PWR_CR1_MRUDS ((uint32_t)0x00000800) /!< Main regulator in deepsleep under-drive mode /
Kojto	115:87f2f5183dfb	5198
Kojto	115:87f2f5183dfb	5199	#define PWR_CR1_ADCDC1 ((uint32_t)0x00002000) /!< Refer to AN4073 on how to use this bit /
Kojto	115:87f2f5183dfb	5200
Kojto	115:87f2f5183dfb	5201	#define PWR_CR1_VOS ((uint32_t)0x0000C000) /!< VOS[1:0] bits (Regulator voltage scaling output selection) /
Kojto	115:87f2f5183dfb	5202	#define PWR_CR1_VOS_0 ((uint32_t)0x00004000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5203	#define PWR_CR1_VOS_1 ((uint32_t)0x00008000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5204
Kojto	115:87f2f5183dfb	5205	#define PWR_CR1_ODEN ((uint32_t)0x00010000) /!< Over Drive enable /
Kojto	115:87f2f5183dfb	5206	#define PWR_CR1_ODSWEN ((uint32_t)0x00020000) /!< Over Drive switch enabled /
Kojto	115:87f2f5183dfb	5207	#define PWR_CR1_UDEN ((uint32_t)0x000C0000) /!< Under Drive enable in stop mode /
Kojto	115:87f2f5183dfb	5208	#define PWR_CR1_UDEN_0 ((uint32_t)0x00040000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5209	#define PWR_CR1_UDEN_1 ((uint32_t)0x00080000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5210
Kojto	115:87f2f5183dfb	5211	/***************** Bit definition for PWR_CSR1 register ******************/
Kojto	115:87f2f5183dfb	5212	#define PWR_CSR1_WUIF ((uint32_t)0x00000001) /!< Wake up internal Flag /
Kojto	115:87f2f5183dfb	5213	#define PWR_CSR1_SBF ((uint32_t)0x00000002) /!< Standby Flag /
Kojto	115:87f2f5183dfb	5214	#define PWR_CSR1_PVDO ((uint32_t)0x00000004) /!< PVD Output /
Kojto	115:87f2f5183dfb	5215	#define PWR_CSR1_BRR ((uint32_t)0x00000008) /!< Backup regulator ready /
Kojto	115:87f2f5183dfb	5216	#define PWR_CSR1_BRE ((uint32_t)0x00000200) /!< Backup regulator enable /
Kojto	115:87f2f5183dfb	5217	#define PWR_CSR1_VOSRDY ((uint32_t)0x00004000) /!< Regulator voltage scaling output selection ready /
Kojto	115:87f2f5183dfb	5218
Kojto	115:87f2f5183dfb	5219	#define PWR_CSR1_ODRDY ((uint32_t)0x00010000) /!< Over Drive generator ready /
Kojto	115:87f2f5183dfb	5220	#define PWR_CSR1_ODSWRDY ((uint32_t)0x00020000) /!< Over Drive Switch ready /
Kojto	115:87f2f5183dfb	5221	#define PWR_CSR1_UDSWRDY ((uint32_t)0x000C0000) /!< Under Drive ready /
Kojto	115:87f2f5183dfb	5222
Kojto	115:87f2f5183dfb	5223	/****************** Bit definition for PWR_CR2 register ******************/
Kojto	115:87f2f5183dfb	5224	#define PWR_CR2_CWUPF1 ((uint32_t)0x00000001) /!< Clear Wakeup Pin Flag for PA0 /
Kojto	115:87f2f5183dfb	5225	#define PWR_CR2_CWUPF2 ((uint32_t)0x00000002) /!< Clear Wakeup Pin Flag for PA2 /
Kojto	115:87f2f5183dfb	5226	#define PWR_CR2_CWUPF3 ((uint32_t)0x00000004) /!< Clear Wakeup Pin Flag for PC1 /
Kojto	115:87f2f5183dfb	5227	#define PWR_CR2_CWUPF4 ((uint32_t)0x00000008) /!< Clear Wakeup Pin Flag for PC13 /
Kojto	115:87f2f5183dfb	5228	#define PWR_CR2_CWUPF5 ((uint32_t)0x00000010) /!< Clear Wakeup Pin Flag for PI8 /
Kojto	115:87f2f5183dfb	5229	#define PWR_CR2_CWUPF6 ((uint32_t)0x00000020) /!< Clear Wakeup Pin Flag for PI11 /
Kojto	115:87f2f5183dfb	5230
Kojto	115:87f2f5183dfb	5231	#define PWR_CR2_WUPP1 ((uint32_t)0x00000100) /!< Wakeup Pin Polarity bit for PA0 /
Kojto	115:87f2f5183dfb	5232	#define PWR_CR2_WUPP2 ((uint32_t)0x00000200) /!< Wakeup Pin Polarity bit for PA2 /
Kojto	115:87f2f5183dfb	5233	#define PWR_CR2_WUPP3 ((uint32_t)0x00000400) /!< Wakeup Pin Polarity bit for PC1 /
Kojto	115:87f2f5183dfb	5234	#define PWR_CR2_WUPP4 ((uint32_t)0x00000800) /!< Wakeup Pin Polarity bit for PC13 /
Kojto	115:87f2f5183dfb	5235	#define PWR_CR2_WUPP5 ((uint32_t)0x00001000) /!< Wakeup Pin Polarity bit for PI8 /
Kojto	115:87f2f5183dfb	5236	#define PWR_CR2_WUPP6 ((uint32_t)0x00002000) /!< Wakeup Pin Polarity bit for PI11 /
Kojto	115:87f2f5183dfb	5237
Kojto	115:87f2f5183dfb	5238	/***************** Bit definition for PWR_CSR2 register ******************/
Kojto	115:87f2f5183dfb	5239	#define PWR_CSR2_WUPF1 ((uint32_t)0x00000001) /!< Wakeup Pin Flag for PA0 /
Kojto	115:87f2f5183dfb	5240	#define PWR_CSR2_WUPF2 ((uint32_t)0x00000002) /!< Wakeup Pin Flag for PA2 /
Kojto	115:87f2f5183dfb	5241	#define PWR_CSR2_WUPF3 ((uint32_t)0x00000004) /!< Wakeup Pin Flag for PC1 /
Kojto	115:87f2f5183dfb	5242	#define PWR_CSR2_WUPF4 ((uint32_t)0x00000008) /!< Wakeup Pin Flag for PC13 /
Kojto	115:87f2f5183dfb	5243	#define PWR_CSR2_WUPF5 ((uint32_t)0x00000010) /!< Wakeup Pin Flag for PI8 /
Kojto	115:87f2f5183dfb	5244	#define PWR_CSR2_WUPF6 ((uint32_t)0x00000020) /!< Wakeup Pin Flag for PI11 /
Kojto	115:87f2f5183dfb	5245
Kojto	115:87f2f5183dfb	5246	#define PWR_CSR2_EWUP1 ((uint32_t)0x00000100) /!< Enable Wakeup Pin PA0 /
Kojto	115:87f2f5183dfb	5247	#define PWR_CSR2_EWUP2 ((uint32_t)0x00000200) /!< Enable Wakeup Pin PA2 /
Kojto	115:87f2f5183dfb	5248	#define PWR_CSR2_EWUP3 ((uint32_t)0x00000400) /!< Enable Wakeup Pin PC1 /
Kojto	115:87f2f5183dfb	5249	#define PWR_CSR2_EWUP4 ((uint32_t)0x00000800) /!< Enable Wakeup Pin PC13 /
Kojto	115:87f2f5183dfb	5250	#define PWR_CSR2_EWUP5 ((uint32_t)0x00001000) /!< Enable Wakeup Pin PI8 /
Kojto	115:87f2f5183dfb	5251	#define PWR_CSR2_EWUP6 ((uint32_t)0x00002000) /!< Enable Wakeup Pin PI11 /
Kojto	115:87f2f5183dfb	5252
Kojto	115:87f2f5183dfb	5253	/******************************************************************************/
Kojto	115:87f2f5183dfb	5254	/* */
Kojto	115:87f2f5183dfb	5255	/* QUADSPI */
Kojto	115:87f2f5183dfb	5256	/* */
Kojto	115:87f2f5183dfb	5257	/******************************************************************************/
Kojto	115:87f2f5183dfb	5258	/*************** Bit definition for QUADSPI_CR register *****************/
Kojto	115:87f2f5183dfb	5259	#define QUADSPI_CR_EN ((uint32_t)0x00000001) /!< Enable /
Kojto	115:87f2f5183dfb	5260	#define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /!< Abort request /
Kojto	115:87f2f5183dfb	5261	#define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /!< DMA Enable /
Kojto	115:87f2f5183dfb	5262	#define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /!< Timeout Counter Enable /
Kojto	115:87f2f5183dfb	5263	#define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /!< Sample Shift /
Kojto	115:87f2f5183dfb	5264	#define QUADSPI_CR_DFM ((uint32_t)0x00000040) /!< Dual Flash Mode /
Kojto	115:87f2f5183dfb	5265	#define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /!< Flash Select /
Kojto	115:87f2f5183dfb	5266	#define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /!< FTHRES[3:0] FIFO Level /
Kojto	115:87f2f5183dfb	5267	#define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5268	#define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5269	#define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /!< Bit 2 /
Kojto	115:87f2f5183dfb	5270	#define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /!< Bit 3 /
Kojto	115:87f2f5183dfb	5271	#define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /!< Transfer Error Interrupt Enable /
Kojto	115:87f2f5183dfb	5272	#define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /!< Transfer Complete Interrupt Enable /
Kojto	115:87f2f5183dfb	5273	#define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /!< FIFO Threshold Interrupt Enable /
Kojto	115:87f2f5183dfb	5274	#define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /!< Status Match Interrupt Enable /
Kojto	115:87f2f5183dfb	5275	#define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /!< TimeOut Interrupt Enable /
Kojto	115:87f2f5183dfb	5276	#define QUADSPI_CR_APMS ((uint32_t)0x00400000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5277	#define QUADSPI_CR_PMM ((uint32_t)0x00800000) /!< Polling Match Mode /
Kojto	115:87f2f5183dfb	5278	#define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /!< PRESCALER[7:0] Clock prescaler /
Kojto	115:87f2f5183dfb	5279	#define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5280	#define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5281	#define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /!< Bit 2 /
Kojto	115:87f2f5183dfb	5282	#define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /!< Bit 3 /
Kojto	115:87f2f5183dfb	5283	#define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /!< Bit 4 /
Kojto	115:87f2f5183dfb	5284	#define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /!< Bit 5 /
Kojto	115:87f2f5183dfb	5285	#define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /!< Bit 6 /
Kojto	115:87f2f5183dfb	5286	#define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /!< Bit 7 /
Kojto	115:87f2f5183dfb	5287
Kojto	115:87f2f5183dfb	5288	/*************** Bit definition for QUADSPI_DCR register ****************/
Kojto	115:87f2f5183dfb	5289	#define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /!< Mode 0 / Mode 3 /
Kojto	115:87f2f5183dfb	5290	#define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /!< CSHT[2:0]: ChipSelect High Time /
Kojto	115:87f2f5183dfb	5291	#define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5292	#define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5293	#define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /!< Bit 2 /
Kojto	115:87f2f5183dfb	5294	#define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /!< FSIZE[4:0]: Flash Size /
Kojto	115:87f2f5183dfb	5295	#define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5296	#define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5297	#define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /!< Bit 2 /
Kojto	115:87f2f5183dfb	5298	#define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /!< Bit 3 /
Kojto	115:87f2f5183dfb	5299	#define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /!< Bit 4 /
Kojto	115:87f2f5183dfb	5300
Kojto	115:87f2f5183dfb	5301	/**************** Bit definition for QUADSPI_SR register *****************/
Kojto	115:87f2f5183dfb	5302	#define QUADSPI_SR_TEF ((uint32_t)0x00000001) /!< Transfer Error Flag /
Kojto	115:87f2f5183dfb	5303	#define QUADSPI_SR_TCF ((uint32_t)0x00000002) /!< Transfer Complete Flag /
Kojto	115:87f2f5183dfb	5304	#define QUADSPI_SR_FTF ((uint32_t)0x00000004) /!< FIFO Threshlod Flag /
Kojto	115:87f2f5183dfb	5305	#define QUADSPI_SR_SMF ((uint32_t)0x00000008) /!< Status Match Flag /
Kojto	115:87f2f5183dfb	5306	#define QUADSPI_SR_TOF ((uint32_t)0x00000010) /!< Timeout Flag /
Kojto	115:87f2f5183dfb	5307	#define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /!< Busy /
Kojto	115:87f2f5183dfb	5308	#define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00) /!< FIFO Threshlod Flag /
Kojto	115:87f2f5183dfb	5309	#define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5310	#define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5311	#define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /!< Bit 2 /
Kojto	115:87f2f5183dfb	5312	#define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /!< Bit 3 /
Kojto	115:87f2f5183dfb	5313	#define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /!< Bit 4 /
Kojto	115:87f2f5183dfb	5314
Kojto	115:87f2f5183dfb	5315	/**************** Bit definition for QUADSPI_FCR register ****************/
Kojto	115:87f2f5183dfb	5316	#define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /!< Clear Transfer Error Flag /
Kojto	115:87f2f5183dfb	5317	#define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /!< Clear Transfer Complete Flag /
Kojto	115:87f2f5183dfb	5318	#define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /!< Clear Status Match Flag /
Kojto	115:87f2f5183dfb	5319	#define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /!< Clear Timeout Flag /
Kojto	115:87f2f5183dfb	5320
Kojto	115:87f2f5183dfb	5321	/**************** Bit definition for QUADSPI_DLR register ****************/
Kojto	115:87f2f5183dfb	5322	#define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /!< DL[31:0]: Data Length /
Kojto	115:87f2f5183dfb	5323
Kojto	115:87f2f5183dfb	5324	/**************** Bit definition for QUADSPI_CCR register ****************/
Kojto	115:87f2f5183dfb	5325	#define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /!< INSTRUCTION[7:0]: Instruction /
Kojto	115:87f2f5183dfb	5326	#define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5327	#define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5328	#define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	115:87f2f5183dfb	5329	#define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	115:87f2f5183dfb	5330	#define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /!< Bit 4 /
Kojto	115:87f2f5183dfb	5331	#define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /!< Bit 5 /
Kojto	115:87f2f5183dfb	5332	#define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /!< Bit 6 /
Kojto	115:87f2f5183dfb	5333	#define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /!< Bit 7 /
Kojto	115:87f2f5183dfb	5334	#define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /!< IMODE[1:0]: Instruction Mode /
Kojto	115:87f2f5183dfb	5335	#define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5336	#define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5337	#define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /!< ADMODE[1:0]: Address Mode /
Kojto	115:87f2f5183dfb	5338	#define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5339	#define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5340	#define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /!< ADSIZE[1:0]: Address Size /
Kojto	115:87f2f5183dfb	5341	#define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5342	#define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5343	#define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /!< ABMODE[1:0]: Alternate Bytes Mode /
Kojto	115:87f2f5183dfb	5344	#define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5345	#define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5346	#define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /!< ABSIZE[1:0]: Instruction Mode /
Kojto	115:87f2f5183dfb	5347	#define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5348	#define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5349	#define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /!< DCYC[4:0]: Dummy Cycles /
Kojto	115:87f2f5183dfb	5350	#define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5351	#define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5352	#define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /!< Bit 2 /
Kojto	115:87f2f5183dfb	5353	#define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /!< Bit 3 /
Kojto	115:87f2f5183dfb	5354	#define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /!< Bit 4 /
Kojto	115:87f2f5183dfb	5355	#define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /!< DMODE[1:0]: Data Mode /
Kojto	115:87f2f5183dfb	5356	#define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5357	#define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5358	#define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /!< FMODE[1:0]: Functional Mode /
Kojto	115:87f2f5183dfb	5359	#define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5360	#define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5361	#define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /!< SIOO: Send Instruction Only Once Mode /
Kojto	115:87f2f5183dfb	5362	#define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /!< DHHC: Delay Half Hclk Cycle /
Kojto	115:87f2f5183dfb	5363	#define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /!< DDRM: Double Data Rate Mode /
Kojto	115:87f2f5183dfb	5364	/**************** Bit definition for QUADSPI_AR register *****************/
Kojto	115:87f2f5183dfb	5365	#define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< ADDRESS[31:0]: Address /
Kojto	115:87f2f5183dfb	5366
Kojto	115:87f2f5183dfb	5367	/**************** Bit definition for QUADSPI_ABR register ****************/
Kojto	115:87f2f5183dfb	5368	#define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /!< ALTERNATE[31:0]: Alternate Bytes /
Kojto	115:87f2f5183dfb	5369
Kojto	115:87f2f5183dfb	5370	/**************** Bit definition for QUADSPI_DR register *****************/
Kojto	115:87f2f5183dfb	5371	#define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /!< DATA[31:0]: Data /
Kojto	115:87f2f5183dfb	5372
Kojto	115:87f2f5183dfb	5373	/**************** Bit definition for QUADSPI_PSMKR register **************/
Kojto	115:87f2f5183dfb	5374	#define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /!< MASK[31:0]: Status Mask /
Kojto	115:87f2f5183dfb	5375
Kojto	115:87f2f5183dfb	5376	/**************** Bit definition for QUADSPI_PSMAR register **************/
Kojto	115:87f2f5183dfb	5377	#define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /!< MATCH[31:0]: Status Match /
Kojto	115:87f2f5183dfb	5378
Kojto	115:87f2f5183dfb	5379	/**************** Bit definition for QUADSPI_PIR register ***************/
Kojto	115:87f2f5183dfb	5380	#define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /!< INTERVAL[15:0]: Polling Interval /
Kojto	115:87f2f5183dfb	5381
Kojto	115:87f2f5183dfb	5382	/**************** Bit definition for QUADSPI_LPTR register ***************/
Kojto	115:87f2f5183dfb	5383	#define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /!< TIMEOUT[15:0]: Timeout period /
Kojto	115:87f2f5183dfb	5384
Kojto	115:87f2f5183dfb	5385	/******************************************************************************/
Kojto	115:87f2f5183dfb	5386	/* */
Kojto	115:87f2f5183dfb	5387	/* Reset and Clock Control */
Kojto	115:87f2f5183dfb	5388	/* */
Kojto	115:87f2f5183dfb	5389	/******************************************************************************/
Kojto	115:87f2f5183dfb	5390	/****************** Bit definition for RCC_CR register ******************/
Kojto	115:87f2f5183dfb	5391	#define RCC_CR_HSION ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5392	#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5393
Kojto	115:87f2f5183dfb	5394	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
Kojto	115:87f2f5183dfb	5395	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /!<Bit 0 /
Kojto	115:87f2f5183dfb	5396	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /!<Bit 1 /
Kojto	115:87f2f5183dfb	5397	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /!<Bit 2 /
Kojto	115:87f2f5183dfb	5398	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /!<Bit 3 /
Kojto	115:87f2f5183dfb	5399	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /!<Bit 4 /
Kojto	115:87f2f5183dfb	5400
Kojto	115:87f2f5183dfb	5401	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
Kojto	115:87f2f5183dfb	5402	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	5403	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	5404	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	5405	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	5406	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	5407	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	5408	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	5409	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	5410
Kojto	115:87f2f5183dfb	5411	#define RCC_CR_HSEON ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5412	#define RCC_CR_HSERDY ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5413	#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	5414	#define RCC_CR_CSSON ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	5415	#define RCC_CR_PLLON ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	5416	#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5417	#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5418	#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	5419	#define RCC_CR_PLLSAION ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	5420	#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	5421
Kojto	115:87f2f5183dfb	5422	/****************** Bit definition for RCC_PLLCFGR register *************/
Kojto	115:87f2f5183dfb	5423	#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
Kojto	115:87f2f5183dfb	5424	#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5425	#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5426	#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5427	#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	5428	#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5429	#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5430
Kojto	115:87f2f5183dfb	5431	#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
Kojto	115:87f2f5183dfb	5432	#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5433	#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5434	#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5435	#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5436	#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	5437	#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	5438	#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	5439	#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	5440	#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	5441
Kojto	115:87f2f5183dfb	5442	#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
Kojto	115:87f2f5183dfb	5443	#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5444	#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5445
Kojto	115:87f2f5183dfb	5446	#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5447	#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5448	#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	5449
Kojto	115:87f2f5183dfb	5450	#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
Kojto	115:87f2f5183dfb	5451	#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	5452	#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5453	#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5454	#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	5455
Kojto	115:87f2f5183dfb	5456	/****************** Bit definition for RCC_CFGR register ****************/
Kojto	115:87f2f5183dfb	5457	/!< SW configuration /
Kojto	115:87f2f5183dfb	5458	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
Kojto	115:87f2f5183dfb	5459	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5460	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5461
Kojto	115:87f2f5183dfb	5462	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
Kojto	115:87f2f5183dfb	5463	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
Kojto	115:87f2f5183dfb	5464	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
Kojto	115:87f2f5183dfb	5465
Kojto	115:87f2f5183dfb	5466	/!< SWS configuration /
Kojto	115:87f2f5183dfb	5467	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
Kojto	115:87f2f5183dfb	5468	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5469	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5470
Kojto	115:87f2f5183dfb	5471	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
Kojto	115:87f2f5183dfb	5472	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
Kojto	115:87f2f5183dfb	5473	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
Kojto	115:87f2f5183dfb	5474
Kojto	115:87f2f5183dfb	5475	/!< HPRE configuration /
Kojto	115:87f2f5183dfb	5476	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
Kojto	115:87f2f5183dfb	5477	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5478	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5479	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
Kojto	115:87f2f5183dfb	5480	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
Kojto	115:87f2f5183dfb	5481
Kojto	115:87f2f5183dfb	5482	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
Kojto	115:87f2f5183dfb	5483	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
Kojto	115:87f2f5183dfb	5484	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
Kojto	115:87f2f5183dfb	5485	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
Kojto	115:87f2f5183dfb	5486	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
Kojto	115:87f2f5183dfb	5487	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
Kojto	115:87f2f5183dfb	5488	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
Kojto	115:87f2f5183dfb	5489	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
Kojto	115:87f2f5183dfb	5490	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
Kojto	115:87f2f5183dfb	5491
Kojto	115:87f2f5183dfb	5492	/!< PPRE1 configuration /
Kojto	115:87f2f5183dfb	5493	#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /!< PRE1[2:0] bits (APB1 prescaler) /
Kojto	115:87f2f5183dfb	5494	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5495	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5496	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /!< Bit 2 /
Kojto	115:87f2f5183dfb	5497
Kojto	115:87f2f5183dfb	5498	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
Kojto	115:87f2f5183dfb	5499	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /!< HCLK divided by 2 /
Kojto	115:87f2f5183dfb	5500	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /!< HCLK divided by 4 /
Kojto	115:87f2f5183dfb	5501	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /!< HCLK divided by 8 /
Kojto	115:87f2f5183dfb	5502	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /!< HCLK divided by 16 /
Kojto	115:87f2f5183dfb	5503
Kojto	115:87f2f5183dfb	5504	/!< PPRE2 configuration /
Kojto	115:87f2f5183dfb	5505	#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /!< PRE2[2:0] bits (APB2 prescaler) /
Kojto	115:87f2f5183dfb	5506	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	5507	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	5508	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /!< Bit 2 /
Kojto	115:87f2f5183dfb	5509
Kojto	115:87f2f5183dfb	5510	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
Kojto	115:87f2f5183dfb	5511	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /!< HCLK divided by 2 /
Kojto	115:87f2f5183dfb	5512	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /!< HCLK divided by 4 /
Kojto	115:87f2f5183dfb	5513	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /!< HCLK divided by 8 /
Kojto	115:87f2f5183dfb	5514	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /!< HCLK divided by 16 /
Kojto	115:87f2f5183dfb	5515
Kojto	115:87f2f5183dfb	5516	/!< RTCPRE configuration /
Kojto	115:87f2f5183dfb	5517	#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
Kojto	115:87f2f5183dfb	5518	#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5519	#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5520	#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	5521	#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	5522	#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	5523
Kojto	115:87f2f5183dfb	5524	/!< MCO1 configuration /
Kojto	115:87f2f5183dfb	5525	#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
Kojto	115:87f2f5183dfb	5526	#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5527	#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5528
Kojto	115:87f2f5183dfb	5529	#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5530
Kojto	115:87f2f5183dfb	5531	#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
Kojto	115:87f2f5183dfb	5532	#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	5533	#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5534	#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5535
Kojto	115:87f2f5183dfb	5536	#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
Kojto	115:87f2f5183dfb	5537	#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	5538	#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	5539	#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	5540
Kojto	115:87f2f5183dfb	5541	#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
Kojto	115:87f2f5183dfb	5542	#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	5543	#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	5544
Kojto	115:87f2f5183dfb	5545	/****************** Bit definition for RCC_CIR register *****************/
Kojto	115:87f2f5183dfb	5546	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5547	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5548	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5549	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	5550	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5551	#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5552	#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5553	#define RCC_CIR_CSSF ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5554	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5555	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5556	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	5557	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	5558	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	5559	#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	5560	#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	5561	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5562	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5563	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	5564	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	5565	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	5566	#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5567	#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5568	#define RCC_CIR_CSSC ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5569
Kojto	115:87f2f5183dfb	5570	/****************** Bit definition for RCC_AHB1RSTR register ************/
Kojto	115:87f2f5183dfb	5571	#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5572	#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5573	#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5574	#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	5575	#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5576	#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5577	#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5578	#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5579	#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5580	#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5581	#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	5582	#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	5583	#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5584	#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5585	#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5586	#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5587	#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	5588
Kojto	115:87f2f5183dfb	5589	/****************** Bit definition for RCC_AHB2RSTR register ************/
Kojto	115:87f2f5183dfb	5590	#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5591	#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5592	#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5593
Kojto	115:87f2f5183dfb	5594	/****************** Bit definition for RCC_AHB3RSTR register ************/
Kojto	115:87f2f5183dfb	5595
Kojto	115:87f2f5183dfb	5596	#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5597	#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5598
Kojto	115:87f2f5183dfb	5599	/****************** Bit definition for RCC_APB1RSTR register ************/
Kojto	115:87f2f5183dfb	5600	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5601	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5602	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5603	#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	5604	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5605	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5606	#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5607	#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5608	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5609	#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5610	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	5611	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	5612	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	5613	#define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5614	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5615	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	5616	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	5617	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	5618	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5619	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5620	#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5621	#define RCC_APB1RSTR_I2C4RST ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	5622	#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5623	#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5624	#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	5625	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	5626	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	5627	#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	5628	#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	5629
Kojto	115:87f2f5183dfb	5630	/****************** Bit definition for RCC_APB2RSTR register ************/
Kojto	115:87f2f5183dfb	5631	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5632	#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5633	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5634	#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5635	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5636	#define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	5637	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	5638	#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	5639	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	5640	#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5641	#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5642	#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	5643	#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	5644	#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5645	#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5646	#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5647	#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5648
Kojto	115:87f2f5183dfb	5649	/****************** Bit definition for RCC_AHB1ENR register *************/
Kojto	115:87f2f5183dfb	5650	#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5651	#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5652	#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5653	#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	5654	#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5655	#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5656	#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5657	#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5658	#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5659	#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5660	#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	5661	#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	5662	#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	5663	#define RCC_AHB1ENR_DTCMRAMEN ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	5664	#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5665	#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5666	#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5667	#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5668	#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5669	#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	5670	#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	5671	#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	5672	#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	5673
Kojto	115:87f2f5183dfb	5674	/****************** Bit definition for RCC_AHB2ENR register *************/
Kojto	115:87f2f5183dfb	5675	#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5676	#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5677	#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5678
Kojto	115:87f2f5183dfb	5679	/****************** Bit definition for RCC_AHB3ENR register *************/
Kojto	115:87f2f5183dfb	5680
Kojto	115:87f2f5183dfb	5681	#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5682	#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5683
Kojto	115:87f2f5183dfb	5684	/****************** Bit definition for RCC_APB1ENR register *************/
Kojto	115:87f2f5183dfb	5685	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5686	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5687	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5688	#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	5689	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5690	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5691	#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5692	#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5693	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5694	#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5695	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	5696	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	5697	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	5698	#define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5699	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5700	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	5701	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	5702	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	5703	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5704	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5705	#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5706	#define RCC_APB1ENR_I2C4EN ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	5707	#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5708	#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5709	#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	5710	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	5711	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	5712	#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	5713	#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	5714
Kojto	115:87f2f5183dfb	5715	/****************** Bit definition for RCC_APB2ENR register *************/
Kojto	115:87f2f5183dfb	5716	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5717	#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5718	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5719	#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5720	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5721	#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5722	#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	5723	#define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	5724	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	5725	#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	5726	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	5727	#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5728	#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5729	#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	5730	#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	5731	#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5732	#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5733	#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5734	#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5735
Kojto	115:87f2f5183dfb	5736	/****************** Bit definition for RCC_AHB1LPENR register ***********/
Kojto	115:87f2f5183dfb	5737	#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5738	#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5739	#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5740	#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	5741	#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5742	#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5743	#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5744	#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5745	#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5746	#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5747	#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	5748
Kojto	115:87f2f5183dfb	5749	#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	5750	#define RCC_AHB1LPENR_AXILPEN ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	5751	#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	5752	#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5753	#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5754	#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	5755	#define RCC_AHB1LPENR_DTCMLPEN ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	5756	#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5757	#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5758	#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5759	#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5760	#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5761	#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	5762	#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	5763	#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	5764	#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	5765
Kojto	115:87f2f5183dfb	5766	/****************** Bit definition for RCC_AHB2LPENR register ***********/
Kojto	115:87f2f5183dfb	5767	#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5768	#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5769	#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5770
Kojto	115:87f2f5183dfb	5771	/****************** Bit definition for RCC_AHB3LPENR register ***********/
Kojto	115:87f2f5183dfb	5772	#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5773	#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5774	/****************** Bit definition for RCC_APB1LPENR register ***********/
Kojto	115:87f2f5183dfb	5775	#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5776	#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5777	#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5778	#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	5779	#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5780	#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5781	#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5782	#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5783	#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5784	#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5785	#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	5786	#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	5787	#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	5788	#define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5789	#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5790	#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	5791	#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	5792	#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	5793	#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5794	#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5795	#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5796	#define RCC_APB1LPENR_I2C4LPEN ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	5797	#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5798	#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5799	#define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	5800	#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	5801	#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	5802	#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	5803	#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	5804
Kojto	115:87f2f5183dfb	5805	/****************** Bit definition for RCC_APB2LPENR register ***********/
Kojto	115:87f2f5183dfb	5806	#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5807	#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5808	#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5809	#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5810	#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5811	#define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5812	#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	5813	#define RCC_APB2LPENR_SDMMC1LPEN ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	5814	#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	5815	#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	5816	#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	5817	#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5818	#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5819	#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	5820	#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	5821	#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5822	#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5823	#define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5824	#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5825
Kojto	115:87f2f5183dfb	5826	/****************** Bit definition for RCC_BDCR register ****************/
Kojto	115:87f2f5183dfb	5827	#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5828	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5829	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5830	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018)
Kojto	115:87f2f5183dfb	5831	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	5832	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5833	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
Kojto	115:87f2f5183dfb	5834	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5835	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5836	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	5837	#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5838
Kojto	115:87f2f5183dfb	5839	/****************** Bit definition for RCC_CSR register *****************/
Kojto	115:87f2f5183dfb	5840	#define RCC_CSR_LSION ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5841	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5842	#define RCC_CSR_RMVF ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	5843	#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5844	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5845	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	5846	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	5847	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	5848	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	5849	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	5850
Kojto	115:87f2f5183dfb	5851	/****************** Bit definition for RCC_SSCGR register ***************/
Kojto	115:87f2f5183dfb	5852	#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
Kojto	115:87f2f5183dfb	5853	#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
Kojto	115:87f2f5183dfb	5854	#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	5855	#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	5856
Kojto	115:87f2f5183dfb	5857	/****************** Bit definition for RCC_PLLI2SCFGR register **********/
Kojto	115:87f2f5183dfb	5858	#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
Kojto	115:87f2f5183dfb	5859	#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5860	#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5861	#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5862	#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5863	#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	5864	#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	5865	#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	5866	#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	5867	#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	5868
Kojto	115:87f2f5183dfb	5869	#define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
Kojto	115:87f2f5183dfb	5870	#define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5871	#define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5872
Kojto	115:87f2f5183dfb	5873	#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
Kojto	115:87f2f5183dfb	5874	#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	5875	#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5876	#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5877	#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	5878
Kojto	115:87f2f5183dfb	5879	#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
Kojto	115:87f2f5183dfb	5880	#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	5881	#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	5882	#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	5883
Kojto	115:87f2f5183dfb	5884	/****************** Bit definition for RCC_PLLSAICFGR register **********/
Kojto	115:87f2f5183dfb	5885	#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
Kojto	115:87f2f5183dfb	5886	#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5887	#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5888	#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5889	#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5890	#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	5891	#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	5892	#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	5893	#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	5894	#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	5895
Kojto	115:87f2f5183dfb	5896	#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
Kojto	115:87f2f5183dfb	5897	#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5898	#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5899
Kojto	115:87f2f5183dfb	5900	#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
Kojto	115:87f2f5183dfb	5901	#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	5902	#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5903	#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5904	#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	5905
Kojto	115:87f2f5183dfb	5906	#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
Kojto	115:87f2f5183dfb	5907	#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	5908	#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	5909	#define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	5910
Kojto	115:87f2f5183dfb	5911	/****************** Bit definition for RCC_DCKCFGR1 register *************/
Kojto	115:87f2f5183dfb	5912	#define RCC_DCKCFGR1_PLLI2SDIVQ ((uint32_t)0x0000001F)
Kojto	115:87f2f5183dfb	5913	#define RCC_DCKCFGR1_PLLI2SDIVQ_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5914	#define RCC_DCKCFGR1_PLLI2SDIVQ_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5915	#define RCC_DCKCFGR1_PLLI2SDIVQ_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5916	#define RCC_DCKCFGR1_PLLI2SDIVQ_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	5917	#define RCC_DCKCFGR1_PLLI2SDIVQ_4 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5918
Kojto	115:87f2f5183dfb	5919	#define RCC_DCKCFGR1_PLLSAIDIVQ ((uint32_t)0x00001F00)
Kojto	115:87f2f5183dfb	5920	#define RCC_DCKCFGR1_PLLSAIDIVQ_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5921	#define RCC_DCKCFGR1_PLLSAIDIVQ_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5922	#define RCC_DCKCFGR1_PLLSAIDIVQ_2 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	5923	#define RCC_DCKCFGR1_PLLSAIDIVQ_3 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	5924	#define RCC_DCKCFGR1_PLLSAIDIVQ_4 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	5925
Kojto	115:87f2f5183dfb	5926	#define RCC_DCKCFGR1_PLLSAIDIVR ((uint32_t)0x00030000)
Kojto	115:87f2f5183dfb	5927	#define RCC_DCKCFGR1_PLLSAIDIVR_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5928	#define RCC_DCKCFGR1_PLLSAIDIVR_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5929
Kojto	115:87f2f5183dfb	5930	#define RCC_DCKCFGR1_SAI1SEL ((uint32_t)0x00300000)
Kojto	115:87f2f5183dfb	5931	#define RCC_DCKCFGR1_SAI1SEL_0 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	5932	#define RCC_DCKCFGR1_SAI1SEL_1 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5933
Kojto	115:87f2f5183dfb	5934	#define RCC_DCKCFGR1_SAI2SEL ((uint32_t)0x00C00000)
Kojto	115:87f2f5183dfb	5935	#define RCC_DCKCFGR1_SAI2SEL_0 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5936	#define RCC_DCKCFGR1_SAI2SEL_1 ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5937
Kojto	115:87f2f5183dfb	5938	#define RCC_DCKCFGR1_TIMPRE ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	5939
Kojto	115:87f2f5183dfb	5940	/****************** Bit definition for RCC_DCKCFGR2 register *************/
Kojto	115:87f2f5183dfb	5941	#define RCC_DCKCFGR2_USART1SEL ((uint32_t)0x00000003)
Kojto	115:87f2f5183dfb	5942	#define RCC_DCKCFGR2_USART1SEL_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5943	#define RCC_DCKCFGR2_USART1SEL_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5944	#define RCC_DCKCFGR2_USART2SEL ((uint32_t)0x0000000C)
Kojto	115:87f2f5183dfb	5945	#define RCC_DCKCFGR2_USART2SEL_0 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5946	#define RCC_DCKCFGR2_USART2SEL_1 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	5947	#define RCC_DCKCFGR2_USART3SEL ((uint32_t)0x00000030)
Kojto	115:87f2f5183dfb	5948	#define RCC_DCKCFGR2_USART3SEL_0 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	5949	#define RCC_DCKCFGR2_USART3SEL_1 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5950	#define RCC_DCKCFGR2_UART4SEL ((uint32_t)0x000000C0)
Kojto	115:87f2f5183dfb	5951	#define RCC_DCKCFGR2_UART4SEL_0 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5952	#define RCC_DCKCFGR2_UART4SEL_1 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	5953	#define RCC_DCKCFGR2_UART5SEL ((uint32_t)0x00000300)
Kojto	115:87f2f5183dfb	5954	#define RCC_DCKCFGR2_UART5SEL_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	5955	#define RCC_DCKCFGR2_UART5SEL_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	5956	#define RCC_DCKCFGR2_USART6SEL ((uint32_t)0x00000C00)
Kojto	115:87f2f5183dfb	5957	#define RCC_DCKCFGR2_USART6SEL_0 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	5958	#define RCC_DCKCFGR2_USART6SEL_1 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	5959	#define RCC_DCKCFGR2_UART7SEL ((uint32_t)0x00003000)
Kojto	115:87f2f5183dfb	5960	#define RCC_DCKCFGR2_UART7SEL_0 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	5961	#define RCC_DCKCFGR2_UART7SEL_1 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	5962	#define RCC_DCKCFGR2_UART8SEL ((uint32_t)0x0000C000)
Kojto	115:87f2f5183dfb	5963	#define RCC_DCKCFGR2_UART8SEL_0 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	5964	#define RCC_DCKCFGR2_UART8SEL_1 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	5965	#define RCC_DCKCFGR2_I2C1SEL ((uint32_t)0x00030000)
Kojto	115:87f2f5183dfb	5966	#define RCC_DCKCFGR2_I2C1SEL_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	5967	#define RCC_DCKCFGR2_I2C1SEL_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	5968	#define RCC_DCKCFGR2_I2C2SEL ((uint32_t)0x000C0000)
Kojto	115:87f2f5183dfb	5969	#define RCC_DCKCFGR2_I2C2SEL_0 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	5970	#define RCC_DCKCFGR2_I2C2SEL_1 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	5971	#define RCC_DCKCFGR2_I2C3SEL ((uint32_t)0x00300000)
Kojto	115:87f2f5183dfb	5972	#define RCC_DCKCFGR2_I2C3SEL_0 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	5973	#define RCC_DCKCFGR2_I2C3SEL_1 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	5974	#define RCC_DCKCFGR2_I2C4SEL ((uint32_t)0x00C00000)
Kojto	115:87f2f5183dfb	5975	#define RCC_DCKCFGR2_I2C4SEL_0 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	5976	#define RCC_DCKCFGR2_I2C4SEL_1 ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	5977	#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0x03000000)
Kojto	115:87f2f5183dfb	5978	#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	5979	#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	5980	#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	5981	#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	5982	#define RCC_DCKCFGR2_SDMMC1SEL ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	5983
Kojto	115:87f2f5183dfb	5984	/******************************************************************************/
Kojto	115:87f2f5183dfb	5985	/* */
Kojto	115:87f2f5183dfb	5986	/* RNG */
Kojto	115:87f2f5183dfb	5987	/* */
Kojto	115:87f2f5183dfb	5988	/******************************************************************************/
Kojto	115:87f2f5183dfb	5989	/****************** Bits definition for RNG_CR register *****************/
Kojto	115:87f2f5183dfb	5990	#define RNG_CR_RNGEN ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5991	#define RNG_CR_IE ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	5992
Kojto	115:87f2f5183dfb	5993	/****************** Bits definition for RNG_SR register *****************/
Kojto	115:87f2f5183dfb	5994	#define RNG_SR_DRDY ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	5995	#define RNG_SR_CECS ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	5996	#define RNG_SR_SECS ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	5997	#define RNG_SR_CEIS ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	5998	#define RNG_SR_SEIS ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	5999
Kojto	115:87f2f5183dfb	6000	/******************************************************************************/
Kojto	115:87f2f5183dfb	6001	/* */
Kojto	115:87f2f5183dfb	6002	/* Real-Time Clock (RTC) */
Kojto	115:87f2f5183dfb	6003	/* */
Kojto	115:87f2f5183dfb	6004	/******************************************************************************/
Kojto	115:87f2f5183dfb	6005	/****************** Bits definition for RTC_TR register *****************/
Kojto	115:87f2f5183dfb	6006	#define RTC_TR_PM ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	6007	#define RTC_TR_HT ((uint32_t)0x00300000)
Kojto	115:87f2f5183dfb	6008	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	6009	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	6010	#define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto	115:87f2f5183dfb	6011	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	6012	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	6013	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	6014	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	6015	#define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto	115:87f2f5183dfb	6016	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	6017	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	6018	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	6019	#define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto	115:87f2f5183dfb	6020	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	6021	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	6022	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	6023	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	6024	#define RTC_TR_ST ((uint32_t)0x00000070)
Kojto	115:87f2f5183dfb	6025	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	6026	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	6027	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	6028	#define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto	115:87f2f5183dfb	6029	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	6030	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	6031	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	6032	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	6033
Kojto	115:87f2f5183dfb	6034	/****************** Bits definition for RTC_DR register *****************/
Kojto	115:87f2f5183dfb	6035	#define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto	115:87f2f5183dfb	6036	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	6037	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	6038	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	6039	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	6040	#define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto	115:87f2f5183dfb	6041	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	6042	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	6043	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	6044	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	6045	#define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto	115:87f2f5183dfb	6046	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	6047	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	6048	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	6049	#define RTC_DR_MT ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	6050	#define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto	115:87f2f5183dfb	6051	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	6052	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	6053	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	6054	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	6055	#define RTC_DR_DT ((uint32_t)0x00000030)
Kojto	115:87f2f5183dfb	6056	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	6057	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	6058	#define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto	115:87f2f5183dfb	6059	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	6060	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	6061	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	6062	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	6063
Kojto	115:87f2f5183dfb	6064	/****************** Bits definition for RTC_CR register *****************/
Kojto	115:87f2f5183dfb	6065	#define RTC_CR_ITSE ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	6066	#define RTC_CR_COE ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	6067	#define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto	115:87f2f5183dfb	6068	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	6069	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	6070	#define RTC_CR_POL ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	6071	#define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	6072	#define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	6073	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	6074	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	6075	#define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	6076	#define RTC_CR_WUTIE ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	6077	#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	6078	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	6079	#define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	6080	#define RTC_CR_WUTE ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	6081	#define RTC_CR_ALRBE ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	6082	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	6083	#define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	6084	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	6085	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	6086	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	6087	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
Kojto	115:87f2f5183dfb	6088	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	6089	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	6090	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	6091
Kojto	115:87f2f5183dfb	6092	/****************** Bits definition for RTC_ISR register ****************/
Kojto	115:87f2f5183dfb	6093	#define RTC_ISR_ITSF ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	6094	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	6095	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	6096	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	6097	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	6098	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	6099	#define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	6100	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	6101	#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	6102	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	6103	#define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	6104	#define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	6105	#define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	6106	#define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	6107	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	6108	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	6109	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	6110	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	6111
Kojto	115:87f2f5183dfb	6112	/****************** Bits definition for RTC_PRER register ***************/
Kojto	115:87f2f5183dfb	6113	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto	115:87f2f5183dfb	6114	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Kojto	115:87f2f5183dfb	6115
Kojto	115:87f2f5183dfb	6116	/****************** Bits definition for RTC_WUTR register ***************/
Kojto	115:87f2f5183dfb	6117	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
Kojto	115:87f2f5183dfb	6118
Kojto	115:87f2f5183dfb	6119	/****************** Bits definition for RTC_ALRMAR register *************/
Kojto	115:87f2f5183dfb	6120	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	6121	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	6122	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto	115:87f2f5183dfb	6123	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	6124	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	6125	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto	115:87f2f5183dfb	6126	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	6127	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	6128	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	6129	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	6130	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	6131	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	6132	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto	115:87f2f5183dfb	6133	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	6134	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	6135	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto	115:87f2f5183dfb	6136	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	6137	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	6138	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	6139	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	6140	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	6141	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto	115:87f2f5183dfb	6142	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	6143	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	6144	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	6145	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto	115:87f2f5183dfb	6146	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	6147	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	6148	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	6149	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	6150	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	6151	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto	115:87f2f5183dfb	6152	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	6153	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	6154	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	6155	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto	115:87f2f5183dfb	6156	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	6157	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	6158	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	6159	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	6160
Kojto	115:87f2f5183dfb	6161	/****************** Bits definition for RTC_ALRMBR register *************/
Kojto	115:87f2f5183dfb	6162	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	6163	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
Kojto	115:87f2f5183dfb	6164	#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
Kojto	115:87f2f5183dfb	6165	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
Kojto	115:87f2f5183dfb	6166	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
Kojto	115:87f2f5183dfb	6167	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
Kojto	115:87f2f5183dfb	6168	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	6169	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	6170	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	6171	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	6172	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	6173	#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	6174	#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
Kojto	115:87f2f5183dfb	6175	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	6176	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	6177	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
Kojto	115:87f2f5183dfb	6178	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	6179	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	6180	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	6181	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	6182	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	6183	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
Kojto	115:87f2f5183dfb	6184	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	6185	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	6186	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	6187	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
Kojto	115:87f2f5183dfb	6188	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	6189	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	6190	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	6191	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	6192	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	6193	#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
Kojto	115:87f2f5183dfb	6194	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	6195	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	6196	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	6197	#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
Kojto	115:87f2f5183dfb	6198	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	6199	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	6200	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	6201	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	6202
Kojto	115:87f2f5183dfb	6203	/****************** Bits definition for RTC_WPR register ****************/
Kojto	115:87f2f5183dfb	6204	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto	115:87f2f5183dfb	6205
Kojto	115:87f2f5183dfb	6206	/****************** Bits definition for RTC_SSR register ****************/
Kojto	115:87f2f5183dfb	6207	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto	115:87f2f5183dfb	6208
Kojto	115:87f2f5183dfb	6209	/****************** Bits definition for RTC_SHIFTR register *************/
Kojto	115:87f2f5183dfb	6210	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto	115:87f2f5183dfb	6211	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto	115:87f2f5183dfb	6212
Kojto	115:87f2f5183dfb	6213	/****************** Bits definition for RTC_TSTR register ***************/
Kojto	115:87f2f5183dfb	6214	#define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	6215	#define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto	115:87f2f5183dfb	6216	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	6217	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	6218	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto	115:87f2f5183dfb	6219	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	6220	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	6221	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	6222	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	6223	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto	115:87f2f5183dfb	6224	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	6225	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	6226	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	6227	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto	115:87f2f5183dfb	6228	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	6229	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	6230	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	6231	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	6232	#define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto	115:87f2f5183dfb	6233	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	6234	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	6235	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	6236	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto	115:87f2f5183dfb	6237	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	6238	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	6239	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	6240	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	6241
Kojto	115:87f2f5183dfb	6242	/****************** Bits definition for RTC_TSDR register ***************/
Kojto	115:87f2f5183dfb	6243	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto	115:87f2f5183dfb	6244	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	6245	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	6246	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	6247	#define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	6248	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto	115:87f2f5183dfb	6249	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	6250	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	6251	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	6252	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	6253	#define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto	115:87f2f5183dfb	6254	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	6255	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	6256	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto	115:87f2f5183dfb	6257	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	6258	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	6259	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	6260	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	6261
Kojto	115:87f2f5183dfb	6262	/****************** Bits definition for RTC_TSSSR register **************/
Kojto	115:87f2f5183dfb	6263	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto	115:87f2f5183dfb	6264
Kojto	115:87f2f5183dfb	6265	/****************** Bits definition for RTC_CAL register ***************/
Kojto	115:87f2f5183dfb	6266	#define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	6267	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	6268	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	6269	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto	115:87f2f5183dfb	6270	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	6271	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	6272	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	6273	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	6274	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	6275	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	6276	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	6277	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	6278	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	6279
Kojto	115:87f2f5183dfb	6280	/****************** Bits definition for RTC_TAMPCR register **************/
Kojto	115:87f2f5183dfb	6281	#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	6282	#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	6283	#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	6284	#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	6285	#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	6286	#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	6287	#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	6288	#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	6289	#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	6290	#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	6291	#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto	115:87f2f5183dfb	6292	#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	6293	#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	6294	#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800)
Kojto	115:87f2f5183dfb	6295	#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	6296	#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	6297	#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto	115:87f2f5183dfb	6298	#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	6299	#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	6300	#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	6301	#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	6302	#define RTC_TAMPCR_TAMP3_TRG ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	6303	#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	6304	#define RTC_TAMPCR_TAMP2_TRG ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	6305	#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	6306	#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	6307	#define RTC_TAMPCR_TAMP1_TRG ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	6308	#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	6309
Kojto	115:87f2f5183dfb	6310	/****************** Bits definition for RTC_ALRMASSR register ***********/
Kojto	115:87f2f5183dfb	6311	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto	115:87f2f5183dfb	6312	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	6313	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	6314	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	6315	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	6316	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto	115:87f2f5183dfb	6317
Kojto	115:87f2f5183dfb	6318	/****************** Bits definition for RTC_ALRMBSSR register ***********/
Kojto	115:87f2f5183dfb	6319	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
Kojto	115:87f2f5183dfb	6320	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	6321	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	6322	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	6323	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto	115:87f2f5183dfb	6324	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
Kojto	115:87f2f5183dfb	6325
Kojto	115:87f2f5183dfb	6326	/****************** Bits definition for RTC_OR register **************/
Kojto	115:87f2f5183dfb	6327	#define RTC_OR_TSINSEL ((uint32_t)0x00000006)
Kojto	115:87f2f5183dfb	6328	#define RTC_OR_TSINSEL_0 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	6329	#define RTC_OR_TSINSEL_1 ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	6330	#define RTC_OR_ALARMTYPE ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	6331
Kojto	115:87f2f5183dfb	6332
Kojto	115:87f2f5183dfb	6333	/****************** Bits definition for RTC_BKP0R register **************/
Kojto	115:87f2f5183dfb	6334	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6335
Kojto	115:87f2f5183dfb	6336	/****************** Bits definition for RTC_BKP1R register **************/
Kojto	115:87f2f5183dfb	6337	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6338
Kojto	115:87f2f5183dfb	6339	/****************** Bits definition for RTC_BKP2R register **************/
Kojto	115:87f2f5183dfb	6340	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6341
Kojto	115:87f2f5183dfb	6342	/****************** Bits definition for RTC_BKP3R register **************/
Kojto	115:87f2f5183dfb	6343	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6344
Kojto	115:87f2f5183dfb	6345	/****************** Bits definition for RTC_BKP4R register **************/
Kojto	115:87f2f5183dfb	6346	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6347
Kojto	115:87f2f5183dfb	6348	/****************** Bits definition for RTC_BKP5R register **************/
Kojto	115:87f2f5183dfb	6349	#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6350
Kojto	115:87f2f5183dfb	6351	/****************** Bits definition for RTC_BKP6R register **************/
Kojto	115:87f2f5183dfb	6352	#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6353
Kojto	115:87f2f5183dfb	6354	/****************** Bits definition for RTC_BKP7R register **************/
Kojto	115:87f2f5183dfb	6355	#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6356
Kojto	115:87f2f5183dfb	6357	/****************** Bits definition for RTC_BKP8R register **************/
Kojto	115:87f2f5183dfb	6358	#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6359
Kojto	115:87f2f5183dfb	6360	/****************** Bits definition for RTC_BKP9R register **************/
Kojto	115:87f2f5183dfb	6361	#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6362
Kojto	115:87f2f5183dfb	6363	/****************** Bits definition for RTC_BKP10R register *************/
Kojto	115:87f2f5183dfb	6364	#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6365
Kojto	115:87f2f5183dfb	6366	/****************** Bits definition for RTC_BKP11R register *************/
Kojto	115:87f2f5183dfb	6367	#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6368
Kojto	115:87f2f5183dfb	6369	/****************** Bits definition for RTC_BKP12R register *************/
Kojto	115:87f2f5183dfb	6370	#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6371
Kojto	115:87f2f5183dfb	6372	/****************** Bits definition for RTC_BKP13R register *************/
Kojto	115:87f2f5183dfb	6373	#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6374
Kojto	115:87f2f5183dfb	6375	/****************** Bits definition for RTC_BKP14R register *************/
Kojto	115:87f2f5183dfb	6376	#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6377
Kojto	115:87f2f5183dfb	6378	/****************** Bits definition for RTC_BKP15R register *************/
Kojto	115:87f2f5183dfb	6379	#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6380
Kojto	115:87f2f5183dfb	6381	/****************** Bits definition for RTC_BKP16R register *************/
Kojto	115:87f2f5183dfb	6382	#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6383
Kojto	115:87f2f5183dfb	6384	/****************** Bits definition for RTC_BKP17R register *************/
Kojto	115:87f2f5183dfb	6385	#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6386
Kojto	115:87f2f5183dfb	6387	/****************** Bits definition for RTC_BKP18R register *************/
Kojto	115:87f2f5183dfb	6388	#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6389
Kojto	115:87f2f5183dfb	6390	/****************** Bits definition for RTC_BKP19R register *************/
Kojto	115:87f2f5183dfb	6391	#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6392
Kojto	115:87f2f5183dfb	6393	/****************** Bits definition for RTC_BKP20R register *************/
Kojto	115:87f2f5183dfb	6394	#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6395
Kojto	115:87f2f5183dfb	6396	/****************** Bits definition for RTC_BKP21R register *************/
Kojto	115:87f2f5183dfb	6397	#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6398
Kojto	115:87f2f5183dfb	6399	/****************** Bits definition for RTC_BKP22R register *************/
Kojto	115:87f2f5183dfb	6400	#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6401
Kojto	115:87f2f5183dfb	6402	/****************** Bits definition for RTC_BKP23R register *************/
Kojto	115:87f2f5183dfb	6403	#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6404
Kojto	115:87f2f5183dfb	6405	/****************** Bits definition for RTC_BKP24R register *************/
Kojto	115:87f2f5183dfb	6406	#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6407
Kojto	115:87f2f5183dfb	6408	/****************** Bits definition for RTC_BKP25R register *************/
Kojto	115:87f2f5183dfb	6409	#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6410
Kojto	115:87f2f5183dfb	6411	/****************** Bits definition for RTC_BKP26R register *************/
Kojto	115:87f2f5183dfb	6412	#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6413
Kojto	115:87f2f5183dfb	6414	/****************** Bits definition for RTC_BKP27R register *************/
Kojto	115:87f2f5183dfb	6415	#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6416
Kojto	115:87f2f5183dfb	6417	/****************** Bits definition for RTC_BKP28R register *************/
Kojto	115:87f2f5183dfb	6418	#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6419
Kojto	115:87f2f5183dfb	6420	/****************** Bits definition for RTC_BKP29R register *************/
Kojto	115:87f2f5183dfb	6421	#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6422
Kojto	115:87f2f5183dfb	6423	/****************** Bits definition for RTC_BKP30R register *************/
Kojto	115:87f2f5183dfb	6424	#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6425
Kojto	115:87f2f5183dfb	6426	/****************** Bits definition for RTC_BKP31R register *************/
Kojto	115:87f2f5183dfb	6427	#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6428
Kojto	115:87f2f5183dfb	6429	/****************** Number of backup registers ****************************/
Kojto	115:87f2f5183dfb	6430	#define RTC_BKP_NUMBER ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	6431
Kojto	115:87f2f5183dfb	6432
Kojto	115:87f2f5183dfb	6433	/******************************************************************************/
Kojto	115:87f2f5183dfb	6434	/* */
Kojto	115:87f2f5183dfb	6435	/* Serial Audio Interface */
Kojto	115:87f2f5183dfb	6436	/* */
Kojto	115:87f2f5183dfb	6437	/******************************************************************************/
Kojto	115:87f2f5183dfb	6438	/****************** Bit definition for SAI_GCR register *****************/
Kojto	115:87f2f5183dfb	6439	#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /!<SYNCIN[1:0] bits (Synchronization Inputs) /
Kojto	115:87f2f5183dfb	6440	#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6441	#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6442
Kojto	115:87f2f5183dfb	6443	#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /!<SYNCOUT[1:0] bits (Synchronization Outputs) /
Kojto	115:87f2f5183dfb	6444	#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6445	#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6446
Kojto	115:87f2f5183dfb	6447	/***************** Bit definition for SAI_xCR1 register *****************/
Kojto	115:87f2f5183dfb	6448	#define SAI_xCR1_MODE ((uint32_t)0x00000003) /!<MODE[1:0] bits (Audio Block Mode) /
Kojto	115:87f2f5183dfb	6449	#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6450	#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6451
Kojto	115:87f2f5183dfb	6452	#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /!<PRTCFG[1:0] bits (Protocol Configuration) /
Kojto	115:87f2f5183dfb	6453	#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6454	#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6455
Kojto	115:87f2f5183dfb	6456	#define SAI_xCR1_DS ((uint32_t)0x000000E0) /!<DS[1:0] bits (Data Size) /
Kojto	115:87f2f5183dfb	6457	#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6458	#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6459	#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /!<Bit 2 /
Kojto	115:87f2f5183dfb	6460
Kojto	115:87f2f5183dfb	6461	#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /!<LSB First Configuration /
Kojto	115:87f2f5183dfb	6462	#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /!<ClocK STRobing edge /
Kojto	115:87f2f5183dfb	6463
Kojto	115:87f2f5183dfb	6464	#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /!<SYNCEN[1:0](SYNChronization ENable) /
Kojto	115:87f2f5183dfb	6465	#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6466	#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6467
Kojto	115:87f2f5183dfb	6468	#define SAI_xCR1_MONO ((uint32_t)0x00001000) /!<Mono mode /
Kojto	115:87f2f5183dfb	6469	#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /!<Output Drive /
Kojto	115:87f2f5183dfb	6470	#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /!<Audio Block enable /
Kojto	115:87f2f5183dfb	6471	#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /!<DMA enable /
Kojto	115:87f2f5183dfb	6472	#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /!<No Divider Configuration /
Kojto	115:87f2f5183dfb	6473
Kojto	115:87f2f5183dfb	6474	#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /!<MCKDIV[3:0] (Master ClocK Divider) /
Kojto	115:87f2f5183dfb	6475	#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6476	#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6477	#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	6478	#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	6479
Kojto	115:87f2f5183dfb	6480	/***************** Bit definition for SAI_xCR2 register *****************/
Kojto	115:87f2f5183dfb	6481	#define SAI_xCR2_FTH ((uint32_t)0x00000007) /!<FTH[2:0](Fifo THreshold) /
Kojto	115:87f2f5183dfb	6482	#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6483	#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6484	#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	6485
Kojto	115:87f2f5183dfb	6486	#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /!<Fifo FLUSH /
Kojto	115:87f2f5183dfb	6487	#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /!<TRIState Management on data line /
Kojto	115:87f2f5183dfb	6488	#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /!<Mute mode /
Kojto	115:87f2f5183dfb	6489	#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /!<Muate value /
Kojto	115:87f2f5183dfb	6490
Kojto	115:87f2f5183dfb	6491	#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /!<MUTECNT[5:0] (MUTE counter) /
Kojto	115:87f2f5183dfb	6492	#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6493	#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6494	#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /!<Bit 2 /
Kojto	115:87f2f5183dfb	6495	#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /!<Bit 3 /
Kojto	115:87f2f5183dfb	6496	#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /!<Bit 4 /
Kojto	115:87f2f5183dfb	6497	#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	6498
Kojto	115:87f2f5183dfb	6499	#define SAI_xCR2_CPL ((uint32_t)0x00080000) /!< Complement Bit /
Kojto	115:87f2f5183dfb	6500
Kojto	115:87f2f5183dfb	6501	#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /!<COMP[1:0] (Companding mode) /
Kojto	115:87f2f5183dfb	6502	#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6503	#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6504
Kojto	115:87f2f5183dfb	6505	/**************** Bit definition for SAI_xFRCR register *****************/
Kojto	115:87f2f5183dfb	6506	#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /!<FRL[1:0](Frame length) /
Kojto	115:87f2f5183dfb	6507	#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6508	#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6509	#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	6510	#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	6511	#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	6512	#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /!<Bit 5 /
Kojto	115:87f2f5183dfb	6513	#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /!<Bit 6 /
Kojto	115:87f2f5183dfb	6514	#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /!<Bit 7 /
Kojto	115:87f2f5183dfb	6515
Kojto	115:87f2f5183dfb	6516	#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /!<FRL[1:0] (Frame synchronization active level length) /
Kojto	115:87f2f5183dfb	6517	#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6518	#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6519	#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	6520	#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	6521	#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	6522	#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	6523	#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	6524
Kojto	115:87f2f5183dfb	6525	#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /!< Frame Synchronization Definition /
Kojto	115:87f2f5183dfb	6526	#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /!<Frame Synchronization POLarity /
Kojto	115:87f2f5183dfb	6527	#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /!<Frame Synchronization OFFset /
Kojto	115:87f2f5183dfb	6528
Kojto	115:87f2f5183dfb	6529	/**************** Bit definition for SAI_xSLOTR register *****************/
Kojto	115:87f2f5183dfb	6530	#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /!<FRL[4:0](First Bit Offset) /
Kojto	115:87f2f5183dfb	6531	#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6532	#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6533	#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	6534	#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	6535	#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	6536
Kojto	115:87f2f5183dfb	6537	#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /!<SLOTSZ[1:0] (Slot size) /
Kojto	115:87f2f5183dfb	6538	#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6539	#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6540
Kojto	115:87f2f5183dfb	6541	#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /!<NBSLOT[3:0] (Number of Slot in audio Frame) /
Kojto	115:87f2f5183dfb	6542	#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6543	#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6544	#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	6545	#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	6546
Kojto	115:87f2f5183dfb	6547	#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /!<SLOTEN[15:0] (Slot Enable) /
Kojto	115:87f2f5183dfb	6548
Kojto	115:87f2f5183dfb	6549	/***************** Bit definition for SAI_xIMR register *****************/
Kojto	115:87f2f5183dfb	6550	#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /!<Overrun underrun interrupt enable /
Kojto	115:87f2f5183dfb	6551	#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /!<Mute detection interrupt enable /
Kojto	115:87f2f5183dfb	6552	#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /!<Wrong Clock Configuration interrupt enable /
Kojto	115:87f2f5183dfb	6553	#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /!<FIFO request interrupt enable /
Kojto	115:87f2f5183dfb	6554	#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /!<Codec not ready interrupt enable /
Kojto	115:87f2f5183dfb	6555	#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /!<Anticipated frame synchronization detection interrupt enable /
Kojto	115:87f2f5183dfb	6556	#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /!<Late frame synchronization detection interrupt enable /
Kojto	115:87f2f5183dfb	6557
Kojto	115:87f2f5183dfb	6558	/****************** Bit definition for SAI_xSR register *****************/
Kojto	115:87f2f5183dfb	6559	#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /!<Overrun underrun /
Kojto	115:87f2f5183dfb	6560	#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /!<Mute detection /
Kojto	115:87f2f5183dfb	6561	#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /!<Wrong Clock Configuration /
Kojto	115:87f2f5183dfb	6562	#define SAI_xSR_FREQ ((uint32_t)0x00000008) /!<FIFO request /
Kojto	115:87f2f5183dfb	6563	#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /!<Codec not ready /
Kojto	115:87f2f5183dfb	6564	#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /!<Anticipated frame synchronization detection /
Kojto	115:87f2f5183dfb	6565	#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /!<Late frame synchronization detection /
Kojto	115:87f2f5183dfb	6566
Kojto	115:87f2f5183dfb	6567	#define SAI_xSR_FLVL ((uint32_t)0x00070000) /!<FLVL[2:0] (FIFO Level Threshold) /
Kojto	115:87f2f5183dfb	6568	#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6569	#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6570	#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	6571
Kojto	115:87f2f5183dfb	6572	/**************** Bit definition for SAI_xCLRFR register ****************/
Kojto	115:87f2f5183dfb	6573	#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /!<Clear Overrun underrun /
Kojto	115:87f2f5183dfb	6574	#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /!<Clear Mute detection /
Kojto	115:87f2f5183dfb	6575	#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /!<Clear Wrong Clock Configuration /
Kojto	115:87f2f5183dfb	6576	#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /!<Clear FIFO request /
Kojto	115:87f2f5183dfb	6577	#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /!<Clear Codec not ready /
Kojto	115:87f2f5183dfb	6578	#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /!<Clear Anticipated frame synchronization detection /
Kojto	115:87f2f5183dfb	6579	#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /!<Clear Late frame synchronization detection /
Kojto	115:87f2f5183dfb	6580
Kojto	115:87f2f5183dfb	6581	/**************** Bit definition for SAI_xDR register *******************/
Kojto	115:87f2f5183dfb	6582	#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
Kojto	115:87f2f5183dfb	6583
Kojto	115:87f2f5183dfb	6584	/******************************************************************************/
Kojto	115:87f2f5183dfb	6585	/* */
Kojto	115:87f2f5183dfb	6586	/* SPDIF-RX Interface */
Kojto	115:87f2f5183dfb	6587	/* */
Kojto	115:87f2f5183dfb	6588	/******************************************************************************/
Kojto	115:87f2f5183dfb	6589	/****************** Bit definition for SPDIF_CR register *****************/
Kojto	115:87f2f5183dfb	6590	#define SPDIFRX_CR_SPDIFEN ((uint32_t)0x00000003) /!<Peripheral Block Enable /
Kojto	115:87f2f5183dfb	6591	#define SPDIFRX_CR_RXDMAEN ((uint32_t)0x00000004) /!<Receiver DMA Enable for data flow /
Kojto	115:87f2f5183dfb	6592	#define SPDIFRX_CR_RXSTEO ((uint32_t)0x00000008) /!<Stereo Mode /
Kojto	115:87f2f5183dfb	6593	#define SPDIFRX_CR_DRFMT ((uint32_t)0x00000030) /!<RX Data format /
Kojto	115:87f2f5183dfb	6594	#define SPDIFRX_CR_PMSK ((uint32_t)0x00000040) /!<Mask Parity error bit /
Kojto	115:87f2f5183dfb	6595	#define SPDIFRX_CR_VMSK ((uint32_t)0x00000080) /!<Mask of Validity bit /
Kojto	115:87f2f5183dfb	6596	#define SPDIFRX_CR_CUMSK ((uint32_t)0x00000100) /!<Mask of channel status and user bits /
Kojto	115:87f2f5183dfb	6597	#define SPDIFRX_CR_PTMSK ((uint32_t)0x00000200) /!<Mask of Preamble Type bits /
Kojto	115:87f2f5183dfb	6598	#define SPDIFRX_CR_CBDMAEN ((uint32_t)0x00000400) /!<Control Buffer DMA ENable for control flow /
Kojto	115:87f2f5183dfb	6599	#define SPDIFRX_CR_CHSEL ((uint32_t)0x00000800) /!<Channel Selection /
Kojto	115:87f2f5183dfb	6600	#define SPDIFRX_CR_NBTR ((uint32_t)0x00003000) /!<Maximum allowed re-tries during synchronization phase /
Kojto	115:87f2f5183dfb	6601	#define SPDIFRX_CR_WFA ((uint32_t)0x00004000) /!<Wait For Activity /
Kojto	115:87f2f5183dfb	6602	#define SPDIFRX_CR_INSEL ((uint32_t)0x00070000) /!<SPDIF input selection /
Kojto	115:87f2f5183dfb	6603
Kojto	115:87f2f5183dfb	6604	/***************** Bit definition for SPDIFRX_IMR register *****************/
Kojto	115:87f2f5183dfb	6605	#define SPDIFRX_IMR_RXNEIE ((uint32_t)0x00000001) /!<RXNE interrupt enable /
Kojto	115:87f2f5183dfb	6606	#define SPDIFRX_IMR_CSRNEIE ((uint32_t)0x00000002) /!<Control Buffer Ready Interrupt Enable /
Kojto	115:87f2f5183dfb	6607	#define SPDIFRX_IMR_PERRIE ((uint32_t)0x00000004) /!<Parity error interrupt enable /
Kojto	115:87f2f5183dfb	6608	#define SPDIFRX_IMR_OVRIE ((uint32_t)0x00000008) /!<Overrun error Interrupt Enable /
Kojto	115:87f2f5183dfb	6609	#define SPDIFRX_IMR_SBLKIE ((uint32_t)0x00000010) /!<Synchronization Block Detected Interrupt Enable /
Kojto	115:87f2f5183dfb	6610	#define SPDIFRX_IMR_SYNCDIE ((uint32_t)0x00000020) /!<Synchronization Done /
Kojto	115:87f2f5183dfb	6611	#define SPDIFRX_IMR_IFEIE ((uint32_t)0x00000040) /!<Serial Interface Error Interrupt Enable /
Kojto	115:87f2f5183dfb	6612
Kojto	115:87f2f5183dfb	6613	/***************** Bit definition for SPDIFRX_SR register *****************/
Kojto	115:87f2f5183dfb	6614	#define SPDIFRX_SR_RXNE ((uint32_t)0x00000001) /!<Read data register not empty /
Kojto	115:87f2f5183dfb	6615	#define SPDIFRX_SR_CSRNE ((uint32_t)0x00000002) /!<The Control Buffer register is not empty /
Kojto	115:87f2f5183dfb	6616	#define SPDIFRX_SR_PERR ((uint32_t)0x00000004) /!<Parity error /
Kojto	115:87f2f5183dfb	6617	#define SPDIFRX_SR_OVR ((uint32_t)0x00000008) /!<Overrun error /
Kojto	115:87f2f5183dfb	6618	#define SPDIFRX_SR_SBD ((uint32_t)0x00000010) /!<Synchronization Block Detected /
Kojto	115:87f2f5183dfb	6619	#define SPDIFRX_SR_SYNCD ((uint32_t)0x00000020) /!<Synchronization Done /
Kojto	115:87f2f5183dfb	6620	#define SPDIFRX_SR_FERR ((uint32_t)0x00000040) /!<Framing error /
Kojto	115:87f2f5183dfb	6621	#define SPDIFRX_SR_SERR ((uint32_t)0x00000080) /!<Synchronization error /
Kojto	115:87f2f5183dfb	6622	#define SPDIFRX_SR_TERR ((uint32_t)0x00000100) /!<Time-out error /
Kojto	115:87f2f5183dfb	6623	#define SPDIFRX_SR_WIDTH5 ((uint32_t)0x7FFF0000) /!<Duration of 5 symbols counted with spdif_clk /
Kojto	115:87f2f5183dfb	6624
Kojto	115:87f2f5183dfb	6625	/***************** Bit definition for SPDIFRX_IFCR register *****************/
Kojto	115:87f2f5183dfb	6626	#define SPDIFRX_IFCR_PERRCF ((uint32_t)0x00000004) /!<Clears the Parity error flag /
Kojto	115:87f2f5183dfb	6627	#define SPDIFRX_IFCR_OVRCF ((uint32_t)0x00000008) /!<Clears the Overrun error flag /
Kojto	115:87f2f5183dfb	6628	#define SPDIFRX_IFCR_SBDCF ((uint32_t)0x00000010) /!<Clears the Synchronization Block Detected flag /
Kojto	115:87f2f5183dfb	6629	#define SPDIFRX_IFCR_SYNCDCF ((uint32_t)0x00000020) /!<Clears the Synchronization Done flag /
Kojto	115:87f2f5183dfb	6630
Kojto	115:87f2f5183dfb	6631	/***************** Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *****************/
Kojto	115:87f2f5183dfb	6632	#define SPDIFRX_DR0_DR ((uint32_t)0x00FFFFFF) /!<Data value /
Kojto	115:87f2f5183dfb	6633	#define SPDIFRX_DR0_PE ((uint32_t)0x01000000) /!<Parity Error bit /
Kojto	115:87f2f5183dfb	6634	#define SPDIFRX_DR0_V ((uint32_t)0x02000000) /!<Validity bit /
Kojto	115:87f2f5183dfb	6635	#define SPDIFRX_DR0_U ((uint32_t)0x04000000) /!<User bit /
Kojto	115:87f2f5183dfb	6636	#define SPDIFRX_DR0_C ((uint32_t)0x08000000) /!<Channel Status bit /
Kojto	115:87f2f5183dfb	6637	#define SPDIFRX_DR0_PT ((uint32_t)0x30000000) /!<Preamble Type /
Kojto	115:87f2f5183dfb	6638
Kojto	115:87f2f5183dfb	6639	/***************** Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *****************/
Kojto	115:87f2f5183dfb	6640	#define SPDIFRX_DR1_DR ((uint32_t)0xFFFFFF00) /!<Data value /
Kojto	115:87f2f5183dfb	6641	#define SPDIFRX_DR1_PT ((uint32_t)0x00000030) /!<Preamble Type /
Kojto	115:87f2f5183dfb	6642	#define SPDIFRX_DR1_C ((uint32_t)0x00000008) /!<Channel Status bit /
Kojto	115:87f2f5183dfb	6643	#define SPDIFRX_DR1_U ((uint32_t)0x00000004) /!<User bit /
Kojto	115:87f2f5183dfb	6644	#define SPDIFRX_DR1_V ((uint32_t)0x00000002) /!<Validity bit /
Kojto	115:87f2f5183dfb	6645	#define SPDIFRX_DR1_PE ((uint32_t)0x00000001) /!<Parity Error bit /
Kojto	115:87f2f5183dfb	6646
Kojto	115:87f2f5183dfb	6647	/***************** Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *****************/
Kojto	115:87f2f5183dfb	6648	#define SPDIFRX_DR1_DRNL1 ((uint32_t)0xFFFF0000) /!<Data value Channel B /
Kojto	115:87f2f5183dfb	6649	#define SPDIFRX_DR1_DRNL2 ((uint32_t)0x0000FFFF) /!<Data value Channel A /
Kojto	115:87f2f5183dfb	6650
Kojto	115:87f2f5183dfb	6651	/***************** Bit definition for SPDIFRX_CSR register *****************/
Kojto	115:87f2f5183dfb	6652	#define SPDIFRX_CSR_USR ((uint32_t)0x0000FFFF) /!<User data information /
Kojto	115:87f2f5183dfb	6653	#define SPDIFRX_CSR_CS ((uint32_t)0x00FF0000) /!<Channel A status information /
Kojto	115:87f2f5183dfb	6654	#define SPDIFRX_CSR_SOB ((uint32_t)0x01000000) /!<Start Of Block /
Kojto	115:87f2f5183dfb	6655
Kojto	115:87f2f5183dfb	6656	/***************** Bit definition for SPDIFRX_DIR register *****************/
Kojto	115:87f2f5183dfb	6657	#define SPDIFRX_DIR_THI ((uint32_t)0x000013FF) /!<Threshold LOW /
Kojto	115:87f2f5183dfb	6658	#define SPDIFRX_DIR_TLO ((uint32_t)0x1FFF0000) /!<Threshold HIGH /
Kojto	115:87f2f5183dfb	6659
Kojto	115:87f2f5183dfb	6660
Kojto	115:87f2f5183dfb	6661	/******************************************************************************/
Kojto	115:87f2f5183dfb	6662	/* */
Kojto	115:87f2f5183dfb	6663	/* SD host Interface */
Kojto	115:87f2f5183dfb	6664	/* */
Kojto	115:87f2f5183dfb	6665	/******************************************************************************/
Kojto	115:87f2f5183dfb	6666	/**************** Bit definition for SDMMC_POWER register ****************/
Kojto	115:87f2f5183dfb	6667	#define SDMMC_POWER_PWRCTRL ((uint32_t)0x03) /!<PWRCTRL[1:0] bits (Power supply control bits) /
Kojto	115:87f2f5183dfb	6668	#define SDMMC_POWER_PWRCTRL_0 ((uint32_t)0x01) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6669	#define SDMMC_POWER_PWRCTRL_1 ((uint32_t)0x02) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6670
Kojto	115:87f2f5183dfb	6671	/**************** Bit definition for SDMMC_CLKCR register ****************/
Kojto	115:87f2f5183dfb	6672	#define SDMMC_CLKCR_CLKDIV ((uint32_t)0x00FF) /!<Clock divide factor /
Kojto	115:87f2f5183dfb	6673	#define SDMMC_CLKCR_CLKEN ((uint32_t)0x0100) /!<Clock enable bit /
Kojto	115:87f2f5183dfb	6674	#define SDMMC_CLKCR_PWRSAV ((uint32_t)0x0200) /!<Power saving configuration bit /
Kojto	115:87f2f5183dfb	6675	#define SDMMC_CLKCR_BYPASS ((uint32_t)0x0400) /!<Clock divider bypass enable bit /
Kojto	115:87f2f5183dfb	6676
Kojto	115:87f2f5183dfb	6677	#define SDMMC_CLKCR_WIDBUS ((uint32_t)0x1800) /!<WIDBUS[1:0] bits (Wide bus mode enable bit) /
Kojto	115:87f2f5183dfb	6678	#define SDMMC_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6679	#define SDMMC_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6680
Kojto	115:87f2f5183dfb	6681	#define SDMMC_CLKCR_NEGEDGE ((uint32_t)0x2000) /!<SDMMC_CK dephasing selection bit /
Kojto	115:87f2f5183dfb	6682	#define SDMMC_CLKCR_HWFC_EN ((uint32_t)0x4000) /!<HW Flow Control enable /
Kojto	115:87f2f5183dfb	6683
Kojto	115:87f2f5183dfb	6684	/***************** Bit definition for SDMMC_ARG register *****************/
Kojto	115:87f2f5183dfb	6685	#define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!<Command argument /
Kojto	115:87f2f5183dfb	6686
Kojto	115:87f2f5183dfb	6687	/***************** Bit definition for SDMMC_CMD register *****************/
Kojto	115:87f2f5183dfb	6688	#define SDMMC_CMD_CMDINDEX ((uint32_t)0x003F) /!<Command Index /
Kojto	115:87f2f5183dfb	6689
Kojto	115:87f2f5183dfb	6690	#define SDMMC_CMD_WAITRESP ((uint32_t)0x00C0) /!<WAITRESP[1:0] bits (Wait for response bits) /
Kojto	115:87f2f5183dfb	6691	#define SDMMC_CMD_WAITRESP_0 ((uint32_t)0x0040) /!< Bit 0 /
Kojto	115:87f2f5183dfb	6692	#define SDMMC_CMD_WAITRESP_1 ((uint32_t)0x0080) /!< Bit 1 /
Kojto	115:87f2f5183dfb	6693
Kojto	115:87f2f5183dfb	6694	#define SDMMC_CMD_WAITINT ((uint32_t)0x0100) /!<CPSM Waits for Interrupt Request /
Kojto	115:87f2f5183dfb	6695	#define SDMMC_CMD_WAITPEND ((uint32_t)0x0200) /!<CPSM Waits for ends of data transfer (CmdPend internal signal) /
Kojto	115:87f2f5183dfb	6696	#define SDMMC_CMD_CPSMEN ((uint32_t)0x0400) /!<Command path state machine (CPSM) Enable bit /
Kojto	115:87f2f5183dfb	6697	#define SDMMC_CMD_SDIOSUSPEND ((uint32_t)0x0800) /!<SD I/O suspend command /
Kojto	115:87f2f5183dfb	6698
Kojto	115:87f2f5183dfb	6699	/*************** Bit definition for SDMMC_RESPCMD register ***************/
Kojto	115:87f2f5183dfb	6700	#define SDMMC_RESPCMD_RESPCMD ((uint32_t)0x3F) /!<Response command index /
Kojto	115:87f2f5183dfb	6701
Kojto	115:87f2f5183dfb	6702	/**************** Bit definition for SDMMC_RESP0 register ****************/
Kojto	115:87f2f5183dfb	6703	#define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!<Card Status /
Kojto	115:87f2f5183dfb	6704
Kojto	115:87f2f5183dfb	6705	/**************** Bit definition for SDMMC_RESP1 register ****************/
Kojto	115:87f2f5183dfb	6706	#define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!<Card Status /
Kojto	115:87f2f5183dfb	6707
Kojto	115:87f2f5183dfb	6708	/**************** Bit definition for SDMMC_RESP2 register ****************/
Kojto	115:87f2f5183dfb	6709	#define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!<Card Status /
Kojto	115:87f2f5183dfb	6710
Kojto	115:87f2f5183dfb	6711	/**************** Bit definition for SDMMC_RESP3 register ****************/
Kojto	115:87f2f5183dfb	6712	#define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!<Card Status /
Kojto	115:87f2f5183dfb	6713
Kojto	115:87f2f5183dfb	6714	/**************** Bit definition for SDMMC_RESP4 register ****************/
Kojto	115:87f2f5183dfb	6715	#define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!<Card Status /
Kojto	115:87f2f5183dfb	6716
Kojto	115:87f2f5183dfb	6717	/**************** Bit definition for SDMMC_DTIMER register ***************/
Kojto	115:87f2f5183dfb	6718	#define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!<Data timeout period. /
Kojto	115:87f2f5183dfb	6719
Kojto	115:87f2f5183dfb	6720	/**************** Bit definition for SDMMC_DLEN register *****************/
Kojto	115:87f2f5183dfb	6721	#define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!<Data length value /
Kojto	115:87f2f5183dfb	6722
Kojto	115:87f2f5183dfb	6723	/**************** Bit definition for SDMMC_DCTRL register ****************/
Kojto	115:87f2f5183dfb	6724	#define SDMMC_DCTRL_DTEN ((uint32_t)0x0001) /!<Data transfer enabled bit /
Kojto	115:87f2f5183dfb	6725	#define SDMMC_DCTRL_DTDIR ((uint32_t)0x0002) /!<Data transfer direction selection /
Kojto	115:87f2f5183dfb	6726	#define SDMMC_DCTRL_DTMODE ((uint32_t)0x0004) /!<Data transfer mode selection /
Kojto	115:87f2f5183dfb	6727	#define SDMMC_DCTRL_DMAEN ((uint32_t)0x0008) /!<DMA enabled bit /
Kojto	115:87f2f5183dfb	6728
Kojto	115:87f2f5183dfb	6729	#define SDMMC_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /!<DBLOCKSIZE[3:0] bits (Data block size) /
Kojto	115:87f2f5183dfb	6730	#define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6731	#define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6732	#define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	6733	#define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	6734
Kojto	115:87f2f5183dfb	6735	#define SDMMC_DCTRL_RWSTART ((uint32_t)0x0100) /!<Read wait start /
Kojto	115:87f2f5183dfb	6736	#define SDMMC_DCTRL_RWSTOP ((uint32_t)0x0200) /!<Read wait stop /
Kojto	115:87f2f5183dfb	6737	#define SDMMC_DCTRL_RWMOD ((uint32_t)0x0400) /!<Read wait mode /
Kojto	115:87f2f5183dfb	6738	#define SDMMC_DCTRL_SDIOEN ((uint32_t)0x0800) /!<SD I/O enable functions /
Kojto	115:87f2f5183dfb	6739
Kojto	115:87f2f5183dfb	6740	/**************** Bit definition for SDMMC_DCOUNT register ***************/
Kojto	115:87f2f5183dfb	6741	#define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!<Data count value /
Kojto	115:87f2f5183dfb	6742
Kojto	115:87f2f5183dfb	6743	/**************** Bit definition for SDMMC_STA register ******************/
Kojto	115:87f2f5183dfb	6744	#define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001) /!<Command response received (CRC check failed) /
Kojto	115:87f2f5183dfb	6745	#define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002) /!<Data block sent/received (CRC check failed) /
Kojto	115:87f2f5183dfb	6746	#define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004) /!<Command response timeout /
Kojto	115:87f2f5183dfb	6747	#define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008) /!<Data timeout /
Kojto	115:87f2f5183dfb	6748	#define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010) /!<Transmit FIFO underrun error /
Kojto	115:87f2f5183dfb	6749	#define SDMMC_STA_RXOVERR ((uint32_t)0x00000020) /!<Received FIFO overrun error /
Kojto	115:87f2f5183dfb	6750	#define SDMMC_STA_CMDREND ((uint32_t)0x00000040) /!<Command response received (CRC check passed) /
Kojto	115:87f2f5183dfb	6751	#define SDMMC_STA_CMDSENT ((uint32_t)0x00000080) /!<Command sent (no response required) /
Kojto	115:87f2f5183dfb	6752	#define SDMMC_STA_DATAEND ((uint32_t)0x00000100) /!<Data end (data counter, SDIDCOUNT, is zero) /
Kojto	115:87f2f5183dfb	6753	#define SDMMC_STA_DBCKEND ((uint32_t)0x00000400) /!<Data block sent/received (CRC check passed) /
Kojto	115:87f2f5183dfb	6754	#define SDMMC_STA_CMDACT ((uint32_t)0x00000800) /!<Command transfer in progress /
Kojto	115:87f2f5183dfb	6755	#define SDMMC_STA_TXACT ((uint32_t)0x00001000) /!<Data transmit in progress /
Kojto	115:87f2f5183dfb	6756	#define SDMMC_STA_RXACT ((uint32_t)0x00002000) /!<Data receive in progress /
Kojto	115:87f2f5183dfb	6757	#define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000) /!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
Kojto	115:87f2f5183dfb	6758	#define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000) /!<Receive FIFO Half Full: there are at least 8 words in the FIFO /
Kojto	115:87f2f5183dfb	6759	#define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000) /!<Transmit FIFO full /
Kojto	115:87f2f5183dfb	6760	#define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000) /!<Receive FIFO full /
Kojto	115:87f2f5183dfb	6761	#define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000) /!<Transmit FIFO empty /
Kojto	115:87f2f5183dfb	6762	#define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000) /!<Receive FIFO empty /
Kojto	115:87f2f5183dfb	6763	#define SDMMC_STA_TXDAVL ((uint32_t)0x00100000) /!<Data available in transmit FIFO /
Kojto	115:87f2f5183dfb	6764	#define SDMMC_STA_RXDAVL ((uint32_t)0x00200000) /!<Data available in receive FIFO /
Kojto	115:87f2f5183dfb	6765	#define SDMMC_STA_SDIOIT ((uint32_t)0x00400000) /!<SDMMC interrupt received /
Kojto	115:87f2f5183dfb	6766
Kojto	115:87f2f5183dfb	6767	/***************** Bit definition for SDMMC_ICR register *****************/
Kojto	115:87f2f5183dfb	6768	#define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001) /!<CCRCFAIL flag clear bit /
Kojto	115:87f2f5183dfb	6769	#define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002) /!<DCRCFAIL flag clear bit /
Kojto	115:87f2f5183dfb	6770	#define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!<CTIMEOUT flag clear bit /
Kojto	115:87f2f5183dfb	6771	#define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!<DTIMEOUT flag clear bit /
Kojto	115:87f2f5183dfb	6772	#define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010) /!<TXUNDERR flag clear bit /
Kojto	115:87f2f5183dfb	6773	#define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020) /!<RXOVERR flag clear bit /
Kojto	115:87f2f5183dfb	6774	#define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040) /!<CMDREND flag clear bit /
Kojto	115:87f2f5183dfb	6775	#define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080) /!<CMDSENT flag clear bit /
Kojto	115:87f2f5183dfb	6776	#define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100) /!<DATAEND flag clear bit /
Kojto	115:87f2f5183dfb	6777	#define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400) /!<DBCKEND flag clear bit /
Kojto	115:87f2f5183dfb	6778	#define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000) /!<SDMMCIT flag clear bit /
Kojto	115:87f2f5183dfb	6779
Kojto	115:87f2f5183dfb	6780	/**************** Bit definition for SDMMC_MASK register *****************/
Kojto	115:87f2f5183dfb	6781	#define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!<Command CRC Fail Interrupt Enable /
Kojto	115:87f2f5183dfb	6782	#define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!<Data CRC Fail Interrupt Enable /
Kojto	115:87f2f5183dfb	6783	#define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!<Command TimeOut Interrupt Enable /
Kojto	115:87f2f5183dfb	6784	#define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!<Data TimeOut Interrupt Enable /
Kojto	115:87f2f5183dfb	6785	#define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!<Tx FIFO UnderRun Error Interrupt Enable /
Kojto	115:87f2f5183dfb	6786	#define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020) /!<Rx FIFO OverRun Error Interrupt Enable /
Kojto	115:87f2f5183dfb	6787	#define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040) /!<Command Response Received Interrupt Enable /
Kojto	115:87f2f5183dfb	6788	#define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080) /!<Command Sent Interrupt Enable /
Kojto	115:87f2f5183dfb	6789	#define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100) /!<Data End Interrupt Enable /
Kojto	115:87f2f5183dfb	6790	#define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400) /!<Data Block End Interrupt Enable /
Kojto	115:87f2f5183dfb	6791	#define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800) /!<CCommand Acting Interrupt Enable /
Kojto	115:87f2f5183dfb	6792	#define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000) /!<Data Transmit Acting Interrupt Enable /
Kojto	115:87f2f5183dfb	6793	#define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000) /!<Data receive acting interrupt enabled /
Kojto	115:87f2f5183dfb	6794	#define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!<Tx FIFO Half Empty interrupt Enable /
Kojto	115:87f2f5183dfb	6795	#define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!<Rx FIFO Half Full interrupt Enable /
Kojto	115:87f2f5183dfb	6796	#define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!<Tx FIFO Full interrupt Enable /
Kojto	115:87f2f5183dfb	6797	#define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!<Rx FIFO Full interrupt Enable /
Kojto	115:87f2f5183dfb	6798	#define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!<Tx FIFO Empty interrupt Enable /
Kojto	115:87f2f5183dfb	6799	#define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!<Rx FIFO Empty interrupt Enable /
Kojto	115:87f2f5183dfb	6800	#define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000) /!<Data available in Tx FIFO interrupt Enable /
Kojto	115:87f2f5183dfb	6801	#define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000) /!<Data available in Rx FIFO interrupt Enable /
Kojto	115:87f2f5183dfb	6802	#define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000) /!<SDMMC Mode Interrupt Received interrupt Enable /
Kojto	115:87f2f5183dfb	6803
Kojto	115:87f2f5183dfb	6804	/*************** Bit definition for SDMMC_FIFOCNT register ***************/
Kojto	115:87f2f5183dfb	6805	#define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!<Remaining number of words to be written to or read from the FIFO /
Kojto	115:87f2f5183dfb	6806
Kojto	115:87f2f5183dfb	6807	/**************** Bit definition for SDMMC_FIFO register *****************/
Kojto	115:87f2f5183dfb	6808	#define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!<Receive and transmit FIFO data /
Kojto	115:87f2f5183dfb	6809
Kojto	115:87f2f5183dfb	6810	/******************************************************************************/
Kojto	115:87f2f5183dfb	6811	/* */
Kojto	115:87f2f5183dfb	6812	/* Serial Peripheral Interface (SPI) */
Kojto	115:87f2f5183dfb	6813	/* */
Kojto	115:87f2f5183dfb	6814	/******************************************************************************/
Kojto	115:87f2f5183dfb	6815	/***************** Bit definition for SPI_CR1 register ******************/
Kojto	115:87f2f5183dfb	6816	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
Kojto	115:87f2f5183dfb	6817	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
Kojto	115:87f2f5183dfb	6818	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
Kojto	115:87f2f5183dfb	6819	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
Kojto	115:87f2f5183dfb	6820	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
Kojto	115:87f2f5183dfb	6821	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
Kojto	115:87f2f5183dfb	6822	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
Kojto	115:87f2f5183dfb	6823	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
Kojto	115:87f2f5183dfb	6824	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
Kojto	115:87f2f5183dfb	6825	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
Kojto	115:87f2f5183dfb	6826	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
Kojto	115:87f2f5183dfb	6827	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
Kojto	115:87f2f5183dfb	6828	#define SPI_CR1_CRCL ((uint32_t)0x00000800) /!< CRC Length /
Kojto	115:87f2f5183dfb	6829	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
Kojto	115:87f2f5183dfb	6830	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
Kojto	115:87f2f5183dfb	6831	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
Kojto	115:87f2f5183dfb	6832	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
Kojto	115:87f2f5183dfb	6833
Kojto	115:87f2f5183dfb	6834	/***************** Bit definition for SPI_CR2 register ******************/
Kojto	115:87f2f5183dfb	6835	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
Kojto	115:87f2f5183dfb	6836	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
Kojto	115:87f2f5183dfb	6837	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
Kojto	115:87f2f5183dfb	6838	#define SPI_CR2_NSSP ((uint32_t)0x00000008) /!< NSS pulse management Enable /
Kojto	115:87f2f5183dfb	6839	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame Format Enable /
Kojto	115:87f2f5183dfb	6840	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
Kojto	115:87f2f5183dfb	6841	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
Kojto	115:87f2f5183dfb	6842	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
Kojto	115:87f2f5183dfb	6843	#define SPI_CR2_DS ((uint32_t)0x00000F00) /!< DS[3:0] Data Size /
Kojto	115:87f2f5183dfb	6844	#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	115:87f2f5183dfb	6845	#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	115:87f2f5183dfb	6846	#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /!< Bit 2 /
Kojto	115:87f2f5183dfb	6847	#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /!< Bit 3 /
Kojto	115:87f2f5183dfb	6848	#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /!< FIFO reception Threshold /
Kojto	115:87f2f5183dfb	6849	#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /!< Last DMA transfer for reception /
Kojto	115:87f2f5183dfb	6850	#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /!< Last DMA transfer for transmission /
Kojto	115:87f2f5183dfb	6851
Kojto	115:87f2f5183dfb	6852	/****************** Bit definition for SPI_SR register ******************/
Kojto	115:87f2f5183dfb	6853	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
Kojto	115:87f2f5183dfb	6854	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
Kojto	115:87f2f5183dfb	6855	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
Kojto	115:87f2f5183dfb	6856	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
Kojto	115:87f2f5183dfb	6857	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
Kojto	115:87f2f5183dfb	6858	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
Kojto	115:87f2f5183dfb	6859	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
Kojto	115:87f2f5183dfb	6860	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
Kojto	115:87f2f5183dfb	6861	#define SPI_SR_FRE ((uint32_t)0x00000100) /!< TI frame format error /
Kojto	115:87f2f5183dfb	6862	#define SPI_SR_FRLVL ((uint32_t)0x00000600) /!< FIFO Reception Level /
Kojto	115:87f2f5183dfb	6863	#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /!< Bit 0 /
Kojto	115:87f2f5183dfb	6864	#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /!< Bit 1 /
Kojto	115:87f2f5183dfb	6865	#define SPI_SR_FTLVL ((uint32_t)0x00001800) /!< FIFO Transmission Level /
Kojto	115:87f2f5183dfb	6866	#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /!< Bit 0 /
Kojto	115:87f2f5183dfb	6867	#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	6868
Kojto	115:87f2f5183dfb	6869	/****************** Bit definition for SPI_DR register ******************/
Kojto	115:87f2f5183dfb	6870	#define SPI_DR_DR ((uint32_t)0xFFFF) /!< Data Register /
Kojto	115:87f2f5183dfb	6871
Kojto	115:87f2f5183dfb	6872	/***************** Bit definition for SPI_CRCPR register ****************/
Kojto	115:87f2f5183dfb	6873	#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFF) /!< CRC polynomial register /
Kojto	115:87f2f5183dfb	6874
Kojto	115:87f2f5183dfb	6875	/**************** Bit definition for SPI_RXCRCR register ****************/
Kojto	115:87f2f5183dfb	6876	#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFF) /!< Rx CRC Register /
Kojto	115:87f2f5183dfb	6877
Kojto	115:87f2f5183dfb	6878	/**************** Bit definition for SPI_TXCRCR register ****************/
Kojto	115:87f2f5183dfb	6879	#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFF) /!< Tx CRC Register /
Kojto	115:87f2f5183dfb	6880
Kojto	115:87f2f5183dfb	6881	/**************** Bit definition for SPI_I2SCFGR register ***************/
Kojto	115:87f2f5183dfb	6882	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!<Channel length (number of bits per audio channel) /
Kojto	115:87f2f5183dfb	6883	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!<DATLEN[1:0] bits (Data length to be transferred) /
Kojto	115:87f2f5183dfb	6884	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6885	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6886	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!<steady state clock polarity /
Kojto	115:87f2f5183dfb	6887	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!<I2SSTD[1:0] bits (I2S standard selection) /
Kojto	115:87f2f5183dfb	6888	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6889	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6890	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!<PCM frame synchronization /
Kojto	115:87f2f5183dfb	6891	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
Kojto	115:87f2f5183dfb	6892	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	6893	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	6894	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!<I2S Enable /
Kojto	115:87f2f5183dfb	6895	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!<I2S mode selection /
Kojto	115:87f2f5183dfb	6896	#define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /!<Asynchronous start enable /
Kojto	115:87f2f5183dfb	6897
Kojto	115:87f2f5183dfb	6898	/**************** Bit definition for SPI_I2SPR register *****************/
Kojto	115:87f2f5183dfb	6899	#define SPI_I2SPR_I2SDIV ((uint32_t)0x00FF) /!<I2S Linear prescaler /
Kojto	115:87f2f5183dfb	6900	#define SPI_I2SPR_ODD ((uint32_t)0x0100) /!<Odd factor for the prescaler /
Kojto	115:87f2f5183dfb	6901	#define SPI_I2SPR_MCKOE ((uint32_t)0x0200) /!<Master Clock Output Enable /
Kojto	115:87f2f5183dfb	6902
Kojto	115:87f2f5183dfb	6903
Kojto	115:87f2f5183dfb	6904	/******************************************************************************/
Kojto	115:87f2f5183dfb	6905	/* */
Kojto	115:87f2f5183dfb	6906	/* SYSCFG */
Kojto	115:87f2f5183dfb	6907	/* */
Kojto	115:87f2f5183dfb	6908	/******************************************************************************/
Kojto	115:87f2f5183dfb	6909	/**************** Bit definition for SYSCFG_MEMRMP register *************/
Kojto	115:87f2f5183dfb	6910	#define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /!< Boot information after Reset /
Kojto	115:87f2f5183dfb	6911
Kojto	115:87f2f5183dfb	6912	#define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) /!< FMC Memory Mapping swapping /
Kojto	115:87f2f5183dfb	6913	#define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	6914	#define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	6915
Kojto	115:87f2f5183dfb	6916	/**************** Bit definition for SYSCFG_PMC register ****************/
Kojto	115:87f2f5183dfb	6917	#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /!< Refer to AN4073 on how to use this bit /
Kojto	115:87f2f5183dfb	6918	#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /!< Refer to AN4073 on how to use this bit /
Kojto	115:87f2f5183dfb	6919	#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /!< Refer to AN4073 on how to use this bit /
Kojto	115:87f2f5183dfb	6920	#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /!< Refer to AN4073 on how to use this bit /
Kojto	115:87f2f5183dfb	6921
Kojto	115:87f2f5183dfb	6922	#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /!<Ethernet PHY interface selection /
Kojto	115:87f2f5183dfb	6923
Kojto	115:87f2f5183dfb	6924	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
Kojto	115:87f2f5183dfb	6925	#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /!<EXTI 0 configuration /
Kojto	115:87f2f5183dfb	6926	#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /!<EXTI 1 configuration /
Kojto	115:87f2f5183dfb	6927	#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /!<EXTI 2 configuration /
Kojto	115:87f2f5183dfb	6928	#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /!<EXTI 3 configuration /
Kojto	115:87f2f5183dfb	6929	/**
Kojto	115:87f2f5183dfb	6930	* @brief EXTI0 configuration
Kojto	115:87f2f5183dfb	6931	*/
Kojto	115:87f2f5183dfb	6932	#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /!<PA[0] pin /
Kojto	115:87f2f5183dfb	6933	#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /!<PB[0] pin /
Kojto	115:87f2f5183dfb	6934	#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /!<PC[0] pin /
Kojto	115:87f2f5183dfb	6935	#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /!<PD[0] pin /
Kojto	115:87f2f5183dfb	6936	#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /!<PE[0] pin /
Kojto	115:87f2f5183dfb	6937	#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /!<PF[0] pin /
Kojto	115:87f2f5183dfb	6938	#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /!<PG[0] pin /
Kojto	115:87f2f5183dfb	6939	#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /!<PH[0] pin /
Kojto	115:87f2f5183dfb	6940	#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /!<PI[0] pin /
Kojto	115:87f2f5183dfb	6941	#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /!<PJ[0] pin /
Kojto	115:87f2f5183dfb	6942	#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /!<PK[0] pin /
Kojto	115:87f2f5183dfb	6943
Kojto	115:87f2f5183dfb	6944	/**
Kojto	115:87f2f5183dfb	6945	* @brief EXTI1 configuration
Kojto	115:87f2f5183dfb	6946	*/
Kojto	115:87f2f5183dfb	6947	#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /!<PA[1] pin /
Kojto	115:87f2f5183dfb	6948	#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /!<PB[1] pin /
Kojto	115:87f2f5183dfb	6949	#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /!<PC[1] pin /
Kojto	115:87f2f5183dfb	6950	#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /!<PD[1] pin /
Kojto	115:87f2f5183dfb	6951	#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /!<PE[1] pin /
Kojto	115:87f2f5183dfb	6952	#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /!<PF[1] pin /
Kojto	115:87f2f5183dfb	6953	#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /!<PG[1] pin /
Kojto	115:87f2f5183dfb	6954	#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /!<PH[1] pin /
Kojto	115:87f2f5183dfb	6955	#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /!<PI[1] pin /
Kojto	115:87f2f5183dfb	6956	#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /!<PJ[1] pin /
Kojto	115:87f2f5183dfb	6957	#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /!<PK[1] pin /
Kojto	115:87f2f5183dfb	6958
Kojto	115:87f2f5183dfb	6959	/**
Kojto	115:87f2f5183dfb	6960	* @brief EXTI2 configuration
Kojto	115:87f2f5183dfb	6961	*/
Kojto	115:87f2f5183dfb	6962	#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /!<PA[2] pin /
Kojto	115:87f2f5183dfb	6963	#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /!<PB[2] pin /
Kojto	115:87f2f5183dfb	6964	#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /!<PC[2] pin /
Kojto	115:87f2f5183dfb	6965	#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /!<PD[2] pin /
Kojto	115:87f2f5183dfb	6966	#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /!<PE[2] pin /
Kojto	115:87f2f5183dfb	6967	#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /!<PF[2] pin /
Kojto	115:87f2f5183dfb	6968	#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /!<PG[2] pin /
Kojto	115:87f2f5183dfb	6969	#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /!<PH[2] pin /
Kojto	115:87f2f5183dfb	6970	#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /!<PI[2] pin /
Kojto	115:87f2f5183dfb	6971	#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /!<PJ[2] pin /
Kojto	115:87f2f5183dfb	6972	#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /!<PK[2] pin /
Kojto	115:87f2f5183dfb	6973
Kojto	115:87f2f5183dfb	6974	/**
Kojto	115:87f2f5183dfb	6975	* @brief EXTI3 configuration
Kojto	115:87f2f5183dfb	6976	*/
Kojto	115:87f2f5183dfb	6977	#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /!<PA[3] pin /
Kojto	115:87f2f5183dfb	6978	#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /!<PB[3] pin /
Kojto	115:87f2f5183dfb	6979	#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /!<PC[3] pin /
Kojto	115:87f2f5183dfb	6980	#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /!<PD[3] pin /
Kojto	115:87f2f5183dfb	6981	#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /!<PE[3] pin /
Kojto	115:87f2f5183dfb	6982	#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /!<PF[3] pin /
Kojto	115:87f2f5183dfb	6983	#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /!<PG[3] pin /
Kojto	115:87f2f5183dfb	6984	#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /!<PH[3] pin /
Kojto	115:87f2f5183dfb	6985	#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /!<PI[3] pin /
Kojto	115:87f2f5183dfb	6986	#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /!<PJ[3] pin /
Kojto	115:87f2f5183dfb	6987	#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /!<PK[3] pin /
Kojto	115:87f2f5183dfb	6988
Kojto	115:87f2f5183dfb	6989	/*************** Bit definition for SYSCFG_EXTICR2 register *************/
Kojto	115:87f2f5183dfb	6990	#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /!<EXTI 4 configuration /
Kojto	115:87f2f5183dfb	6991	#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /!<EXTI 5 configuration /
Kojto	115:87f2f5183dfb	6992	#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /!<EXTI 6 configuration /
Kojto	115:87f2f5183dfb	6993	#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /!<EXTI 7 configuration /
Kojto	115:87f2f5183dfb	6994	/**
Kojto	115:87f2f5183dfb	6995	* @brief EXTI4 configuration
Kojto	115:87f2f5183dfb	6996	*/
Kojto	115:87f2f5183dfb	6997	#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /!<PA[4] pin /
Kojto	115:87f2f5183dfb	6998	#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /!<PB[4] pin /
Kojto	115:87f2f5183dfb	6999	#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /!<PC[4] pin /
Kojto	115:87f2f5183dfb	7000	#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /!<PD[4] pin /
Kojto	115:87f2f5183dfb	7001	#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /!<PE[4] pin /
Kojto	115:87f2f5183dfb	7002	#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /!<PF[4] pin /
Kojto	115:87f2f5183dfb	7003	#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /!<PG[4] pin /
Kojto	115:87f2f5183dfb	7004	#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /!<PH[4] pin /
Kojto	115:87f2f5183dfb	7005	#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /!<PI[4] pin /
Kojto	115:87f2f5183dfb	7006	#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /!<PJ[4] pin /
Kojto	115:87f2f5183dfb	7007	#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /!<PK[4] pin /
Kojto	115:87f2f5183dfb	7008
Kojto	115:87f2f5183dfb	7009	/**
Kojto	115:87f2f5183dfb	7010	* @brief EXTI5 configuration
Kojto	115:87f2f5183dfb	7011	*/
Kojto	115:87f2f5183dfb	7012	#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /!<PA[5] pin /
Kojto	115:87f2f5183dfb	7013	#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /!<PB[5] pin /
Kojto	115:87f2f5183dfb	7014	#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /!<PC[5] pin /
Kojto	115:87f2f5183dfb	7015	#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /!<PD[5] pin /
Kojto	115:87f2f5183dfb	7016	#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /!<PE[5] pin /
Kojto	115:87f2f5183dfb	7017	#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /!<PF[5] pin /
Kojto	115:87f2f5183dfb	7018	#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /!<PG[5] pin /
Kojto	115:87f2f5183dfb	7019	#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /!<PH[5] pin /
Kojto	115:87f2f5183dfb	7020	#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /!<PI[5] pin /
Kojto	115:87f2f5183dfb	7021	#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /!<PJ[5] pin /
Kojto	115:87f2f5183dfb	7022	#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /!<PK[5] pin /
Kojto	115:87f2f5183dfb	7023
Kojto	115:87f2f5183dfb	7024	/**
Kojto	115:87f2f5183dfb	7025	* @brief EXTI6 configuration
Kojto	115:87f2f5183dfb	7026	*/
Kojto	115:87f2f5183dfb	7027	#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /!<PA[6] pin /
Kojto	115:87f2f5183dfb	7028	#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /!<PB[6] pin /
Kojto	115:87f2f5183dfb	7029	#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /!<PC[6] pin /
Kojto	115:87f2f5183dfb	7030	#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /!<PD[6] pin /
Kojto	115:87f2f5183dfb	7031	#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /!<PE[6] pin /
Kojto	115:87f2f5183dfb	7032	#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /!<PF[6] pin /
Kojto	115:87f2f5183dfb	7033	#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /!<PG[6] pin /
Kojto	115:87f2f5183dfb	7034	#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /!<PH[6] pin /
Kojto	115:87f2f5183dfb	7035	#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /!<PI[6] pin /
Kojto	115:87f2f5183dfb	7036	#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /!<PJ[6] pin /
Kojto	115:87f2f5183dfb	7037	#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /!<PK[6] pin /
Kojto	115:87f2f5183dfb	7038
Kojto	115:87f2f5183dfb	7039	/**
Kojto	115:87f2f5183dfb	7040	* @brief EXTI7 configuration
Kojto	115:87f2f5183dfb	7041	*/
Kojto	115:87f2f5183dfb	7042	#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /!<PA[7] pin /
Kojto	115:87f2f5183dfb	7043	#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /!<PB[7] pin /
Kojto	115:87f2f5183dfb	7044	#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /!<PC[7] pin /
Kojto	115:87f2f5183dfb	7045	#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /!<PD[7] pin /
Kojto	115:87f2f5183dfb	7046	#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /!<PE[7] pin /
Kojto	115:87f2f5183dfb	7047	#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /!<PF[7] pin /
Kojto	115:87f2f5183dfb	7048	#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /!<PG[7] pin /
Kojto	115:87f2f5183dfb	7049	#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /!<PH[7] pin /
Kojto	115:87f2f5183dfb	7050	#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /!<PI[7] pin /
Kojto	115:87f2f5183dfb	7051	#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /!<PJ[7] pin /
Kojto	115:87f2f5183dfb	7052	#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /!<PK[7] pin /
Kojto	115:87f2f5183dfb	7053
Kojto	115:87f2f5183dfb	7054	/*************** Bit definition for SYSCFG_EXTICR3 register *************/
Kojto	115:87f2f5183dfb	7055	#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /!<EXTI 8 configuration /
Kojto	115:87f2f5183dfb	7056	#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /!<EXTI 9 configuration /
Kojto	115:87f2f5183dfb	7057	#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /!<EXTI 10 configuration /
Kojto	115:87f2f5183dfb	7058	#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /!<EXTI 11 configuration /
Kojto	115:87f2f5183dfb	7059
Kojto	115:87f2f5183dfb	7060	/**
Kojto	115:87f2f5183dfb	7061	* @brief EXTI8 configuration
Kojto	115:87f2f5183dfb	7062	*/
Kojto	115:87f2f5183dfb	7063	#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /!<PA[8] pin /
Kojto	115:87f2f5183dfb	7064	#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /!<PB[8] pin /
Kojto	115:87f2f5183dfb	7065	#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /!<PC[8] pin /
Kojto	115:87f2f5183dfb	7066	#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /!<PD[8] pin /
Kojto	115:87f2f5183dfb	7067	#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /!<PE[8] pin /
Kojto	115:87f2f5183dfb	7068	#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /!<PF[8] pin /
Kojto	115:87f2f5183dfb	7069	#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /!<PG[8] pin /
Kojto	115:87f2f5183dfb	7070	#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /!<PH[8] pin /
Kojto	115:87f2f5183dfb	7071	#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /!<PI[8] pin /
Kojto	115:87f2f5183dfb	7072	#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /!<PJ[8] pin /
Kojto	115:87f2f5183dfb	7073
Kojto	115:87f2f5183dfb	7074	/**
Kojto	115:87f2f5183dfb	7075	* @brief EXTI9 configuration
Kojto	115:87f2f5183dfb	7076	*/
Kojto	115:87f2f5183dfb	7077	#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /!<PA[9] pin /
Kojto	115:87f2f5183dfb	7078	#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /!<PB[9] pin /
Kojto	115:87f2f5183dfb	7079	#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /!<PC[9] pin /
Kojto	115:87f2f5183dfb	7080	#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /!<PD[9] pin /
Kojto	115:87f2f5183dfb	7081	#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /!<PE[9] pin /
Kojto	115:87f2f5183dfb	7082	#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /!<PF[9] pin /
Kojto	115:87f2f5183dfb	7083	#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /!<PG[9] pin /
Kojto	115:87f2f5183dfb	7084	#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /!<PH[9] pin /
Kojto	115:87f2f5183dfb	7085	#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /!<PI[9] pin /
Kojto	115:87f2f5183dfb	7086	#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /!<PJ[9] pin /
Kojto	115:87f2f5183dfb	7087
Kojto	115:87f2f5183dfb	7088	/**
Kojto	115:87f2f5183dfb	7089	* @brief EXTI10 configuration
Kojto	115:87f2f5183dfb	7090	*/
Kojto	115:87f2f5183dfb	7091	#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /!<PA[10] pin /
Kojto	115:87f2f5183dfb	7092	#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /!<PB[10] pin /
Kojto	115:87f2f5183dfb	7093	#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /!<PC[10] pin /
Kojto	115:87f2f5183dfb	7094	#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /!<PD[10] pin /
Kojto	115:87f2f5183dfb	7095	#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /!<PE[10] pin /
Kojto	115:87f2f5183dfb	7096	#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /!<PF[10] pin /
Kojto	115:87f2f5183dfb	7097	#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /!<PG[10] pin /
Kojto	115:87f2f5183dfb	7098	#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /!<PH[10] pin /
Kojto	115:87f2f5183dfb	7099	#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /!<PI[10] pin /
Kojto	115:87f2f5183dfb	7100	#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /!<PJ[10] pin /
Kojto	115:87f2f5183dfb	7101
Kojto	115:87f2f5183dfb	7102	/**
Kojto	115:87f2f5183dfb	7103	* @brief EXTI11 configuration
Kojto	115:87f2f5183dfb	7104	*/
Kojto	115:87f2f5183dfb	7105	#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /!<PA[11] pin /
Kojto	115:87f2f5183dfb	7106	#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /!<PB[11] pin /
Kojto	115:87f2f5183dfb	7107	#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /!<PC[11] pin /
Kojto	115:87f2f5183dfb	7108	#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /!<PD[11] pin /
Kojto	115:87f2f5183dfb	7109	#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /!<PE[11] pin /
Kojto	115:87f2f5183dfb	7110	#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /!<PF[11] pin /
Kojto	115:87f2f5183dfb	7111	#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /!<PG[11] pin /
Kojto	115:87f2f5183dfb	7112	#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /!<PH[11] pin /
Kojto	115:87f2f5183dfb	7113	#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /!<PI[11] pin /
Kojto	115:87f2f5183dfb	7114	#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /!<PJ[11] pin /
Kojto	115:87f2f5183dfb	7115
Kojto	115:87f2f5183dfb	7116
Kojto	115:87f2f5183dfb	7117	/*************** Bit definition for SYSCFG_EXTICR4 register *************/
Kojto	115:87f2f5183dfb	7118	#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /!<EXTI 12 configuration /
Kojto	115:87f2f5183dfb	7119	#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /!<EXTI 13 configuration /
Kojto	115:87f2f5183dfb	7120	#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /!<EXTI 14 configuration /
Kojto	115:87f2f5183dfb	7121	#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /!<EXTI 15 configuration /
Kojto	115:87f2f5183dfb	7122	/**
Kojto	115:87f2f5183dfb	7123	* @brief EXTI12 configuration
Kojto	115:87f2f5183dfb	7124	*/
Kojto	115:87f2f5183dfb	7125	#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /!<PA[12] pin /
Kojto	115:87f2f5183dfb	7126	#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /!<PB[12] pin /
Kojto	115:87f2f5183dfb	7127	#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /!<PC[12] pin /
Kojto	115:87f2f5183dfb	7128	#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /!<PD[12] pin /
Kojto	115:87f2f5183dfb	7129	#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /!<PE[12] pin /
Kojto	115:87f2f5183dfb	7130	#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /!<PF[12] pin /
Kojto	115:87f2f5183dfb	7131	#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /!<PG[12] pin /
Kojto	115:87f2f5183dfb	7132	#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /!<PH[12] pin /
Kojto	115:87f2f5183dfb	7133	#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /!<PI[12] pin /
Kojto	115:87f2f5183dfb	7134	#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /!<PJ[12] pin /
Kojto	115:87f2f5183dfb	7135
Kojto	115:87f2f5183dfb	7136	/**
Kojto	115:87f2f5183dfb	7137	* @brief EXTI13 configuration
Kojto	115:87f2f5183dfb	7138	*/
Kojto	115:87f2f5183dfb	7139	#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /!<PA[13] pin /
Kojto	115:87f2f5183dfb	7140	#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /!<PB[13] pin /
Kojto	115:87f2f5183dfb	7141	#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /!<PC[13] pin /
Kojto	115:87f2f5183dfb	7142	#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /!<PD[13] pin /
Kojto	115:87f2f5183dfb	7143	#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /!<PE[13] pin /
Kojto	115:87f2f5183dfb	7144	#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /!<PF[13] pin /
Kojto	115:87f2f5183dfb	7145	#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /!<PG[13] pin /
Kojto	115:87f2f5183dfb	7146	#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /!<PH[13] pin /
Kojto	115:87f2f5183dfb	7147	#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /!<PI[13] pin /
Kojto	115:87f2f5183dfb	7148	#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /!<PJ[13] pin /
Kojto	115:87f2f5183dfb	7149
Kojto	115:87f2f5183dfb	7150	/**
Kojto	115:87f2f5183dfb	7151	* @brief EXTI14 configuration
Kojto	115:87f2f5183dfb	7152	*/
Kojto	115:87f2f5183dfb	7153	#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /!<PA[14] pin /
Kojto	115:87f2f5183dfb	7154	#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /!<PB[14] pin /
Kojto	115:87f2f5183dfb	7155	#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /!<PC[14] pin /
Kojto	115:87f2f5183dfb	7156	#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /!<PD[14] pin /
Kojto	115:87f2f5183dfb	7157	#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /!<PE[14] pin /
Kojto	115:87f2f5183dfb	7158	#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /!<PF[14] pin /
Kojto	115:87f2f5183dfb	7159	#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /!<PG[14] pin /
Kojto	115:87f2f5183dfb	7160	#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /!<PH[14] pin /
Kojto	115:87f2f5183dfb	7161	#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /!<PI[14] pin /
Kojto	115:87f2f5183dfb	7162	#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /!<PJ[14] pin /
Kojto	115:87f2f5183dfb	7163
Kojto	115:87f2f5183dfb	7164	/**
Kojto	115:87f2f5183dfb	7165	* @brief EXTI15 configuration
Kojto	115:87f2f5183dfb	7166	*/
Kojto	115:87f2f5183dfb	7167	#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /!<PA[15] pin /
Kojto	115:87f2f5183dfb	7168	#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /!<PB[15] pin /
Kojto	115:87f2f5183dfb	7169	#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /!<PC[15] pin /
Kojto	115:87f2f5183dfb	7170	#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /!<PD[15] pin /
Kojto	115:87f2f5183dfb	7171	#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /!<PE[15] pin /
Kojto	115:87f2f5183dfb	7172	#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /!<PF[15] pin /
Kojto	115:87f2f5183dfb	7173	#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /!<PG[15] pin /
Kojto	115:87f2f5183dfb	7174	#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /!<PH[15] pin /
Kojto	115:87f2f5183dfb	7175	#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /!<PI[15] pin /
Kojto	115:87f2f5183dfb	7176	#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /!<PJ[15] pin /
Kojto	115:87f2f5183dfb	7177
Kojto	115:87f2f5183dfb	7178	/**************** Bit definition for SYSCFG_CMPCR register **************/
Kojto	115:87f2f5183dfb	7179	#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /!<Compensation cell power-down /
Kojto	115:87f2f5183dfb	7180	#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /!<Compensation cell ready flag/
Kojto	115:87f2f5183dfb	7181
Kojto	115:87f2f5183dfb	7182	/******************************************************************************/
Kojto	115:87f2f5183dfb	7183	/* */
Kojto	115:87f2f5183dfb	7184	/* TIM */
Kojto	115:87f2f5183dfb	7185	/* */
Kojto	115:87f2f5183dfb	7186	/******************************************************************************/
Kojto	115:87f2f5183dfb	7187	/***************** Bit definition for TIM_CR1 register ******************/
Kojto	115:87f2f5183dfb	7188	#define TIM_CR1_CEN ((uint32_t)0x0001) /!<Counter enable /
Kojto	115:87f2f5183dfb	7189	#define TIM_CR1_UDIS ((uint32_t)0x0002) /!<Update disable /
Kojto	115:87f2f5183dfb	7190	#define TIM_CR1_URS ((uint32_t)0x0004) /!<Update request source /
Kojto	115:87f2f5183dfb	7191	#define TIM_CR1_OPM ((uint32_t)0x0008) /!<One pulse mode /
Kojto	115:87f2f5183dfb	7192	#define TIM_CR1_DIR ((uint32_t)0x0010) /!<Direction /
Kojto	115:87f2f5183dfb	7193
Kojto	115:87f2f5183dfb	7194	#define TIM_CR1_CMS ((uint32_t)0x0060) /!<CMS[1:0] bits (Center-aligned mode selection) /
Kojto	115:87f2f5183dfb	7195	#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7196	#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7197
Kojto	115:87f2f5183dfb	7198	#define TIM_CR1_ARPE ((uint32_t)0x0080) /!<Auto-reload preload enable /
Kojto	115:87f2f5183dfb	7199
Kojto	115:87f2f5183dfb	7200	#define TIM_CR1_CKD ((uint32_t)0x0300) /!<CKD[1:0] bits (clock division) /
Kojto	115:87f2f5183dfb	7201	#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7202	#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7203	#define TIM_CR1_UIFREMAP ((uint32_t)0x0800) /!<UIF status bit /
Kojto	115:87f2f5183dfb	7204
Kojto	115:87f2f5183dfb	7205	/***************** Bit definition for TIM_CR2 register ******************/
Kojto	115:87f2f5183dfb	7206	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
Kojto	115:87f2f5183dfb	7207	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
Kojto	115:87f2f5183dfb	7208	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
Kojto	115:87f2f5183dfb	7209
Kojto	115:87f2f5183dfb	7210	#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /!<Output Idle state 4 (OC4 output) /
Kojto	115:87f2f5183dfb	7211	#define TIM_CR2_OIS6 ((uint32_t)0x00040000) /!<Output Idle state 4 (OC4 output) /
Kojto	115:87f2f5183dfb	7212
Kojto	115:87f2f5183dfb	7213	#define TIM_CR2_MMS ((uint32_t)0x0070) /!<MMS[2:0] bits (Master Mode Selection) /
Kojto	115:87f2f5183dfb	7214	#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7215	#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7216	#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7217
Kojto	115:87f2f5183dfb	7218	#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /!<MMS[2:0] bits (Master Mode Selection) /
Kojto	115:87f2f5183dfb	7219	#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7220	#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7221	#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7222	#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7223
Kojto	115:87f2f5183dfb	7224	#define TIM_CR2_TI1S ((uint32_t)0x0080) /!<TI1 Selection /
Kojto	115:87f2f5183dfb	7225	#define TIM_CR2_OIS1 ((uint32_t)0x0100) /!<Output Idle state 1 (OC1 output) /
Kojto	115:87f2f5183dfb	7226	#define TIM_CR2_OIS1N ((uint32_t)0x0200) /!<Output Idle state 1 (OC1N output) /
Kojto	115:87f2f5183dfb	7227	#define TIM_CR2_OIS2 ((uint32_t)0x0400) /!<Output Idle state 2 (OC2 output) /
Kojto	115:87f2f5183dfb	7228	#define TIM_CR2_OIS2N ((uint32_t)0x0800) /!<Output Idle state 2 (OC2N output) /
Kojto	115:87f2f5183dfb	7229	#define TIM_CR2_OIS3 ((uint32_t)0x1000) /!<Output Idle state 3 (OC3 output) /
Kojto	115:87f2f5183dfb	7230	#define TIM_CR2_OIS3N ((uint32_t)0x2000) /!<Output Idle state 3 (OC3N output) /
Kojto	115:87f2f5183dfb	7231	#define TIM_CR2_OIS4 ((uint32_t)0x4000) /!<Output Idle state 4 (OC4 output) /
Kojto	115:87f2f5183dfb	7232
Kojto	115:87f2f5183dfb	7233	/***************** Bit definition for TIM_SMCR register *****************/
Kojto	115:87f2f5183dfb	7234	#define TIM_SMCR_SMS ((uint32_t)0x00010007) /!<SMS[2:0] bits (Slave mode selection) /
Kojto	115:87f2f5183dfb	7235	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7236	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7237	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7238	#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7239	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
Kojto	115:87f2f5183dfb	7240
Kojto	115:87f2f5183dfb	7241	#define TIM_SMCR_TS ((uint32_t)0x0070) /!<TS[2:0] bits (Trigger selection) /
Kojto	115:87f2f5183dfb	7242	#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7243	#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7244	#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7245
Kojto	115:87f2f5183dfb	7246	#define TIM_SMCR_MSM ((uint32_t)0x0080) /!<Master/slave mode /
Kojto	115:87f2f5183dfb	7247
Kojto	115:87f2f5183dfb	7248	#define TIM_SMCR_ETF ((uint32_t)0x0F00) /!<ETF[3:0] bits (External trigger filter) /
Kojto	115:87f2f5183dfb	7249	#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7250	#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7251	#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7252	#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7253
Kojto	115:87f2f5183dfb	7254	#define TIM_SMCR_ETPS ((uint32_t)0x3000) /!<ETPS[1:0] bits (External trigger prescaler) /
Kojto	115:87f2f5183dfb	7255	#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7256	#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7257
Kojto	115:87f2f5183dfb	7258
Kojto	115:87f2f5183dfb	7259	#define TIM_SMCR_ECE ((uint32_t)0x4000) /!<External clock enable /
Kojto	115:87f2f5183dfb	7260	#define TIM_SMCR_ETP ((uint32_t)0x8000) /!<External trigger polarity /
Kojto	115:87f2f5183dfb	7261
Kojto	115:87f2f5183dfb	7262	/***************** Bit definition for TIM_DIER register *****************/
Kojto	115:87f2f5183dfb	7263	#define TIM_DIER_UIE ((uint32_t)0x0001) /!<Update interrupt enable /
Kojto	115:87f2f5183dfb	7264	#define TIM_DIER_CC1IE ((uint32_t)0x0002) /!<Capture/Compare 1 interrupt enable /
Kojto	115:87f2f5183dfb	7265	#define TIM_DIER_CC2IE ((uint32_t)0x0004) /!<Capture/Compare 2 interrupt enable /
Kojto	115:87f2f5183dfb	7266	#define TIM_DIER_CC3IE ((uint32_t)0x0008) /!<Capture/Compare 3 interrupt enable /
Kojto	115:87f2f5183dfb	7267	#define TIM_DIER_CC4IE ((uint32_t)0x0010) /!<Capture/Compare 4 interrupt enable /
Kojto	115:87f2f5183dfb	7268	#define TIM_DIER_COMIE ((uint32_t)0x0020) /!<COM interrupt enable /
Kojto	115:87f2f5183dfb	7269	#define TIM_DIER_TIE ((uint32_t)0x0040) /!<Trigger interrupt enable /
Kojto	115:87f2f5183dfb	7270	#define TIM_DIER_BIE ((uint32_t)0x0080) /!<Break interrupt enable /
Kojto	115:87f2f5183dfb	7271	#define TIM_DIER_UDE ((uint32_t)0x0100) /!<Update DMA request enable /
Kojto	115:87f2f5183dfb	7272	#define TIM_DIER_CC1DE ((uint32_t)0x0200) /!<Capture/Compare 1 DMA request enable /
Kojto	115:87f2f5183dfb	7273	#define TIM_DIER_CC2DE ((uint32_t)0x0400) /!<Capture/Compare 2 DMA request enable /
Kojto	115:87f2f5183dfb	7274	#define TIM_DIER_CC3DE ((uint32_t)0x0800) /!<Capture/Compare 3 DMA request enable /
Kojto	115:87f2f5183dfb	7275	#define TIM_DIER_CC4DE ((uint32_t)0x1000) /!<Capture/Compare 4 DMA request enable /
Kojto	115:87f2f5183dfb	7276	#define TIM_DIER_COMDE ((uint32_t)0x2000) /!<COM DMA request enable /
Kojto	115:87f2f5183dfb	7277	#define TIM_DIER_TDE ((uint32_t)0x4000) /!<Trigger DMA request enable /
Kojto	115:87f2f5183dfb	7278
Kojto	115:87f2f5183dfb	7279	/****************** Bit definition for TIM_SR register ******************/
Kojto	115:87f2f5183dfb	7280	#define TIM_SR_UIF ((uint32_t)0x0001) /!<Update interrupt Flag /
Kojto	115:87f2f5183dfb	7281	#define TIM_SR_CC1IF ((uint32_t)0x0002) /!<Capture/Compare 1 interrupt Flag /
Kojto	115:87f2f5183dfb	7282	#define TIM_SR_CC2IF ((uint32_t)0x0004) /!<Capture/Compare 2 interrupt Flag /
Kojto	115:87f2f5183dfb	7283	#define TIM_SR_CC3IF ((uint32_t)0x0008) /!<Capture/Compare 3 interrupt Flag /
Kojto	115:87f2f5183dfb	7284	#define TIM_SR_CC4IF ((uint32_t)0x0010) /!<Capture/Compare 4 interrupt Flag /
Kojto	115:87f2f5183dfb	7285	#define TIM_SR_COMIF ((uint32_t)0x0020) /!<COM interrupt Flag /
Kojto	115:87f2f5183dfb	7286	#define TIM_SR_TIF ((uint32_t)0x0040) /!<Trigger interrupt Flag /
Kojto	115:87f2f5183dfb	7287	#define TIM_SR_BIF ((uint32_t)0x0080) /!<Break interrupt Flag /
Kojto	115:87f2f5183dfb	7288	#define TIM_SR_B2IF ((uint32_t)0x0100) /!<Break2 interrupt Flag /
Kojto	115:87f2f5183dfb	7289	#define TIM_SR_CC1OF ((uint32_t)0x0200) /!<Capture/Compare 1 Overcapture Flag /
Kojto	115:87f2f5183dfb	7290	#define TIM_SR_CC2OF ((uint32_t)0x0400) /!<Capture/Compare 2 Overcapture Flag /
Kojto	115:87f2f5183dfb	7291	#define TIM_SR_CC3OF ((uint32_t)0x0800) /!<Capture/Compare 3 Overcapture Flag /
Kojto	115:87f2f5183dfb	7292	#define TIM_SR_CC4OF ((uint32_t)0x1000) /!<Capture/Compare 4 Overcapture Flag /
Kojto	115:87f2f5183dfb	7293
Kojto	115:87f2f5183dfb	7294	/***************** Bit definition for TIM_EGR register ******************/
Kojto	115:87f2f5183dfb	7295	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
Kojto	115:87f2f5183dfb	7296	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
Kojto	115:87f2f5183dfb	7297	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
Kojto	115:87f2f5183dfb	7298	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
Kojto	115:87f2f5183dfb	7299	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
Kojto	115:87f2f5183dfb	7300	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
Kojto	115:87f2f5183dfb	7301	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
Kojto	115:87f2f5183dfb	7302	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
Kojto	115:87f2f5183dfb	7303	#define TIM_EGR_B2G ((uint32_t)0x00000100) /!<Break2 Generation /
Kojto	115:87f2f5183dfb	7304
Kojto	115:87f2f5183dfb	7305	/**************** Bit definition for TIM_CCMR1 register *****************/
Kojto	115:87f2f5183dfb	7306	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
Kojto	115:87f2f5183dfb	7307	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7308	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7309
Kojto	115:87f2f5183dfb	7310	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
Kojto	115:87f2f5183dfb	7311	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
Kojto	115:87f2f5183dfb	7312
Kojto	115:87f2f5183dfb	7313	#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
Kojto	115:87f2f5183dfb	7314	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7315	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7316	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7317	#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7318
Kojto	115:87f2f5183dfb	7319	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
Kojto	115:87f2f5183dfb	7320
Kojto	115:87f2f5183dfb	7321	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
Kojto	115:87f2f5183dfb	7322	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7323	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7324
Kojto	115:87f2f5183dfb	7325	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
Kojto	115:87f2f5183dfb	7326	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
Kojto	115:87f2f5183dfb	7327
Kojto	115:87f2f5183dfb	7328	#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
Kojto	115:87f2f5183dfb	7329	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7330	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7331	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7332	#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7333
Kojto	115:87f2f5183dfb	7334	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
Kojto	115:87f2f5183dfb	7335
Kojto	115:87f2f5183dfb	7336	/----------------------------------------------------------------------------/
Kojto	115:87f2f5183dfb	7337
Kojto	115:87f2f5183dfb	7338	#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
Kojto	115:87f2f5183dfb	7339	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7340	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7341
Kojto	115:87f2f5183dfb	7342	#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
Kojto	115:87f2f5183dfb	7343	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7344	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7345	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7346	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7347
Kojto	115:87f2f5183dfb	7348	#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
Kojto	115:87f2f5183dfb	7349	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7350	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7351
Kojto	115:87f2f5183dfb	7352	#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
Kojto	115:87f2f5183dfb	7353	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7354	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7355	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7356	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7357
Kojto	115:87f2f5183dfb	7358	/**************** Bit definition for TIM_CCMR2 register *****************/
Kojto	115:87f2f5183dfb	7359	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
Kojto	115:87f2f5183dfb	7360	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7361	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7362
Kojto	115:87f2f5183dfb	7363	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
Kojto	115:87f2f5183dfb	7364	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
Kojto	115:87f2f5183dfb	7365
Kojto	115:87f2f5183dfb	7366	#define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
Kojto	115:87f2f5183dfb	7367	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7368	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7369	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7370	#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7371
Kojto	115:87f2f5183dfb	7372
Kojto	115:87f2f5183dfb	7373
Kojto	115:87f2f5183dfb	7374	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
Kojto	115:87f2f5183dfb	7375
Kojto	115:87f2f5183dfb	7376	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
Kojto	115:87f2f5183dfb	7377	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7378	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7379
Kojto	115:87f2f5183dfb	7380	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
Kojto	115:87f2f5183dfb	7381	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
Kojto	115:87f2f5183dfb	7382
Kojto	115:87f2f5183dfb	7383	#define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
Kojto	115:87f2f5183dfb	7384	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7385	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7386	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7387	#define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7388
Kojto	115:87f2f5183dfb	7389	#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /!<Output Compare 4 Clear Enable /
Kojto	115:87f2f5183dfb	7390
Kojto	115:87f2f5183dfb	7391	/----------------------------------------------------------------------------/
Kojto	115:87f2f5183dfb	7392
Kojto	115:87f2f5183dfb	7393	#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
Kojto	115:87f2f5183dfb	7394	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7395	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7396
Kojto	115:87f2f5183dfb	7397	#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
Kojto	115:87f2f5183dfb	7398	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7399	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7400	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7401	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7402
Kojto	115:87f2f5183dfb	7403	#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
Kojto	115:87f2f5183dfb	7404	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7405	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7406
Kojto	115:87f2f5183dfb	7407	#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
Kojto	115:87f2f5183dfb	7408	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7409	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7410	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7411	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7412
Kojto	115:87f2f5183dfb	7413	/***************** Bit definition for TIM_CCER register *****************/
Kojto	115:87f2f5183dfb	7414	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
Kojto	115:87f2f5183dfb	7415	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
Kojto	115:87f2f5183dfb	7416	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
Kojto	115:87f2f5183dfb	7417	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
Kojto	115:87f2f5183dfb	7418	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
Kojto	115:87f2f5183dfb	7419	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
Kojto	115:87f2f5183dfb	7420	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
Kojto	115:87f2f5183dfb	7421	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
Kojto	115:87f2f5183dfb	7422	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
Kojto	115:87f2f5183dfb	7423	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
Kojto	115:87f2f5183dfb	7424	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
Kojto	115:87f2f5183dfb	7425	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
Kojto	115:87f2f5183dfb	7426	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
Kojto	115:87f2f5183dfb	7427	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
Kojto	115:87f2f5183dfb	7428	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
Kojto	115:87f2f5183dfb	7429	#define TIM_CCER_CC5E ((uint32_t)0x00010000) /!<Capture/Compare 5 output enable /
Kojto	115:87f2f5183dfb	7430	#define TIM_CCER_CC5P ((uint32_t)0x00020000) /!<Capture/Compare 5 output Polarity /
Kojto	115:87f2f5183dfb	7431	#define TIM_CCER_CC6E ((uint32_t)0x00100000) /!<Capture/Compare 6 output enable /
Kojto	115:87f2f5183dfb	7432	#define TIM_CCER_CC6P ((uint32_t)0x00200000) /!<Capture/Compare 6 output Polarity /
Kojto	115:87f2f5183dfb	7433
Kojto	115:87f2f5183dfb	7434
Kojto	115:87f2f5183dfb	7435	/***************** Bit definition for TIM_CNT register ******************/
Kojto	115:87f2f5183dfb	7436	#define TIM_CNT_CNT ((uint32_t)0xFFFF) /!<Counter Value /
Kojto	115:87f2f5183dfb	7437
Kojto	115:87f2f5183dfb	7438	/***************** Bit definition for TIM_PSC register ******************/
Kojto	115:87f2f5183dfb	7439	#define TIM_PSC_PSC ((uint32_t)0xFFFF) /!<Prescaler Value /
Kojto	115:87f2f5183dfb	7440
Kojto	115:87f2f5183dfb	7441	/***************** Bit definition for TIM_ARR register ******************/
Kojto	115:87f2f5183dfb	7442	#define TIM_ARR_ARR ((uint32_t)0xFFFF) /!<actual auto-reload Value /
Kojto	115:87f2f5183dfb	7443
Kojto	115:87f2f5183dfb	7444	/***************** Bit definition for TIM_RCR register ******************/
Kojto	115:87f2f5183dfb	7445	#define TIM_RCR_REP ((uint8_t)0xFF) /!<Repetition Counter Value /
Kojto	115:87f2f5183dfb	7446
Kojto	115:87f2f5183dfb	7447	/***************** Bit definition for TIM_CCR1 register *****************/
Kojto	115:87f2f5183dfb	7448	#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /!<Capture/Compare 1 Value /
Kojto	115:87f2f5183dfb	7449
Kojto	115:87f2f5183dfb	7450	/***************** Bit definition for TIM_CCR2 register *****************/
Kojto	115:87f2f5183dfb	7451	#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /!<Capture/Compare 2 Value /
Kojto	115:87f2f5183dfb	7452
Kojto	115:87f2f5183dfb	7453	/***************** Bit definition for TIM_CCR3 register *****************/
Kojto	115:87f2f5183dfb	7454	#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /!<Capture/Compare 3 Value /
Kojto	115:87f2f5183dfb	7455
Kojto	115:87f2f5183dfb	7456	/***************** Bit definition for TIM_CCR4 register *****************/
Kojto	115:87f2f5183dfb	7457	#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /!<Capture/Compare 4 Value /
Kojto	115:87f2f5183dfb	7458
Kojto	115:87f2f5183dfb	7459	/***************** Bit definition for TIM_BDTR register *****************/
Kojto	115:87f2f5183dfb	7460	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
Kojto	115:87f2f5183dfb	7461	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7462	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7463	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7464	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7465	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	7466	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
Kojto	115:87f2f5183dfb	7467	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
Kojto	115:87f2f5183dfb	7468	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
Kojto	115:87f2f5183dfb	7469
Kojto	115:87f2f5183dfb	7470	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
Kojto	115:87f2f5183dfb	7471	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7472	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7473
Kojto	115:87f2f5183dfb	7474	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
Kojto	115:87f2f5183dfb	7475	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
Kojto	115:87f2f5183dfb	7476	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
Kojto	115:87f2f5183dfb	7477	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
Kojto	115:87f2f5183dfb	7478	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
Kojto	115:87f2f5183dfb	7479	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
Kojto	115:87f2f5183dfb	7480	#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /!<Break Filter for Break1 /
Kojto	115:87f2f5183dfb	7481	#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /!<Break Filter for Break2 /
Kojto	115:87f2f5183dfb	7482	#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /!<Break enable for Break2 /
Kojto	115:87f2f5183dfb	7483	#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /!<Break Polarity for Break2 /
Kojto	115:87f2f5183dfb	7484
Kojto	115:87f2f5183dfb	7485	/***************** Bit definition for TIM_DCR register ******************/
Kojto	115:87f2f5183dfb	7486	#define TIM_DCR_DBA ((uint32_t)0x001F) /!<DBA[4:0] bits (DMA Base Address) /
Kojto	115:87f2f5183dfb	7487	#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7488	#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7489	#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7490	#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7491	#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	7492
Kojto	115:87f2f5183dfb	7493	#define TIM_DCR_DBL ((uint32_t)0x1F00) /!<DBL[4:0] bits (DMA Burst Length) /
Kojto	115:87f2f5183dfb	7494	#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7495	#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7496	#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7497	#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7498	#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	7499
Kojto	115:87f2f5183dfb	7500	/***************** Bit definition for TIM_DMAR register *****************/
Kojto	115:87f2f5183dfb	7501	#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /!<DMA register for burst accesses /
Kojto	115:87f2f5183dfb	7502
Kojto	115:87f2f5183dfb	7503	/***************** Bit definition for TIM_OR register *******************/
Kojto	115:87f2f5183dfb	7504	#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) /
Kojto	115:87f2f5183dfb	7505	#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7506	#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7507	#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) /
Kojto	115:87f2f5183dfb	7508	#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7509	#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7510
Kojto	115:87f2f5183dfb	7511	/**************** Bit definition for TIM_CCMR3 register *****************/
Kojto	115:87f2f5183dfb	7512	#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /!<Output Compare 5 Fast enable /
Kojto	115:87f2f5183dfb	7513	#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /!<Output Compare 5 Preload enable /
Kojto	115:87f2f5183dfb	7514
Kojto	115:87f2f5183dfb	7515	#define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /!<OC5M[2:0] bits (Output Compare 5 Mode) /
Kojto	115:87f2f5183dfb	7516	#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7517	#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7518	#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7519	#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7520
Kojto	115:87f2f5183dfb	7521	#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /!<Output Compare 5 Clear Enable /
Kojto	115:87f2f5183dfb	7522
Kojto	115:87f2f5183dfb	7523	#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
Kojto	115:87f2f5183dfb	7524	#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
Kojto	115:87f2f5183dfb	7525
Kojto	115:87f2f5183dfb	7526	#define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
Kojto	115:87f2f5183dfb	7527	#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7528	#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7529	#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7530	#define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7531
Kojto	115:87f2f5183dfb	7532	#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
Kojto	115:87f2f5183dfb	7533
Kojto	115:87f2f5183dfb	7534	/***************** Bit definition for TIM_CCR5 register *****************/
Kojto	115:87f2f5183dfb	7535	#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /!<Capture/Compare 5 Value /
Kojto	115:87f2f5183dfb	7536	#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /!<Group Channel 5 and Channel 1 /
Kojto	115:87f2f5183dfb	7537	#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /!<Group Channel 5 and Channel 2 /
Kojto	115:87f2f5183dfb	7538	#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /!<Group Channel 5 and Channel 3 /
Kojto	115:87f2f5183dfb	7539
Kojto	115:87f2f5183dfb	7540	/***************** Bit definition for TIM_CCR6 register *****************/
Kojto	115:87f2f5183dfb	7541	#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /!<Capture/Compare 6 Value /
Kojto	115:87f2f5183dfb	7542
Kojto	115:87f2f5183dfb	7543	/******************************************************************************/
Kojto	115:87f2f5183dfb	7544	/* */
Kojto	115:87f2f5183dfb	7545	/* Low Power Timer (LPTIM) */
Kojto	115:87f2f5183dfb	7546	/* */
Kojto	115:87f2f5183dfb	7547	/******************************************************************************/
Kojto	115:87f2f5183dfb	7548	/**************** Bit definition for LPTIM_ISR register *****************/
Kojto	115:87f2f5183dfb	7549	#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /!< Compare match /
Kojto	115:87f2f5183dfb	7550	#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /!< Autoreload match /
Kojto	115:87f2f5183dfb	7551	#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /!< External trigger edge event /
Kojto	115:87f2f5183dfb	7552	#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /!< Compare register update OK /
Kojto	115:87f2f5183dfb	7553	#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /!< Autoreload register update OK /
Kojto	115:87f2f5183dfb	7554	#define LPTIM_ISR_UP ((uint32_t)0x00000020) /!< Counter direction change down to up /
Kojto	115:87f2f5183dfb	7555	#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /!< Counter direction change up to down /
Kojto	115:87f2f5183dfb	7556
Kojto	115:87f2f5183dfb	7557	/**************** Bit definition for LPTIM_ICR register *****************/
Kojto	115:87f2f5183dfb	7558	#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /!< Compare match Clear Flag /
Kojto	115:87f2f5183dfb	7559	#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /!< Autoreload match Clear Flag /
Kojto	115:87f2f5183dfb	7560	#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /!< External trigger edge event Clear Flag /
Kojto	115:87f2f5183dfb	7561	#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /!< Compare register update OK Clear Flag /
Kojto	115:87f2f5183dfb	7562	#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /!< Autoreload register update OK Clear Flag /
Kojto	115:87f2f5183dfb	7563	#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /!< Counter direction change down to up Clear Flag /
Kojto	115:87f2f5183dfb	7564	#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /!< Counter direction change up to down Clear Flag /
Kojto	115:87f2f5183dfb	7565
Kojto	115:87f2f5183dfb	7566	/**************** Bit definition for LPTIM_IER register ******************/
Kojto	115:87f2f5183dfb	7567	#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /!< Compare match Interrupt Enable /
Kojto	115:87f2f5183dfb	7568	#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /!< Autoreload match Interrupt Enable /
Kojto	115:87f2f5183dfb	7569	#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /!< External trigger edge event Interrupt Enable /
Kojto	115:87f2f5183dfb	7570	#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /!< Compare register update OK Interrupt Enable /
Kojto	115:87f2f5183dfb	7571	#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /!< Autoreload register update OK Interrupt Enable /
Kojto	115:87f2f5183dfb	7572	#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /!< Counter direction change down to up Interrupt Enable /
Kojto	115:87f2f5183dfb	7573	#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /!< Counter direction change up to down Interrupt Enable /
Kojto	115:87f2f5183dfb	7574
Kojto	115:87f2f5183dfb	7575	/**************** Bit definition for LPTIM_CFGR register *****************/
Kojto	115:87f2f5183dfb	7576	#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /!< Clock selector /
Kojto	115:87f2f5183dfb	7577
Kojto	115:87f2f5183dfb	7578	#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /!< CKPOL[1:0] bits (Clock polarity) /
Kojto	115:87f2f5183dfb	7579	#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /!< Bit 0 /
Kojto	115:87f2f5183dfb	7580	#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /!< Bit 1 /
Kojto	115:87f2f5183dfb	7581
Kojto	115:87f2f5183dfb	7582	#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /!< CKFLT[1:0] bits (Configurable digital filter for external clock) /
Kojto	115:87f2f5183dfb	7583	#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /!< Bit 0 /
Kojto	115:87f2f5183dfb	7584	#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /!< Bit 1 /
Kojto	115:87f2f5183dfb	7585
Kojto	115:87f2f5183dfb	7586	#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /!< TRGFLT[1:0] bits (Configurable digital filter for trigger) /
Kojto	115:87f2f5183dfb	7587	#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /!< Bit 0 /
Kojto	115:87f2f5183dfb	7588	#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /!< Bit 1 /
Kojto	115:87f2f5183dfb	7589
Kojto	115:87f2f5183dfb	7590	#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /!< PRESC[2:0] bits (Clock prescaler) /
Kojto	115:87f2f5183dfb	7591	#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /!< Bit 0 /
Kojto	115:87f2f5183dfb	7592	#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /!< Bit 1 /
Kojto	115:87f2f5183dfb	7593	#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /!< Bit 2 /
Kojto	115:87f2f5183dfb	7594
Kojto	115:87f2f5183dfb	7595	#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /!< TRIGSEL[2:0]] bits (Trigger selector) /
Kojto	115:87f2f5183dfb	7596	#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	7597	#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	7598	#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /!< Bit 2 /
Kojto	115:87f2f5183dfb	7599
Kojto	115:87f2f5183dfb	7600	#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /!< TRIGEN[1:0] bits (Trigger enable and polarity) /
Kojto	115:87f2f5183dfb	7601	#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	7602	#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	7603
Kojto	115:87f2f5183dfb	7604	#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /!< Timout enable /
Kojto	115:87f2f5183dfb	7605	#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /!< Waveform shape /
Kojto	115:87f2f5183dfb	7606	#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /!< Waveform shape polarity /
Kojto	115:87f2f5183dfb	7607	#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /!< Reg update mode /
Kojto	115:87f2f5183dfb	7608	#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /!< Counter mode enable /
Kojto	115:87f2f5183dfb	7609	#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /!< Encoder mode enable /
Kojto	115:87f2f5183dfb	7610
Kojto	115:87f2f5183dfb	7611	/**************** Bit definition for LPTIM_CR register ******************/
Kojto	115:87f2f5183dfb	7612	#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /!< LPTIMer enable /
Kojto	115:87f2f5183dfb	7613	#define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /!< Timer start in single mode /
Kojto	115:87f2f5183dfb	7614	#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /!< Timer start in continuous mode /
Kojto	115:87f2f5183dfb	7615
Kojto	115:87f2f5183dfb	7616	/**************** Bit definition for LPTIM_CMP register *****************/
Kojto	115:87f2f5183dfb	7617	#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /!< Compare register /
Kojto	115:87f2f5183dfb	7618
Kojto	115:87f2f5183dfb	7619	/**************** Bit definition for LPTIM_ARR register *****************/
Kojto	115:87f2f5183dfb	7620	#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /!< Auto reload register /
Kojto	115:87f2f5183dfb	7621
Kojto	115:87f2f5183dfb	7622	/**************** Bit definition for LPTIM_CNT register *****************/
Kojto	115:87f2f5183dfb	7623	#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /!< Counter register /
Kojto	115:87f2f5183dfb	7624	/******************************************************************************/
Kojto	115:87f2f5183dfb	7625	/* */
Kojto	115:87f2f5183dfb	7626	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto	115:87f2f5183dfb	7627	/* */
Kojto	115:87f2f5183dfb	7628	/******************************************************************************/
Kojto	115:87f2f5183dfb	7629	/**************** Bit definition for USART_CR1 register *****************/
Kojto	115:87f2f5183dfb	7630	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
Kojto	115:87f2f5183dfb	7631	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
Kojto	115:87f2f5183dfb	7632	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
Kojto	115:87f2f5183dfb	7633	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
Kojto	115:87f2f5183dfb	7634	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
Kojto	115:87f2f5183dfb	7635	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
Kojto	115:87f2f5183dfb	7636	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
Kojto	115:87f2f5183dfb	7637	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
Kojto	115:87f2f5183dfb	7638	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
Kojto	115:87f2f5183dfb	7639	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
Kojto	115:87f2f5183dfb	7640	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
Kojto	115:87f2f5183dfb	7641	#define USART_CR1_M ((uint32_t)0x10001000) /!< Word length /
Kojto	115:87f2f5183dfb	7642	#define USART_CR1_M_0 ((uint32_t)0x00001000) /!< Word length - Bit 0 /
Kojto	115:87f2f5183dfb	7643	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
Kojto	115:87f2f5183dfb	7644	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
Kojto	115:87f2f5183dfb	7645	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
Kojto	115:87f2f5183dfb	7646	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
Kojto	115:87f2f5183dfb	7647	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	7648	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	7649	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
Kojto	115:87f2f5183dfb	7650	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
Kojto	115:87f2f5183dfb	7651	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
Kojto	115:87f2f5183dfb	7652	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
Kojto	115:87f2f5183dfb	7653	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	7654	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	7655	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
Kojto	115:87f2f5183dfb	7656	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
Kojto	115:87f2f5183dfb	7657	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
Kojto	115:87f2f5183dfb	7658	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
Kojto	115:87f2f5183dfb	7659	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
Kojto	115:87f2f5183dfb	7660	#define USART_CR1_M_1 ((uint32_t)0x10000000) /!< Word length - Bit 1 /
Kojto	115:87f2f5183dfb	7661
Kojto	115:87f2f5183dfb	7662	/**************** Bit definition for USART_CR2 register *****************/
Kojto	115:87f2f5183dfb	7663	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
Kojto	115:87f2f5183dfb	7664	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
Kojto	115:87f2f5183dfb	7665	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
Kojto	115:87f2f5183dfb	7666	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
Kojto	115:87f2f5183dfb	7667	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
Kojto	115:87f2f5183dfb	7668	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
Kojto	115:87f2f5183dfb	7669	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
Kojto	115:87f2f5183dfb	7670	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
Kojto	115:87f2f5183dfb	7671	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	7672	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	7673	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
Kojto	115:87f2f5183dfb	7674	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
Kojto	115:87f2f5183dfb	7675	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
Kojto	115:87f2f5183dfb	7676	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
Kojto	115:87f2f5183dfb	7677	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
Kojto	115:87f2f5183dfb	7678	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
Kojto	115:87f2f5183dfb	7679	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable /
Kojto	115:87f2f5183dfb	7680	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
Kojto	115:87f2f5183dfb	7681	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	7682	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	7683	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
Kojto	115:87f2f5183dfb	7684	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
Kojto	115:87f2f5183dfb	7685
Kojto	115:87f2f5183dfb	7686	/**************** Bit definition for USART_CR3 register *****************/
Kojto	115:87f2f5183dfb	7687	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
Kojto	115:87f2f5183dfb	7688	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
Kojto	115:87f2f5183dfb	7689	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
Kojto	115:87f2f5183dfb	7690	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
Kojto	115:87f2f5183dfb	7691	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
Kojto	115:87f2f5183dfb	7692	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
Kojto	115:87f2f5183dfb	7693	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
Kojto	115:87f2f5183dfb	7694	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
Kojto	115:87f2f5183dfb	7695	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
Kojto	115:87f2f5183dfb	7696	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
Kojto	115:87f2f5183dfb	7697	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
Kojto	115:87f2f5183dfb	7698	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
Kojto	115:87f2f5183dfb	7699	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
Kojto	115:87f2f5183dfb	7700	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
Kojto	115:87f2f5183dfb	7701	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
Kojto	115:87f2f5183dfb	7702	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
Kojto	115:87f2f5183dfb	7703	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
Kojto	115:87f2f5183dfb	7704	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
Kojto	115:87f2f5183dfb	7705	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
Kojto	115:87f2f5183dfb	7706	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
Kojto	115:87f2f5183dfb	7707
Kojto	115:87f2f5183dfb	7708	/**************** Bit definition for USART_BRR register *****************/
Kojto	115:87f2f5183dfb	7709	#define USART_BRR_DIV_FRACTION ((uint32_t)0x000F) /!< Fraction of USARTDIV /
Kojto	115:87f2f5183dfb	7710	#define USART_BRR_DIV_MANTISSA ((uint32_t)0xFFF0) /!< Mantissa of USARTDIV /
Kojto	115:87f2f5183dfb	7711
Kojto	115:87f2f5183dfb	7712	/**************** Bit definition for USART_GTPR register ****************/
Kojto	115:87f2f5183dfb	7713	#define USART_GTPR_PSC ((uint32_t)0x00FF) /!< PSC[7:0] bits (Prescaler value) /
Kojto	115:87f2f5183dfb	7714	#define USART_GTPR_GT ((uint32_t)0xFF00) /!< GT[7:0] bits (Guard time value) /
Kojto	115:87f2f5183dfb	7715
Kojto	115:87f2f5183dfb	7716
Kojto	115:87f2f5183dfb	7717	/***************** Bit definition for USART_RTOR register ***************/
Kojto	115:87f2f5183dfb	7718	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
Kojto	115:87f2f5183dfb	7719	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
Kojto	115:87f2f5183dfb	7720
Kojto	115:87f2f5183dfb	7721	/***************** Bit definition for USART_RQR register ****************/
Kojto	115:87f2f5183dfb	7722	#define USART_RQR_ABRRQ ((uint32_t)0x0001) /!< Auto-Baud Rate Request /
Kojto	115:87f2f5183dfb	7723	#define USART_RQR_SBKRQ ((uint32_t)0x0002) /!< Send Break Request /
Kojto	115:87f2f5183dfb	7724	#define USART_RQR_MMRQ ((uint32_t)0x0004) /!< Mute Mode Request /
Kojto	115:87f2f5183dfb	7725	#define USART_RQR_RXFRQ ((uint32_t)0x0008) /!< Receive Data flush Request /
Kojto	115:87f2f5183dfb	7726	#define USART_RQR_TXFRQ ((uint32_t)0x0010) /!< Transmit data flush Request /
Kojto	115:87f2f5183dfb	7727
Kojto	115:87f2f5183dfb	7728	/***************** Bit definition for USART_ISR register ****************/
Kojto	115:87f2f5183dfb	7729	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
Kojto	115:87f2f5183dfb	7730	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
Kojto	115:87f2f5183dfb	7731	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
Kojto	115:87f2f5183dfb	7732	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
Kojto	115:87f2f5183dfb	7733	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
Kojto	115:87f2f5183dfb	7734	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
Kojto	115:87f2f5183dfb	7735	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
Kojto	115:87f2f5183dfb	7736	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
Kojto	115:87f2f5183dfb	7737	#define USART_ISR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
Kojto	115:87f2f5183dfb	7738	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
Kojto	115:87f2f5183dfb	7739	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
Kojto	115:87f2f5183dfb	7740	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
Kojto	115:87f2f5183dfb	7741	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
Kojto	115:87f2f5183dfb	7742	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
Kojto	115:87f2f5183dfb	7743	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
Kojto	115:87f2f5183dfb	7744	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
Kojto	115:87f2f5183dfb	7745	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
Kojto	115:87f2f5183dfb	7746	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
Kojto	115:87f2f5183dfb	7747	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
Kojto	115:87f2f5183dfb	7748	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
Kojto	115:87f2f5183dfb	7749	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
Kojto	115:87f2f5183dfb	7750	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
Kojto	115:87f2f5183dfb	7751
Kojto	115:87f2f5183dfb	7752	/***************** Bit definition for USART_ICR register ****************/
Kojto	115:87f2f5183dfb	7753	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
Kojto	115:87f2f5183dfb	7754	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
Kojto	115:87f2f5183dfb	7755	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
Kojto	115:87f2f5183dfb	7756	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
Kojto	115:87f2f5183dfb	7757	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
Kojto	115:87f2f5183dfb	7758	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
Kojto	115:87f2f5183dfb	7759	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
Kojto	115:87f2f5183dfb	7760	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
Kojto	115:87f2f5183dfb	7761	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
Kojto	115:87f2f5183dfb	7762	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
Kojto	115:87f2f5183dfb	7763	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
Kojto	115:87f2f5183dfb	7764	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
Kojto	115:87f2f5183dfb	7765
Kojto	115:87f2f5183dfb	7766	/***************** Bit definition for USART_RDR register ****************/
Kojto	115:87f2f5183dfb	7767	#define USART_RDR_RDR ((uint32_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
Kojto	115:87f2f5183dfb	7768
Kojto	115:87f2f5183dfb	7769	/***************** Bit definition for USART_TDR register ****************/
Kojto	115:87f2f5183dfb	7770	#define USART_TDR_TDR ((uint32_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
Kojto	115:87f2f5183dfb	7771
Kojto	115:87f2f5183dfb	7772	/******************************************************************************/
Kojto	115:87f2f5183dfb	7773	/* */
Kojto	115:87f2f5183dfb	7774	/* Window WATCHDOG */
Kojto	115:87f2f5183dfb	7775	/* */
Kojto	115:87f2f5183dfb	7776	/******************************************************************************/
Kojto	115:87f2f5183dfb	7777	/***************** Bit definition for WWDG_CR register ******************/
Kojto	115:87f2f5183dfb	7778	#define WWDG_CR_T ((uint32_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
Kojto	115:87f2f5183dfb	7779	#define WWDG_CR_T0 ((uint32_t)0x01) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7780	#define WWDG_CR_T1 ((uint32_t)0x02) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7781	#define WWDG_CR_T2 ((uint32_t)0x04) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7782	#define WWDG_CR_T3 ((uint32_t)0x08) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7783	#define WWDG_CR_T4 ((uint32_t)0x10) /!<Bit 4 /
Kojto	115:87f2f5183dfb	7784	#define WWDG_CR_T5 ((uint32_t)0x20) /!<Bit 5 /
Kojto	115:87f2f5183dfb	7785	#define WWDG_CR_T6 ((uint32_t)0x40) /!<Bit 6 /
Kojto	115:87f2f5183dfb	7786
Kojto	115:87f2f5183dfb	7787	#define WWDG_CR_WDGA ((uint32_t)0x80) /!<Activation bit /
Kojto	115:87f2f5183dfb	7788
Kojto	115:87f2f5183dfb	7789	/***************** Bit definition for WWDG_CFR register *****************/
Kojto	115:87f2f5183dfb	7790	#define WWDG_CFR_W ((uint32_t)0x007F) /!<W[6:0] bits (7-bit window value) /
Kojto	115:87f2f5183dfb	7791	#define WWDG_CFR_W0 ((uint32_t)0x0001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7792	#define WWDG_CFR_W1 ((uint32_t)0x0002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7793	#define WWDG_CFR_W2 ((uint32_t)0x0004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	7794	#define WWDG_CFR_W3 ((uint32_t)0x0008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	7795	#define WWDG_CFR_W4 ((uint32_t)0x0010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	7796	#define WWDG_CFR_W5 ((uint32_t)0x0020) /!<Bit 5 /
Kojto	115:87f2f5183dfb	7797	#define WWDG_CFR_W6 ((uint32_t)0x0040) /!<Bit 6 /
Kojto	115:87f2f5183dfb	7798
Kojto	115:87f2f5183dfb	7799	#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
Kojto	115:87f2f5183dfb	7800	#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7801	#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7802
Kojto	115:87f2f5183dfb	7803	#define WWDG_CFR_EWI ((uint32_t)0x0200) /!<Early Wakeup Interrupt /
Kojto	115:87f2f5183dfb	7804
Kojto	115:87f2f5183dfb	7805	/***************** Bit definition for WWDG_SR register ******************/
Kojto	115:87f2f5183dfb	7806	#define WWDG_SR_EWIF ((uint32_t)0x01) /!<Early Wakeup Interrupt Flag /
Kojto	115:87f2f5183dfb	7807
Kojto	115:87f2f5183dfb	7808	/******************************************************************************/
Kojto	115:87f2f5183dfb	7809	/* */
Kojto	115:87f2f5183dfb	7810	/* DBG */
Kojto	115:87f2f5183dfb	7811	/* */
Kojto	115:87f2f5183dfb	7812	/******************************************************************************/
Kojto	115:87f2f5183dfb	7813	/****************** Bit definition for DBGMCU_IDCODE register ***********/
Kojto	115:87f2f5183dfb	7814	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
Kojto	115:87f2f5183dfb	7815	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
Kojto	115:87f2f5183dfb	7816
Kojto	115:87f2f5183dfb	7817	/****************** Bit definition for DBGMCU_CR register ***************/
Kojto	115:87f2f5183dfb	7818	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	7819	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	7820	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	7821	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	7822
Kojto	115:87f2f5183dfb	7823	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
Kojto	115:87f2f5183dfb	7824	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!<Bit 0 /
Kojto	115:87f2f5183dfb	7825	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!<Bit 1 /
Kojto	115:87f2f5183dfb	7826
Kojto	115:87f2f5183dfb	7827	/****************** Bit definition for DBGMCU_APB1_FZ register **********/
Kojto	115:87f2f5183dfb	7828	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	7829	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	7830	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
Kojto	115:87f2f5183dfb	7831	#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
Kojto	115:87f2f5183dfb	7832	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	7833	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	7834	#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	7835	#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	7836	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	7837	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	7838	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	7839	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	7840	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	7841	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	7842	#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	7843	#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	7844	#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
Kojto	115:87f2f5183dfb	7845
Kojto	115:87f2f5183dfb	7846	/****************** Bit definition for DBGMCU_APB2_FZ register **********/
Kojto	115:87f2f5183dfb	7847	#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	7848	#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	7849	#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	7850	#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	7851	#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	7852
Kojto	115:87f2f5183dfb	7853	/******************************************************************************/
Kojto	115:87f2f5183dfb	7854	/* */
Kojto	115:87f2f5183dfb	7855	/* Ethernet MAC Registers bits definitions */
Kojto	115:87f2f5183dfb	7856	/* */
Kojto	115:87f2f5183dfb	7857	/******************************************************************************/
Kojto	115:87f2f5183dfb	7858	/* Bit definition for Ethernet MAC Control Register register */
Kojto	115:87f2f5183dfb	7859	#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
Kojto	115:87f2f5183dfb	7860	#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
Kojto	115:87f2f5183dfb	7861	#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
Kojto	115:87f2f5183dfb	7862	#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
Kojto	115:87f2f5183dfb	7863	#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
Kojto	115:87f2f5183dfb	7864	#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
Kojto	115:87f2f5183dfb	7865	#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
Kojto	115:87f2f5183dfb	7866	#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
Kojto	115:87f2f5183dfb	7867	#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
Kojto	115:87f2f5183dfb	7868	#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
Kojto	115:87f2f5183dfb	7869	#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
Kojto	115:87f2f5183dfb	7870	#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
Kojto	115:87f2f5183dfb	7871	#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
Kojto	115:87f2f5183dfb	7872	#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
Kojto	115:87f2f5183dfb	7873	#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
Kojto	115:87f2f5183dfb	7874	#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
Kojto	115:87f2f5183dfb	7875	#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
Kojto	115:87f2f5183dfb	7876	#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
Kojto	115:87f2f5183dfb	7877	#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
Kojto	115:87f2f5183dfb	7878	#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
Kojto	115:87f2f5183dfb	7879	a transmission attempt during retries after a collision: 0 =< r <2^k */
Kojto	115:87f2f5183dfb	7880	#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
Kojto	115:87f2f5183dfb	7881	#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
Kojto	115:87f2f5183dfb	7882	#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
Kojto	115:87f2f5183dfb	7883	#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
Kojto	115:87f2f5183dfb	7884	#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
Kojto	115:87f2f5183dfb	7885	#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
Kojto	115:87f2f5183dfb	7886	#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
Kojto	115:87f2f5183dfb	7887
Kojto	115:87f2f5183dfb	7888	/* Bit definition for Ethernet MAC Frame Filter Register */
Kojto	115:87f2f5183dfb	7889	#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
Kojto	115:87f2f5183dfb	7890	#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
Kojto	115:87f2f5183dfb	7891	#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
Kojto	115:87f2f5183dfb	7892	#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
Kojto	115:87f2f5183dfb	7893	#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
Kojto	115:87f2f5183dfb	7894	#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
Kojto	115:87f2f5183dfb	7895	#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
Kojto	115:87f2f5183dfb	7896	#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
Kojto	115:87f2f5183dfb	7897	#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
Kojto	115:87f2f5183dfb	7898	#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
Kojto	115:87f2f5183dfb	7899	#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
Kojto	115:87f2f5183dfb	7900	#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
Kojto	115:87f2f5183dfb	7901	#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
Kojto	115:87f2f5183dfb	7902	#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
Kojto	115:87f2f5183dfb	7903
Kojto	115:87f2f5183dfb	7904	/* Bit definition for Ethernet MAC Hash Table High Register */
Kojto	115:87f2f5183dfb	7905	#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
Kojto	115:87f2f5183dfb	7906
Kojto	115:87f2f5183dfb	7907	/* Bit definition for Ethernet MAC Hash Table Low Register */
Kojto	115:87f2f5183dfb	7908	#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
Kojto	115:87f2f5183dfb	7909
Kojto	115:87f2f5183dfb	7910	/* Bit definition for Ethernet MAC MII Address Register */
Kojto	115:87f2f5183dfb	7911	#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
Kojto	115:87f2f5183dfb	7912	#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
Kojto	115:87f2f5183dfb	7913	#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
Kojto	115:87f2f5183dfb	7914	#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
Kojto	115:87f2f5183dfb	7915	#define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
Kojto	115:87f2f5183dfb	7916	#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
Kojto	115:87f2f5183dfb	7917	#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
Kojto	115:87f2f5183dfb	7918	#define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
Kojto	115:87f2f5183dfb	7919	#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
Kojto	115:87f2f5183dfb	7920	#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
Kojto	115:87f2f5183dfb	7921
Kojto	115:87f2f5183dfb	7922	/* Bit definition for Ethernet MAC MII Data Register */
Kojto	115:87f2f5183dfb	7923	#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
Kojto	115:87f2f5183dfb	7924
Kojto	115:87f2f5183dfb	7925	/* Bit definition for Ethernet MAC Flow Control Register */
Kojto	115:87f2f5183dfb	7926	#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
Kojto	115:87f2f5183dfb	7927	#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
Kojto	115:87f2f5183dfb	7928	#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
Kojto	115:87f2f5183dfb	7929	#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
Kojto	115:87f2f5183dfb	7930	#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
Kojto	115:87f2f5183dfb	7931	#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
Kojto	115:87f2f5183dfb	7932	#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
Kojto	115:87f2f5183dfb	7933	#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
Kojto	115:87f2f5183dfb	7934	#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
Kojto	115:87f2f5183dfb	7935	#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
Kojto	115:87f2f5183dfb	7936	#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
Kojto	115:87f2f5183dfb	7937
Kojto	115:87f2f5183dfb	7938	/* Bit definition for Ethernet MAC VLAN Tag Register */
Kojto	115:87f2f5183dfb	7939	#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
Kojto	115:87f2f5183dfb	7940	#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
Kojto	115:87f2f5183dfb	7941
Kojto	115:87f2f5183dfb	7942	/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
Kojto	115:87f2f5183dfb	7943	#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
Kojto	115:87f2f5183dfb	7944	/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
Kojto	115:87f2f5183dfb	7945	Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
Kojto	115:87f2f5183dfb	7946	/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
Kojto	115:87f2f5183dfb	7947	Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
Kojto	115:87f2f5183dfb	7948	Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
Kojto	115:87f2f5183dfb	7949	Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
Kojto	115:87f2f5183dfb	7950	Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
Kojto	115:87f2f5183dfb	7951	RSVD - Filter1 Command - RSVD - Filter0 Command
Kojto	115:87f2f5183dfb	7952	Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
Kojto	115:87f2f5183dfb	7953	Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
Kojto	115:87f2f5183dfb	7954	Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
Kojto	115:87f2f5183dfb	7955
Kojto	115:87f2f5183dfb	7956	/* Bit definition for Ethernet MAC PMT Control and Status Register */
Kojto	115:87f2f5183dfb	7957	#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
Kojto	115:87f2f5183dfb	7958	#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
Kojto	115:87f2f5183dfb	7959	#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
Kojto	115:87f2f5183dfb	7960	#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
Kojto	115:87f2f5183dfb	7961	#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
Kojto	115:87f2f5183dfb	7962	#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
Kojto	115:87f2f5183dfb	7963	#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
Kojto	115:87f2f5183dfb	7964
Kojto	115:87f2f5183dfb	7965	/* Bit definition for Ethernet MAC Status Register */
Kojto	115:87f2f5183dfb	7966	#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
Kojto	115:87f2f5183dfb	7967	#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
Kojto	115:87f2f5183dfb	7968	#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
Kojto	115:87f2f5183dfb	7969	#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
Kojto	115:87f2f5183dfb	7970	#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
Kojto	115:87f2f5183dfb	7971
Kojto	115:87f2f5183dfb	7972	/* Bit definition for Ethernet MAC Interrupt Mask Register */
Kojto	115:87f2f5183dfb	7973	#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
Kojto	115:87f2f5183dfb	7974	#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
Kojto	115:87f2f5183dfb	7975
Kojto	115:87f2f5183dfb	7976	/* Bit definition for Ethernet MAC Address0 High Register */
Kojto	115:87f2f5183dfb	7977	#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
Kojto	115:87f2f5183dfb	7978
Kojto	115:87f2f5183dfb	7979	/* Bit definition for Ethernet MAC Address0 Low Register */
Kojto	115:87f2f5183dfb	7980	#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
Kojto	115:87f2f5183dfb	7981
Kojto	115:87f2f5183dfb	7982	/* Bit definition for Ethernet MAC Address1 High Register */
Kojto	115:87f2f5183dfb	7983	#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
Kojto	115:87f2f5183dfb	7984	#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
Kojto	115:87f2f5183dfb	7985	#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
Kojto	115:87f2f5183dfb	7986	#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
Kojto	115:87f2f5183dfb	7987	#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
Kojto	115:87f2f5183dfb	7988	#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
Kojto	115:87f2f5183dfb	7989	#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
Kojto	115:87f2f5183dfb	7990	#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
Kojto	115:87f2f5183dfb	7991	#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
Kojto	115:87f2f5183dfb	7992	#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
Kojto	115:87f2f5183dfb	7993
Kojto	115:87f2f5183dfb	7994	/* Bit definition for Ethernet MAC Address1 Low Register */
Kojto	115:87f2f5183dfb	7995	#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
Kojto	115:87f2f5183dfb	7996
Kojto	115:87f2f5183dfb	7997	/* Bit definition for Ethernet MAC Address2 High Register */
Kojto	115:87f2f5183dfb	7998	#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
Kojto	115:87f2f5183dfb	7999	#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
Kojto	115:87f2f5183dfb	8000	#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
Kojto	115:87f2f5183dfb	8001	#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
Kojto	115:87f2f5183dfb	8002	#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
Kojto	115:87f2f5183dfb	8003	#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
Kojto	115:87f2f5183dfb	8004	#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
Kojto	115:87f2f5183dfb	8005	#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
Kojto	115:87f2f5183dfb	8006	#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
Kojto	115:87f2f5183dfb	8007	#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
Kojto	115:87f2f5183dfb	8008
Kojto	115:87f2f5183dfb	8009	/* Bit definition for Ethernet MAC Address2 Low Register */
Kojto	115:87f2f5183dfb	8010	#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
Kojto	115:87f2f5183dfb	8011
Kojto	115:87f2f5183dfb	8012	/* Bit definition for Ethernet MAC Address3 High Register */
Kojto	115:87f2f5183dfb	8013	#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
Kojto	115:87f2f5183dfb	8014	#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
Kojto	115:87f2f5183dfb	8015	#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
Kojto	115:87f2f5183dfb	8016	#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
Kojto	115:87f2f5183dfb	8017	#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
Kojto	115:87f2f5183dfb	8018	#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
Kojto	115:87f2f5183dfb	8019	#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
Kojto	115:87f2f5183dfb	8020	#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
Kojto	115:87f2f5183dfb	8021	#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
Kojto	115:87f2f5183dfb	8022	#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
Kojto	115:87f2f5183dfb	8023
Kojto	115:87f2f5183dfb	8024	/* Bit definition for Ethernet MAC Address3 Low Register */
Kojto	115:87f2f5183dfb	8025	#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
Kojto	115:87f2f5183dfb	8026
Kojto	115:87f2f5183dfb	8027	/******************************************************************************/
Kojto	115:87f2f5183dfb	8028	/* Ethernet MMC Registers bits definition */
Kojto	115:87f2f5183dfb	8029	/******************************************************************************/
Kojto	115:87f2f5183dfb	8030
Kojto	115:87f2f5183dfb	8031	/* Bit definition for Ethernet MMC Contol Register */
Kojto	115:87f2f5183dfb	8032	#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
Kojto	115:87f2f5183dfb	8033	#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
Kojto	115:87f2f5183dfb	8034	#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
Kojto	115:87f2f5183dfb	8035	#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
Kojto	115:87f2f5183dfb	8036	#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
Kojto	115:87f2f5183dfb	8037	#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
Kojto	115:87f2f5183dfb	8038
Kojto	115:87f2f5183dfb	8039	/* Bit definition for Ethernet MMC Receive Interrupt Register */
Kojto	115:87f2f5183dfb	8040	#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
Kojto	115:87f2f5183dfb	8041	#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
Kojto	115:87f2f5183dfb	8042	#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
Kojto	115:87f2f5183dfb	8043
Kojto	115:87f2f5183dfb	8044	/* Bit definition for Ethernet MMC Transmit Interrupt Register */
Kojto	115:87f2f5183dfb	8045	#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
Kojto	115:87f2f5183dfb	8046	#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
Kojto	115:87f2f5183dfb	8047	#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
Kojto	115:87f2f5183dfb	8048
Kojto	115:87f2f5183dfb	8049	/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
Kojto	115:87f2f5183dfb	8050	#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
Kojto	115:87f2f5183dfb	8051	#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
Kojto	115:87f2f5183dfb	8052	#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
Kojto	115:87f2f5183dfb	8053
Kojto	115:87f2f5183dfb	8054	/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
Kojto	115:87f2f5183dfb	8055	#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
Kojto	115:87f2f5183dfb	8056	#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
Kojto	115:87f2f5183dfb	8057	#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
Kojto	115:87f2f5183dfb	8058
Kojto	115:87f2f5183dfb	8059	/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
Kojto	115:87f2f5183dfb	8060	#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
Kojto	115:87f2f5183dfb	8061
Kojto	115:87f2f5183dfb	8062	/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
Kojto	115:87f2f5183dfb	8063	#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
Kojto	115:87f2f5183dfb	8064
Kojto	115:87f2f5183dfb	8065	/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
Kojto	115:87f2f5183dfb	8066	#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
Kojto	115:87f2f5183dfb	8067
Kojto	115:87f2f5183dfb	8068	/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
Kojto	115:87f2f5183dfb	8069	#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
Kojto	115:87f2f5183dfb	8070
Kojto	115:87f2f5183dfb	8071	/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
Kojto	115:87f2f5183dfb	8072	#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
Kojto	115:87f2f5183dfb	8073
Kojto	115:87f2f5183dfb	8074	/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
Kojto	115:87f2f5183dfb	8075	#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
Kojto	115:87f2f5183dfb	8076
Kojto	115:87f2f5183dfb	8077	/******************************************************************************/
Kojto	115:87f2f5183dfb	8078	/* Ethernet PTP Registers bits definition */
Kojto	115:87f2f5183dfb	8079	/******************************************************************************/
Kojto	115:87f2f5183dfb	8080
Kojto	115:87f2f5183dfb	8081	/* Bit definition for Ethernet PTP Time Stamp Contol Register */
Kojto	115:87f2f5183dfb	8082	#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
Kojto	115:87f2f5183dfb	8083	#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
Kojto	115:87f2f5183dfb	8084	#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
Kojto	115:87f2f5183dfb	8085	#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
Kojto	115:87f2f5183dfb	8086	#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
Kojto	115:87f2f5183dfb	8087	#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
Kojto	115:87f2f5183dfb	8088	#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
Kojto	115:87f2f5183dfb	8089	#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
Kojto	115:87f2f5183dfb	8090	#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
Kojto	115:87f2f5183dfb	8091
Kojto	115:87f2f5183dfb	8092	#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
Kojto	115:87f2f5183dfb	8093	#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
Kojto	115:87f2f5183dfb	8094	#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
Kojto	115:87f2f5183dfb	8095	#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
Kojto	115:87f2f5183dfb	8096	#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
Kojto	115:87f2f5183dfb	8097	#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
Kojto	115:87f2f5183dfb	8098
Kojto	115:87f2f5183dfb	8099	/* Bit definition for Ethernet PTP Sub-Second Increment Register */
Kojto	115:87f2f5183dfb	8100	#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
Kojto	115:87f2f5183dfb	8101
Kojto	115:87f2f5183dfb	8102	/* Bit definition for Ethernet PTP Time Stamp High Register */
Kojto	115:87f2f5183dfb	8103	#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
Kojto	115:87f2f5183dfb	8104
Kojto	115:87f2f5183dfb	8105	/* Bit definition for Ethernet PTP Time Stamp Low Register */
Kojto	115:87f2f5183dfb	8106	#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
Kojto	115:87f2f5183dfb	8107	#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
Kojto	115:87f2f5183dfb	8108
Kojto	115:87f2f5183dfb	8109	/* Bit definition for Ethernet PTP Time Stamp High Update Register */
Kojto	115:87f2f5183dfb	8110	#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
Kojto	115:87f2f5183dfb	8111
Kojto	115:87f2f5183dfb	8112	/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
Kojto	115:87f2f5183dfb	8113	#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
Kojto	115:87f2f5183dfb	8114	#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
Kojto	115:87f2f5183dfb	8115
Kojto	115:87f2f5183dfb	8116	/* Bit definition for Ethernet PTP Time Stamp Addend Register */
Kojto	115:87f2f5183dfb	8117	#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
Kojto	115:87f2f5183dfb	8118
Kojto	115:87f2f5183dfb	8119	/* Bit definition for Ethernet PTP Target Time High Register */
Kojto	115:87f2f5183dfb	8120	#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
Kojto	115:87f2f5183dfb	8121
Kojto	115:87f2f5183dfb	8122	/* Bit definition for Ethernet PTP Target Time Low Register */
Kojto	115:87f2f5183dfb	8123	#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
Kojto	115:87f2f5183dfb	8124
Kojto	115:87f2f5183dfb	8125	/* Bit definition for Ethernet PTP Time Stamp Status Register */
Kojto	115:87f2f5183dfb	8126	#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
Kojto	115:87f2f5183dfb	8127	#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
Kojto	115:87f2f5183dfb	8128
Kojto	115:87f2f5183dfb	8129	/******************************************************************************/
Kojto	115:87f2f5183dfb	8130	/* Ethernet DMA Registers bits definition */
Kojto	115:87f2f5183dfb	8131	/******************************************************************************/
Kojto	115:87f2f5183dfb	8132
Kojto	115:87f2f5183dfb	8133	/* Bit definition for Ethernet DMA Bus Mode Register */
Kojto	115:87f2f5183dfb	8134	#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
Kojto	115:87f2f5183dfb	8135	#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
Kojto	115:87f2f5183dfb	8136	#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
Kojto	115:87f2f5183dfb	8137	#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
Kojto	115:87f2f5183dfb	8138	#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
Kojto	115:87f2f5183dfb	8139	#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
Kojto	115:87f2f5183dfb	8140	#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto	115:87f2f5183dfb	8141	#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto	115:87f2f5183dfb	8142	#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto	115:87f2f5183dfb	8143	#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto	115:87f2f5183dfb	8144	#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto	115:87f2f5183dfb	8145	#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto	115:87f2f5183dfb	8146	#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto	115:87f2f5183dfb	8147	#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto	115:87f2f5183dfb	8148	#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
Kojto	115:87f2f5183dfb	8149	#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
Kojto	115:87f2f5183dfb	8150	#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
Kojto	115:87f2f5183dfb	8151	#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
Kojto	115:87f2f5183dfb	8152	#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
Kojto	115:87f2f5183dfb	8153	#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
Kojto	115:87f2f5183dfb	8154	#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
Kojto	115:87f2f5183dfb	8155	#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
Kojto	115:87f2f5183dfb	8156	#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
Kojto	115:87f2f5183dfb	8157	#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
Kojto	115:87f2f5183dfb	8158	#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
Kojto	115:87f2f5183dfb	8159	#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto	115:87f2f5183dfb	8160	#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto	115:87f2f5183dfb	8161	#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto	115:87f2f5183dfb	8162	#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto	115:87f2f5183dfb	8163	#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto	115:87f2f5183dfb	8164	#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto	115:87f2f5183dfb	8165	#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto	115:87f2f5183dfb	8166	#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto	115:87f2f5183dfb	8167	#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
Kojto	115:87f2f5183dfb	8168	#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
Kojto	115:87f2f5183dfb	8169	#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
Kojto	115:87f2f5183dfb	8170	#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
Kojto	115:87f2f5183dfb	8171	#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
Kojto	115:87f2f5183dfb	8172	#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
Kojto	115:87f2f5183dfb	8173
Kojto	115:87f2f5183dfb	8174	/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
Kojto	115:87f2f5183dfb	8175	#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
Kojto	115:87f2f5183dfb	8176
Kojto	115:87f2f5183dfb	8177	/* Bit definition for Ethernet DMA Receive Poll Demand Register */
Kojto	115:87f2f5183dfb	8178	#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
Kojto	115:87f2f5183dfb	8179
Kojto	115:87f2f5183dfb	8180	/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
Kojto	115:87f2f5183dfb	8181	#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
Kojto	115:87f2f5183dfb	8182
Kojto	115:87f2f5183dfb	8183	/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
Kojto	115:87f2f5183dfb	8184	#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
Kojto	115:87f2f5183dfb	8185
Kojto	115:87f2f5183dfb	8186	/* Bit definition for Ethernet DMA Status Register */
Kojto	115:87f2f5183dfb	8187	#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
Kojto	115:87f2f5183dfb	8188	#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
Kojto	115:87f2f5183dfb	8189	#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
Kojto	115:87f2f5183dfb	8190	#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
Kojto	115:87f2f5183dfb	8191	/* combination with EBS[2:0] for GetFlagStatus function */
Kojto	115:87f2f5183dfb	8192	#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
Kojto	115:87f2f5183dfb	8193	#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
Kojto	115:87f2f5183dfb	8194	#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
Kojto	115:87f2f5183dfb	8195	#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
Kojto	115:87f2f5183dfb	8196	#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
Kojto	115:87f2f5183dfb	8197	#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
Kojto	115:87f2f5183dfb	8198	#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
Kojto	115:87f2f5183dfb	8199	#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
Kojto	115:87f2f5183dfb	8200	#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
Kojto	115:87f2f5183dfb	8201	#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
Kojto	115:87f2f5183dfb	8202	#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
Kojto	115:87f2f5183dfb	8203	#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
Kojto	115:87f2f5183dfb	8204	#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
Kojto	115:87f2f5183dfb	8205	#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
Kojto	115:87f2f5183dfb	8206	#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
Kojto	115:87f2f5183dfb	8207	#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
Kojto	115:87f2f5183dfb	8208	#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
Kojto	115:87f2f5183dfb	8209	#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
Kojto	115:87f2f5183dfb	8210	#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
Kojto	115:87f2f5183dfb	8211	#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
Kojto	115:87f2f5183dfb	8212	#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
Kojto	115:87f2f5183dfb	8213	#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
Kojto	115:87f2f5183dfb	8214	#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
Kojto	115:87f2f5183dfb	8215	#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
Kojto	115:87f2f5183dfb	8216	#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
Kojto	115:87f2f5183dfb	8217	#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
Kojto	115:87f2f5183dfb	8218	#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
Kojto	115:87f2f5183dfb	8219	#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
Kojto	115:87f2f5183dfb	8220	#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
Kojto	115:87f2f5183dfb	8221	#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
Kojto	115:87f2f5183dfb	8222	#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
Kojto	115:87f2f5183dfb	8223	#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
Kojto	115:87f2f5183dfb	8224
Kojto	115:87f2f5183dfb	8225	/* Bit definition for Ethernet DMA Operation Mode Register */
Kojto	115:87f2f5183dfb	8226	#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
Kojto	115:87f2f5183dfb	8227	#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
Kojto	115:87f2f5183dfb	8228	#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
Kojto	115:87f2f5183dfb	8229	#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
Kojto	115:87f2f5183dfb	8230	#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
Kojto	115:87f2f5183dfb	8231	#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
Kojto	115:87f2f5183dfb	8232	#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
Kojto	115:87f2f5183dfb	8233	#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
Kojto	115:87f2f5183dfb	8234	#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
Kojto	115:87f2f5183dfb	8235	#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
Kojto	115:87f2f5183dfb	8236	#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
Kojto	115:87f2f5183dfb	8237	#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
Kojto	115:87f2f5183dfb	8238	#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
Kojto	115:87f2f5183dfb	8239	#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
Kojto	115:87f2f5183dfb	8240	#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
Kojto	115:87f2f5183dfb	8241	#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
Kojto	115:87f2f5183dfb	8242	#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
Kojto	115:87f2f5183dfb	8243	#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
Kojto	115:87f2f5183dfb	8244	#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
Kojto	115:87f2f5183dfb	8245	#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
Kojto	115:87f2f5183dfb	8246	#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
Kojto	115:87f2f5183dfb	8247	#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
Kojto	115:87f2f5183dfb	8248	#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
Kojto	115:87f2f5183dfb	8249	#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
Kojto	115:87f2f5183dfb	8250
Kojto	115:87f2f5183dfb	8251	/* Bit definition for Ethernet DMA Interrupt Enable Register */
Kojto	115:87f2f5183dfb	8252	#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
Kojto	115:87f2f5183dfb	8253	#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
Kojto	115:87f2f5183dfb	8254	#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
Kojto	115:87f2f5183dfb	8255	#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
Kojto	115:87f2f5183dfb	8256	#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
Kojto	115:87f2f5183dfb	8257	#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
Kojto	115:87f2f5183dfb	8258	#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
Kojto	115:87f2f5183dfb	8259	#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
Kojto	115:87f2f5183dfb	8260	#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
Kojto	115:87f2f5183dfb	8261	#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
Kojto	115:87f2f5183dfb	8262	#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
Kojto	115:87f2f5183dfb	8263	#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
Kojto	115:87f2f5183dfb	8264	#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
Kojto	115:87f2f5183dfb	8265	#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
Kojto	115:87f2f5183dfb	8266	#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
Kojto	115:87f2f5183dfb	8267
Kojto	115:87f2f5183dfb	8268	/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
Kojto	115:87f2f5183dfb	8269	#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
Kojto	115:87f2f5183dfb	8270	#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
Kojto	115:87f2f5183dfb	8271	#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
Kojto	115:87f2f5183dfb	8272	#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
Kojto	115:87f2f5183dfb	8273
Kojto	115:87f2f5183dfb	8274	/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
Kojto	115:87f2f5183dfb	8275	#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
Kojto	115:87f2f5183dfb	8276
Kojto	115:87f2f5183dfb	8277	/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
Kojto	115:87f2f5183dfb	8278	#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
Kojto	115:87f2f5183dfb	8279
Kojto	115:87f2f5183dfb	8280	/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
Kojto	115:87f2f5183dfb	8281	#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
Kojto	115:87f2f5183dfb	8282
Kojto	115:87f2f5183dfb	8283	/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
Kojto	115:87f2f5183dfb	8284	#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
Kojto	115:87f2f5183dfb	8285
Kojto	115:87f2f5183dfb	8286	/******************************************************************************/
Kojto	115:87f2f5183dfb	8287	/* */
Kojto	115:87f2f5183dfb	8288	/* USB_OTG */
Kojto	115:87f2f5183dfb	8289	/* */
Kojto	115:87f2f5183dfb	8290	/******************************************************************************/
Kojto	115:87f2f5183dfb	8291	/****************** Bit definition for USB_OTG_GOTGCTL register ******************/
Kojto	115:87f2f5183dfb	8292	#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /!< Session request success /
Kojto	115:87f2f5183dfb	8293	#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /!< Session request /
Kojto	115:87f2f5183dfb	8294	#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /!< VBUS valid override enable /
Kojto	115:87f2f5183dfb	8295	#define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /!< VBUS valid override value /
Kojto	115:87f2f5183dfb	8296	#define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /!< A-peripheral session valid override enable /
Kojto	115:87f2f5183dfb	8297	#define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /!< A-peripheral session valid override value /
Kojto	115:87f2f5183dfb	8298	#define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /!< B-peripheral session valid override enable /
Kojto	115:87f2f5183dfb	8299	#define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /!< B-peripheral session valid override value /
Kojto	115:87f2f5183dfb	8300	#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /!< Host set HNP enable /
Kojto	115:87f2f5183dfb	8301	#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /!< HNP request /
Kojto	115:87f2f5183dfb	8302	#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /!< Host set HNP enable /
Kojto	115:87f2f5183dfb	8303	#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /!< Device HNP enabled /
Kojto	115:87f2f5183dfb	8304	#define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /!< Embedded host enable /
Kojto	115:87f2f5183dfb	8305	#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /!< Connector ID status /
Kojto	115:87f2f5183dfb	8306	#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /!< Long/short debounce time /
Kojto	115:87f2f5183dfb	8307	#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /!< A-session valid /
Kojto	115:87f2f5183dfb	8308	#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /!< B-session valid /
Kojto	115:87f2f5183dfb	8309	#define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /!< OTG version /
Kojto	115:87f2f5183dfb	8310
Kojto	115:87f2f5183dfb	8311	/****************** Bit definition for USB_OTG_HCFG register ******************/
Kojto	115:87f2f5183dfb	8312	#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /!< FS/LS PHY clock select /
Kojto	115:87f2f5183dfb	8313	#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8314	#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8315	#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /!< FS- and LS-only support /
Kojto	115:87f2f5183dfb	8316
Kojto	115:87f2f5183dfb	8317	/****************** Bit definition for USB_OTG_DCFG register ******************/
Kojto	115:87f2f5183dfb	8318	#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /!< Device speed /
Kojto	115:87f2f5183dfb	8319	#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8320	#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8321	#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /!< Nonzero-length status OUT handshake /
Kojto	115:87f2f5183dfb	8322
Kojto	115:87f2f5183dfb	8323	#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /!< Device address /
Kojto	115:87f2f5183dfb	8324	#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8325	#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8326	#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8327	#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8328	#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /!<Bit 4 /
Kojto	115:87f2f5183dfb	8329	#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /!<Bit 5 /
Kojto	115:87f2f5183dfb	8330	#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /!<Bit 6 /
Kojto	115:87f2f5183dfb	8331
Kojto	115:87f2f5183dfb	8332	#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /!< Periodic (micro)frame interval /
Kojto	115:87f2f5183dfb	8333	#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8334	#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8335
Kojto	115:87f2f5183dfb	8336	#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /!< Periodic scheduling interval /
Kojto	115:87f2f5183dfb	8337	#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8338	#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8339
Kojto	115:87f2f5183dfb	8340	/****************** Bit definition for USB_OTG_PCGCR register ******************/
Kojto	115:87f2f5183dfb	8341	#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /!< Stop PHY clock /
Kojto	115:87f2f5183dfb	8342	#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /!< Gate HCLK /
Kojto	115:87f2f5183dfb	8343	#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /!< PHY suspended /
Kojto	115:87f2f5183dfb	8344
Kojto	115:87f2f5183dfb	8345	/****************** Bit definition for USB_OTG_GOTGINT register ******************/
Kojto	115:87f2f5183dfb	8346	#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /!< Session end detected /
Kojto	115:87f2f5183dfb	8347	#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /!< Session request success status change /
Kojto	115:87f2f5183dfb	8348	#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /!< Host negotiation success status change /
Kojto	115:87f2f5183dfb	8349	#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /!< Host negotiation detected /
Kojto	115:87f2f5183dfb	8350	#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /!< A-device timeout change /
Kojto	115:87f2f5183dfb	8351	#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /!< Debounce done /
Kojto	115:87f2f5183dfb	8352	#define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /!< Change in ID pin input value /
Kojto	115:87f2f5183dfb	8353
Kojto	115:87f2f5183dfb	8354	/****************** Bit definition for USB_OTG_DCTL register ******************/
Kojto	115:87f2f5183dfb	8355	#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /!< Remote wakeup signaling /
Kojto	115:87f2f5183dfb	8356	#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /!< Soft disconnect /
Kojto	115:87f2f5183dfb	8357	#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /!< Global IN NAK status /
Kojto	115:87f2f5183dfb	8358	#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /!< Global OUT NAK status /
Kojto	115:87f2f5183dfb	8359
Kojto	115:87f2f5183dfb	8360	#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /!< Test control /
Kojto	115:87f2f5183dfb	8361	#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8362	#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8363	#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8364	#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /!< Set global IN NAK /
Kojto	115:87f2f5183dfb	8365	#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /!< Clear global IN NAK /
Kojto	115:87f2f5183dfb	8366	#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /!< Set global OUT NAK /
Kojto	115:87f2f5183dfb	8367	#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /!< Clear global OUT NAK /
Kojto	115:87f2f5183dfb	8368	#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /!< Power-on programming done /
Kojto	115:87f2f5183dfb	8369
Kojto	115:87f2f5183dfb	8370	/****************** Bit definition for USB_OTG_HFIR register ******************/
Kojto	115:87f2f5183dfb	8371	#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /!< Frame interval /
Kojto	115:87f2f5183dfb	8372
Kojto	115:87f2f5183dfb	8373	/****************** Bit definition for USB_OTG_HFNUM register ******************/
Kojto	115:87f2f5183dfb	8374	#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /!< Frame number /
Kojto	115:87f2f5183dfb	8375	#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /!< Frame time remaining /
Kojto	115:87f2f5183dfb	8376
Kojto	115:87f2f5183dfb	8377	/****************** Bit definition for USB_OTG_DSTS register ******************/
Kojto	115:87f2f5183dfb	8378	#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /!< Suspend status /
Kojto	115:87f2f5183dfb	8379
Kojto	115:87f2f5183dfb	8380	#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /!< Enumerated speed /
Kojto	115:87f2f5183dfb	8381	#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8382	#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8383	#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /!< Erratic error /
Kojto	115:87f2f5183dfb	8384	#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /!< Frame number of the received SOF /
Kojto	115:87f2f5183dfb	8385
Kojto	115:87f2f5183dfb	8386	/****************** Bit definition for USB_OTG_GAHBCFG register ******************/
Kojto	115:87f2f5183dfb	8387	#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /!< Global interrupt mask /
Kojto	115:87f2f5183dfb	8388	#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /!< Burst length/type /
Kojto	115:87f2f5183dfb	8389	#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8390	#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8391	#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8392	#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8393	#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /!< DMA enable /
Kojto	115:87f2f5183dfb	8394	#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /!< TxFIFO empty level /
Kojto	115:87f2f5183dfb	8395	#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /!< Periodic TxFIFO empty level /
Kojto	115:87f2f5183dfb	8396
Kojto	115:87f2f5183dfb	8397	/****************** Bit definition for USB_OTG_GUSBCFG register ******************/
Kojto	115:87f2f5183dfb	8398	#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /!< FS timeout calibration /
Kojto	115:87f2f5183dfb	8399	#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8400	#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8401	#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8402	#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select /
Kojto	115:87f2f5183dfb	8403	#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /!< SRP-capable /
Kojto	115:87f2f5183dfb	8404	#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /!< HNP-capable /
Kojto	115:87f2f5183dfb	8405	#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /!< USB turnaround time /
Kojto	115:87f2f5183dfb	8406	#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8407	#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8408	#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8409	#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8410	#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /!< PHY Low-power clock select /
Kojto	115:87f2f5183dfb	8411	#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /!< ULPI FS/LS select /
Kojto	115:87f2f5183dfb	8412	#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /!< ULPI Auto-resume /
Kojto	115:87f2f5183dfb	8413	#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /!< ULPI Clock SuspendM /
Kojto	115:87f2f5183dfb	8414	#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /!< ULPI External VBUS Drive /
Kojto	115:87f2f5183dfb	8415	#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /!< ULPI external VBUS indicator /
Kojto	115:87f2f5183dfb	8416	#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /!< TermSel DLine pulsing selection /
Kojto	115:87f2f5183dfb	8417	#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /!< Indicator complement /
Kojto	115:87f2f5183dfb	8418	#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /!< Indicator pass through /
Kojto	115:87f2f5183dfb	8419	#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /!< ULPI interface protect disable /
Kojto	115:87f2f5183dfb	8420	#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /!< Forced host mode /
Kojto	115:87f2f5183dfb	8421	#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /!< Forced peripheral mode /
Kojto	115:87f2f5183dfb	8422	#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /!< Corrupt Tx packet /
Kojto	115:87f2f5183dfb	8423
Kojto	115:87f2f5183dfb	8424	/****************** Bit definition for USB_OTG_GRSTCTL register ******************/
Kojto	115:87f2f5183dfb	8425	#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /!< Core soft reset /
Kojto	115:87f2f5183dfb	8426	#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /!< HCLK soft reset /
Kojto	115:87f2f5183dfb	8427	#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /!< Host frame counter reset /
Kojto	115:87f2f5183dfb	8428	#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /!< RxFIFO flush /
Kojto	115:87f2f5183dfb	8429	#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /!< TxFIFO flush /
Kojto	115:87f2f5183dfb	8430	#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /!< TxFIFO number /
Kojto	115:87f2f5183dfb	8431	#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8432	#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8433	#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8434	#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8435	#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /!<Bit 4 /
Kojto	115:87f2f5183dfb	8436	#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /!< DMA request signal /
Kojto	115:87f2f5183dfb	8437	#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /!< AHB master idle /
Kojto	115:87f2f5183dfb	8438
Kojto	115:87f2f5183dfb	8439	/****************** Bit definition for USB_OTG_DIEPMSK register ******************/
Kojto	115:87f2f5183dfb	8440	#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
Kojto	115:87f2f5183dfb	8441	#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
Kojto	115:87f2f5183dfb	8442	#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /!< Timeout condition mask (nonisochronous endpoints) /
Kojto	115:87f2f5183dfb	8443	#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
Kojto	115:87f2f5183dfb	8444	#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
Kojto	115:87f2f5183dfb	8445	#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
Kojto	115:87f2f5183dfb	8446	#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /!< FIFO underrun mask /
Kojto	115:87f2f5183dfb	8447	#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
Kojto	115:87f2f5183dfb	8448
Kojto	115:87f2f5183dfb	8449	/****************** Bit definition for USB_OTG_HPTXSTS register ******************/
Kojto	115:87f2f5183dfb	8450	#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /!< Periodic transmit data FIFO space available /
Kojto	115:87f2f5183dfb	8451	#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /!< Periodic transmit request queue space available /
Kojto	115:87f2f5183dfb	8452	#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8453	#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8454	#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8455	#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8456	#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	8457	#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	8458	#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	8459	#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	8460
Kojto	115:87f2f5183dfb	8461	#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /!< Top of the periodic transmit request queue /
Kojto	115:87f2f5183dfb	8462	#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8463	#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8464	#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8465	#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8466	#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	8467	#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	8468	#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	8469	#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	8470
Kojto	115:87f2f5183dfb	8471	/****************** Bit definition for USB_OTG_HAINT register ******************/
Kojto	115:87f2f5183dfb	8472	#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /!< Channel interrupts /
Kojto	115:87f2f5183dfb	8473
Kojto	115:87f2f5183dfb	8474	/****************** Bit definition for USB_OTG_DOEPMSK register ******************/
Kojto	115:87f2f5183dfb	8475	#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
Kojto	115:87f2f5183dfb	8476	#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
Kojto	115:87f2f5183dfb	8477	#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /!< SETUP phase done mask /
Kojto	115:87f2f5183dfb	8478	#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /!< OUT token received when endpoint disabled mask /
Kojto	115:87f2f5183dfb	8479	#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /!< Back-to-back SETUP packets received mask /
Kojto	115:87f2f5183dfb	8480	#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /!< OUT packet error mask /
Kojto	115:87f2f5183dfb	8481	#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
Kojto	115:87f2f5183dfb	8482
Kojto	115:87f2f5183dfb	8483	/****************** Bit definition for USB_OTG_GINTSTS register ******************/
Kojto	115:87f2f5183dfb	8484	#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /!< Current mode of operation /
Kojto	115:87f2f5183dfb	8485	#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /!< Mode mismatch interrupt /
Kojto	115:87f2f5183dfb	8486	#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /!< OTG interrupt /
Kojto	115:87f2f5183dfb	8487	#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /!< Start of frame /
Kojto	115:87f2f5183dfb	8488	#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /!< RxFIFO nonempty /
Kojto	115:87f2f5183dfb	8489	#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /!< Nonperiodic TxFIFO empty /
Kojto	115:87f2f5183dfb	8490	#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /!< Global IN nonperiodic NAK effective /
Kojto	115:87f2f5183dfb	8491	#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /!< Global OUT NAK effective /
Kojto	115:87f2f5183dfb	8492	#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /!< Early suspend /
Kojto	115:87f2f5183dfb	8493	#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /!< USB suspend /
Kojto	115:87f2f5183dfb	8494	#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /!< USB reset /
Kojto	115:87f2f5183dfb	8495	#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /!< Enumeration done /
Kojto	115:87f2f5183dfb	8496	#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /!< Isochronous OUT packet dropped interrupt /
Kojto	115:87f2f5183dfb	8497	#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /!< End of periodic frame interrupt /
Kojto	115:87f2f5183dfb	8498	#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /!< IN endpoint interrupt /
Kojto	115:87f2f5183dfb	8499	#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /!< OUT endpoint interrupt /
Kojto	115:87f2f5183dfb	8500	#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /!< Incomplete isochronous IN transfer /
Kojto	115:87f2f5183dfb	8501	#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /!< Incomplete periodic transfer /
Kojto	115:87f2f5183dfb	8502	#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /!< Data fetch suspended /
Kojto	115:87f2f5183dfb	8503	#define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /!< Reset detected interrupt /
Kojto	115:87f2f5183dfb	8504	#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /!< Host port interrupt /
Kojto	115:87f2f5183dfb	8505	#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /!< Host channels interrupt /
Kojto	115:87f2f5183dfb	8506	#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /!< Periodic TxFIFO empty /
Kojto	115:87f2f5183dfb	8507	#define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /!< LPM interrupt /
Kojto	115:87f2f5183dfb	8508	#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /!< Connector ID status change /
Kojto	115:87f2f5183dfb	8509	#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /!< Disconnect detected interrupt /
Kojto	115:87f2f5183dfb	8510	#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /!< Session request/new session detected interrupt /
Kojto	115:87f2f5183dfb	8511	#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /!< Resume/remote wakeup detected interrupt /
Kojto	115:87f2f5183dfb	8512
Kojto	115:87f2f5183dfb	8513	/****************** Bit definition for USB_OTG_GINTMSK register ******************/
Kojto	115:87f2f5183dfb	8514	#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /!< Mode mismatch interrupt mask /
Kojto	115:87f2f5183dfb	8515	#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /!< OTG interrupt mask /
Kojto	115:87f2f5183dfb	8516	#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /!< Start of frame mask /
Kojto	115:87f2f5183dfb	8517	#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /!< Receive FIFO nonempty mask /
Kojto	115:87f2f5183dfb	8518	#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /!< Nonperiodic TxFIFO empty mask /
Kojto	115:87f2f5183dfb	8519	#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /!< Global nonperiodic IN NAK effective mask /
Kojto	115:87f2f5183dfb	8520	#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /!< Global OUT NAK effective mask /
Kojto	115:87f2f5183dfb	8521	#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /!< Early suspend mask /
Kojto	115:87f2f5183dfb	8522	#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /!< USB suspend mask /
Kojto	115:87f2f5183dfb	8523	#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /!< USB reset mask /
Kojto	115:87f2f5183dfb	8524	#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /!< Enumeration done mask /
Kojto	115:87f2f5183dfb	8525	#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /!< Isochronous OUT packet dropped interrupt mask /
Kojto	115:87f2f5183dfb	8526	#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /!< End of periodic frame interrupt mask /
Kojto	115:87f2f5183dfb	8527	#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /!< Endpoint mismatch interrupt mask /
Kojto	115:87f2f5183dfb	8528	#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /!< IN endpoints interrupt mask /
Kojto	115:87f2f5183dfb	8529	#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /!< OUT endpoints interrupt mask /
Kojto	115:87f2f5183dfb	8530	#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /!< Incomplete isochronous IN transfer mask /
Kojto	115:87f2f5183dfb	8531	#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /!< Incomplete periodic transfer mask /
Kojto	115:87f2f5183dfb	8532	#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /!< Data fetch suspended mask /
Kojto	115:87f2f5183dfb	8533	#define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /!< Reset detected interrupt mask /
Kojto	115:87f2f5183dfb	8534	#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /!< Host port interrupt mask /
Kojto	115:87f2f5183dfb	8535	#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /!< Host channels interrupt mask /
Kojto	115:87f2f5183dfb	8536	#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /!< Periodic TxFIFO empty mask /
Kojto	115:87f2f5183dfb	8537	#define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /!< LPM interrupt Mask /
Kojto	115:87f2f5183dfb	8538	#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /!< Connector ID status change mask /
Kojto	115:87f2f5183dfb	8539	#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /!< Disconnect detected interrupt mask /
Kojto	115:87f2f5183dfb	8540	#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /!< Session request/new session detected interrupt mask /
Kojto	115:87f2f5183dfb	8541	#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /!< Resume/remote wakeup detected interrupt mask /
Kojto	115:87f2f5183dfb	8542
Kojto	115:87f2f5183dfb	8543	/****************** Bit definition for USB_OTG_DAINT register ******************/
Kojto	115:87f2f5183dfb	8544	#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /!< IN endpoint interrupt bits /
Kojto	115:87f2f5183dfb	8545	#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /!< OUT endpoint interrupt bits /
Kojto	115:87f2f5183dfb	8546
Kojto	115:87f2f5183dfb	8547	/****************** Bit definition for USB_OTG_HAINTMSK register ******************/
Kojto	115:87f2f5183dfb	8548	#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /!< Channel interrupt mask /
Kojto	115:87f2f5183dfb	8549
Kojto	115:87f2f5183dfb	8550	/****************** Bit definition for USB_OTG_GRXSTSP register ******************/
Kojto	115:87f2f5183dfb	8551	#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /!< IN EP interrupt mask bits /
Kojto	115:87f2f5183dfb	8552	#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /!< OUT EP interrupt mask bits /
Kojto	115:87f2f5183dfb	8553	#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /!< OUT EP interrupt mask bits /
Kojto	115:87f2f5183dfb	8554	#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /!< OUT EP interrupt mask bits /
Kojto	115:87f2f5183dfb	8555
Kojto	115:87f2f5183dfb	8556	/****************** Bit definition for USB_OTG_DAINTMSK register ******************/
Kojto	115:87f2f5183dfb	8557	#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /!< IN EP interrupt mask bits /
Kojto	115:87f2f5183dfb	8558	#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /!< OUT EP interrupt mask bits /
Kojto	115:87f2f5183dfb	8559
Kojto	115:87f2f5183dfb	8560	/****************** Bit definition for OTG register ******************/
Kojto	115:87f2f5183dfb	8561
Kojto	115:87f2f5183dfb	8562	#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /!< Channel number /
Kojto	115:87f2f5183dfb	8563	#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8564	#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8565	#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8566	#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8567	#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /!< Byte count /
Kojto	115:87f2f5183dfb	8568
Kojto	115:87f2f5183dfb	8569	#define USB_OTG_DPID ((uint32_t)0x00018000) /!< Data PID /
Kojto	115:87f2f5183dfb	8570	#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8571	#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8572
Kojto	115:87f2f5183dfb	8573	#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /!< Packet status /
Kojto	115:87f2f5183dfb	8574	#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8575	#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8576	#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8577	#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8578
Kojto	115:87f2f5183dfb	8579	#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /!< Endpoint number /
Kojto	115:87f2f5183dfb	8580	#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8581	#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8582	#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8583	#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8584
Kojto	115:87f2f5183dfb	8585	#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /!< Frame number /
Kojto	115:87f2f5183dfb	8586	#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8587	#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8588	#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8589	#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8590
Kojto	115:87f2f5183dfb	8591	/****************** Bit definition for OTG register ******************/
Kojto	115:87f2f5183dfb	8592
Kojto	115:87f2f5183dfb	8593	#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /!< Channel number /
Kojto	115:87f2f5183dfb	8594	#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8595	#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8596	#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8597	#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8598	#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /!< Byte count /
Kojto	115:87f2f5183dfb	8599
Kojto	115:87f2f5183dfb	8600	#define USB_OTG_DPID ((uint32_t)0x00018000) /!< Data PID /
Kojto	115:87f2f5183dfb	8601	#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8602	#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8603
Kojto	115:87f2f5183dfb	8604	#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /!< Packet status /
Kojto	115:87f2f5183dfb	8605	#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8606	#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8607	#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8608	#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8609
Kojto	115:87f2f5183dfb	8610	#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /!< Endpoint number /
Kojto	115:87f2f5183dfb	8611	#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8612	#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8613	#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8614	#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8615
Kojto	115:87f2f5183dfb	8616	#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /!< Frame number /
Kojto	115:87f2f5183dfb	8617	#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8618	#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8619	#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8620	#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8621
Kojto	115:87f2f5183dfb	8622	/****************** Bit definition for USB_OTG_GRXFSIZ register ******************/
Kojto	115:87f2f5183dfb	8623	#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /!< RxFIFO depth /
Kojto	115:87f2f5183dfb	8624
Kojto	115:87f2f5183dfb	8625	/****************** Bit definition for USB_OTG_DVBUSDIS register ******************/
Kojto	115:87f2f5183dfb	8626	#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /!< Device VBUS discharge time /
Kojto	115:87f2f5183dfb	8627
Kojto	115:87f2f5183dfb	8628	/****************** Bit definition for OTG register ******************/
Kojto	115:87f2f5183dfb	8629	#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /!< Nonperiodic transmit RAM start address /
Kojto	115:87f2f5183dfb	8630	#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /!< Nonperiodic TxFIFO depth /
Kojto	115:87f2f5183dfb	8631	#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /!< Endpoint 0 transmit RAM start address /
Kojto	115:87f2f5183dfb	8632	#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /!< Endpoint 0 TxFIFO depth /
Kojto	115:87f2f5183dfb	8633
Kojto	115:87f2f5183dfb	8634	/****************** Bit definition for USB_OTG_DVBUSPULSE register ******************/
Kojto	115:87f2f5183dfb	8635	#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /!< Device VBUS pulsing time /
Kojto	115:87f2f5183dfb	8636
Kojto	115:87f2f5183dfb	8637	/****************** Bit definition for USB_OTG_GNPTXSTS register ******************/
Kojto	115:87f2f5183dfb	8638	#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /!< Nonperiodic TxFIFO space available /
Kojto	115:87f2f5183dfb	8639
Kojto	115:87f2f5183dfb	8640	#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /!< Nonperiodic transmit request queue space available /
Kojto	115:87f2f5183dfb	8641	#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8642	#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8643	#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8644	#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8645	#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	8646	#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	8647	#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	8648	#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	8649
Kojto	115:87f2f5183dfb	8650	#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /!< Top of the nonperiodic transmit request queue /
Kojto	115:87f2f5183dfb	8651	#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8652	#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8653	#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8654	#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8655	#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	8656	#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	8657	#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	8658
Kojto	115:87f2f5183dfb	8659	/****************** Bit definition for USB_OTG_DTHRCTL register ******************/
Kojto	115:87f2f5183dfb	8660	#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /!< Nonisochronous IN endpoints threshold enable /
Kojto	115:87f2f5183dfb	8661	#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /!< ISO IN endpoint threshold enable /
Kojto	115:87f2f5183dfb	8662
Kojto	115:87f2f5183dfb	8663	#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /!< Transmit threshold length /
Kojto	115:87f2f5183dfb	8664	#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8665	#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8666	#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8667	#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8668	#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /!<Bit 4 /
Kojto	115:87f2f5183dfb	8669	#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /!<Bit 5 /
Kojto	115:87f2f5183dfb	8670	#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /!<Bit 6 /
Kojto	115:87f2f5183dfb	8671	#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /!<Bit 7 /
Kojto	115:87f2f5183dfb	8672	#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /!<Bit 8 /
Kojto	115:87f2f5183dfb	8673	#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /!< Receive threshold enable /
Kojto	115:87f2f5183dfb	8674
Kojto	115:87f2f5183dfb	8675	#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /!< Receive threshold length /
Kojto	115:87f2f5183dfb	8676	#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8677	#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8678	#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8679	#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8680	#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	8681	#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	8682	#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	8683	#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /!<Bit 7 /
Kojto	115:87f2f5183dfb	8684	#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /!<Bit 8 /
Kojto	115:87f2f5183dfb	8685	#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /!< Arbiter parking enable /
Kojto	115:87f2f5183dfb	8686
Kojto	115:87f2f5183dfb	8687	/****************** Bit definition for USB_OTG_DIEPEMPMSK register ******************/
Kojto	115:87f2f5183dfb	8688	#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /!< IN EP Tx FIFO empty interrupt mask bits /
Kojto	115:87f2f5183dfb	8689
Kojto	115:87f2f5183dfb	8690	/****************** Bit definition for USB_OTG_DEACHINT register ******************/
Kojto	115:87f2f5183dfb	8691	#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /!< IN endpoint 1interrupt bit /
Kojto	115:87f2f5183dfb	8692	#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /!< OUT endpoint 1 interrupt bit /
Kojto	115:87f2f5183dfb	8693
Kojto	115:87f2f5183dfb	8694	/****************** Bit definition for USB_OTG_GCCFG register ******************/
Kojto	115:87f2f5183dfb	8695	#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /!< Power down /
Kojto	115:87f2f5183dfb	8696	#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /!< USB VBUS Detection Enable /
Kojto	115:87f2f5183dfb	8697
Kojto	115:87f2f5183dfb	8698	/****************** Bit definition for USB_OTG_GPWRDN) register ******************/
Kojto	115:87f2f5183dfb	8699	#define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /!< ADP module enable /
Kojto	115:87f2f5183dfb	8700	#define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /!< ADP Interrupt flag /
Kojto	115:87f2f5183dfb	8701
Kojto	115:87f2f5183dfb	8702	/****************** Bit definition for USB_OTG_DEACHINTMSK register ******************/
Kojto	115:87f2f5183dfb	8703	#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /!< IN Endpoint 1 interrupt mask bit /
Kojto	115:87f2f5183dfb	8704	#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /!< OUT Endpoint 1 interrupt mask bit /
Kojto	115:87f2f5183dfb	8705
Kojto	115:87f2f5183dfb	8706	/****************** Bit definition for USB_OTG_CID register ******************/
Kojto	115:87f2f5183dfb	8707	#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /!< Product ID field /
Kojto	115:87f2f5183dfb	8708
Kojto	115:87f2f5183dfb	8709	/****************** Bit definition for USB_OTG_GLPMCFG register ******************/
Kojto	115:87f2f5183dfb	8710	#define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /!< LPM support enable /
Kojto	115:87f2f5183dfb	8711	#define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /!< LPM Token acknowledge enable /
Kojto	115:87f2f5183dfb	8712	#define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /!< BESL value received with last ACKed LPM Token /
Kojto	115:87f2f5183dfb	8713	#define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /!< bRemoteWake value received with last ACKed LPM Token /
Kojto	115:87f2f5183dfb	8714	#define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /!< L1 shallow sleep enable /
Kojto	115:87f2f5183dfb	8715	#define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /!< BESL threshold /
Kojto	115:87f2f5183dfb	8716	#define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /!< L1 deep sleep enable /
Kojto	115:87f2f5183dfb	8717	#define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /!< LPM response /
Kojto	115:87f2f5183dfb	8718	#define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /!< Port sleep status /
Kojto	115:87f2f5183dfb	8719	#define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /!< Sleep State Resume OK /
Kojto	115:87f2f5183dfb	8720	#define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /!< LPM Channel Index /
Kojto	115:87f2f5183dfb	8721	#define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /!< LPM retry count /
Kojto	115:87f2f5183dfb	8722	#define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /!< Send LPM transaction /
Kojto	115:87f2f5183dfb	8723	#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /!< LPM retry count status /
Kojto	115:87f2f5183dfb	8724	#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /!< Enable best effort service latency /
Kojto	115:87f2f5183dfb	8725
Kojto	115:87f2f5183dfb	8726	/****************** Bit definition for USB_OTG_DIEPEACHMSK1 register ******************/
Kojto	115:87f2f5183dfb	8727	#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
Kojto	115:87f2f5183dfb	8728	#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
Kojto	115:87f2f5183dfb	8729	#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /!< Timeout condition mask (nonisochronous endpoints) /
Kojto	115:87f2f5183dfb	8730	#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
Kojto	115:87f2f5183dfb	8731	#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
Kojto	115:87f2f5183dfb	8732	#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
Kojto	115:87f2f5183dfb	8733	#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /!< FIFO underrun mask /
Kojto	115:87f2f5183dfb	8734	#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
Kojto	115:87f2f5183dfb	8735	#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /!< NAK interrupt mask /
Kojto	115:87f2f5183dfb	8736
Kojto	115:87f2f5183dfb	8737	/****************** Bit definition for USB_OTG_HPRT register ******************/
Kojto	115:87f2f5183dfb	8738	#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /!< Port connect status /
Kojto	115:87f2f5183dfb	8739	#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /!< Port connect detected /
Kojto	115:87f2f5183dfb	8740	#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /!< Port enable /
Kojto	115:87f2f5183dfb	8741	#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /!< Port enable/disable change /
Kojto	115:87f2f5183dfb	8742	#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /!< Port overcurrent active /
Kojto	115:87f2f5183dfb	8743	#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /!< Port overcurrent change /
Kojto	115:87f2f5183dfb	8744	#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /!< Port resume /
Kojto	115:87f2f5183dfb	8745	#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /!< Port suspend /
Kojto	115:87f2f5183dfb	8746	#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /!< Port reset /
Kojto	115:87f2f5183dfb	8747
Kojto	115:87f2f5183dfb	8748	#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /!< Port line status /
Kojto	115:87f2f5183dfb	8749	#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8750	#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8751	#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /!< Port power /
Kojto	115:87f2f5183dfb	8752
Kojto	115:87f2f5183dfb	8753	#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /!< Port test control /
Kojto	115:87f2f5183dfb	8754	#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8755	#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8756	#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8757	#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8758
Kojto	115:87f2f5183dfb	8759	#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /!< Port speed /
Kojto	115:87f2f5183dfb	8760	#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8761	#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8762
Kojto	115:87f2f5183dfb	8763	/****************** Bit definition for USB_OTG_DOEPEACHMSK1 register ******************/
Kojto	115:87f2f5183dfb	8764	#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
Kojto	115:87f2f5183dfb	8765	#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
Kojto	115:87f2f5183dfb	8766	#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /!< Timeout condition mask /
Kojto	115:87f2f5183dfb	8767	#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
Kojto	115:87f2f5183dfb	8768	#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
Kojto	115:87f2f5183dfb	8769	#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
Kojto	115:87f2f5183dfb	8770	#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /!< OUT packet error mask /
Kojto	115:87f2f5183dfb	8771	#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
Kojto	115:87f2f5183dfb	8772	#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /!< Bubble error interrupt mask /
Kojto	115:87f2f5183dfb	8773	#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /!< NAK interrupt mask /
Kojto	115:87f2f5183dfb	8774	#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /!< NYET interrupt mask /
Kojto	115:87f2f5183dfb	8775
Kojto	115:87f2f5183dfb	8776	/****************** Bit definition for USB_OTG_HPTXFSIZ register ******************/
Kojto	115:87f2f5183dfb	8777	#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /!< Host periodic TxFIFO start address /
Kojto	115:87f2f5183dfb	8778	#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /!< Host periodic TxFIFO depth /
Kojto	115:87f2f5183dfb	8779
Kojto	115:87f2f5183dfb	8780	/****************** Bit definition for USB_OTG_DIEPCTL register ******************/
Kojto	115:87f2f5183dfb	8781	#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size /
Kojto	115:87f2f5183dfb	8782	#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /!< USB active endpoint /
Kojto	115:87f2f5183dfb	8783	#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /!< Even/odd frame /
Kojto	115:87f2f5183dfb	8784	#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /!< NAK status /
Kojto	115:87f2f5183dfb	8785
Kojto	115:87f2f5183dfb	8786	#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
Kojto	115:87f2f5183dfb	8787	#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8788	#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8789	#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /!< STALL handshake /
Kojto	115:87f2f5183dfb	8790
Kojto	115:87f2f5183dfb	8791	#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /!< TxFIFO number /
Kojto	115:87f2f5183dfb	8792	#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8793	#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8794	#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8795	#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8796	#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /!< Clear NAK /
Kojto	115:87f2f5183dfb	8797	#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /!< Set NAK /
Kojto	115:87f2f5183dfb	8798	#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /!< Set DATA0 PID /
Kojto	115:87f2f5183dfb	8799	#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /!< Set odd frame /
Kojto	115:87f2f5183dfb	8800	#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /!< Endpoint disable /
Kojto	115:87f2f5183dfb	8801	#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /!< Endpoint enable /
Kojto	115:87f2f5183dfb	8802
Kojto	115:87f2f5183dfb	8803	/****************** Bit definition for USB_OTG_HCCHAR register ******************/
Kojto	115:87f2f5183dfb	8804	#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size /
Kojto	115:87f2f5183dfb	8805
Kojto	115:87f2f5183dfb	8806	#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /!< Endpoint number /
Kojto	115:87f2f5183dfb	8807	#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8808	#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8809	#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8810	#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8811	#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /!< Endpoint direction /
Kojto	115:87f2f5183dfb	8812	#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /!< Low-speed device /
Kojto	115:87f2f5183dfb	8813
Kojto	115:87f2f5183dfb	8814	#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
Kojto	115:87f2f5183dfb	8815	#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8816	#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8817
Kojto	115:87f2f5183dfb	8818	#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /!< Multi Count (MC) / Error Count (EC) /
Kojto	115:87f2f5183dfb	8819	#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8820	#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8821
Kojto	115:87f2f5183dfb	8822	#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /!< Device address /
Kojto	115:87f2f5183dfb	8823	#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8824	#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8825	#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8826	#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8827	#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /!<Bit 4 /
Kojto	115:87f2f5183dfb	8828	#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	8829	#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	8830	#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /!< Odd frame /
Kojto	115:87f2f5183dfb	8831	#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /!< Channel disable /
Kojto	115:87f2f5183dfb	8832	#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /!< Channel enable /
Kojto	115:87f2f5183dfb	8833
Kojto	115:87f2f5183dfb	8834	/****************** Bit definition for USB_OTG_HCSPLT register ******************/
Kojto	115:87f2f5183dfb	8835
Kojto	115:87f2f5183dfb	8836	#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /!< Port address /
Kojto	115:87f2f5183dfb	8837	#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8838	#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8839	#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8840	#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8841	#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	115:87f2f5183dfb	8842	#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /!<Bit 5 /
Kojto	115:87f2f5183dfb	8843	#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /!<Bit 6 /
Kojto	115:87f2f5183dfb	8844
Kojto	115:87f2f5183dfb	8845	#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /!< Hub address /
Kojto	115:87f2f5183dfb	8846	#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8847	#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8848	#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /!<Bit 2 /
Kojto	115:87f2f5183dfb	8849	#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /!<Bit 3 /
Kojto	115:87f2f5183dfb	8850	#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /!<Bit 4 /
Kojto	115:87f2f5183dfb	8851	#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /!<Bit 5 /
Kojto	115:87f2f5183dfb	8852	#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /!<Bit 6 /
Kojto	115:87f2f5183dfb	8853
Kojto	115:87f2f5183dfb	8854	#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /!< XACTPOS /
Kojto	115:87f2f5183dfb	8855	#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8856	#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8857	#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /!< Do complete split /
Kojto	115:87f2f5183dfb	8858	#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /!< Split enable /
Kojto	115:87f2f5183dfb	8859
Kojto	115:87f2f5183dfb	8860	/****************** Bit definition for USB_OTG_HCINT register ******************/
Kojto	115:87f2f5183dfb	8861	#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed /
Kojto	115:87f2f5183dfb	8862	#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /!< Channel halted /
Kojto	115:87f2f5183dfb	8863	#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /!< AHB error /
Kojto	115:87f2f5183dfb	8864	#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /!< STALL response received interrupt /
Kojto	115:87f2f5183dfb	8865	#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /!< NAK response received interrupt /
Kojto	115:87f2f5183dfb	8866	#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /!< ACK response received/transmitted interrupt /
Kojto	115:87f2f5183dfb	8867	#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /!< Response received interrupt /
Kojto	115:87f2f5183dfb	8868	#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /!< Transaction error /
Kojto	115:87f2f5183dfb	8869	#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /!< Babble error /
Kojto	115:87f2f5183dfb	8870	#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /!< Frame overrun /
Kojto	115:87f2f5183dfb	8871	#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /!< Data toggle error /
Kojto	115:87f2f5183dfb	8872
Kojto	115:87f2f5183dfb	8873	/****************** Bit definition for USB_OTG_DIEPINT register ******************/
Kojto	115:87f2f5183dfb	8874	#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed interrupt /
Kojto	115:87f2f5183dfb	8875	#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /!< Endpoint disabled interrupt /
Kojto	115:87f2f5183dfb	8876	#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /!< Timeout condition /
Kojto	115:87f2f5183dfb	8877	#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /!< IN token received when TxFIFO is empty /
Kojto	115:87f2f5183dfb	8878	#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /!< IN endpoint NAK effective /
Kojto	115:87f2f5183dfb	8879	#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /!< Transmit FIFO empty /
Kojto	115:87f2f5183dfb	8880	#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /!< Transmit Fifo Underrun /
Kojto	115:87f2f5183dfb	8881	#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /!< Buffer not available interrupt /
Kojto	115:87f2f5183dfb	8882	#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /!< Packet dropped status /
Kojto	115:87f2f5183dfb	8883	#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /!< Babble error interrupt /
Kojto	115:87f2f5183dfb	8884	#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /!< NAK interrupt /
Kojto	115:87f2f5183dfb	8885
Kojto	115:87f2f5183dfb	8886	/****************** Bit definition for USB_OTG_HCINTMSK register ******************/
Kojto	115:87f2f5183dfb	8887	#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed mask /
Kojto	115:87f2f5183dfb	8888	#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /!< Channel halted mask /
Kojto	115:87f2f5183dfb	8889	#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /!< AHB error /
Kojto	115:87f2f5183dfb	8890	#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /!< STALL response received interrupt mask /
Kojto	115:87f2f5183dfb	8891	#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /!< NAK response received interrupt mask /
Kojto	115:87f2f5183dfb	8892	#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /!< ACK response received/transmitted interrupt mask /
Kojto	115:87f2f5183dfb	8893	#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /!< response received interrupt mask /
Kojto	115:87f2f5183dfb	8894	#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /!< Transaction error mask /
Kojto	115:87f2f5183dfb	8895	#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /!< Babble error mask /
Kojto	115:87f2f5183dfb	8896	#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /!< Frame overrun mask /
Kojto	115:87f2f5183dfb	8897	#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /!< Data toggle error mask /
Kojto	115:87f2f5183dfb	8898
Kojto	115:87f2f5183dfb	8899	/****************** Bit definition for USB_OTG_DIEPTSIZ register ******************/
Kojto	115:87f2f5183dfb	8900
Kojto	115:87f2f5183dfb	8901	#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
Kojto	115:87f2f5183dfb	8902	#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
Kojto	115:87f2f5183dfb	8903	#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /!< Packet count /
Kojto	115:87f2f5183dfb	8904	/****************** Bit definition for USB_OTG_HCTSIZ register ******************/
Kojto	115:87f2f5183dfb	8905	#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
Kojto	115:87f2f5183dfb	8906	#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
Kojto	115:87f2f5183dfb	8907	#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /!< Do PING /
Kojto	115:87f2f5183dfb	8908	#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /!< Data PID /
Kojto	115:87f2f5183dfb	8909	#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8910	#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8911
Kojto	115:87f2f5183dfb	8912	/****************** Bit definition for USB_OTG_DIEPDMA register ******************/
Kojto	115:87f2f5183dfb	8913	#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /!< DMA address /
Kojto	115:87f2f5183dfb	8914
Kojto	115:87f2f5183dfb	8915	/****************** Bit definition for USB_OTG_HCDMA register ******************/
Kojto	115:87f2f5183dfb	8916	#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /!< DMA address /
Kojto	115:87f2f5183dfb	8917
Kojto	115:87f2f5183dfb	8918	/****************** Bit definition for USB_OTG_DTXFSTS register ******************/
Kojto	115:87f2f5183dfb	8919	#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /!< IN endpoint TxFIFO space available /
Kojto	115:87f2f5183dfb	8920
Kojto	115:87f2f5183dfb	8921	/****************** Bit definition for USB_OTG_DIEPTXF register ******************/
Kojto	115:87f2f5183dfb	8922	#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /!< IN endpoint FIFOx transmit RAM start address /
Kojto	115:87f2f5183dfb	8923	#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /!< IN endpoint TxFIFO depth /
Kojto	115:87f2f5183dfb	8924
Kojto	115:87f2f5183dfb	8925	/****************** Bit definition for USB_OTG_DOEPCTL register ******************/
Kojto	115:87f2f5183dfb	8926	#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size / /!<Bit 1 /
Kojto	115:87f2f5183dfb	8927	#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /!< USB active endpoint /
Kojto	115:87f2f5183dfb	8928	#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /!< NAK status /
Kojto	115:87f2f5183dfb	8929	#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /!< Set DATA0 PID /
Kojto	115:87f2f5183dfb	8930	#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /!< Set odd frame /
Kojto	115:87f2f5183dfb	8931	#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
Kojto	115:87f2f5183dfb	8932	#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8933	#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8934	#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /!< Snoop mode /
Kojto	115:87f2f5183dfb	8935	#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /!< STALL handshake /
Kojto	115:87f2f5183dfb	8936	#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /!< Clear NAK /
Kojto	115:87f2f5183dfb	8937	#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /!< Set NAK /
Kojto	115:87f2f5183dfb	8938	#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /!< Endpoint disable /
Kojto	115:87f2f5183dfb	8939	#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /!< Endpoint enable /
Kojto	115:87f2f5183dfb	8940
Kojto	115:87f2f5183dfb	8941	/****************** Bit definition for USB_OTG_DOEPINT register ******************/
Kojto	115:87f2f5183dfb	8942	#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed interrupt /
Kojto	115:87f2f5183dfb	8943	#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /!< Endpoint disabled interrupt /
Kojto	115:87f2f5183dfb	8944	#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /!< SETUP phase done /
Kojto	115:87f2f5183dfb	8945	#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /!< OUT token received when endpoint disabled /
Kojto	115:87f2f5183dfb	8946	#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /!< Back-to-back SETUP packets received /
Kojto	115:87f2f5183dfb	8947	#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /!< NYET interrupt /
Kojto	115:87f2f5183dfb	8948
Kojto	115:87f2f5183dfb	8949	/****************** Bit definition for USB_OTG_DOEPTSIZ register ******************/
Kojto	115:87f2f5183dfb	8950	#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
Kojto	115:87f2f5183dfb	8951	#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
Kojto	115:87f2f5183dfb	8952
Kojto	115:87f2f5183dfb	8953	#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /!< SETUP packet count /
Kojto	115:87f2f5183dfb	8954	#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8955	#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8956
Kojto	115:87f2f5183dfb	8957	/****************** Bit definition for PCGCCTL register ******************/
Kojto	115:87f2f5183dfb	8958	#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /!< SETUP packet count /
Kojto	115:87f2f5183dfb	8959	#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /!<Bit 0 /
Kojto	115:87f2f5183dfb	8960	#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /!<Bit 1 /
Kojto	115:87f2f5183dfb	8961
Kojto	115:87f2f5183dfb	8962	/**
Kojto	115:87f2f5183dfb	8963	* @}
Kojto	115:87f2f5183dfb	8964	*/
Kojto	115:87f2f5183dfb	8965
Kojto	115:87f2f5183dfb	8966	/**
Kojto	115:87f2f5183dfb	8967	* @}
Kojto	115:87f2f5183dfb	8968	*/
Kojto	115:87f2f5183dfb	8969
Kojto	115:87f2f5183dfb	8970	/** @addtogroup Exported_macros
Kojto	115:87f2f5183dfb	8971	* @{
Kojto	115:87f2f5183dfb	8972	*/
Kojto	115:87f2f5183dfb	8973
Kojto	115:87f2f5183dfb	8974	/***************************** ADC Instances ******************************/
Kojto	115:87f2f5183dfb	8975	#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) \|\| \
Kojto	115:87f2f5183dfb	8976	((__INSTANCE__) == ADC2) \|\| \
Kojto	115:87f2f5183dfb	8977	((__INSTANCE__) == ADC3))
Kojto	115:87f2f5183dfb	8978
Kojto	115:87f2f5183dfb	8979	/***************************** CAN Instances ******************************/
Kojto	115:87f2f5183dfb	8980	#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) \|\| \
Kojto	115:87f2f5183dfb	8981	((__INSTANCE__) == CAN2))
Kojto	115:87f2f5183dfb	8982
Kojto	115:87f2f5183dfb	8983	/***************************** CRC Instances ******************************/
Kojto	115:87f2f5183dfb	8984	#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
Kojto	115:87f2f5183dfb	8985
Kojto	115:87f2f5183dfb	8986	/***************************** DAC Instances ******************************/
Kojto	115:87f2f5183dfb	8987	#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
Kojto	115:87f2f5183dfb	8988
Kojto	115:87f2f5183dfb	8989	/***************************** DCMI Instances *****************************/
Kojto	115:87f2f5183dfb	8990	#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
Kojto	115:87f2f5183dfb	8991
Kojto	115:87f2f5183dfb	8992	/***************************** DMA2D Instances *****************************/
Kojto	115:87f2f5183dfb	8993	#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
Kojto	115:87f2f5183dfb	8994
Kojto	115:87f2f5183dfb	8995	/****************************** DMA Instances *****************************/
Kojto	115:87f2f5183dfb	8996	#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) \|\| \
Kojto	115:87f2f5183dfb	8997	((__INSTANCE__) == DMA1_Stream1) \|\| \
Kojto	115:87f2f5183dfb	8998	((__INSTANCE__) == DMA1_Stream2) \|\| \
Kojto	115:87f2f5183dfb	8999	((__INSTANCE__) == DMA1_Stream3) \|\| \
Kojto	115:87f2f5183dfb	9000	((__INSTANCE__) == DMA1_Stream4) \|\| \
Kojto	115:87f2f5183dfb	9001	((__INSTANCE__) == DMA1_Stream5) \|\| \
Kojto	115:87f2f5183dfb	9002	((__INSTANCE__) == DMA1_Stream6) \|\| \
Kojto	115:87f2f5183dfb	9003	((__INSTANCE__) == DMA1_Stream7) \|\| \
Kojto	115:87f2f5183dfb	9004	((__INSTANCE__) == DMA2_Stream0) \|\| \
Kojto	115:87f2f5183dfb	9005	((__INSTANCE__) == DMA2_Stream1) \|\| \
Kojto	115:87f2f5183dfb	9006	((__INSTANCE__) == DMA2_Stream2) \|\| \
Kojto	115:87f2f5183dfb	9007	((__INSTANCE__) == DMA2_Stream3) \|\| \
Kojto	115:87f2f5183dfb	9008	((__INSTANCE__) == DMA2_Stream4) \|\| \
Kojto	115:87f2f5183dfb	9009	((__INSTANCE__) == DMA2_Stream5) \|\| \
Kojto	115:87f2f5183dfb	9010	((__INSTANCE__) == DMA2_Stream6) \|\| \
Kojto	115:87f2f5183dfb	9011	((__INSTANCE__) == DMA2_Stream7))
Kojto	115:87f2f5183dfb	9012
Kojto	115:87f2f5183dfb	9013	/***************************** GPIO Instances *****************************/
Kojto	115:87f2f5183dfb	9014	#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) \|\| \
Kojto	115:87f2f5183dfb	9015	((__INSTANCE__) == GPIOB) \|\| \
Kojto	115:87f2f5183dfb	9016	((__INSTANCE__) == GPIOC) \|\| \
Kojto	115:87f2f5183dfb	9017	((__INSTANCE__) == GPIOD) \|\| \
Kojto	115:87f2f5183dfb	9018	((__INSTANCE__) == GPIOE) \|\| \
Kojto	115:87f2f5183dfb	9019	((__INSTANCE__) == GPIOF) \|\| \
Kojto	115:87f2f5183dfb	9020	((__INSTANCE__) == GPIOG) \|\| \
Kojto	115:87f2f5183dfb	9021	((__INSTANCE__) == GPIOH) \|\| \
Kojto	115:87f2f5183dfb	9022	((__INSTANCE__) == GPIOI) \|\| \
Kojto	115:87f2f5183dfb	9023	((__INSTANCE__) == GPIOJ) \|\| \
Kojto	115:87f2f5183dfb	9024	((__INSTANCE__) == GPIOK))
Kojto	115:87f2f5183dfb	9025
Kojto	115:87f2f5183dfb	9026	#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) \|\| \
Kojto	115:87f2f5183dfb	9027	((__INSTANCE__) == GPIOB) \|\| \
Kojto	115:87f2f5183dfb	9028	((__INSTANCE__) == GPIOC) \|\| \
Kojto	115:87f2f5183dfb	9029	((__INSTANCE__) == GPIOD) \|\| \
Kojto	115:87f2f5183dfb	9030	((__INSTANCE__) == GPIOE) \|\| \
Kojto	115:87f2f5183dfb	9031	((__INSTANCE__) == GPIOF) \|\| \
Kojto	115:87f2f5183dfb	9032	((__INSTANCE__) == GPIOG) \|\| \
Kojto	115:87f2f5183dfb	9033	((__INSTANCE__) == GPIOH) \|\| \
Kojto	115:87f2f5183dfb	9034	((__INSTANCE__) == GPIOI) \|\| \
Kojto	115:87f2f5183dfb	9035	((__INSTANCE__) == GPIOJ) \|\| \
Kojto	115:87f2f5183dfb	9036	((__INSTANCE__) == GPIOK))
Kojto	115:87f2f5183dfb	9037
Kojto	115:87f2f5183dfb	9038	/**************************** CEC Instances *******************************/
Kojto	115:87f2f5183dfb	9039	#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
Kojto	115:87f2f5183dfb	9040
Kojto	115:87f2f5183dfb	9041	/**************************** QSPI Instances *******************************/
Kojto	115:87f2f5183dfb	9042	#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
Kojto	115:87f2f5183dfb	9043
Kojto	115:87f2f5183dfb	9044
Kojto	115:87f2f5183dfb	9045	/****************************** I2C Instances *****************************/
Kojto	115:87f2f5183dfb	9046	#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) \|\| \
Kojto	115:87f2f5183dfb	9047	((__INSTANCE__) == I2C2) \|\| \
Kojto	115:87f2f5183dfb	9048	((__INSTANCE__) == I2C3) \|\| \
Kojto	115:87f2f5183dfb	9049	((__INSTANCE__) == I2C4))
Kojto	115:87f2f5183dfb	9050
Kojto	115:87f2f5183dfb	9051	/****************************** I2S Instances *****************************/
Kojto	115:87f2f5183dfb	9052	#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) \|\| \
Kojto	115:87f2f5183dfb	9053	((__INSTANCE__) == SPI2) \|\| \
Kojto	115:87f2f5183dfb	9054	((__INSTANCE__) == SPI3))
Kojto	115:87f2f5183dfb	9055
Kojto	115:87f2f5183dfb	9056	/***************************** LPTIM Instances ******************************/
Kojto	115:87f2f5183dfb	9057	#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
Kojto	115:87f2f5183dfb	9058
Kojto	115:87f2f5183dfb	9059	/**************************** LTDC Instances ******************************/
Kojto	115:87f2f5183dfb	9060	#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
Kojto	115:87f2f5183dfb	9061
Kojto	115:87f2f5183dfb	9062	/***************************** RNG Instances ******************************/
Kojto	115:87f2f5183dfb	9063	#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
Kojto	115:87f2f5183dfb	9064
Kojto	115:87f2f5183dfb	9065	/**************************** RTC Instances *******************************/
Kojto	115:87f2f5183dfb	9066	#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
Kojto	115:87f2f5183dfb	9067
Kojto	115:87f2f5183dfb	9068	/***************************** SAI Instances ******************************/
Kojto	115:87f2f5183dfb	9069	#define IS_SAI_BLOCK_PERIPH(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) \|\| \
Kojto	115:87f2f5183dfb	9070	((__PERIPH__) == SAI1_Block_B) \|\| \
Kojto	115:87f2f5183dfb	9071	((__PERIPH__) == SAI2_Block_A) \|\| \
Kojto	115:87f2f5183dfb	9072	((__PERIPH__) == SAI2_Block_B))
Kojto	115:87f2f5183dfb	9073
Kojto	115:87f2f5183dfb	9074
Kojto	115:87f2f5183dfb	9075	/****************************** SDMMC Instances *****************************/
Kojto	115:87f2f5183dfb	9076	#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
Kojto	115:87f2f5183dfb	9077
Kojto	115:87f2f5183dfb	9078
Kojto	115:87f2f5183dfb	9079	/**************************** SPDIFRX Instances *******************************/
Kojto	115:87f2f5183dfb	9080	#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
Kojto	115:87f2f5183dfb	9081
Kojto	115:87f2f5183dfb	9082	/****************************** SPI Instances *****************************/
Kojto	115:87f2f5183dfb	9083	#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) \|\| \
Kojto	115:87f2f5183dfb	9084	((__INSTANCE__) == SPI2) \|\| \
Kojto	115:87f2f5183dfb	9085	((__INSTANCE__) == SPI3) \|\| \
Kojto	115:87f2f5183dfb	9086	((__INSTANCE__) == SPI4) \|\| \
Kojto	115:87f2f5183dfb	9087	((__INSTANCE__) == SPI5) \|\| \
Kojto	115:87f2f5183dfb	9088	((__INSTANCE__) == SPI6))
Kojto	115:87f2f5183dfb	9089
Kojto	115:87f2f5183dfb	9090	/**************** TIM Instances : All supported instances *****************/
Kojto	115:87f2f5183dfb	9091	#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9092	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9093	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9094	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9095	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9096	((__INSTANCE__) == TIM6) \|\| \
Kojto	115:87f2f5183dfb	9097	((__INSTANCE__) == TIM7) \|\| \
Kojto	115:87f2f5183dfb	9098	((__INSTANCE__) == TIM8) \|\| \
Kojto	115:87f2f5183dfb	9099	((__INSTANCE__) == TIM9) \|\| \
Kojto	115:87f2f5183dfb	9100	((__INSTANCE__) == TIM10) \|\| \
Kojto	115:87f2f5183dfb	9101	((__INSTANCE__) == TIM11) \|\| \
Kojto	115:87f2f5183dfb	9102	((__INSTANCE__) == TIM12) \|\| \
Kojto	115:87f2f5183dfb	9103	((__INSTANCE__) == TIM13) \|\| \
Kojto	115:87f2f5183dfb	9104	((__INSTANCE__) == TIM14))
Kojto	115:87f2f5183dfb	9105
Kojto	115:87f2f5183dfb	9106	/*********** TIM Instances : at least 1 capture/compare channel ***********/
Kojto	115:87f2f5183dfb	9107	#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9108	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9109	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9110	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9111	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9112	((__INSTANCE__) == TIM8) \|\| \
Kojto	115:87f2f5183dfb	9113	((__INSTANCE__) == TIM9) \|\| \
Kojto	115:87f2f5183dfb	9114	((__INSTANCE__) == TIM10) \|\| \
Kojto	115:87f2f5183dfb	9115	((__INSTANCE__) == TIM11) \|\| \
Kojto	115:87f2f5183dfb	9116	((__INSTANCE__) == TIM12) \|\| \
Kojto	115:87f2f5183dfb	9117	((__INSTANCE__) == TIM13) \|\| \
Kojto	115:87f2f5183dfb	9118	((__INSTANCE__) == TIM14))
Kojto	115:87f2f5183dfb	9119
Kojto	115:87f2f5183dfb	9120	/********** TIM Instances : at least 2 capture/compare channels ***********/
Kojto	115:87f2f5183dfb	9121	#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9122	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9123	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9124	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9125	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9126	((__INSTANCE__) == TIM8) \|\| \
Kojto	115:87f2f5183dfb	9127	((__INSTANCE__) == TIM9) \|\| \
Kojto	115:87f2f5183dfb	9128	((__INSTANCE__) == TIM12))
Kojto	115:87f2f5183dfb	9129
Kojto	115:87f2f5183dfb	9130	/********** TIM Instances : at least 3 capture/compare channels ***********/
Kojto	115:87f2f5183dfb	9131	#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9132	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9133	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9134	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9135	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9136	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9137
Kojto	115:87f2f5183dfb	9138	/********** TIM Instances : at least 4 capture/compare channels ***********/
Kojto	115:87f2f5183dfb	9139	#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9140	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9141	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9142	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9143	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9144	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9145
Kojto	115:87f2f5183dfb	9146	/**************** TIM Instances : supporting combined 3-phase PWM mode ****/
Kojto	115:87f2f5183dfb	9147	#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
Kojto	115:87f2f5183dfb	9148	(((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9149	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9150
Kojto	115:87f2f5183dfb	9151	/**************** TIM Instances : supporting OCxREF clear *****************/
Kojto	115:87f2f5183dfb	9152	#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
Kojto	115:87f2f5183dfb	9153	(((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9154	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9155	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9156	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9157	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9158
Kojto	115:87f2f5183dfb	9159	/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
Kojto	115:87f2f5183dfb	9160	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
Kojto	115:87f2f5183dfb	9161	(((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9162	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9163	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9164	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9165	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9166	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9167
Kojto	115:87f2f5183dfb	9168	/**************** TIM Instances : supporting internal trigger inputs(ITRX) *****/
Kojto	115:87f2f5183dfb	9169	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
Kojto	115:87f2f5183dfb	9170	(((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9171	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9172	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9173	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9174	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9175	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9176	/**************** TIM Instances : at least 5 capture/compare channels *****/
Kojto	115:87f2f5183dfb	9177	#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
Kojto	115:87f2f5183dfb	9178	(((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9179	((__INSTANCE__) == TIM8) )
Kojto	115:87f2f5183dfb	9180
Kojto	115:87f2f5183dfb	9181	/**************** TIM Instances : at least 6 capture/compare channels *****/
Kojto	115:87f2f5183dfb	9182	#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
Kojto	115:87f2f5183dfb	9183	(((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9184	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9185
Kojto	115:87f2f5183dfb	9186
Kojto	115:87f2f5183dfb	9187	/****************** TIM Instances : Advanced-control timers ***************/
Kojto	115:87f2f5183dfb	9188	#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9189	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9190
Kojto	115:87f2f5183dfb	9191	/**************** TIM Instances : supporting 2 break inputs ***************/
Kojto	115:87f2f5183dfb	9192	#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
Kojto	115:87f2f5183dfb	9193	(((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9194	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9195
Kojto	115:87f2f5183dfb	9196	/***************** TIM Instances : Timer input XOR function ***************/
Kojto	115:87f2f5183dfb	9197	#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9198	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9199	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9200	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9201	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9202	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9203
Kojto	115:87f2f5183dfb	9204	/**************** TIM Instances : DMA requests generation (UDE) ***********/
Kojto	115:87f2f5183dfb	9205	#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9206	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9207	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9208	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9209	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9210	((__INSTANCE__) == TIM6) \|\| \
Kojto	115:87f2f5183dfb	9211	((__INSTANCE__) == TIM7) \|\| \
Kojto	115:87f2f5183dfb	9212	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9213
Kojto	115:87f2f5183dfb	9214	/********** TIM Instances : DMA requests generation (CCxDE) ***************/
Kojto	115:87f2f5183dfb	9215	#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9216	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9217	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9218	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9219	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9220	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9221
Kojto	115:87f2f5183dfb	9222	/********** TIM Instances : DMA requests generation (COMDE) ***************/
Kojto	115:87f2f5183dfb	9223	#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9224	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9225	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9226	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9227	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9228	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9229
Kojto	115:87f2f5183dfb	9230	/****************** TIM Instances : DMA burst feature *********************/
Kojto	115:87f2f5183dfb	9231	#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9232	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9233	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9234	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9235	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9236	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9237
Kojto	115:87f2f5183dfb	9238	/**** TIM Instances : master mode available (TIMx_CR2.MMS available )******/
Kojto	115:87f2f5183dfb	9239	#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9240	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9241	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9242	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9243	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9244	((__INSTANCE__) == TIM6) \|\| \
Kojto	115:87f2f5183dfb	9245	((__INSTANCE__) == TIM7) \|\| \
Kojto	115:87f2f5183dfb	9246	((__INSTANCE__) == TIM8) \|\| \
Kojto	115:87f2f5183dfb	9247	((__INSTANCE__) == TIM13) \|\| \
Kojto	115:87f2f5183dfb	9248	((__INSTANCE__) == TIM14))
Kojto	115:87f2f5183dfb	9249
Kojto	115:87f2f5183dfb	9250	/********* TIM Instances : Slave mode available (TIMx_SMCR available )*****/
Kojto	115:87f2f5183dfb	9251	#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9252	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9253	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9254	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9255	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9256	((__INSTANCE__) == TIM8) \|\| \
Kojto	115:87f2f5183dfb	9257	((__INSTANCE__) == TIM9) \|\| \
Kojto	115:87f2f5183dfb	9258	((__INSTANCE__) == TIM12))
Kojto	115:87f2f5183dfb	9259
Kojto	115:87f2f5183dfb	9260	/******************** TIM Instances : 32 bit Counter **********************/
Kojto	115:87f2f5183dfb	9261	#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9262	((__INSTANCE__) == TIM5))
Kojto	115:87f2f5183dfb	9263
Kojto	115:87f2f5183dfb	9264	/*************** TIM Instances : external trigger input available **********/
Kojto	115:87f2f5183dfb	9265	#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9266	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9267	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9268	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9269	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9270	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9271
Kojto	115:87f2f5183dfb	9272	/**************** TIM Instances : remapping capability ********************/
Kojto	115:87f2f5183dfb	9273	#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9274	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9275	((__INSTANCE__) == TIM11))
Kojto	115:87f2f5183dfb	9276
Kojto	115:87f2f5183dfb	9277	/***************** TIM Instances : output(s) available ********************/
Kojto	115:87f2f5183dfb	9278	#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
Kojto	115:87f2f5183dfb	9279	((((__INSTANCE__) == TIM1) && \
Kojto	115:87f2f5183dfb	9280	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	115:87f2f5183dfb	9281	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	115:87f2f5183dfb	9282	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
Kojto	115:87f2f5183dfb	9283	((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto	115:87f2f5183dfb	9284	\|\| \
Kojto	115:87f2f5183dfb	9285	(((__INSTANCE__) == TIM2) && \
Kojto	115:87f2f5183dfb	9286	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	115:87f2f5183dfb	9287	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	115:87f2f5183dfb	9288	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
Kojto	115:87f2f5183dfb	9289	((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto	115:87f2f5183dfb	9290	\|\| \
Kojto	115:87f2f5183dfb	9291	(((__INSTANCE__) == TIM3) && \
Kojto	115:87f2f5183dfb	9292	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	115:87f2f5183dfb	9293	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	115:87f2f5183dfb	9294	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
Kojto	115:87f2f5183dfb	9295	((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto	115:87f2f5183dfb	9296	\|\| \
Kojto	115:87f2f5183dfb	9297	(((__INSTANCE__) == TIM4) && \
Kojto	115:87f2f5183dfb	9298	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	115:87f2f5183dfb	9299	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	115:87f2f5183dfb	9300	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
Kojto	115:87f2f5183dfb	9301	((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto	115:87f2f5183dfb	9302	\|\| \
Kojto	115:87f2f5183dfb	9303	(((__INSTANCE__) == TIM5) && \
Kojto	115:87f2f5183dfb	9304	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	115:87f2f5183dfb	9305	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	115:87f2f5183dfb	9306	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
Kojto	115:87f2f5183dfb	9307	((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto	115:87f2f5183dfb	9308	\|\| \
Kojto	115:87f2f5183dfb	9309	(((__INSTANCE__) == TIM8) && \
Kojto	115:87f2f5183dfb	9310	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	115:87f2f5183dfb	9311	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	115:87f2f5183dfb	9312	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
Kojto	115:87f2f5183dfb	9313	((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto	115:87f2f5183dfb	9314	\|\| \
Kojto	115:87f2f5183dfb	9315	(((__INSTANCE__) == TIM9) && \
Kojto	115:87f2f5183dfb	9316	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	115:87f2f5183dfb	9317	((__CHANNEL__) == TIM_CHANNEL_2))) \
Kojto	115:87f2f5183dfb	9318	\|\| \
Kojto	115:87f2f5183dfb	9319	(((__INSTANCE__) == TIM10) && \
Kojto	115:87f2f5183dfb	9320	(((__CHANNEL__) == TIM_CHANNEL_1))) \
Kojto	115:87f2f5183dfb	9321	\|\| \
Kojto	115:87f2f5183dfb	9322	(((__INSTANCE__) == TIM11) && \
Kojto	115:87f2f5183dfb	9323	(((__CHANNEL__) == TIM_CHANNEL_1))) \
Kojto	115:87f2f5183dfb	9324	\|\| \
Kojto	115:87f2f5183dfb	9325	(((__INSTANCE__) == TIM12) && \
Kojto	115:87f2f5183dfb	9326	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	115:87f2f5183dfb	9327	((__CHANNEL__) == TIM_CHANNEL_2))) \
Kojto	115:87f2f5183dfb	9328	\|\| \
Kojto	115:87f2f5183dfb	9329	(((__INSTANCE__) == TIM13) && \
Kojto	115:87f2f5183dfb	9330	(((__CHANNEL__) == TIM_CHANNEL_1))) \
Kojto	115:87f2f5183dfb	9331	\|\| \
Kojto	115:87f2f5183dfb	9332	(((__INSTANCE__) == TIM14) && \
Kojto	115:87f2f5183dfb	9333	(((__CHANNEL__) == TIM_CHANNEL_1))))
Kojto	115:87f2f5183dfb	9334
Kojto	115:87f2f5183dfb	9335	/********** TIM Instances : complementary output(s) available *************/
Kojto	115:87f2f5183dfb	9336	#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
Kojto	115:87f2f5183dfb	9337	((((__INSTANCE__) == TIM1) && \
Kojto	115:87f2f5183dfb	9338	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	115:87f2f5183dfb	9339	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	115:87f2f5183dfb	9340	((__CHANNEL__) == TIM_CHANNEL_3))) \
Kojto	115:87f2f5183dfb	9341	\|\| \
Kojto	115:87f2f5183dfb	9342	(((__INSTANCE__) == TIM8) && \
Kojto	115:87f2f5183dfb	9343	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	115:87f2f5183dfb	9344	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	115:87f2f5183dfb	9345	((__CHANNEL__) == TIM_CHANNEL_3))))
Kojto	115:87f2f5183dfb	9346
Kojto	115:87f2f5183dfb	9347	/**************** TIM Instances : supporting ADC triggering through TRGO2 */
Kojto	115:87f2f5183dfb	9348	#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
Kojto	115:87f2f5183dfb	9349	(((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9350	((__INSTANCE__) == TIM8) )
Kojto	115:87f2f5183dfb	9351
Kojto	115:87f2f5183dfb	9352	/**************** TIM Instances : supporting synchronization **************/
Kojto	115:87f2f5183dfb	9353	#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
Kojto	115:87f2f5183dfb	9354	(((__INSTANCE__) == TIM1) \|\| \
Kojto	115:87f2f5183dfb	9355	((__INSTANCE__) == TIM2) \|\| \
Kojto	115:87f2f5183dfb	9356	((__INSTANCE__) == TIM3) \|\| \
Kojto	115:87f2f5183dfb	9357	((__INSTANCE__) == TIM4) \|\| \
Kojto	115:87f2f5183dfb	9358	((__INSTANCE__) == TIM5) \|\| \
Kojto	115:87f2f5183dfb	9359	((__INSTANCE__) == TIM6) \|\| \
Kojto	115:87f2f5183dfb	9360	((__INSTANCE__) == TIM7) \|\| \
Kojto	115:87f2f5183dfb	9361	((__INSTANCE__) == TIM8))
Kojto	115:87f2f5183dfb	9362
Kojto	115:87f2f5183dfb	9363	/****************** USART Instances : Synchronous mode ********************/
Kojto	115:87f2f5183dfb	9364	#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
Kojto	115:87f2f5183dfb	9365	((__INSTANCE__) == USART2) \|\| \
Kojto	115:87f2f5183dfb	9366	((__INSTANCE__) == USART3) \|\| \
Kojto	115:87f2f5183dfb	9367	((__INSTANCE__) == USART6))
Kojto	115:87f2f5183dfb	9368
Kojto	115:87f2f5183dfb	9369	/****************** UART Instances : Asynchronous mode ********************/
Kojto	115:87f2f5183dfb	9370	#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
Kojto	115:87f2f5183dfb	9371	((__INSTANCE__) == USART2) \|\| \
Kojto	115:87f2f5183dfb	9372	((__INSTANCE__) == USART3) \|\| \
Kojto	115:87f2f5183dfb	9373	((__INSTANCE__) == UART4) \|\| \
Kojto	115:87f2f5183dfb	9374	((__INSTANCE__) == UART5) \|\| \
Kojto	115:87f2f5183dfb	9375	((__INSTANCE__) == USART6) \|\| \
Kojto	115:87f2f5183dfb	9376	((__INSTANCE__) == UART7) \|\| \
Kojto	115:87f2f5183dfb	9377	((__INSTANCE__) == UART8))
Kojto	115:87f2f5183dfb	9378
Kojto	115:87f2f5183dfb	9379	/**************** UART Instances : Hardware Flow control ******************/
Kojto	115:87f2f5183dfb	9380	#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
Kojto	115:87f2f5183dfb	9381	((__INSTANCE__) == USART2) \|\| \
Kojto	115:87f2f5183dfb	9382	((__INSTANCE__) == USART3) \|\| \
Kojto	115:87f2f5183dfb	9383	((__INSTANCE__) == UART4) \|\| \
Kojto	115:87f2f5183dfb	9384	((__INSTANCE__) == UART5) \|\| \
Kojto	115:87f2f5183dfb	9385	((__INSTANCE__) == USART6) \|\| \
Kojto	115:87f2f5183dfb	9386	((__INSTANCE__) == UART7) \|\| \
Kojto	115:87f2f5183dfb	9387	((__INSTANCE__) == UART8))
Kojto	115:87f2f5183dfb	9388
Kojto	115:87f2f5183dfb	9389	/******************* UART Instances : Smart card mode *********************/
Kojto	115:87f2f5183dfb	9390	#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
Kojto	115:87f2f5183dfb	9391	((__INSTANCE__) == USART2) \|\| \
Kojto	115:87f2f5183dfb	9392	((__INSTANCE__) == USART3) \|\| \
Kojto	115:87f2f5183dfb	9393	((__INSTANCE__) == USART6))
Kojto	115:87f2f5183dfb	9394
Kojto	115:87f2f5183dfb	9395	/********************* UART Instances : IRDA mode *************************/
Kojto	115:87f2f5183dfb	9396	#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
Kojto	115:87f2f5183dfb	9397	((__INSTANCE__) == USART2) \|\| \
Kojto	115:87f2f5183dfb	9398	((__INSTANCE__) == USART3) \|\| \
Kojto	115:87f2f5183dfb	9399	((__INSTANCE__) == UART4) \|\| \
Kojto	115:87f2f5183dfb	9400	((__INSTANCE__) == UART5) \|\| \
Kojto	115:87f2f5183dfb	9401	((__INSTANCE__) == USART6) \|\| \
Kojto	115:87f2f5183dfb	9402	((__INSTANCE__) == UART7) \|\| \
Kojto	115:87f2f5183dfb	9403	((__INSTANCE__) == UART8))
Kojto	115:87f2f5183dfb	9404
Kojto	115:87f2f5183dfb	9405	/**************************** IWDG Instances ******************************/
Kojto	115:87f2f5183dfb	9406	#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
Kojto	115:87f2f5183dfb	9407
Kojto	115:87f2f5183dfb	9408	/**************************** WWDG Instances ******************************/
Kojto	115:87f2f5183dfb	9409	#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
Kojto	115:87f2f5183dfb	9410
Kojto	115:87f2f5183dfb	9411
Kojto	115:87f2f5183dfb	9412	/******************************************************************************/
Kojto	115:87f2f5183dfb	9413	/* For a painless codes migration between the STM32F7xx device product */
Kojto	115:87f2f5183dfb	9414	/* lines, the aliases defined below are put in place to overcome the */
Kojto	115:87f2f5183dfb	9415	/* differences in the interrupt handlers and IRQn definitions. */
Kojto	115:87f2f5183dfb	9416	/* No need to update developed interrupt code when moving across */
Kojto	115:87f2f5183dfb	9417	/* product lines within the same STM32F7 Family */
Kojto	115:87f2f5183dfb	9418	/******************************************************************************/
Kojto	115:87f2f5183dfb	9419
Kojto	115:87f2f5183dfb	9420	/* Aliases for __IRQn */
Kojto	115:87f2f5183dfb	9421	#define HASH_RNG_IRQn RNG_IRQn
Kojto	115:87f2f5183dfb	9422
Kojto	115:87f2f5183dfb	9423	/* Aliases for __IRQHandler */
Kojto	115:87f2f5183dfb	9424	#define HASH_RNG_IRQHandler RNG_IRQHandler
Kojto	115:87f2f5183dfb	9425
Kojto	115:87f2f5183dfb	9426	/**
Kojto	115:87f2f5183dfb	9427	* @}
Kojto	115:87f2f5183dfb	9428	*/
Kojto	115:87f2f5183dfb	9429
Kojto	115:87f2f5183dfb	9430	/**
Kojto	115:87f2f5183dfb	9431	* @}
Kojto	115:87f2f5183dfb	9432	*/
Kojto	115:87f2f5183dfb	9433
Kojto	115:87f2f5183dfb	9434	/**
Kojto	115:87f2f5183dfb	9435	* @}
Kojto	115:87f2f5183dfb	9436	*/
Kojto	115:87f2f5183dfb	9437
Kojto	115:87f2f5183dfb	9438	#ifdef __cplusplus
Kojto	115:87f2f5183dfb	9439	}
Kojto	115:87f2f5183dfb	9440	#endif /* __cplusplus */
Kojto	115:87f2f5183dfb	9441
Kojto	115:87f2f5183dfb	9442	#endif /* __STM32F746xx_H */
Kojto	115:87f2f5183dfb	9443
Kojto	115:87f2f5183dfb	9444
Kojto	115:87f2f5183dfb	9445	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F746ZG/stm32f746xx.h@115:87f2f5183dfb, 2016-03-02 (annotated)

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