Elijah Orr / mbed-renbed

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Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

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TARGET_WIZwiki_W7500/W7500x_crg.h@101:7cff1c4259d7, 2015-06-09 (annotated)

Committer:
Kojto
Date:
Tue Jun 09 14:29:26 2015 +0100
Revision:
101:7cff1c4259d7
Release 101 of the mbed library



Changes:

- new platform: APPNEARME_MICRONFCBOARD, MTS_DRAGONFLY_F411RE, MAX32600MBED, WIZwiki_W7500

- Silabs memory optimization in gpio, pwm fixes

- SPI  - ssel documentation fixes and its use

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /**
Kojto 101:7cff1c4259d7 2 ******************************************************************************
Kojto 101:7cff1c4259d7 3 * @file
Kojto 101:7cff1c4259d7 4 * @author
Kojto 101:7cff1c4259d7 5 * @version
Kojto 101:7cff1c4259d7 6 * @date
Kojto 101:7cff1c4259d7 7 * @brief This file contains all the functions prototypes for the Clock Reset Generator
Kojto 101:7cff1c4259d7 8 * firmware library.
Kojto 101:7cff1c4259d7 9 ******************************************************************************
Kojto 101:7cff1c4259d7 10 *
Kojto 101:7cff1c4259d7 11 ******************************************************************************
Kojto 101:7cff1c4259d7 12 */
Kojto 101:7cff1c4259d7 13
Kojto 101:7cff1c4259d7 14 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 101:7cff1c4259d7 15 #ifndef __W7500X_CRG_H
Kojto 101:7cff1c4259d7 16 #define __W7500X_CRG_H
Kojto 101:7cff1c4259d7 17
Kojto 101:7cff1c4259d7 18 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 19 extern "C" {
Kojto 101:7cff1c4259d7 20 #endif
Kojto 101:7cff1c4259d7 21
Kojto 101:7cff1c4259d7 22 /* Includes ------------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 23 #include "W7500x.h"
Kojto 101:7cff1c4259d7 24
Kojto 101:7cff1c4259d7 25 // It will be in W7500x_crg.h
Kojto 101:7cff1c4259d7 26 typedef enum { CRG_CLK_DIS = 0, CRG_MCLK, CRG_RCLK, CRG_OCLK } CRG_CLK_SOURCE;
Kojto 101:7cff1c4259d7 27 typedef enum { CRG_CLK_HIGH = 0, CRG_CLK_LOW } CRG_CLK_LOW_SOURCE;
Kojto 101:7cff1c4259d7 28 typedef enum { CRG_PREDIV1 = 0, CRG_PREDIV2, CRG_PREDIV4, CRG_PREDIV8, CRG_PREDIV16, \
Kojto 101:7cff1c4259d7 29 CRG_PREDIV32, CRG_PREDIV64, CRG_PREDIV128 } CRG_PREDIV;
Kojto 101:7cff1c4259d7 30 typedef enum { CRG_TIMER0 = 0, CRG_TIMER1 } CRG_TIMER;
Kojto 101:7cff1c4259d7 31 typedef enum { CRG_PWM0 = 0, CRG_PWM1, CRG_PWM2, CRG_PWM3, CRG_PWM4, CRG_PWM5, CRG_PWM6, CRG_PWM7 } CRG_PWM;
Kojto 101:7cff1c4259d7 32
Kojto 101:7cff1c4259d7 33
Kojto 101:7cff1c4259d7 34
Kojto 101:7cff1c4259d7 35 #define IS_CRG_PLL_SRC(SRC) (((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
Kojto 101:7cff1c4259d7 36 #define IS_CRG_FCLK_SRC(SRC) (((SRC) == CRG_MCLK) || ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
Kojto 101:7cff1c4259d7 37
Kojto 101:7cff1c4259d7 38 #define CRG_CLK_SRC_DEFAULT(SRC) (((SRC) == CRG_CLK_DIS) || ((SRC) == CRG_MCLK) || \
Kojto 101:7cff1c4259d7 39 ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
Kojto 101:7cff1c4259d7 40 #define CRG_CLK_SRC_LOW(SRC) (((SRC) == CRG_CLK_HIGH) || ((SRC) == CRG_CLK_LOW))
Kojto 101:7cff1c4259d7 41
Kojto 101:7cff1c4259d7 42 #define CRG_CLK_PREDIV_DEFAULT(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \
Kojto 101:7cff1c4259d7 43 ((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8))
Kojto 101:7cff1c4259d7 44 #define CRG_CLK_PREDIV_ADVANCE(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \
Kojto 101:7cff1c4259d7 45 ((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8) || \
Kojto 101:7cff1c4259d7 46 ((DIV) == CRG_PREDIV16) || ((DIV) == CRG_PREDIV32) || \
Kojto 101:7cff1c4259d7 47 ((DIV) == CRG_PREDIV64) || ((DIV) == CRG_PREDIV128))
Kojto 101:7cff1c4259d7 48
Kojto 101:7cff1c4259d7 49
Kojto 101:7cff1c4259d7 50 #define IS_CRG_FCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
Kojto 101:7cff1c4259d7 51
Kojto 101:7cff1c4259d7 52 #define IS_CRG_SSPCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
Kojto 101:7cff1c4259d7 53 #define IS_CRG_SSPCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
Kojto 101:7cff1c4259d7 54
Kojto 101:7cff1c4259d7 55 #define IS_CRG_ADCCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
Kojto 101:7cff1c4259d7 56 #define IS_CRG_ADCCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
Kojto 101:7cff1c4259d7 57
Kojto 101:7cff1c4259d7 58
Kojto 101:7cff1c4259d7 59
Kojto 101:7cff1c4259d7 60
Kojto 101:7cff1c4259d7 61
Kojto 101:7cff1c4259d7 62 #define IS_CRG_TIMERCLK_NUM(NUM) (((NUM) == CRG_TIMER0) || ((NUM) == CRG_TIMER1))
Kojto 101:7cff1c4259d7 63 #define IS_CRG_TIMERCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
Kojto 101:7cff1c4259d7 64 #define IS_CRG_TIMERCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
Kojto 101:7cff1c4259d7 65
Kojto 101:7cff1c4259d7 66 #define CRG_SET_TIMERCLK_SSR(NUM,VALUE) \
Kojto 101:7cff1c4259d7 67 (*((volatile uint32_t *)(CRG->TIMER0CLK_SSR) + (0x10ul * NUM)) = VALUE)
Kojto 101:7cff1c4259d7 68 #define CRG_SET_TIMERCLK_PREDIV(NUM,VALUE) \
Kojto 101:7cff1c4259d7 69 (*((volatile uint32_t *)(CRG->TIMER0CLK_PVSR) + (0x10ul * NUM)) = VALUE)
Kojto 101:7cff1c4259d7 70 //#define CRG_SET_TIMERCLK_SSR(num,value) CRG->TIMER##num##CLK_SSR = value
Kojto 101:7cff1c4259d7 71 //#define CRG_SET_TIMERCLK_PREDIV(num,value) CRG->TIMER##num##CLK_PVSR = value
Kojto 101:7cff1c4259d7 72
Kojto 101:7cff1c4259d7 73
Kojto 101:7cff1c4259d7 74 #define IS_CRG_PWMCLK_NUM(NUM) (((NUM) == CRG_PWM0) || ((NUM) == CRG_PWM1) || \
Kojto 101:7cff1c4259d7 75 ((NUM) == CRG_PWM2) || ((NUM) == CRG_PWM3) || \
Kojto 101:7cff1c4259d7 76 ((NUM) == CRG_PWM4) || ((NUM) == CRG_PWM5) || \
Kojto 101:7cff1c4259d7 77 ((NUM) == CRG_PWM6) || ((NUM) == CRG_PWM7) )
Kojto 101:7cff1c4259d7 78 #define IS_CRG_PWMCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
Kojto 101:7cff1c4259d7 79 #define IS_CRG_PWMCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
Kojto 101:7cff1c4259d7 80
Kojto 101:7cff1c4259d7 81 #define CRG_SET_PWMCLK_SSR(NUM,VALUE) \
Kojto 101:7cff1c4259d7 82 (*((volatile uint32_t *)(CRG->PWM0CLK_SSR) + (0x10ul * NUM)) = VALUE)
Kojto 101:7cff1c4259d7 83 #define CRG_SET_PWMCLK_PREDIV(NUM,VALUE) \
Kojto 101:7cff1c4259d7 84 (*((volatile uint32_t *)(CRG->PWM0CLK_PVSR) + (0x10ul * NUM)) = VALUE)
Kojto 101:7cff1c4259d7 85 //#define CRG_SET_PWMCLK_SSR(num,value) CRG->PWM##num##CLK_SSR = value
Kojto 101:7cff1c4259d7 86 //#define CRG_SET_PWMCLK_PREDIV(num,value) CRG->PWM##num##CLK_PVSR = value
Kojto 101:7cff1c4259d7 87
Kojto 101:7cff1c4259d7 88 #define IS_CRG_RTC_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
Kojto 101:7cff1c4259d7 89 #define IS_CRG_RTC_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
Kojto 101:7cff1c4259d7 90 #define IS_CRG_RTC_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC)
Kojto 101:7cff1c4259d7 91
Kojto 101:7cff1c4259d7 92 #define IS_CRG_WDOGCLK_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
Kojto 101:7cff1c4259d7 93 #define IS_CRG_WDOGCLK_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
Kojto 101:7cff1c4259d7 94 #define IS_CRG_WDOGCLK_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC)
Kojto 101:7cff1c4259d7 95
Kojto 101:7cff1c4259d7 96 #define IS_CRG_UARTCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
Kojto 101:7cff1c4259d7 97 #define IS_CRG_UARTCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
Kojto 101:7cff1c4259d7 98
Kojto 101:7cff1c4259d7 99 #define IS_CRG_MONCLK_SSR(value) (((value) >= 0x00ul) || ((value) <= 0x13ul))
Kojto 101:7cff1c4259d7 100
Kojto 101:7cff1c4259d7 101 void CRG_DeInit(void);
Kojto 101:7cff1c4259d7 102 void CRG_OSC_PowerDownEnable (FunctionalState NewState);
Kojto 101:7cff1c4259d7 103 void CRG_PLL_PowerDownEnable (FunctionalState NewState);
Kojto 101:7cff1c4259d7 104 void CRG_PLL_OutputEnable (FunctionalState NewState);
Kojto 101:7cff1c4259d7 105 void CRG_PLL_BypassEnable (FunctionalState NewState);
Kojto 101:7cff1c4259d7 106 void CRG_PLL_InputFrequencySelect (CRG_CLK_SOURCE src);
Kojto 101:7cff1c4259d7 107
Kojto 101:7cff1c4259d7 108 void CRG_FCLK_SourceSelect (CRG_CLK_SOURCE src);
Kojto 101:7cff1c4259d7 109 void CRG_FCLK_SetPrescale (CRG_PREDIV prediv);
Kojto 101:7cff1c4259d7 110
Kojto 101:7cff1c4259d7 111 void CRG_SSPCLK_SourceSelect (CRG_CLK_SOURCE src);
Kojto 101:7cff1c4259d7 112 void CRG_SSPCLK_SetPrescale (CRG_PREDIV prediv);
Kojto 101:7cff1c4259d7 113
Kojto 101:7cff1c4259d7 114 void CRG_ADCCLK_SourceSelect (CRG_CLK_SOURCE src);
Kojto 101:7cff1c4259d7 115 void CRG_ADCCLK_SetPrescale (CRG_PREDIV prediv);
Kojto 101:7cff1c4259d7 116
Kojto 101:7cff1c4259d7 117 void CRG_TIMERCLK_SourceSelect (CRG_TIMER num, CRG_CLK_SOURCE src);
Kojto 101:7cff1c4259d7 118 void CRG_TIMERCLK_SetPrescale (CRG_TIMER num, CRG_PREDIV prediv);
Kojto 101:7cff1c4259d7 119
Kojto 101:7cff1c4259d7 120 void CRG_PWMCLK_SourceSelect (CRG_PWM num, CRG_CLK_SOURCE src);
Kojto 101:7cff1c4259d7 121 void CRG_PWMCLK_SetPrescale (CRG_PWM num, CRG_PREDIV prediv);
Kojto 101:7cff1c4259d7 122
Kojto 101:7cff1c4259d7 123 void CRG_RTC_HS_SourceSelect (CRG_CLK_SOURCE src);
Kojto 101:7cff1c4259d7 124 void CRG_RTC_HS_SetPrescale (CRG_PREDIV prediv);
Kojto 101:7cff1c4259d7 125 void CRG_RTC_SourceSelect (CRG_CLK_LOW_SOURCE src);
Kojto 101:7cff1c4259d7 126
Kojto 101:7cff1c4259d7 127 void CRG_WDOGCLK_HS_SourceSelect (CRG_CLK_SOURCE src);
Kojto 101:7cff1c4259d7 128 void CRG_WDOGCLK_HS_SetPrescale (CRG_PREDIV prediv);
Kojto 101:7cff1c4259d7 129 void CRG_WDOGCLK_SourceSelect (CRG_CLK_LOW_SOURCE src);
Kojto 101:7cff1c4259d7 130
Kojto 101:7cff1c4259d7 131 void CRG_UARTCLK_SourceSelect (CRG_CLK_SOURCE src);
Kojto 101:7cff1c4259d7 132 void CRG_UARTCLK_SetPrescale (CRG_PREDIV prediv);
Kojto 101:7cff1c4259d7 133
Kojto 101:7cff1c4259d7 134 void CRG_MII_Enable (FunctionalState rx_clk, FunctionalState tx_clk);
Kojto 101:7cff1c4259d7 135
Kojto 101:7cff1c4259d7 136 void CRG_SetMonitoringClock (uint32_t value);
Kojto 101:7cff1c4259d7 137 uint32_t CRG_GetMonitoringClock (void);
Kojto 101:7cff1c4259d7 138
Kojto 101:7cff1c4259d7 139
Kojto 101:7cff1c4259d7 140 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 141 }
Kojto 101:7cff1c4259d7 142 #endif
Kojto 101:7cff1c4259d7 143
Kojto 101:7cff1c4259d7 144 #endif
Kojto 101:7cff1c4259d7 145