Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_SAMR21G18A/comp_gclk.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
111:4336505e4b1c 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for GCLK
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43
Kojto 111:4336505e4b1c 44 #ifndef _SAMR21_GCLK_COMPONENT_
Kojto 111:4336505e4b1c 45 #define _SAMR21_GCLK_COMPONENT_
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 /* ========================================================================== */
Kojto 111:4336505e4b1c 48 /** SOFTWARE API DEFINITION FOR GCLK */
Kojto 111:4336505e4b1c 49 /* ========================================================================== */
Kojto 111:4336505e4b1c 50 /** \addtogroup SAMR21_GCLK Generic Clock Generator */
Kojto 111:4336505e4b1c 51 /*@{*/
Kojto 111:4336505e4b1c 52
Kojto 111:4336505e4b1c 53 #define GCLK_U2102
Kojto 111:4336505e4b1c 54 #define REV_GCLK 0x210
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 /* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
Kojto 111:4336505e4b1c 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 58 typedef union {
Kojto 111:4336505e4b1c 59 struct {
Kojto 111:4336505e4b1c 60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 61 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 62 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 63 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 64 } GCLK_CTRL_Type;
Kojto 111:4336505e4b1c 65 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 66
Kojto 111:4336505e4b1c 67 #define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */
Kojto 111:4336505e4b1c 68 #define GCLK_CTRL_RESETVALUE 0x00ul /**< \brief (GCLK_CTRL reset_value) Control */
Kojto 111:4336505e4b1c 69
Kojto 111:4336505e4b1c 70 #define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */
Kojto 111:4336505e4b1c 71 #define GCLK_CTRL_SWRST (0x1ul << GCLK_CTRL_SWRST_Pos)
Kojto 111:4336505e4b1c 72 #define GCLK_CTRL_MASK 0x01ul /**< \brief (GCLK_CTRL) MASK Register */
Kojto 111:4336505e4b1c 73
Kojto 111:4336505e4b1c 74 /* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
Kojto 111:4336505e4b1c 75 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 76 typedef union {
Kojto 111:4336505e4b1c 77 struct {
Kojto 111:4336505e4b1c 78 uint8_t :7; /*!< bit: 0.. 6 Reserved */
Kojto 111:4336505e4b1c 79 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
Kojto 111:4336505e4b1c 80 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 81 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 82 } GCLK_STATUS_Type;
Kojto 111:4336505e4b1c 83 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 84
Kojto 111:4336505e4b1c 85 #define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */
Kojto 111:4336505e4b1c 86 #define GCLK_STATUS_RESETVALUE 0x00ul /**< \brief (GCLK_STATUS reset_value) Status */
Kojto 111:4336505e4b1c 87
Kojto 111:4336505e4b1c 88 #define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */
Kojto 111:4336505e4b1c 89 #define GCLK_STATUS_SYNCBUSY (0x1ul << GCLK_STATUS_SYNCBUSY_Pos)
Kojto 111:4336505e4b1c 90 #define GCLK_STATUS_MASK 0x80ul /**< \brief (GCLK_STATUS) MASK Register */
Kojto 111:4336505e4b1c 91
Kojto 111:4336505e4b1c 92 /* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
Kojto 111:4336505e4b1c 93 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 94 typedef union {
Kojto 111:4336505e4b1c 95 struct {
Kojto 111:4336505e4b1c 96 uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
Kojto 111:4336505e4b1c 97 uint16_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 98 uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
Kojto 111:4336505e4b1c 99 uint16_t :2; /*!< bit: 12..13 Reserved */
Kojto 111:4336505e4b1c 100 uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
Kojto 111:4336505e4b1c 101 uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
Kojto 111:4336505e4b1c 102 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 103 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 104 } GCLK_CLKCTRL_Type;
Kojto 111:4336505e4b1c 105 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 106
Kojto 111:4336505e4b1c 107 #define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
Kojto 111:4336505e4b1c 108 #define GCLK_CLKCTRL_RESETVALUE 0x0000ul /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
Kojto 111:4336505e4b1c 109
Kojto 111:4336505e4b1c 110 #define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
Kojto 111:4336505e4b1c 111 #define GCLK_CLKCTRL_ID_Msk (0x3Ful << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 112 #define GCLK_CLKCTRL_ID(value) (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
Kojto 111:4336505e4b1c 113 #define GCLK_CLKCTRL_ID_DFLL48_Val 0x0ul /**< \brief (GCLK_CLKCTRL) DFLL48 */
Kojto 111:4336505e4b1c 114 #define GCLK_CLKCTRL_ID_FDPLL_Val 0x1ul /**< \brief (GCLK_CLKCTRL) FDPLL */
Kojto 111:4336505e4b1c 115 #define GCLK_CLKCTRL_ID_FDPLL32K_Val 0x2ul /**< \brief (GCLK_CLKCTRL) FDPLL32K */
Kojto 111:4336505e4b1c 116 #define GCLK_CLKCTRL_ID_WDT_Val 0x3ul /**< \brief (GCLK_CLKCTRL) WDT */
Kojto 111:4336505e4b1c 117 #define GCLK_CLKCTRL_ID_RTC_Val 0x4ul /**< \brief (GCLK_CLKCTRL) RTC */
Kojto 111:4336505e4b1c 118 #define GCLK_CLKCTRL_ID_EIC_Val 0x5ul /**< \brief (GCLK_CLKCTRL) EIC */
Kojto 111:4336505e4b1c 119 #define GCLK_CLKCTRL_ID_USB_Val 0x6ul /**< \brief (GCLK_CLKCTRL) USB */
Kojto 111:4336505e4b1c 120 #define GCLK_CLKCTRL_ID_EVSYS_0_Val 0x7ul /**< \brief (GCLK_CLKCTRL) EVSYS_0 */
Kojto 111:4336505e4b1c 121 #define GCLK_CLKCTRL_ID_EVSYS_1_Val 0x8ul /**< \brief (GCLK_CLKCTRL) EVSYS_1 */
Kojto 111:4336505e4b1c 122 #define GCLK_CLKCTRL_ID_EVSYS_2_Val 0x9ul /**< \brief (GCLK_CLKCTRL) EVSYS_2 */
Kojto 111:4336505e4b1c 123 #define GCLK_CLKCTRL_ID_EVSYS_3_Val 0xAul /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
Kojto 111:4336505e4b1c 124 #define GCLK_CLKCTRL_ID_EVSYS_4_Val 0xBul /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
Kojto 111:4336505e4b1c 125 #define GCLK_CLKCTRL_ID_EVSYS_5_Val 0xCul /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
Kojto 111:4336505e4b1c 126 #define GCLK_CLKCTRL_ID_EVSYS_6_Val 0xDul /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
Kojto 111:4336505e4b1c 127 #define GCLK_CLKCTRL_ID_EVSYS_7_Val 0xEul /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
Kojto 111:4336505e4b1c 128 #define GCLK_CLKCTRL_ID_EVSYS_8_Val 0xFul /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
Kojto 111:4336505e4b1c 129 #define GCLK_CLKCTRL_ID_EVSYS_9_Val 0x10ul /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
Kojto 111:4336505e4b1c 130 #define GCLK_CLKCTRL_ID_EVSYS_10_Val 0x11ul /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
Kojto 111:4336505e4b1c 131 #define GCLK_CLKCTRL_ID_EVSYS_11_Val 0x12ul /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
Kojto 111:4336505e4b1c 132 #define GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
Kojto 111:4336505e4b1c 133 #define GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
Kojto 111:4336505e4b1c 134 #define GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
Kojto 111:4336505e4b1c 135 #define GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
Kojto 111:4336505e4b1c 136 #define GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
Kojto 111:4336505e4b1c 137 #define GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
Kojto 111:4336505e4b1c 138 #define GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
Kojto 111:4336505e4b1c 139 #define GCLK_CLKCTRL_ID_TCC0_TCC1_Val 0x1Aul /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
Kojto 111:4336505e4b1c 140 #define GCLK_CLKCTRL_ID_TCC2_TC3_Val 0x1Bul /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
Kojto 111:4336505e4b1c 141 #define GCLK_CLKCTRL_ID_TC4_TC5_Val 0x1Cul /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
Kojto 111:4336505e4b1c 142 #define GCLK_CLKCTRL_ID_TC6_TC7_Val 0x1Dul /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
Kojto 111:4336505e4b1c 143 #define GCLK_CLKCTRL_ID_ADC_Val 0x1Eul /**< \brief (GCLK_CLKCTRL) ADC */
Kojto 111:4336505e4b1c 144 #define GCLK_CLKCTRL_ID_AC_DIG_Val 0x1Ful /**< \brief (GCLK_CLKCTRL) AC_DIG */
Kojto 111:4336505e4b1c 145 #define GCLK_CLKCTRL_ID_AC_ANA_Val 0x20ul /**< \brief (GCLK_CLKCTRL) AC_ANA */
Kojto 111:4336505e4b1c 146 #define GCLK_CLKCTRL_ID_DAC_Val 0x21ul /**< \brief (GCLK_CLKCTRL) DAC */
Kojto 111:4336505e4b1c 147 #define GCLK_CLKCTRL_ID_PTC_Val 0x22ul /**< \brief (GCLK_CLKCTRL) PTC */
Kojto 111:4336505e4b1c 148 #define GCLK_CLKCTRL_ID_I2S_0_Val 0x23ul /**< \brief (GCLK_CLKCTRL) I2S_0 */
Kojto 111:4336505e4b1c 149 #define GCLK_CLKCTRL_ID_I2S_1_Val 0x24ul /**< \brief (GCLK_CLKCTRL) I2S_1 */
Kojto 111:4336505e4b1c 150 #define GCLK_CLKCTRL_ID_DFLL48 (GCLK_CLKCTRL_ID_DFLL48_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 151 #define GCLK_CLKCTRL_ID_FDPLL (GCLK_CLKCTRL_ID_FDPLL_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 152 #define GCLK_CLKCTRL_ID_FDPLL32K (GCLK_CLKCTRL_ID_FDPLL32K_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 153 #define GCLK_CLKCTRL_ID_WDT (GCLK_CLKCTRL_ID_WDT_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 154 #define GCLK_CLKCTRL_ID_RTC (GCLK_CLKCTRL_ID_RTC_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 155 #define GCLK_CLKCTRL_ID_EIC (GCLK_CLKCTRL_ID_EIC_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 156 #define GCLK_CLKCTRL_ID_USB (GCLK_CLKCTRL_ID_USB_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 157 #define GCLK_CLKCTRL_ID_EVSYS_0 (GCLK_CLKCTRL_ID_EVSYS_0_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 158 #define GCLK_CLKCTRL_ID_EVSYS_1 (GCLK_CLKCTRL_ID_EVSYS_1_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 159 #define GCLK_CLKCTRL_ID_EVSYS_2 (GCLK_CLKCTRL_ID_EVSYS_2_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 160 #define GCLK_CLKCTRL_ID_EVSYS_3 (GCLK_CLKCTRL_ID_EVSYS_3_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 161 #define GCLK_CLKCTRL_ID_EVSYS_4 (GCLK_CLKCTRL_ID_EVSYS_4_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 162 #define GCLK_CLKCTRL_ID_EVSYS_5 (GCLK_CLKCTRL_ID_EVSYS_5_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 163 #define GCLK_CLKCTRL_ID_EVSYS_6 (GCLK_CLKCTRL_ID_EVSYS_6_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 164 #define GCLK_CLKCTRL_ID_EVSYS_7 (GCLK_CLKCTRL_ID_EVSYS_7_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 165 #define GCLK_CLKCTRL_ID_EVSYS_8 (GCLK_CLKCTRL_ID_EVSYS_8_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 166 #define GCLK_CLKCTRL_ID_EVSYS_9 (GCLK_CLKCTRL_ID_EVSYS_9_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 167 #define GCLK_CLKCTRL_ID_EVSYS_10 (GCLK_CLKCTRL_ID_EVSYS_10_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 168 #define GCLK_CLKCTRL_ID_EVSYS_11 (GCLK_CLKCTRL_ID_EVSYS_11_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 169 #define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 170 #define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 171 #define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 172 #define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 173 #define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 174 #define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 175 #define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 176 #define GCLK_CLKCTRL_ID_TCC0_TCC1 (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 177 #define GCLK_CLKCTRL_ID_TCC2_TC3 (GCLK_CLKCTRL_ID_TCC2_TC3_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 178 #define GCLK_CLKCTRL_ID_TC4_TC5 (GCLK_CLKCTRL_ID_TC4_TC5_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 179 #define GCLK_CLKCTRL_ID_TC6_TC7 (GCLK_CLKCTRL_ID_TC6_TC7_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 180 #define GCLK_CLKCTRL_ID_ADC (GCLK_CLKCTRL_ID_ADC_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 181 #define GCLK_CLKCTRL_ID_AC_DIG (GCLK_CLKCTRL_ID_AC_DIG_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 182 #define GCLK_CLKCTRL_ID_AC_ANA (GCLK_CLKCTRL_ID_AC_ANA_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 183 #define GCLK_CLKCTRL_ID_DAC (GCLK_CLKCTRL_ID_DAC_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 184 #define GCLK_CLKCTRL_ID_PTC (GCLK_CLKCTRL_ID_PTC_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 185 #define GCLK_CLKCTRL_ID_I2S_0 (GCLK_CLKCTRL_ID_I2S_0_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 186 #define GCLK_CLKCTRL_ID_I2S_1 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos)
Kojto 111:4336505e4b1c 187 #define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
Kojto 111:4336505e4b1c 188 #define GCLK_CLKCTRL_GEN_Msk (0xFul << GCLK_CLKCTRL_GEN_Pos)
Kojto 111:4336505e4b1c 189 #define GCLK_CLKCTRL_GEN(value) (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
Kojto 111:4336505e4b1c 190 #define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
Kojto 111:4336505e4b1c 191 #define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
Kojto 111:4336505e4b1c 192 #define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
Kojto 111:4336505e4b1c 193 #define GCLK_CLKCTRL_GEN_GCLK3_Val 0x3ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
Kojto 111:4336505e4b1c 194 #define GCLK_CLKCTRL_GEN_GCLK4_Val 0x4ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
Kojto 111:4336505e4b1c 195 #define GCLK_CLKCTRL_GEN_GCLK5_Val 0x5ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
Kojto 111:4336505e4b1c 196 #define GCLK_CLKCTRL_GEN_GCLK6_Val 0x6ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
Kojto 111:4336505e4b1c 197 #define GCLK_CLKCTRL_GEN_GCLK7_Val 0x7ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
Kojto 111:4336505e4b1c 198 #define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos)
Kojto 111:4336505e4b1c 199 #define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos)
Kojto 111:4336505e4b1c 200 #define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos)
Kojto 111:4336505e4b1c 201 #define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos)
Kojto 111:4336505e4b1c 202 #define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos)
Kojto 111:4336505e4b1c 203 #define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos)
Kojto 111:4336505e4b1c 204 #define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos)
Kojto 111:4336505e4b1c 205 #define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos)
Kojto 111:4336505e4b1c 206 #define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */
Kojto 111:4336505e4b1c 207 #define GCLK_CLKCTRL_CLKEN (0x1ul << GCLK_CLKCTRL_CLKEN_Pos)
Kojto 111:4336505e4b1c 208 #define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */
Kojto 111:4336505e4b1c 209 #define GCLK_CLKCTRL_WRTLOCK (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos)
Kojto 111:4336505e4b1c 210 #define GCLK_CLKCTRL_MASK 0xCF3Ful /**< \brief (GCLK_CLKCTRL) MASK Register */
Kojto 111:4336505e4b1c 211
Kojto 111:4336505e4b1c 212 /* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
Kojto 111:4336505e4b1c 213 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 214 typedef union {
Kojto 111:4336505e4b1c 215 struct {
Kojto 111:4336505e4b1c 216 uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
Kojto 111:4336505e4b1c 217 uint32_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 218 uint32_t SRC:5; /*!< bit: 8..12 Source Select */
Kojto 111:4336505e4b1c 219 uint32_t :3; /*!< bit: 13..15 Reserved */
Kojto 111:4336505e4b1c 220 uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
Kojto 111:4336505e4b1c 221 uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
Kojto 111:4336505e4b1c 222 uint32_t OOV:1; /*!< bit: 18 Output Off Value */
Kojto 111:4336505e4b1c 223 uint32_t OE:1; /*!< bit: 19 Output Enable */
Kojto 111:4336505e4b1c 224 uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
Kojto 111:4336505e4b1c 225 uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
Kojto 111:4336505e4b1c 226 uint32_t :10; /*!< bit: 22..31 Reserved */
Kojto 111:4336505e4b1c 227 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 228 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 229 } GCLK_GENCTRL_Type;
Kojto 111:4336505e4b1c 230 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 231
Kojto 111:4336505e4b1c 232 #define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
Kojto 111:4336505e4b1c 233 #define GCLK_GENCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
Kojto 111:4336505e4b1c 234
Kojto 111:4336505e4b1c 235 #define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
Kojto 111:4336505e4b1c 236 #define GCLK_GENCTRL_ID_Msk (0xFul << GCLK_GENCTRL_ID_Pos)
Kojto 111:4336505e4b1c 237 #define GCLK_GENCTRL_ID(value) (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
Kojto 111:4336505e4b1c 238 #define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */
Kojto 111:4336505e4b1c 239 #define GCLK_GENCTRL_SRC_Msk (0x1Ful << GCLK_GENCTRL_SRC_Pos)
Kojto 111:4336505e4b1c 240 #define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
Kojto 111:4336505e4b1c 241 #define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
Kojto 111:4336505e4b1c 242 #define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */
Kojto 111:4336505e4b1c 243 #define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
Kojto 111:4336505e4b1c 244 #define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3ul /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
Kojto 111:4336505e4b1c 245 #define GCLK_GENCTRL_SRC_OSC32K_Val 0x4ul /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
Kojto 111:4336505e4b1c 246 #define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5ul /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
Kojto 111:4336505e4b1c 247 #define GCLK_GENCTRL_SRC_OSC8M_Val 0x6ul /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
Kojto 111:4336505e4b1c 248 #define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7ul /**< \brief (GCLK_GENCTRL) DFLL48M output */
Kojto 111:4336505e4b1c 249 #define GCLK_GENCTRL_SRC_FDPLL_Val 0x8ul /**< \brief (GCLK_GENCTRL) FDPLL output */
Kojto 111:4336505e4b1c 250 #define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
Kojto 111:4336505e4b1c 251 #define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
Kojto 111:4336505e4b1c 252 #define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
Kojto 111:4336505e4b1c 253 #define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
Kojto 111:4336505e4b1c 254 #define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos)
Kojto 111:4336505e4b1c 255 #define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
Kojto 111:4336505e4b1c 256 #define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos)
Kojto 111:4336505e4b1c 257 #define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos)
Kojto 111:4336505e4b1c 258 #define GCLK_GENCTRL_SRC_FDPLL (GCLK_GENCTRL_SRC_FDPLL_Val << GCLK_GENCTRL_SRC_Pos)
Kojto 111:4336505e4b1c 259 #define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
Kojto 111:4336505e4b1c 260 #define GCLK_GENCTRL_GENEN (0x1ul << GCLK_GENCTRL_GENEN_Pos)
Kojto 111:4336505e4b1c 261 #define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
Kojto 111:4336505e4b1c 262 #define GCLK_GENCTRL_IDC (0x1ul << GCLK_GENCTRL_IDC_Pos)
Kojto 111:4336505e4b1c 263 #define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */
Kojto 111:4336505e4b1c 264 #define GCLK_GENCTRL_OOV (0x1ul << GCLK_GENCTRL_OOV_Pos)
Kojto 111:4336505e4b1c 265 #define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */
Kojto 111:4336505e4b1c 266 #define GCLK_GENCTRL_OE (0x1ul << GCLK_GENCTRL_OE_Pos)
Kojto 111:4336505e4b1c 267 #define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */
Kojto 111:4336505e4b1c 268 #define GCLK_GENCTRL_DIVSEL (0x1ul << GCLK_GENCTRL_DIVSEL_Pos)
Kojto 111:4336505e4b1c 269 #define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */
Kojto 111:4336505e4b1c 270 #define GCLK_GENCTRL_RUNSTDBY (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 271 #define GCLK_GENCTRL_MASK 0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */
Kojto 111:4336505e4b1c 272
Kojto 111:4336505e4b1c 273 /* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
Kojto 111:4336505e4b1c 274 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 275 typedef union {
Kojto 111:4336505e4b1c 276 struct {
Kojto 111:4336505e4b1c 277 uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
Kojto 111:4336505e4b1c 278 uint32_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 279 uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
Kojto 111:4336505e4b1c 280 uint32_t :8; /*!< bit: 24..31 Reserved */
Kojto 111:4336505e4b1c 281 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 282 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 283 } GCLK_GENDIV_Type;
Kojto 111:4336505e4b1c 284 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 285
Kojto 111:4336505e4b1c 286 #define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
Kojto 111:4336505e4b1c 287 #define GCLK_GENDIV_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
Kojto 111:4336505e4b1c 288
Kojto 111:4336505e4b1c 289 #define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
Kojto 111:4336505e4b1c 290 #define GCLK_GENDIV_ID_Msk (0xFul << GCLK_GENDIV_ID_Pos)
Kojto 111:4336505e4b1c 291 #define GCLK_GENDIV_ID(value) (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
Kojto 111:4336505e4b1c 292 #define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */
Kojto 111:4336505e4b1c 293 #define GCLK_GENDIV_DIV_Msk (0xFFFFul << GCLK_GENDIV_DIV_Pos)
Kojto 111:4336505e4b1c 294 #define GCLK_GENDIV_DIV(value) (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
Kojto 111:4336505e4b1c 295 #define GCLK_GENDIV_MASK 0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */
Kojto 111:4336505e4b1c 296
Kojto 111:4336505e4b1c 297 /** \brief GCLK hardware registers */
Kojto 111:4336505e4b1c 298 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 299 typedef struct {
Kojto 111:4336505e4b1c 300 __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
Kojto 111:4336505e4b1c 301 __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
Kojto 111:4336505e4b1c 302 __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
Kojto 111:4336505e4b1c 303 __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
Kojto 111:4336505e4b1c 304 __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
Kojto 111:4336505e4b1c 305 } Gclk;
Kojto 111:4336505e4b1c 306 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 307
Kojto 111:4336505e4b1c 308 /*@}*/
Kojto 111:4336505e4b1c 309
Kojto 111:4336505e4b1c 310 #endif /* _SAMR21_GCLK_COMPONENT_ */