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TARGET_SAMR21G18A/comp_eic.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
111:4336505e4b1c 
.

Who changed what in which revision?

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Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for EIC
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43
Kojto 111:4336505e4b1c 44 #ifndef _SAMR21_EIC_COMPONENT_
Kojto 111:4336505e4b1c 45 #define _SAMR21_EIC_COMPONENT_
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 /* ========================================================================== */
Kojto 111:4336505e4b1c 48 /** SOFTWARE API DEFINITION FOR EIC */
Kojto 111:4336505e4b1c 49 /* ========================================================================== */
Kojto 111:4336505e4b1c 50 /** \addtogroup SAMR21_EIC External Interrupt Controller */
Kojto 111:4336505e4b1c 51 /*@{*/
Kojto 111:4336505e4b1c 52
Kojto 111:4336505e4b1c 53 #define EIC_U2217
Kojto 111:4336505e4b1c 54 #define REV_EIC 0x101
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 /* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
Kojto 111:4336505e4b1c 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 58 typedef union {
Kojto 111:4336505e4b1c 59 struct {
Kojto 111:4336505e4b1c 60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 61 uint8_t ENABLE:1; /*!< bit: 1 Enable */
Kojto 111:4336505e4b1c 62 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 63 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 64 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 65 } EIC_CTRL_Type;
Kojto 111:4336505e4b1c 66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 67
Kojto 111:4336505e4b1c 68 #define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control */
Kojto 111:4336505e4b1c 69 #define EIC_CTRL_RESETVALUE 0x00ul /**< \brief (EIC_CTRL reset_value) Control */
Kojto 111:4336505e4b1c 70
Kojto 111:4336505e4b1c 71 #define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */
Kojto 111:4336505e4b1c 72 #define EIC_CTRL_SWRST (0x1ul << EIC_CTRL_SWRST_Pos)
Kojto 111:4336505e4b1c 73 #define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */
Kojto 111:4336505e4b1c 74 #define EIC_CTRL_ENABLE (0x1ul << EIC_CTRL_ENABLE_Pos)
Kojto 111:4336505e4b1c 75 #define EIC_CTRL_MASK 0x03ul /**< \brief (EIC_CTRL) MASK Register */
Kojto 111:4336505e4b1c 76
Kojto 111:4336505e4b1c 77 /* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
Kojto 111:4336505e4b1c 78 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 79 typedef union {
Kojto 111:4336505e4b1c 80 struct {
Kojto 111:4336505e4b1c 81 uint8_t :7; /*!< bit: 0.. 6 Reserved */
Kojto 111:4336505e4b1c 82 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
Kojto 111:4336505e4b1c 83 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 84 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 85 } EIC_STATUS_Type;
Kojto 111:4336505e4b1c 86 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 87
Kojto 111:4336505e4b1c 88 #define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status */
Kojto 111:4336505e4b1c 89 #define EIC_STATUS_RESETVALUE 0x00ul /**< \brief (EIC_STATUS reset_value) Status */
Kojto 111:4336505e4b1c 90
Kojto 111:4336505e4b1c 91 #define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Synchronization Busy */
Kojto 111:4336505e4b1c 92 #define EIC_STATUS_SYNCBUSY (0x1ul << EIC_STATUS_SYNCBUSY_Pos)
Kojto 111:4336505e4b1c 93 #define EIC_STATUS_MASK 0x80ul /**< \brief (EIC_STATUS) MASK Register */
Kojto 111:4336505e4b1c 94
Kojto 111:4336505e4b1c 95 /* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
Kojto 111:4336505e4b1c 96 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 97 typedef union {
Kojto 111:4336505e4b1c 98 struct {
Kojto 111:4336505e4b1c 99 uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
Kojto 111:4336505e4b1c 100 uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
Kojto 111:4336505e4b1c 101 uint8_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 102 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 103 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 104 } EIC_NMICTRL_Type;
Kojto 111:4336505e4b1c 105 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 106
Kojto 111:4336505e4b1c 107 #define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
Kojto 111:4336505e4b1c 108 #define EIC_NMICTRL_RESETVALUE 0x00ul /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
Kojto 111:4336505e4b1c 109
Kojto 111:4336505e4b1c 110 #define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
Kojto 111:4336505e4b1c 111 #define EIC_NMICTRL_NMISENSE_Msk (0x7ul << EIC_NMICTRL_NMISENSE_Pos)
Kojto 111:4336505e4b1c 112 #define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
Kojto 111:4336505e4b1c 113 #define EIC_NMICTRL_NMISENSE_NONE_Val 0x0ul /**< \brief (EIC_NMICTRL) No detection */
Kojto 111:4336505e4b1c 114 #define EIC_NMICTRL_NMISENSE_RISE_Val 0x1ul /**< \brief (EIC_NMICTRL) Rising-edge detection */
Kojto 111:4336505e4b1c 115 #define EIC_NMICTRL_NMISENSE_FALL_Val 0x2ul /**< \brief (EIC_NMICTRL) Falling-edge detection */
Kojto 111:4336505e4b1c 116 #define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3ul /**< \brief (EIC_NMICTRL) Both-edges detection */
Kojto 111:4336505e4b1c 117 #define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4ul /**< \brief (EIC_NMICTRL) High-level detection */
Kojto 111:4336505e4b1c 118 #define EIC_NMICTRL_NMISENSE_LOW_Val 0x5ul /**< \brief (EIC_NMICTRL) Low-level detection */
Kojto 111:4336505e4b1c 119 #define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
Kojto 111:4336505e4b1c 120 #define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
Kojto 111:4336505e4b1c 121 #define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
Kojto 111:4336505e4b1c 122 #define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
Kojto 111:4336505e4b1c 123 #define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
Kojto 111:4336505e4b1c 124 #define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
Kojto 111:4336505e4b1c 125 #define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
Kojto 111:4336505e4b1c 126 #define EIC_NMICTRL_NMIFILTEN (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos)
Kojto 111:4336505e4b1c 127 #define EIC_NMICTRL_MASK 0x0Ful /**< \brief (EIC_NMICTRL) MASK Register */
Kojto 111:4336505e4b1c 128
Kojto 111:4336505e4b1c 129 /* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 130 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 131 typedef union {
Kojto 111:4336505e4b1c 132 struct {
Kojto 111:4336505e4b1c 133 uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
Kojto 111:4336505e4b1c 134 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 135 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 136 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 137 } EIC_NMIFLAG_Type;
Kojto 111:4336505e4b1c 138 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 139
Kojto 111:4336505e4b1c 140 #define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 141 #define EIC_NMIFLAG_RESETVALUE 0x00ul /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 142
Kojto 111:4336505e4b1c 143 #define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
Kojto 111:4336505e4b1c 144 #define EIC_NMIFLAG_NMI (0x1ul << EIC_NMIFLAG_NMI_Pos)
Kojto 111:4336505e4b1c 145 #define EIC_NMIFLAG_MASK 0x01ul /**< \brief (EIC_NMIFLAG) MASK Register */
Kojto 111:4336505e4b1c 146
Kojto 111:4336505e4b1c 147 /* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
Kojto 111:4336505e4b1c 148 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 149 typedef union {
Kojto 111:4336505e4b1c 150 struct {
Kojto 111:4336505e4b1c 151 uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
Kojto 111:4336505e4b1c 152 uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
Kojto 111:4336505e4b1c 153 uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
Kojto 111:4336505e4b1c 154 uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
Kojto 111:4336505e4b1c 155 uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
Kojto 111:4336505e4b1c 156 uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
Kojto 111:4336505e4b1c 157 uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
Kojto 111:4336505e4b1c 158 uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
Kojto 111:4336505e4b1c 159 uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
Kojto 111:4336505e4b1c 160 uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
Kojto 111:4336505e4b1c 161 uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
Kojto 111:4336505e4b1c 162 uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
Kojto 111:4336505e4b1c 163 uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
Kojto 111:4336505e4b1c 164 uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
Kojto 111:4336505e4b1c 165 uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
Kojto 111:4336505e4b1c 166 uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
Kojto 111:4336505e4b1c 167 uint32_t :16; /*!< bit: 16..31 Reserved */
Kojto 111:4336505e4b1c 168 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 169 struct {
Kojto 111:4336505e4b1c 170 uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
Kojto 111:4336505e4b1c 171 uint32_t :16; /*!< bit: 16..31 Reserved */
Kojto 111:4336505e4b1c 172 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 173 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 174 } EIC_EVCTRL_Type;
Kojto 111:4336505e4b1c 175 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 176
Kojto 111:4336505e4b1c 177 #define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control */
Kojto 111:4336505e4b1c 178 #define EIC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */
Kojto 111:4336505e4b1c 179
Kojto 111:4336505e4b1c 180 #define EIC_EVCTRL_EXTINTEO0_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
Kojto 111:4336505e4b1c 181 #define EIC_EVCTRL_EXTINTEO0 (1 << EIC_EVCTRL_EXTINTEO0_Pos)
Kojto 111:4336505e4b1c 182 #define EIC_EVCTRL_EXTINTEO1_Pos 1 /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
Kojto 111:4336505e4b1c 183 #define EIC_EVCTRL_EXTINTEO1 (1 << EIC_EVCTRL_EXTINTEO1_Pos)
Kojto 111:4336505e4b1c 184 #define EIC_EVCTRL_EXTINTEO2_Pos 2 /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
Kojto 111:4336505e4b1c 185 #define EIC_EVCTRL_EXTINTEO2 (1 << EIC_EVCTRL_EXTINTEO2_Pos)
Kojto 111:4336505e4b1c 186 #define EIC_EVCTRL_EXTINTEO3_Pos 3 /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
Kojto 111:4336505e4b1c 187 #define EIC_EVCTRL_EXTINTEO3 (1 << EIC_EVCTRL_EXTINTEO3_Pos)
Kojto 111:4336505e4b1c 188 #define EIC_EVCTRL_EXTINTEO4_Pos 4 /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
Kojto 111:4336505e4b1c 189 #define EIC_EVCTRL_EXTINTEO4 (1 << EIC_EVCTRL_EXTINTEO4_Pos)
Kojto 111:4336505e4b1c 190 #define EIC_EVCTRL_EXTINTEO5_Pos 5 /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
Kojto 111:4336505e4b1c 191 #define EIC_EVCTRL_EXTINTEO5 (1 << EIC_EVCTRL_EXTINTEO5_Pos)
Kojto 111:4336505e4b1c 192 #define EIC_EVCTRL_EXTINTEO6_Pos 6 /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
Kojto 111:4336505e4b1c 193 #define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos)
Kojto 111:4336505e4b1c 194 #define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
Kojto 111:4336505e4b1c 195 #define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos)
Kojto 111:4336505e4b1c 196 #define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
Kojto 111:4336505e4b1c 197 #define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos)
Kojto 111:4336505e4b1c 198 #define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
Kojto 111:4336505e4b1c 199 #define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos)
Kojto 111:4336505e4b1c 200 #define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
Kojto 111:4336505e4b1c 201 #define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos)
Kojto 111:4336505e4b1c 202 #define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
Kojto 111:4336505e4b1c 203 #define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos)
Kojto 111:4336505e4b1c 204 #define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
Kojto 111:4336505e4b1c 205 #define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos)
Kojto 111:4336505e4b1c 206 #define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
Kojto 111:4336505e4b1c 207 #define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos)
Kojto 111:4336505e4b1c 208 #define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
Kojto 111:4336505e4b1c 209 #define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos)
Kojto 111:4336505e4b1c 210 #define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
Kojto 111:4336505e4b1c 211 #define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos)
Kojto 111:4336505e4b1c 212 #define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
Kojto 111:4336505e4b1c 213 #define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos)
Kojto 111:4336505e4b1c 214 #define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
Kojto 111:4336505e4b1c 215 #define EIC_EVCTRL_MASK 0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */
Kojto 111:4336505e4b1c 216
Kojto 111:4336505e4b1c 217 /* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 218 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 219 typedef union {
Kojto 111:4336505e4b1c 220 struct {
Kojto 111:4336505e4b1c 221 uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
Kojto 111:4336505e4b1c 222 uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
Kojto 111:4336505e4b1c 223 uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
Kojto 111:4336505e4b1c 224 uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
Kojto 111:4336505e4b1c 225 uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
Kojto 111:4336505e4b1c 226 uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
Kojto 111:4336505e4b1c 227 uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
Kojto 111:4336505e4b1c 228 uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
Kojto 111:4336505e4b1c 229 uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
Kojto 111:4336505e4b1c 230 uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
Kojto 111:4336505e4b1c 231 uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
Kojto 111:4336505e4b1c 232 uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
Kojto 111:4336505e4b1c 233 uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
Kojto 111:4336505e4b1c 234 uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
Kojto 111:4336505e4b1c 235 uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
Kojto 111:4336505e4b1c 236 uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
Kojto 111:4336505e4b1c 237 uint32_t :16; /*!< bit: 16..31 Reserved */
Kojto 111:4336505e4b1c 238 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 239 struct {
Kojto 111:4336505e4b1c 240 uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
Kojto 111:4336505e4b1c 241 uint32_t :16; /*!< bit: 16..31 Reserved */
Kojto 111:4336505e4b1c 242 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 243 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 244 } EIC_INTENCLR_Type;
Kojto 111:4336505e4b1c 245 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 246
Kojto 111:4336505e4b1c 247 #define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 248 #define EIC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 249
Kojto 111:4336505e4b1c 250 #define EIC_INTENCLR_EXTINT0_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
Kojto 111:4336505e4b1c 251 #define EIC_INTENCLR_EXTINT0 (1 << EIC_INTENCLR_EXTINT0_Pos)
Kojto 111:4336505e4b1c 252 #define EIC_INTENCLR_EXTINT1_Pos 1 /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
Kojto 111:4336505e4b1c 253 #define EIC_INTENCLR_EXTINT1 (1 << EIC_INTENCLR_EXTINT1_Pos)
Kojto 111:4336505e4b1c 254 #define EIC_INTENCLR_EXTINT2_Pos 2 /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
Kojto 111:4336505e4b1c 255 #define EIC_INTENCLR_EXTINT2 (1 << EIC_INTENCLR_EXTINT2_Pos)
Kojto 111:4336505e4b1c 256 #define EIC_INTENCLR_EXTINT3_Pos 3 /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
Kojto 111:4336505e4b1c 257 #define EIC_INTENCLR_EXTINT3 (1 << EIC_INTENCLR_EXTINT3_Pos)
Kojto 111:4336505e4b1c 258 #define EIC_INTENCLR_EXTINT4_Pos 4 /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
Kojto 111:4336505e4b1c 259 #define EIC_INTENCLR_EXTINT4 (1 << EIC_INTENCLR_EXTINT4_Pos)
Kojto 111:4336505e4b1c 260 #define EIC_INTENCLR_EXTINT5_Pos 5 /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
Kojto 111:4336505e4b1c 261 #define EIC_INTENCLR_EXTINT5 (1 << EIC_INTENCLR_EXTINT5_Pos)
Kojto 111:4336505e4b1c 262 #define EIC_INTENCLR_EXTINT6_Pos 6 /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
Kojto 111:4336505e4b1c 263 #define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos)
Kojto 111:4336505e4b1c 264 #define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
Kojto 111:4336505e4b1c 265 #define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos)
Kojto 111:4336505e4b1c 266 #define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
Kojto 111:4336505e4b1c 267 #define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos)
Kojto 111:4336505e4b1c 268 #define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
Kojto 111:4336505e4b1c 269 #define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos)
Kojto 111:4336505e4b1c 270 #define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
Kojto 111:4336505e4b1c 271 #define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos)
Kojto 111:4336505e4b1c 272 #define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
Kojto 111:4336505e4b1c 273 #define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos)
Kojto 111:4336505e4b1c 274 #define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
Kojto 111:4336505e4b1c 275 #define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos)
Kojto 111:4336505e4b1c 276 #define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
Kojto 111:4336505e4b1c 277 #define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos)
Kojto 111:4336505e4b1c 278 #define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
Kojto 111:4336505e4b1c 279 #define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos)
Kojto 111:4336505e4b1c 280 #define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
Kojto 111:4336505e4b1c 281 #define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos)
Kojto 111:4336505e4b1c 282 #define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
Kojto 111:4336505e4b1c 283 #define EIC_INTENCLR_EXTINT_Msk (0xFFFFul << EIC_INTENCLR_EXTINT_Pos)
Kojto 111:4336505e4b1c 284 #define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
Kojto 111:4336505e4b1c 285 #define EIC_INTENCLR_MASK 0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 286
Kojto 111:4336505e4b1c 287 /* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 288 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 289 typedef union {
Kojto 111:4336505e4b1c 290 struct {
Kojto 111:4336505e4b1c 291 uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
Kojto 111:4336505e4b1c 292 uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
Kojto 111:4336505e4b1c 293 uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
Kojto 111:4336505e4b1c 294 uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
Kojto 111:4336505e4b1c 295 uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
Kojto 111:4336505e4b1c 296 uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
Kojto 111:4336505e4b1c 297 uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
Kojto 111:4336505e4b1c 298 uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
Kojto 111:4336505e4b1c 299 uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
Kojto 111:4336505e4b1c 300 uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
Kojto 111:4336505e4b1c 301 uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
Kojto 111:4336505e4b1c 302 uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
Kojto 111:4336505e4b1c 303 uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
Kojto 111:4336505e4b1c 304 uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
Kojto 111:4336505e4b1c 305 uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
Kojto 111:4336505e4b1c 306 uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
Kojto 111:4336505e4b1c 307 uint32_t :16; /*!< bit: 16..31 Reserved */
Kojto 111:4336505e4b1c 308 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 309 struct {
Kojto 111:4336505e4b1c 310 uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
Kojto 111:4336505e4b1c 311 uint32_t :16; /*!< bit: 16..31 Reserved */
Kojto 111:4336505e4b1c 312 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 313 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 314 } EIC_INTENSET_Type;
Kojto 111:4336505e4b1c 315 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 316
Kojto 111:4336505e4b1c 317 #define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
Kojto 111:4336505e4b1c 318 #define EIC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
Kojto 111:4336505e4b1c 319
Kojto 111:4336505e4b1c 320 #define EIC_INTENSET_EXTINT0_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
Kojto 111:4336505e4b1c 321 #define EIC_INTENSET_EXTINT0 (1 << EIC_INTENSET_EXTINT0_Pos)
Kojto 111:4336505e4b1c 322 #define EIC_INTENSET_EXTINT1_Pos 1 /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
Kojto 111:4336505e4b1c 323 #define EIC_INTENSET_EXTINT1 (1 << EIC_INTENSET_EXTINT1_Pos)
Kojto 111:4336505e4b1c 324 #define EIC_INTENSET_EXTINT2_Pos 2 /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
Kojto 111:4336505e4b1c 325 #define EIC_INTENSET_EXTINT2 (1 << EIC_INTENSET_EXTINT2_Pos)
Kojto 111:4336505e4b1c 326 #define EIC_INTENSET_EXTINT3_Pos 3 /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
Kojto 111:4336505e4b1c 327 #define EIC_INTENSET_EXTINT3 (1 << EIC_INTENSET_EXTINT3_Pos)
Kojto 111:4336505e4b1c 328 #define EIC_INTENSET_EXTINT4_Pos 4 /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
Kojto 111:4336505e4b1c 329 #define EIC_INTENSET_EXTINT4 (1 << EIC_INTENSET_EXTINT4_Pos)
Kojto 111:4336505e4b1c 330 #define EIC_INTENSET_EXTINT5_Pos 5 /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
Kojto 111:4336505e4b1c 331 #define EIC_INTENSET_EXTINT5 (1 << EIC_INTENSET_EXTINT5_Pos)
Kojto 111:4336505e4b1c 332 #define EIC_INTENSET_EXTINT6_Pos 6 /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
Kojto 111:4336505e4b1c 333 #define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos)
Kojto 111:4336505e4b1c 334 #define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
Kojto 111:4336505e4b1c 335 #define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos)
Kojto 111:4336505e4b1c 336 #define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
Kojto 111:4336505e4b1c 337 #define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos)
Kojto 111:4336505e4b1c 338 #define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
Kojto 111:4336505e4b1c 339 #define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos)
Kojto 111:4336505e4b1c 340 #define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
Kojto 111:4336505e4b1c 341 #define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos)
Kojto 111:4336505e4b1c 342 #define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
Kojto 111:4336505e4b1c 343 #define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos)
Kojto 111:4336505e4b1c 344 #define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
Kojto 111:4336505e4b1c 345 #define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos)
Kojto 111:4336505e4b1c 346 #define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
Kojto 111:4336505e4b1c 347 #define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos)
Kojto 111:4336505e4b1c 348 #define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
Kojto 111:4336505e4b1c 349 #define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos)
Kojto 111:4336505e4b1c 350 #define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
Kojto 111:4336505e4b1c 351 #define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos)
Kojto 111:4336505e4b1c 352 #define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */
Kojto 111:4336505e4b1c 353 #define EIC_INTENSET_EXTINT_Msk (0xFFFFul << EIC_INTENSET_EXTINT_Pos)
Kojto 111:4336505e4b1c 354 #define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
Kojto 111:4336505e4b1c 355 #define EIC_INTENSET_MASK 0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 356
Kojto 111:4336505e4b1c 357 /* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 358 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 359 typedef union { // __I to avoid read-modify-write on write-to-clear register
Kojto 111:4336505e4b1c 360 struct {
Kojto 111:4336505e4b1c 361 __I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
Kojto 111:4336505e4b1c 362 __I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
Kojto 111:4336505e4b1c 363 __I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
Kojto 111:4336505e4b1c 364 __I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
Kojto 111:4336505e4b1c 365 __I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
Kojto 111:4336505e4b1c 366 __I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
Kojto 111:4336505e4b1c 367 __I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
Kojto 111:4336505e4b1c 368 __I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
Kojto 111:4336505e4b1c 369 __I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
Kojto 111:4336505e4b1c 370 __I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
Kojto 111:4336505e4b1c 371 __I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
Kojto 111:4336505e4b1c 372 __I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
Kojto 111:4336505e4b1c 373 __I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
Kojto 111:4336505e4b1c 374 __I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
Kojto 111:4336505e4b1c 375 __I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
Kojto 111:4336505e4b1c 376 __I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
Kojto 111:4336505e4b1c 377 __I uint32_t :16; /*!< bit: 16..31 Reserved */
Kojto 111:4336505e4b1c 378 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 379 struct {
Kojto 111:4336505e4b1c 380 __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
Kojto 111:4336505e4b1c 381 __I uint32_t :16; /*!< bit: 16..31 Reserved */
Kojto 111:4336505e4b1c 382 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 383 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 384 } EIC_INTFLAG_Type;
Kojto 111:4336505e4b1c 385 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 386
Kojto 111:4336505e4b1c 387 #define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 388 #define EIC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 389
Kojto 111:4336505e4b1c 390 #define EIC_INTFLAG_EXTINT0_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt 0 */
Kojto 111:4336505e4b1c 391 #define EIC_INTFLAG_EXTINT0 (1 << EIC_INTFLAG_EXTINT0_Pos)
Kojto 111:4336505e4b1c 392 #define EIC_INTFLAG_EXTINT1_Pos 1 /**< \brief (EIC_INTFLAG) External Interrupt 1 */
Kojto 111:4336505e4b1c 393 #define EIC_INTFLAG_EXTINT1 (1 << EIC_INTFLAG_EXTINT1_Pos)
Kojto 111:4336505e4b1c 394 #define EIC_INTFLAG_EXTINT2_Pos 2 /**< \brief (EIC_INTFLAG) External Interrupt 2 */
Kojto 111:4336505e4b1c 395 #define EIC_INTFLAG_EXTINT2 (1 << EIC_INTFLAG_EXTINT2_Pos)
Kojto 111:4336505e4b1c 396 #define EIC_INTFLAG_EXTINT3_Pos 3 /**< \brief (EIC_INTFLAG) External Interrupt 3 */
Kojto 111:4336505e4b1c 397 #define EIC_INTFLAG_EXTINT3 (1 << EIC_INTFLAG_EXTINT3_Pos)
Kojto 111:4336505e4b1c 398 #define EIC_INTFLAG_EXTINT4_Pos 4 /**< \brief (EIC_INTFLAG) External Interrupt 4 */
Kojto 111:4336505e4b1c 399 #define EIC_INTFLAG_EXTINT4 (1 << EIC_INTFLAG_EXTINT4_Pos)
Kojto 111:4336505e4b1c 400 #define EIC_INTFLAG_EXTINT5_Pos 5 /**< \brief (EIC_INTFLAG) External Interrupt 5 */
Kojto 111:4336505e4b1c 401 #define EIC_INTFLAG_EXTINT5 (1 << EIC_INTFLAG_EXTINT5_Pos)
Kojto 111:4336505e4b1c 402 #define EIC_INTFLAG_EXTINT6_Pos 6 /**< \brief (EIC_INTFLAG) External Interrupt 6 */
Kojto 111:4336505e4b1c 403 #define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos)
Kojto 111:4336505e4b1c 404 #define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */
Kojto 111:4336505e4b1c 405 #define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos)
Kojto 111:4336505e4b1c 406 #define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */
Kojto 111:4336505e4b1c 407 #define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos)
Kojto 111:4336505e4b1c 408 #define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */
Kojto 111:4336505e4b1c 409 #define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos)
Kojto 111:4336505e4b1c 410 #define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */
Kojto 111:4336505e4b1c 411 #define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos)
Kojto 111:4336505e4b1c 412 #define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */
Kojto 111:4336505e4b1c 413 #define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos)
Kojto 111:4336505e4b1c 414 #define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */
Kojto 111:4336505e4b1c 415 #define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos)
Kojto 111:4336505e4b1c 416 #define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */
Kojto 111:4336505e4b1c 417 #define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos)
Kojto 111:4336505e4b1c 418 #define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */
Kojto 111:4336505e4b1c 419 #define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos)
Kojto 111:4336505e4b1c 420 #define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */
Kojto 111:4336505e4b1c 421 #define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos)
Kojto 111:4336505e4b1c 422 #define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */
Kojto 111:4336505e4b1c 423 #define EIC_INTFLAG_EXTINT_Msk (0xFFFFul << EIC_INTFLAG_EXTINT_Pos)
Kojto 111:4336505e4b1c 424 #define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
Kojto 111:4336505e4b1c 425 #define EIC_INTFLAG_MASK 0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 426
Kojto 111:4336505e4b1c 427 /* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
Kojto 111:4336505e4b1c 428 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 429 typedef union {
Kojto 111:4336505e4b1c 430 struct {
Kojto 111:4336505e4b1c 431 uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
Kojto 111:4336505e4b1c 432 uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
Kojto 111:4336505e4b1c 433 uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
Kojto 111:4336505e4b1c 434 uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
Kojto 111:4336505e4b1c 435 uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
Kojto 111:4336505e4b1c 436 uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
Kojto 111:4336505e4b1c 437 uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
Kojto 111:4336505e4b1c 438 uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
Kojto 111:4336505e4b1c 439 uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
Kojto 111:4336505e4b1c 440 uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
Kojto 111:4336505e4b1c 441 uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
Kojto 111:4336505e4b1c 442 uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
Kojto 111:4336505e4b1c 443 uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
Kojto 111:4336505e4b1c 444 uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
Kojto 111:4336505e4b1c 445 uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
Kojto 111:4336505e4b1c 446 uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
Kojto 111:4336505e4b1c 447 uint32_t :16; /*!< bit: 16..31 Reserved */
Kojto 111:4336505e4b1c 448 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 449 struct {
Kojto 111:4336505e4b1c 450 uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
Kojto 111:4336505e4b1c 451 uint32_t :16; /*!< bit: 16..31 Reserved */
Kojto 111:4336505e4b1c 452 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 453 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 454 } EIC_WAKEUP_Type;
Kojto 111:4336505e4b1c 455 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 456
Kojto 111:4336505e4b1c 457 #define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
Kojto 111:4336505e4b1c 458 #define EIC_WAKEUP_RESETVALUE 0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
Kojto 111:4336505e4b1c 459
Kojto 111:4336505e4b1c 460 #define EIC_WAKEUP_WAKEUPEN0_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
Kojto 111:4336505e4b1c 461 #define EIC_WAKEUP_WAKEUPEN0 (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
Kojto 111:4336505e4b1c 462 #define EIC_WAKEUP_WAKEUPEN1_Pos 1 /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
Kojto 111:4336505e4b1c 463 #define EIC_WAKEUP_WAKEUPEN1 (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
Kojto 111:4336505e4b1c 464 #define EIC_WAKEUP_WAKEUPEN2_Pos 2 /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
Kojto 111:4336505e4b1c 465 #define EIC_WAKEUP_WAKEUPEN2 (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
Kojto 111:4336505e4b1c 466 #define EIC_WAKEUP_WAKEUPEN3_Pos 3 /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
Kojto 111:4336505e4b1c 467 #define EIC_WAKEUP_WAKEUPEN3 (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
Kojto 111:4336505e4b1c 468 #define EIC_WAKEUP_WAKEUPEN4_Pos 4 /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
Kojto 111:4336505e4b1c 469 #define EIC_WAKEUP_WAKEUPEN4 (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
Kojto 111:4336505e4b1c 470 #define EIC_WAKEUP_WAKEUPEN5_Pos 5 /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
Kojto 111:4336505e4b1c 471 #define EIC_WAKEUP_WAKEUPEN5 (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
Kojto 111:4336505e4b1c 472 #define EIC_WAKEUP_WAKEUPEN6_Pos 6 /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
Kojto 111:4336505e4b1c 473 #define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
Kojto 111:4336505e4b1c 474 #define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
Kojto 111:4336505e4b1c 475 #define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
Kojto 111:4336505e4b1c 476 #define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
Kojto 111:4336505e4b1c 477 #define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
Kojto 111:4336505e4b1c 478 #define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
Kojto 111:4336505e4b1c 479 #define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
Kojto 111:4336505e4b1c 480 #define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
Kojto 111:4336505e4b1c 481 #define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
Kojto 111:4336505e4b1c 482 #define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
Kojto 111:4336505e4b1c 483 #define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
Kojto 111:4336505e4b1c 484 #define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
Kojto 111:4336505e4b1c 485 #define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
Kojto 111:4336505e4b1c 486 #define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
Kojto 111:4336505e4b1c 487 #define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
Kojto 111:4336505e4b1c 488 #define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
Kojto 111:4336505e4b1c 489 #define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
Kojto 111:4336505e4b1c 490 #define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
Kojto 111:4336505e4b1c 491 #define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
Kojto 111:4336505e4b1c 492 #define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
Kojto 111:4336505e4b1c 493 #define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos)
Kojto 111:4336505e4b1c 494 #define EIC_WAKEUP_WAKEUPEN(value) (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))
Kojto 111:4336505e4b1c 495 #define EIC_WAKEUP_MASK 0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */
Kojto 111:4336505e4b1c 496
Kojto 111:4336505e4b1c 497 /* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
Kojto 111:4336505e4b1c 498 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 499 typedef union {
Kojto 111:4336505e4b1c 500 struct {
Kojto 111:4336505e4b1c 501 uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
Kojto 111:4336505e4b1c 502 uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
Kojto 111:4336505e4b1c 503 uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
Kojto 111:4336505e4b1c 504 uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
Kojto 111:4336505e4b1c 505 uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
Kojto 111:4336505e4b1c 506 uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
Kojto 111:4336505e4b1c 507 uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
Kojto 111:4336505e4b1c 508 uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
Kojto 111:4336505e4b1c 509 uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
Kojto 111:4336505e4b1c 510 uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
Kojto 111:4336505e4b1c 511 uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
Kojto 111:4336505e4b1c 512 uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
Kojto 111:4336505e4b1c 513 uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
Kojto 111:4336505e4b1c 514 uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
Kojto 111:4336505e4b1c 515 uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
Kojto 111:4336505e4b1c 516 uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
Kojto 111:4336505e4b1c 517 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 518 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 519 } EIC_CONFIG_Type;
Kojto 111:4336505e4b1c 520 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 521
Kojto 111:4336505e4b1c 522 #define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Configuration n */
Kojto 111:4336505e4b1c 523 #define EIC_CONFIG_RESETVALUE 0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */
Kojto 111:4336505e4b1c 524
Kojto 111:4336505e4b1c 525 #define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
Kojto 111:4336505e4b1c 526 #define EIC_CONFIG_SENSE0_Msk (0x7ul << EIC_CONFIG_SENSE0_Pos)
Kojto 111:4336505e4b1c 527 #define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
Kojto 111:4336505e4b1c 528 #define EIC_CONFIG_SENSE0_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
Kojto 111:4336505e4b1c 529 #define EIC_CONFIG_SENSE0_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising-edge detection */
Kojto 111:4336505e4b1c 530 #define EIC_CONFIG_SENSE0_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling-edge detection */
Kojto 111:4336505e4b1c 531 #define EIC_CONFIG_SENSE0_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both-edges detection */
Kojto 111:4336505e4b1c 532 #define EIC_CONFIG_SENSE0_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High-level detection */
Kojto 111:4336505e4b1c 533 #define EIC_CONFIG_SENSE0_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low-level detection */
Kojto 111:4336505e4b1c 534 #define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
Kojto 111:4336505e4b1c 535 #define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
Kojto 111:4336505e4b1c 536 #define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
Kojto 111:4336505e4b1c 537 #define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
Kojto 111:4336505e4b1c 538 #define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
Kojto 111:4336505e4b1c 539 #define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
Kojto 111:4336505e4b1c 540 #define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter 0 Enable */
Kojto 111:4336505e4b1c 541 #define EIC_CONFIG_FILTEN0 (0x1ul << EIC_CONFIG_FILTEN0_Pos)
Kojto 111:4336505e4b1c 542 #define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
Kojto 111:4336505e4b1c 543 #define EIC_CONFIG_SENSE1_Msk (0x7ul << EIC_CONFIG_SENSE1_Pos)
Kojto 111:4336505e4b1c 544 #define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
Kojto 111:4336505e4b1c 545 #define EIC_CONFIG_SENSE1_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
Kojto 111:4336505e4b1c 546 #define EIC_CONFIG_SENSE1_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
Kojto 111:4336505e4b1c 547 #define EIC_CONFIG_SENSE1_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
Kojto 111:4336505e4b1c 548 #define EIC_CONFIG_SENSE1_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
Kojto 111:4336505e4b1c 549 #define EIC_CONFIG_SENSE1_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
Kojto 111:4336505e4b1c 550 #define EIC_CONFIG_SENSE1_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
Kojto 111:4336505e4b1c 551 #define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
Kojto 111:4336505e4b1c 552 #define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
Kojto 111:4336505e4b1c 553 #define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
Kojto 111:4336505e4b1c 554 #define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
Kojto 111:4336505e4b1c 555 #define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
Kojto 111:4336505e4b1c 556 #define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
Kojto 111:4336505e4b1c 557 #define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter 1 Enable */
Kojto 111:4336505e4b1c 558 #define EIC_CONFIG_FILTEN1 (0x1ul << EIC_CONFIG_FILTEN1_Pos)
Kojto 111:4336505e4b1c 559 #define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
Kojto 111:4336505e4b1c 560 #define EIC_CONFIG_SENSE2_Msk (0x7ul << EIC_CONFIG_SENSE2_Pos)
Kojto 111:4336505e4b1c 561 #define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
Kojto 111:4336505e4b1c 562 #define EIC_CONFIG_SENSE2_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
Kojto 111:4336505e4b1c 563 #define EIC_CONFIG_SENSE2_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
Kojto 111:4336505e4b1c 564 #define EIC_CONFIG_SENSE2_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
Kojto 111:4336505e4b1c 565 #define EIC_CONFIG_SENSE2_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
Kojto 111:4336505e4b1c 566 #define EIC_CONFIG_SENSE2_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
Kojto 111:4336505e4b1c 567 #define EIC_CONFIG_SENSE2_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
Kojto 111:4336505e4b1c 568 #define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
Kojto 111:4336505e4b1c 569 #define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
Kojto 111:4336505e4b1c 570 #define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
Kojto 111:4336505e4b1c 571 #define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
Kojto 111:4336505e4b1c 572 #define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
Kojto 111:4336505e4b1c 573 #define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
Kojto 111:4336505e4b1c 574 #define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter 2 Enable */
Kojto 111:4336505e4b1c 575 #define EIC_CONFIG_FILTEN2 (0x1ul << EIC_CONFIG_FILTEN2_Pos)
Kojto 111:4336505e4b1c 576 #define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
Kojto 111:4336505e4b1c 577 #define EIC_CONFIG_SENSE3_Msk (0x7ul << EIC_CONFIG_SENSE3_Pos)
Kojto 111:4336505e4b1c 578 #define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
Kojto 111:4336505e4b1c 579 #define EIC_CONFIG_SENSE3_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
Kojto 111:4336505e4b1c 580 #define EIC_CONFIG_SENSE3_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
Kojto 111:4336505e4b1c 581 #define EIC_CONFIG_SENSE3_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
Kojto 111:4336505e4b1c 582 #define EIC_CONFIG_SENSE3_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
Kojto 111:4336505e4b1c 583 #define EIC_CONFIG_SENSE3_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
Kojto 111:4336505e4b1c 584 #define EIC_CONFIG_SENSE3_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
Kojto 111:4336505e4b1c 585 #define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
Kojto 111:4336505e4b1c 586 #define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
Kojto 111:4336505e4b1c 587 #define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
Kojto 111:4336505e4b1c 588 #define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
Kojto 111:4336505e4b1c 589 #define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
Kojto 111:4336505e4b1c 590 #define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
Kojto 111:4336505e4b1c 591 #define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter 3 Enable */
Kojto 111:4336505e4b1c 592 #define EIC_CONFIG_FILTEN3 (0x1ul << EIC_CONFIG_FILTEN3_Pos)
Kojto 111:4336505e4b1c 593 #define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
Kojto 111:4336505e4b1c 594 #define EIC_CONFIG_SENSE4_Msk (0x7ul << EIC_CONFIG_SENSE4_Pos)
Kojto 111:4336505e4b1c 595 #define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
Kojto 111:4336505e4b1c 596 #define EIC_CONFIG_SENSE4_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
Kojto 111:4336505e4b1c 597 #define EIC_CONFIG_SENSE4_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
Kojto 111:4336505e4b1c 598 #define EIC_CONFIG_SENSE4_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
Kojto 111:4336505e4b1c 599 #define EIC_CONFIG_SENSE4_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
Kojto 111:4336505e4b1c 600 #define EIC_CONFIG_SENSE4_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
Kojto 111:4336505e4b1c 601 #define EIC_CONFIG_SENSE4_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
Kojto 111:4336505e4b1c 602 #define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
Kojto 111:4336505e4b1c 603 #define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
Kojto 111:4336505e4b1c 604 #define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
Kojto 111:4336505e4b1c 605 #define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
Kojto 111:4336505e4b1c 606 #define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
Kojto 111:4336505e4b1c 607 #define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
Kojto 111:4336505e4b1c 608 #define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter 4 Enable */
Kojto 111:4336505e4b1c 609 #define EIC_CONFIG_FILTEN4 (0x1ul << EIC_CONFIG_FILTEN4_Pos)
Kojto 111:4336505e4b1c 610 #define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
Kojto 111:4336505e4b1c 611 #define EIC_CONFIG_SENSE5_Msk (0x7ul << EIC_CONFIG_SENSE5_Pos)
Kojto 111:4336505e4b1c 612 #define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
Kojto 111:4336505e4b1c 613 #define EIC_CONFIG_SENSE5_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
Kojto 111:4336505e4b1c 614 #define EIC_CONFIG_SENSE5_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
Kojto 111:4336505e4b1c 615 #define EIC_CONFIG_SENSE5_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
Kojto 111:4336505e4b1c 616 #define EIC_CONFIG_SENSE5_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
Kojto 111:4336505e4b1c 617 #define EIC_CONFIG_SENSE5_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
Kojto 111:4336505e4b1c 618 #define EIC_CONFIG_SENSE5_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
Kojto 111:4336505e4b1c 619 #define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
Kojto 111:4336505e4b1c 620 #define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
Kojto 111:4336505e4b1c 621 #define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
Kojto 111:4336505e4b1c 622 #define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
Kojto 111:4336505e4b1c 623 #define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
Kojto 111:4336505e4b1c 624 #define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
Kojto 111:4336505e4b1c 625 #define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter 5 Enable */
Kojto 111:4336505e4b1c 626 #define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos)
Kojto 111:4336505e4b1c 627 #define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
Kojto 111:4336505e4b1c 628 #define EIC_CONFIG_SENSE6_Msk (0x7ul << EIC_CONFIG_SENSE6_Pos)
Kojto 111:4336505e4b1c 629 #define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
Kojto 111:4336505e4b1c 630 #define EIC_CONFIG_SENSE6_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
Kojto 111:4336505e4b1c 631 #define EIC_CONFIG_SENSE6_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
Kojto 111:4336505e4b1c 632 #define EIC_CONFIG_SENSE6_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
Kojto 111:4336505e4b1c 633 #define EIC_CONFIG_SENSE6_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
Kojto 111:4336505e4b1c 634 #define EIC_CONFIG_SENSE6_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
Kojto 111:4336505e4b1c 635 #define EIC_CONFIG_SENSE6_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
Kojto 111:4336505e4b1c 636 #define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
Kojto 111:4336505e4b1c 637 #define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
Kojto 111:4336505e4b1c 638 #define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
Kojto 111:4336505e4b1c 639 #define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
Kojto 111:4336505e4b1c 640 #define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
Kojto 111:4336505e4b1c 641 #define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
Kojto 111:4336505e4b1c 642 #define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter 6 Enable */
Kojto 111:4336505e4b1c 643 #define EIC_CONFIG_FILTEN6 (0x1ul << EIC_CONFIG_FILTEN6_Pos)
Kojto 111:4336505e4b1c 644 #define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
Kojto 111:4336505e4b1c 645 #define EIC_CONFIG_SENSE7_Msk (0x7ul << EIC_CONFIG_SENSE7_Pos)
Kojto 111:4336505e4b1c 646 #define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
Kojto 111:4336505e4b1c 647 #define EIC_CONFIG_SENSE7_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
Kojto 111:4336505e4b1c 648 #define EIC_CONFIG_SENSE7_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
Kojto 111:4336505e4b1c 649 #define EIC_CONFIG_SENSE7_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
Kojto 111:4336505e4b1c 650 #define EIC_CONFIG_SENSE7_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
Kojto 111:4336505e4b1c 651 #define EIC_CONFIG_SENSE7_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
Kojto 111:4336505e4b1c 652 #define EIC_CONFIG_SENSE7_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
Kojto 111:4336505e4b1c 653 #define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
Kojto 111:4336505e4b1c 654 #define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
Kojto 111:4336505e4b1c 655 #define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
Kojto 111:4336505e4b1c 656 #define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
Kojto 111:4336505e4b1c 657 #define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
Kojto 111:4336505e4b1c 658 #define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
Kojto 111:4336505e4b1c 659 #define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter 7 Enable */
Kojto 111:4336505e4b1c 660 #define EIC_CONFIG_FILTEN7 (0x1ul << EIC_CONFIG_FILTEN7_Pos)
Kojto 111:4336505e4b1c 661 #define EIC_CONFIG_MASK 0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */
Kojto 111:4336505e4b1c 662
Kojto 111:4336505e4b1c 663 /** \brief EIC hardware registers */
Kojto 111:4336505e4b1c 664 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 665 typedef struct {
Kojto 111:4336505e4b1c 666 __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
Kojto 111:4336505e4b1c 667 __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
Kojto 111:4336505e4b1c 668 __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
Kojto 111:4336505e4b1c 669 __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 670 __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
Kojto 111:4336505e4b1c 671 __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 672 __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
Kojto 111:4336505e4b1c 673 __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 674 __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
Kojto 111:4336505e4b1c 675 __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
Kojto 111:4336505e4b1c 676 } Eic;
Kojto 111:4336505e4b1c 677 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 678
Kojto 111:4336505e4b1c 679 /*@}*/
Kojto 111:4336505e4b1c 680
Kojto 111:4336505e4b1c 681 #endif /* _SAMR21_EIC_COMPONENT_ */