Elijah Orr
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TARGET_SAMD21G18A/pio_samd21e15b.h@121:672067c3ada4, 2016-04-14 (annotated)
- Committer:
- elijahorr
- Date:
- Thu Apr 14 07:28:54 2016 +0000
- Revision:
- 121:672067c3ada4
- Parent:
- 111:4336505e4b1c
.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kojto | 111:4336505e4b1c | 1 | /** |
| Kojto | 111:4336505e4b1c | 2 | * \file |
| Kojto | 111:4336505e4b1c | 3 | * |
| Kojto | 111:4336505e4b1c | 4 | * \brief Peripheral I/O description for SAMD21E15B |
| Kojto | 111:4336505e4b1c | 5 | * |
| Kojto | 111:4336505e4b1c | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
| Kojto | 111:4336505e4b1c | 7 | * |
| Kojto | 111:4336505e4b1c | 8 | * \asf_license_start |
| Kojto | 111:4336505e4b1c | 9 | * |
| Kojto | 111:4336505e4b1c | 10 | * \page License |
| Kojto | 111:4336505e4b1c | 11 | * |
| Kojto | 111:4336505e4b1c | 12 | * Redistribution and use in source and binary forms, with or without |
| Kojto | 111:4336505e4b1c | 13 | * modification, are permitted provided that the following conditions are met: |
| Kojto | 111:4336505e4b1c | 14 | * |
| Kojto | 111:4336505e4b1c | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| Kojto | 111:4336505e4b1c | 16 | * this list of conditions and the following disclaimer. |
| Kojto | 111:4336505e4b1c | 17 | * |
| Kojto | 111:4336505e4b1c | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Kojto | 111:4336505e4b1c | 19 | * this list of conditions and the following disclaimer in the documentation |
| Kojto | 111:4336505e4b1c | 20 | * and/or other materials provided with the distribution. |
| Kojto | 111:4336505e4b1c | 21 | * |
| Kojto | 111:4336505e4b1c | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
| Kojto | 111:4336505e4b1c | 23 | * from this software without specific prior written permission. |
| Kojto | 111:4336505e4b1c | 24 | * |
| Kojto | 111:4336505e4b1c | 25 | * 4. This software may only be redistributed and used in connection with an |
| Kojto | 111:4336505e4b1c | 26 | * Atmel microcontroller product. |
| Kojto | 111:4336505e4b1c | 27 | * |
| Kojto | 111:4336505e4b1c | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
| Kojto | 111:4336505e4b1c | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| Kojto | 111:4336505e4b1c | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
| Kojto | 111:4336505e4b1c | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
| Kojto | 111:4336505e4b1c | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Kojto | 111:4336505e4b1c | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| Kojto | 111:4336505e4b1c | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| Kojto | 111:4336505e4b1c | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| Kojto | 111:4336505e4b1c | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| Kojto | 111:4336505e4b1c | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| Kojto | 111:4336505e4b1c | 38 | * POSSIBILITY OF SUCH DAMAGE. |
| Kojto | 111:4336505e4b1c | 39 | * |
| Kojto | 111:4336505e4b1c | 40 | * \asf_license_stop |
| Kojto | 111:4336505e4b1c | 41 | * |
| Kojto | 111:4336505e4b1c | 42 | */ |
| Kojto | 111:4336505e4b1c | 43 | |
| Kojto | 111:4336505e4b1c | 44 | #ifndef _SAMD21E15B_PIO_ |
| Kojto | 111:4336505e4b1c | 45 | #define _SAMD21E15B_PIO_ |
| Kojto | 111:4336505e4b1c | 46 | |
| Kojto | 111:4336505e4b1c | 47 | #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ |
| Kojto | 111:4336505e4b1c | 48 | #define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ |
| Kojto | 111:4336505e4b1c | 49 | #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ |
| Kojto | 111:4336505e4b1c | 50 | #define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ |
| Kojto | 111:4336505e4b1c | 51 | #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ |
| Kojto | 111:4336505e4b1c | 52 | #define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ |
| Kojto | 111:4336505e4b1c | 53 | #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ |
| Kojto | 111:4336505e4b1c | 54 | #define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ |
| Kojto | 111:4336505e4b1c | 55 | #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ |
| Kojto | 111:4336505e4b1c | 56 | #define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ |
| Kojto | 111:4336505e4b1c | 57 | #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ |
| Kojto | 111:4336505e4b1c | 58 | #define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ |
| Kojto | 111:4336505e4b1c | 59 | #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ |
| Kojto | 111:4336505e4b1c | 60 | #define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ |
| Kojto | 111:4336505e4b1c | 61 | #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ |
| Kojto | 111:4336505e4b1c | 62 | #define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ |
| Kojto | 111:4336505e4b1c | 63 | #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ |
| Kojto | 111:4336505e4b1c | 64 | #define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ |
| Kojto | 111:4336505e4b1c | 65 | #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ |
| Kojto | 111:4336505e4b1c | 66 | #define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ |
| Kojto | 111:4336505e4b1c | 67 | #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ |
| Kojto | 111:4336505e4b1c | 68 | #define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ |
| Kojto | 111:4336505e4b1c | 69 | #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ |
| Kojto | 111:4336505e4b1c | 70 | #define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ |
| Kojto | 111:4336505e4b1c | 71 | #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ |
| Kojto | 111:4336505e4b1c | 72 | #define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ |
| Kojto | 111:4336505e4b1c | 73 | #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ |
| Kojto | 111:4336505e4b1c | 74 | #define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ |
| Kojto | 111:4336505e4b1c | 75 | #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ |
| Kojto | 111:4336505e4b1c | 76 | #define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ |
| Kojto | 111:4336505e4b1c | 77 | #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ |
| Kojto | 111:4336505e4b1c | 78 | #define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ |
| Kojto | 111:4336505e4b1c | 79 | #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ |
| Kojto | 111:4336505e4b1c | 80 | #define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ |
| Kojto | 111:4336505e4b1c | 81 | #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ |
| Kojto | 111:4336505e4b1c | 82 | #define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ |
| Kojto | 111:4336505e4b1c | 83 | #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ |
| Kojto | 111:4336505e4b1c | 84 | #define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ |
| Kojto | 111:4336505e4b1c | 85 | #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ |
| Kojto | 111:4336505e4b1c | 86 | #define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ |
| Kojto | 111:4336505e4b1c | 87 | #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ |
| Kojto | 111:4336505e4b1c | 88 | #define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ |
| Kojto | 111:4336505e4b1c | 89 | #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ |
| Kojto | 111:4336505e4b1c | 90 | #define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ |
| Kojto | 111:4336505e4b1c | 91 | #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ |
| Kojto | 111:4336505e4b1c | 92 | #define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ |
| Kojto | 111:4336505e4b1c | 93 | #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ |
| Kojto | 111:4336505e4b1c | 94 | #define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ |
| Kojto | 111:4336505e4b1c | 95 | #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ |
| Kojto | 111:4336505e4b1c | 96 | #define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ |
| Kojto | 111:4336505e4b1c | 97 | #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ |
| Kojto | 111:4336505e4b1c | 98 | #define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ |
| Kojto | 111:4336505e4b1c | 99 | /* ========== PORT definition for GCLK peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 100 | #define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ |
| Kojto | 111:4336505e4b1c | 101 | #define MUX_PA14H_GCLK_IO0 7L |
| Kojto | 111:4336505e4b1c | 102 | #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) |
| Kojto | 111:4336505e4b1c | 103 | #define PORT_PA14H_GCLK_IO0 (1ul << 14) |
| Kojto | 111:4336505e4b1c | 104 | #define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ |
| Kojto | 111:4336505e4b1c | 105 | #define MUX_PA27H_GCLK_IO0 7L |
| Kojto | 111:4336505e4b1c | 106 | #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) |
| Kojto | 111:4336505e4b1c | 107 | #define PORT_PA27H_GCLK_IO0 (1ul << 27) |
| Kojto | 111:4336505e4b1c | 108 | #define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ |
| Kojto | 111:4336505e4b1c | 109 | #define MUX_PA28H_GCLK_IO0 7L |
| Kojto | 111:4336505e4b1c | 110 | #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) |
| Kojto | 111:4336505e4b1c | 111 | #define PORT_PA28H_GCLK_IO0 (1ul << 28) |
| Kojto | 111:4336505e4b1c | 112 | #define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ |
| Kojto | 111:4336505e4b1c | 113 | #define MUX_PA30H_GCLK_IO0 7L |
| Kojto | 111:4336505e4b1c | 114 | #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) |
| Kojto | 111:4336505e4b1c | 115 | #define PORT_PA30H_GCLK_IO0 (1ul << 30) |
| Kojto | 111:4336505e4b1c | 116 | #define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ |
| Kojto | 111:4336505e4b1c | 117 | #define MUX_PA15H_GCLK_IO1 7L |
| Kojto | 111:4336505e4b1c | 118 | #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) |
| Kojto | 111:4336505e4b1c | 119 | #define PORT_PA15H_GCLK_IO1 (1ul << 15) |
| Kojto | 111:4336505e4b1c | 120 | #define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ |
| Kojto | 111:4336505e4b1c | 121 | #define MUX_PA16H_GCLK_IO2 7L |
| Kojto | 111:4336505e4b1c | 122 | #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) |
| Kojto | 111:4336505e4b1c | 123 | #define PORT_PA16H_GCLK_IO2 (1ul << 16) |
| Kojto | 111:4336505e4b1c | 124 | #define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ |
| Kojto | 111:4336505e4b1c | 125 | #define MUX_PA17H_GCLK_IO3 7L |
| Kojto | 111:4336505e4b1c | 126 | #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) |
| Kojto | 111:4336505e4b1c | 127 | #define PORT_PA17H_GCLK_IO3 (1ul << 17) |
| Kojto | 111:4336505e4b1c | 128 | #define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ |
| Kojto | 111:4336505e4b1c | 129 | #define MUX_PA10H_GCLK_IO4 7L |
| Kojto | 111:4336505e4b1c | 130 | #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) |
| Kojto | 111:4336505e4b1c | 131 | #define PORT_PA10H_GCLK_IO4 (1ul << 10) |
| Kojto | 111:4336505e4b1c | 132 | #define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ |
| Kojto | 111:4336505e4b1c | 133 | #define MUX_PA11H_GCLK_IO5 7L |
| Kojto | 111:4336505e4b1c | 134 | #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) |
| Kojto | 111:4336505e4b1c | 135 | #define PORT_PA11H_GCLK_IO5 (1ul << 11) |
| Kojto | 111:4336505e4b1c | 136 | #define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ |
| Kojto | 111:4336505e4b1c | 137 | #define MUX_PA22H_GCLK_IO6 7L |
| Kojto | 111:4336505e4b1c | 138 | #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) |
| Kojto | 111:4336505e4b1c | 139 | #define PORT_PA22H_GCLK_IO6 (1ul << 22) |
| Kojto | 111:4336505e4b1c | 140 | #define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ |
| Kojto | 111:4336505e4b1c | 141 | #define MUX_PA23H_GCLK_IO7 7L |
| Kojto | 111:4336505e4b1c | 142 | #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) |
| Kojto | 111:4336505e4b1c | 143 | #define PORT_PA23H_GCLK_IO7 (1ul << 23) |
| Kojto | 111:4336505e4b1c | 144 | /* ========== PORT definition for EIC peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 145 | #define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ |
| Kojto | 111:4336505e4b1c | 146 | #define MUX_PA16A_EIC_EXTINT0 0L |
| Kojto | 111:4336505e4b1c | 147 | #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) |
| Kojto | 111:4336505e4b1c | 148 | #define PORT_PA16A_EIC_EXTINT0 (1ul << 16) |
| Kojto | 111:4336505e4b1c | 149 | #define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ |
| Kojto | 111:4336505e4b1c | 150 | #define MUX_PA00A_EIC_EXTINT0 0L |
| Kojto | 111:4336505e4b1c | 151 | #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) |
| Kojto | 111:4336505e4b1c | 152 | #define PORT_PA00A_EIC_EXTINT0 (1ul << 0) |
| Kojto | 111:4336505e4b1c | 153 | #define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ |
| Kojto | 111:4336505e4b1c | 154 | #define MUX_PA17A_EIC_EXTINT1 0L |
| Kojto | 111:4336505e4b1c | 155 | #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) |
| Kojto | 111:4336505e4b1c | 156 | #define PORT_PA17A_EIC_EXTINT1 (1ul << 17) |
| Kojto | 111:4336505e4b1c | 157 | #define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ |
| Kojto | 111:4336505e4b1c | 158 | #define MUX_PA01A_EIC_EXTINT1 0L |
| Kojto | 111:4336505e4b1c | 159 | #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) |
| Kojto | 111:4336505e4b1c | 160 | #define PORT_PA01A_EIC_EXTINT1 (1ul << 1) |
| Kojto | 111:4336505e4b1c | 161 | #define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ |
| Kojto | 111:4336505e4b1c | 162 | #define MUX_PA02A_EIC_EXTINT2 0L |
| Kojto | 111:4336505e4b1c | 163 | #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) |
| Kojto | 111:4336505e4b1c | 164 | #define PORT_PA02A_EIC_EXTINT2 (1ul << 2) |
| Kojto | 111:4336505e4b1c | 165 | #define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ |
| Kojto | 111:4336505e4b1c | 166 | #define MUX_PA18A_EIC_EXTINT2 0L |
| Kojto | 111:4336505e4b1c | 167 | #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) |
| Kojto | 111:4336505e4b1c | 168 | #define PORT_PA18A_EIC_EXTINT2 (1ul << 18) |
| Kojto | 111:4336505e4b1c | 169 | #define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ |
| Kojto | 111:4336505e4b1c | 170 | #define MUX_PA03A_EIC_EXTINT3 0L |
| Kojto | 111:4336505e4b1c | 171 | #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) |
| Kojto | 111:4336505e4b1c | 172 | #define PORT_PA03A_EIC_EXTINT3 (1ul << 3) |
| Kojto | 111:4336505e4b1c | 173 | #define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ |
| Kojto | 111:4336505e4b1c | 174 | #define MUX_PA19A_EIC_EXTINT3 0L |
| Kojto | 111:4336505e4b1c | 175 | #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) |
| Kojto | 111:4336505e4b1c | 176 | #define PORT_PA19A_EIC_EXTINT3 (1ul << 19) |
| Kojto | 111:4336505e4b1c | 177 | #define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ |
| Kojto | 111:4336505e4b1c | 178 | #define MUX_PA04A_EIC_EXTINT4 0L |
| Kojto | 111:4336505e4b1c | 179 | #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) |
| Kojto | 111:4336505e4b1c | 180 | #define PORT_PA04A_EIC_EXTINT4 (1ul << 4) |
| Kojto | 111:4336505e4b1c | 181 | #define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ |
| Kojto | 111:4336505e4b1c | 182 | #define MUX_PA05A_EIC_EXTINT5 0L |
| Kojto | 111:4336505e4b1c | 183 | #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) |
| Kojto | 111:4336505e4b1c | 184 | #define PORT_PA05A_EIC_EXTINT5 (1ul << 5) |
| Kojto | 111:4336505e4b1c | 185 | #define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ |
| Kojto | 111:4336505e4b1c | 186 | #define MUX_PA06A_EIC_EXTINT6 0L |
| Kojto | 111:4336505e4b1c | 187 | #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) |
| Kojto | 111:4336505e4b1c | 188 | #define PORT_PA06A_EIC_EXTINT6 (1ul << 6) |
| Kojto | 111:4336505e4b1c | 189 | #define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ |
| Kojto | 111:4336505e4b1c | 190 | #define MUX_PA22A_EIC_EXTINT6 0L |
| Kojto | 111:4336505e4b1c | 191 | #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) |
| Kojto | 111:4336505e4b1c | 192 | #define PORT_PA22A_EIC_EXTINT6 (1ul << 22) |
| Kojto | 111:4336505e4b1c | 193 | #define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ |
| Kojto | 111:4336505e4b1c | 194 | #define MUX_PA07A_EIC_EXTINT7 0L |
| Kojto | 111:4336505e4b1c | 195 | #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) |
| Kojto | 111:4336505e4b1c | 196 | #define PORT_PA07A_EIC_EXTINT7 (1ul << 7) |
| Kojto | 111:4336505e4b1c | 197 | #define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ |
| Kojto | 111:4336505e4b1c | 198 | #define MUX_PA23A_EIC_EXTINT7 0L |
| Kojto | 111:4336505e4b1c | 199 | #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) |
| Kojto | 111:4336505e4b1c | 200 | #define PORT_PA23A_EIC_EXTINT7 (1ul << 23) |
| Kojto | 111:4336505e4b1c | 201 | #define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ |
| Kojto | 111:4336505e4b1c | 202 | #define MUX_PA28A_EIC_EXTINT8 0L |
| Kojto | 111:4336505e4b1c | 203 | #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) |
| Kojto | 111:4336505e4b1c | 204 | #define PORT_PA28A_EIC_EXTINT8 (1ul << 28) |
| Kojto | 111:4336505e4b1c | 205 | #define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ |
| Kojto | 111:4336505e4b1c | 206 | #define MUX_PA09A_EIC_EXTINT9 0L |
| Kojto | 111:4336505e4b1c | 207 | #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) |
| Kojto | 111:4336505e4b1c | 208 | #define PORT_PA09A_EIC_EXTINT9 (1ul << 9) |
| Kojto | 111:4336505e4b1c | 209 | #define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ |
| Kojto | 111:4336505e4b1c | 210 | #define MUX_PA10A_EIC_EXTINT10 0L |
| Kojto | 111:4336505e4b1c | 211 | #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) |
| Kojto | 111:4336505e4b1c | 212 | #define PORT_PA10A_EIC_EXTINT10 (1ul << 10) |
| Kojto | 111:4336505e4b1c | 213 | #define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ |
| Kojto | 111:4336505e4b1c | 214 | #define MUX_PA30A_EIC_EXTINT10 0L |
| Kojto | 111:4336505e4b1c | 215 | #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) |
| Kojto | 111:4336505e4b1c | 216 | #define PORT_PA30A_EIC_EXTINT10 (1ul << 30) |
| Kojto | 111:4336505e4b1c | 217 | #define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ |
| Kojto | 111:4336505e4b1c | 218 | #define MUX_PA11A_EIC_EXTINT11 0L |
| Kojto | 111:4336505e4b1c | 219 | #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) |
| Kojto | 111:4336505e4b1c | 220 | #define PORT_PA11A_EIC_EXTINT11 (1ul << 11) |
| Kojto | 111:4336505e4b1c | 221 | #define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ |
| Kojto | 111:4336505e4b1c | 222 | #define MUX_PA31A_EIC_EXTINT11 0L |
| Kojto | 111:4336505e4b1c | 223 | #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) |
| Kojto | 111:4336505e4b1c | 224 | #define PORT_PA31A_EIC_EXTINT11 (1ul << 31) |
| Kojto | 111:4336505e4b1c | 225 | #define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ |
| Kojto | 111:4336505e4b1c | 226 | #define MUX_PA24A_EIC_EXTINT12 0L |
| Kojto | 111:4336505e4b1c | 227 | #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) |
| Kojto | 111:4336505e4b1c | 228 | #define PORT_PA24A_EIC_EXTINT12 (1ul << 24) |
| Kojto | 111:4336505e4b1c | 229 | #define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ |
| Kojto | 111:4336505e4b1c | 230 | #define MUX_PA25A_EIC_EXTINT13 0L |
| Kojto | 111:4336505e4b1c | 231 | #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) |
| Kojto | 111:4336505e4b1c | 232 | #define PORT_PA25A_EIC_EXTINT13 (1ul << 25) |
| Kojto | 111:4336505e4b1c | 233 | #define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ |
| Kojto | 111:4336505e4b1c | 234 | #define MUX_PA14A_EIC_EXTINT14 0L |
| Kojto | 111:4336505e4b1c | 235 | #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) |
| Kojto | 111:4336505e4b1c | 236 | #define PORT_PA14A_EIC_EXTINT14 (1ul << 14) |
| Kojto | 111:4336505e4b1c | 237 | #define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ |
| Kojto | 111:4336505e4b1c | 238 | #define MUX_PA27A_EIC_EXTINT15 0L |
| Kojto | 111:4336505e4b1c | 239 | #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) |
| Kojto | 111:4336505e4b1c | 240 | #define PORT_PA27A_EIC_EXTINT15 (1ul << 27) |
| Kojto | 111:4336505e4b1c | 241 | #define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ |
| Kojto | 111:4336505e4b1c | 242 | #define MUX_PA15A_EIC_EXTINT15 0L |
| Kojto | 111:4336505e4b1c | 243 | #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) |
| Kojto | 111:4336505e4b1c | 244 | #define PORT_PA15A_EIC_EXTINT15 (1ul << 15) |
| Kojto | 111:4336505e4b1c | 245 | #define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ |
| Kojto | 111:4336505e4b1c | 246 | #define MUX_PA08A_EIC_NMI 0L |
| Kojto | 111:4336505e4b1c | 247 | #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) |
| Kojto | 111:4336505e4b1c | 248 | #define PORT_PA08A_EIC_NMI (1ul << 8) |
| Kojto | 111:4336505e4b1c | 249 | /* ========== PORT definition for USB peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 250 | #define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ |
| Kojto | 111:4336505e4b1c | 251 | #define MUX_PA24G_USB_DM 6L |
| Kojto | 111:4336505e4b1c | 252 | #define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) |
| Kojto | 111:4336505e4b1c | 253 | #define PORT_PA24G_USB_DM (1ul << 24) |
| Kojto | 111:4336505e4b1c | 254 | #define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ |
| Kojto | 111:4336505e4b1c | 255 | #define MUX_PA25G_USB_DP 6L |
| Kojto | 111:4336505e4b1c | 256 | #define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) |
| Kojto | 111:4336505e4b1c | 257 | #define PORT_PA25G_USB_DP (1ul << 25) |
| Kojto | 111:4336505e4b1c | 258 | #define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ |
| Kojto | 111:4336505e4b1c | 259 | #define MUX_PA23G_USB_SOF_1KHZ 6L |
| Kojto | 111:4336505e4b1c | 260 | #define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) |
| Kojto | 111:4336505e4b1c | 261 | #define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) |
| Kojto | 111:4336505e4b1c | 262 | /* ========== PORT definition for SERCOM0 peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 263 | #define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ |
| Kojto | 111:4336505e4b1c | 264 | #define MUX_PA04D_SERCOM0_PAD0 3L |
| Kojto | 111:4336505e4b1c | 265 | #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) |
| Kojto | 111:4336505e4b1c | 266 | #define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) |
| Kojto | 111:4336505e4b1c | 267 | #define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ |
| Kojto | 111:4336505e4b1c | 268 | #define MUX_PA08C_SERCOM0_PAD0 2L |
| Kojto | 111:4336505e4b1c | 269 | #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) |
| Kojto | 111:4336505e4b1c | 270 | #define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) |
| Kojto | 111:4336505e4b1c | 271 | #define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ |
| Kojto | 111:4336505e4b1c | 272 | #define MUX_PA05D_SERCOM0_PAD1 3L |
| Kojto | 111:4336505e4b1c | 273 | #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) |
| Kojto | 111:4336505e4b1c | 274 | #define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) |
| Kojto | 111:4336505e4b1c | 275 | #define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ |
| Kojto | 111:4336505e4b1c | 276 | #define MUX_PA09C_SERCOM0_PAD1 2L |
| Kojto | 111:4336505e4b1c | 277 | #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) |
| Kojto | 111:4336505e4b1c | 278 | #define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) |
| Kojto | 111:4336505e4b1c | 279 | #define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ |
| Kojto | 111:4336505e4b1c | 280 | #define MUX_PA06D_SERCOM0_PAD2 3L |
| Kojto | 111:4336505e4b1c | 281 | #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) |
| Kojto | 111:4336505e4b1c | 282 | #define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) |
| Kojto | 111:4336505e4b1c | 283 | #define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ |
| Kojto | 111:4336505e4b1c | 284 | #define MUX_PA10C_SERCOM0_PAD2 2L |
| Kojto | 111:4336505e4b1c | 285 | #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) |
| Kojto | 111:4336505e4b1c | 286 | #define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) |
| Kojto | 111:4336505e4b1c | 287 | #define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ |
| Kojto | 111:4336505e4b1c | 288 | #define MUX_PA07D_SERCOM0_PAD3 3L |
| Kojto | 111:4336505e4b1c | 289 | #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) |
| Kojto | 111:4336505e4b1c | 290 | #define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) |
| Kojto | 111:4336505e4b1c | 291 | #define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ |
| Kojto | 111:4336505e4b1c | 292 | #define MUX_PA11C_SERCOM0_PAD3 2L |
| Kojto | 111:4336505e4b1c | 293 | #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) |
| Kojto | 111:4336505e4b1c | 294 | #define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) |
| Kojto | 111:4336505e4b1c | 295 | /* ========== PORT definition for SERCOM1 peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 296 | #define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ |
| Kojto | 111:4336505e4b1c | 297 | #define MUX_PA16C_SERCOM1_PAD0 2L |
| Kojto | 111:4336505e4b1c | 298 | #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) |
| Kojto | 111:4336505e4b1c | 299 | #define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) |
| Kojto | 111:4336505e4b1c | 300 | #define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ |
| Kojto | 111:4336505e4b1c | 301 | #define MUX_PA00D_SERCOM1_PAD0 3L |
| Kojto | 111:4336505e4b1c | 302 | #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) |
| Kojto | 111:4336505e4b1c | 303 | #define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) |
| Kojto | 111:4336505e4b1c | 304 | #define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ |
| Kojto | 111:4336505e4b1c | 305 | #define MUX_PA17C_SERCOM1_PAD1 2L |
| Kojto | 111:4336505e4b1c | 306 | #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) |
| Kojto | 111:4336505e4b1c | 307 | #define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) |
| Kojto | 111:4336505e4b1c | 308 | #define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ |
| Kojto | 111:4336505e4b1c | 309 | #define MUX_PA01D_SERCOM1_PAD1 3L |
| Kojto | 111:4336505e4b1c | 310 | #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) |
| Kojto | 111:4336505e4b1c | 311 | #define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) |
| Kojto | 111:4336505e4b1c | 312 | #define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ |
| Kojto | 111:4336505e4b1c | 313 | #define MUX_PA30D_SERCOM1_PAD2 3L |
| Kojto | 111:4336505e4b1c | 314 | #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) |
| Kojto | 111:4336505e4b1c | 315 | #define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) |
| Kojto | 111:4336505e4b1c | 316 | #define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ |
| Kojto | 111:4336505e4b1c | 317 | #define MUX_PA18C_SERCOM1_PAD2 2L |
| Kojto | 111:4336505e4b1c | 318 | #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) |
| Kojto | 111:4336505e4b1c | 319 | #define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) |
| Kojto | 111:4336505e4b1c | 320 | #define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ |
| Kojto | 111:4336505e4b1c | 321 | #define MUX_PA31D_SERCOM1_PAD3 3L |
| Kojto | 111:4336505e4b1c | 322 | #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) |
| Kojto | 111:4336505e4b1c | 323 | #define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) |
| Kojto | 111:4336505e4b1c | 324 | #define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ |
| Kojto | 111:4336505e4b1c | 325 | #define MUX_PA19C_SERCOM1_PAD3 2L |
| Kojto | 111:4336505e4b1c | 326 | #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) |
| Kojto | 111:4336505e4b1c | 327 | #define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) |
| Kojto | 111:4336505e4b1c | 328 | /* ========== PORT definition for SERCOM2 peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 329 | #define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ |
| Kojto | 111:4336505e4b1c | 330 | #define MUX_PA08D_SERCOM2_PAD0 3L |
| Kojto | 111:4336505e4b1c | 331 | #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) |
| Kojto | 111:4336505e4b1c | 332 | #define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) |
| Kojto | 111:4336505e4b1c | 333 | #define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ |
| Kojto | 111:4336505e4b1c | 334 | #define MUX_PA09D_SERCOM2_PAD1 3L |
| Kojto | 111:4336505e4b1c | 335 | #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) |
| Kojto | 111:4336505e4b1c | 336 | #define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) |
| Kojto | 111:4336505e4b1c | 337 | #define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ |
| Kojto | 111:4336505e4b1c | 338 | #define MUX_PA10D_SERCOM2_PAD2 3L |
| Kojto | 111:4336505e4b1c | 339 | #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) |
| Kojto | 111:4336505e4b1c | 340 | #define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) |
| Kojto | 111:4336505e4b1c | 341 | #define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ |
| Kojto | 111:4336505e4b1c | 342 | #define MUX_PA14C_SERCOM2_PAD2 2L |
| Kojto | 111:4336505e4b1c | 343 | #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) |
| Kojto | 111:4336505e4b1c | 344 | #define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) |
| Kojto | 111:4336505e4b1c | 345 | #define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ |
| Kojto | 111:4336505e4b1c | 346 | #define MUX_PA11D_SERCOM2_PAD3 3L |
| Kojto | 111:4336505e4b1c | 347 | #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) |
| Kojto | 111:4336505e4b1c | 348 | #define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) |
| Kojto | 111:4336505e4b1c | 349 | #define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ |
| Kojto | 111:4336505e4b1c | 350 | #define MUX_PA15C_SERCOM2_PAD3 2L |
| Kojto | 111:4336505e4b1c | 351 | #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) |
| Kojto | 111:4336505e4b1c | 352 | #define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) |
| Kojto | 111:4336505e4b1c | 353 | /* ========== PORT definition for SERCOM3 peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 354 | #define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ |
| Kojto | 111:4336505e4b1c | 355 | #define MUX_PA16D_SERCOM3_PAD0 3L |
| Kojto | 111:4336505e4b1c | 356 | #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) |
| Kojto | 111:4336505e4b1c | 357 | #define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) |
| Kojto | 111:4336505e4b1c | 358 | #define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ |
| Kojto | 111:4336505e4b1c | 359 | #define MUX_PA22C_SERCOM3_PAD0 2L |
| Kojto | 111:4336505e4b1c | 360 | #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) |
| Kojto | 111:4336505e4b1c | 361 | #define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) |
| Kojto | 111:4336505e4b1c | 362 | #define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ |
| Kojto | 111:4336505e4b1c | 363 | #define MUX_PA17D_SERCOM3_PAD1 3L |
| Kojto | 111:4336505e4b1c | 364 | #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) |
| Kojto | 111:4336505e4b1c | 365 | #define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) |
| Kojto | 111:4336505e4b1c | 366 | #define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ |
| Kojto | 111:4336505e4b1c | 367 | #define MUX_PA23C_SERCOM3_PAD1 2L |
| Kojto | 111:4336505e4b1c | 368 | #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) |
| Kojto | 111:4336505e4b1c | 369 | #define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) |
| Kojto | 111:4336505e4b1c | 370 | #define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ |
| Kojto | 111:4336505e4b1c | 371 | #define MUX_PA18D_SERCOM3_PAD2 3L |
| Kojto | 111:4336505e4b1c | 372 | #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) |
| Kojto | 111:4336505e4b1c | 373 | #define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) |
| Kojto | 111:4336505e4b1c | 374 | #define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ |
| Kojto | 111:4336505e4b1c | 375 | #define MUX_PA24C_SERCOM3_PAD2 2L |
| Kojto | 111:4336505e4b1c | 376 | #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) |
| Kojto | 111:4336505e4b1c | 377 | #define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) |
| Kojto | 111:4336505e4b1c | 378 | #define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ |
| Kojto | 111:4336505e4b1c | 379 | #define MUX_PA19D_SERCOM3_PAD3 3L |
| Kojto | 111:4336505e4b1c | 380 | #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) |
| Kojto | 111:4336505e4b1c | 381 | #define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) |
| Kojto | 111:4336505e4b1c | 382 | #define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ |
| Kojto | 111:4336505e4b1c | 383 | #define MUX_PA25C_SERCOM3_PAD3 2L |
| Kojto | 111:4336505e4b1c | 384 | #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) |
| Kojto | 111:4336505e4b1c | 385 | #define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) |
| Kojto | 111:4336505e4b1c | 386 | /* ========== PORT definition for TCC0 peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 387 | #define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ |
| Kojto | 111:4336505e4b1c | 388 | #define MUX_PA04E_TCC0_WO0 4L |
| Kojto | 111:4336505e4b1c | 389 | #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) |
| Kojto | 111:4336505e4b1c | 390 | #define PORT_PA04E_TCC0_WO0 (1ul << 4) |
| Kojto | 111:4336505e4b1c | 391 | #define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ |
| Kojto | 111:4336505e4b1c | 392 | #define MUX_PA08E_TCC0_WO0 4L |
| Kojto | 111:4336505e4b1c | 393 | #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) |
| Kojto | 111:4336505e4b1c | 394 | #define PORT_PA08E_TCC0_WO0 (1ul << 8) |
| Kojto | 111:4336505e4b1c | 395 | #define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ |
| Kojto | 111:4336505e4b1c | 396 | #define MUX_PA05E_TCC0_WO1 4L |
| Kojto | 111:4336505e4b1c | 397 | #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) |
| Kojto | 111:4336505e4b1c | 398 | #define PORT_PA05E_TCC0_WO1 (1ul << 5) |
| Kojto | 111:4336505e4b1c | 399 | #define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ |
| Kojto | 111:4336505e4b1c | 400 | #define MUX_PA09E_TCC0_WO1 4L |
| Kojto | 111:4336505e4b1c | 401 | #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) |
| Kojto | 111:4336505e4b1c | 402 | #define PORT_PA09E_TCC0_WO1 (1ul << 9) |
| Kojto | 111:4336505e4b1c | 403 | #define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ |
| Kojto | 111:4336505e4b1c | 404 | #define MUX_PA10F_TCC0_WO2 5L |
| Kojto | 111:4336505e4b1c | 405 | #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) |
| Kojto | 111:4336505e4b1c | 406 | #define PORT_PA10F_TCC0_WO2 (1ul << 10) |
| Kojto | 111:4336505e4b1c | 407 | #define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ |
| Kojto | 111:4336505e4b1c | 408 | #define MUX_PA18F_TCC0_WO2 5L |
| Kojto | 111:4336505e4b1c | 409 | #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) |
| Kojto | 111:4336505e4b1c | 410 | #define PORT_PA18F_TCC0_WO2 (1ul << 18) |
| Kojto | 111:4336505e4b1c | 411 | #define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ |
| Kojto | 111:4336505e4b1c | 412 | #define MUX_PA11F_TCC0_WO3 5L |
| Kojto | 111:4336505e4b1c | 413 | #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) |
| Kojto | 111:4336505e4b1c | 414 | #define PORT_PA11F_TCC0_WO3 (1ul << 11) |
| Kojto | 111:4336505e4b1c | 415 | #define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ |
| Kojto | 111:4336505e4b1c | 416 | #define MUX_PA19F_TCC0_WO3 5L |
| Kojto | 111:4336505e4b1c | 417 | #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) |
| Kojto | 111:4336505e4b1c | 418 | #define PORT_PA19F_TCC0_WO3 (1ul << 19) |
| Kojto | 111:4336505e4b1c | 419 | #define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ |
| Kojto | 111:4336505e4b1c | 420 | #define MUX_PA22F_TCC0_WO4 5L |
| Kojto | 111:4336505e4b1c | 421 | #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) |
| Kojto | 111:4336505e4b1c | 422 | #define PORT_PA22F_TCC0_WO4 (1ul << 22) |
| Kojto | 111:4336505e4b1c | 423 | #define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ |
| Kojto | 111:4336505e4b1c | 424 | #define MUX_PA14F_TCC0_WO4 5L |
| Kojto | 111:4336505e4b1c | 425 | #define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) |
| Kojto | 111:4336505e4b1c | 426 | #define PORT_PA14F_TCC0_WO4 (1ul << 14) |
| Kojto | 111:4336505e4b1c | 427 | #define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ |
| Kojto | 111:4336505e4b1c | 428 | #define MUX_PA23F_TCC0_WO5 5L |
| Kojto | 111:4336505e4b1c | 429 | #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) |
| Kojto | 111:4336505e4b1c | 430 | #define PORT_PA23F_TCC0_WO5 (1ul << 23) |
| Kojto | 111:4336505e4b1c | 431 | #define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ |
| Kojto | 111:4336505e4b1c | 432 | #define MUX_PA15F_TCC0_WO5 5L |
| Kojto | 111:4336505e4b1c | 433 | #define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) |
| Kojto | 111:4336505e4b1c | 434 | #define PORT_PA15F_TCC0_WO5 (1ul << 15) |
| Kojto | 111:4336505e4b1c | 435 | #define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ |
| Kojto | 111:4336505e4b1c | 436 | #define MUX_PA16F_TCC0_WO6 5L |
| Kojto | 111:4336505e4b1c | 437 | #define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) |
| Kojto | 111:4336505e4b1c | 438 | #define PORT_PA16F_TCC0_WO6 (1ul << 16) |
| Kojto | 111:4336505e4b1c | 439 | #define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ |
| Kojto | 111:4336505e4b1c | 440 | #define MUX_PA17F_TCC0_WO7 5L |
| Kojto | 111:4336505e4b1c | 441 | #define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) |
| Kojto | 111:4336505e4b1c | 442 | #define PORT_PA17F_TCC0_WO7 (1ul << 17) |
| Kojto | 111:4336505e4b1c | 443 | /* ========== PORT definition for TCC1 peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 444 | #define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ |
| Kojto | 111:4336505e4b1c | 445 | #define MUX_PA06E_TCC1_WO0 4L |
| Kojto | 111:4336505e4b1c | 446 | #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) |
| Kojto | 111:4336505e4b1c | 447 | #define PORT_PA06E_TCC1_WO0 (1ul << 6) |
| Kojto | 111:4336505e4b1c | 448 | #define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ |
| Kojto | 111:4336505e4b1c | 449 | #define MUX_PA10E_TCC1_WO0 4L |
| Kojto | 111:4336505e4b1c | 450 | #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) |
| Kojto | 111:4336505e4b1c | 451 | #define PORT_PA10E_TCC1_WO0 (1ul << 10) |
| Kojto | 111:4336505e4b1c | 452 | #define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ |
| Kojto | 111:4336505e4b1c | 453 | #define MUX_PA30E_TCC1_WO0 4L |
| Kojto | 111:4336505e4b1c | 454 | #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) |
| Kojto | 111:4336505e4b1c | 455 | #define PORT_PA30E_TCC1_WO0 (1ul << 30) |
| Kojto | 111:4336505e4b1c | 456 | #define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ |
| Kojto | 111:4336505e4b1c | 457 | #define MUX_PA07E_TCC1_WO1 4L |
| Kojto | 111:4336505e4b1c | 458 | #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) |
| Kojto | 111:4336505e4b1c | 459 | #define PORT_PA07E_TCC1_WO1 (1ul << 7) |
| Kojto | 111:4336505e4b1c | 460 | #define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ |
| Kojto | 111:4336505e4b1c | 461 | #define MUX_PA11E_TCC1_WO1 4L |
| Kojto | 111:4336505e4b1c | 462 | #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) |
| Kojto | 111:4336505e4b1c | 463 | #define PORT_PA11E_TCC1_WO1 (1ul << 11) |
| Kojto | 111:4336505e4b1c | 464 | #define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ |
| Kojto | 111:4336505e4b1c | 465 | #define MUX_PA31E_TCC1_WO1 4L |
| Kojto | 111:4336505e4b1c | 466 | #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) |
| Kojto | 111:4336505e4b1c | 467 | #define PORT_PA31E_TCC1_WO1 (1ul << 31) |
| Kojto | 111:4336505e4b1c | 468 | #define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ |
| Kojto | 111:4336505e4b1c | 469 | #define MUX_PA08F_TCC1_WO2 5L |
| Kojto | 111:4336505e4b1c | 470 | #define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) |
| Kojto | 111:4336505e4b1c | 471 | #define PORT_PA08F_TCC1_WO2 (1ul << 8) |
| Kojto | 111:4336505e4b1c | 472 | #define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ |
| Kojto | 111:4336505e4b1c | 473 | #define MUX_PA24F_TCC1_WO2 5L |
| Kojto | 111:4336505e4b1c | 474 | #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) |
| Kojto | 111:4336505e4b1c | 475 | #define PORT_PA24F_TCC1_WO2 (1ul << 24) |
| Kojto | 111:4336505e4b1c | 476 | #define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ |
| Kojto | 111:4336505e4b1c | 477 | #define MUX_PA09F_TCC1_WO3 5L |
| Kojto | 111:4336505e4b1c | 478 | #define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) |
| Kojto | 111:4336505e4b1c | 479 | #define PORT_PA09F_TCC1_WO3 (1ul << 9) |
| Kojto | 111:4336505e4b1c | 480 | #define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ |
| Kojto | 111:4336505e4b1c | 481 | #define MUX_PA25F_TCC1_WO3 5L |
| Kojto | 111:4336505e4b1c | 482 | #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) |
| Kojto | 111:4336505e4b1c | 483 | #define PORT_PA25F_TCC1_WO3 (1ul << 25) |
| Kojto | 111:4336505e4b1c | 484 | /* ========== PORT definition for TCC2 peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 485 | #define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ |
| Kojto | 111:4336505e4b1c | 486 | #define MUX_PA16E_TCC2_WO0 4L |
| Kojto | 111:4336505e4b1c | 487 | #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) |
| Kojto | 111:4336505e4b1c | 488 | #define PORT_PA16E_TCC2_WO0 (1ul << 16) |
| Kojto | 111:4336505e4b1c | 489 | #define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ |
| Kojto | 111:4336505e4b1c | 490 | #define MUX_PA00E_TCC2_WO0 4L |
| Kojto | 111:4336505e4b1c | 491 | #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) |
| Kojto | 111:4336505e4b1c | 492 | #define PORT_PA00E_TCC2_WO0 (1ul << 0) |
| Kojto | 111:4336505e4b1c | 493 | #define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ |
| Kojto | 111:4336505e4b1c | 494 | #define MUX_PA17E_TCC2_WO1 4L |
| Kojto | 111:4336505e4b1c | 495 | #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) |
| Kojto | 111:4336505e4b1c | 496 | #define PORT_PA17E_TCC2_WO1 (1ul << 17) |
| Kojto | 111:4336505e4b1c | 497 | #define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ |
| Kojto | 111:4336505e4b1c | 498 | #define MUX_PA01E_TCC2_WO1 4L |
| Kojto | 111:4336505e4b1c | 499 | #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) |
| Kojto | 111:4336505e4b1c | 500 | #define PORT_PA01E_TCC2_WO1 (1ul << 1) |
| Kojto | 111:4336505e4b1c | 501 | /* ========== PORT definition for TC3 peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 502 | #define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ |
| Kojto | 111:4336505e4b1c | 503 | #define MUX_PA18E_TC3_WO0 4L |
| Kojto | 111:4336505e4b1c | 504 | #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) |
| Kojto | 111:4336505e4b1c | 505 | #define PORT_PA18E_TC3_WO0 (1ul << 18) |
| Kojto | 111:4336505e4b1c | 506 | #define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ |
| Kojto | 111:4336505e4b1c | 507 | #define MUX_PA14E_TC3_WO0 4L |
| Kojto | 111:4336505e4b1c | 508 | #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) |
| Kojto | 111:4336505e4b1c | 509 | #define PORT_PA14E_TC3_WO0 (1ul << 14) |
| Kojto | 111:4336505e4b1c | 510 | #define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ |
| Kojto | 111:4336505e4b1c | 511 | #define MUX_PA19E_TC3_WO1 4L |
| Kojto | 111:4336505e4b1c | 512 | #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) |
| Kojto | 111:4336505e4b1c | 513 | #define PORT_PA19E_TC3_WO1 (1ul << 19) |
| Kojto | 111:4336505e4b1c | 514 | #define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ |
| Kojto | 111:4336505e4b1c | 515 | #define MUX_PA15E_TC3_WO1 4L |
| Kojto | 111:4336505e4b1c | 516 | #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) |
| Kojto | 111:4336505e4b1c | 517 | #define PORT_PA15E_TC3_WO1 (1ul << 15) |
| Kojto | 111:4336505e4b1c | 518 | /* ========== PORT definition for TC4 peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 519 | #define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ |
| Kojto | 111:4336505e4b1c | 520 | #define MUX_PA22E_TC4_WO0 4L |
| Kojto | 111:4336505e4b1c | 521 | #define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) |
| Kojto | 111:4336505e4b1c | 522 | #define PORT_PA22E_TC4_WO0 (1ul << 22) |
| Kojto | 111:4336505e4b1c | 523 | #define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ |
| Kojto | 111:4336505e4b1c | 524 | #define MUX_PA23E_TC4_WO1 4L |
| Kojto | 111:4336505e4b1c | 525 | #define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) |
| Kojto | 111:4336505e4b1c | 526 | #define PORT_PA23E_TC4_WO1 (1ul << 23) |
| Kojto | 111:4336505e4b1c | 527 | /* ========== PORT definition for TC5 peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 528 | #define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ |
| Kojto | 111:4336505e4b1c | 529 | #define MUX_PA24E_TC5_WO0 4L |
| Kojto | 111:4336505e4b1c | 530 | #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) |
| Kojto | 111:4336505e4b1c | 531 | #define PORT_PA24E_TC5_WO0 (1ul << 24) |
| Kojto | 111:4336505e4b1c | 532 | #define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ |
| Kojto | 111:4336505e4b1c | 533 | #define MUX_PA25E_TC5_WO1 4L |
| Kojto | 111:4336505e4b1c | 534 | #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) |
| Kojto | 111:4336505e4b1c | 535 | #define PORT_PA25E_TC5_WO1 (1ul << 25) |
| Kojto | 111:4336505e4b1c | 536 | /* ========== PORT definition for ADC peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 537 | #define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ |
| Kojto | 111:4336505e4b1c | 538 | #define MUX_PA02B_ADC_AIN0 1L |
| Kojto | 111:4336505e4b1c | 539 | #define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) |
| Kojto | 111:4336505e4b1c | 540 | #define PORT_PA02B_ADC_AIN0 (1ul << 2) |
| Kojto | 111:4336505e4b1c | 541 | #define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ |
| Kojto | 111:4336505e4b1c | 542 | #define MUX_PA03B_ADC_AIN1 1L |
| Kojto | 111:4336505e4b1c | 543 | #define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) |
| Kojto | 111:4336505e4b1c | 544 | #define PORT_PA03B_ADC_AIN1 (1ul << 3) |
| Kojto | 111:4336505e4b1c | 545 | #define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ |
| Kojto | 111:4336505e4b1c | 546 | #define MUX_PA04B_ADC_AIN4 1L |
| Kojto | 111:4336505e4b1c | 547 | #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) |
| Kojto | 111:4336505e4b1c | 548 | #define PORT_PA04B_ADC_AIN4 (1ul << 4) |
| Kojto | 111:4336505e4b1c | 549 | #define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ |
| Kojto | 111:4336505e4b1c | 550 | #define MUX_PA05B_ADC_AIN5 1L |
| Kojto | 111:4336505e4b1c | 551 | #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) |
| Kojto | 111:4336505e4b1c | 552 | #define PORT_PA05B_ADC_AIN5 (1ul << 5) |
| Kojto | 111:4336505e4b1c | 553 | #define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ |
| Kojto | 111:4336505e4b1c | 554 | #define MUX_PA06B_ADC_AIN6 1L |
| Kojto | 111:4336505e4b1c | 555 | #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) |
| Kojto | 111:4336505e4b1c | 556 | #define PORT_PA06B_ADC_AIN6 (1ul << 6) |
| Kojto | 111:4336505e4b1c | 557 | #define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ |
| Kojto | 111:4336505e4b1c | 558 | #define MUX_PA07B_ADC_AIN7 1L |
| Kojto | 111:4336505e4b1c | 559 | #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) |
| Kojto | 111:4336505e4b1c | 560 | #define PORT_PA07B_ADC_AIN7 (1ul << 7) |
| Kojto | 111:4336505e4b1c | 561 | #define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ |
| Kojto | 111:4336505e4b1c | 562 | #define MUX_PA08B_ADC_AIN16 1L |
| Kojto | 111:4336505e4b1c | 563 | #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) |
| Kojto | 111:4336505e4b1c | 564 | #define PORT_PA08B_ADC_AIN16 (1ul << 8) |
| Kojto | 111:4336505e4b1c | 565 | #define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ |
| Kojto | 111:4336505e4b1c | 566 | #define MUX_PA09B_ADC_AIN17 1L |
| Kojto | 111:4336505e4b1c | 567 | #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) |
| Kojto | 111:4336505e4b1c | 568 | #define PORT_PA09B_ADC_AIN17 (1ul << 9) |
| Kojto | 111:4336505e4b1c | 569 | #define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ |
| Kojto | 111:4336505e4b1c | 570 | #define MUX_PA10B_ADC_AIN18 1L |
| Kojto | 111:4336505e4b1c | 571 | #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) |
| Kojto | 111:4336505e4b1c | 572 | #define PORT_PA10B_ADC_AIN18 (1ul << 10) |
| Kojto | 111:4336505e4b1c | 573 | #define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ |
| Kojto | 111:4336505e4b1c | 574 | #define MUX_PA11B_ADC_AIN19 1L |
| Kojto | 111:4336505e4b1c | 575 | #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) |
| Kojto | 111:4336505e4b1c | 576 | #define PORT_PA11B_ADC_AIN19 (1ul << 11) |
| Kojto | 111:4336505e4b1c | 577 | #define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ |
| Kojto | 111:4336505e4b1c | 578 | #define MUX_PA04B_ADC_VREFP 1L |
| Kojto | 111:4336505e4b1c | 579 | #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) |
| Kojto | 111:4336505e4b1c | 580 | #define PORT_PA04B_ADC_VREFP (1ul << 4) |
| Kojto | 111:4336505e4b1c | 581 | /* ========== PORT definition for AC peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 582 | #define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ |
| Kojto | 111:4336505e4b1c | 583 | #define MUX_PA04B_AC_AIN0 1L |
| Kojto | 111:4336505e4b1c | 584 | #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) |
| Kojto | 111:4336505e4b1c | 585 | #define PORT_PA04B_AC_AIN0 (1ul << 4) |
| Kojto | 111:4336505e4b1c | 586 | #define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ |
| Kojto | 111:4336505e4b1c | 587 | #define MUX_PA05B_AC_AIN1 1L |
| Kojto | 111:4336505e4b1c | 588 | #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) |
| Kojto | 111:4336505e4b1c | 589 | #define PORT_PA05B_AC_AIN1 (1ul << 5) |
| Kojto | 111:4336505e4b1c | 590 | #define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ |
| Kojto | 111:4336505e4b1c | 591 | #define MUX_PA06B_AC_AIN2 1L |
| Kojto | 111:4336505e4b1c | 592 | #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) |
| Kojto | 111:4336505e4b1c | 593 | #define PORT_PA06B_AC_AIN2 (1ul << 6) |
| Kojto | 111:4336505e4b1c | 594 | #define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ |
| Kojto | 111:4336505e4b1c | 595 | #define MUX_PA07B_AC_AIN3 1L |
| Kojto | 111:4336505e4b1c | 596 | #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) |
| Kojto | 111:4336505e4b1c | 597 | #define PORT_PA07B_AC_AIN3 (1ul << 7) |
| Kojto | 111:4336505e4b1c | 598 | #define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ |
| Kojto | 111:4336505e4b1c | 599 | #define MUX_PA18H_AC_CMP0 7L |
| Kojto | 111:4336505e4b1c | 600 | #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) |
| Kojto | 111:4336505e4b1c | 601 | #define PORT_PA18H_AC_CMP0 (1ul << 18) |
| Kojto | 111:4336505e4b1c | 602 | #define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ |
| Kojto | 111:4336505e4b1c | 603 | #define MUX_PA19H_AC_CMP1 7L |
| Kojto | 111:4336505e4b1c | 604 | #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) |
| Kojto | 111:4336505e4b1c | 605 | #define PORT_PA19H_AC_CMP1 (1ul << 19) |
| Kojto | 111:4336505e4b1c | 606 | /* ========== PORT definition for DAC peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 607 | #define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ |
| Kojto | 111:4336505e4b1c | 608 | #define MUX_PA02B_DAC_VOUT 1L |
| Kojto | 111:4336505e4b1c | 609 | #define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) |
| Kojto | 111:4336505e4b1c | 610 | #define PORT_PA02B_DAC_VOUT (1ul << 2) |
| Kojto | 111:4336505e4b1c | 611 | #define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ |
| Kojto | 111:4336505e4b1c | 612 | #define MUX_PA03B_DAC_VREFP 1L |
| Kojto | 111:4336505e4b1c | 613 | #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) |
| Kojto | 111:4336505e4b1c | 614 | #define PORT_PA03B_DAC_VREFP (1ul << 3) |
| Kojto | 111:4336505e4b1c | 615 | /* ========== PORT definition for I2S peripheral ========== */ |
| Kojto | 111:4336505e4b1c | 616 | #define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ |
| Kojto | 111:4336505e4b1c | 617 | #define MUX_PA11G_I2S_FS0 6L |
| Kojto | 111:4336505e4b1c | 618 | #define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) |
| Kojto | 111:4336505e4b1c | 619 | #define PORT_PA11G_I2S_FS0 (1ul << 11) |
| Kojto | 111:4336505e4b1c | 620 | #define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ |
| Kojto | 111:4336505e4b1c | 621 | #define MUX_PA09G_I2S_MCK0 6L |
| Kojto | 111:4336505e4b1c | 622 | #define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) |
| Kojto | 111:4336505e4b1c | 623 | #define PORT_PA09G_I2S_MCK0 (1ul << 9) |
| Kojto | 111:4336505e4b1c | 624 | #define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ |
| Kojto | 111:4336505e4b1c | 625 | #define MUX_PA10G_I2S_SCK0 6L |
| Kojto | 111:4336505e4b1c | 626 | #define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) |
| Kojto | 111:4336505e4b1c | 627 | #define PORT_PA10G_I2S_SCK0 (1ul << 10) |
| Kojto | 111:4336505e4b1c | 628 | #define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ |
| Kojto | 111:4336505e4b1c | 629 | #define MUX_PA07G_I2S_SD0 6L |
| Kojto | 111:4336505e4b1c | 630 | #define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) |
| Kojto | 111:4336505e4b1c | 631 | #define PORT_PA07G_I2S_SD0 (1ul << 7) |
| Kojto | 111:4336505e4b1c | 632 | #define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ |
| Kojto | 111:4336505e4b1c | 633 | #define MUX_PA19G_I2S_SD0 6L |
| Kojto | 111:4336505e4b1c | 634 | #define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) |
| Kojto | 111:4336505e4b1c | 635 | #define PORT_PA19G_I2S_SD0 (1ul << 19) |
| Kojto | 111:4336505e4b1c | 636 | #define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ |
| Kojto | 111:4336505e4b1c | 637 | #define MUX_PA08G_I2S_SD1 6L |
| Kojto | 111:4336505e4b1c | 638 | #define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) |
| Kojto | 111:4336505e4b1c | 639 | #define PORT_PA08G_I2S_SD1 (1ul << 8) |
| Kojto | 111:4336505e4b1c | 640 | |
| Kojto | 111:4336505e4b1c | 641 | #endif /* _SAMD21E15B_PIO_ */ |