Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_SAMD21G18A/ins_tcc2.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
111:4336505e4b1c 
.

Who changed what in which revision?

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Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Instance description for TCC2
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43 /*
Kojto 111:4336505e4b1c 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
Kojto 111:4336505e4b1c 45 */
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 #ifndef _SAMD21_TCC2_INSTANCE_
Kojto 111:4336505e4b1c 48 #define _SAMD21_TCC2_INSTANCE_
Kojto 111:4336505e4b1c 49
Kojto 111:4336505e4b1c 50 /* ========== Register definition for TCC2 peripheral ========== */
Kojto 111:4336505e4b1c 51 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 52 #define REG_TCC2_CTRLA (0x42002800U) /**< \brief (TCC2) Control A */
Kojto 111:4336505e4b1c 53 #define REG_TCC2_CTRLBCLR (0x42002804U) /**< \brief (TCC2) Control B Clear */
Kojto 111:4336505e4b1c 54 #define REG_TCC2_CTRLBSET (0x42002805U) /**< \brief (TCC2) Control B Set */
Kojto 111:4336505e4b1c 55 #define REG_TCC2_SYNCBUSY (0x42002808U) /**< \brief (TCC2) Synchronization Busy */
Kojto 111:4336505e4b1c 56 #define REG_TCC2_FCTRLA (0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
Kojto 111:4336505e4b1c 57 #define REG_TCC2_FCTRLB (0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
Kojto 111:4336505e4b1c 58 #define REG_TCC2_DRVCTRL (0x42002818U) /**< \brief (TCC2) Driver Control */
Kojto 111:4336505e4b1c 59 #define REG_TCC2_DBGCTRL (0x4200281EU) /**< \brief (TCC2) Debug Control */
Kojto 111:4336505e4b1c 60 #define REG_TCC2_EVCTRL (0x42002820U) /**< \brief (TCC2) Event Control */
Kojto 111:4336505e4b1c 61 #define REG_TCC2_INTENCLR (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 62 #define REG_TCC2_INTENSET (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
Kojto 111:4336505e4b1c 63 #define REG_TCC2_INTFLAG (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 64 #define REG_TCC2_STATUS (0x42002830U) /**< \brief (TCC2) Status */
Kojto 111:4336505e4b1c 65 #define REG_TCC2_COUNT (0x42002834U) /**< \brief (TCC2) Count */
Kojto 111:4336505e4b1c 66 #define REG_TCC2_WAVE (0x4200283CU) /**< \brief (TCC2) Waveform Control */
Kojto 111:4336505e4b1c 67 #define REG_TCC2_PER (0x42002840U) /**< \brief (TCC2) Period */
Kojto 111:4336505e4b1c 68 #define REG_TCC2_CC0 (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
Kojto 111:4336505e4b1c 69 #define REG_TCC2_CC1 (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
Kojto 111:4336505e4b1c 70 #define REG_TCC2_WAVEB (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
Kojto 111:4336505e4b1c 71 #define REG_TCC2_PERB (0x4200286CU) /**< \brief (TCC2) Period Buffer */
Kojto 111:4336505e4b1c 72 #define REG_TCC2_CCB0 (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
Kojto 111:4336505e4b1c 73 #define REG_TCC2_CCB1 (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
Kojto 111:4336505e4b1c 74 #else
Kojto 111:4336505e4b1c 75 #define REG_TCC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TCC2) Control A */
Kojto 111:4336505e4b1c 76 #define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */
Kojto 111:4336505e4b1c 77 #define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */
Kojto 111:4336505e4b1c 78 #define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */
Kojto 111:4336505e4b1c 79 #define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
Kojto 111:4336505e4b1c 80 #define REG_TCC2_FCTRLB (*(RwReg *)0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
Kojto 111:4336505e4b1c 81 #define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818U) /**< \brief (TCC2) Driver Control */
Kojto 111:4336505e4b1c 82 #define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */
Kojto 111:4336505e4b1c 83 #define REG_TCC2_EVCTRL (*(RwReg *)0x42002820U) /**< \brief (TCC2) Event Control */
Kojto 111:4336505e4b1c 84 #define REG_TCC2_INTENCLR (*(RwReg *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 85 #define REG_TCC2_INTENSET (*(RwReg *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
Kojto 111:4336505e4b1c 86 #define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 87 #define REG_TCC2_STATUS (*(RwReg *)0x42002830U) /**< \brief (TCC2) Status */
Kojto 111:4336505e4b1c 88 #define REG_TCC2_COUNT (*(RwReg *)0x42002834U) /**< \brief (TCC2) Count */
Kojto 111:4336505e4b1c 89 #define REG_TCC2_WAVE (*(RwReg *)0x4200283CU) /**< \brief (TCC2) Waveform Control */
Kojto 111:4336505e4b1c 90 #define REG_TCC2_PER (*(RwReg *)0x42002840U) /**< \brief (TCC2) Period */
Kojto 111:4336505e4b1c 91 #define REG_TCC2_CC0 (*(RwReg *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
Kojto 111:4336505e4b1c 92 #define REG_TCC2_CC1 (*(RwReg *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
Kojto 111:4336505e4b1c 93 #define REG_TCC2_WAVEB (*(RwReg *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
Kojto 111:4336505e4b1c 94 #define REG_TCC2_PERB (*(RwReg *)0x4200286CU) /**< \brief (TCC2) Period Buffer */
Kojto 111:4336505e4b1c 95 #define REG_TCC2_CCB0 (*(RwReg *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
Kojto 111:4336505e4b1c 96 #define REG_TCC2_CCB1 (*(RwReg *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
Kojto 111:4336505e4b1c 97 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 98
Kojto 111:4336505e4b1c 99 /* ========== Instance parameters for TCC2 peripheral ========== */
Kojto 111:4336505e4b1c 100 #define TCC2_CC_NUM 2 // Number of Compare/Capture units
Kojto 111:4336505e4b1c 101 #define TCC2_DITHERING 0 // Dithering feature implemented
Kojto 111:4336505e4b1c 102 #define TCC2_DMAC_ID_MC_0 22
Kojto 111:4336505e4b1c 103 #define TCC2_DMAC_ID_MC_1 23
Kojto 111:4336505e4b1c 104 #define TCC2_DMAC_ID_MC_LSB 22
Kojto 111:4336505e4b1c 105 #define TCC2_DMAC_ID_MC_MSB 23
Kojto 111:4336505e4b1c 106 #define TCC2_DMAC_ID_MC_SIZE 2
Kojto 111:4336505e4b1c 107 #define TCC2_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger
Kojto 111:4336505e4b1c 108 #define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
Kojto 111:4336505e4b1c 109 #define TCC2_EXT 0 // Coding of implemented extended features
Kojto 111:4336505e4b1c 110 #define TCC2_GCLK_ID 27 // Index of Generic Clock
Kojto 111:4336505e4b1c 111 #define TCC2_MASTER 0
Kojto 111:4336505e4b1c 112 #define TCC2_OTMX 0 // Output Matrix feature implemented
Kojto 111:4336505e4b1c 113 #define TCC2_OW_NUM 2 // Number of Output Waveforms
Kojto 111:4336505e4b1c 114 #define TCC2_PG 0 // Pattern Generation feature implemented
Kojto 111:4336505e4b1c 115 #define TCC2_SIZE 16
Kojto 111:4336505e4b1c 116 #define TCC2_SWAP 0 // DTI outputs swap feature implemented
Kojto 111:4336505e4b1c 117 #define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
Kojto 111:4336505e4b1c 118
Kojto 111:4336505e4b1c 119 #endif /* _SAMD21_TCC2_INSTANCE_ */