Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_SAMD21G18A/comp_usb.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
111:4336505e4b1c 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for USB
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43 /*
Kojto 111:4336505e4b1c 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
Kojto 111:4336505e4b1c 45 */
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 #ifndef _SAMD21_USB_COMPONENT_
Kojto 111:4336505e4b1c 48 #define _SAMD21_USB_COMPONENT_
Kojto 111:4336505e4b1c 49
Kojto 111:4336505e4b1c 50 /* ========================================================================== */
Kojto 111:4336505e4b1c 51 /** SOFTWARE API DEFINITION FOR USB */
Kojto 111:4336505e4b1c 52 /* ========================================================================== */
Kojto 111:4336505e4b1c 53 /** \addtogroup SAMD21_USB Universal Serial Bus */
Kojto 111:4336505e4b1c 54 /*@{*/
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 #define USB_U2222
Kojto 111:4336505e4b1c 57 #define REV_USB 0x103
Kojto 111:4336505e4b1c 58
Kojto 111:4336505e4b1c 59 /* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
Kojto 111:4336505e4b1c 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 61 typedef union {
Kojto 111:4336505e4b1c 62 struct {
Kojto 111:4336505e4b1c 63 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 64 uint8_t ENABLE:1; /*!< bit: 1 Enable */
Kojto 111:4336505e4b1c 65 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
Kojto 111:4336505e4b1c 66 uint8_t :4; /*!< bit: 3.. 6 Reserved */
Kojto 111:4336505e4b1c 67 uint8_t MODE:1; /*!< bit: 7 Operating Mode */
Kojto 111:4336505e4b1c 68 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 69 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 70 } USB_CTRLA_Type;
Kojto 111:4336505e4b1c 71 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 72
Kojto 111:4336505e4b1c 73 #define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */
Kojto 111:4336505e4b1c 74 #define USB_CTRLA_RESETVALUE 0x00ul /**< \brief (USB_CTRLA reset_value) Control A */
Kojto 111:4336505e4b1c 75
Kojto 111:4336505e4b1c 76 #define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */
Kojto 111:4336505e4b1c 77 #define USB_CTRLA_SWRST (0x1ul << USB_CTRLA_SWRST_Pos)
Kojto 111:4336505e4b1c 78 #define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */
Kojto 111:4336505e4b1c 79 #define USB_CTRLA_ENABLE (0x1ul << USB_CTRLA_ENABLE_Pos)
Kojto 111:4336505e4b1c 80 #define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */
Kojto 111:4336505e4b1c 81 #define USB_CTRLA_RUNSTDBY (0x1ul << USB_CTRLA_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 82 #define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */
Kojto 111:4336505e4b1c 83 #define USB_CTRLA_MODE (0x1ul << USB_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 84 #define USB_CTRLA_MODE_DEVICE_Val 0x0ul /**< \brief (USB_CTRLA) Device Mode */
Kojto 111:4336505e4b1c 85 #define USB_CTRLA_MODE_HOST_Val 0x1ul /**< \brief (USB_CTRLA) Host Mode */
Kojto 111:4336505e4b1c 86 #define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 87 #define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 88 #define USB_CTRLA_MASK 0x87ul /**< \brief (USB_CTRLA) MASK Register */
Kojto 111:4336505e4b1c 89
Kojto 111:4336505e4b1c 90 /* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
Kojto 111:4336505e4b1c 91 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 92 typedef union {
Kojto 111:4336505e4b1c 93 struct {
Kojto 111:4336505e4b1c 94 uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
Kojto 111:4336505e4b1c 95 uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
Kojto 111:4336505e4b1c 96 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 97 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 98 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 99 } USB_SYNCBUSY_Type;
Kojto 111:4336505e4b1c 100 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 101
Kojto 111:4336505e4b1c 102 #define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
Kojto 111:4336505e4b1c 103 #define USB_SYNCBUSY_RESETVALUE 0x00ul /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
Kojto 111:4336505e4b1c 104
Kojto 111:4336505e4b1c 105 #define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
Kojto 111:4336505e4b1c 106 #define USB_SYNCBUSY_SWRST (0x1ul << USB_SYNCBUSY_SWRST_Pos)
Kojto 111:4336505e4b1c 107 #define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
Kojto 111:4336505e4b1c 108 #define USB_SYNCBUSY_ENABLE (0x1ul << USB_SYNCBUSY_ENABLE_Pos)
Kojto 111:4336505e4b1c 109 #define USB_SYNCBUSY_MASK 0x03ul /**< \brief (USB_SYNCBUSY) MASK Register */
Kojto 111:4336505e4b1c 110
Kojto 111:4336505e4b1c 111 /* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */
Kojto 111:4336505e4b1c 112 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 113 typedef union {
Kojto 111:4336505e4b1c 114 struct {
Kojto 111:4336505e4b1c 115 uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
Kojto 111:4336505e4b1c 116 uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
Kojto 111:4336505e4b1c 117 uint8_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 118 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 119 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 120 } USB_QOSCTRL_Type;
Kojto 111:4336505e4b1c 121 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 122
Kojto 111:4336505e4b1c 123 #define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
Kojto 111:4336505e4b1c 124 #define USB_QOSCTRL_RESETVALUE 0x05ul /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
Kojto 111:4336505e4b1c 125
Kojto 111:4336505e4b1c 126 #define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
Kojto 111:4336505e4b1c 127 #define USB_QOSCTRL_CQOS_Msk (0x3ul << USB_QOSCTRL_CQOS_Pos)
Kojto 111:4336505e4b1c 128 #define USB_QOSCTRL_CQOS(value) ((USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos)))
Kojto 111:4336505e4b1c 129 #define USB_QOSCTRL_CQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
Kojto 111:4336505e4b1c 130 #define USB_QOSCTRL_CQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
Kojto 111:4336505e4b1c 131 #define USB_QOSCTRL_CQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */
Kojto 111:4336505e4b1c 132 #define USB_QOSCTRL_CQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */
Kojto 111:4336505e4b1c 133 #define USB_QOSCTRL_CQOS_DISABLE (USB_QOSCTRL_CQOS_DISABLE_Val << USB_QOSCTRL_CQOS_Pos)
Kojto 111:4336505e4b1c 134 #define USB_QOSCTRL_CQOS_LOW (USB_QOSCTRL_CQOS_LOW_Val << USB_QOSCTRL_CQOS_Pos)
Kojto 111:4336505e4b1c 135 #define USB_QOSCTRL_CQOS_MEDIUM (USB_QOSCTRL_CQOS_MEDIUM_Val << USB_QOSCTRL_CQOS_Pos)
Kojto 111:4336505e4b1c 136 #define USB_QOSCTRL_CQOS_HIGH (USB_QOSCTRL_CQOS_HIGH_Val << USB_QOSCTRL_CQOS_Pos)
Kojto 111:4336505e4b1c 137 #define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */
Kojto 111:4336505e4b1c 138 #define USB_QOSCTRL_DQOS_Msk (0x3ul << USB_QOSCTRL_DQOS_Pos)
Kojto 111:4336505e4b1c 139 #define USB_QOSCTRL_DQOS(value) ((USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos)))
Kojto 111:4336505e4b1c 140 #define USB_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
Kojto 111:4336505e4b1c 141 #define USB_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
Kojto 111:4336505e4b1c 142 #define USB_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */
Kojto 111:4336505e4b1c 143 #define USB_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */
Kojto 111:4336505e4b1c 144 #define USB_QOSCTRL_DQOS_DISABLE (USB_QOSCTRL_DQOS_DISABLE_Val << USB_QOSCTRL_DQOS_Pos)
Kojto 111:4336505e4b1c 145 #define USB_QOSCTRL_DQOS_LOW (USB_QOSCTRL_DQOS_LOW_Val << USB_QOSCTRL_DQOS_Pos)
Kojto 111:4336505e4b1c 146 #define USB_QOSCTRL_DQOS_MEDIUM (USB_QOSCTRL_DQOS_MEDIUM_Val << USB_QOSCTRL_DQOS_Pos)
Kojto 111:4336505e4b1c 147 #define USB_QOSCTRL_DQOS_HIGH (USB_QOSCTRL_DQOS_HIGH_Val << USB_QOSCTRL_DQOS_Pos)
Kojto 111:4336505e4b1c 148 #define USB_QOSCTRL_MASK 0x0Ful /**< \brief (USB_QOSCTRL) MASK Register */
Kojto 111:4336505e4b1c 149
Kojto 111:4336505e4b1c 150 /* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
Kojto 111:4336505e4b1c 151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 152 typedef union {
Kojto 111:4336505e4b1c 153 struct {
Kojto 111:4336505e4b1c 154 uint16_t DETACH:1; /*!< bit: 0 Detach */
Kojto 111:4336505e4b1c 155 uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
Kojto 111:4336505e4b1c 156 uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
Kojto 111:4336505e4b1c 157 uint16_t NREPLY:1; /*!< bit: 4 No Reply */
Kojto 111:4336505e4b1c 158 uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
Kojto 111:4336505e4b1c 159 uint16_t TSTK:1; /*!< bit: 6 Test mode K */
Kojto 111:4336505e4b1c 160 uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
Kojto 111:4336505e4b1c 161 uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
Kojto 111:4336505e4b1c 162 uint16_t GNAK:1; /*!< bit: 9 Global NAK */
Kojto 111:4336505e4b1c 163 uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
Kojto 111:4336505e4b1c 164 uint16_t :4; /*!< bit: 12..15 Reserved */
Kojto 111:4336505e4b1c 165 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 166 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 167 } USB_DEVICE_CTRLB_Type;
Kojto 111:4336505e4b1c 168 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 169
Kojto 111:4336505e4b1c 170 #define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
Kojto 111:4336505e4b1c 171 #define USB_DEVICE_CTRLB_RESETVALUE 0x0001ul /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
Kojto 111:4336505e4b1c 172
Kojto 111:4336505e4b1c 173 #define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */
Kojto 111:4336505e4b1c 174 #define USB_DEVICE_CTRLB_DETACH (0x1ul << USB_DEVICE_CTRLB_DETACH_Pos)
Kojto 111:4336505e4b1c 175 #define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
Kojto 111:4336505e4b1c 176 #define USB_DEVICE_CTRLB_UPRSM (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos)
Kojto 111:4336505e4b1c 177 #define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
Kojto 111:4336505e4b1c 178 #define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos)
Kojto 111:4336505e4b1c 179 #define USB_DEVICE_CTRLB_SPDCONF(value) ((USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos)))
Kojto 111:4336505e4b1c 180 #define USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
Kojto 111:4336505e4b1c 181 #define USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
Kojto 111:4336505e4b1c 182 #define USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
Kojto 111:4336505e4b1c 183 #define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
Kojto 111:4336505e4b1c 184 #define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
Kojto 111:4336505e4b1c 185 #define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
Kojto 111:4336505e4b1c 186 #define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
Kojto 111:4336505e4b1c 187 #define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
Kojto 111:4336505e4b1c 188 #define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */
Kojto 111:4336505e4b1c 189 #define USB_DEVICE_CTRLB_NREPLY (0x1ul << USB_DEVICE_CTRLB_NREPLY_Pos)
Kojto 111:4336505e4b1c 190 #define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */
Kojto 111:4336505e4b1c 191 #define USB_DEVICE_CTRLB_TSTJ (0x1ul << USB_DEVICE_CTRLB_TSTJ_Pos)
Kojto 111:4336505e4b1c 192 #define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */
Kojto 111:4336505e4b1c 193 #define USB_DEVICE_CTRLB_TSTK (0x1ul << USB_DEVICE_CTRLB_TSTK_Pos)
Kojto 111:4336505e4b1c 194 #define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
Kojto 111:4336505e4b1c 195 #define USB_DEVICE_CTRLB_TSTPCKT (0x1ul << USB_DEVICE_CTRLB_TSTPCKT_Pos)
Kojto 111:4336505e4b1c 196 #define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
Kojto 111:4336505e4b1c 197 #define USB_DEVICE_CTRLB_OPMODE2 (0x1ul << USB_DEVICE_CTRLB_OPMODE2_Pos)
Kojto 111:4336505e4b1c 198 #define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */
Kojto 111:4336505e4b1c 199 #define USB_DEVICE_CTRLB_GNAK (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos)
Kojto 111:4336505e4b1c 200 #define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
Kojto 111:4336505e4b1c 201 #define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos)
Kojto 111:4336505e4b1c 202 #define USB_DEVICE_CTRLB_LPMHDSK(value) ((USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos)))
Kojto 111:4336505e4b1c 203 #define USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
Kojto 111:4336505e4b1c 204 #define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) ACK */
Kojto 111:4336505e4b1c 205 #define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) NYET */
Kojto 111:4336505e4b1c 206 #define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) STALL */
Kojto 111:4336505e4b1c 207 #define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
Kojto 111:4336505e4b1c 208 #define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
Kojto 111:4336505e4b1c 209 #define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
Kojto 111:4336505e4b1c 210 #define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
Kojto 111:4336505e4b1c 211 #define USB_DEVICE_CTRLB_MASK 0x0FFFul /**< \brief (USB_DEVICE_CTRLB) MASK Register */
Kojto 111:4336505e4b1c 212
Kojto 111:4336505e4b1c 213 /* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
Kojto 111:4336505e4b1c 214 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 215 typedef union {
Kojto 111:4336505e4b1c 216 struct {
Kojto 111:4336505e4b1c 217 uint16_t :1; /*!< bit: 0 Reserved */
Kojto 111:4336505e4b1c 218 uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
Kojto 111:4336505e4b1c 219 uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
Kojto 111:4336505e4b1c 220 uint16_t :1; /*!< bit: 4 Reserved */
Kojto 111:4336505e4b1c 221 uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
Kojto 111:4336505e4b1c 222 uint16_t TSTK:1; /*!< bit: 6 Test mode K */
Kojto 111:4336505e4b1c 223 uint16_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 224 uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
Kojto 111:4336505e4b1c 225 uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
Kojto 111:4336505e4b1c 226 uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
Kojto 111:4336505e4b1c 227 uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
Kojto 111:4336505e4b1c 228 uint16_t :4; /*!< bit: 12..15 Reserved */
Kojto 111:4336505e4b1c 229 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 230 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 231 } USB_HOST_CTRLB_Type;
Kojto 111:4336505e4b1c 232 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 233
Kojto 111:4336505e4b1c 234 #define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
Kojto 111:4336505e4b1c 235 #define USB_HOST_CTRLB_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
Kojto 111:4336505e4b1c 236
Kojto 111:4336505e4b1c 237 #define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */
Kojto 111:4336505e4b1c 238 #define USB_HOST_CTRLB_RESUME (0x1ul << USB_HOST_CTRLB_RESUME_Pos)
Kojto 111:4336505e4b1c 239 #define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
Kojto 111:4336505e4b1c 240 #define USB_HOST_CTRLB_SPDCONF_Msk (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos)
Kojto 111:4336505e4b1c 241 #define USB_HOST_CTRLB_SPDCONF(value) ((USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos)))
Kojto 111:4336505e4b1c 242 #define USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
Kojto 111:4336505e4b1c 243 #define USB_HOST_CTRLB_SPDCONF_FS_Val 0x3ul /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
Kojto 111:4336505e4b1c 244 #define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
Kojto 111:4336505e4b1c 245 #define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
Kojto 111:4336505e4b1c 246 #define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */
Kojto 111:4336505e4b1c 247 #define USB_HOST_CTRLB_TSTJ (0x1ul << USB_HOST_CTRLB_TSTJ_Pos)
Kojto 111:4336505e4b1c 248 #define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */
Kojto 111:4336505e4b1c 249 #define USB_HOST_CTRLB_TSTK (0x1ul << USB_HOST_CTRLB_TSTK_Pos)
Kojto 111:4336505e4b1c 250 #define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
Kojto 111:4336505e4b1c 251 #define USB_HOST_CTRLB_SOFE (0x1ul << USB_HOST_CTRLB_SOFE_Pos)
Kojto 111:4336505e4b1c 252 #define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */
Kojto 111:4336505e4b1c 253 #define USB_HOST_CTRLB_BUSRESET (0x1ul << USB_HOST_CTRLB_BUSRESET_Pos)
Kojto 111:4336505e4b1c 254 #define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */
Kojto 111:4336505e4b1c 255 #define USB_HOST_CTRLB_VBUSOK (0x1ul << USB_HOST_CTRLB_VBUSOK_Pos)
Kojto 111:4336505e4b1c 256 #define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
Kojto 111:4336505e4b1c 257 #define USB_HOST_CTRLB_L1RESUME (0x1ul << USB_HOST_CTRLB_L1RESUME_Pos)
Kojto 111:4336505e4b1c 258 #define USB_HOST_CTRLB_MASK 0x0F6Eul /**< \brief (USB_HOST_CTRLB) MASK Register */
Kojto 111:4336505e4b1c 259
Kojto 111:4336505e4b1c 260 /* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
Kojto 111:4336505e4b1c 261 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 262 typedef union {
Kojto 111:4336505e4b1c 263 struct {
Kojto 111:4336505e4b1c 264 uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
Kojto 111:4336505e4b1c 265 uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
Kojto 111:4336505e4b1c 266 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 267 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 268 } USB_DEVICE_DADD_Type;
Kojto 111:4336505e4b1c 269 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 270
Kojto 111:4336505e4b1c 271 #define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
Kojto 111:4336505e4b1c 272 #define USB_DEVICE_DADD_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
Kojto 111:4336505e4b1c 273
Kojto 111:4336505e4b1c 274 #define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */
Kojto 111:4336505e4b1c 275 #define USB_DEVICE_DADD_DADD_Msk (0x7Ful << USB_DEVICE_DADD_DADD_Pos)
Kojto 111:4336505e4b1c 276 #define USB_DEVICE_DADD_DADD(value) ((USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos)))
Kojto 111:4336505e4b1c 277 #define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */
Kojto 111:4336505e4b1c 278 #define USB_DEVICE_DADD_ADDEN (0x1ul << USB_DEVICE_DADD_ADDEN_Pos)
Kojto 111:4336505e4b1c 279 #define USB_DEVICE_DADD_MASK 0xFFul /**< \brief (USB_DEVICE_DADD) MASK Register */
Kojto 111:4336505e4b1c 280
Kojto 111:4336505e4b1c 281 /* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
Kojto 111:4336505e4b1c 282 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 283 typedef union {
Kojto 111:4336505e4b1c 284 struct {
Kojto 111:4336505e4b1c 285 uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
Kojto 111:4336505e4b1c 286 uint8_t :3; /*!< bit: 4.. 6 Reserved */
Kojto 111:4336505e4b1c 287 uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
Kojto 111:4336505e4b1c 288 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 289 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 290 } USB_HOST_HSOFC_Type;
Kojto 111:4336505e4b1c 291 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 292
Kojto 111:4336505e4b1c 293 #define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
Kojto 111:4336505e4b1c 294 #define USB_HOST_HSOFC_RESETVALUE 0x00ul /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
Kojto 111:4336505e4b1c 295
Kojto 111:4336505e4b1c 296 #define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */
Kojto 111:4336505e4b1c 297 #define USB_HOST_HSOFC_FLENC_Msk (0xFul << USB_HOST_HSOFC_FLENC_Pos)
Kojto 111:4336505e4b1c 298 #define USB_HOST_HSOFC_FLENC(value) ((USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos)))
Kojto 111:4336505e4b1c 299 #define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
Kojto 111:4336505e4b1c 300 #define USB_HOST_HSOFC_FLENCE (0x1ul << USB_HOST_HSOFC_FLENCE_Pos)
Kojto 111:4336505e4b1c 301 #define USB_HOST_HSOFC_MASK 0x8Ful /**< \brief (USB_HOST_HSOFC) MASK Register */
Kojto 111:4336505e4b1c 302
Kojto 111:4336505e4b1c 303 /* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
Kojto 111:4336505e4b1c 304 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 305 typedef union {
Kojto 111:4336505e4b1c 306 struct {
Kojto 111:4336505e4b1c 307 uint8_t :2; /*!< bit: 0.. 1 Reserved */
Kojto 111:4336505e4b1c 308 uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
Kojto 111:4336505e4b1c 309 uint8_t :2; /*!< bit: 4.. 5 Reserved */
Kojto 111:4336505e4b1c 310 uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
Kojto 111:4336505e4b1c 311 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 312 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 313 } USB_DEVICE_STATUS_Type;
Kojto 111:4336505e4b1c 314 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 315
Kojto 111:4336505e4b1c 316 #define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
Kojto 111:4336505e4b1c 317 #define USB_DEVICE_STATUS_RESETVALUE 0x40ul /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
Kojto 111:4336505e4b1c 318
Kojto 111:4336505e4b1c 319 #define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */
Kojto 111:4336505e4b1c 320 #define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos)
Kojto 111:4336505e4b1c 321 #define USB_DEVICE_STATUS_SPEED(value) ((USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos)))
Kojto 111:4336505e4b1c 322 #define USB_DEVICE_STATUS_SPEED_FS_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
Kojto 111:4336505e4b1c 323 #define USB_DEVICE_STATUS_SPEED_HS_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) High-speed mode */
Kojto 111:4336505e4b1c 324 #define USB_DEVICE_STATUS_SPEED_LS_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
Kojto 111:4336505e4b1c 325 #define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
Kojto 111:4336505e4b1c 326 #define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
Kojto 111:4336505e4b1c 327 #define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
Kojto 111:4336505e4b1c 328 #define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
Kojto 111:4336505e4b1c 329 #define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos)
Kojto 111:4336505e4b1c 330 #define USB_DEVICE_STATUS_LINESTATE(value) ((USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos)))
Kojto 111:4336505e4b1c 331 #define USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
Kojto 111:4336505e4b1c 332 #define USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
Kojto 111:4336505e4b1c 333 #define USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
Kojto 111:4336505e4b1c 334 #define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
Kojto 111:4336505e4b1c 335 #define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
Kojto 111:4336505e4b1c 336 #define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
Kojto 111:4336505e4b1c 337 #define USB_DEVICE_STATUS_MASK 0xCCul /**< \brief (USB_DEVICE_STATUS) MASK Register */
Kojto 111:4336505e4b1c 338
Kojto 111:4336505e4b1c 339 /* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
Kojto 111:4336505e4b1c 340 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 341 typedef union {
Kojto 111:4336505e4b1c 342 struct {
Kojto 111:4336505e4b1c 343 uint8_t :2; /*!< bit: 0.. 1 Reserved */
Kojto 111:4336505e4b1c 344 uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
Kojto 111:4336505e4b1c 345 uint8_t :2; /*!< bit: 4.. 5 Reserved */
Kojto 111:4336505e4b1c 346 uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
Kojto 111:4336505e4b1c 347 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 348 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 349 } USB_HOST_STATUS_Type;
Kojto 111:4336505e4b1c 350 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 351
Kojto 111:4336505e4b1c 352 #define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */
Kojto 111:4336505e4b1c 353 #define USB_HOST_STATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
Kojto 111:4336505e4b1c 354
Kojto 111:4336505e4b1c 355 #define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */
Kojto 111:4336505e4b1c 356 #define USB_HOST_STATUS_SPEED_Msk (0x3ul << USB_HOST_STATUS_SPEED_Pos)
Kojto 111:4336505e4b1c 357 #define USB_HOST_STATUS_SPEED(value) ((USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos)))
Kojto 111:4336505e4b1c 358 #define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */
Kojto 111:4336505e4b1c 359 #define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos)
Kojto 111:4336505e4b1c 360 #define USB_HOST_STATUS_LINESTATE(value) ((USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos)))
Kojto 111:4336505e4b1c 361 #define USB_HOST_STATUS_MASK 0xCCul /**< \brief (USB_HOST_STATUS) MASK Register */
Kojto 111:4336505e4b1c 362
Kojto 111:4336505e4b1c 363 /* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
Kojto 111:4336505e4b1c 364 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 365 typedef union {
Kojto 111:4336505e4b1c 366 struct {
Kojto 111:4336505e4b1c 367 uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
Kojto 111:4336505e4b1c 368 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 369 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 370 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 371 } USB_FSMSTATUS_Type;
Kojto 111:4336505e4b1c 372 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 373
Kojto 111:4336505e4b1c 374 #define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
Kojto 111:4336505e4b1c 375 #define USB_FSMSTATUS_RESETVALUE 0x01ul /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
Kojto 111:4336505e4b1c 376
Kojto 111:4336505e4b1c 377 #define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
Kojto 111:4336505e4b1c 378 #define USB_FSMSTATUS_FSMSTATE_Msk (0x3Ful << USB_FSMSTATUS_FSMSTATE_Pos)
Kojto 111:4336505e4b1c 379 #define USB_FSMSTATUS_FSMSTATE(value) ((USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos)))
Kojto 111:4336505e4b1c 380 #define USB_FSMSTATUS_FSMSTATE_OFF_Val 0x1ul /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
Kojto 111:4336505e4b1c 381 #define USB_FSMSTATUS_FSMSTATE_ON_Val 0x2ul /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
Kojto 111:4336505e4b1c 382 #define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
Kojto 111:4336505e4b1c 383 #define USB_FSMSTATUS_FSMSTATE_SLEEP_Val 0x8ul /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
Kojto 111:4336505e4b1c 384 #define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val 0x10ul /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
Kojto 111:4336505e4b1c 385 #define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val 0x20ul /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
Kojto 111:4336505e4b1c 386 #define USB_FSMSTATUS_FSMSTATE_RESET_Val 0x40ul /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
Kojto 111:4336505e4b1c 387 #define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
Kojto 111:4336505e4b1c 388 #define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
Kojto 111:4336505e4b1c 389 #define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
Kojto 111:4336505e4b1c 390 #define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
Kojto 111:4336505e4b1c 391 #define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
Kojto 111:4336505e4b1c 392 #define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
Kojto 111:4336505e4b1c 393 #define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
Kojto 111:4336505e4b1c 394 #define USB_FSMSTATUS_MASK 0x3Ful /**< \brief (USB_FSMSTATUS) MASK Register */
Kojto 111:4336505e4b1c 395
Kojto 111:4336505e4b1c 396 /* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
Kojto 111:4336505e4b1c 397 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 398 typedef union {
Kojto 111:4336505e4b1c 399 struct {
Kojto 111:4336505e4b1c 400 uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
Kojto 111:4336505e4b1c 401 uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
Kojto 111:4336505e4b1c 402 uint16_t :1; /*!< bit: 14 Reserved */
Kojto 111:4336505e4b1c 403 uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
Kojto 111:4336505e4b1c 404 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 405 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 406 } USB_DEVICE_FNUM_Type;
Kojto 111:4336505e4b1c 407 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 408
Kojto 111:4336505e4b1c 409 #define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
Kojto 111:4336505e4b1c 410 #define USB_DEVICE_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
Kojto 111:4336505e4b1c 411
Kojto 111:4336505e4b1c 412 #define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
Kojto 111:4336505e4b1c 413 #define USB_DEVICE_FNUM_MFNUM_Msk (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos)
Kojto 111:4336505e4b1c 414 #define USB_DEVICE_FNUM_MFNUM(value) ((USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos)))
Kojto 111:4336505e4b1c 415 #define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */
Kojto 111:4336505e4b1c 416 #define USB_DEVICE_FNUM_FNUM_Msk (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos)
Kojto 111:4336505e4b1c 417 #define USB_DEVICE_FNUM_FNUM(value) ((USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos)))
Kojto 111:4336505e4b1c 418 #define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
Kojto 111:4336505e4b1c 419 #define USB_DEVICE_FNUM_FNCERR (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos)
Kojto 111:4336505e4b1c 420 #define USB_DEVICE_FNUM_MASK 0xBFFFul /**< \brief (USB_DEVICE_FNUM) MASK Register */
Kojto 111:4336505e4b1c 421
Kojto 111:4336505e4b1c 422 /* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
Kojto 111:4336505e4b1c 423 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 424 typedef union {
Kojto 111:4336505e4b1c 425 struct {
Kojto 111:4336505e4b1c 426 uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
Kojto 111:4336505e4b1c 427 uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
Kojto 111:4336505e4b1c 428 uint16_t :2; /*!< bit: 14..15 Reserved */
Kojto 111:4336505e4b1c 429 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 430 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 431 } USB_HOST_FNUM_Type;
Kojto 111:4336505e4b1c 432 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 433
Kojto 111:4336505e4b1c 434 #define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
Kojto 111:4336505e4b1c 435 #define USB_HOST_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
Kojto 111:4336505e4b1c 436
Kojto 111:4336505e4b1c 437 #define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */
Kojto 111:4336505e4b1c 438 #define USB_HOST_FNUM_MFNUM_Msk (0x7ul << USB_HOST_FNUM_MFNUM_Pos)
Kojto 111:4336505e4b1c 439 #define USB_HOST_FNUM_MFNUM(value) ((USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos)))
Kojto 111:4336505e4b1c 440 #define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */
Kojto 111:4336505e4b1c 441 #define USB_HOST_FNUM_FNUM_Msk (0x7FFul << USB_HOST_FNUM_FNUM_Pos)
Kojto 111:4336505e4b1c 442 #define USB_HOST_FNUM_FNUM(value) ((USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos)))
Kojto 111:4336505e4b1c 443 #define USB_HOST_FNUM_MASK 0x3FFFul /**< \brief (USB_HOST_FNUM) MASK Register */
Kojto 111:4336505e4b1c 444
Kojto 111:4336505e4b1c 445 /* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
Kojto 111:4336505e4b1c 446 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 447 typedef union {
Kojto 111:4336505e4b1c 448 struct {
Kojto 111:4336505e4b1c 449 uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
Kojto 111:4336505e4b1c 450 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 451 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 452 } USB_HOST_FLENHIGH_Type;
Kojto 111:4336505e4b1c 453 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 454
Kojto 111:4336505e4b1c 455 #define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
Kojto 111:4336505e4b1c 456 #define USB_HOST_FLENHIGH_RESETVALUE 0x00ul /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
Kojto 111:4336505e4b1c 457
Kojto 111:4336505e4b1c 458 #define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */
Kojto 111:4336505e4b1c 459 #define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos)
Kojto 111:4336505e4b1c 460 #define USB_HOST_FLENHIGH_FLENHIGH(value) ((USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos)))
Kojto 111:4336505e4b1c 461 #define USB_HOST_FLENHIGH_MASK 0xFFul /**< \brief (USB_HOST_FLENHIGH) MASK Register */
Kojto 111:4336505e4b1c 462
Kojto 111:4336505e4b1c 463 /* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 464 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 465 typedef union {
Kojto 111:4336505e4b1c 466 struct {
Kojto 111:4336505e4b1c 467 uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
Kojto 111:4336505e4b1c 468 uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
Kojto 111:4336505e4b1c 469 uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
Kojto 111:4336505e4b1c 470 uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
Kojto 111:4336505e4b1c 471 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
Kojto 111:4336505e4b1c 472 uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
Kojto 111:4336505e4b1c 473 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
Kojto 111:4336505e4b1c 474 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
Kojto 111:4336505e4b1c 475 uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
Kojto 111:4336505e4b1c 476 uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
Kojto 111:4336505e4b1c 477 uint16_t :6; /*!< bit: 10..15 Reserved */
Kojto 111:4336505e4b1c 478 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 479 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 480 } USB_DEVICE_INTENCLR_Type;
Kojto 111:4336505e4b1c 481 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 482
Kojto 111:4336505e4b1c 483 #define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
Kojto 111:4336505e4b1c 484 #define USB_DEVICE_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
Kojto 111:4336505e4b1c 485
Kojto 111:4336505e4b1c 486 #define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
Kojto 111:4336505e4b1c 487 #define USB_DEVICE_INTENCLR_SUSPEND (0x1ul << USB_DEVICE_INTENCLR_SUSPEND_Pos)
Kojto 111:4336505e4b1c 488 #define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
Kojto 111:4336505e4b1c 489 #define USB_DEVICE_INTENCLR_MSOF (0x1ul << USB_DEVICE_INTENCLR_MSOF_Pos)
Kojto 111:4336505e4b1c 490 #define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
Kojto 111:4336505e4b1c 491 #define USB_DEVICE_INTENCLR_SOF (0x1ul << USB_DEVICE_INTENCLR_SOF_Pos)
Kojto 111:4336505e4b1c 492 #define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
Kojto 111:4336505e4b1c 493 #define USB_DEVICE_INTENCLR_EORST (0x1ul << USB_DEVICE_INTENCLR_EORST_Pos)
Kojto 111:4336505e4b1c 494 #define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
Kojto 111:4336505e4b1c 495 #define USB_DEVICE_INTENCLR_WAKEUP (0x1ul << USB_DEVICE_INTENCLR_WAKEUP_Pos)
Kojto 111:4336505e4b1c 496 #define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
Kojto 111:4336505e4b1c 497 #define USB_DEVICE_INTENCLR_EORSM (0x1ul << USB_DEVICE_INTENCLR_EORSM_Pos)
Kojto 111:4336505e4b1c 498 #define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
Kojto 111:4336505e4b1c 499 #define USB_DEVICE_INTENCLR_UPRSM (0x1ul << USB_DEVICE_INTENCLR_UPRSM_Pos)
Kojto 111:4336505e4b1c 500 #define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
Kojto 111:4336505e4b1c 501 #define USB_DEVICE_INTENCLR_RAMACER (0x1ul << USB_DEVICE_INTENCLR_RAMACER_Pos)
Kojto 111:4336505e4b1c 502 #define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
Kojto 111:4336505e4b1c 503 #define USB_DEVICE_INTENCLR_LPMNYET (0x1ul << USB_DEVICE_INTENCLR_LPMNYET_Pos)
Kojto 111:4336505e4b1c 504 #define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
Kojto 111:4336505e4b1c 505 #define USB_DEVICE_INTENCLR_LPMSUSP (0x1ul << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
Kojto 111:4336505e4b1c 506 #define USB_DEVICE_INTENCLR_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 507
Kojto 111:4336505e4b1c 508 /* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 509 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 510 typedef union {
Kojto 111:4336505e4b1c 511 struct {
Kojto 111:4336505e4b1c 512 uint16_t :2; /*!< bit: 0.. 1 Reserved */
Kojto 111:4336505e4b1c 513 uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
Kojto 111:4336505e4b1c 514 uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
Kojto 111:4336505e4b1c 515 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
Kojto 111:4336505e4b1c 516 uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
Kojto 111:4336505e4b1c 517 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
Kojto 111:4336505e4b1c 518 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
Kojto 111:4336505e4b1c 519 uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
Kojto 111:4336505e4b1c 520 uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
Kojto 111:4336505e4b1c 521 uint16_t :6; /*!< bit: 10..15 Reserved */
Kojto 111:4336505e4b1c 522 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 523 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 524 } USB_HOST_INTENCLR_Type;
Kojto 111:4336505e4b1c 525 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 526
Kojto 111:4336505e4b1c 527 #define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
Kojto 111:4336505e4b1c 528 #define USB_HOST_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
Kojto 111:4336505e4b1c 529
Kojto 111:4336505e4b1c 530 #define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
Kojto 111:4336505e4b1c 531 #define USB_HOST_INTENCLR_HSOF (0x1ul << USB_HOST_INTENCLR_HSOF_Pos)
Kojto 111:4336505e4b1c 532 #define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
Kojto 111:4336505e4b1c 533 #define USB_HOST_INTENCLR_RST (0x1ul << USB_HOST_INTENCLR_RST_Pos)
Kojto 111:4336505e4b1c 534 #define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
Kojto 111:4336505e4b1c 535 #define USB_HOST_INTENCLR_WAKEUP (0x1ul << USB_HOST_INTENCLR_WAKEUP_Pos)
Kojto 111:4336505e4b1c 536 #define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
Kojto 111:4336505e4b1c 537 #define USB_HOST_INTENCLR_DNRSM (0x1ul << USB_HOST_INTENCLR_DNRSM_Pos)
Kojto 111:4336505e4b1c 538 #define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
Kojto 111:4336505e4b1c 539 #define USB_HOST_INTENCLR_UPRSM (0x1ul << USB_HOST_INTENCLR_UPRSM_Pos)
Kojto 111:4336505e4b1c 540 #define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
Kojto 111:4336505e4b1c 541 #define USB_HOST_INTENCLR_RAMACER (0x1ul << USB_HOST_INTENCLR_RAMACER_Pos)
Kojto 111:4336505e4b1c 542 #define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
Kojto 111:4336505e4b1c 543 #define USB_HOST_INTENCLR_DCONN (0x1ul << USB_HOST_INTENCLR_DCONN_Pos)
Kojto 111:4336505e4b1c 544 #define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
Kojto 111:4336505e4b1c 545 #define USB_HOST_INTENCLR_DDISC (0x1ul << USB_HOST_INTENCLR_DDISC_Pos)
Kojto 111:4336505e4b1c 546 #define USB_HOST_INTENCLR_MASK 0x03FCul /**< \brief (USB_HOST_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 547
Kojto 111:4336505e4b1c 548 /* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 549 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 550 typedef union {
Kojto 111:4336505e4b1c 551 struct {
Kojto 111:4336505e4b1c 552 uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
Kojto 111:4336505e4b1c 553 uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
Kojto 111:4336505e4b1c 554 uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
Kojto 111:4336505e4b1c 555 uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
Kojto 111:4336505e4b1c 556 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
Kojto 111:4336505e4b1c 557 uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
Kojto 111:4336505e4b1c 558 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
Kojto 111:4336505e4b1c 559 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
Kojto 111:4336505e4b1c 560 uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
Kojto 111:4336505e4b1c 561 uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
Kojto 111:4336505e4b1c 562 uint16_t :6; /*!< bit: 10..15 Reserved */
Kojto 111:4336505e4b1c 563 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 564 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 565 } USB_DEVICE_INTENSET_Type;
Kojto 111:4336505e4b1c 566 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 567
Kojto 111:4336505e4b1c 568 #define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
Kojto 111:4336505e4b1c 569 #define USB_DEVICE_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
Kojto 111:4336505e4b1c 570
Kojto 111:4336505e4b1c 571 #define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
Kojto 111:4336505e4b1c 572 #define USB_DEVICE_INTENSET_SUSPEND (0x1ul << USB_DEVICE_INTENSET_SUSPEND_Pos)
Kojto 111:4336505e4b1c 573 #define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
Kojto 111:4336505e4b1c 574 #define USB_DEVICE_INTENSET_MSOF (0x1ul << USB_DEVICE_INTENSET_MSOF_Pos)
Kojto 111:4336505e4b1c 575 #define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
Kojto 111:4336505e4b1c 576 #define USB_DEVICE_INTENSET_SOF (0x1ul << USB_DEVICE_INTENSET_SOF_Pos)
Kojto 111:4336505e4b1c 577 #define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
Kojto 111:4336505e4b1c 578 #define USB_DEVICE_INTENSET_EORST (0x1ul << USB_DEVICE_INTENSET_EORST_Pos)
Kojto 111:4336505e4b1c 579 #define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
Kojto 111:4336505e4b1c 580 #define USB_DEVICE_INTENSET_WAKEUP (0x1ul << USB_DEVICE_INTENSET_WAKEUP_Pos)
Kojto 111:4336505e4b1c 581 #define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
Kojto 111:4336505e4b1c 582 #define USB_DEVICE_INTENSET_EORSM (0x1ul << USB_DEVICE_INTENSET_EORSM_Pos)
Kojto 111:4336505e4b1c 583 #define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
Kojto 111:4336505e4b1c 584 #define USB_DEVICE_INTENSET_UPRSM (0x1ul << USB_DEVICE_INTENSET_UPRSM_Pos)
Kojto 111:4336505e4b1c 585 #define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
Kojto 111:4336505e4b1c 586 #define USB_DEVICE_INTENSET_RAMACER (0x1ul << USB_DEVICE_INTENSET_RAMACER_Pos)
Kojto 111:4336505e4b1c 587 #define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
Kojto 111:4336505e4b1c 588 #define USB_DEVICE_INTENSET_LPMNYET (0x1ul << USB_DEVICE_INTENSET_LPMNYET_Pos)
Kojto 111:4336505e4b1c 589 #define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
Kojto 111:4336505e4b1c 590 #define USB_DEVICE_INTENSET_LPMSUSP (0x1ul << USB_DEVICE_INTENSET_LPMSUSP_Pos)
Kojto 111:4336505e4b1c 591 #define USB_DEVICE_INTENSET_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 592
Kojto 111:4336505e4b1c 593 /* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 594 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 595 typedef union {
Kojto 111:4336505e4b1c 596 struct {
Kojto 111:4336505e4b1c 597 uint16_t :2; /*!< bit: 0.. 1 Reserved */
Kojto 111:4336505e4b1c 598 uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
Kojto 111:4336505e4b1c 599 uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
Kojto 111:4336505e4b1c 600 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
Kojto 111:4336505e4b1c 601 uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
Kojto 111:4336505e4b1c 602 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
Kojto 111:4336505e4b1c 603 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
Kojto 111:4336505e4b1c 604 uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
Kojto 111:4336505e4b1c 605 uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
Kojto 111:4336505e4b1c 606 uint16_t :6; /*!< bit: 10..15 Reserved */
Kojto 111:4336505e4b1c 607 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 608 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 609 } USB_HOST_INTENSET_Type;
Kojto 111:4336505e4b1c 610 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 611
Kojto 111:4336505e4b1c 612 #define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
Kojto 111:4336505e4b1c 613 #define USB_HOST_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
Kojto 111:4336505e4b1c 614
Kojto 111:4336505e4b1c 615 #define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
Kojto 111:4336505e4b1c 616 #define USB_HOST_INTENSET_HSOF (0x1ul << USB_HOST_INTENSET_HSOF_Pos)
Kojto 111:4336505e4b1c 617 #define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
Kojto 111:4336505e4b1c 618 #define USB_HOST_INTENSET_RST (0x1ul << USB_HOST_INTENSET_RST_Pos)
Kojto 111:4336505e4b1c 619 #define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
Kojto 111:4336505e4b1c 620 #define USB_HOST_INTENSET_WAKEUP (0x1ul << USB_HOST_INTENSET_WAKEUP_Pos)
Kojto 111:4336505e4b1c 621 #define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
Kojto 111:4336505e4b1c 622 #define USB_HOST_INTENSET_DNRSM (0x1ul << USB_HOST_INTENSET_DNRSM_Pos)
Kojto 111:4336505e4b1c 623 #define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
Kojto 111:4336505e4b1c 624 #define USB_HOST_INTENSET_UPRSM (0x1ul << USB_HOST_INTENSET_UPRSM_Pos)
Kojto 111:4336505e4b1c 625 #define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
Kojto 111:4336505e4b1c 626 #define USB_HOST_INTENSET_RAMACER (0x1ul << USB_HOST_INTENSET_RAMACER_Pos)
Kojto 111:4336505e4b1c 627 #define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
Kojto 111:4336505e4b1c 628 #define USB_HOST_INTENSET_DCONN (0x1ul << USB_HOST_INTENSET_DCONN_Pos)
Kojto 111:4336505e4b1c 629 #define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
Kojto 111:4336505e4b1c 630 #define USB_HOST_INTENSET_DDISC (0x1ul << USB_HOST_INTENSET_DDISC_Pos)
Kojto 111:4336505e4b1c 631 #define USB_HOST_INTENSET_MASK 0x03FCul /**< \brief (USB_HOST_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 632
Kojto 111:4336505e4b1c 633 /* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
Kojto 111:4336505e4b1c 634 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 635 typedef union {
Kojto 111:4336505e4b1c 636 struct {
Kojto 111:4336505e4b1c 637 uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
Kojto 111:4336505e4b1c 638 uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
Kojto 111:4336505e4b1c 639 uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
Kojto 111:4336505e4b1c 640 uint16_t EORST:1; /*!< bit: 3 End of Reset */
Kojto 111:4336505e4b1c 641 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
Kojto 111:4336505e4b1c 642 uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
Kojto 111:4336505e4b1c 643 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
Kojto 111:4336505e4b1c 644 uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
Kojto 111:4336505e4b1c 645 uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
Kojto 111:4336505e4b1c 646 uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
Kojto 111:4336505e4b1c 647 uint16_t :6; /*!< bit: 10..15 Reserved */
Kojto 111:4336505e4b1c 648 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 649 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 650 } USB_DEVICE_INTFLAG_Type;
Kojto 111:4336505e4b1c 651 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 652
Kojto 111:4336505e4b1c 653 #define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
Kojto 111:4336505e4b1c 654 #define USB_DEVICE_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
Kojto 111:4336505e4b1c 655
Kojto 111:4336505e4b1c 656 #define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */
Kojto 111:4336505e4b1c 657 #define USB_DEVICE_INTFLAG_SUSPEND (0x1ul << USB_DEVICE_INTFLAG_SUSPEND_Pos)
Kojto 111:4336505e4b1c 658 #define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
Kojto 111:4336505e4b1c 659 #define USB_DEVICE_INTFLAG_MSOF (0x1ul << USB_DEVICE_INTFLAG_MSOF_Pos)
Kojto 111:4336505e4b1c 660 #define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
Kojto 111:4336505e4b1c 661 #define USB_DEVICE_INTFLAG_SOF (0x1ul << USB_DEVICE_INTFLAG_SOF_Pos)
Kojto 111:4336505e4b1c 662 #define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
Kojto 111:4336505e4b1c 663 #define USB_DEVICE_INTFLAG_EORST (0x1ul << USB_DEVICE_INTFLAG_EORST_Pos)
Kojto 111:4336505e4b1c 664 #define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
Kojto 111:4336505e4b1c 665 #define USB_DEVICE_INTFLAG_WAKEUP (0x1ul << USB_DEVICE_INTFLAG_WAKEUP_Pos)
Kojto 111:4336505e4b1c 666 #define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
Kojto 111:4336505e4b1c 667 #define USB_DEVICE_INTFLAG_EORSM (0x1ul << USB_DEVICE_INTFLAG_EORSM_Pos)
Kojto 111:4336505e4b1c 668 #define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
Kojto 111:4336505e4b1c 669 #define USB_DEVICE_INTFLAG_UPRSM (0x1ul << USB_DEVICE_INTFLAG_UPRSM_Pos)
Kojto 111:4336505e4b1c 670 #define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
Kojto 111:4336505e4b1c 671 #define USB_DEVICE_INTFLAG_RAMACER (0x1ul << USB_DEVICE_INTFLAG_RAMACER_Pos)
Kojto 111:4336505e4b1c 672 #define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
Kojto 111:4336505e4b1c 673 #define USB_DEVICE_INTFLAG_LPMNYET (0x1ul << USB_DEVICE_INTFLAG_LPMNYET_Pos)
Kojto 111:4336505e4b1c 674 #define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
Kojto 111:4336505e4b1c 675 #define USB_DEVICE_INTFLAG_LPMSUSP (0x1ul << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
Kojto 111:4336505e4b1c 676 #define USB_DEVICE_INTFLAG_MASK 0x03FFul /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 677
Kojto 111:4336505e4b1c 678 /* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
Kojto 111:4336505e4b1c 679 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 680 typedef union {
Kojto 111:4336505e4b1c 681 struct {
Kojto 111:4336505e4b1c 682 uint16_t :2; /*!< bit: 0.. 1 Reserved */
Kojto 111:4336505e4b1c 683 uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
Kojto 111:4336505e4b1c 684 uint16_t RST:1; /*!< bit: 3 Bus Reset */
Kojto 111:4336505e4b1c 685 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
Kojto 111:4336505e4b1c 686 uint16_t DNRSM:1; /*!< bit: 5 Downstream */
Kojto 111:4336505e4b1c 687 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
Kojto 111:4336505e4b1c 688 uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
Kojto 111:4336505e4b1c 689 uint16_t DCONN:1; /*!< bit: 8 Device Connection */
Kojto 111:4336505e4b1c 690 uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
Kojto 111:4336505e4b1c 691 uint16_t :6; /*!< bit: 10..15 Reserved */
Kojto 111:4336505e4b1c 692 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 693 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 694 } USB_HOST_INTFLAG_Type;
Kojto 111:4336505e4b1c 695 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 696
Kojto 111:4336505e4b1c 697 #define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
Kojto 111:4336505e4b1c 698 #define USB_HOST_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
Kojto 111:4336505e4b1c 699
Kojto 111:4336505e4b1c 700 #define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
Kojto 111:4336505e4b1c 701 #define USB_HOST_INTFLAG_HSOF (0x1ul << USB_HOST_INTFLAG_HSOF_Pos)
Kojto 111:4336505e4b1c 702 #define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */
Kojto 111:4336505e4b1c 703 #define USB_HOST_INTFLAG_RST (0x1ul << USB_HOST_INTFLAG_RST_Pos)
Kojto 111:4336505e4b1c 704 #define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */
Kojto 111:4336505e4b1c 705 #define USB_HOST_INTFLAG_WAKEUP (0x1ul << USB_HOST_INTFLAG_WAKEUP_Pos)
Kojto 111:4336505e4b1c 706 #define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */
Kojto 111:4336505e4b1c 707 #define USB_HOST_INTFLAG_DNRSM (0x1ul << USB_HOST_INTFLAG_DNRSM_Pos)
Kojto 111:4336505e4b1c 708 #define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
Kojto 111:4336505e4b1c 709 #define USB_HOST_INTFLAG_UPRSM (0x1ul << USB_HOST_INTFLAG_UPRSM_Pos)
Kojto 111:4336505e4b1c 710 #define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */
Kojto 111:4336505e4b1c 711 #define USB_HOST_INTFLAG_RAMACER (0x1ul << USB_HOST_INTFLAG_RAMACER_Pos)
Kojto 111:4336505e4b1c 712 #define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */
Kojto 111:4336505e4b1c 713 #define USB_HOST_INTFLAG_DCONN (0x1ul << USB_HOST_INTFLAG_DCONN_Pos)
Kojto 111:4336505e4b1c 714 #define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
Kojto 111:4336505e4b1c 715 #define USB_HOST_INTFLAG_DDISC (0x1ul << USB_HOST_INTFLAG_DDISC_Pos)
Kojto 111:4336505e4b1c 716 #define USB_HOST_INTFLAG_MASK 0x03FCul /**< \brief (USB_HOST_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 717
Kojto 111:4336505e4b1c 718 /* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
Kojto 111:4336505e4b1c 719 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 720 typedef union {
Kojto 111:4336505e4b1c 721 struct {
Kojto 111:4336505e4b1c 722 uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
Kojto 111:4336505e4b1c 723 uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
Kojto 111:4336505e4b1c 724 uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
Kojto 111:4336505e4b1c 725 uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
Kojto 111:4336505e4b1c 726 uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
Kojto 111:4336505e4b1c 727 uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
Kojto 111:4336505e4b1c 728 uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
Kojto 111:4336505e4b1c 729 uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
Kojto 111:4336505e4b1c 730 uint16_t :8; /*!< bit: 8..15 Reserved */
Kojto 111:4336505e4b1c 731 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 732 struct {
Kojto 111:4336505e4b1c 733 uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
Kojto 111:4336505e4b1c 734 uint16_t :8; /*!< bit: 8..15 Reserved */
Kojto 111:4336505e4b1c 735 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 736 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 737 } USB_DEVICE_EPINTSMRY_Type;
Kojto 111:4336505e4b1c 738 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 739
Kojto 111:4336505e4b1c 740 #define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
Kojto 111:4336505e4b1c 741 #define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
Kojto 111:4336505e4b1c 742
Kojto 111:4336505e4b1c 743 #define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
Kojto 111:4336505e4b1c 744 #define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
Kojto 111:4336505e4b1c 745 #define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
Kojto 111:4336505e4b1c 746 #define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
Kojto 111:4336505e4b1c 747 #define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
Kojto 111:4336505e4b1c 748 #define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
Kojto 111:4336505e4b1c 749 #define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
Kojto 111:4336505e4b1c 750 #define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
Kojto 111:4336505e4b1c 751 #define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
Kojto 111:4336505e4b1c 752 #define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
Kojto 111:4336505e4b1c 753 #define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
Kojto 111:4336505e4b1c 754 #define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
Kojto 111:4336505e4b1c 755 #define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
Kojto 111:4336505e4b1c 756 #define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
Kojto 111:4336505e4b1c 757 #define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
Kojto 111:4336505e4b1c 758 #define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
Kojto 111:4336505e4b1c 759 #define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
Kojto 111:4336505e4b1c 760 #define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos)
Kojto 111:4336505e4b1c 761 #define USB_DEVICE_EPINTSMRY_EPINT(value) ((USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos)))
Kojto 111:4336505e4b1c 762 #define USB_DEVICE_EPINTSMRY_MASK 0x00FFul /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
Kojto 111:4336505e4b1c 763
Kojto 111:4336505e4b1c 764 /* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
Kojto 111:4336505e4b1c 765 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 766 typedef union {
Kojto 111:4336505e4b1c 767 struct {
Kojto 111:4336505e4b1c 768 uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
Kojto 111:4336505e4b1c 769 uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
Kojto 111:4336505e4b1c 770 uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
Kojto 111:4336505e4b1c 771 uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
Kojto 111:4336505e4b1c 772 uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
Kojto 111:4336505e4b1c 773 uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
Kojto 111:4336505e4b1c 774 uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
Kojto 111:4336505e4b1c 775 uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
Kojto 111:4336505e4b1c 776 uint16_t :8; /*!< bit: 8..15 Reserved */
Kojto 111:4336505e4b1c 777 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 778 struct {
Kojto 111:4336505e4b1c 779 uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
Kojto 111:4336505e4b1c 780 uint16_t :8; /*!< bit: 8..15 Reserved */
Kojto 111:4336505e4b1c 781 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 782 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 783 } USB_HOST_PINTSMRY_Type;
Kojto 111:4336505e4b1c 784 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 785
Kojto 111:4336505e4b1c 786 #define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
Kojto 111:4336505e4b1c 787 #define USB_HOST_PINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
Kojto 111:4336505e4b1c 788
Kojto 111:4336505e4b1c 789 #define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
Kojto 111:4336505e4b1c 790 #define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos)
Kojto 111:4336505e4b1c 791 #define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
Kojto 111:4336505e4b1c 792 #define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos)
Kojto 111:4336505e4b1c 793 #define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
Kojto 111:4336505e4b1c 794 #define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos)
Kojto 111:4336505e4b1c 795 #define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
Kojto 111:4336505e4b1c 796 #define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos)
Kojto 111:4336505e4b1c 797 #define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
Kojto 111:4336505e4b1c 798 #define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos)
Kojto 111:4336505e4b1c 799 #define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
Kojto 111:4336505e4b1c 800 #define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos)
Kojto 111:4336505e4b1c 801 #define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
Kojto 111:4336505e4b1c 802 #define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos)
Kojto 111:4336505e4b1c 803 #define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
Kojto 111:4336505e4b1c 804 #define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos)
Kojto 111:4336505e4b1c 805 #define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
Kojto 111:4336505e4b1c 806 #define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos)
Kojto 111:4336505e4b1c 807 #define USB_HOST_PINTSMRY_EPINT(value) ((USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos)))
Kojto 111:4336505e4b1c 808 #define USB_HOST_PINTSMRY_MASK 0x00FFul /**< \brief (USB_HOST_PINTSMRY) MASK Register */
Kojto 111:4336505e4b1c 809
Kojto 111:4336505e4b1c 810 /* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
Kojto 111:4336505e4b1c 811 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 812 typedef union {
Kojto 111:4336505e4b1c 813 struct {
Kojto 111:4336505e4b1c 814 uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
Kojto 111:4336505e4b1c 815 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 816 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 817 } USB_DESCADD_Type;
Kojto 111:4336505e4b1c 818 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 819
Kojto 111:4336505e4b1c 820 #define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */
Kojto 111:4336505e4b1c 821 #define USB_DESCADD_RESETVALUE 0x00000000ul /**< \brief (USB_DESCADD reset_value) Descriptor Address */
Kojto 111:4336505e4b1c 822
Kojto 111:4336505e4b1c 823 #define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */
Kojto 111:4336505e4b1c 824 #define USB_DESCADD_DESCADD_Msk (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos)
Kojto 111:4336505e4b1c 825 #define USB_DESCADD_DESCADD(value) ((USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos)))
Kojto 111:4336505e4b1c 826 #define USB_DESCADD_MASK 0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */
Kojto 111:4336505e4b1c 827
Kojto 111:4336505e4b1c 828 /* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
Kojto 111:4336505e4b1c 829 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 830 typedef union {
Kojto 111:4336505e4b1c 831 struct {
Kojto 111:4336505e4b1c 832 uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
Kojto 111:4336505e4b1c 833 uint16_t :1; /*!< bit: 5 Reserved */
Kojto 111:4336505e4b1c 834 uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
Kojto 111:4336505e4b1c 835 uint16_t :1; /*!< bit: 11 Reserved */
Kojto 111:4336505e4b1c 836 uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
Kojto 111:4336505e4b1c 837 uint16_t :1; /*!< bit: 15 Reserved */
Kojto 111:4336505e4b1c 838 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 839 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 840 } USB_PADCAL_Type;
Kojto 111:4336505e4b1c 841 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 842
Kojto 111:4336505e4b1c 843 #define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */
Kojto 111:4336505e4b1c 844 #define USB_PADCAL_RESETVALUE 0x0000ul /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
Kojto 111:4336505e4b1c 845
Kojto 111:4336505e4b1c 846 #define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */
Kojto 111:4336505e4b1c 847 #define USB_PADCAL_TRANSP_Msk (0x1Ful << USB_PADCAL_TRANSP_Pos)
Kojto 111:4336505e4b1c 848 #define USB_PADCAL_TRANSP(value) ((USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos)))
Kojto 111:4336505e4b1c 849 #define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */
Kojto 111:4336505e4b1c 850 #define USB_PADCAL_TRANSN_Msk (0x1Ful << USB_PADCAL_TRANSN_Pos)
Kojto 111:4336505e4b1c 851 #define USB_PADCAL_TRANSN(value) ((USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos)))
Kojto 111:4336505e4b1c 852 #define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */
Kojto 111:4336505e4b1c 853 #define USB_PADCAL_TRIM_Msk (0x7ul << USB_PADCAL_TRIM_Pos)
Kojto 111:4336505e4b1c 854 #define USB_PADCAL_TRIM(value) ((USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos)))
Kojto 111:4336505e4b1c 855 #define USB_PADCAL_MASK 0x77DFul /**< \brief (USB_PADCAL) MASK Register */
Kojto 111:4336505e4b1c 856
Kojto 111:4336505e4b1c 857 /* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
Kojto 111:4336505e4b1c 858 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 859 typedef union {
Kojto 111:4336505e4b1c 860 struct {
Kojto 111:4336505e4b1c 861 uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
Kojto 111:4336505e4b1c 862 uint8_t :1; /*!< bit: 3 Reserved */
Kojto 111:4336505e4b1c 863 uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
Kojto 111:4336505e4b1c 864 uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
Kojto 111:4336505e4b1c 865 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 866 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 867 } USB_DEVICE_EPCFG_Type;
Kojto 111:4336505e4b1c 868 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 869
Kojto 111:4336505e4b1c 870 #define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
Kojto 111:4336505e4b1c 871 #define USB_DEVICE_EPCFG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
Kojto 111:4336505e4b1c 872
Kojto 111:4336505e4b1c 873 #define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
Kojto 111:4336505e4b1c 874 #define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos)
Kojto 111:4336505e4b1c 875 #define USB_DEVICE_EPCFG_EPTYPE0(value) ((USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos)))
Kojto 111:4336505e4b1c 876 #define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
Kojto 111:4336505e4b1c 877 #define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos)
Kojto 111:4336505e4b1c 878 #define USB_DEVICE_EPCFG_EPTYPE1(value) ((USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos)))
Kojto 111:4336505e4b1c 879 #define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
Kojto 111:4336505e4b1c 880 #define USB_DEVICE_EPCFG_NYETDIS (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos)
Kojto 111:4336505e4b1c 881 #define USB_DEVICE_EPCFG_MASK 0xF7ul /**< \brief (USB_DEVICE_EPCFG) MASK Register */
Kojto 111:4336505e4b1c 882
Kojto 111:4336505e4b1c 883 /* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
Kojto 111:4336505e4b1c 884 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 885 typedef union {
Kojto 111:4336505e4b1c 886 struct {
Kojto 111:4336505e4b1c 887 uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
Kojto 111:4336505e4b1c 888 uint8_t BK:1; /*!< bit: 2 Pipe Bank */
Kojto 111:4336505e4b1c 889 uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
Kojto 111:4336505e4b1c 890 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 891 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 892 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 893 } USB_HOST_PCFG_Type;
Kojto 111:4336505e4b1c 894 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 895
Kojto 111:4336505e4b1c 896 #define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
Kojto 111:4336505e4b1c 897 #define USB_HOST_PCFG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
Kojto 111:4336505e4b1c 898
Kojto 111:4336505e4b1c 899 #define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */
Kojto 111:4336505e4b1c 900 #define USB_HOST_PCFG_PTOKEN_Msk (0x3ul << USB_HOST_PCFG_PTOKEN_Pos)
Kojto 111:4336505e4b1c 901 #define USB_HOST_PCFG_PTOKEN(value) ((USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos)))
Kojto 111:4336505e4b1c 902 #define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */
Kojto 111:4336505e4b1c 903 #define USB_HOST_PCFG_BK (0x1ul << USB_HOST_PCFG_BK_Pos)
Kojto 111:4336505e4b1c 904 #define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */
Kojto 111:4336505e4b1c 905 #define USB_HOST_PCFG_PTYPE_Msk (0x7ul << USB_HOST_PCFG_PTYPE_Pos)
Kojto 111:4336505e4b1c 906 #define USB_HOST_PCFG_PTYPE(value) ((USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos)))
Kojto 111:4336505e4b1c 907 #define USB_HOST_PCFG_MASK 0x3Ful /**< \brief (USB_HOST_PCFG) MASK Register */
Kojto 111:4336505e4b1c 908
Kojto 111:4336505e4b1c 909 /* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
Kojto 111:4336505e4b1c 910 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 911 typedef union {
Kojto 111:4336505e4b1c 912 struct {
Kojto 111:4336505e4b1c 913 uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
Kojto 111:4336505e4b1c 914 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 915 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 916 } USB_HOST_BINTERVAL_Type;
Kojto 111:4336505e4b1c 917 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 918
Kojto 111:4336505e4b1c 919 #define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
Kojto 111:4336505e4b1c 920 #define USB_HOST_BINTERVAL_RESETVALUE 0x00ul /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
Kojto 111:4336505e4b1c 921
Kojto 111:4336505e4b1c 922 #define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
Kojto 111:4336505e4b1c 923 #define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
Kojto 111:4336505e4b1c 924 #define USB_HOST_BINTERVAL_BITINTERVAL(value) ((USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)))
Kojto 111:4336505e4b1c 925 #define USB_HOST_BINTERVAL_MASK 0xFFul /**< \brief (USB_HOST_BINTERVAL) MASK Register */
Kojto 111:4336505e4b1c 926
Kojto 111:4336505e4b1c 927 /* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
Kojto 111:4336505e4b1c 928 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 929 typedef union {
Kojto 111:4336505e4b1c 930 struct {
Kojto 111:4336505e4b1c 931 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
Kojto 111:4336505e4b1c 932 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
Kojto 111:4336505e4b1c 933 uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
Kojto 111:4336505e4b1c 934 uint8_t :1; /*!< bit: 3 Reserved */
Kojto 111:4336505e4b1c 935 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
Kojto 111:4336505e4b1c 936 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
Kojto 111:4336505e4b1c 937 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
Kojto 111:4336505e4b1c 938 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
Kojto 111:4336505e4b1c 939 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 940 struct {
Kojto 111:4336505e4b1c 941 uint8_t :4; /*!< bit: 0.. 3 Reserved */
Kojto 111:4336505e4b1c 942 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
Kojto 111:4336505e4b1c 943 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 944 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 945 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 946 } USB_DEVICE_EPSTATUSCLR_Type;
Kojto 111:4336505e4b1c 947 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 948
Kojto 111:4336505e4b1c 949 #define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
Kojto 111:4336505e4b1c 950 #define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
Kojto 111:4336505e4b1c 951
Kojto 111:4336505e4b1c 952 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
Kojto 111:4336505e4b1c 953 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
Kojto 111:4336505e4b1c 954 #define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
Kojto 111:4336505e4b1c 955 #define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
Kojto 111:4336505e4b1c 956 #define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */
Kojto 111:4336505e4b1c 957 #define USB_DEVICE_EPSTATUSCLR_CURBK (0x1ul << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
Kojto 111:4336505e4b1c 958 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
Kojto 111:4336505e4b1c 959 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
Kojto 111:4336505e4b1c 960 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
Kojto 111:4336505e4b1c 961 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
Kojto 111:4336505e4b1c 962 #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
Kojto 111:4336505e4b1c 963 #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
Kojto 111:4336505e4b1c 964 #define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) ((USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)))
Kojto 111:4336505e4b1c 965 #define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
Kojto 111:4336505e4b1c 966 #define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
Kojto 111:4336505e4b1c 967 #define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
Kojto 111:4336505e4b1c 968 #define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
Kojto 111:4336505e4b1c 969 #define USB_DEVICE_EPSTATUSCLR_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
Kojto 111:4336505e4b1c 970
Kojto 111:4336505e4b1c 971 /* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
Kojto 111:4336505e4b1c 972 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 973 typedef union {
Kojto 111:4336505e4b1c 974 struct {
Kojto 111:4336505e4b1c 975 uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
Kojto 111:4336505e4b1c 976 uint8_t :1; /*!< bit: 1 Reserved */
Kojto 111:4336505e4b1c 977 uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
Kojto 111:4336505e4b1c 978 uint8_t :1; /*!< bit: 3 Reserved */
Kojto 111:4336505e4b1c 979 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
Kojto 111:4336505e4b1c 980 uint8_t :1; /*!< bit: 5 Reserved */
Kojto 111:4336505e4b1c 981 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
Kojto 111:4336505e4b1c 982 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
Kojto 111:4336505e4b1c 983 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 984 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 985 } USB_HOST_PSTATUSCLR_Type;
Kojto 111:4336505e4b1c 986 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 987
Kojto 111:4336505e4b1c 988 #define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
Kojto 111:4336505e4b1c 989 #define USB_HOST_PSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
Kojto 111:4336505e4b1c 990
Kojto 111:4336505e4b1c 991 #define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
Kojto 111:4336505e4b1c 992 #define USB_HOST_PSTATUSCLR_DTGL (0x1ul << USB_HOST_PSTATUSCLR_DTGL_Pos)
Kojto 111:4336505e4b1c 993 #define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
Kojto 111:4336505e4b1c 994 #define USB_HOST_PSTATUSCLR_CURBK (0x1ul << USB_HOST_PSTATUSCLR_CURBK_Pos)
Kojto 111:4336505e4b1c 995 #define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
Kojto 111:4336505e4b1c 996 #define USB_HOST_PSTATUSCLR_PFREEZE (0x1ul << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
Kojto 111:4336505e4b1c 997 #define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
Kojto 111:4336505e4b1c 998 #define USB_HOST_PSTATUSCLR_BK0RDY (0x1ul << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
Kojto 111:4336505e4b1c 999 #define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
Kojto 111:4336505e4b1c 1000 #define USB_HOST_PSTATUSCLR_BK1RDY (0x1ul << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
Kojto 111:4336505e4b1c 1001 #define USB_HOST_PSTATUSCLR_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
Kojto 111:4336505e4b1c 1002
Kojto 111:4336505e4b1c 1003 /* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
Kojto 111:4336505e4b1c 1004 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1005 typedef union {
Kojto 111:4336505e4b1c 1006 struct {
Kojto 111:4336505e4b1c 1007 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
Kojto 111:4336505e4b1c 1008 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
Kojto 111:4336505e4b1c 1009 uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
Kojto 111:4336505e4b1c 1010 uint8_t :1; /*!< bit: 3 Reserved */
Kojto 111:4336505e4b1c 1011 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
Kojto 111:4336505e4b1c 1012 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
Kojto 111:4336505e4b1c 1013 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
Kojto 111:4336505e4b1c 1014 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
Kojto 111:4336505e4b1c 1015 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1016 struct {
Kojto 111:4336505e4b1c 1017 uint8_t :4; /*!< bit: 0.. 3 Reserved */
Kojto 111:4336505e4b1c 1018 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
Kojto 111:4336505e4b1c 1019 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 1020 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 1021 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1022 } USB_DEVICE_EPSTATUSSET_Type;
Kojto 111:4336505e4b1c 1023 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1024
Kojto 111:4336505e4b1c 1025 #define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
Kojto 111:4336505e4b1c 1026 #define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
Kojto 111:4336505e4b1c 1027
Kojto 111:4336505e4b1c 1028 #define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
Kojto 111:4336505e4b1c 1029 #define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
Kojto 111:4336505e4b1c 1030 #define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
Kojto 111:4336505e4b1c 1031 #define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
Kojto 111:4336505e4b1c 1032 #define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
Kojto 111:4336505e4b1c 1033 #define USB_DEVICE_EPSTATUSSET_CURBK (0x1ul << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
Kojto 111:4336505e4b1c 1034 #define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
Kojto 111:4336505e4b1c 1035 #define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
Kojto 111:4336505e4b1c 1036 #define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
Kojto 111:4336505e4b1c 1037 #define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
Kojto 111:4336505e4b1c 1038 #define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
Kojto 111:4336505e4b1c 1039 #define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
Kojto 111:4336505e4b1c 1040 #define USB_DEVICE_EPSTATUSSET_STALLRQ(value) ((USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)))
Kojto 111:4336505e4b1c 1041 #define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
Kojto 111:4336505e4b1c 1042 #define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
Kojto 111:4336505e4b1c 1043 #define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
Kojto 111:4336505e4b1c 1044 #define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
Kojto 111:4336505e4b1c 1045 #define USB_DEVICE_EPSTATUSSET_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
Kojto 111:4336505e4b1c 1046
Kojto 111:4336505e4b1c 1047 /* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
Kojto 111:4336505e4b1c 1048 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1049 typedef union {
Kojto 111:4336505e4b1c 1050 struct {
Kojto 111:4336505e4b1c 1051 uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
Kojto 111:4336505e4b1c 1052 uint8_t :1; /*!< bit: 1 Reserved */
Kojto 111:4336505e4b1c 1053 uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
Kojto 111:4336505e4b1c 1054 uint8_t :1; /*!< bit: 3 Reserved */
Kojto 111:4336505e4b1c 1055 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
Kojto 111:4336505e4b1c 1056 uint8_t :1; /*!< bit: 5 Reserved */
Kojto 111:4336505e4b1c 1057 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
Kojto 111:4336505e4b1c 1058 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
Kojto 111:4336505e4b1c 1059 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1060 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1061 } USB_HOST_PSTATUSSET_Type;
Kojto 111:4336505e4b1c 1062 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1063
Kojto 111:4336505e4b1c 1064 #define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
Kojto 111:4336505e4b1c 1065 #define USB_HOST_PSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
Kojto 111:4336505e4b1c 1066
Kojto 111:4336505e4b1c 1067 #define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
Kojto 111:4336505e4b1c 1068 #define USB_HOST_PSTATUSSET_DTGL (0x1ul << USB_HOST_PSTATUSSET_DTGL_Pos)
Kojto 111:4336505e4b1c 1069 #define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
Kojto 111:4336505e4b1c 1070 #define USB_HOST_PSTATUSSET_CURBK (0x1ul << USB_HOST_PSTATUSSET_CURBK_Pos)
Kojto 111:4336505e4b1c 1071 #define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
Kojto 111:4336505e4b1c 1072 #define USB_HOST_PSTATUSSET_PFREEZE (0x1ul << USB_HOST_PSTATUSSET_PFREEZE_Pos)
Kojto 111:4336505e4b1c 1073 #define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
Kojto 111:4336505e4b1c 1074 #define USB_HOST_PSTATUSSET_BK0RDY (0x1ul << USB_HOST_PSTATUSSET_BK0RDY_Pos)
Kojto 111:4336505e4b1c 1075 #define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
Kojto 111:4336505e4b1c 1076 #define USB_HOST_PSTATUSSET_BK1RDY (0x1ul << USB_HOST_PSTATUSSET_BK1RDY_Pos)
Kojto 111:4336505e4b1c 1077 #define USB_HOST_PSTATUSSET_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
Kojto 111:4336505e4b1c 1078
Kojto 111:4336505e4b1c 1079 /* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
Kojto 111:4336505e4b1c 1080 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1081 typedef union {
Kojto 111:4336505e4b1c 1082 struct {
Kojto 111:4336505e4b1c 1083 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
Kojto 111:4336505e4b1c 1084 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
Kojto 111:4336505e4b1c 1085 uint8_t CURBK:1; /*!< bit: 2 Current Bank */
Kojto 111:4336505e4b1c 1086 uint8_t :1; /*!< bit: 3 Reserved */
Kojto 111:4336505e4b1c 1087 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
Kojto 111:4336505e4b1c 1088 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
Kojto 111:4336505e4b1c 1089 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
Kojto 111:4336505e4b1c 1090 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
Kojto 111:4336505e4b1c 1091 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1092 struct {
Kojto 111:4336505e4b1c 1093 uint8_t :4; /*!< bit: 0.. 3 Reserved */
Kojto 111:4336505e4b1c 1094 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
Kojto 111:4336505e4b1c 1095 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 1096 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 1097 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1098 } USB_DEVICE_EPSTATUS_Type;
Kojto 111:4336505e4b1c 1099 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1100
Kojto 111:4336505e4b1c 1101 #define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
Kojto 111:4336505e4b1c 1102 #define USB_DEVICE_EPSTATUS_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
Kojto 111:4336505e4b1c 1103
Kojto 111:4336505e4b1c 1104 #define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
Kojto 111:4336505e4b1c 1105 #define USB_DEVICE_EPSTATUS_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
Kojto 111:4336505e4b1c 1106 #define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
Kojto 111:4336505e4b1c 1107 #define USB_DEVICE_EPSTATUS_DTGLIN (0x1ul << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
Kojto 111:4336505e4b1c 1108 #define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
Kojto 111:4336505e4b1c 1109 #define USB_DEVICE_EPSTATUS_CURBK (0x1ul << USB_DEVICE_EPSTATUS_CURBK_Pos)
Kojto 111:4336505e4b1c 1110 #define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
Kojto 111:4336505e4b1c 1111 #define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
Kojto 111:4336505e4b1c 1112 #define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
Kojto 111:4336505e4b1c 1113 #define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
Kojto 111:4336505e4b1c 1114 #define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
Kojto 111:4336505e4b1c 1115 #define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
Kojto 111:4336505e4b1c 1116 #define USB_DEVICE_EPSTATUS_STALLRQ(value) ((USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)))
Kojto 111:4336505e4b1c 1117 #define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
Kojto 111:4336505e4b1c 1118 #define USB_DEVICE_EPSTATUS_BK0RDY (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
Kojto 111:4336505e4b1c 1119 #define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
Kojto 111:4336505e4b1c 1120 #define USB_DEVICE_EPSTATUS_BK1RDY (0x1ul << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
Kojto 111:4336505e4b1c 1121 #define USB_DEVICE_EPSTATUS_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
Kojto 111:4336505e4b1c 1122
Kojto 111:4336505e4b1c 1123 /* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
Kojto 111:4336505e4b1c 1124 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1125 typedef union {
Kojto 111:4336505e4b1c 1126 struct {
Kojto 111:4336505e4b1c 1127 uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
Kojto 111:4336505e4b1c 1128 uint8_t :1; /*!< bit: 1 Reserved */
Kojto 111:4336505e4b1c 1129 uint8_t CURBK:1; /*!< bit: 2 Current Bank */
Kojto 111:4336505e4b1c 1130 uint8_t :1; /*!< bit: 3 Reserved */
Kojto 111:4336505e4b1c 1131 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
Kojto 111:4336505e4b1c 1132 uint8_t :1; /*!< bit: 5 Reserved */
Kojto 111:4336505e4b1c 1133 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
Kojto 111:4336505e4b1c 1134 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
Kojto 111:4336505e4b1c 1135 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1136 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1137 } USB_HOST_PSTATUS_Type;
Kojto 111:4336505e4b1c 1138 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1139
Kojto 111:4336505e4b1c 1140 #define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
Kojto 111:4336505e4b1c 1141 #define USB_HOST_PSTATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
Kojto 111:4336505e4b1c 1142
Kojto 111:4336505e4b1c 1143 #define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */
Kojto 111:4336505e4b1c 1144 #define USB_HOST_PSTATUS_DTGL (0x1ul << USB_HOST_PSTATUS_DTGL_Pos)
Kojto 111:4336505e4b1c 1145 #define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */
Kojto 111:4336505e4b1c 1146 #define USB_HOST_PSTATUS_CURBK (0x1ul << USB_HOST_PSTATUS_CURBK_Pos)
Kojto 111:4336505e4b1c 1147 #define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
Kojto 111:4336505e4b1c 1148 #define USB_HOST_PSTATUS_PFREEZE (0x1ul << USB_HOST_PSTATUS_PFREEZE_Pos)
Kojto 111:4336505e4b1c 1149 #define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
Kojto 111:4336505e4b1c 1150 #define USB_HOST_PSTATUS_BK0RDY (0x1ul << USB_HOST_PSTATUS_BK0RDY_Pos)
Kojto 111:4336505e4b1c 1151 #define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
Kojto 111:4336505e4b1c 1152 #define USB_HOST_PSTATUS_BK1RDY (0x1ul << USB_HOST_PSTATUS_BK1RDY_Pos)
Kojto 111:4336505e4b1c 1153 #define USB_HOST_PSTATUS_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUS) MASK Register */
Kojto 111:4336505e4b1c 1154
Kojto 111:4336505e4b1c 1155 /* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
Kojto 111:4336505e4b1c 1156 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1157 typedef union {
Kojto 111:4336505e4b1c 1158 struct {
Kojto 111:4336505e4b1c 1159 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
Kojto 111:4336505e4b1c 1160 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
Kojto 111:4336505e4b1c 1161 uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
Kojto 111:4336505e4b1c 1162 uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
Kojto 111:4336505e4b1c 1163 uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
Kojto 111:4336505e4b1c 1164 uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
Kojto 111:4336505e4b1c 1165 uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
Kojto 111:4336505e4b1c 1166 uint8_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 1167 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1168 struct {
Kojto 111:4336505e4b1c 1169 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
Kojto 111:4336505e4b1c 1170 uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
Kojto 111:4336505e4b1c 1171 uint8_t :1; /*!< bit: 4 Reserved */
Kojto 111:4336505e4b1c 1172 uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
Kojto 111:4336505e4b1c 1173 uint8_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 1174 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 1175 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1176 } USB_DEVICE_EPINTFLAG_Type;
Kojto 111:4336505e4b1c 1177 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1178
Kojto 111:4336505e4b1c 1179 #define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
Kojto 111:4336505e4b1c 1180 #define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
Kojto 111:4336505e4b1c 1181
Kojto 111:4336505e4b1c 1182 #define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
Kojto 111:4336505e4b1c 1183 #define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
Kojto 111:4336505e4b1c 1184 #define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
Kojto 111:4336505e4b1c 1185 #define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
Kojto 111:4336505e4b1c 1186 #define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
Kojto 111:4336505e4b1c 1187 #define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
Kojto 111:4336505e4b1c 1188 #define USB_DEVICE_EPINTFLAG_TRCPT(value) ((USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)))
Kojto 111:4336505e4b1c 1189 #define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
Kojto 111:4336505e4b1c 1190 #define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
Kojto 111:4336505e4b1c 1191 #define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
Kojto 111:4336505e4b1c 1192 #define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
Kojto 111:4336505e4b1c 1193 #define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
Kojto 111:4336505e4b1c 1194 #define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
Kojto 111:4336505e4b1c 1195 #define USB_DEVICE_EPINTFLAG_TRFAIL(value) ((USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)))
Kojto 111:4336505e4b1c 1196 #define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
Kojto 111:4336505e4b1c 1197 #define USB_DEVICE_EPINTFLAG_RXSTP (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
Kojto 111:4336505e4b1c 1198 #define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
Kojto 111:4336505e4b1c 1199 #define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos)
Kojto 111:4336505e4b1c 1200 #define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
Kojto 111:4336505e4b1c 1201 #define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos)
Kojto 111:4336505e4b1c 1202 #define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
Kojto 111:4336505e4b1c 1203 #define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos)
Kojto 111:4336505e4b1c 1204 #define USB_DEVICE_EPINTFLAG_STALL(value) ((USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos)))
Kojto 111:4336505e4b1c 1205 #define USB_DEVICE_EPINTFLAG_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
Kojto 111:4336505e4b1c 1206
Kojto 111:4336505e4b1c 1207 /* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
Kojto 111:4336505e4b1c 1208 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1209 typedef union {
Kojto 111:4336505e4b1c 1210 struct {
Kojto 111:4336505e4b1c 1211 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
Kojto 111:4336505e4b1c 1212 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
Kojto 111:4336505e4b1c 1213 uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
Kojto 111:4336505e4b1c 1214 uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
Kojto 111:4336505e4b1c 1215 uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
Kojto 111:4336505e4b1c 1216 uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
Kojto 111:4336505e4b1c 1217 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 1218 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1219 struct {
Kojto 111:4336505e4b1c 1220 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
Kojto 111:4336505e4b1c 1221 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 1222 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 1223 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1224 } USB_HOST_PINTFLAG_Type;
Kojto 111:4336505e4b1c 1225 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1226
Kojto 111:4336505e4b1c 1227 #define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
Kojto 111:4336505e4b1c 1228 #define USB_HOST_PINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
Kojto 111:4336505e4b1c 1229
Kojto 111:4336505e4b1c 1230 #define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
Kojto 111:4336505e4b1c 1231 #define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos)
Kojto 111:4336505e4b1c 1232 #define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
Kojto 111:4336505e4b1c 1233 #define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos)
Kojto 111:4336505e4b1c 1234 #define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
Kojto 111:4336505e4b1c 1235 #define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos)
Kojto 111:4336505e4b1c 1236 #define USB_HOST_PINTFLAG_TRCPT(value) ((USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos)))
Kojto 111:4336505e4b1c 1237 #define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
Kojto 111:4336505e4b1c 1238 #define USB_HOST_PINTFLAG_TRFAIL (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos)
Kojto 111:4336505e4b1c 1239 #define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
Kojto 111:4336505e4b1c 1240 #define USB_HOST_PINTFLAG_PERR (0x1ul << USB_HOST_PINTFLAG_PERR_Pos)
Kojto 111:4336505e4b1c 1241 #define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */
Kojto 111:4336505e4b1c 1242 #define USB_HOST_PINTFLAG_TXSTP (0x1ul << USB_HOST_PINTFLAG_TXSTP_Pos)
Kojto 111:4336505e4b1c 1243 #define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
Kojto 111:4336505e4b1c 1244 #define USB_HOST_PINTFLAG_STALL (0x1ul << USB_HOST_PINTFLAG_STALL_Pos)
Kojto 111:4336505e4b1c 1245 #define USB_HOST_PINTFLAG_MASK 0x3Ful /**< \brief (USB_HOST_PINTFLAG) MASK Register */
Kojto 111:4336505e4b1c 1246
Kojto 111:4336505e4b1c 1247 /* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
Kojto 111:4336505e4b1c 1248 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1249 typedef union {
Kojto 111:4336505e4b1c 1250 struct {
Kojto 111:4336505e4b1c 1251 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
Kojto 111:4336505e4b1c 1252 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
Kojto 111:4336505e4b1c 1253 uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
Kojto 111:4336505e4b1c 1254 uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
Kojto 111:4336505e4b1c 1255 uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
Kojto 111:4336505e4b1c 1256 uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
Kojto 111:4336505e4b1c 1257 uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
Kojto 111:4336505e4b1c 1258 uint8_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 1259 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1260 struct {
Kojto 111:4336505e4b1c 1261 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
Kojto 111:4336505e4b1c 1262 uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
Kojto 111:4336505e4b1c 1263 uint8_t :1; /*!< bit: 4 Reserved */
Kojto 111:4336505e4b1c 1264 uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
Kojto 111:4336505e4b1c 1265 uint8_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 1266 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 1267 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1268 } USB_DEVICE_EPINTENCLR_Type;
Kojto 111:4336505e4b1c 1269 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1270
Kojto 111:4336505e4b1c 1271 #define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
Kojto 111:4336505e4b1c 1272 #define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
Kojto 111:4336505e4b1c 1273
Kojto 111:4336505e4b1c 1274 #define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
Kojto 111:4336505e4b1c 1275 #define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
Kojto 111:4336505e4b1c 1276 #define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
Kojto 111:4336505e4b1c 1277 #define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
Kojto 111:4336505e4b1c 1278 #define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
Kojto 111:4336505e4b1c 1279 #define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
Kojto 111:4336505e4b1c 1280 #define USB_DEVICE_EPINTENCLR_TRCPT(value) ((USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)))
Kojto 111:4336505e4b1c 1281 #define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
Kojto 111:4336505e4b1c 1282 #define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
Kojto 111:4336505e4b1c 1283 #define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
Kojto 111:4336505e4b1c 1284 #define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
Kojto 111:4336505e4b1c 1285 #define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
Kojto 111:4336505e4b1c 1286 #define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
Kojto 111:4336505e4b1c 1287 #define USB_DEVICE_EPINTENCLR_TRFAIL(value) ((USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)))
Kojto 111:4336505e4b1c 1288 #define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
Kojto 111:4336505e4b1c 1289 #define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
Kojto 111:4336505e4b1c 1290 #define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
Kojto 111:4336505e4b1c 1291 #define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos)
Kojto 111:4336505e4b1c 1292 #define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
Kojto 111:4336505e4b1c 1293 #define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos)
Kojto 111:4336505e4b1c 1294 #define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
Kojto 111:4336505e4b1c 1295 #define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos)
Kojto 111:4336505e4b1c 1296 #define USB_DEVICE_EPINTENCLR_STALL(value) ((USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos)))
Kojto 111:4336505e4b1c 1297 #define USB_DEVICE_EPINTENCLR_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
Kojto 111:4336505e4b1c 1298
Kojto 111:4336505e4b1c 1299 /* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
Kojto 111:4336505e4b1c 1300 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1301 typedef union {
Kojto 111:4336505e4b1c 1302 struct {
Kojto 111:4336505e4b1c 1303 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
Kojto 111:4336505e4b1c 1304 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
Kojto 111:4336505e4b1c 1305 uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
Kojto 111:4336505e4b1c 1306 uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
Kojto 111:4336505e4b1c 1307 uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
Kojto 111:4336505e4b1c 1308 uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Disable */
Kojto 111:4336505e4b1c 1309 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 1310 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1311 struct {
Kojto 111:4336505e4b1c 1312 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
Kojto 111:4336505e4b1c 1313 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 1314 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 1315 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1316 } USB_HOST_PINTENCLR_Type;
Kojto 111:4336505e4b1c 1317 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1318
Kojto 111:4336505e4b1c 1319 #define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
Kojto 111:4336505e4b1c 1320 #define USB_HOST_PINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
Kojto 111:4336505e4b1c 1321
Kojto 111:4336505e4b1c 1322 #define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
Kojto 111:4336505e4b1c 1323 #define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos)
Kojto 111:4336505e4b1c 1324 #define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
Kojto 111:4336505e4b1c 1325 #define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos)
Kojto 111:4336505e4b1c 1326 #define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
Kojto 111:4336505e4b1c 1327 #define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos)
Kojto 111:4336505e4b1c 1328 #define USB_HOST_PINTENCLR_TRCPT(value) ((USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos)))
Kojto 111:4336505e4b1c 1329 #define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
Kojto 111:4336505e4b1c 1330 #define USB_HOST_PINTENCLR_TRFAIL (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos)
Kojto 111:4336505e4b1c 1331 #define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
Kojto 111:4336505e4b1c 1332 #define USB_HOST_PINTENCLR_PERR (0x1ul << USB_HOST_PINTENCLR_PERR_Pos)
Kojto 111:4336505e4b1c 1333 #define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */
Kojto 111:4336505e4b1c 1334 #define USB_HOST_PINTENCLR_TXSTP (0x1ul << USB_HOST_PINTENCLR_TXSTP_Pos)
Kojto 111:4336505e4b1c 1335 #define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Interrupt Disable */
Kojto 111:4336505e4b1c 1336 #define USB_HOST_PINTENCLR_STALL (0x1ul << USB_HOST_PINTENCLR_STALL_Pos)
Kojto 111:4336505e4b1c 1337 #define USB_HOST_PINTENCLR_MASK 0x3Ful /**< \brief (USB_HOST_PINTENCLR) MASK Register */
Kojto 111:4336505e4b1c 1338
Kojto 111:4336505e4b1c 1339 /* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
Kojto 111:4336505e4b1c 1340 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1341 typedef union {
Kojto 111:4336505e4b1c 1342 struct {
Kojto 111:4336505e4b1c 1343 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
Kojto 111:4336505e4b1c 1344 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
Kojto 111:4336505e4b1c 1345 uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
Kojto 111:4336505e4b1c 1346 uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
Kojto 111:4336505e4b1c 1347 uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
Kojto 111:4336505e4b1c 1348 uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
Kojto 111:4336505e4b1c 1349 uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
Kojto 111:4336505e4b1c 1350 uint8_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 1351 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1352 struct {
Kojto 111:4336505e4b1c 1353 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
Kojto 111:4336505e4b1c 1354 uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
Kojto 111:4336505e4b1c 1355 uint8_t :1; /*!< bit: 4 Reserved */
Kojto 111:4336505e4b1c 1356 uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
Kojto 111:4336505e4b1c 1357 uint8_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 1358 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 1359 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1360 } USB_DEVICE_EPINTENSET_Type;
Kojto 111:4336505e4b1c 1361 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1362
Kojto 111:4336505e4b1c 1363 #define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
Kojto 111:4336505e4b1c 1364 #define USB_DEVICE_EPINTENSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
Kojto 111:4336505e4b1c 1365
Kojto 111:4336505e4b1c 1366 #define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
Kojto 111:4336505e4b1c 1367 #define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
Kojto 111:4336505e4b1c 1368 #define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
Kojto 111:4336505e4b1c 1369 #define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
Kojto 111:4336505e4b1c 1370 #define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
Kojto 111:4336505e4b1c 1371 #define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos)
Kojto 111:4336505e4b1c 1372 #define USB_DEVICE_EPINTENSET_TRCPT(value) ((USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos)))
Kojto 111:4336505e4b1c 1373 #define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
Kojto 111:4336505e4b1c 1374 #define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
Kojto 111:4336505e4b1c 1375 #define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
Kojto 111:4336505e4b1c 1376 #define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
Kojto 111:4336505e4b1c 1377 #define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
Kojto 111:4336505e4b1c 1378 #define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
Kojto 111:4336505e4b1c 1379 #define USB_DEVICE_EPINTENSET_TRFAIL(value) ((USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)))
Kojto 111:4336505e4b1c 1380 #define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
Kojto 111:4336505e4b1c 1381 #define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos)
Kojto 111:4336505e4b1c 1382 #define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
Kojto 111:4336505e4b1c 1383 #define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos)
Kojto 111:4336505e4b1c 1384 #define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
Kojto 111:4336505e4b1c 1385 #define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos)
Kojto 111:4336505e4b1c 1386 #define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
Kojto 111:4336505e4b1c 1387 #define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos)
Kojto 111:4336505e4b1c 1388 #define USB_DEVICE_EPINTENSET_STALL(value) ((USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos)))
Kojto 111:4336505e4b1c 1389 #define USB_DEVICE_EPINTENSET_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
Kojto 111:4336505e4b1c 1390
Kojto 111:4336505e4b1c 1391 /* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
Kojto 111:4336505e4b1c 1392 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1393 typedef union {
Kojto 111:4336505e4b1c 1394 struct {
Kojto 111:4336505e4b1c 1395 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
Kojto 111:4336505e4b1c 1396 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
Kojto 111:4336505e4b1c 1397 uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
Kojto 111:4336505e4b1c 1398 uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
Kojto 111:4336505e4b1c 1399 uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
Kojto 111:4336505e4b1c 1400 uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
Kojto 111:4336505e4b1c 1401 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 1402 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1403 struct {
Kojto 111:4336505e4b1c 1404 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
Kojto 111:4336505e4b1c 1405 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 1406 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 1407 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1408 } USB_HOST_PINTENSET_Type;
Kojto 111:4336505e4b1c 1409 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1410
Kojto 111:4336505e4b1c 1411 #define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
Kojto 111:4336505e4b1c 1412 #define USB_HOST_PINTENSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
Kojto 111:4336505e4b1c 1413
Kojto 111:4336505e4b1c 1414 #define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
Kojto 111:4336505e4b1c 1415 #define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos)
Kojto 111:4336505e4b1c 1416 #define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
Kojto 111:4336505e4b1c 1417 #define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos)
Kojto 111:4336505e4b1c 1418 #define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
Kojto 111:4336505e4b1c 1419 #define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos)
Kojto 111:4336505e4b1c 1420 #define USB_HOST_PINTENSET_TRCPT(value) ((USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos)))
Kojto 111:4336505e4b1c 1421 #define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
Kojto 111:4336505e4b1c 1422 #define USB_HOST_PINTENSET_TRFAIL (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos)
Kojto 111:4336505e4b1c 1423 #define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
Kojto 111:4336505e4b1c 1424 #define USB_HOST_PINTENSET_PERR (0x1ul << USB_HOST_PINTENSET_PERR_Pos)
Kojto 111:4336505e4b1c 1425 #define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */
Kojto 111:4336505e4b1c 1426 #define USB_HOST_PINTENSET_TXSTP (0x1ul << USB_HOST_PINTENSET_TXSTP_Pos)
Kojto 111:4336505e4b1c 1427 #define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
Kojto 111:4336505e4b1c 1428 #define USB_HOST_PINTENSET_STALL (0x1ul << USB_HOST_PINTENSET_STALL_Pos)
Kojto 111:4336505e4b1c 1429 #define USB_HOST_PINTENSET_MASK 0x3Ful /**< \brief (USB_HOST_PINTENSET) MASK Register */
Kojto 111:4336505e4b1c 1430
Kojto 111:4336505e4b1c 1431 /* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
Kojto 111:4336505e4b1c 1432 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1433 typedef union {
Kojto 111:4336505e4b1c 1434 struct {
Kojto 111:4336505e4b1c 1435 uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
Kojto 111:4336505e4b1c 1436 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1437 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1438 } USB_DEVICE_ADDR_Type;
Kojto 111:4336505e4b1c 1439 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1440
Kojto 111:4336505e4b1c 1441 #define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
Kojto 111:4336505e4b1c 1442
Kojto 111:4336505e4b1c 1443 #define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
Kojto 111:4336505e4b1c 1444 #define USB_DEVICE_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos)
Kojto 111:4336505e4b1c 1445 #define USB_DEVICE_ADDR_ADDR(value) ((USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos)))
Kojto 111:4336505e4b1c 1446 #define USB_DEVICE_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */
Kojto 111:4336505e4b1c 1447
Kojto 111:4336505e4b1c 1448 /* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
Kojto 111:4336505e4b1c 1449 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1450 typedef union {
Kojto 111:4336505e4b1c 1451 struct {
Kojto 111:4336505e4b1c 1452 uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
Kojto 111:4336505e4b1c 1453 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1454 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1455 } USB_HOST_ADDR_Type;
Kojto 111:4336505e4b1c 1456 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1457
Kojto 111:4336505e4b1c 1458 #define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
Kojto 111:4336505e4b1c 1459
Kojto 111:4336505e4b1c 1460 #define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */
Kojto 111:4336505e4b1c 1461 #define USB_HOST_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos)
Kojto 111:4336505e4b1c 1462 #define USB_HOST_ADDR_ADDR(value) ((USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos)))
Kojto 111:4336505e4b1c 1463 #define USB_HOST_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */
Kojto 111:4336505e4b1c 1464
Kojto 111:4336505e4b1c 1465 /* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
Kojto 111:4336505e4b1c 1466 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1467 typedef union {
Kojto 111:4336505e4b1c 1468 struct {
Kojto 111:4336505e4b1c 1469 uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
Kojto 111:4336505e4b1c 1470 uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
Kojto 111:4336505e4b1c 1471 uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
Kojto 111:4336505e4b1c 1472 uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
Kojto 111:4336505e4b1c 1473 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1474 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1475 } USB_DEVICE_PCKSIZE_Type;
Kojto 111:4336505e4b1c 1476 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1477
Kojto 111:4336505e4b1c 1478 #define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
Kojto 111:4336505e4b1c 1479
Kojto 111:4336505e4b1c 1480 #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
Kojto 111:4336505e4b1c 1481 #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
Kojto 111:4336505e4b1c 1482 #define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) ((USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)))
Kojto 111:4336505e4b1c 1483 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
Kojto 111:4336505e4b1c 1484 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
Kojto 111:4336505e4b1c 1485 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)))
Kojto 111:4336505e4b1c 1486 #define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
Kojto 111:4336505e4b1c 1487 #define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos)
Kojto 111:4336505e4b1c 1488 #define USB_DEVICE_PCKSIZE_SIZE(value) ((USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos)))
Kojto 111:4336505e4b1c 1489 #define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
Kojto 111:4336505e4b1c 1490 #define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
Kojto 111:4336505e4b1c 1491 #define USB_DEVICE_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
Kojto 111:4336505e4b1c 1492
Kojto 111:4336505e4b1c 1493 /* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
Kojto 111:4336505e4b1c 1494 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1495 typedef union {
Kojto 111:4336505e4b1c 1496 struct {
Kojto 111:4336505e4b1c 1497 uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
Kojto 111:4336505e4b1c 1498 uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
Kojto 111:4336505e4b1c 1499 uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
Kojto 111:4336505e4b1c 1500 uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
Kojto 111:4336505e4b1c 1501 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1502 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1503 } USB_HOST_PCKSIZE_Type;
Kojto 111:4336505e4b1c 1504 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1505
Kojto 111:4336505e4b1c 1506 #define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
Kojto 111:4336505e4b1c 1507
Kojto 111:4336505e4b1c 1508 #define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */
Kojto 111:4336505e4b1c 1509 #define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
Kojto 111:4336505e4b1c 1510 #define USB_HOST_PCKSIZE_BYTE_COUNT(value) ((USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)))
Kojto 111:4336505e4b1c 1511 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
Kojto 111:4336505e4b1c 1512 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
Kojto 111:4336505e4b1c 1513 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)))
Kojto 111:4336505e4b1c 1514 #define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */
Kojto 111:4336505e4b1c 1515 #define USB_HOST_PCKSIZE_SIZE_Msk (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos)
Kojto 111:4336505e4b1c 1516 #define USB_HOST_PCKSIZE_SIZE(value) ((USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos)))
Kojto 111:4336505e4b1c 1517 #define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
Kojto 111:4336505e4b1c 1518 #define USB_HOST_PCKSIZE_AUTO_ZLP (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
Kojto 111:4336505e4b1c 1519 #define USB_HOST_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */
Kojto 111:4336505e4b1c 1520
Kojto 111:4336505e4b1c 1521 /* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
Kojto 111:4336505e4b1c 1522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1523 typedef union {
Kojto 111:4336505e4b1c 1524 struct {
Kojto 111:4336505e4b1c 1525 uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
Kojto 111:4336505e4b1c 1526 uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
Kojto 111:4336505e4b1c 1527 uint16_t :1; /*!< bit: 15 Reserved */
Kojto 111:4336505e4b1c 1528 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1529 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1530 } USB_DEVICE_EXTREG_Type;
Kojto 111:4336505e4b1c 1531 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1532
Kojto 111:4336505e4b1c 1533 #define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
Kojto 111:4336505e4b1c 1534
Kojto 111:4336505e4b1c 1535 #define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
Kojto 111:4336505e4b1c 1536 #define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos)
Kojto 111:4336505e4b1c 1537 #define USB_DEVICE_EXTREG_SUBPID(value) ((USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos)))
Kojto 111:4336505e4b1c 1538 #define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
Kojto 111:4336505e4b1c 1539 #define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos)
Kojto 111:4336505e4b1c 1540 #define USB_DEVICE_EXTREG_VARIABLE(value) ((USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos)))
Kojto 111:4336505e4b1c 1541 #define USB_DEVICE_EXTREG_MASK 0x7FFFul /**< \brief (USB_DEVICE_EXTREG) MASK Register */
Kojto 111:4336505e4b1c 1542
Kojto 111:4336505e4b1c 1543 /* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
Kojto 111:4336505e4b1c 1544 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1545 typedef union {
Kojto 111:4336505e4b1c 1546 struct {
Kojto 111:4336505e4b1c 1547 uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
Kojto 111:4336505e4b1c 1548 uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
Kojto 111:4336505e4b1c 1549 uint16_t :1; /*!< bit: 15 Reserved */
Kojto 111:4336505e4b1c 1550 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1551 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1552 } USB_HOST_EXTREG_Type;
Kojto 111:4336505e4b1c 1553 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1554
Kojto 111:4336505e4b1c 1555 #define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
Kojto 111:4336505e4b1c 1556
Kojto 111:4336505e4b1c 1557 #define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
Kojto 111:4336505e4b1c 1558 #define USB_HOST_EXTREG_SUBPID_Msk (0xFul << USB_HOST_EXTREG_SUBPID_Pos)
Kojto 111:4336505e4b1c 1559 #define USB_HOST_EXTREG_SUBPID(value) ((USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos)))
Kojto 111:4336505e4b1c 1560 #define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
Kojto 111:4336505e4b1c 1561 #define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos)
Kojto 111:4336505e4b1c 1562 #define USB_HOST_EXTREG_VARIABLE(value) ((USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos)))
Kojto 111:4336505e4b1c 1563 #define USB_HOST_EXTREG_MASK 0x7FFFul /**< \brief (USB_HOST_EXTREG) MASK Register */
Kojto 111:4336505e4b1c 1564
Kojto 111:4336505e4b1c 1565 /* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
Kojto 111:4336505e4b1c 1566 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1567 typedef union {
Kojto 111:4336505e4b1c 1568 struct {
Kojto 111:4336505e4b1c 1569 uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
Kojto 111:4336505e4b1c 1570 uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
Kojto 111:4336505e4b1c 1571 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 1572 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1573 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1574 } USB_DEVICE_STATUS_BK_Type;
Kojto 111:4336505e4b1c 1575 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1576
Kojto 111:4336505e4b1c 1577 #define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
Kojto 111:4336505e4b1c 1578
Kojto 111:4336505e4b1c 1579 #define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
Kojto 111:4336505e4b1c 1580 #define USB_DEVICE_STATUS_BK_CRCERR (0x1ul << USB_DEVICE_STATUS_BK_CRCERR_Pos)
Kojto 111:4336505e4b1c 1581 #define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
Kojto 111:4336505e4b1c 1582 #define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1ul << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
Kojto 111:4336505e4b1c 1583 #define USB_DEVICE_STATUS_BK_MASK 0x03ul /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
Kojto 111:4336505e4b1c 1584
Kojto 111:4336505e4b1c 1585 /* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
Kojto 111:4336505e4b1c 1586 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1587 typedef union {
Kojto 111:4336505e4b1c 1588 struct {
Kojto 111:4336505e4b1c 1589 uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
Kojto 111:4336505e4b1c 1590 uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
Kojto 111:4336505e4b1c 1591 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 1592 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1593 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1594 } USB_HOST_STATUS_BK_Type;
Kojto 111:4336505e4b1c 1595 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1596
Kojto 111:4336505e4b1c 1597 #define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
Kojto 111:4336505e4b1c 1598
Kojto 111:4336505e4b1c 1599 #define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
Kojto 111:4336505e4b1c 1600 #define USB_HOST_STATUS_BK_CRCERR (0x1ul << USB_HOST_STATUS_BK_CRCERR_Pos)
Kojto 111:4336505e4b1c 1601 #define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
Kojto 111:4336505e4b1c 1602 #define USB_HOST_STATUS_BK_ERRORFLOW (0x1ul << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
Kojto 111:4336505e4b1c 1603 #define USB_HOST_STATUS_BK_MASK 0x03ul /**< \brief (USB_HOST_STATUS_BK) MASK Register */
Kojto 111:4336505e4b1c 1604
Kojto 111:4336505e4b1c 1605 /* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
Kojto 111:4336505e4b1c 1606 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1607 typedef union {
Kojto 111:4336505e4b1c 1608 struct {
Kojto 111:4336505e4b1c 1609 uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
Kojto 111:4336505e4b1c 1610 uint16_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 1611 uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
Kojto 111:4336505e4b1c 1612 uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
Kojto 111:4336505e4b1c 1613 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1614 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1615 } USB_HOST_CTRL_PIPE_Type;
Kojto 111:4336505e4b1c 1616 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1617
Kojto 111:4336505e4b1c 1618 #define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
Kojto 111:4336505e4b1c 1619 #define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
Kojto 111:4336505e4b1c 1620
Kojto 111:4336505e4b1c 1621 #define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
Kojto 111:4336505e4b1c 1622 #define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos)
Kojto 111:4336505e4b1c 1623 #define USB_HOST_CTRL_PIPE_PDADDR(value) ((USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos)))
Kojto 111:4336505e4b1c 1624 #define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
Kojto 111:4336505e4b1c 1625 #define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
Kojto 111:4336505e4b1c 1626 #define USB_HOST_CTRL_PIPE_PEPNUM(value) ((USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)))
Kojto 111:4336505e4b1c 1627 #define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
Kojto 111:4336505e4b1c 1628 #define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos)
Kojto 111:4336505e4b1c 1629 #define USB_HOST_CTRL_PIPE_PERMAX(value) ((USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos)))
Kojto 111:4336505e4b1c 1630 #define USB_HOST_CTRL_PIPE_MASK 0xFF7Ful /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
Kojto 111:4336505e4b1c 1631
Kojto 111:4336505e4b1c 1632 /* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
Kojto 111:4336505e4b1c 1633 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1634 typedef union {
Kojto 111:4336505e4b1c 1635 struct {
Kojto 111:4336505e4b1c 1636 uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
Kojto 111:4336505e4b1c 1637 uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
Kojto 111:4336505e4b1c 1638 uint16_t PIDER:1; /*!< bit: 2 PID Error */
Kojto 111:4336505e4b1c 1639 uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
Kojto 111:4336505e4b1c 1640 uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
Kojto 111:4336505e4b1c 1641 uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
Kojto 111:4336505e4b1c 1642 uint16_t :8; /*!< bit: 8..15 Reserved */
Kojto 111:4336505e4b1c 1643 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1644 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1645 } USB_HOST_STATUS_PIPE_Type;
Kojto 111:4336505e4b1c 1646 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1647
Kojto 111:4336505e4b1c 1648 #define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
Kojto 111:4336505e4b1c 1649
Kojto 111:4336505e4b1c 1650 #define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
Kojto 111:4336505e4b1c 1651 #define USB_HOST_STATUS_PIPE_DTGLER (0x1ul << USB_HOST_STATUS_PIPE_DTGLER_Pos)
Kojto 111:4336505e4b1c 1652 #define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
Kojto 111:4336505e4b1c 1653 #define USB_HOST_STATUS_PIPE_DAPIDER (0x1ul << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
Kojto 111:4336505e4b1c 1654 #define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
Kojto 111:4336505e4b1c 1655 #define USB_HOST_STATUS_PIPE_PIDER (0x1ul << USB_HOST_STATUS_PIPE_PIDER_Pos)
Kojto 111:4336505e4b1c 1656 #define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
Kojto 111:4336505e4b1c 1657 #define USB_HOST_STATUS_PIPE_TOUTER (0x1ul << USB_HOST_STATUS_PIPE_TOUTER_Pos)
Kojto 111:4336505e4b1c 1658 #define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
Kojto 111:4336505e4b1c 1659 #define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
Kojto 111:4336505e4b1c 1660 #define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
Kojto 111:4336505e4b1c 1661 #define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos)
Kojto 111:4336505e4b1c 1662 #define USB_HOST_STATUS_PIPE_ERCNT(value) ((USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos)))
Kojto 111:4336505e4b1c 1663 #define USB_HOST_STATUS_PIPE_MASK 0x00FFul /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
Kojto 111:4336505e4b1c 1664
Kojto 111:4336505e4b1c 1665 /** \brief UsbDeviceDescBank SRAM registers */
Kojto 111:4336505e4b1c 1666 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1667 typedef struct {
Kojto 111:4336505e4b1c 1668 __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
Kojto 111:4336505e4b1c 1669 __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
Kojto 111:4336505e4b1c 1670 __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
Kojto 111:4336505e4b1c 1671 __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
Kojto 111:4336505e4b1c 1672 RoReg8 Reserved1[0x5];
Kojto 111:4336505e4b1c 1673 } UsbDeviceDescBank;
Kojto 111:4336505e4b1c 1674 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1675
Kojto 111:4336505e4b1c 1676 /** \brief UsbHostDescBank SRAM registers */
Kojto 111:4336505e4b1c 1677 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1678 typedef struct {
Kojto 111:4336505e4b1c 1679 __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
Kojto 111:4336505e4b1c 1680 __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
Kojto 111:4336505e4b1c 1681 __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
Kojto 111:4336505e4b1c 1682 __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
Kojto 111:4336505e4b1c 1683 RoReg8 Reserved1[0x1];
Kojto 111:4336505e4b1c 1684 __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
Kojto 111:4336505e4b1c 1685 __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
Kojto 111:4336505e4b1c 1686 } UsbHostDescBank;
Kojto 111:4336505e4b1c 1687 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1688
Kojto 111:4336505e4b1c 1689 /** \brief UsbDeviceEndpoint hardware registers */
Kojto 111:4336505e4b1c 1690 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1691 typedef struct {
Kojto 111:4336505e4b1c 1692 __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
Kojto 111:4336505e4b1c 1693 RoReg8 Reserved1[0x3];
Kojto 111:4336505e4b1c 1694 __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
Kojto 111:4336505e4b1c 1695 __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
Kojto 111:4336505e4b1c 1696 __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
Kojto 111:4336505e4b1c 1697 __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
Kojto 111:4336505e4b1c 1698 __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
Kojto 111:4336505e4b1c 1699 __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
Kojto 111:4336505e4b1c 1700 RoReg8 Reserved2[0x16];
Kojto 111:4336505e4b1c 1701 } UsbDeviceEndpoint;
Kojto 111:4336505e4b1c 1702 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1703
Kojto 111:4336505e4b1c 1704 /** \brief UsbHostPipe hardware registers */
Kojto 111:4336505e4b1c 1705 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1706 typedef struct {
Kojto 111:4336505e4b1c 1707 __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
Kojto 111:4336505e4b1c 1708 RoReg8 Reserved1[0x2];
Kojto 111:4336505e4b1c 1709 __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
Kojto 111:4336505e4b1c 1710 __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
Kojto 111:4336505e4b1c 1711 __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
Kojto 111:4336505e4b1c 1712 __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
Kojto 111:4336505e4b1c 1713 __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
Kojto 111:4336505e4b1c 1714 __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
Kojto 111:4336505e4b1c 1715 __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
Kojto 111:4336505e4b1c 1716 RoReg8 Reserved2[0x16];
Kojto 111:4336505e4b1c 1717 } UsbHostPipe;
Kojto 111:4336505e4b1c 1718 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1719
Kojto 111:4336505e4b1c 1720 /** \brief USB_DEVICE APB hardware registers */
Kojto 111:4336505e4b1c 1721 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1722 typedef struct { /* USB is Device */
Kojto 111:4336505e4b1c 1723 __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
Kojto 111:4336505e4b1c 1724 RoReg8 Reserved1[0x1];
Kojto 111:4336505e4b1c 1725 __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
Kojto 111:4336505e4b1c 1726 __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
Kojto 111:4336505e4b1c 1727 RoReg8 Reserved2[0x4];
Kojto 111:4336505e4b1c 1728 __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
Kojto 111:4336505e4b1c 1729 __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
Kojto 111:4336505e4b1c 1730 RoReg8 Reserved3[0x1];
Kojto 111:4336505e4b1c 1731 __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
Kojto 111:4336505e4b1c 1732 __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
Kojto 111:4336505e4b1c 1733 RoReg8 Reserved4[0x2];
Kojto 111:4336505e4b1c 1734 __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
Kojto 111:4336505e4b1c 1735 RoReg8 Reserved5[0x2];
Kojto 111:4336505e4b1c 1736 __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
Kojto 111:4336505e4b1c 1737 RoReg8 Reserved6[0x2];
Kojto 111:4336505e4b1c 1738 __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
Kojto 111:4336505e4b1c 1739 RoReg8 Reserved7[0x2];
Kojto 111:4336505e4b1c 1740 __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
Kojto 111:4336505e4b1c 1741 RoReg8 Reserved8[0x2];
Kojto 111:4336505e4b1c 1742 __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
Kojto 111:4336505e4b1c 1743 RoReg8 Reserved9[0x2];
Kojto 111:4336505e4b1c 1744 __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
Kojto 111:4336505e4b1c 1745 __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
Kojto 111:4336505e4b1c 1746 RoReg8 Reserved10[0xD6];
Kojto 111:4336505e4b1c 1747 UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
Kojto 111:4336505e4b1c 1748 } UsbDevice;
Kojto 111:4336505e4b1c 1749 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1750
Kojto 111:4336505e4b1c 1751 /** \brief USB_HOST hardware registers */
Kojto 111:4336505e4b1c 1752 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1753 typedef struct { /* USB is Host */
Kojto 111:4336505e4b1c 1754 __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
Kojto 111:4336505e4b1c 1755 RoReg8 Reserved1[0x1];
Kojto 111:4336505e4b1c 1756 __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
Kojto 111:4336505e4b1c 1757 __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
Kojto 111:4336505e4b1c 1758 RoReg8 Reserved2[0x4];
Kojto 111:4336505e4b1c 1759 __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
Kojto 111:4336505e4b1c 1760 __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
Kojto 111:4336505e4b1c 1761 RoReg8 Reserved3[0x1];
Kojto 111:4336505e4b1c 1762 __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
Kojto 111:4336505e4b1c 1763 __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
Kojto 111:4336505e4b1c 1764 RoReg8 Reserved4[0x2];
Kojto 111:4336505e4b1c 1765 __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
Kojto 111:4336505e4b1c 1766 __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
Kojto 111:4336505e4b1c 1767 RoReg8 Reserved5[0x1];
Kojto 111:4336505e4b1c 1768 __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
Kojto 111:4336505e4b1c 1769 RoReg8 Reserved6[0x2];
Kojto 111:4336505e4b1c 1770 __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
Kojto 111:4336505e4b1c 1771 RoReg8 Reserved7[0x2];
Kojto 111:4336505e4b1c 1772 __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
Kojto 111:4336505e4b1c 1773 RoReg8 Reserved8[0x2];
Kojto 111:4336505e4b1c 1774 __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
Kojto 111:4336505e4b1c 1775 RoReg8 Reserved9[0x2];
Kojto 111:4336505e4b1c 1776 __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
Kojto 111:4336505e4b1c 1777 __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
Kojto 111:4336505e4b1c 1778 RoReg8 Reserved10[0xD6];
Kojto 111:4336505e4b1c 1779 UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
Kojto 111:4336505e4b1c 1780 } UsbHost;
Kojto 111:4336505e4b1c 1781 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1782
Kojto 111:4336505e4b1c 1783 /** \brief USB_DEVICE Descriptor SRAM registers */
Kojto 111:4336505e4b1c 1784 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1785 typedef struct { /* USB is Device */
Kojto 111:4336505e4b1c 1786 UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
Kojto 111:4336505e4b1c 1787 } UsbDeviceDescriptor;
Kojto 111:4336505e4b1c 1788 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1789
Kojto 111:4336505e4b1c 1790 /** \brief USB_HOST Descriptor SRAM registers */
Kojto 111:4336505e4b1c 1791 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1792 typedef struct { /* USB is Host */
Kojto 111:4336505e4b1c 1793 UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
Kojto 111:4336505e4b1c 1794 } UsbHostDescriptor;
Kojto 111:4336505e4b1c 1795 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1796 #define SECTION_USB_DESCRIPTOR
Kojto 111:4336505e4b1c 1797
Kojto 111:4336505e4b1c 1798 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1799 typedef union {
Kojto 111:4336505e4b1c 1800 UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
Kojto 111:4336505e4b1c 1801 UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
Kojto 111:4336505e4b1c 1802 } Usb;
Kojto 111:4336505e4b1c 1803 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1804
Kojto 111:4336505e4b1c 1805 /*@}*/
Kojto 111:4336505e4b1c 1806
Kojto 111:4336505e4b1c 1807 #endif /* _SAMD21_USB_COMPONENT_ */