Elijah Orr / mbed-renbed

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TARGET_SAMD21G18A/comp_sysctrl.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
111:4336505e4b1c 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for SYSCTRL
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43 /*
Kojto 111:4336505e4b1c 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
Kojto 111:4336505e4b1c 45 */
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 #ifndef _SAMD21_SYSCTRL_COMPONENT_
Kojto 111:4336505e4b1c 48 #define _SAMD21_SYSCTRL_COMPONENT_
Kojto 111:4336505e4b1c 49
Kojto 111:4336505e4b1c 50 /* ========================================================================== */
Kojto 111:4336505e4b1c 51 /** SOFTWARE API DEFINITION FOR SYSCTRL */
Kojto 111:4336505e4b1c 52 /* ========================================================================== */
Kojto 111:4336505e4b1c 53 /** \addtogroup SAMD21_SYSCTRL System Control */
Kojto 111:4336505e4b1c 54 /*@{*/
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 #define SYSCTRL_U2100
Kojto 111:4336505e4b1c 57 #define REV_SYSCTRL 0x201
Kojto 111:4336505e4b1c 58
Kojto 111:4336505e4b1c 59 /* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 61 typedef union {
Kojto 111:4336505e4b1c 62 struct {
Kojto 111:4336505e4b1c 63 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
Kojto 111:4336505e4b1c 64 uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
Kojto 111:4336505e4b1c 65 uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
Kojto 111:4336505e4b1c 66 uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
Kojto 111:4336505e4b1c 67 uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
Kojto 111:4336505e4b1c 68 uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
Kojto 111:4336505e4b1c 69 uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
Kojto 111:4336505e4b1c 70 uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
Kojto 111:4336505e4b1c 71 uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
Kojto 111:4336505e4b1c 72 uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
Kojto 111:4336505e4b1c 73 uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
Kojto 111:4336505e4b1c 74 uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 75 uint32_t :3; /*!< bit: 12..14 Reserved */
Kojto 111:4336505e4b1c 76 uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
Kojto 111:4336505e4b1c 77 uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
Kojto 111:4336505e4b1c 78 uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
Kojto 111:4336505e4b1c 79 uint32_t :14; /*!< bit: 18..31 Reserved */
Kojto 111:4336505e4b1c 80 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 81 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 82 } SYSCTRL_INTENCLR_Type;
Kojto 111:4336505e4b1c 83 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 84
Kojto 111:4336505e4b1c 85 #define SYSCTRL_INTENCLR_OFFSET 0x00 /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 86 #define SYSCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 87
Kojto 111:4336505e4b1c 88 #define SYSCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */
Kojto 111:4336505e4b1c 89 #define SYSCTRL_INTENCLR_XOSCRDY (0x1ul << SYSCTRL_INTENCLR_XOSCRDY_Pos)
Kojto 111:4336505e4b1c 90 #define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
Kojto 111:4336505e4b1c 91 #define SYSCTRL_INTENCLR_XOSC32KRDY (0x1ul << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)
Kojto 111:4336505e4b1c 92 #define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
Kojto 111:4336505e4b1c 93 #define SYSCTRL_INTENCLR_OSC32KRDY (0x1ul << SYSCTRL_INTENCLR_OSC32KRDY_Pos)
Kojto 111:4336505e4b1c 94 #define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */
Kojto 111:4336505e4b1c 95 #define SYSCTRL_INTENCLR_OSC8MRDY (0x1ul << SYSCTRL_INTENCLR_OSC8MRDY_Pos)
Kojto 111:4336505e4b1c 96 #define SYSCTRL_INTENCLR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */
Kojto 111:4336505e4b1c 97 #define SYSCTRL_INTENCLR_DFLLRDY (0x1ul << SYSCTRL_INTENCLR_DFLLRDY_Pos)
Kojto 111:4336505e4b1c 98 #define SYSCTRL_INTENCLR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
Kojto 111:4336505e4b1c 99 #define SYSCTRL_INTENCLR_DFLLOOB (0x1ul << SYSCTRL_INTENCLR_DFLLOOB_Pos)
Kojto 111:4336505e4b1c 100 #define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
Kojto 111:4336505e4b1c 101 #define SYSCTRL_INTENCLR_DFLLLCKF (0x1ul << SYSCTRL_INTENCLR_DFLLLCKF_Pos)
Kojto 111:4336505e4b1c 102 #define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
Kojto 111:4336505e4b1c 103 #define SYSCTRL_INTENCLR_DFLLLCKC (0x1ul << SYSCTRL_INTENCLR_DFLLLCKC_Pos)
Kojto 111:4336505e4b1c 104 #define SYSCTRL_INTENCLR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
Kojto 111:4336505e4b1c 105 #define SYSCTRL_INTENCLR_DFLLRCS (0x1ul << SYSCTRL_INTENCLR_DFLLRCS_Pos)
Kojto 111:4336505e4b1c 106 #define SYSCTRL_INTENCLR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */
Kojto 111:4336505e4b1c 107 #define SYSCTRL_INTENCLR_BOD33RDY (0x1ul << SYSCTRL_INTENCLR_BOD33RDY_Pos)
Kojto 111:4336505e4b1c 108 #define SYSCTRL_INTENCLR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */
Kojto 111:4336505e4b1c 109 #define SYSCTRL_INTENCLR_BOD33DET (0x1ul << SYSCTRL_INTENCLR_BOD33DET_Pos)
Kojto 111:4336505e4b1c 110 #define SYSCTRL_INTENCLR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 111 #define SYSCTRL_INTENCLR_B33SRDY (0x1ul << SYSCTRL_INTENCLR_B33SRDY_Pos)
Kojto 111:4336505e4b1c 112 #define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
Kojto 111:4336505e4b1c 113 #define SYSCTRL_INTENCLR_DPLLLCKR (0x1ul << SYSCTRL_INTENCLR_DPLLLCKR_Pos)
Kojto 111:4336505e4b1c 114 #define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
Kojto 111:4336505e4b1c 115 #define SYSCTRL_INTENCLR_DPLLLCKF (0x1ul << SYSCTRL_INTENCLR_DPLLLCKF_Pos)
Kojto 111:4336505e4b1c 116 #define SYSCTRL_INTENCLR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */
Kojto 111:4336505e4b1c 117 #define SYSCTRL_INTENCLR_DPLLLTO (0x1ul << SYSCTRL_INTENCLR_DPLLLTO_Pos)
Kojto 111:4336505e4b1c 118 #define SYSCTRL_INTENCLR_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 119
Kojto 111:4336505e4b1c 120 /* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 121 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 122 typedef union {
Kojto 111:4336505e4b1c 123 struct {
Kojto 111:4336505e4b1c 124 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
Kojto 111:4336505e4b1c 125 uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
Kojto 111:4336505e4b1c 126 uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
Kojto 111:4336505e4b1c 127 uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
Kojto 111:4336505e4b1c 128 uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
Kojto 111:4336505e4b1c 129 uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
Kojto 111:4336505e4b1c 130 uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
Kojto 111:4336505e4b1c 131 uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
Kojto 111:4336505e4b1c 132 uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
Kojto 111:4336505e4b1c 133 uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
Kojto 111:4336505e4b1c 134 uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
Kojto 111:4336505e4b1c 135 uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 136 uint32_t :3; /*!< bit: 12..14 Reserved */
Kojto 111:4336505e4b1c 137 uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
Kojto 111:4336505e4b1c 138 uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
Kojto 111:4336505e4b1c 139 uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
Kojto 111:4336505e4b1c 140 uint32_t :14; /*!< bit: 18..31 Reserved */
Kojto 111:4336505e4b1c 141 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 142 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 143 } SYSCTRL_INTENSET_Type;
Kojto 111:4336505e4b1c 144 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 145
Kojto 111:4336505e4b1c 146 #define SYSCTRL_INTENSET_OFFSET 0x04 /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */
Kojto 111:4336505e4b1c 147 #define SYSCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */
Kojto 111:4336505e4b1c 148
Kojto 111:4336505e4b1c 149 #define SYSCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */
Kojto 111:4336505e4b1c 150 #define SYSCTRL_INTENSET_XOSCRDY (0x1ul << SYSCTRL_INTENSET_XOSCRDY_Pos)
Kojto 111:4336505e4b1c 151 #define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
Kojto 111:4336505e4b1c 152 #define SYSCTRL_INTENSET_XOSC32KRDY (0x1ul << SYSCTRL_INTENSET_XOSC32KRDY_Pos)
Kojto 111:4336505e4b1c 153 #define SYSCTRL_INTENSET_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */
Kojto 111:4336505e4b1c 154 #define SYSCTRL_INTENSET_OSC32KRDY (0x1ul << SYSCTRL_INTENSET_OSC32KRDY_Pos)
Kojto 111:4336505e4b1c 155 #define SYSCTRL_INTENSET_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */
Kojto 111:4336505e4b1c 156 #define SYSCTRL_INTENSET_OSC8MRDY (0x1ul << SYSCTRL_INTENSET_OSC8MRDY_Pos)
Kojto 111:4336505e4b1c 157 #define SYSCTRL_INTENSET_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */
Kojto 111:4336505e4b1c 158 #define SYSCTRL_INTENSET_DFLLRDY (0x1ul << SYSCTRL_INTENSET_DFLLRDY_Pos)
Kojto 111:4336505e4b1c 159 #define SYSCTRL_INTENSET_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
Kojto 111:4336505e4b1c 160 #define SYSCTRL_INTENSET_DFLLOOB (0x1ul << SYSCTRL_INTENSET_DFLLOOB_Pos)
Kojto 111:4336505e4b1c 161 #define SYSCTRL_INTENSET_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
Kojto 111:4336505e4b1c 162 #define SYSCTRL_INTENSET_DFLLLCKF (0x1ul << SYSCTRL_INTENSET_DFLLLCKF_Pos)
Kojto 111:4336505e4b1c 163 #define SYSCTRL_INTENSET_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
Kojto 111:4336505e4b1c 164 #define SYSCTRL_INTENSET_DFLLLCKC (0x1ul << SYSCTRL_INTENSET_DFLLLCKC_Pos)
Kojto 111:4336505e4b1c 165 #define SYSCTRL_INTENSET_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
Kojto 111:4336505e4b1c 166 #define SYSCTRL_INTENSET_DFLLRCS (0x1ul << SYSCTRL_INTENSET_DFLLRCS_Pos)
Kojto 111:4336505e4b1c 167 #define SYSCTRL_INTENSET_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */
Kojto 111:4336505e4b1c 168 #define SYSCTRL_INTENSET_BOD33RDY (0x1ul << SYSCTRL_INTENSET_BOD33RDY_Pos)
Kojto 111:4336505e4b1c 169 #define SYSCTRL_INTENSET_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */
Kojto 111:4336505e4b1c 170 #define SYSCTRL_INTENSET_BOD33DET (0x1ul << SYSCTRL_INTENSET_BOD33DET_Pos)
Kojto 111:4336505e4b1c 171 #define SYSCTRL_INTENSET_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 172 #define SYSCTRL_INTENSET_B33SRDY (0x1ul << SYSCTRL_INTENSET_B33SRDY_Pos)
Kojto 111:4336505e4b1c 173 #define SYSCTRL_INTENSET_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
Kojto 111:4336505e4b1c 174 #define SYSCTRL_INTENSET_DPLLLCKR (0x1ul << SYSCTRL_INTENSET_DPLLLCKR_Pos)
Kojto 111:4336505e4b1c 175 #define SYSCTRL_INTENSET_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
Kojto 111:4336505e4b1c 176 #define SYSCTRL_INTENSET_DPLLLCKF (0x1ul << SYSCTRL_INTENSET_DPLLLCKF_Pos)
Kojto 111:4336505e4b1c 177 #define SYSCTRL_INTENSET_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */
Kojto 111:4336505e4b1c 178 #define SYSCTRL_INTENSET_DPLLLTO (0x1ul << SYSCTRL_INTENSET_DPLLLTO_Pos)
Kojto 111:4336505e4b1c 179 #define SYSCTRL_INTENSET_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 180
Kojto 111:4336505e4b1c 181 /* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 182 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 183 typedef union {
Kojto 111:4336505e4b1c 184 struct {
Kojto 111:4336505e4b1c 185 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
Kojto 111:4336505e4b1c 186 uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
Kojto 111:4336505e4b1c 187 uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
Kojto 111:4336505e4b1c 188 uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
Kojto 111:4336505e4b1c 189 uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
Kojto 111:4336505e4b1c 190 uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
Kojto 111:4336505e4b1c 191 uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
Kojto 111:4336505e4b1c 192 uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
Kojto 111:4336505e4b1c 193 uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
Kojto 111:4336505e4b1c 194 uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
Kojto 111:4336505e4b1c 195 uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
Kojto 111:4336505e4b1c 196 uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
Kojto 111:4336505e4b1c 197 uint32_t :3; /*!< bit: 12..14 Reserved */
Kojto 111:4336505e4b1c 198 uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
Kojto 111:4336505e4b1c 199 uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
Kojto 111:4336505e4b1c 200 uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
Kojto 111:4336505e4b1c 201 uint32_t :14; /*!< bit: 18..31 Reserved */
Kojto 111:4336505e4b1c 202 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 203 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 204 } SYSCTRL_INTFLAG_Type;
Kojto 111:4336505e4b1c 205 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 206
Kojto 111:4336505e4b1c 207 #define SYSCTRL_INTFLAG_OFFSET 0x08 /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 208 #define SYSCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 209
Kojto 111:4336505e4b1c 210 #define SYSCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */
Kojto 111:4336505e4b1c 211 #define SYSCTRL_INTFLAG_XOSCRDY (0x1ul << SYSCTRL_INTFLAG_XOSCRDY_Pos)
Kojto 111:4336505e4b1c 212 #define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */
Kojto 111:4336505e4b1c 213 #define SYSCTRL_INTFLAG_XOSC32KRDY (0x1ul << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)
Kojto 111:4336505e4b1c 214 #define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */
Kojto 111:4336505e4b1c 215 #define SYSCTRL_INTFLAG_OSC32KRDY (0x1ul << SYSCTRL_INTFLAG_OSC32KRDY_Pos)
Kojto 111:4336505e4b1c 216 #define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */
Kojto 111:4336505e4b1c 217 #define SYSCTRL_INTFLAG_OSC8MRDY (0x1ul << SYSCTRL_INTFLAG_OSC8MRDY_Pos)
Kojto 111:4336505e4b1c 218 #define SYSCTRL_INTFLAG_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */
Kojto 111:4336505e4b1c 219 #define SYSCTRL_INTFLAG_DFLLRDY (0x1ul << SYSCTRL_INTFLAG_DFLLRDY_Pos)
Kojto 111:4336505e4b1c 220 #define SYSCTRL_INTFLAG_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */
Kojto 111:4336505e4b1c 221 #define SYSCTRL_INTFLAG_DFLLOOB (0x1ul << SYSCTRL_INTFLAG_DFLLOOB_Pos)
Kojto 111:4336505e4b1c 222 #define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */
Kojto 111:4336505e4b1c 223 #define SYSCTRL_INTFLAG_DFLLLCKF (0x1ul << SYSCTRL_INTFLAG_DFLLLCKF_Pos)
Kojto 111:4336505e4b1c 224 #define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */
Kojto 111:4336505e4b1c 225 #define SYSCTRL_INTFLAG_DFLLLCKC (0x1ul << SYSCTRL_INTFLAG_DFLLLCKC_Pos)
Kojto 111:4336505e4b1c 226 #define SYSCTRL_INTFLAG_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */
Kojto 111:4336505e4b1c 227 #define SYSCTRL_INTFLAG_DFLLRCS (0x1ul << SYSCTRL_INTFLAG_DFLLRCS_Pos)
Kojto 111:4336505e4b1c 228 #define SYSCTRL_INTFLAG_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */
Kojto 111:4336505e4b1c 229 #define SYSCTRL_INTFLAG_BOD33RDY (0x1ul << SYSCTRL_INTFLAG_BOD33RDY_Pos)
Kojto 111:4336505e4b1c 230 #define SYSCTRL_INTFLAG_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */
Kojto 111:4336505e4b1c 231 #define SYSCTRL_INTFLAG_BOD33DET (0x1ul << SYSCTRL_INTFLAG_BOD33DET_Pos)
Kojto 111:4336505e4b1c 232 #define SYSCTRL_INTFLAG_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */
Kojto 111:4336505e4b1c 233 #define SYSCTRL_INTFLAG_B33SRDY (0x1ul << SYSCTRL_INTFLAG_B33SRDY_Pos)
Kojto 111:4336505e4b1c 234 #define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */
Kojto 111:4336505e4b1c 235 #define SYSCTRL_INTFLAG_DPLLLCKR (0x1ul << SYSCTRL_INTFLAG_DPLLLCKR_Pos)
Kojto 111:4336505e4b1c 236 #define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */
Kojto 111:4336505e4b1c 237 #define SYSCTRL_INTFLAG_DPLLLCKF (0x1ul << SYSCTRL_INTFLAG_DPLLLCKF_Pos)
Kojto 111:4336505e4b1c 238 #define SYSCTRL_INTFLAG_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */
Kojto 111:4336505e4b1c 239 #define SYSCTRL_INTFLAG_DPLLLTO (0x1ul << SYSCTRL_INTFLAG_DPLLLTO_Pos)
Kojto 111:4336505e4b1c 240 #define SYSCTRL_INTFLAG_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 241
Kojto 111:4336505e4b1c 242 /* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
Kojto 111:4336505e4b1c 243 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 244 typedef union {
Kojto 111:4336505e4b1c 245 struct {
Kojto 111:4336505e4b1c 246 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
Kojto 111:4336505e4b1c 247 uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
Kojto 111:4336505e4b1c 248 uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
Kojto 111:4336505e4b1c 249 uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
Kojto 111:4336505e4b1c 250 uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
Kojto 111:4336505e4b1c 251 uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
Kojto 111:4336505e4b1c 252 uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
Kojto 111:4336505e4b1c 253 uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
Kojto 111:4336505e4b1c 254 uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
Kojto 111:4336505e4b1c 255 uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
Kojto 111:4336505e4b1c 256 uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
Kojto 111:4336505e4b1c 257 uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
Kojto 111:4336505e4b1c 258 uint32_t :3; /*!< bit: 12..14 Reserved */
Kojto 111:4336505e4b1c 259 uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
Kojto 111:4336505e4b1c 260 uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
Kojto 111:4336505e4b1c 261 uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
Kojto 111:4336505e4b1c 262 uint32_t :14; /*!< bit: 18..31 Reserved */
Kojto 111:4336505e4b1c 263 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 264 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 265 } SYSCTRL_PCLKSR_Type;
Kojto 111:4336505e4b1c 266 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 267
Kojto 111:4336505e4b1c 268 #define SYSCTRL_PCLKSR_OFFSET 0x0C /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */
Kojto 111:4336505e4b1c 269 #define SYSCTRL_PCLKSR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */
Kojto 111:4336505e4b1c 270
Kojto 111:4336505e4b1c 271 #define SYSCTRL_PCLKSR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */
Kojto 111:4336505e4b1c 272 #define SYSCTRL_PCLKSR_XOSCRDY (0x1ul << SYSCTRL_PCLKSR_XOSCRDY_Pos)
Kojto 111:4336505e4b1c 273 #define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */
Kojto 111:4336505e4b1c 274 #define SYSCTRL_PCLKSR_XOSC32KRDY (0x1ul << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)
Kojto 111:4336505e4b1c 275 #define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */
Kojto 111:4336505e4b1c 276 #define SYSCTRL_PCLKSR_OSC32KRDY (0x1ul << SYSCTRL_PCLKSR_OSC32KRDY_Pos)
Kojto 111:4336505e4b1c 277 #define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */
Kojto 111:4336505e4b1c 278 #define SYSCTRL_PCLKSR_OSC8MRDY (0x1ul << SYSCTRL_PCLKSR_OSC8MRDY_Pos)
Kojto 111:4336505e4b1c 279 #define SYSCTRL_PCLKSR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */
Kojto 111:4336505e4b1c 280 #define SYSCTRL_PCLKSR_DFLLRDY (0x1ul << SYSCTRL_PCLKSR_DFLLRDY_Pos)
Kojto 111:4336505e4b1c 281 #define SYSCTRL_PCLKSR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */
Kojto 111:4336505e4b1c 282 #define SYSCTRL_PCLKSR_DFLLOOB (0x1ul << SYSCTRL_PCLKSR_DFLLOOB_Pos)
Kojto 111:4336505e4b1c 283 #define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */
Kojto 111:4336505e4b1c 284 #define SYSCTRL_PCLKSR_DFLLLCKF (0x1ul << SYSCTRL_PCLKSR_DFLLLCKF_Pos)
Kojto 111:4336505e4b1c 285 #define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */
Kojto 111:4336505e4b1c 286 #define SYSCTRL_PCLKSR_DFLLLCKC (0x1ul << SYSCTRL_PCLKSR_DFLLLCKC_Pos)
Kojto 111:4336505e4b1c 287 #define SYSCTRL_PCLKSR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */
Kojto 111:4336505e4b1c 288 #define SYSCTRL_PCLKSR_DFLLRCS (0x1ul << SYSCTRL_PCLKSR_DFLLRCS_Pos)
Kojto 111:4336505e4b1c 289 #define SYSCTRL_PCLKSR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */
Kojto 111:4336505e4b1c 290 #define SYSCTRL_PCLKSR_BOD33RDY (0x1ul << SYSCTRL_PCLKSR_BOD33RDY_Pos)
Kojto 111:4336505e4b1c 291 #define SYSCTRL_PCLKSR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */
Kojto 111:4336505e4b1c 292 #define SYSCTRL_PCLKSR_BOD33DET (0x1ul << SYSCTRL_PCLKSR_BOD33DET_Pos)
Kojto 111:4336505e4b1c 293 #define SYSCTRL_PCLKSR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */
Kojto 111:4336505e4b1c 294 #define SYSCTRL_PCLKSR_B33SRDY (0x1ul << SYSCTRL_PCLKSR_B33SRDY_Pos)
Kojto 111:4336505e4b1c 295 #define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */
Kojto 111:4336505e4b1c 296 #define SYSCTRL_PCLKSR_DPLLLCKR (0x1ul << SYSCTRL_PCLKSR_DPLLLCKR_Pos)
Kojto 111:4336505e4b1c 297 #define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */
Kojto 111:4336505e4b1c 298 #define SYSCTRL_PCLKSR_DPLLLCKF (0x1ul << SYSCTRL_PCLKSR_DPLLLCKF_Pos)
Kojto 111:4336505e4b1c 299 #define SYSCTRL_PCLKSR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */
Kojto 111:4336505e4b1c 300 #define SYSCTRL_PCLKSR_DPLLLTO (0x1ul << SYSCTRL_PCLKSR_DPLLLTO_Pos)
Kojto 111:4336505e4b1c 301 #define SYSCTRL_PCLKSR_MASK 0x00038FFFul /**< \brief (SYSCTRL_PCLKSR) MASK Register */
Kojto 111:4336505e4b1c 302
Kojto 111:4336505e4b1c 303 /* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
Kojto 111:4336505e4b1c 304 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 305 typedef union {
Kojto 111:4336505e4b1c 306 struct {
Kojto 111:4336505e4b1c 307 uint16_t :1; /*!< bit: 0 Reserved */
Kojto 111:4336505e4b1c 308 uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
Kojto 111:4336505e4b1c 309 uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
Kojto 111:4336505e4b1c 310 uint16_t :3; /*!< bit: 3.. 5 Reserved */
Kojto 111:4336505e4b1c 311 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
Kojto 111:4336505e4b1c 312 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
Kojto 111:4336505e4b1c 313 uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
Kojto 111:4336505e4b1c 314 uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
Kojto 111:4336505e4b1c 315 uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
Kojto 111:4336505e4b1c 316 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 317 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 318 } SYSCTRL_XOSC_Type;
Kojto 111:4336505e4b1c 319 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 320
Kojto 111:4336505e4b1c 321 #define SYSCTRL_XOSC_OFFSET 0x10 /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */
Kojto 111:4336505e4b1c 322 #define SYSCTRL_XOSC_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
Kojto 111:4336505e4b1c 323
Kojto 111:4336505e4b1c 324 #define SYSCTRL_XOSC_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC) Oscillator Enable */
Kojto 111:4336505e4b1c 325 #define SYSCTRL_XOSC_ENABLE (0x1ul << SYSCTRL_XOSC_ENABLE_Pos)
Kojto 111:4336505e4b1c 326 #define SYSCTRL_XOSC_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */
Kojto 111:4336505e4b1c 327 #define SYSCTRL_XOSC_XTALEN (0x1ul << SYSCTRL_XOSC_XTALEN_Pos)
Kojto 111:4336505e4b1c 328 #define SYSCTRL_XOSC_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC) Run in Standby */
Kojto 111:4336505e4b1c 329 #define SYSCTRL_XOSC_RUNSTDBY (0x1ul << SYSCTRL_XOSC_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 330 #define SYSCTRL_XOSC_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC) On Demand Control */
Kojto 111:4336505e4b1c 331 #define SYSCTRL_XOSC_ONDEMAND (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos)
Kojto 111:4336505e4b1c 332 #define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
Kojto 111:4336505e4b1c 333 #define SYSCTRL_XOSC_GAIN_Msk (0x7ul << SYSCTRL_XOSC_GAIN_Pos)
Kojto 111:4336505e4b1c 334 #define SYSCTRL_XOSC_GAIN(value) ((SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)))
Kojto 111:4336505e4b1c 335 #define SYSCTRL_XOSC_GAIN_0_Val 0x0ul /**< \brief (SYSCTRL_XOSC) 2MHz */
Kojto 111:4336505e4b1c 336 #define SYSCTRL_XOSC_GAIN_1_Val 0x1ul /**< \brief (SYSCTRL_XOSC) 4MHz */
Kojto 111:4336505e4b1c 337 #define SYSCTRL_XOSC_GAIN_2_Val 0x2ul /**< \brief (SYSCTRL_XOSC) 8MHz */
Kojto 111:4336505e4b1c 338 #define SYSCTRL_XOSC_GAIN_3_Val 0x3ul /**< \brief (SYSCTRL_XOSC) 16MHz */
Kojto 111:4336505e4b1c 339 #define SYSCTRL_XOSC_GAIN_4_Val 0x4ul /**< \brief (SYSCTRL_XOSC) 30MHz */
Kojto 111:4336505e4b1c 340 #define SYSCTRL_XOSC_GAIN_0 (SYSCTRL_XOSC_GAIN_0_Val << SYSCTRL_XOSC_GAIN_Pos)
Kojto 111:4336505e4b1c 341 #define SYSCTRL_XOSC_GAIN_1 (SYSCTRL_XOSC_GAIN_1_Val << SYSCTRL_XOSC_GAIN_Pos)
Kojto 111:4336505e4b1c 342 #define SYSCTRL_XOSC_GAIN_2 (SYSCTRL_XOSC_GAIN_2_Val << SYSCTRL_XOSC_GAIN_Pos)
Kojto 111:4336505e4b1c 343 #define SYSCTRL_XOSC_GAIN_3 (SYSCTRL_XOSC_GAIN_3_Val << SYSCTRL_XOSC_GAIN_Pos)
Kojto 111:4336505e4b1c 344 #define SYSCTRL_XOSC_GAIN_4 (SYSCTRL_XOSC_GAIN_4_Val << SYSCTRL_XOSC_GAIN_Pos)
Kojto 111:4336505e4b1c 345 #define SYSCTRL_XOSC_AMPGC_Pos 11 /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */
Kojto 111:4336505e4b1c 346 #define SYSCTRL_XOSC_AMPGC (0x1ul << SYSCTRL_XOSC_AMPGC_Pos)
Kojto 111:4336505e4b1c 347 #define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */
Kojto 111:4336505e4b1c 348 #define SYSCTRL_XOSC_STARTUP_Msk (0xFul << SYSCTRL_XOSC_STARTUP_Pos)
Kojto 111:4336505e4b1c 349 #define SYSCTRL_XOSC_STARTUP(value) ((SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)))
Kojto 111:4336505e4b1c 350 #define SYSCTRL_XOSC_MASK 0xFFC6ul /**< \brief (SYSCTRL_XOSC) MASK Register */
Kojto 111:4336505e4b1c 351
Kojto 111:4336505e4b1c 352 /* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
Kojto 111:4336505e4b1c 353 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 354 typedef union {
Kojto 111:4336505e4b1c 355 struct {
Kojto 111:4336505e4b1c 356 uint16_t :1; /*!< bit: 0 Reserved */
Kojto 111:4336505e4b1c 357 uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
Kojto 111:4336505e4b1c 358 uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
Kojto 111:4336505e4b1c 359 uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
Kojto 111:4336505e4b1c 360 uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
Kojto 111:4336505e4b1c 361 uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
Kojto 111:4336505e4b1c 362 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
Kojto 111:4336505e4b1c 363 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
Kojto 111:4336505e4b1c 364 uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
Kojto 111:4336505e4b1c 365 uint16_t :1; /*!< bit: 11 Reserved */
Kojto 111:4336505e4b1c 366 uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
Kojto 111:4336505e4b1c 367 uint16_t :3; /*!< bit: 13..15 Reserved */
Kojto 111:4336505e4b1c 368 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 369 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 370 } SYSCTRL_XOSC32K_Type;
Kojto 111:4336505e4b1c 371 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 372
Kojto 111:4336505e4b1c 373 #define SYSCTRL_XOSC32K_OFFSET 0x14 /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
Kojto 111:4336505e4b1c 374 #define SYSCTRL_XOSC32K_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
Kojto 111:4336505e4b1c 375
Kojto 111:4336505e4b1c 376 #define SYSCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */
Kojto 111:4336505e4b1c 377 #define SYSCTRL_XOSC32K_ENABLE (0x1ul << SYSCTRL_XOSC32K_ENABLE_Pos)
Kojto 111:4336505e4b1c 378 #define SYSCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */
Kojto 111:4336505e4b1c 379 #define SYSCTRL_XOSC32K_XTALEN (0x1ul << SYSCTRL_XOSC32K_XTALEN_Pos)
Kojto 111:4336505e4b1c 380 #define SYSCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */
Kojto 111:4336505e4b1c 381 #define SYSCTRL_XOSC32K_EN32K (0x1ul << SYSCTRL_XOSC32K_EN32K_Pos)
Kojto 111:4336505e4b1c 382 #define SYSCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */
Kojto 111:4336505e4b1c 383 #define SYSCTRL_XOSC32K_EN1K (0x1ul << SYSCTRL_XOSC32K_EN1K_Pos)
Kojto 111:4336505e4b1c 384 #define SYSCTRL_XOSC32K_AAMPEN_Pos 5 /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */
Kojto 111:4336505e4b1c 385 #define SYSCTRL_XOSC32K_AAMPEN (0x1ul << SYSCTRL_XOSC32K_AAMPEN_Pos)
Kojto 111:4336505e4b1c 386 #define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC32K) Run in Standby */
Kojto 111:4336505e4b1c 387 #define SYSCTRL_XOSC32K_RUNSTDBY (0x1ul << SYSCTRL_XOSC32K_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 388 #define SYSCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC32K) On Demand Control */
Kojto 111:4336505e4b1c 389 #define SYSCTRL_XOSC32K_ONDEMAND (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos)
Kojto 111:4336505e4b1c 390 #define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
Kojto 111:4336505e4b1c 391 #define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos)
Kojto 111:4336505e4b1c 392 #define SYSCTRL_XOSC32K_STARTUP(value) ((SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)))
Kojto 111:4336505e4b1c 393 #define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */
Kojto 111:4336505e4b1c 394 #define SYSCTRL_XOSC32K_WRTLOCK (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos)
Kojto 111:4336505e4b1c 395 #define SYSCTRL_XOSC32K_MASK 0x17FEul /**< \brief (SYSCTRL_XOSC32K) MASK Register */
Kojto 111:4336505e4b1c 396
Kojto 111:4336505e4b1c 397 /* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
Kojto 111:4336505e4b1c 398 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 399 typedef union {
Kojto 111:4336505e4b1c 400 struct {
Kojto 111:4336505e4b1c 401 uint32_t :1; /*!< bit: 0 Reserved */
Kojto 111:4336505e4b1c 402 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
Kojto 111:4336505e4b1c 403 uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
Kojto 111:4336505e4b1c 404 uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
Kojto 111:4336505e4b1c 405 uint32_t :2; /*!< bit: 4.. 5 Reserved */
Kojto 111:4336505e4b1c 406 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
Kojto 111:4336505e4b1c 407 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
Kojto 111:4336505e4b1c 408 uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
Kojto 111:4336505e4b1c 409 uint32_t :1; /*!< bit: 11 Reserved */
Kojto 111:4336505e4b1c 410 uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
Kojto 111:4336505e4b1c 411 uint32_t :3; /*!< bit: 13..15 Reserved */
Kojto 111:4336505e4b1c 412 uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
Kojto 111:4336505e4b1c 413 uint32_t :9; /*!< bit: 23..31 Reserved */
Kojto 111:4336505e4b1c 414 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 415 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 416 } SYSCTRL_OSC32K_Type;
Kojto 111:4336505e4b1c 417 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 418
Kojto 111:4336505e4b1c 419 #define SYSCTRL_OSC32K_OFFSET 0x18 /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
Kojto 111:4336505e4b1c 420 #define SYSCTRL_OSC32K_RESETVALUE 0x003F0080ul /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
Kojto 111:4336505e4b1c 421
Kojto 111:4336505e4b1c 422 #define SYSCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */
Kojto 111:4336505e4b1c 423 #define SYSCTRL_OSC32K_ENABLE (0x1ul << SYSCTRL_OSC32K_ENABLE_Pos)
Kojto 111:4336505e4b1c 424 #define SYSCTRL_OSC32K_EN32K_Pos 2 /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */
Kojto 111:4336505e4b1c 425 #define SYSCTRL_OSC32K_EN32K (0x1ul << SYSCTRL_OSC32K_EN32K_Pos)
Kojto 111:4336505e4b1c 426 #define SYSCTRL_OSC32K_EN1K_Pos 3 /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */
Kojto 111:4336505e4b1c 427 #define SYSCTRL_OSC32K_EN1K (0x1ul << SYSCTRL_OSC32K_EN1K_Pos)
Kojto 111:4336505e4b1c 428 #define SYSCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC32K) Run in Standby */
Kojto 111:4336505e4b1c 429 #define SYSCTRL_OSC32K_RUNSTDBY (0x1ul << SYSCTRL_OSC32K_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 430 #define SYSCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC32K) On Demand Control */
Kojto 111:4336505e4b1c 431 #define SYSCTRL_OSC32K_ONDEMAND (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos)
Kojto 111:4336505e4b1c 432 #define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
Kojto 111:4336505e4b1c 433 #define SYSCTRL_OSC32K_STARTUP_Msk (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos)
Kojto 111:4336505e4b1c 434 #define SYSCTRL_OSC32K_STARTUP(value) ((SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)))
Kojto 111:4336505e4b1c 435 #define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */
Kojto 111:4336505e4b1c 436 #define SYSCTRL_OSC32K_WRTLOCK (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos)
Kojto 111:4336505e4b1c 437 #define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
Kojto 111:4336505e4b1c 438 #define SYSCTRL_OSC32K_CALIB_Msk (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos)
Kojto 111:4336505e4b1c 439 #define SYSCTRL_OSC32K_CALIB(value) ((SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)))
Kojto 111:4336505e4b1c 440 #define SYSCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */
Kojto 111:4336505e4b1c 441
Kojto 111:4336505e4b1c 442 /* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
Kojto 111:4336505e4b1c 443 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 444 typedef union {
Kojto 111:4336505e4b1c 445 struct {
Kojto 111:4336505e4b1c 446 uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
Kojto 111:4336505e4b1c 447 uint8_t :2; /*!< bit: 5.. 6 Reserved */
Kojto 111:4336505e4b1c 448 uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
Kojto 111:4336505e4b1c 449 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 450 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 451 } SYSCTRL_OSCULP32K_Type;
Kojto 111:4336505e4b1c 452 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 453
Kojto 111:4336505e4b1c 454 #define SYSCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
Kojto 111:4336505e4b1c 455 #define SYSCTRL_OSCULP32K_RESETVALUE 0x1Ful /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
Kojto 111:4336505e4b1c 456
Kojto 111:4336505e4b1c 457 #define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
Kojto 111:4336505e4b1c 458 #define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos)
Kojto 111:4336505e4b1c 459 #define SYSCTRL_OSCULP32K_CALIB(value) ((SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)))
Kojto 111:4336505e4b1c 460 #define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
Kojto 111:4336505e4b1c 461 #define SYSCTRL_OSCULP32K_WRTLOCK (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
Kojto 111:4336505e4b1c 462 #define SYSCTRL_OSCULP32K_MASK 0x9Ful /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
Kojto 111:4336505e4b1c 463
Kojto 111:4336505e4b1c 464 /* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
Kojto 111:4336505e4b1c 465 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 466 typedef union {
Kojto 111:4336505e4b1c 467 struct {
Kojto 111:4336505e4b1c 468 uint32_t :1; /*!< bit: 0 Reserved */
Kojto 111:4336505e4b1c 469 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
Kojto 111:4336505e4b1c 470 uint32_t :4; /*!< bit: 2.. 5 Reserved */
Kojto 111:4336505e4b1c 471 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
Kojto 111:4336505e4b1c 472 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
Kojto 111:4336505e4b1c 473 uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
Kojto 111:4336505e4b1c 474 uint32_t :6; /*!< bit: 10..15 Reserved */
Kojto 111:4336505e4b1c 475 uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
Kojto 111:4336505e4b1c 476 uint32_t :2; /*!< bit: 28..29 Reserved */
Kojto 111:4336505e4b1c 477 uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
Kojto 111:4336505e4b1c 478 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 479 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 480 } SYSCTRL_OSC8M_Type;
Kojto 111:4336505e4b1c 481 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 482
Kojto 111:4336505e4b1c 483 #define SYSCTRL_OSC8M_OFFSET 0x20 /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */
Kojto 111:4336505e4b1c 484 #define SYSCTRL_OSC8M_RESETVALUE 0x87070382ul /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */
Kojto 111:4336505e4b1c 485
Kojto 111:4336505e4b1c 486 #define SYSCTRL_OSC8M_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */
Kojto 111:4336505e4b1c 487 #define SYSCTRL_OSC8M_ENABLE (0x1ul << SYSCTRL_OSC8M_ENABLE_Pos)
Kojto 111:4336505e4b1c 488 #define SYSCTRL_OSC8M_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC8M) Run in Standby */
Kojto 111:4336505e4b1c 489 #define SYSCTRL_OSC8M_RUNSTDBY (0x1ul << SYSCTRL_OSC8M_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 490 #define SYSCTRL_OSC8M_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC8M) On Demand Control */
Kojto 111:4336505e4b1c 491 #define SYSCTRL_OSC8M_ONDEMAND (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos)
Kojto 111:4336505e4b1c 492 #define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
Kojto 111:4336505e4b1c 493 #define SYSCTRL_OSC8M_PRESC_Msk (0x3ul << SYSCTRL_OSC8M_PRESC_Pos)
Kojto 111:4336505e4b1c 494 #define SYSCTRL_OSC8M_PRESC(value) ((SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)))
Kojto 111:4336505e4b1c 495 #define SYSCTRL_OSC8M_PRESC_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 1 */
Kojto 111:4336505e4b1c 496 #define SYSCTRL_OSC8M_PRESC_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 2 */
Kojto 111:4336505e4b1c 497 #define SYSCTRL_OSC8M_PRESC_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 4 */
Kojto 111:4336505e4b1c 498 #define SYSCTRL_OSC8M_PRESC_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 8 */
Kojto 111:4336505e4b1c 499 #define SYSCTRL_OSC8M_PRESC_0 (SYSCTRL_OSC8M_PRESC_0_Val << SYSCTRL_OSC8M_PRESC_Pos)
Kojto 111:4336505e4b1c 500 #define SYSCTRL_OSC8M_PRESC_1 (SYSCTRL_OSC8M_PRESC_1_Val << SYSCTRL_OSC8M_PRESC_Pos)
Kojto 111:4336505e4b1c 501 #define SYSCTRL_OSC8M_PRESC_2 (SYSCTRL_OSC8M_PRESC_2_Val << SYSCTRL_OSC8M_PRESC_Pos)
Kojto 111:4336505e4b1c 502 #define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos)
Kojto 111:4336505e4b1c 503 #define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
Kojto 111:4336505e4b1c 504 #define SYSCTRL_OSC8M_CALIB_Msk (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos)
Kojto 111:4336505e4b1c 505 #define SYSCTRL_OSC8M_CALIB(value) ((SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)))
Kojto 111:4336505e4b1c 506 #define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
Kojto 111:4336505e4b1c 507 #define SYSCTRL_OSC8M_FRANGE_Msk (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos)
Kojto 111:4336505e4b1c 508 #define SYSCTRL_OSC8M_FRANGE(value) ((SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)))
Kojto 111:4336505e4b1c 509 #define SYSCTRL_OSC8M_FRANGE_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
Kojto 111:4336505e4b1c 510 #define SYSCTRL_OSC8M_FRANGE_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
Kojto 111:4336505e4b1c 511 #define SYSCTRL_OSC8M_FRANGE_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
Kojto 111:4336505e4b1c 512 #define SYSCTRL_OSC8M_FRANGE_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */
Kojto 111:4336505e4b1c 513 #define SYSCTRL_OSC8M_FRANGE_0 (SYSCTRL_OSC8M_FRANGE_0_Val << SYSCTRL_OSC8M_FRANGE_Pos)
Kojto 111:4336505e4b1c 514 #define SYSCTRL_OSC8M_FRANGE_1 (SYSCTRL_OSC8M_FRANGE_1_Val << SYSCTRL_OSC8M_FRANGE_Pos)
Kojto 111:4336505e4b1c 515 #define SYSCTRL_OSC8M_FRANGE_2 (SYSCTRL_OSC8M_FRANGE_2_Val << SYSCTRL_OSC8M_FRANGE_Pos)
Kojto 111:4336505e4b1c 516 #define SYSCTRL_OSC8M_FRANGE_3 (SYSCTRL_OSC8M_FRANGE_3_Val << SYSCTRL_OSC8M_FRANGE_Pos)
Kojto 111:4336505e4b1c 517 #define SYSCTRL_OSC8M_MASK 0xCFFF03C2ul /**< \brief (SYSCTRL_OSC8M) MASK Register */
Kojto 111:4336505e4b1c 518
Kojto 111:4336505e4b1c 519 /* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
Kojto 111:4336505e4b1c 520 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 521 typedef union {
Kojto 111:4336505e4b1c 522 struct {
Kojto 111:4336505e4b1c 523 uint16_t :1; /*!< bit: 0 Reserved */
Kojto 111:4336505e4b1c 524 uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
Kojto 111:4336505e4b1c 525 uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
Kojto 111:4336505e4b1c 526 uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
Kojto 111:4336505e4b1c 527 uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
Kojto 111:4336505e4b1c 528 uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
Kojto 111:4336505e4b1c 529 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
Kojto 111:4336505e4b1c 530 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
Kojto 111:4336505e4b1c 531 uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
Kojto 111:4336505e4b1c 532 uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
Kojto 111:4336505e4b1c 533 uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
Kojto 111:4336505e4b1c 534 uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
Kojto 111:4336505e4b1c 535 uint16_t :4; /*!< bit: 12..15 Reserved */
Kojto 111:4336505e4b1c 536 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 537 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 538 } SYSCTRL_DFLLCTRL_Type;
Kojto 111:4336505e4b1c 539 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 540
Kojto 111:4336505e4b1c 541 #define SYSCTRL_DFLLCTRL_OFFSET 0x24 /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */
Kojto 111:4336505e4b1c 542 #define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */
Kojto 111:4336505e4b1c 543
Kojto 111:4336505e4b1c 544 #define SYSCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */
Kojto 111:4336505e4b1c 545 #define SYSCTRL_DFLLCTRL_ENABLE (0x1ul << SYSCTRL_DFLLCTRL_ENABLE_Pos)
Kojto 111:4336505e4b1c 546 #define SYSCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */
Kojto 111:4336505e4b1c 547 #define SYSCTRL_DFLLCTRL_MODE (0x1ul << SYSCTRL_DFLLCTRL_MODE_Pos)
Kojto 111:4336505e4b1c 548 #define SYSCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */
Kojto 111:4336505e4b1c 549 #define SYSCTRL_DFLLCTRL_STABLE (0x1ul << SYSCTRL_DFLLCTRL_STABLE_Pos)
Kojto 111:4336505e4b1c 550 #define SYSCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */
Kojto 111:4336505e4b1c 551 #define SYSCTRL_DFLLCTRL_LLAW (0x1ul << SYSCTRL_DFLLCTRL_LLAW_Pos)
Kojto 111:4336505e4b1c 552 #define SYSCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */
Kojto 111:4336505e4b1c 553 #define SYSCTRL_DFLLCTRL_USBCRM (0x1ul << SYSCTRL_DFLLCTRL_USBCRM_Pos)
Kojto 111:4336505e4b1c 554 #define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */
Kojto 111:4336505e4b1c 555 #define SYSCTRL_DFLLCTRL_RUNSTDBY (0x1ul << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 556 #define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */
Kojto 111:4336505e4b1c 557 #define SYSCTRL_DFLLCTRL_ONDEMAND (0x1ul << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)
Kojto 111:4336505e4b1c 558 #define SYSCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */
Kojto 111:4336505e4b1c 559 #define SYSCTRL_DFLLCTRL_CCDIS (0x1ul << SYSCTRL_DFLLCTRL_CCDIS_Pos)
Kojto 111:4336505e4b1c 560 #define SYSCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */
Kojto 111:4336505e4b1c 561 #define SYSCTRL_DFLLCTRL_QLDIS (0x1ul << SYSCTRL_DFLLCTRL_QLDIS_Pos)
Kojto 111:4336505e4b1c 562 #define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */
Kojto 111:4336505e4b1c 563 #define SYSCTRL_DFLLCTRL_BPLCKC (0x1ul << SYSCTRL_DFLLCTRL_BPLCKC_Pos)
Kojto 111:4336505e4b1c 564 #define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */
Kojto 111:4336505e4b1c 565 #define SYSCTRL_DFLLCTRL_WAITLOCK (0x1ul << SYSCTRL_DFLLCTRL_WAITLOCK_Pos)
Kojto 111:4336505e4b1c 566 #define SYSCTRL_DFLLCTRL_MASK 0x0FFEul /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */
Kojto 111:4336505e4b1c 567
Kojto 111:4336505e4b1c 568 /* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
Kojto 111:4336505e4b1c 569 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 570 typedef union {
Kojto 111:4336505e4b1c 571 struct {
Kojto 111:4336505e4b1c 572 uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
Kojto 111:4336505e4b1c 573 uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
Kojto 111:4336505e4b1c 574 uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
Kojto 111:4336505e4b1c 575 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 576 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 577 } SYSCTRL_DFLLVAL_Type;
Kojto 111:4336505e4b1c 578 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 579
Kojto 111:4336505e4b1c 580 #define SYSCTRL_DFLLVAL_OFFSET 0x28 /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */
Kojto 111:4336505e4b1c 581 #define SYSCTRL_DFLLVAL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */
Kojto 111:4336505e4b1c 582
Kojto 111:4336505e4b1c 583 #define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
Kojto 111:4336505e4b1c 584 #define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos)
Kojto 111:4336505e4b1c 585 #define SYSCTRL_DFLLVAL_FINE(value) ((SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)))
Kojto 111:4336505e4b1c 586 #define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
Kojto 111:4336505e4b1c 587 #define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos)
Kojto 111:4336505e4b1c 588 #define SYSCTRL_DFLLVAL_COARSE(value) ((SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)))
Kojto 111:4336505e4b1c 589 #define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
Kojto 111:4336505e4b1c 590 #define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos)
Kojto 111:4336505e4b1c 591 #define SYSCTRL_DFLLVAL_DIFF(value) ((SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)))
Kojto 111:4336505e4b1c 592 #define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
Kojto 111:4336505e4b1c 593
Kojto 111:4336505e4b1c 594 /* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
Kojto 111:4336505e4b1c 595 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 596 typedef union {
Kojto 111:4336505e4b1c 597 struct {
Kojto 111:4336505e4b1c 598 uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
Kojto 111:4336505e4b1c 599 uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
Kojto 111:4336505e4b1c 600 uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
Kojto 111:4336505e4b1c 601 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 602 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 603 } SYSCTRL_DFLLMUL_Type;
Kojto 111:4336505e4b1c 604 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 605
Kojto 111:4336505e4b1c 606 #define SYSCTRL_DFLLMUL_OFFSET 0x2C /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */
Kojto 111:4336505e4b1c 607 #define SYSCTRL_DFLLMUL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
Kojto 111:4336505e4b1c 608
Kojto 111:4336505e4b1c 609 #define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
Kojto 111:4336505e4b1c 610 #define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos)
Kojto 111:4336505e4b1c 611 #define SYSCTRL_DFLLMUL_MUL(value) ((SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)))
Kojto 111:4336505e4b1c 612 #define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
Kojto 111:4336505e4b1c 613 #define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos)
Kojto 111:4336505e4b1c 614 #define SYSCTRL_DFLLMUL_FSTEP(value) ((SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)))
Kojto 111:4336505e4b1c 615 #define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
Kojto 111:4336505e4b1c 616 #define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos)
Kojto 111:4336505e4b1c 617 #define SYSCTRL_DFLLMUL_CSTEP(value) ((SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)))
Kojto 111:4336505e4b1c 618 #define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
Kojto 111:4336505e4b1c 619
Kojto 111:4336505e4b1c 620 /* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
Kojto 111:4336505e4b1c 621 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 622 typedef union {
Kojto 111:4336505e4b1c 623 struct {
Kojto 111:4336505e4b1c 624 uint8_t :7; /*!< bit: 0.. 6 Reserved */
Kojto 111:4336505e4b1c 625 uint8_t READREQ:1; /*!< bit: 7 Read Request */
Kojto 111:4336505e4b1c 626 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 627 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 628 } SYSCTRL_DFLLSYNC_Type;
Kojto 111:4336505e4b1c 629 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 630
Kojto 111:4336505e4b1c 631 #define SYSCTRL_DFLLSYNC_OFFSET 0x30 /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */
Kojto 111:4336505e4b1c 632 #define SYSCTRL_DFLLSYNC_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
Kojto 111:4336505e4b1c 633
Kojto 111:4336505e4b1c 634 #define SYSCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (SYSCTRL_DFLLSYNC) Read Request */
Kojto 111:4336505e4b1c 635 #define SYSCTRL_DFLLSYNC_READREQ (0x1ul << SYSCTRL_DFLLSYNC_READREQ_Pos)
Kojto 111:4336505e4b1c 636 #define SYSCTRL_DFLLSYNC_MASK 0x80ul /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */
Kojto 111:4336505e4b1c 637
Kojto 111:4336505e4b1c 638 /* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
Kojto 111:4336505e4b1c 639 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 640 typedef union {
Kojto 111:4336505e4b1c 641 struct {
Kojto 111:4336505e4b1c 642 uint32_t :1; /*!< bit: 0 Reserved */
Kojto 111:4336505e4b1c 643 uint32_t ENABLE:1; /*!< bit: 1 Enable */
Kojto 111:4336505e4b1c 644 uint32_t HYST:1; /*!< bit: 2 Hysteresis */
Kojto 111:4336505e4b1c 645 uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
Kojto 111:4336505e4b1c 646 uint32_t :1; /*!< bit: 5 Reserved */
Kojto 111:4336505e4b1c 647 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
Kojto 111:4336505e4b1c 648 uint32_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 649 uint32_t MODE:1; /*!< bit: 8 Operation Mode */
Kojto 111:4336505e4b1c 650 uint32_t CEN:1; /*!< bit: 9 Clock Enable */
Kojto 111:4336505e4b1c 651 uint32_t :2; /*!< bit: 10..11 Reserved */
Kojto 111:4336505e4b1c 652 uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
Kojto 111:4336505e4b1c 653 uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
Kojto 111:4336505e4b1c 654 uint32_t :10; /*!< bit: 22..31 Reserved */
Kojto 111:4336505e4b1c 655 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 656 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 657 } SYSCTRL_BOD33_Type;
Kojto 111:4336505e4b1c 658 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 659
Kojto 111:4336505e4b1c 660 #define SYSCTRL_BOD33_OFFSET 0x34 /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */
Kojto 111:4336505e4b1c 661 #define SYSCTRL_BOD33_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */
Kojto 111:4336505e4b1c 662
Kojto 111:4336505e4b1c 663 #define SYSCTRL_BOD33_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD33) Enable */
Kojto 111:4336505e4b1c 664 #define SYSCTRL_BOD33_ENABLE (0x1ul << SYSCTRL_BOD33_ENABLE_Pos)
Kojto 111:4336505e4b1c 665 #define SYSCTRL_BOD33_HYST_Pos 2 /**< \brief (SYSCTRL_BOD33) Hysteresis */
Kojto 111:4336505e4b1c 666 #define SYSCTRL_BOD33_HYST (0x1ul << SYSCTRL_BOD33_HYST_Pos)
Kojto 111:4336505e4b1c 667 #define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */
Kojto 111:4336505e4b1c 668 #define SYSCTRL_BOD33_ACTION_Msk (0x3ul << SYSCTRL_BOD33_ACTION_Pos)
Kojto 111:4336505e4b1c 669 #define SYSCTRL_BOD33_ACTION(value) ((SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)))
Kojto 111:4336505e4b1c 670 #define SYSCTRL_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SYSCTRL_BOD33) No action */
Kojto 111:4336505e4b1c 671 #define SYSCTRL_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
Kojto 111:4336505e4b1c 672 #define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
Kojto 111:4336505e4b1c 673 #define SYSCTRL_BOD33_ACTION_NONE (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos)
Kojto 111:4336505e4b1c 674 #define SYSCTRL_BOD33_ACTION_RESET (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos)
Kojto 111:4336505e4b1c 675 #define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos)
Kojto 111:4336505e4b1c 676 #define SYSCTRL_BOD33_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD33) Run in Standby */
Kojto 111:4336505e4b1c 677 #define SYSCTRL_BOD33_RUNSTDBY (0x1ul << SYSCTRL_BOD33_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 678 #define SYSCTRL_BOD33_MODE_Pos 8 /**< \brief (SYSCTRL_BOD33) Operation Mode */
Kojto 111:4336505e4b1c 679 #define SYSCTRL_BOD33_MODE (0x1ul << SYSCTRL_BOD33_MODE_Pos)
Kojto 111:4336505e4b1c 680 #define SYSCTRL_BOD33_CEN_Pos 9 /**< \brief (SYSCTRL_BOD33) Clock Enable */
Kojto 111:4336505e4b1c 681 #define SYSCTRL_BOD33_CEN (0x1ul << SYSCTRL_BOD33_CEN_Pos)
Kojto 111:4336505e4b1c 682 #define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */
Kojto 111:4336505e4b1c 683 #define SYSCTRL_BOD33_PSEL_Msk (0xFul << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 684 #define SYSCTRL_BOD33_PSEL(value) ((SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)))
Kojto 111:4336505e4b1c 685 #define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
Kojto 111:4336505e4b1c 686 #define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
Kojto 111:4336505e4b1c 687 #define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
Kojto 111:4336505e4b1c 688 #define SYSCTRL_BOD33_PSEL_DIV16_Val 0x3ul /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */
Kojto 111:4336505e4b1c 689 #define SYSCTRL_BOD33_PSEL_DIV32_Val 0x4ul /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */
Kojto 111:4336505e4b1c 690 #define SYSCTRL_BOD33_PSEL_DIV64_Val 0x5ul /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */
Kojto 111:4336505e4b1c 691 #define SYSCTRL_BOD33_PSEL_DIV128_Val 0x6ul /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */
Kojto 111:4336505e4b1c 692 #define SYSCTRL_BOD33_PSEL_DIV256_Val 0x7ul /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */
Kojto 111:4336505e4b1c 693 #define SYSCTRL_BOD33_PSEL_DIV512_Val 0x8ul /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */
Kojto 111:4336505e4b1c 694 #define SYSCTRL_BOD33_PSEL_DIV1K_Val 0x9ul /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */
Kojto 111:4336505e4b1c 695 #define SYSCTRL_BOD33_PSEL_DIV2K_Val 0xAul /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */
Kojto 111:4336505e4b1c 696 #define SYSCTRL_BOD33_PSEL_DIV4K_Val 0xBul /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */
Kojto 111:4336505e4b1c 697 #define SYSCTRL_BOD33_PSEL_DIV8K_Val 0xCul /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */
Kojto 111:4336505e4b1c 698 #define SYSCTRL_BOD33_PSEL_DIV16K_Val 0xDul /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */
Kojto 111:4336505e4b1c 699 #define SYSCTRL_BOD33_PSEL_DIV32K_Val 0xEul /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */
Kojto 111:4336505e4b1c 700 #define SYSCTRL_BOD33_PSEL_DIV64K_Val 0xFul /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */
Kojto 111:4336505e4b1c 701 #define SYSCTRL_BOD33_PSEL_DIV2 (SYSCTRL_BOD33_PSEL_DIV2_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 702 #define SYSCTRL_BOD33_PSEL_DIV4 (SYSCTRL_BOD33_PSEL_DIV4_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 703 #define SYSCTRL_BOD33_PSEL_DIV8 (SYSCTRL_BOD33_PSEL_DIV8_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 704 #define SYSCTRL_BOD33_PSEL_DIV16 (SYSCTRL_BOD33_PSEL_DIV16_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 705 #define SYSCTRL_BOD33_PSEL_DIV32 (SYSCTRL_BOD33_PSEL_DIV32_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 706 #define SYSCTRL_BOD33_PSEL_DIV64 (SYSCTRL_BOD33_PSEL_DIV64_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 707 #define SYSCTRL_BOD33_PSEL_DIV128 (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 708 #define SYSCTRL_BOD33_PSEL_DIV256 (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 709 #define SYSCTRL_BOD33_PSEL_DIV512 (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 710 #define SYSCTRL_BOD33_PSEL_DIV1K (SYSCTRL_BOD33_PSEL_DIV1K_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 711 #define SYSCTRL_BOD33_PSEL_DIV2K (SYSCTRL_BOD33_PSEL_DIV2K_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 712 #define SYSCTRL_BOD33_PSEL_DIV4K (SYSCTRL_BOD33_PSEL_DIV4K_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 713 #define SYSCTRL_BOD33_PSEL_DIV8K (SYSCTRL_BOD33_PSEL_DIV8K_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 714 #define SYSCTRL_BOD33_PSEL_DIV16K (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 715 #define SYSCTRL_BOD33_PSEL_DIV32K (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 716 #define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
Kojto 111:4336505e4b1c 717 #define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
Kojto 111:4336505e4b1c 718 #define SYSCTRL_BOD33_LEVEL_Msk (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos)
Kojto 111:4336505e4b1c 719 #define SYSCTRL_BOD33_LEVEL(value) ((SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)))
Kojto 111:4336505e4b1c 720 #define SYSCTRL_BOD33_MASK 0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */
Kojto 111:4336505e4b1c 721
Kojto 111:4336505e4b1c 722 /* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
Kojto 111:4336505e4b1c 723 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 724 typedef union {
Kojto 111:4336505e4b1c 725 struct {
Kojto 111:4336505e4b1c 726 uint16_t :6; /*!< bit: 0.. 5 Reserved */
Kojto 111:4336505e4b1c 727 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
Kojto 111:4336505e4b1c 728 uint16_t :6; /*!< bit: 7..12 Reserved */
Kojto 111:4336505e4b1c 729 uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
Kojto 111:4336505e4b1c 730 uint16_t :2; /*!< bit: 14..15 Reserved */
Kojto 111:4336505e4b1c 731 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 732 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 733 } SYSCTRL_VREG_Type;
Kojto 111:4336505e4b1c 734 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 735
Kojto 111:4336505e4b1c 736 #define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */
Kojto 111:4336505e4b1c 737 #define SYSCTRL_VREG_RESETVALUE 0x0000ul /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */
Kojto 111:4336505e4b1c 738
Kojto 111:4336505e4b1c 739 #define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run in Standby */
Kojto 111:4336505e4b1c 740 #define SYSCTRL_VREG_RUNSTDBY (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 741 #define SYSCTRL_VREG_FORCELDO_Pos 13 /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */
Kojto 111:4336505e4b1c 742 #define SYSCTRL_VREG_FORCELDO (0x1ul << SYSCTRL_VREG_FORCELDO_Pos)
Kojto 111:4336505e4b1c 743 #define SYSCTRL_VREG_MASK 0x2040ul /**< \brief (SYSCTRL_VREG) MASK Register */
Kojto 111:4336505e4b1c 744
Kojto 111:4336505e4b1c 745 /* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
Kojto 111:4336505e4b1c 746 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 747 typedef union {
Kojto 111:4336505e4b1c 748 struct {
Kojto 111:4336505e4b1c 749 uint32_t :1; /*!< bit: 0 Reserved */
Kojto 111:4336505e4b1c 750 uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
Kojto 111:4336505e4b1c 751 uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
Kojto 111:4336505e4b1c 752 uint32_t :13; /*!< bit: 3..15 Reserved */
Kojto 111:4336505e4b1c 753 uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
Kojto 111:4336505e4b1c 754 uint32_t :5; /*!< bit: 27..31 Reserved */
Kojto 111:4336505e4b1c 755 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 756 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 757 } SYSCTRL_VREF_Type;
Kojto 111:4336505e4b1c 758 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 759
Kojto 111:4336505e4b1c 760 #define SYSCTRL_VREF_OFFSET 0x40 /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */
Kojto 111:4336505e4b1c 761 #define SYSCTRL_VREF_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */
Kojto 111:4336505e4b1c 762
Kojto 111:4336505e4b1c 763 #define SYSCTRL_VREF_TSEN_Pos 1 /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */
Kojto 111:4336505e4b1c 764 #define SYSCTRL_VREF_TSEN (0x1ul << SYSCTRL_VREF_TSEN_Pos)
Kojto 111:4336505e4b1c 765 #define SYSCTRL_VREF_BGOUTEN_Pos 2 /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */
Kojto 111:4336505e4b1c 766 #define SYSCTRL_VREF_BGOUTEN (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos)
Kojto 111:4336505e4b1c 767 #define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
Kojto 111:4336505e4b1c 768 #define SYSCTRL_VREF_CALIB_Msk (0x7FFul << SYSCTRL_VREF_CALIB_Pos)
Kojto 111:4336505e4b1c 769 #define SYSCTRL_VREF_CALIB(value) ((SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)))
Kojto 111:4336505e4b1c 770 #define SYSCTRL_VREF_MASK 0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */
Kojto 111:4336505e4b1c 771
Kojto 111:4336505e4b1c 772 /* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
Kojto 111:4336505e4b1c 773 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 774 typedef union {
Kojto 111:4336505e4b1c 775 struct {
Kojto 111:4336505e4b1c 776 uint8_t :1; /*!< bit: 0 Reserved */
Kojto 111:4336505e4b1c 777 uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
Kojto 111:4336505e4b1c 778 uint8_t :4; /*!< bit: 2.. 5 Reserved */
Kojto 111:4336505e4b1c 779 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
Kojto 111:4336505e4b1c 780 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
Kojto 111:4336505e4b1c 781 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 782 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 783 } SYSCTRL_DPLLCTRLA_Type;
Kojto 111:4336505e4b1c 784 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 785
Kojto 111:4336505e4b1c 786 #define SYSCTRL_DPLLCTRLA_OFFSET 0x44 /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */
Kojto 111:4336505e4b1c 787 #define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80ul /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */
Kojto 111:4336505e4b1c 788
Kojto 111:4336505e4b1c 789 #define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */
Kojto 111:4336505e4b1c 790 #define SYSCTRL_DPLLCTRLA_ENABLE (0x1ul << SYSCTRL_DPLLCTRLA_ENABLE_Pos)
Kojto 111:4336505e4b1c 791 #define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */
Kojto 111:4336505e4b1c 792 #define SYSCTRL_DPLLCTRLA_RUNSTDBY (0x1ul << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 793 #define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */
Kojto 111:4336505e4b1c 794 #define SYSCTRL_DPLLCTRLA_ONDEMAND (0x1ul << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos)
Kojto 111:4336505e4b1c 795 #define SYSCTRL_DPLLCTRLA_MASK 0xC2ul /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */
Kojto 111:4336505e4b1c 796
Kojto 111:4336505e4b1c 797 /* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
Kojto 111:4336505e4b1c 798 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 799 typedef union {
Kojto 111:4336505e4b1c 800 struct {
Kojto 111:4336505e4b1c 801 uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
Kojto 111:4336505e4b1c 802 uint32_t :4; /*!< bit: 12..15 Reserved */
Kojto 111:4336505e4b1c 803 uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
Kojto 111:4336505e4b1c 804 uint32_t :12; /*!< bit: 20..31 Reserved */
Kojto 111:4336505e4b1c 805 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 806 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 807 } SYSCTRL_DPLLRATIO_Type;
Kojto 111:4336505e4b1c 808 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 809
Kojto 111:4336505e4b1c 810 #define SYSCTRL_DPLLRATIO_OFFSET 0x48 /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */
Kojto 111:4336505e4b1c 811 #define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
Kojto 111:4336505e4b1c 812
Kojto 111:4336505e4b1c 813 #define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
Kojto 111:4336505e4b1c 814 #define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos)
Kojto 111:4336505e4b1c 815 #define SYSCTRL_DPLLRATIO_LDR(value) ((SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos)))
Kojto 111:4336505e4b1c 816 #define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
Kojto 111:4336505e4b1c 817 #define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
Kojto 111:4336505e4b1c 818 #define SYSCTRL_DPLLRATIO_LDRFRAC(value) ((SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)))
Kojto 111:4336505e4b1c 819 #define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
Kojto 111:4336505e4b1c 820
Kojto 111:4336505e4b1c 821 /* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
Kojto 111:4336505e4b1c 822 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 823 typedef union {
Kojto 111:4336505e4b1c 824 struct {
Kojto 111:4336505e4b1c 825 uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
Kojto 111:4336505e4b1c 826 uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
Kojto 111:4336505e4b1c 827 uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
Kojto 111:4336505e4b1c 828 uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
Kojto 111:4336505e4b1c 829 uint32_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 830 uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
Kojto 111:4336505e4b1c 831 uint32_t :1; /*!< bit: 11 Reserved */
Kojto 111:4336505e4b1c 832 uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
Kojto 111:4336505e4b1c 833 uint32_t :3; /*!< bit: 13..15 Reserved */
Kojto 111:4336505e4b1c 834 uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
Kojto 111:4336505e4b1c 835 uint32_t :5; /*!< bit: 27..31 Reserved */
Kojto 111:4336505e4b1c 836 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 837 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 838 } SYSCTRL_DPLLCTRLB_Type;
Kojto 111:4336505e4b1c 839 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 840
Kojto 111:4336505e4b1c 841 #define SYSCTRL_DPLLCTRLB_OFFSET 0x4C /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */
Kojto 111:4336505e4b1c 842 #define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */
Kojto 111:4336505e4b1c 843
Kojto 111:4336505e4b1c 844 #define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
Kojto 111:4336505e4b1c 845 #define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos)
Kojto 111:4336505e4b1c 846 #define SYSCTRL_DPLLCTRLB_FILTER(value) ((SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos)))
Kojto 111:4336505e4b1c 847 #define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
Kojto 111:4336505e4b1c 848 #define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
Kojto 111:4336505e4b1c 849 #define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
Kojto 111:4336505e4b1c 850 #define SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3ul /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */
Kojto 111:4336505e4b1c 851 #define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
Kojto 111:4336505e4b1c 852 #define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
Kojto 111:4336505e4b1c 853 #define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
Kojto 111:4336505e4b1c 854 #define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
Kojto 111:4336505e4b1c 855 #define SYSCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */
Kojto 111:4336505e4b1c 856 #define SYSCTRL_DPLLCTRLB_LPEN (0x1ul << SYSCTRL_DPLLCTRLB_LPEN_Pos)
Kojto 111:4336505e4b1c 857 #define SYSCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */
Kojto 111:4336505e4b1c 858 #define SYSCTRL_DPLLCTRLB_WUF (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos)
Kojto 111:4336505e4b1c 859 #define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
Kojto 111:4336505e4b1c 860 #define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
Kojto 111:4336505e4b1c 861 #define SYSCTRL_DPLLCTRLB_REFCLK(value) ((SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos)))
Kojto 111:4336505e4b1c 862 #define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
Kojto 111:4336505e4b1c 863 #define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
Kojto 111:4336505e4b1c 864 #define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
Kojto 111:4336505e4b1c 865 #define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
Kojto 111:4336505e4b1c 866 #define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
Kojto 111:4336505e4b1c 867 #define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
Kojto 111:4336505e4b1c 868 #define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
Kojto 111:4336505e4b1c 869 #define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos)
Kojto 111:4336505e4b1c 870 #define SYSCTRL_DPLLCTRLB_LTIME(value) ((SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos)))
Kojto 111:4336505e4b1c 871 #define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
Kojto 111:4336505e4b1c 872 #define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
Kojto 111:4336505e4b1c 873 #define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
Kojto 111:4336505e4b1c 874 #define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */
Kojto 111:4336505e4b1c 875 #define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */
Kojto 111:4336505e4b1c 876 #define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
Kojto 111:4336505e4b1c 877 #define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
Kojto 111:4336505e4b1c 878 #define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
Kojto 111:4336505e4b1c 879 #define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
Kojto 111:4336505e4b1c 880 #define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
Kojto 111:4336505e4b1c 881 #define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */
Kojto 111:4336505e4b1c 882 #define SYSCTRL_DPLLCTRLB_LBYPASS (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
Kojto 111:4336505e4b1c 883 #define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
Kojto 111:4336505e4b1c 884 #define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos)
Kojto 111:4336505e4b1c 885 #define SYSCTRL_DPLLCTRLB_DIV(value) ((SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos)))
Kojto 111:4336505e4b1c 886 #define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
Kojto 111:4336505e4b1c 887
Kojto 111:4336505e4b1c 888 /* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
Kojto 111:4336505e4b1c 889 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 890 typedef union {
Kojto 111:4336505e4b1c 891 struct {
Kojto 111:4336505e4b1c 892 uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
Kojto 111:4336505e4b1c 893 uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
Kojto 111:4336505e4b1c 894 uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
Kojto 111:4336505e4b1c 895 uint8_t DIV:1; /*!< bit: 3 Divider Enable */
Kojto 111:4336505e4b1c 896 uint8_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 897 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 898 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 899 } SYSCTRL_DPLLSTATUS_Type;
Kojto 111:4336505e4b1c 900 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 901
Kojto 111:4336505e4b1c 902 #define SYSCTRL_DPLLSTATUS_OFFSET 0x50 /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */
Kojto 111:4336505e4b1c 903 #define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */
Kojto 111:4336505e4b1c 904
Kojto 111:4336505e4b1c 905 #define SYSCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */
Kojto 111:4336505e4b1c 906 #define SYSCTRL_DPLLSTATUS_LOCK (0x1ul << SYSCTRL_DPLLSTATUS_LOCK_Pos)
Kojto 111:4336505e4b1c 907 #define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */
Kojto 111:4336505e4b1c 908 #define SYSCTRL_DPLLSTATUS_CLKRDY (0x1ul << SYSCTRL_DPLLSTATUS_CLKRDY_Pos)
Kojto 111:4336505e4b1c 909 #define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */
Kojto 111:4336505e4b1c 910 #define SYSCTRL_DPLLSTATUS_ENABLE (0x1ul << SYSCTRL_DPLLSTATUS_ENABLE_Pos)
Kojto 111:4336505e4b1c 911 #define SYSCTRL_DPLLSTATUS_DIV_Pos 3 /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */
Kojto 111:4336505e4b1c 912 #define SYSCTRL_DPLLSTATUS_DIV (0x1ul << SYSCTRL_DPLLSTATUS_DIV_Pos)
Kojto 111:4336505e4b1c 913 #define SYSCTRL_DPLLSTATUS_MASK 0x0Ful /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */
Kojto 111:4336505e4b1c 914
Kojto 111:4336505e4b1c 915 /** \brief SYSCTRL hardware registers */
Kojto 111:4336505e4b1c 916 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 917 typedef struct {
Kojto 111:4336505e4b1c 918 __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 919 __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
Kojto 111:4336505e4b1c 920 __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 921 __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
Kojto 111:4336505e4b1c 922 __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
Kojto 111:4336505e4b1c 923 RoReg8 Reserved1[0x2];
Kojto 111:4336505e4b1c 924 __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
Kojto 111:4336505e4b1c 925 RoReg8 Reserved2[0x2];
Kojto 111:4336505e4b1c 926 __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
Kojto 111:4336505e4b1c 927 __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
Kojto 111:4336505e4b1c 928 RoReg8 Reserved3[0x3];
Kojto 111:4336505e4b1c 929 __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
Kojto 111:4336505e4b1c 930 __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
Kojto 111:4336505e4b1c 931 RoReg8 Reserved4[0x2];
Kojto 111:4336505e4b1c 932 __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
Kojto 111:4336505e4b1c 933 __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
Kojto 111:4336505e4b1c 934 __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
Kojto 111:4336505e4b1c 935 RoReg8 Reserved5[0x3];
Kojto 111:4336505e4b1c 936 __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
Kojto 111:4336505e4b1c 937 RoReg8 Reserved6[0x4];
Kojto 111:4336505e4b1c 938 __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
Kojto 111:4336505e4b1c 939 RoReg8 Reserved7[0x2];
Kojto 111:4336505e4b1c 940 __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
Kojto 111:4336505e4b1c 941 __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
Kojto 111:4336505e4b1c 942 RoReg8 Reserved8[0x3];
Kojto 111:4336505e4b1c 943 __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
Kojto 111:4336505e4b1c 944 __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
Kojto 111:4336505e4b1c 945 __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
Kojto 111:4336505e4b1c 946 } Sysctrl;
Kojto 111:4336505e4b1c 947 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 948
Kojto 111:4336505e4b1c 949 /*@}*/
Kojto 111:4336505e4b1c 950
Kojto 111:4336505e4b1c 951 #endif /* _SAMD21_SYSCTRL_COMPONENT_ */